FCC ID: 2AFOSWT1231H-915 RF module

 

WT1231H ISM TRANSCEIVER MODULE V1.3 WT1231H TALGENERAL DESCRIPTION ND The WT1231H is a transceiver module capable of operation over a wide frequency range, including the 315,433,868 and 915MHz license-free ISM (Industry Scientific and Medical) frequency bands. All major RF communication parameters are programmable and most of them can be dynamically set. The WT1231H offers the unique advantage of programmable narrow-band and wide- band communication modes. The WT1231H is optimized for low power consumption while offering high RF output power and channelized operation. Compliance ETSI and FCC regulations. In order to better use WT1231H modules, this specification also involves a large number of the parameters and functions of its core chip WT1231H's,including those IC pins which are not leaded out. All of these can help customers gain a better understanding of the performance of WT1231H modules, and enhance the application skills. KEY PRODUCT FEATURES

+20 dBm - 100 mW Power Output Capability

High Sensitivity: down to -120 dBm at 1.2 kbps

High Selectivity: 16-tap FIR Channel Filter

Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,80 dB Blocking Immunity, no Image Frequency response

Low current: Rx = 16 mA, 100nA register retention

Programmable Pout: -18 to +20 dBm in 1dB steps

Constant RF performance over voltage range of module

FSK Bit rates up to 300 kb/s

Fully integrated synthesizer with a resolution of 61 Hz

FSK, GFSK, MSK, GMSK and OOK modulations

Built-in Bit Synchronizer performing Clock Recovery

115 dB+ Dynamic Range RSSI

Automatic RF Sense with ultra-fast AFC

Packet engine with CRC-16, AES-128, 66-byte FIFO Incoming Sync Word Recognition Built-in temperature sensor APPLICATIONS

Automated Meter Reading

Wireless Sensor Networks

Home and Building Automation

Wireless Alarm and Security Systems

Wireless M-BUS Industrial Monitoring and Control

Module Size:19.7X16mm Page 1 WT1231H Table of Contents 1. General Description ................................................................................................................................................ 8 1.1. Simplified Block Diagram ............................................................................................................................. 8 1.2. Pin and Marking Diagram................................................................................................................................. 9 Page 1.3. Pin Description ....................................................................................................................................10 2. Electrical Characteristics........................................................................................................................................11 2.1. Absolute Maximum Ratings ..................................................................................................................11 2.2. Operating Range............................................................................................................................................ 11 2.3. Module Specification ...........................................................................................................................12 2.3.1. Power Consumption ................................................................................................................................. 12 2.3.2. Frequency Synthesis ................................................................................................................................ 12 2.3.3. Receiver .....................................................................................................................................................13 2.3.4. Transmitter ............................................................................................................................................... 14 2.3.5. Digital Specification ................................................................................................................................. 15 3. Module Description.................................................................................................................................................16 3.1. Power Supply Strategy.............................................................................................................................16 3.2. Frequency Synthesis..................................................................................................................................... 16 3.2.1. Reference Oscillator ................................................................................................................................. 16 3.2.2. CLKOUT Output ....................................................................................................................................... 17 3.2.3. PLL Architecture ....................................................................................................................................... 17 3.2.4. Lock Time ....................................................................................................................................................18 3.2.5. Lock Detect Indicator................................................................................................................................ 18 3.3. Transmitter Description .................................................................................................................................. 19 3.3.1. Architecture Description ........................................................................................................................... 19 3.3.2. Bit Rate Setting ........................................................................................................................................ 19 3.3.3. FSK Modulation ......................................................................................................................................... 20 3.3.4. OOK Modulation ....................................................................................................................................... 20 3.3.5. Modulation Shaping.................................................................................................................................... 21 3.3.6. Power Amplifiers ...................................................................................................................................... 21 3.3.7. High Power Settings ................................................................................................................................. 22 3.3.8. Output Power Summary ............................................................................................................................ 22 3.3.9. Over Current Protection ............................................................................................................................ 22 3.4. Receiver Description ..............................................................................................................................23 3.4.1. Block Diagram .......................................................................................................................................... 23 3.4.2. LNA - Single to Differential Buffer ............................................................................................................ 23 3.4.3. Automatic Gain Control ............................................................................................................................ 24 3.4.4. Continuous-Time DAGC........................................................................................................................... 25 3.4.5. Quadrature Mixer - ADCs - Decimators.................................................................................................... 26 3.4.6. Channel Filter ........................................................................................................................................... 26 3.4.7. DC Cancellation ....................................................................................................................................... 27 Page 2 WT1231H 4.3. 3.4.8. Complex Filter - OOK ............................................................................................................................... 27 3.4.9. RSSI ......................................................................................................................................................... 27 3.4.10. Cordic ..................................................................................................................................................... 28 3.4.11. FSK Demodulator ....................................................................................................................................29 3.4.12. OOK Demodulator .................................................................................................................................. 29 3.4.13. Bit Synchronizer ..................................................................................................................................... 31 3.4.14. Frequency Error Indicator....................................................................................................................... 31 3.4.15. Automatic Frequency Correction ............................................................................................................ 32 3.4.16. Optimized Setup for Low Modulation Index Systems ............................................................................. 33 3.4.17. Temperature Sensor ............................................................................................................................... 34 3.4.18. Timeout Function.................................................................................................................................... 34 4. Operating Modes .................................................................................................................................................... 35 4.1. Basic Modes.................................................................................................................................................. 35 4.2. Automatic Sequencer and Wake-Up Times .................................................................................................. 35 4.2.1. Transmitter Startup Time ..........................................................................................................................36 4.2.2. Tx Start Procedure ................................................................................................................................... 36 4.2.3. Receiver Startup Time.............................................................................................................................. 36 4.2.4. Rx Start Procedure ................................................................................................................................... 38 4.2.5. Optimized Frequency Hopping Sequences .............................................................................................. 38 Listen Mode..................................................................................................................................................... 39 4.3.1. Timings ..................................................................................................................................................... 39 4.3.2. Criteria ...................................................................................................................................................... 40 4.3.3. End of Cycle Actions ................................................................................................................................ 40 4.3.4. Stopping Listen Mode............................................................................................................................... 41 4.3.5. RC Timer Accuracy .................................................................................................................................. 41 4.4. AutoModes ...................................................................................................................................................... 42 5. Data Processing...................................................................................................................................................... 43 5.1. Overview ......................................................................................................................................................... 43 5.1.1. Block Diagram .......................................................................................................................................... 43 5.1.2. Data Operation Modes ............................................................................................................................. 43 5.2. Control Block Description .............................................................................................................................. 44 5.2.1. SPI Interface............................................................................................................................................... 44 5.2.2. FIFO ........................................................................................................................................................... 45 5.2.3. Sync Word Recognition ............................................................................................................................ 46 5.2.4. Packet Handler ......................................................................................................................................... 47 5.2.5. Control ........................................................................................................................................................ 47 5.3. Digital IO Pins Mapping................................................................................................................................. 47 5.3.1. DIO Pins Mapping in Continuous Mode ................................................................................................... 48 5.3.2. DIO Pins Mapping in Packet Mode .......................................................................................................... 48 5.4. Continuous Mode ........................................................................................................................................... 49 5.4.1. General Description................................................................................................................................... 49 5.4.2. Tx Processing............................................................................................................................................ 49 Page 3 WT1231H 5.4.3. Rx Processing .......................................................................................................................................... 50 5.5. Packet Mode .................................................................................................................................................. 50 5.5.1. General Description................................................................................................................................... 50 5.5.2. Packet Format .......................................................................................................................................... 51 5.5.3. Tx Processing (without AES).................................................................................................................... 53 5.5.4. Rx Processing (without AES) ................................................................................................................... 54 5.5.5. AES ........................................................................................................................................................... 54 5.5.6. Handling Large Packets ........................................................................................................................... 56 5.5.7. Packet Filtering.......................................................................................................................................... 56 5.5.8. DC-Free Data Mechanisms ...................................................................................................................... 58 6. Configuration and Status Registers ...................................................................................................................... 60 6.1. General Description ...................................................................................................................................... 60 6.2. Common Configuration Registers ................................................................................................................. 63 6.3. Transmitter Registers ..................................................................................................................................... 66 6.4. Receiver Registers......................................................................................................................................... 67 6.5. IRQ and Pin Mapping Registers.................................................................................................................... 69 6.6. Packet Engine Registers ............................................................................................................................... 71 6.7. Temperature Sensor Registers ..................................................................................................................... 74 6.8. Test Registers ............................................................................................................................................... 74 7. Application Information ......................................................................................................................................... 75 7.1. Crystal Resonator Specification .................................................................................................................... 75 7.2. Reset of the Module ...................................................................................................................................... 75 7.2.1. POR.......................................................................................................................................................... . 75 7.2.2. Manual Reset .............................................................................................................................................. 76 7.3. Reference Design ......................................................................................................................................... 77 8. Packaging Information .......................................................................................................................................... 78 8.1. Package Outline Drawing.............................................................................................................................. 78 9. Ordering Information ............................................................................................................................................. 79 Page 4 WT1231H Page Index of Figures Figure 1. Block Diagram ................................................................................................................................................ 8 Figure 2. Pin Diagram .................................................................................................................................................... 9 Figure 3. Marking Diagram ............................................................................................................................................ 9 Figure 4. TCXO Connection ........................................................................................................................................ 16 Figure 5. Transmitter Block Diagram ........................................................................................................................... 19 Figure 6. Output Power Curves ................................................................................................................................... 22 Figure 7. Receiver Block Diagram ............................................................................................................................... 23 Figure 8. AGC Thresholds Settings ............................................................................................................................. 24 Figure 9. RSSI Dynamic Curve .................................................................................................................................... 28 Figure 10. Cordic Extraction ........................................................................................................................................ 28 Figure 11. OOK Peak Demodulator Description .......................................................................................................... 29 Figure 12. Floor Threshold Optimization ..................................................................................................................... 30 Figure 13. Bit Synchronizer Description ...................................................................................................................... 31 Figure 14. FEI Process ................................................................................................................................................ 32 Figure 15. Optimized AFC (AfcLowBetaOn=1) ............................................................................................................ 33 Figure 16. Temperature Sensor Response ................................................................................................................. 34 Figure 17. Tx Startup, FSK and OOK .......................................................................................................................... 36 Figure 18. Rx Startup - No AGC, no AFC .................................................................................................................... 37 Figure 19. Rx Startup - AGC, no AFC ......................................................................................................................... 37 Figure 20. Rx Startup - AGC and AFC ........................................................................................................................ 37 Figure 21. Listen Mode Sequence (no wanted signal is received) .............................................................................. 39 Figure 22. Listen Mode Sequence (wanted signal is received) ................................................................................... 41 Figure 23. Auto Modes of Packet Handler ................................................................................................................... 42 Figure 24. WT1231H Data Processing Conceptual View ................................................................................................ 43 Figure 25. SPI Timing Diagram (single access) .......................................................................................................... 44 Figure 26. FIFO and Shift Register (SR) ..................................................................................................................... 45 Figure 27. FifoLevel IRQ Source Behavior .................................................................................................................. 46 Figure 28. Sync Word Recognition .............................................................................................................................. 47 Figure 29. Continuous Mode Conceptual View ........................................................................................................... 49 Figure 30. Tx Processing in Continuous Mode ............................................................................................................ 49 Figure 31. Rx Processing in Continuous Mode ........................................................................................................... 50 Figure 32. Packet Mode Conceptual View ................................................................................................................... 51 Figure 33. Fixed Length Packet Format ...................................................................................................................... 52 Figure 34. Variable Length Packet Format .................................................................................................................. 52 Figure 35. Unlimited Length Packet Format ................................................................................................................ 53 Figure 36. CRC Implementation .................................................................................................................................. 58 Figure 37. Manchester Encoding/Decoding ................................................................................................................. 58 Figure 38. Data Whitening ........................................................................................................................................... 59 Figure 39. POR Timing Diagram ................................................................................................................................. 75 Figure 40. Manual Reset Timing Diagram ................................................................................................................... 76 Page 5 WT1231H Figure 41. +20dBm Schematic .................................................................................................................................... 77 Figure 42. Package Outline Drawing ........................................................................................................................... 78 Index of Tables Page Table 1. WT1231H Pinouts .............................................................................................................................................. 10 Table 2. Absolute Maximum Ratings ............................................................................................................................ 11 Table 3. Operating Range ............................................................................................................................................ 11 Table 4. Power Consumption Specification .................................................................................................................. 12 Table 5. Frequency Synthesizer Specification .............................................................................................................. 12 Table 6. Receiver Specification .................................................................................................................................... 13 Table 7. Transmitter Specification ................................................................................................................................ 14 Table 8. Digital Specification ........................................................................................................................................ 15 Table 9. Bit Rate Examples .......................................................................................................................................... 20 Table 10. Power Amplifier Mode Selection Truth Table ............................................................................................... 21 Table 11. High Power Settings ..................................................................................................................................... 22 Table 12. LNA Gain Settings ........................................................................................................................................ 23 Table 13. Receiver Performance Summary .................................................................................................................. 25 Table 14. Available RxBw Settings ............................................................................................................................... 26 Table 15. Available DCC Cutoff Frequencies ............................................................................................................... 27 Table 16. Basic Transceiver Modes ............................................................................................................................. 35 Table 17. Range of Durations in Listen Mode .............................................................................................................. 39 Table 18. Signal Acceptance Criteria in Listen Mode ................................................................................................... 40 Table 19. End of Listen Cycle Actions .......................................................................................................................... 40 Table 20. Status of FIFO when Switching Between Different Modes of the Module ................................................... 46 Table 21. DIO Mapping, Continuous Mode .................................................................................................................. 48 Table 22. DIO Mapping, Packet Mode ......................................................................................................................... 48 Table 23. Registers Summary ...................................................................................................................................... 60 Table 24. Common Configuration Registers ................................................................................................................. 63 Table 25. Transmitter Registers ................................................................................................................................... 66 Table 26. Receiver Registers ....................................................................................................................................... 67 Table 27. IRQ and Pin Mapping Registers ................................................................................................................... 69 Table 28. Packet Engine Registers .............................................................................................................................. 71 Table 29. Temperature Sensor Registers ..................................................................................................................... 74 Table 30. Test Registers .............................................................................................................................................. 74 Table 31. Crystal Specification ..................................................................................................................................... 75 Page 6 Acronyms WT1231H BOM BR BW CCITT Comit Consultatif International Bill Of Materials Bit Rate Bandwidth CRC DAC ETSI FCC Fdev FIFO FIR FS FSK GUI IC ID IF IRQ ITU LFSR LNA LO Tlphonique et Tlgraphique - ITU Cyclic Redundancy Check Digital to Analog Converter European Telecommunications Standards Institute Federal Communications Commission Frequency Deviation First In First Out Finite Impulse Response Frequency Synthesizer Frequency Shift Keying Graphical User Interface Integrated Circuit IDentificator Intermediate Frequency Interrupt ReQuest International Telecommunication Union Linear Feedback Shift Register Low Noise Amplifier Local Oscillator LSB MSB NRZ OOK PA PCB PLL POR RBW RF RSSI Rx SAW SPI SR Stby Tx uC VCO XO XOR Least Significant Bit Most Significant Bit Non Return to Zero On Off Keying Power Amplifier Printed Circuit Board Phase-Locked Loop Power On Reset Resolution BandWidth Radio Frequency Received Signal Strength Indicator Receiver Surface Acoustic Wave Serial Peripheral Interface Shift Register Standby Transmitter Microcontroller Voltage Controlled Oscillator Crystal Oscillator eXclusive OR Page 7 WT1231H This product datasheet contains a detailed description of the WT1231H performance and functionality. 1. General Description The WT1231H is a transceiver module ideally suited for today's high performance ISM band RF applications. It is intended for use as high-performance, low-cost FSK and OOK RF transceiver for robust frequency agile, half-duplex bi-

directional RF links, and where stable and constant RF performance is required over the full operating range of the device down to 1.8V. The WT1231H is intended for applications over a wide frequency range, including the 315MHz,433 MHz,868 MHz and 915MHz ISM bands. Coupled with a link budget in excess of 140 dB, the advanced system features of the WT1231H include a 66 byte TX/RX FIFO, configurable automatic packet handler, listen mode, temperature sensor and configurable DIOs which greatly enhance system flexibility whilst at the same time significantly reducing MCU requirements. The WT1231H complies with both ETSI and FCC regulatory requirements and is available 1.1. Simplified Block Diagram Figure 1. Block Diagram Page 8 1.2. Pin and Marking Diagram The following diagram shows the pin arrangement of the top view. WT1231H Figure 3. Marking Diagram Page 9 WT1231H 1.3. Pin Description Table 1 WT1231H Pinouts Number Name Type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RESET DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 3.3V GND ANA GND SCK MISO MOSI NSS NC I/O I/O I/O I/O I/O I/O I/O

-

-

-

I O I I

-

S Description Reset trigger input Digital I/O, software configured Digital I/O, software configured Digital I/O, software configured Digital I/O, software configured Digital I/O, software configured Digital I/O, software configured Supply voltage Ground RF signal output/input. Ground SPI Clock input SPI Data output SPI Data input SPI Chip select input Connect to GND Page 10 WT1231H 2. Electrical Characteristics 2.1. Absolute Maximum Ratings Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 2 Absolute Maximum Ratings Symbol Description VDDmr Tmr Tj Pmr Supply Voltage Temperature Junction temperature RF Input Level DC_20dBm Duty Cycle of transmission at +20dBm output VSWR_20dBm Maximum VSWR at antenna port 2.2. Operating Range Table 3 Operating Range Symbol Description VDDop Supply voltage(1.8V-2.4V 17dBm, 2.4V- 3.6V 20dBm) Top Clop ML Operational temperature range Load capacitance on digital ports RF Input Level Min

-0.5

-55

-

-

-

-

Min 1.8

-10

-

-

Max 3.9

+115

+125

+6 1 3:1 Max 3.6

+40 25 0 Unit V C C dBm

%

-

Unit V C pF dBm Page 11 WT1231H 2.3 Module Specification The tables below give the electrical specifications of the transceiver under the following conditions: Supply voltage VBAT1=

VBAT2=VDD=3.3 V, temperature = 25 C, FRF = 915 MHz, Pout = +20dBm, 2-level FSK modulation without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kb/s and terminated in a matched 50 Ohm impedance, unless otherwise specified. Note Unless otherwise specified, the performances in the other frequency bands are similar or better. 2.3.1. Power Consumption Table 4 Power Consumption Specification Symbol Description Conditions Min Typ Max Unit IDDSL Supply current in Sleep mode IDDIDLE Supply current in Idle mode RC oscillator enabled IDDST IDDFS IDDR IDDT Supply current in Standby mode Crystal oscillator enabled Supply current in Synthesizer mode Supply current in Receive mode Supply current in Transmit mode with appropriate matching, sta-

ble across VDD range RFOP = +20 dBm, on PA_BOOST RFOP = +17 dBm, on PA_BOOST RFOP = +13 dBm, on RFIO pin RFOP = +10 dBm, on RFIO pin 0 dBm, on RFIO pin RFOP =

RFOP =

-1 dBm, on RFIO pin 2.3.2. Frequency Synthesis Table 5 Frequency Synthesizer Specification Symbol Description FR Synthesizer Frequency Range FXOSC Crystal oscillator frequency TS_OSC Crystal oscillator wake-up time TS_FS TS_HOP Frequency synthesizer wake-up time to PllLock signal Frequency synthesizer hop time at most 10 kHz away from the target Conditions 315MHz Module 433MHz Module 868MHz Module 915MHz Module For All Module From Standby mode 200 kHz step 1 MHz step 5 MHz step 7 MHz step 12 MHz step 20 MHz step 25 MHz step

-

-

-

-

-

-

-

-

-

-

-

Min 290 424 862 890

-

-

-

-

-

-

-

-

-

-

0.1 1.2 1

-

1.25 1.5 9 16 130 95 45 33 20 16

-

-

-

-

-

-

-

-

uA uA mA mA mA mA mA mA mA mA mA Typ 32 250 80 20 20 50 50 80 80 80 Max 340 510 890 1020

-

500 150

-

-

-

-

-

-

-

Unit MHz MHz MHz MHz MHz us us us us us us us us us Page 12 WT1231H FSTEP Frequency synthesizer step FRC BRF BRO FDA RC Oscillator frequency Bit rate, FSK Bit rate, OOK Frequency deviation, FSK FSTEP = FXOSC/219 After calibration Programmable Programmable Programmable FDA + BRF/2 =< 500 kHz

-

-

1.2 1.2 0.6 61.0 62.5

-

-

-

-

-

300 32.768 300 Hz kHz kbps kbps kHz 2.3.3. Receiver All receiver tests are performed with RxBw = 10 kHz (Single Side Bandwidth) as programmed in RegRxBw, receiving a PN15 sequence with a BER of 0.1% (Bit Synchronizer is enabled), unless otherwise specified. The LNA impedance is set to 200 Ohms, by setting bit LnaZin in RegLna to 1. Blocking tests are performed with an unmodulated interferer. The wanted signal power for the Blocking Immunity, ACR, IIP2, IIP3 and AMR tests is set 3 dB above the nominal sensitivity level. Table 6 Receiver Specification Description Conditions Min Typ Max Unit Symbol RFS_F FSK sensitivity, highest LNA gain FDA = 5 kHz, BR = 1.2 kb/s FDA = 5 kHz, BR = 4.8 kb/s FDA = 40 kHz, BR = 38.4 kb/s FDA = 5 kHz, BR = 1.2 kb/s *

RFS_O OOK sensitivity, highest LNA gain BR = 4.8 kb/s CCR ACR BI AMR IIP2 Co-Channel Rejection Adjacent Channel Rejection Blocking Immunity Blocking Immunity Wanted signal at sensitivity

+16dB AM Rejection , AM modulated interferer with 100% modulation depth, fm = 1 kHz, square 2nd order Input Intercept Point Unwanted tones are 20 MHz above the LO Offset = +/- 25 kHz Offset = +/- 50 kHz Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz Lowest LNA gain Highest LNA gain

-

-

-

-

-

-13

-

37

-

-

-

-

-

-

-

-

-

-

-

-118

-114

-105

-120

-112

-10 42 42 66 71 79 62 65 73 66 71 79

+75

+35

-

-

-

-

dBm dBm dBm dBm

-109 dBm

-

-

-

-

-

-

-

-

-

-

-

-

-

-

dB dB dB dB dB dB dB dB dB dB dB dB dBm dBm Page 13 WT1231H IIP3 3rd order Input Intercept point Unwanted tones are 1MHz and 1.995 MHz above the LO Lowest LNA gain Highest LNA gain BW_SSB Single Side channel filter BW Programmable IMR_OOK Image rejection in OOK mode TS_RE Receiver wake-up time, from PLL locked state to RxReady TS_RE_AGC Receiver wake-up time, from PLL locked state, AGC enabled TS_RE_AGC

&AFC Receiver wake-up time, from PLL lock state, AGC and AFC enabled TS_FEI TS_AFC FEI sampling time AFC Response Time TS_RSSI RSSI Response Time Wanted signal level = -106 dBm RxBw = 10 kHz, BR = 4.8 kb/s RxBw = 200 kHz, BR = 100 kb/s RxBw = 10 kHz, BR = 4.8 kb/s RxBw = 200 kHz, BR = 100 kb/s RxBw = 10 kHz, BR = 4.8 kb/s RxBw = 200 kHz, BR = 100 kb/s Receiver is ready Receiver is ready Receiver is ready DR_RSSI RSSI Dynamic Range AGC enabled Min Max

-

-23 2.6 27

-

-

-

-

-

-

-

-

+20

-18

-

30 1.7 96 3.0 163 4.8 265 4.Tbit 4.Tbit 2.Tbit

-115 0

-

-

dBm dBm 500 kHz

-

-

-

-

-

-

-

-

dB ms us ms us ms us

-

-

-

dBm dBm

*

Set SensitivityBoost in RegTestLna to 0x2D to reduce the noise floor in the receiver 2.3.4. Transmitter Table 7 Transmitter Specification Symbol Description Conditions Min RF_OP RF output power in 50 ohms On RFIO pin Programmable with 1dB steps Max Min RF_OPH Max RF output power, on PA_BOOST pin RF_OP RF output power stability Transmitter Phase Noise PHN ACP Transmitter adjacent channel power (measured at 25 kHz off-

set) With external match to 50 ohms From VDD=2.4V to 3.6V 50 kHz Offset from carrier 868 / 915 MHz bands 434 / 315 MHz bands BT=0.5 . Measurement conditions as defined by EN 300 220-1 V2.1.1 TS_TR Transmitter wake up time, to the first rising edge of DCLK Frequency Synthesizer enabled, PaRamp = 10 us, BR = 4.8 kb/s.

-

-

-

-

-

-

-

-

Typ

+20

-18

+20

+/-0.3

-95

-99

-

Max Unit

-

-

-

-

-

-

-37 dBm dBm dBm dB dBc/

Hz dBm 120

-

us Page 14 2.3.5. Digital Specification Conditions: Temp = 25C, VDD = 3.3V, unless otherwise specified. Table 8 Digital Specification Symbol Description Conditions VIH VIL VOH VOL FSCK tch tcl trise tfall tsetup thold tnsetup tnhold tnhigh Digital input level high Digital input level low Digital output level high Digital output level low Imax = 1 mA Imax = -1 mA SCK frequency SCK high time SCK low time SCK rise time SCK fall time MOSI setup time MOSI hold time NSS setup time NSS hold time NSS high time between SPI accesses from MOSI change to SCK rising edge from SCK rising edge to MOSI change from NSS falling edge to SCK rising edge from SCK falling edge to NSS rising edge, normal mode T_DATA DATA hold and setup time WT1231H Min 0.8

-

0.9

-

-

50 50

-

-

30 60 30 30 20 250 Typ Max Unit

-

-

-

-

-

-

-

5 5

-

-

-

-

-

-

-

0.2

-

0.1 10 VDD VDD VDD VDD MHz

-

-

-

-

-

-

-

-

-

-

ns ns ns ns ns ns ns ns ns ns Page 15 WT1231H 3. Module Description This section describes in depth the architecture of the WT1231H low-power, highly integrated transceiver. 3.1. Power Supply Strategy The WT1231H employs an advanced power supply scheme, which provides stable operating characteristics over the full temperature and voltage range of operation. This includes the full output power of +20dBm maintained from 2.4 to 3.6V. The WT1231H can be powered from any low-noise voltage source via pins VBAT1 and VBAT2. Decoupling capacitors should be connected, as suggested in the reference design, on VR_PA, VR_DIG and VR_ANA pins to ensure a correct operation of the built-in voltage regulators. 3.2. Frequency Synthesis The LO generation on the WT1231H is based on a state-of-the-art fractional-N PLL. The PLL is fully integrated with automatic calibration. 3.2.1. Reference Oscillator The crystal oscillator is the main timing reference of the WT1231H. It is used as a reference for the frequency synthesizer and as a clock for the digital processing. The XO startup time, TS_OSC, depends on the actual XTAL being connected on pins XTA and XTB. When using the built-

in sequencer, the WT1231H optimizes the startup time and automatically triggers the PLL when the XO signal is stable. To manually control the startup time, the user should either wait for TS_OSC max, or monitor the signal CLKOUT which will only be made available on the output buffer when a stable XO oscillation is achieved. An external clock can be used to replace the crystal oscillator, for instance a tight tolerance TCXO. To do so, bit 4 at address 0x59 should be set to 1, and the external clock has to be provided on XTA. XTB should be left open. The peak-

peak amplitude of the input signal must never exceed 2.4 V. Please consult your TCXO supplier for an appropriate value of decoupling capacitor, CD. XTA XTB NC TCXO 32 MHz OP Vcc GND Vcc CD Figure 4. TCXO Connection Page 16 WT1231H 3.2.2. CLKOUT Output The reference frequency, or a fraction of it, can be provided on DIO5 by modifying bits ClkOut in RegDioMapping2. Two typical applications of the CLKOUT output include:

To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be made available in any operation mode except Sleep mode and is automatically enabled at power on reset.

To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software trimming of the initial crystal tolerance. Note to minimize the current consumption of the WT1231H, please ensure that the CLKOUT signal is disabled when not required. 3.2.3. PLL Architecture The frequency synthesizer generating the LO frequency for both the receiver and the transmitter is a fractional-N sigma-

delta PLL. The PLL incorporates a third order loop capable of fast auto-calibration, and it has a fast switching-time. The VCO and the loop filter are both fully integrated, removing the need for an external tight-tolerance, high-Q inductor in the VCO tank circuit. 3.2.3.1. VCO The VCO runs at 2, 4 or 6 times the RF frequency (respectively in the 915, 434 and 315 MHz bands) to reduce any LO leakage in receiver mode, to improve the quadrature precision of the receiver, and to reduce the pulling effects on the VCO during transmission. The VCO calibration is fully automated. A coarse adjustment is carried out at power on reset, and a fine tuning is performed each time the WT1231H PLL is activated. Automatic calibration times are fully transparent to the end-user, as their processing time is included in the TS_TE and TS_RE specifications. 3.2.3.2. PLL Bandwidth The bandwidth of the WT1231H Fractional-N PLL is wide enough to allow for:

High speed FSK modulation, up to 300 kb/s, inside the PLL bandwidth

Very fast PLL lock times, enabling both short startup and fast hop times required for frequency agile applications 3.2.3.3. Carrier Frequency and Resolution The WT1231H PLL embeds a 19-bit sigma-delta modulator and its frequency resolution, constant over the whole frequency range, and is given by:

F STE P

=

F XOSC

----------------

219 The carrier frequency is programmed through RegFrf, split across addresses 0x07 to 0x09:

FRF = FSTEP Frf(23,0) Note The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the least significant byte FrfLsb in RegFrfLsb is written. This allows for more complex modulation schemes such as m-

ary FSK, where frequency modulation is achieved by changing the programmed RF frequency. Page 17 WT1231H 3.2.4. Lock Time PLL lock time TS_FS is a function of a number of technical factors, such as synthesized frequency, frequency step, etc. When using the built-in sequencer, the WT1231H optimizes the startup time and automatically starts the receiver or the transmitter when the PLL has locked. To manually control the startup time, the user should either wait for TS_FS max given in the specification, or monitor the signal PLL lock detect indicator, which is set when the PLL has is within its locking range. When performing an AFC, which usually corrects very small frequency errors, the PLL response time is approximately:

= -------------

In a frequency hopping scheme, the timings TS_HOP given in the table of specifications give an order of magnitude for the expected lock times. 3.2.5. Lock Detect Indicator A lock indication signal can be made available on some of the DIO pins, and is toggled high when the PLL reaches its locking range. Please refer to Table 21 and Table 22 to map this interrupt to the desired pins. Note The lock detect block may indicate an unlock condition (signal toggling low) when the transmitter is FSK modulated with large frequency deviation settings. Page 18 3.3. Transmitter Description The transmitter of WT1231H comprises the frequency synthesizer, modulator and power amplifier blocks. 3.3.1. Architecture Description WT1231H RFIO PA_BOOST LNA PA0 PA1 PA2 Receiver Chain Local Oscillator Figure 5. Transmitter Block Diagram 3.3.2. Bit Rate Setting When using the WT1231H in Continuous mode, the data stream to be transmitted can be input directly to the modulator via pin DIO2/DATA in an asynchronous manner, unless Gaussian filtering is used, in which case the DCLK signal on pin DIO1/DCLK is used to synchronize the data stream. See section 3.3.5 for details on the Gaussian filter. In Packet mode or in Continuous mode with Gaussian filtering enabled (refer to section 5.5 for details), the Bit Rate (BR) is controlled by bits BitRate in RegBitrate:

Amongst others, the following Bit Rates are accessible:

BR

=

F XOSC

-------------------

BitRate Page 19 Table 9 Bit Rate Examples Type BitRate

(15:8) BitRate

(7:0) Classical modem baud rates

(multiples of 1.2 kbps) Classical modem baud rates

(multiples of 0.9 kbps) Round bit rates

(multiples of 12.5, 25 and 50 kbps) Watch Xtal frequency 0x68 0x34 0x1A 0x0D 0x06 0x03 0x01 0x00 0x02 0x01 0x0A 0x05 0x02 0x01 0x00 0x00 0x00 0x00 0x03 0x2B 0x15 0x0B 0x05 0x83 0x41 0xA1 0xD0 0x2C 0x16 0x00 0x00 0x80 0x40 0xD5 0xA0 0x80 0x6B 0xD1 OOK 1.2 kbps 2.4 kbps 4.8 kbps 9.6 kbps 19.2 kbps 12.5 kbps 25 kbps

(G)FSK

(G)MSK 1.2 kbps 2.4 kbps 4.8 kbps 9.6 kbps 19.2 kbps 38.4 kbps 76.8 kbps 153.6 kbps 57.6 kbps 115.2 kbps 12.5 kbps 25 kbps 50 kbps 100 kbps 150 kbps 200 kbps 250 kbps 300 kbps 32.768 kbps 32.768 kbps WT1231H Actual BR

(b/s) 1200.015 2400.060 4799.760 9600.960 19196.16 38415.36 76738.60 153846.1 57553.95 115107.9 12500.00 25000.00 50000.00 100000.0 150234.7 200000.0 250000.0 299065.4 32753.32 3.3.3. FSK Modulation FSK modulation is performed inside the PLL bandwidth, by changing the fractional divider ratio in the feedback loop of the PLL. The large resolution of the sigma-delta modulator, allows for very narrow frequency deviation. The frequency deviation FDEV is given by:

Note no constraint applies to the modulation index of the transmitter, but the frequency deviation must exceed 600 Hz. 3.3.4. OOK Modulation OOK modulation is applied by switching on and off the Power Amplifier. Digital control and smoothing are available to improve the transient power response of the OOK transmitter. Page 20 3.3.5. Modulation Shaping Modulation shaping can be applied in both OOK and FSK modulation modes, to improve the narrowband response of the transmitter. Both shaping features are controlled with PaRamp bits in RegPaRamp. WT1231H

In FSK mode, a Gaussian filter with BT = 0.3, 0.5 or 1 is used to filter the modulation stream, at the input of the sigma-delta modulator. If the Gaussian filter is enabled when the WT1231H is in Continuous mode, DCLK signal on pin DIO1/DCLK will trigger an interrupt on the uC each time a new bit has to be transmitted. Please refer to section 5.4.2 for details.

When OOK modulation is used, the PA bias voltages are ramped up and down smoothly when the PA is turned on and off, to reduce spectral splatter. Note the transmitter must be restarted if the PaRamp setting is changed, in order to recalibrate the built-in filter. 3.3.6. Power Amplifiers

A higher power mode, when PA1 and PA2 are combined, providing up to +20 dBm to a matched load. When PA1 and PA2 are combined to deliver +20 dBm to the antenna, a specific impedance matching / harmonic filtering design is required to ensure impedance transformation and regulatory compliance. All PA settings are controlled by RegPaLevel, and the truth table of settings is given in Table 10. Table 10 Power Amplifier Mode Selection Truth Table Pa0On Pa1On Pa2On Mode Power Range Pout Formula 1 0 0 0 0 1 1 1 0 0 1 1 PA0 output on pin RFIO

-18 to +13 dBm

-18 dBm + OutputPower PA1 enabled on pin PA_BOOST

-2 to +13 dBm

-18 dBm + OutputPower PA1 and PA2 combined on pin PA_BOOST

+2 to +17 dBm

-14 dBm + OutputPower PA1+PA2 on PA_BOOST with high output power +20dBm settings (see 3.3.7)

+5 to +20 dBm

-11 dBm + OutputPower Other combinations Reserved Notes - To ensure correct operation at the highest power levels, please make sure to adjust the Over Current Protection Limit accordingly in RegOcp, except above +18dBm where it must be disabled

- If PA_BOOST pin is not used (+20dBm applications and less), the pin can be left floating. Page 21 WT1231H 3.3.7. High Power Settings The WT1231H has a high power +20 dBm capability on PA_BOOST pin, with the following settings: Table 11 High Power Settings Register Address Value for High Power Value for Rx or PA0 use Description RegOcp RegTestPa1 RegTestPa2 0x13 0x5A 0x5C 0x0F 0x5D 0x7C 0x1x 0x55 0x70 OCP control High power PA control High power PA control Note High Power settings MUST be turned off when using PA0, and in Receive mode The Duty Cycle of transmission at +20dBm is limited to 1%, with a maximum VSWR of 3:1 at antenna port, over the standard operating range [-40;+85C]. 3.3.8. Output Power Summary The curves below summarize the possible PA options on the WT1231H:

P o ut vs. P ro g ram med P o w er

]

m B d

[

t u o P 22 18 14 10 6 2

-2

-6

-10

-14

-18

-22 Pout on PA0 [dB m ]

Pout on PA1 [dB m ]

Pout on PA1+PA2 [dBm]

P out on P A 1+ P A 2 with 20dB m s ettings [dB m ]

-18

-14

-10

-6

-2 2 6 10 14 18 Pr o g r am m e d Po w e r [d Bm ]

Figure 6. Output Power Curves 3.3.9. Over Current Protection An over current protection block is built-in the module. It helps preventing surge currents required when the transmitter is used at its highest power levels, thus protecting the battery that may power the application. The current clamping value is controlled by OcpTrim bits in RegOcp, and is calculated with the following formula:

Imax = 45 + 5 OcpTrim mA Note Imax sets a limit on the current drain of the Power Amplifier only, hence the maximum current drain of the WT1231H is equal to Imax + IFS Page 22 WT1231H 3.4. Receiver Description The WT1231H features a digital receiver with the analog to digital conversion process being performed directly following the LNA-Mixers block. The zero-IF receiver is able to handle (G)FSK and (G)MSK modulation. ASK and OOK modulation filtering, demodulation, gain control, synchronization and packet handling is performed digitally, which allows a very wide range of bit rates and frequency deviations to be selected. The receiver is also capable of automatic gain calibration in order to improve precision on RSSI measurements. is, however, demodulated by a low-IF architecture. All the 3.4.1. Block Diagram Rx Cal ibration Reference LNA RFIO From PA1 Single to Differential Mi x ers

/

Modulators Channel Fil ter DC Cancel lation Complex Fi lter r o t a m i c e D Local Os c illator By pass ed in FSK AFC AGC Figure 7. Receiver Block Diagram CORDIC Phase Output FSK Demodulator Module Output RSSI OOK Demodul ator i g n s s e c o r P The following sections give a brief description of each of the receiver blocks. 3.4.2. LNA - Single to Differential Buffer The LNA uses a common-gate topology, which allows for a flat characteristic over the whole frequency range. It is designed to have an input impedance of 50 Ohms or 200 Ohms (as selected with bit LnaZin in RegLna), and the parasitic capacitance at the LNA input port is cancelled with the external RF choke. A single to differential buffer is implemented to improve the second order linearity of the receiver. The LNA gain, including the single-to-differential buffer, is programmable over a 48 dB dynamic range, and control is either manual or automatic with the embedded AGC function. Note In the specific case where the LNA gain is manually set by the user, the receiver will not be able to properly handle FSK signals with a modulation index smaller than 2 at an input power greater than the 1dB compression point, tabulated in section 3.4.3. Table 12 LNA Gain Settings LnaGainSelect LNA Gain Gain Setting 000 001 010 011 100 101 110 111 Any of the below, set by the AGC loop Max gain Max gain - 6 dB Max gain - 12 dB Max gain - 24 dB Max gain - 36 dB Max gain - 48 dB Reserved

-

G1 G2 G3 G4 G5 G6

-

Page 23 WT1231H 3.4.3. Automatic Gain Control By default (LnaGainSelect = 000), the LNA gain is controlled by a digital AGC loop in order to obtain the optimal sensitivity/

linearity trade-off. Regardless of the data transfer mode (Packet or Continuous), the following series of events takes place when the receiver is enabled:

The receiver stays in WAIT mode, until RssiValue exceeds RssiThreshold for two consecutive samples. Its power consumption is the receiver power consumption.

When this condition is satisfied, the receiver automatically selects the most suitable LNA gain, optimizing the sensitivity/linearity trade-off.

The programmed LNA gain, read-accessible with LnaCurrentGain in RegLna, is carried on for the whole duration of the packet, until one of the following conditions is fulfilled:

Packet mode: if AutoRxRestartOn = 0, the LNA gain will remain the same for the reception of the following packet. If AutoRxRestartOn = 1, after the controller has emptied the FIFO the receiver will re-enter the WAIT mode described above, after a delay of InterPacketRxDelay, allowing for the distant transmitter to ramp down, hence avoiding a false RSSI detection. In both cases (AutoRxRestartOn=0 or AutoRxRestartOn=1), the receiver can also re-enter the WAIT mode by setting RestartRx bit to 1. The user can decide to do so, to manually launch a new AGC procedure.

Continuous mode: upon reception of valid data, the user can decide to either leave the receiver enabled with the same LNA gain, or to restart the procedure, by setting RestartRx bit to 1, resuming the WAIT mode of the receiver, described above. Notes - the AGC procedure must be performed while receiving preamble in FSK mode

- in OOK mode, the AGC will give better results if performed while receiving a constant 1 sequence The following figure illustrates the AGC behavior:

Towards

-125 dBm 16dB 7dB 11dB 9dB 11dB Pin [dBm]

G1 G2 G3 G4 G5 G6 Higher Sensitivity Lower Linearity Lower Noise Figure Lower Sensitivity Higher Linearity Higher Noise Figure Figure 8. AGC Thresholds Settings The following table summarizes the performance (typical figures) of the complete receiver:

Page 24 WT1231H Table 13 Receiver Performance Summary Input Power Pin Gain Setting Pin < AgcThresh1 AgcThresh1 < Pin < AgcThresh2 AgcThresh2 < Pin < AgcThresh3 AgcThresh3 < Pin < AgcThresh4 AgcThresh4 < Pin < AgcThresh5 AgcThresh5 < Pin G1 G2 G3 G4 G5 G6 P-1dB

[dBm]

-37

-31

-26

-14

>-6

>0 Receiver Performance (typ) NF

[dB]

IIP3

[dBm]

7 13 18 27 36 44

-18

-15

-8

-1

+13

+20 IIP2

[dBm]

+35

+40

+48

+62

+68

+75 3.4.3.1. RssiThreshold Setting For correct operation of the AGC, RssiThreshold in RegRssiThresh must be set to the sensitivity of the receiver. The receiver will remain in WAIT mode until RssiThreshold is exceeded. Note When AFC is enabled and performed automatically at the receiver startup, the channel filter used by the receiver during the AFC and the AGC is RxBwAfc instead of the standard RxBw setting. This may impact the sensitivity of the receiver, and the setting of RssiThreshold accordingly 3.4.3.2. AGC Reference The AGC reference level is automatically computed in the WT1231H, according to: AGC Reference [dBm] = -174 + NF + DemodSnr +10.log(2*RxBw) + FadingMargin [dBm]

With:

NF = 7dB

DemodSnr = 8 dB

RxBw

FadingMargin = 5 dB : Fading margin

: LNAs Noise Figure at maximum gain

: SNR needed by the demodulator

: Single sideband channel filter bandwidth 3.4.4. Continuous-Time DAGC In addition to the automatic gain control described in section 3.4.3, the WT1231H is capable of continuously adjusting its gain in the digital domain, after the analog to digital conversion has occured. This feature, named DAGC, is fully transparent to the end user. The digital gain adjustment is repeated every 2 bits, and has the following benefits:

Fully transparent to the end user

Works in Continuous, Packet, and unlimited length Packet modes Improves the fading margin of the receiver during the reception of a packet, even if the gain of the LNA is frozen Improves the receiver robustness in fast fading signal conditions, by quickly adjusting the receiver gain (every 2 bits) The DAGC is enabled by setting RegTestDagc to 0x20 for low modulation index systems (i.e. when AfcLowBetaOn=1, refer to section 3.4.16), and 0x30 for other systems. It is recommended to always enable the DAGC. Page 25 WT1231H 3.4.5. Quadrature Mixer - ADCs - Decimators The mixer is inserted between output of the RF buffer stage and the input of the analog to digital converter (ADC) of the receiver section. This block is designed to translate the spectrum of the input RF signal to base-band, and offer both high IIP2 and IIP3 responses. In the lower bands of operation (290 to 510 MHz), the multi-phase mixing architecture with weighted phases improves the rejection of the LO harmonics in receiver mode, hence increasing the receiver immunity to out-of-band interferers. The I and Q digitalization is made by two 5th order continuous-time Sigma-Delta Analog to Digital Converters (ADC). Their gain is not constant over temperature, but the whole receiver is calibrated before reception, so that this inaccuracy has no impact on the RSSI precision. The ADC output is one bit per channel. It needs to be decimated and filtered afterwards. This ADC can also be used for temperature measurement, please refer to section 3.4.17 for more details. The decimators decrease the sample rate of the incoming signal in order to optimize the area and power consumption of the following receiver blocks. 3.4.6. Channel Filter The role of the channel filter is to filter out the noise and interferers outside of the channel. Channel filtering on the WT1231H is implemented with a 16-tap Finite Impulse Response (FIR) filter, providing an outstanding Adjacent Channel Rejection performance, even for narrowband applications. Note to respect oversampling rules in the decimation chain of the receiver, the Bit Rate cannot be set at a higher value than 2 times the single-side receiver bandwidth (BitRate < 2 x RxBw) The single-side channel filter bandwidth RxBw is controlled by the parameters RxBwMant and RxBwExp in RegRxBw:

When FSK modulation is enabled:

When OOK modulation is enabled:

RxBw = ------------------------F----X----O----S----C-------------------------

RxBwMant 2RxBwE x p + 2 RxBw = ------------------------F----X----O----S----C-------------------------

RxBwMant 2RxBwE x p + 3 The following channel filter bandwidths are accessible (oscillator is mandated at 32 MHz):

Table 14 Available RxBw Settings RxBwMant

(binary/value) RxBwExp

(decimal) RxBw (kHz) FSK ModulationType=00 OOK ModulationType=01 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 7 7 7 6 6 6 5 5 5 4 2.6 3.1 3.9 5.2 6.3 7.8 10.4 12.5 15.6 20.8 1.3 1.6 2.0 2.6 3.1 3.9 5.2 6.3 7.8 10.4 Page 26 WT1231H 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 4 4 3 3 3 2 2 2 1 1 1 0 0 0 25.0 31.3 41.7 50.0 62.5 83.3 100.0 125.0 166.7 200.0 250.0 333.3 400.0 500.0 12.5 15.6 20.8 25.0 31.3 41.7 50.0 62.5 83.3 100.0 125.0 166.7 200.0 250.0 3.4.7. DC Cancellation DC cancellation is required in zero-IF architecture transceivers to remove any DC offset generated through self-

reception. It is built-in the WT1231H and its adjustable cutoff frequency fc is controlled in RegRxBw:

Table 15 Available DCC Cutoff Frequencies DccFreq in RegRxBw 000 001 010 (default) 011 100 101 110 111 fc in

% of RxBw 16 8 4 2 1 0.5 0.25 0.125 The default value of DccFreq cutoff frequency is typically 4% of the RxBw (channel filter BW). The cutoff frequency of the DCC can however be increased to slightly improve the sensitivity, under wider modulation conditions. It is advised to adjust the DCC setting while monitoring the receiver sensitivity. 3.4.8. Complex Filter - OOK In OOK mode the WT1231H is modified to a low-IF architecture. The IF frequency is automatically set to half the single side bandwidth of the channel filter (FIF = 0.5 x RxBw). The Local Oscillator is automatically offset by the IF in the OOK receiver. A complex filter is implemented on the module to attenuate the resulting image frequency by typically 30 dB. Note this filter is automatically bypassed when receiving FSK signals (ModulationType = 00 in RegDataModul). 3.4.9. RSSI The RSSI block evaluates the amount of energy available within the receiver channel bandwidth. Its resolution is 0.5 dB, and it has a wide dynamic range to accommodate both small and large signal levels that may be present. Its acquisition time is very short, taking only 2 bit periods. The RSSI sampling must occur during the reception of preamble in FSK, and constant 1 reception in OOK. Page 27 WT1231H Note

- RssiValue can only be read when it exceeds RssiThreshold

- The receiver is capable of automatic gain calibration, in order to improve the precision of its RSSI measurements. This function injects a known RF signal at the LNA input, and calibrates the receiver gain accordingly. This calibration is automatically performed during the PLL start-up, making it a transparent process to the end-user

- RSSI accuracy depends on all components located between the antenna port and pin RFIO, and is therefore limited to a few dB. Board-level calibration is advised to further improve accuracy RSSI Chart - With AGC

]

m B d

[

e u l a V i s s R 0.0

-20.0

-40.0

-60.0

-80.0

-100.0

-120.0

-120 -110 -100

-90

-80

-70

-60

-50

-40

-30

-20

-10 0 Pin [dBm]

Figure 9. RSSI Dynamic Curve 3.4.10. Cordic The Cordic task is to extract the phase and the amplitude of the modulation vector (I+j.Q). This information, still in the digital domain is used:

Phase output: used by the FSK demodulator and the AFC blocks.

Amplitude output: used by the RSSI block, for FSK demodulation, AGC and automatic gain calibration purposes. Real-time Magnitude Q(t) Real-time Phase I(t) Figure 10. Cordic Extraction Page 28 WT1231H 3.4.11. FSK Demodulator The FSK demodulator of the WT1231H is designed to demodulate FSK, GFSK, MSK and GMSK modulated signals. It is most efficient when the modulation index of the signal is greater than 0.5 and below 10:

0.5 The output of the FSK demodulator can be fed to the Bit Synchronizer (described in section 3.4.13), to provide the companion processor with a synchronous data stream in Continuous mode. 3.4.12. OOK Demodulator The OOK demodulator performs a comparison of the RSSI output and a threshold value. Three different threshold modes are available, configured through bits OokThreshType in RegOokPeak. The recommended mode of operation is the "Peak" threshold mode, illustrated in Figure 11:

RSSI

[dBm]

Peak -6dB Threshold Floor threshold defined by OokFixedThresh Noise floor of receiver Time Zoom Decay in dB as defined in OokPeakThreshStep Fixed 6dB difference Period as defined in OokPeakThreshDec Figure 11. OOK Peak Demodulator Description In peak threshold mode the comparison threshold level is the peak value of the RSSI, reduced by 6dB. In the absence of an input signal, or during the reception of a logical "0", the acquired peak value is decremented by one OokPeakThreshStep every OokPeakThreshDec period. When the RSSI output is null for a long time (for instance after a long string of "0" received, or if no transmitter is present), the peak threshold level will continue falling until it reaches the "Floor Threshold", programmed in OokFixedThresh. The default settings of the OOK demodulator lead to the performance stated in the electrical specification. However, in applications in which sudden signal drops are awaited during a reception, the three parameters should be optimized accordingly. Page 29 WT1231H 3.4.12.1. Optimizing the Floor Threshold OokFixedThresh determines the sensitivity of the OOK receiver, as it sets the comparison threshold for weak input signals

(i.e. those close to the noise floor). Significant sensitivity improvements can be generated if configured correctly. Note that the noise floor of the receiver at the demodulator input depends on:

The noise figure of the receiver.

The gain of the receive chain from antenna to base band.

The matching - including SAW filter if any.

The bandwidth of the channel filters. It is therefore important to note that the setting of OokFixedThresh will be application dependant. The following procedure is recommended to optimize OokFixedThresh. Increment OokFixedThresh Set WT1231H in OOK Rx mode Adjust Bit Rate, Channel filter BW Default OokFixedThresh setting No input signal Continuous Mode Monitor DIO2/DATA pin Glitch activity on DATA ?

Optimization complete Figure 12. Floor Threshold Optimization The new floor threshold value found during this test should be used for OOK reception with those receiver settings. 3.4.12.2. Optimizing OOK Demodulator for Fast Fading Signals A sudden drop in signal strength can cause the bit error rate to increase. For applications where the expected signal drop can be estimated, the following OOK demodulator parameters OokPeakThreshStep and OokPeakThreshDec can be optimized as described below for a given number of threshold decrements per bit. Refer to RegOokPeak to access those settings. 3.4.12.3. Alternative OOK Demodulator Threshold Modes In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold detectors:

Fixed Threshold: The value is selected through OokFixedThresh

Average Threshold: Data supplied by the RSSI block is averaged, and this operation mode should only be used with DC-free encoded data. Page 30 WT1231H 3.4.13. Bit Synchronizer The Bit Synchronizer is a block that provides a clean and synchronized digital output, free of glitches. Its output is made available on pin DIO1/DCLK in Continuous mode and can be disabled through register settings. However, for optimum receiver performance its use when running Continuous mode is strongly advised. The Bit Synchronizer is automatically activated in Packet mode. Its bit rate is controlled by BitRateMsb and BitRateLsb in RegBitrate. Raw demodulator output

(FSK or OOK) BitSync Output To pin DATA and DCLK in continuous mode DATA DCLK Figure 13. Bit Synchronizer Description To ensure correct operation of the Bit Synchronizer, the following conditions have to be satisfied:

A preamble (0x55 or 0xAA) of 12 bits is required for synchronization (from the RxReady interrupt)

The subsequent payload bit stream must have at least one transition form '0' to '1' or '1' to '0 every 16 bits during data transmission

The bit rate matching between the transmitter and the receiver must be better than 6.5 %. Notes - If the Bit Rates of transmitter and receiver are known to be the same, the WT1231H will be able to receive an infinite unbalanced sequence (all 0s or all 1s) with no restriction.

- If there is a difference in Bit Rate between Tx and Rx, the amount of adjacent bits at the same level that the BitSync can withstand can be estimated as follows:

- This implies approximately 6 consecutive unbalanced bytes when the Bit Rate precision is 1%, which is easily achievable (crystal tolerance is in the range of 50 to 100 ppm). 3.4.14. Frequency Error Indicator This function provides information about the frequency error of the local oscillator (LO) compared with the carrier frequency of a modulated signal at the input of the receiver. When the FEI block is launched, the frequency error is measured and the Page 31 WT1231H signed result is loaded in FeiValue in RegFei, in 2s complement format. The time required for an FEI evaluation is 4 times the bit period. To ensure a proper behavior of the FEI:

The operation must be done during the reception of preamble

The sum of the frequency offset and the 20 dB signal bandwidth must be lower than the base band filter bandwidth The 20 dB bandwidth of the signal can be evaluated as follows (double-side bandwidth):

=

The frequency error, in Hz, can be calculated with the following formula:

SX1WT1231H in Rx mode Preamble-

modulated input s ignal Signal level > Sensitivity Set FeiStart

= 1 FeiDone

= 1 No Yes Read FeiValue Figure 14. FEI Process 3.4.15. Automatic Frequency Correction The AFC is based on the FEI block, and therefore the same input signal and receiver setting conditions apply. When the AFC procedure is done, AfcValue is directly subtracted to the register that defines the frequency of operation of the module, FRF. The AFC can be launched:

Each time the receiver is enabled, if AfcAutoOn = 1

Upon user request, by setting bit AfcStart in RegAfcFei, if AfcAutoOn = 0 Page 32 WT1231H When the AFC is automatically triggered (AfcAutoOn = 1), the user has the option to:

Clear the former AFC correction value, if AfcAutoClearOn = 1

Start the AFC evaluation from the previously corrected frequency. This may be useful in systems in which the LO keeps on drifting in the same direction. Ageing compensation is a good example. The WT1231H offers an alternate receiver bandwidth setting during the AFC phase, to accommodate large LO drifts. If the user considers that the received signal may be out of the receiver bandwidth, a higher channel filter bandwidth can be programmed in RegAfcBw, at the expense of the receiver noise floor, which will impact upon sensitivity. 3.4.16. Optimized Setup for Low Modulation Index Systems

For wide band systems, where AFC is usually not required (XTAL inaccuracies do not typically impact the sensitivity), it is recommended to offset the LO frequency of the receiver to avoid desensitization. This can be simply done by modifying Frf in RegFrfLsb. A good rule of thumb is to offset the receivers LO by 10% of the expected transmitter frequency deviation.

For narrow band systems, it is recommended to perform AFC. The WT1231H has a dedicated AFC, enabled when AfcLowBetaOn in RegAfcCtrl is set to 1. A frequency offset, programmable through LowBetaAfcOffset in RegTestAfc, is added and is calculated as follows:

Offset = LowBetaAfcOffset x 488 Hz The user should ensure that the programmed offset exceeds the DC cancellers cutoff frequency, set through DccFreqAfc in RegAfcBw. RX TX FeiValue RX TX FeiValue f f Standard AFC AfcLowBetaOn = 0 RX & TX AfcValue f TX RX Optimized AFC AfcLowBetaOn = 1 AfcValue LowBetaAfcOffset f Before AFC After AFC Figure 15. Optimized AFC (AfcLowBetaOn=1) As shown on Figure 15, a standard AFC sequence uses the result of the FEI to correct the LO frequency and align both local oscillators. When the optimized AFC is enabled (AfcLowBetaOn=1), the receivers LO is corrected by FeiValue +

LowBetaAfcOffset. When the optimized AFC routine is enabled, the receiver startup time can be computed as follows (refer to section 4.2.3):

TS_RE_AGC&AFC (optimized AFC) = Tana + 4.Tcf + 4.Tdcc + 3.Trssi + 2.Tafc + 2.Tpllafc Page 33 WT1231H 3.4.17. Temperature Sensor When temperature is measured, the receiver ADC is used to digitize the sensor response. Most receiver blocks are disabled, and temperature measurement can only be triggered in Standby or Frequency Synthesizer modes. The response of the temperature sensor is -1C / Lsb. A CMOS temperature sensor is not accurate by nature, therefore it should be calibrated at ambient temperature for precise temperature readings. TempValue

-1C/Lsb TempValue(t) TempValue(t)-1 Returns 150d (typ.) Needs calibration

-40C t t+1 Ambient

+85C Figure 16. Temperature Sensor Response It takes less than 100 microseconds for the WT1231H to evaluate the temperature (from setting TempMeasStart to 1 to TempMeasRunning reset). 3.4.18. Timeout Function The WT1231H includes a Timeout function, which allows it to automatically shut-down the receiver after a receive sequence and therefore save energy.

Timeout interrupt is generated TimeoutRxStart x 16x Tbit after switching to RX mode if RssiThreshold flag does not raise within this time frame

Timeout interrupt is generated TimeoutRssiThresh x 16 x Tbit after RssiThreshold flag has been raised. This timeout interrupt can be used to warn the companion processor to shut down the receiver and return to a lower power mode. Page 34 WT1231H 4. Operating Modes 4.1. Basic Modes The circuit can be set in 5 different basic modes which are described in Table 16. By default, when switching from a mode to another one, the sub-blocks are woken up according to a pre-defined and optimized sequence. Alternatively, these operating modes can be selected directly by disabling the automatic sequencer

(SequencerOff in RegOpMode = 1). Table 16 Basic Transceiver Modes ListenOn in RegOpMode Mode in RegOpMode Selected mode Enabled blocks 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 x Sleep Mode Stand-by Mode FS Mode Transmit Mode Receive Mode Listen Mode None Top regulator and crystal oscillator Frequency synthesizer Frequency synthesizer and transmitter Frequency synthesizer and receiver See Listen Mode, section 4.3 4.2. Automatic Sequencer and Wake-Up Times By default, when switching from one operating mode to another, the circuit takes care of the sequence of events in such a way that the transition timing is optimized. For example, when switching from Sleep mode to Transmit mode, the WT1231H goes first to Standby mode (XO started), then to frequency synthesizer mode, and finally, when the PLL has locked, to transmit mode. Entering transmit mode is also made according to a predefined sequence starting with the wake-up of the PA regulator before applying a ramp-up on the PA and generating the DCLK clock.

The crystal oscillator wake-up time, TS_OSC, is directly related to the time for the crystal oscillator to reach its steady state. It depends notably on the crystal characteristics.

The frequency synthesizer wake-up time, TS_FS, is directly related to the time needed by the PLL to reach its steady state. The signal PLL_LOCK, provided on an external pin, gives an indication of the lock status. It goes high when the PLL reaches its locking range. Four specific cases can be highlighted:

Transmitter Wake Up time from Sleep mode

Receiver Wake Up time from Sleep mode

Receiver Wake Up time from Sleep mode, AGC enabled

Receiver Wake Up time from Sleep mode, AGC and AFC enabled

= TS_OSC + TS_FS + TS_TR

= TS_OSC + TS_FS + TS_RE

= TS_OSC + TS_FS + TS_RE_AGC

= TS_OSC + TS_FS + TS_RE_AGC&AFC These timings are detailed in sections 4.2.1 and 4.2.3. In applications where the target average power consumption, or the target startup time, do not require setting the WT1231H in the lowest power modes (Sleep or Standby), the respective timings TS_OSC and TS_FS in the former equations can be omitted. Page 35 4.2.1. Transmitter Startup Time The transmitter wake-up time, TS_TR, is given by the sequence controlled by the digital part. It is a pure digital delay which depends on the bit rate and the ramp-up time. In FSK mode, this time can be derived from the following equation. WT1231H where PaRamp is the ramp-up time programmed in RegPaRamp and Tbit is the bit time. In OOK mode, this equation can be simplified to the following:

, Tx startup request

(sequencer or user) TS_TR XO Started and PLL is locked Analog group delay 0.5 x Tbit 5 us ModeReady TxReady 1.25 x PaRamp

(only in FSK mode) Transmission of Packet Figure 17. Tx Startup, FSK and OOK 4.2.2. Tx Start Procedure As described in the former section, ModeReady and TxReady interrupts warn the uC that the transmitter is ready to transmit data

In Continuous mode, the preamble bits preceding the payload can be applied on the DIO2/DATA pin immediately after any of these interrupts have fired. The DCLK signal, activated on pin DIO1/DCLK can also be used to start toggling the DATA pin, as described on Figure 30.

In Packet mode, the WT1231H will automatically modulate the RF signal with preamble bytes as soon as TxReady or ModeReady happen. The actual packet transmission (starting with the number of preambles specified in PreambleSize) will start when the TxStartCondition is fulfilled. 4.2.3. Receiver Startup Time It is highly recommended to use the built-in sequencer of the WT1231H, to optimize the delays when setting the module in receive mode. It guarantees the shortest startup times, hence the lowest possible energy usage, for battery operated systems. The startup times of the receiver can be calculated from the following:

Page 36 WT1231H Rx startup request

(sequencer or user) TS_RE XO Started and PLL is locked Analog FEs group delay Channel Filters group delay DC Cutoffs group delay RSSI sampling RSSI sampling Reception of Packet Tana Tcf Tdcc Trssi Trssi ModeReady RxReady Figure 18. Rx Startup - No AGC, no AFC Received Packet Preamble may start Rx startup request

(sequencer or user) TS_RE_AGC The LNA gain is adjusted by the AGC, according to the RSSI result XO Started and PLL is locked Analog FEs group delay Channel Filters group delay DC Cutoffs group delay RSSI sampling RSSI sampling Channel Filters group delay DC Cutoffs group delay RSSI sampling Reception of Packet Tana Tcf Tdcc Trssi Trssi Tcf Tdcc Trssi ModeReady RxReady Rx startup request

(sequencer or user) Received Packet Preamble may start Figure 19. Rx Startup - AGC, no AFC TS_RE_AGC&AFC The LNA gain is adjusted by the AGC, according to the RSSI result Carrier Frequency is adjusted by the AFC XO Started and PLL is locked Analog FEs group delay Channel Filters group delay DC Cutoffs group delay RSSI sampling RSSI sampling Channel Filters group delay DC Cutoffs group delay RSSI sampling AFC PLL lock Channel Filters group delay DC Cutoffs group delay Reception of Packet Tana Tcf Tdcc Trssi Trssi Tcf Tdcc Trssi Tafc Tpllafc Tcf Tdcc ModeReady RxReady Received Packet Preamble may start Figure 20. Rx Startup - AGC and AFC The different timings shown above are as follows:

Group delay of the analog front end:

Channel filters group delay in FSK mode:

Channel filters group delay in OOK mode:

DC Cutoffs group delay:

PLL lock time after AFC adjustment:

AFC sample time:

RSSI sample time:

Tana = 20 us Tcf = 21 / (4.RxBw) Tcf = 34 / (4.RxBw) Tdcc = max(8 , 2^(round(log2(8.RxBw.Tbit)+1)) / (4.RxBw) Tpllafc = 5 / PLLBW (PLLBW = 300 kHz) Tafc = 4 x Tbit Trssi = 2 x int(4.RxBw.Tbit)/(4.RxBw)

(aka TS_RSSI)

(also denoted TS_AFC in the general specification) Note The above timings represent maximum settling times, and shorter settling times may be observed in real cases Page 37 WT1231H 4.2.4. Rx Start Procedure As described in the former sections, the RxReady interrupt warns the uC that the receiver is ready.

In Continuous mode with Bit Synchronizer, the receiver will start locking its Bit Synchronizer on a minimum or 12 bits of received preamble (see section 3.4.13 for details), before the reception of correct Data, or Sync Word (if enabled) can occur.

In Continuous mode without Bit Synchronizer, valid data will be available on DIO2/DATA right after the RxReady interrupt.

In Packet mode, the receiver will start locking its Bit Synchronizer on a minimum or 12 bits of received preamble (see section 3.4.13 for details), before the reception of correct Data, or Sync Word (if enabled) can occur. 4.2.5. Optimized Frequency Hopping Sequences In a frequency hopping-like application, it is required to turn off the transmitter when hopping from one channel to another, to avoid spectral splatter and obtain the best spectral purity.

Transmitter hop from Ch A to Ch B: it is advised to step through the Rx mode:

(0) WT1231H is in Tx mode in Ch A

(1) Program the WT1231H in Rx mode

(2) Change the carrier frequency in the RegFrf registers

(3) Turn the transceiver back to Tx mode

(4) Respect the Tx start procedure, described in section 4.2.2

Receiver hop from Ch A to Ch B:

(0) WT1231H is in Rx mode in Ch A

(1) Change the carrier frequency in the RegFrf registers

(2) Program the WT1231H in FS mode

(3) Turn the transceiver back to Rx mode

(4) Respect the Rx start procedure, described in section 4.2.4 Note all sequences described above are assuming that the sequencer is turned on (SequencerOff=0 in RegOpMode). Page 38 WT1231H 4.3. Listen Mode The circuit can be set to Listen mode, by setting ListenOn in RegOpMode to 1 while in Standby mode. In this mode, WT1231H spends most of the time in Idle mode, during which only the RC oscillator runs. Periodically the receiver is woken up and listens for an RF signal. If a wanted signal is detected, the receiver is kept on and the data is demodulated. Otherwise, if a wanted signal hasn't been detected after a pre-defined period of time, the receiver is disabled until the next time period. This periodical Rx wake-up requirement is very common in low power applications. On WT1231H it is handled locally by the Listen mode block without using uC resources or energy. The simplified timing diagram of this procedure is illustrated in Figure 21. tListenIdle Rx Idle Rx time tListenRx tListenRx Figure 21. Listen Mode Sequence (no wanted signal is received) 4.3.1. Timings The duration of the Idle phase is given by tListenIdle. The time during which the receiver is on and waits for a signal is given by tListenRx. tListenRx includes the wake-up time of the receiver, described in section 4.2.3. This duration can be programmed in the configuration registers via the serial interface. Both time periods tListenRx and tListenIdle (denoted tListenX in the following text) are fixed by two parameters from the configuration register and are calculated as follows:

tListenX = ListenCoefX Listen Re solX where ListenResolX is the Rx or Idle resolution and is independently programmable on three values (64us, 4.1ms or 262ms), whereas ListenCoefX is an integer between 1 and 255. All parameters are located in RegListen registers. The timing ranges are tabulated in Table 17 below. Table 17 Range of Durations in Listen Mode ListenResolX 01 10 11 Min duration

( ListenCoef = 1 ) 64 us 4.1 ms 0.26 s Max duration

( ListenCoef = 255 ) 16 ms 1.04 s 67 s Page 39 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET Notes - the accuracy of the typical timings given in Table 17 will depend in the RC oscillator calibration

- RC oscillator calibration is required, and must be performed at power up. See section 4.3.5 for details 4.3.2. Criteria The criteria taken for detecting a wanted signal and hence deciding to maintain the receiver on is defined by ListenCriteria in RegListen1. Table 18 Signal Acceptance Criteria in Listen Mode ListenCriteria 0 1 Input Signal Power

>= RssiThreshold Required Required SyncAddressMatch Not Required Required 4.3.3. End of Cycle Actions The action taken after detection of a packet, is defined by ListenEnd in RegListen3, as described in the table below. Table 19 End of Listen Cycle Actions ListenEnd 00 01 10 Description Module stays in Rx mode. Listen mode stops and must be disabled. Module stays in Rx mode until PayloadReady or Timeout interrupt occurs. It then goes to the mode defined by Mode. Listen mode stops and must be disabled. Module stays in Rx mode until PayloadReady or Timeout interrupt occurs. Listen mode then resumes in Idle state. FIFO content is lost at next Rx wakeup. Page 40 ADVANCED COMMUNICATIONS & SENSING Upon detection of a valid packet, the sequencing is altered, as shown below:

WT1231H DATASHEET PayloadReady ListenCriteria passed ListenEnd = 00 Listen Mode ListenEnd = 01 Listen Mode ListenEnd = 10 Listen Mode Idle Idle Idle Rx Rx Rx Mode Idle Rx Figure 22. Listen Mode Sequence (wanted signal is received) 4.3.4. Stopping Listen Mode To abort Listen mode operation, the following procedure must be respected:

Program RegOpMode with ListenOn=0, ListenAbort=1, and the desired setting for the Mode bits (Sleep, Stdby, FS, Rx or Tx mode) in a single SPI access

Program RegOpMode with ListenOn=0, ListenAbort=0, and the desired setting for the Mode bits (Sleep, Stdby, FS, Rx or Tx mode) in a second SPI access 4.3.5. RC Timer Accuracy All timings of the Listen Mode rely on the accuracy of the internal low-power RC oscillator. This oscillator is automatically calibrated at the device power-up, and it is a user-transparent process. For applications enduring large temperature variations, and for which the power supply is never removed, RC calibration can be performed upon user request. RcCalStart in RegOsc1 can be used to trigger this calibration, and the flag RcCalDone will be set automatically when the calibration is over. Page 41 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET 4.4. AutoModes Automatic modes of packet handler can be enabled by configuring the related parameters in RegAutoModes. The intermediate mode of the module is called IntermediateMode and the enter and exit conditions to/from this intermediate mode can be configured through the parameters EnterCondition & ExitCondition. The enter and exit conditions cannot be used independently of each other i.e. both should be enabled at the same time. The initial and the final state is the one configured in Mode in RegOpMode. The initial & final states can be different by configuring the modes register while the module is in intermediate mode. The pictorial description of the auto modes is shown below. Intermediate State defined by IntermediateMode EnterCondition ExitCondition Initial state defined By Mode in RegOpMode Final state defined By Mode in RegOpMode Figure 23. Auto Modes of Packet Handler Some typical examples of AutoModes usage are described below:

Automatic transmission (AutoTx) : Mode = Sleep, IntermediateMode = Tx, EnterCondition = FifoLevel, ExitCondition =

PacketSent

Automatic reception (AutoRx) : Mode = Rx, IntermediateMode = Sleep, EnterCondition = CrcOk, ExitCondition = falling edge of FifoNotEmpty

Automatic reception of acknowledge (AutoRxAck): Mode = Tx, IntermediateMode = Rx, EnterCondition = PacketSent, ExitCondition = CrcOk

...

Page 42 WT1231H 5. Data Processing 5.1. Overview 5.1.1. Block Diagram Figure below illustrates the WT1231H data processing circuit. Its role is to interface the data to/from the modulator/ demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers. The circuit contains several control blocks which are described in the following paragraphs. Tx/Rx CONTROL Data Rx SYNC RECOG. Tx PACKET HANDLER FIFO

(+SR) SPI DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 NSS SCK MOSI MISO Potential datapaths (data operation mode dependant) Figure 24. WT1231H Data Processing Conceptual View The WT1231H implements several data operation modes, each with their own data path through the data processing section. Depending on the data operation mode selected, some control blocks are active whilst others remain disabled. 5.1.2. Data Operation Modes The WT1231H has two different data operation modes selectable by the user:

Continuous mode: each bit transmitted or received is accessed in real time at the DIO2/DATA pin. This mode may be

Packet mode (recommended): user only provides/retrieves payload bytes to/from the FIFO. The packet is automatically used if adequate external signal processing is available. built with preamble, Sync word, and optional AES, CRC, and DC-free encoding schemes The reverse operation is performed in reception. The uC processing overhead is hence significantly reduced compared to Continuous mode. Depending on the optional features activated (CRC, AES, etc) the maximum payload length is limited to FIFO size, 255 bytes or unlimited. Each of these data operation modes is described fully in the following sections. Page 43 WT1231H 5.2. Control Block Description 5.2.1. SPI Interface The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to CPOL

= 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented. Three access modes to the registers are provided:

SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received for the read access. The NSS pin goes low at the begin of the frame and goes high after the data byte.

BURST access: the address byte is followed by several data bytes. The address is automatically incremented internally between each data byte. This mode is available for both read and write accesses. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the last byte transfer.

FIFO access: if the address byte corresponds to the address of the FIFO, then succeeding data byte will address the FIFO. The address is not automatically incremented but is memorized and does not need to be sent between each data byte. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the last byte transfer. Figure below shows a typical SPI single access to a register. Figure 25. SPI Timing Diagram (single access) MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the rising edge of SCK. MISO is generated by the slave on the falling edge of SCK. A transfer always starts by the NSS pin going low. MISO is high impedance when NSS is high. The first byte is the address byte. It is made of:

wnr bit, which is 1 for write access and 0 for read access

7 bits of address, MSB first The second byte is a data byte, either sent on MOSI by the master in case of a write access, or received by the master on MISO in case of read access. The data byte is transmitted MSB first. Proceeding bytes may be sent on MOSI (for write access) or received on MISO (for read access) without rising NSS and re-sending the address. In FIFO mode, if the address was the FIFO address then the bytes will be written / read at the FIFO address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented at each new byte received. Page 44 WT1231H The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is actually a special case of FIFO / BURST mode with only 1 data byte transferred. During the write access, the byte transferred from the slave to the master on the MISO line is the value of the written register before the write operation. 5.2.2. FIFO 5.2.2.1. Overview and Shift Register (SR) In packet mode of operation, both data to be transmitted and that has been received are stored in a configurable FIFO

(First In First Out) device. It is accessed via the SPI interface and provides several interrupts for transfer management. The FIFO is 1 byte wide hence it only performs byte (parallel) operations, whereas the demodulator functions serially. A shift register is therefore employed to interface the two devices. In transmit mode it takes bytes from the FIFO and outputs them serially (MSB first) at the programmed bit rate to the modulator. Similarly, in Rx the shift register gets bit by bit data from the demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below. byte1 byte0 8 SR (8bits) FIFO LSB Data Tx/Rx 1 MSB Figure 26. FIFO and Shift Register (SR) Note When switching to Sleep mode, the FIFO can only be used once the ModeReady flag is set (quasi immediate from all modes except from Tx) 5.2.2.2. Size The FIFO size is fixed to 66 bytes. 5.2.2.3. Interrupt Sources and Flags

FifoNotEmpty: FifoNotEmpty interrupt source is low when byte 0, i.e. whole FIFO, is empty. Otherwise it is high. Note that when retrieving data from the FIFO, FifoNotEmpty is updated on NSS falling edge, i.e. when FifoNotEmpty is updated to low state the currently started read operation must be completed. In other words, FifoNotEmpty state must be checked after each read operation for a decision on the next one (FifoNotEmpty = 1: more byte(s) to read;

FifoNotEmpty = 0: no more byte to read).

FifoFull: FifoFull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.

FifoOverrunFlag: FifoOverrunFlag is set when a new byte is written by the user (in Tx or Standby modes) or the SR

(inRx mode) while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1, note that the FIFO will also be cleared.

PacketSent: PacketSent interrupt source goes high when the SR's last bit has been sent.

FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below. Page 45 WT1231H FifoLevel 1 0 B B+1

# of bytes in FIFO Figure 27. FifoLevel IRQ Source Behavior Note

- FifoLevel interrupt is updated only after a read or write operation on the FIFO. Thus the interrupt cannot be dynamically updated by only changing the FifoThreshold parameter

- FifoLevel interrupt is valid as long as FifoFull does not occur. An empty FIFO will restore its normal operation 5.2.2.4. FIFO Clearing Table below summarizes the status of the FIFO when switching between different modes Table 20 Status of FIFO when Switching Between Different Modes of the Module Comments From Stdby Sleep To Sleep Stdby Stdby/Sleep Stdby/Sleep Rx Rx Tx Tx Rx Tx Stdby/Sleep Any FIFO status Not cleared Not cleared Not cleared Cleared Cleared Not cleared Cleared To allow the user to write the FIFO in Stdby/Sleep before Tx To allow the user to read FIFO in Stdby/Sleep mode after Rx 5.2.3. Sync Word Recognition 5.2.3.1. Overview Sync word recognition (also called Pattern recognition) is activated by setting SyncOn in RegSyncConfig. The bit synchronizer must also be activated in continuous mode (automatically done in Packet mode) . The block behaves like a shift register; it continuously compares the incoming data with its internally programmed Sync word and sets SyncAddressMatch when a match is detected. This is illustrated in Figure 28 below. Page 46 WT1231H Rx DATA

(NRZ) Bit N-x =

Sync_value[x]

Bit N-1 =

Sync_value[1]

Bit N =

Sync_value[0]

DCLK SyncAddressMatch Figure 28. Sync Word Recognition During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of RegSyncValue1 and the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync word. When the programmed Sync word is detected the user can assume that this incoming packet is for the node and can be processed accordingly. SyncAddressMatch is cleared when leaving Rx or FIFO is emptied. 5.2.3.2. Configuration

Size: Sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via SyncSize in RegSyncConfig. In Packet mode this field is also used for Sync word generation in Tx mode.

Error tolerance: The number of errors tolerated in the Sync word recognition can be set from 0 to 7 bits to via

Value: The Sync word value is configured in SyncValue(63:0). In Packet mode this field is also used for Sync word SyncTol. generation in Tx mode. Note SyncValue choices containing 0x00 bytes are not allowed 5.2.4. Packet Handler The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5. 5.2.5. Control The control block configures and controls the full module's behavior according to the settings programmed in the configuration registers. 5.3. Digital IO Pins Mapping Six general purpose IO pins are available on the WT1231H, and their configuration in Continuous or Packet mode is controlled through RegDioMapping1 and RegDioMapping2. Page 47 ADVANCED COMMUNICATIONS & SENSING 5.3.1. DIO Pins Mapping in Continuous Mode Table 21 DIO Mapping, Continuous Mode WT1231H DATASHEET Diox Mapping DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 Mode Sleep Stdby FS Rx Tx Mode Sleep Stdby FS Rx Tx 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11

-

-

-

ModeReady ClkOut ModeReady ClkOut ModeReady ClkOut Rssi ModeReady ClkOut ClkOut SyncAddress PllLock Timeout RxReady PllLock TxReady TxReady ModeReady PllLock

-

-

-

-

-

-

-

-

-

-

-

-

-

-

ModeReady ClkOut ModeReady ClkOut

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

AutoMode AutoMode AutoMode Rssi RxReady AutoMode Timeout TxReady TxReady AutoMode TxReady FifoFull

-

-

-

FifoFull

-

-

-

FifoFull PllLock FifoFull Rssi

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Data Data Data Data Data Data Data Data

-

-

-

ModeReady

-

-

-

ModeReady PllLock PllLock Dclk RxReady ModeReady SyncAddress Timeout Rssi SyncAddress ModeReady Dclk TxReady PllLock TxReady PllLock ModeReady

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

FifoNotEmpty AutoMode FifoNotEmpty AutoMode FifoNotEmpty AutoMode FifoNotEmpty Data AutoMode FifoNotEmpty Data

-

-

-

-

-

-

-

-

FifoLevel FifoFull FifoNotEmpty FifoLevel FifoFull FifoNotEmpty FifoLevel FifoFull FifoNotEmpty PllLock FifoLevel FifoFull FifoNotEmpty Timeout FifoLevel FifoFull FifoNotEmpty PllLock ModeReady ClkOut Data

-

ClkOut Data ModeReady PllLock Timeout Rssi RxReady PllLock ModeReady TxReady SyncAddress PllLock FifoFull TxReady ModeReady PllLock PllLock AutoMode PllLock CrcOk PayloadReady SyncAddress Rssi PacketSent TxReady PllLock 5.3.2. DIO Pins Mapping in Packet Mode Table 22 DIO Mapping, Packet Mode Diox Mapping DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 Note Received Data is only shown on the Data signal between RxReady and PayloadReadys rising edges Page 48 ADVANCED COMMUNICATIONS & SENSING 5.4. Continuous Mode WT1231H DATASHEET 5.4.1. General Description As illustrated in Figure 29, in Continuous mode the NRZ data to (from) the (de)modulator is directly accessed by the uC on the bidirectional DIO2/DATA pin. The FIFO and packet handler are thus inactive. Tx/Rx CONTROL Data Rx SYNC RECOG. DIO0 DIO1/DCLK DIO2/DATA DIO3 DIO4 DIO5 SPI NSS SCK MOSI MISO Figure 29. Continuous Mode Conceptual View 5.4.2. Tx Processing In Tx mode, a synchronous data clock for an external uC is provided on DIO1/DCLK pin. Clock timing with respect to the data is illustrated in Figure 30. DATA is internally sampled on the rising edge of DCLK so the uC can change logic state anytime outside the grayed out setup/hold zone. T_DATA T_DATA DATA

(NRZ) DCLK Note the use of DCLK is required when the modulation shaping is enabled (see section 3.3.5). Figure 30. Tx Processing in Continuous Mode Page 49 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET 5.4.3. Rx Processing If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK signal is provided. Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on DIO2/DATA and DIO1/DCLK pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as illustrated below. DATA (NRZ) DCLK Figure 31. Rx Processing in Continuous Mode Note in Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal even if the DCLK signal is not used by the uC (bit synchronizer is automatically enabled in Packet mode). 5.5. Packet Mode 5.5.1. General Description In Packet mode the NRZ data to (from) the (de)modulator is not directly accessed by the uC but stored in the FIFO and accessed via the SPI interface. In addition, the WT1231H packet handler performs several packet oriented tasks such as Preamble and Sync word generation, CRC calculation/check, whitening/dewhitening of data, Manchester encoding/decoding, address filtering, AES encryption/decryption, etc. This simplifies software and reduces uC overhead by performing these repetitive tasks within the RF module itself. Another important feature is ability to fill and empty the FIFO in Sleep/Stdby mode, ensuring optimum power consumption and adding more flexibility for the software. Page 50 DVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET CONTROL Data Rx SYNC RECOG. Tx PACKET HANDLER FIFO

(+SR) SPI DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 NSS SCK MOSI MISO Note The Bit Synchronizer is automatically enabled in Packet mode. Figure 32. Packet Mode Conceptual View 5.5.2. Packet Format 5.5.2.1. Fixed Length Packet Format Fixed length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to any value greater than 0. In applications where the packet length is fixed in advance, this mode of operation may be of interest to minimize RF overhead (no length byte field is required). All nodes, whether Tx only, Rx only, or Tx/Rx should be programmed with the same packet length value. The length of the payload is limited to 255 bytes if AES is not enabled else the message is limited to 64 bytes (i.e. max 65 bytes payload if Address byte is enabled). The length programmed in PayloadLength relates only to the payload which includes the message and the optional address byte. In this mode, the payload must contain at least one byte, i.e. address or message byte. An illustration of a fixed length packet is shown below. It contains the following fields:

Preamble (1010...)

Sync word (Network ID)

Optional Address byte (Node ID)

Message data

Optional 2-bytes CRC checksum Page 51 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET DC free Data encoding CRC checksum calculation AES Enc/Dec Preamble 0 to 65535 bytes Sync Word 0 to 8 bytes Address byte Message Up to 255 bytes CRC 2-bytes Payload

(min 1 byte) Fields added by the packet handler in Tx and processed and removed in Rx Optional User provided fields which are part of the payload Message part of the payload Figure 33. Fixed Length Packet Format 5.5.2.2. Variable Length Packet Format Variable length packet format is selected when bit PacketFormat is set to 1. This mode is useful in applications where the length of the packet is not known in advance and can vary over time. It is then necessary for the transmitter to send the length information together with each packet in order for the receiver to operate properly. In this mode the length of the payload, indicated by the length byte, is given by the first byte of the FIFO and is limited to 255 bytes if AES is not enabled else the message is limited to 64 bytes (i.e. max 66 bytes payload if Address byte is enabled). Note that the length byte itself is not included in its calculation. In this mode, the payload must contain at least 2 bytes, i.e. length + address or message byte. An illustration of a variable length packet is shown below. It contains the following fields:

Preamble (1010...)

Sync word (Network ID)

Length byte

Optional Address byte (Node ID)

Message data

Optional 2-bytes CRC checksum DC free Data encoding CRC checksum calculation AES Enc/Dec Preamble 0 to 65535 bytes Sync Word 0 to 8 bytes Length byte Address byte Message Up to 255 bytes CRC 2-bytes Payload

(min 2 bytes) Fields added by the packet handler in Tx and processed and removed in Rx Optional User provided fields which are part of the payload Message part of the payload Figure 34. Variable Length Packet Format Page 52 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET 5.5.2.3. Unlimited Length Packet Format Unlimited length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to 0. The user can then transmit and receive packet of arbitrary length and PayloadLength register is not used in Tx/Rx modes for counting the length of the bytes transmitted/received. This mode is a replacement for the legacy buffered mode in RF63/RF64 transceivers. In Tx the data is transmitted depending on the TxStartCondition bit. On the Rx side the data processing features like Address filtering, Manchester encoding and data whitening are not available if the sync pattern length is set to zero

(SyncOn = 0). The filling of the FIFO in this case can be controlled by the bit FifoFillCondition. The CRC detection in Rx is also not supported in this mode of the packet handler, however CRC generation in Tx is operational. The interrupts like CrcOk & PayloadReady are not available either. An unlimited length packet shown in is made up of the following fields:

Preamble (1010...).

Sync word (Network ID).

Optional Address byte (Node ID).

Message data

Optional 2-bytes CRC checksum (Tx only) DC free Data encoding Preamble 0 to 65535 bytes Sync Word 0 to 8 bytes Address byte Message unlimited length Payload Fields added by the packet handler in Tx and processed and removed in Rx Message part of the payload Optional User provided fields which are part of the payload Figure 35. Unlimited Length Packet Format 5.5.3. Tx Processing (without AES) In Tx mode the packet handler dynamically builds the packet by performing the following operations on the payload available in the FIFO:

Optionally calculating CRC over complete payload field (optional length byte + optional address byte + message) Add a programmable number of preamble bytes Add a programmable Sync word andappending the 2 bytes checksum.

Optional DC-free encoding of the data (Manchester or whitening) Only the payload (including optional address and length fields) is required to be provided by the user in the FIFO. Page 53 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET The transmission of packet data is initiated by the Packet Handler only if the module is in Tx mode and the transmission condition defined by TxStartCondition is fulfilled. If transmission condition is not fulfilled then the packet handler transmits a preamble sequence until the condition is met. This happens only if the preamble length /= 0, otherwise it transmits a zero or one until the condition is met to transmit the packet data. The transmission condition itself is defined as:

if TxStartCondition = 1, the packet handler waits until the first byte is written into the FIFO, then it starts sending the preamble followed by the sync word and user payload If TxStartCondition = 0, the packet handler waits until the number of bytes written in the FIFO is equal to the number defined in RegFifoThresh + 1 If the condition for transmission was already fulfilled i.e. the FIFO was filled in Sleep/Stdby then the transmission of packet starts immediately on enabling Tx

5.5.4. Rx Processing (without AES) In Rx mode the packet handler extracts the user payload to the FIFO by performing the following operations:

Receiving the preamble and stripping it off

Detecting the Sync word and stripping it off

Optional DC-free decoding of data

Optionally checking the address byte

Optionally checking CRC and reflecting the result on CrcOk. Only the payload (including optional address and length fields) is made available in the FIFO. When the Rx mode is enabled the demodulator receives the preamble followed by the detection of sync word. If fixed length packet format is enabled then the number of bytes received as the payload is given by the PayloadLength parameter. In variable length mode the first byte received after the sync word is interpreted as the length of the received packet. The internal length counter is initialized to this received length. The PayloadLength register is set to a value which is greater than the maximum expected length of the received packet. If the received length is greater than the maximum length stored in PayloadLength register the packet is discarded otherwise the complete packet is received. If the address check is enabled then the second byte received in case of variable length and first byte in case of fixed length is the address byte. If the address matches to the one in the NodeAddress field, reception of the data continues otherwise it's stopped. The CRC check is performed if CrcOn = 1 and the result is available in CrcOk indicating that the CRC was successful. An interrupt (PayloadReady) is also generated on DIO0 as soon as the payload is available in the FIFO. The payload available in the FIFO can also be read in Sleep/Standby mode. If the CRC fails the PayloadReady interrupt is not generated and the FIFO is cleared. This function can be overridden by setting CrcAutoClearOff = 1, forcing the availability of PayloadReady interrupt and the payload in the FIFO even if the CRC fails. 5.5.5. AES AES is the symmetric-key block cipher that provides the cryptographic capabilities to the transceiver. The system proposed can work with 128-bit long fixed keys. The fixed key is stored in a 16-byte write only user configuration register, which retains its value in Sleep mode. Page 54 WT1231H As shown in Figure 33 and Figure 34 above the message part of the Packet can be encrypted and decrypted with the cipher 128- cipher key stored in the configuration registers. 5.5.5.1. Tx Processing 1. User enters the data to be transmitted in FIFO in Stdby/Sleep mode and gives the transmit command. 2. On Tx command the Packet handler state machine takes over the control and If encryption is enabled then the message inside the FIFO is read in blocks of 16 bytes (padded with 0s if needed), encrypted and stored back to FIFO. All this processing is done in Tx mode before enabling the packet handling state machine. Only the Message part of the packet is encrypted and preamble, sync word, length byte, address byte and CRC are not encrypted. 3. Once the encryption is done the Packet handling state machine is enabled to transmit the data. 5.5.5.2. Rx Processing 1. The data received is stored in the FIFO, The address, CRC interrupts are generated as usual because these parameters were not encrypted. 2. Once the complete packet has been received. The data is read from the FIFO, decrypted and written back to FIFO. The PayloadReady interrupt is issued once the decrypted data is ready in the FIFO for reading via the SPI interface. The AES encryption/decryption cannot be used on the fly i.e. while transmitting and receiving data. Thus when AES encryption/decryption is enabled, the FIFO acts as a simple buffer. This buffer is filled before initiating any transmission. The data in the buffer is then encrypted before the transmission can begin. On the receive side the decryption is initiated only once the complete packet has been received in the buffer. The encryption/decryption process takes approximately 7.0 us per 16-byte block. Thus for a maximum of 4 blocks (i.e. 64 bytes) it can take up to 28 us for completing the cryptographic operations. The receive side sees the AES decryption time as a sequential delay before the PayloadReady interrupt is available. The Tx side sees the AES encryption time as a sequential delay in the startup of the Tx chain, thus the startup time of the Tx will increase according to the length of data. In Fixed length mode the Message part of the payload that can be encrypted/decrypted can be 64 bytes long. If the address filtering is enabled, the length of the payload should be at max 65 bytes in this case. In Variable length mode the Max message size that can be encrypted/decrypted is also 64 bytes when address filtering is disabled, else it is 48 bytes. Thus, including length byte, the length of the payload is max 65 or 50 bytes (the latter when address filtering is enabled). If the address filtering is expected then AddressFiltering must be enabled on the transmitter side as well to prevent address byte to be encrypted. Crc check being performed on encrypted data, CrcOk interrupt will occur "decryption time" before PayloadReady interrupt. Page 55 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET 5.5.6. Handling Large Packets When Payload length exceeds FIFO size (66 bytes) whether in fixed, variable or unlimited length packet format, in addition to PacketSent in Tx and PayloadReady or CrcOk in Rx, the FIFO interrupts/flags can be used as described below:

For Tx:

FIFO can be prefilled in Sleep/Standby but must be refilled "on-the-fly" during Tx with the rest of the payload. 1) Prefill FIFO (in Sleep/Standby first or directly in Tx mode) until FifoThreshold or FifoFull is set 2) In Tx, wait for FifoThreshold or FifoNotEmpty to be cleared (i.e. FIFO is nearly empty) 3) Write bytes into the FIFO until FifoThreshold or FifoFull is set. 4) Continue to step 2 until the entire message has been written to the FIFO (PacketSent will fire when the last bit of the packet has been sent).

For Rx:

FIFO must be unfilled "on-the-fly" during Rx to prevent FIFO overrun. 1) Start reading bytes from the FIFO when FifoNotEmpty or FifoThreshold becomes set. 2) Suspend reading from the FIFO if FifoNotEmpty clears before all bytes of the message have been read 3) Continue to step 1 until PayloadReady or CrcOk fires 4) Read all remaining bytes from the FIFO either in Rx or Sleep/Standby mode Note AES encryption is not feasible on large packets, since all Payload bytes need to be in the FIFO at the same time to perform encryption 5.5.7. Packet Filtering WT1231H's packet handler offers several mechanisms for packet filtering, ensuring that only useful packets are made available to the uC, reducing significantly system power consumption and software complexity. 5.5.7.1. Sync Word Based Sync word filtering/recognition is used for identifying the start of the payload and also for network identification. As previously described, the Sync word recognition block is configured (size, error tolerance, value) in RegSyncValue registers. This information is used, both for appending Sync word in Tx, and filtering packets in Rx. Every received packet which does not start with this locally configured Sync word is automatically discarded and no interrupt is generated. When the Sync word is detected, payload reception automatically starts and SyncAddressMatch is asserted. Note Sync Word values containing 0x00 byte(s) are forbidden Page 56 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET 5.5.7.2. Address Based Address filtering can be enabled via the AddressFiltering bits. It adds another level of filtering, above Sync word (i.e. Sync must match first), typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word) and each node has its own ID (address). Two address based filtering options are available:

AddressFiltering = 01: Received address field is compared with internal register NodeAddress. If they match then thepacket is accepted and processed, otherwise it is discarded.

AddressFiltering = 10: Received address internal registers NodeAddress and BroadcastAddress.If either is a match, the received packet is accepted and processed, otherwise it is discarded. This additional check with a constant is useful for implementing broadcast in a multi-node networks is compared with field Please note that the received address byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. In addition, NodeAddress and AddressFiltering only apply to Rx. On Tx side, if address filtering is expected, the address byte should simply be put into the FIFO like any other byte of the payload. As address filtering requires a Sync word match, both features share the same interrupt flag SyncAddressMatch. 5.5.7.3. Length Based In variable length Packet mode, PayloadLength must be programmed with the maximum payload length permitted. If received length byte is smaller than this maximum then the packet is accepted and processed, otherwise it is discarded. Please note that the received length byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. To disable this function the user should set the value of the PayloadLength to 255. 5.5.7.4. CRC Based The CRC check is enabled by setting bit CrcOn in RegPacketConfig1. It is used for checking the integrity of the message.

On Tx side a two byte CRC checksum is calculated on the payload part of the packet and appended to the end of the message

On Rx side the checksum is calculated on the received payload and compared with the two checksum bytes received.The result of the comparison is stored in bit CrcOk. By default, if the CRC check fails then the FIFO is automatically cleared and no interrupt is generated. This filtering function can be disabled via CrcAutoClearOff bit and in this case, even if CRC fails, the FIFO is not cleared and only PayloadReady interrupt goes high. Please note that in both cases, the two CRC checksum bytes are stripped off by the packet handler and only the payload is made available in the FIFO. The CRC is based on the CCITT polynomial as shown below. This implementation also detects errors due to leading and trailing zeros. Page 57 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET data input CRC Polynomial =X16 + X12 + X5 + 1 X15 X14 X13 X12 X11

* * *

X5 X4

* * *

X0 Figure 36. CRC Implementation 5.5.8. DC-Free Data Mechanisms The payload to be transmitted may contain long sequences of 1's and 0's, which introduces a DC bias in the transmitted signal. The radio signal thus produced has a non uniform power distribution over the occupied channel bandwidth. It also introduces data dependencies in the normal operation of the demodulator. Thus it is useful if the transmitted data is random and DC free. For such purposes, two techniques are made available in the packet handler: Manchester encoding and data whitening. Note Only one of the two methods should be enabled at a time. 5.5.8.1. Manchester Encoding Manchester encoding/decoding is enabled if DcFree = 01 and can only be used in Packet mode. The NRZ data is converted to Manchester code by coding '1' as "10" and '0' as "01". In this case, the maximum chip rate is the maximum bit rate given in the specifications section and the actual bit rate is half the chip rate. Manchester encoding and decoding is only applied to the payload and CRC checksum while preamble and Sync word are kept NRZ. However, the chip rate from preamble to CRC is the same and defined by BitRate in RegBitRate (Chip Rate =

Bit Rate NRZ = 2 x Bit Rate Manchester). Manchester encoding/decoding is thus made transparent for the user, who still provides/retrieves NRZ data to/from the FIFO RF chips @ BR User/NRZ bits Manchester OFF User/NRZ bits Manchester ON 1/BR ...Sync 0 1 1 0 1 1

... 1

... 1

... 1 1 1 0 1 1 1 0 0 0 0 0 0 1/BR 0 0 0 0 1 1 Payload... 1 0 0 1 1 1 1 1 0 0 1 1 0 0 1 0 0 1 1 t

... .. .. Figure 37. Manchester Encoding/Decoding Page 58 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET 5.5.8.2. Data Whitening Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission. The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using the same sequence. Comparing to Manchester technique it has the advantage of keeping NRZ data rate i.e. actual bit rate is not halved. The whitening/de-whitening process is enabled if DcFree = 10. A 9-bit LFSR is used to generate a random sequence. The payload and 2-byte CRC checksum is then XORed with this random sequence as shown below. The data is de-whitened on the receiver side by XORing with the same random sequence. Payload whitening/de-whitening is thus made transparent for the user, who still provides/retrieves NRZ data to/from the FIFO. LFS R P o ly nom ia l =X 9 + X 5 + 1 X 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 T ra n s m it d a ta W h iten ed da ta Figure 38. Data Whitening Page 59 WT1231H DATASHEET ADVANCED COMMUNICATIONS & SENSING 6. Configuration and Status Registers 6.1. General Description Table 23 Registers Summary Address Register Name Reset

(built-in) Default

(recom mended) Description 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 RegFifo RegOpMode RegDataModul RegBitrateMsb RegBitrateLsb RegFdevMsb RegFdevLsb RegFrfMsb RegFrfMid RegFrfLsb RegOsc1 RegAfcCtrl Reserved0C RegListen1 RegListen2 RegListen3 RegVersion RegPaLevel RegPaRamp RegOcp Reserved14 Reserved15 Reserved16 Reserved17 RegLna RegRxBw 0x00 0x04 0x00 0x1A 0x0B 0x00 0x52 0xE4 0xC0 0x00 0x41 0x00 0x02 0x92 0xF5 0x20 0x24 0x9F 0x09 0x1A 0x40 0xB0 0x7B 0x9B FIFO read/write access Operating modes of the transceiver Data operation mode and Modulation settings Bit Rate setting, Most Significant Bits Bit Rate setting, Least Significant Bits Frequency Deviation setting, Most Significant Bits Frequency Deviation setting, Least Significant Bits RF Carrier Frequency, Most Significant Bits RF Carrier Frequency, Intermediate Bits RF Carrier Frequency, Least Significant Bits RC Oscillators Settings AFC control in low modulation index situations

-

Listen Mode settings Listen Mode Idle duration Listen Mode Rx duration PA selection and Output Power control Control of the PA ramp time in FSK mode Over Current Protection control

-

-

-

-

0x08 0x86 0x88 0x55 LNA settings Channel Filter BW Control Page 60 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET Address Register Name Reset

(built-in) Default

(recom mended) Description RegAfcBw 0x8A 0x8B Channel Filter BW control during the AFC routine 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D RegOokPeak RegOokAvg RegOokFix RegAfcFei RegAfcMsb RegAfcLsb RegFeiMsb RegFeiLsb RegRssiConfig RegRssiValue RegDioMapping1 RegDioMapping2 0x05 RegIrqFlags1 RegIrqFlags2 RegRssiThresh 0xFF RegRxTimeout1 RegRxTimeout2 RegPreambleMsb RegPreambleLsb RegSyncConfig RegPacketConfig1 RegPayloadLength RegNodeAdrs RegBroadcastAdrs RegAutoModes RegFifoThresh 0x40 0x80 0x06 0x10 0x00 0x00 0x00 0x00 0x02 0xFF 0x00 0x80 0x00 0x00 0x00 0x00 0x03 0x98 0x10 0x40 0x00 0x00 0x00 OOK demodulator selection and control in peak mode Average threshold control of the OOK demodulator Fixed threshold control of the OOK demodulator AFC and FEI control and status MSB of the frequency correction of the AFC LSB of the frequency correction of the AFC MSB of the calculated frequency error LSB of the calculated frequency error RSSI-related settings RSSI value in dBm Mapping of pins DIO0 to DIO3 0x07 Mapping of pins DIO4 and DIO5, ClkOut frequency Status register: PLL Lock state, Timeout, RSSI > Threshold... Status register: FIFO handling flags... 0xE4 RSSI Threshold control Timeout duration between Rx request and RSSI detection Timeout duration between RSSI detection and PayloadReady Preamble length, MSB Preamble length, LSB Sync Word Recognition control 0x01 Sync Word bytes, 1 through 8 Packet mode settings Payload length setting Node address Broadcast address Auto modes settings 0x0F 0x8F Fifo threshold, Tx start condition RegPacketConfig2 0x02 Packet mode settings Page 61 0x2F-0x36 RegSyncValue1-8 0x00 WT1231H Reset

(built-in) Default

(recom mended) Description Address Register Name 0x3E-0x4D RegAesKey1-16 0x4E 0x4F 0x58 0x5A 0x5C 0x6F 0x71 0x50 +

RegTemp1 RegTemp2 RegTestLna RegTestPa1 RegTestPa2 RegTestDagc 0x00 RegTestAfc RegTest 0x00 0x01 0x00 0x1B 0x55 0x70 0x00

-

16 bytes of the cypher key Temperature Sensor control Temperature readout Sensitivity boost High Power PA settings High Power PA settings 0x30 Fading Margin Improvement AFC offset for low modulation index AFC Internal test registers Note

- Reset values are automatically refreshed in the chip at Power On Reset

- Default values are recommended register values, optimizing the device operation

- Registers for which the Default value differs from the Reset value are denoted by a * in the tables of section 6 Page 62 6.2. Common Configuration Registers WT1231H Bits Variable Name Table 24 Common Configuration Registers Name

(Address) RegFifo

(0x00) RegOpMode

(0x01) SequencerOff 7-0 Fifo 7 6 5 ListenOn ListenAbort 4-2 Mode RegDataModul

(0x02)

-

-

1-0 7 6-5 DataMode 4-3 ModulationType

-

2 1-0 ModulationShaping Mode Default Value Description rw 0x00 FIFO data input/output rw rw w rw r r rw rw r rw 0 0 0 001 00 0 00 00 0 00 Controls the automatic Sequencer (see section 4.2 ):

0 Operating mode as selected with Mode bits in RegOpMode is automatically reached with the Sequencer 1 Mode is forced by the user Enables Listen mode, should be enabled whilst in Standby mode:

0 Off (see section 4.3) 1 On Aborts Listen mode when set together with ListenOn=0 See section 4.3.4 for details Always reads 0. Transceivers operating modes:

000 Sleep mode (SLEEP) 001 Standby mode (STDBY) 010 Frequency Synthesizer mode (FS) 011 Transmitter mode (TX) 100 Receiver mode (RX) others reserved; Reads the value corresponding to the current module mode unused unused Data processing mode:

00 Packet mode 01 reserved 10 Continuous mode with bit synchronizer 11 Continuous mode without bit synchronizer Modulation scheme:

00 FSK 01 OOK 10 - 11 reserved unused Data shaping:

in FSK:

00 no shaping 01 Gaussian filter, BT = 1.0 10 Gaussian filter, BT = 0.5 11 Gaussian filter, BT = 0.3 in OOK:

00 no shaping 01 filtering with fcutoff = BR 10 filtering with fcutoff = 2*BR 11 reserved RegBitrateMsb

(0x03) 7-0 BitRate(15:8) rw 0x1a MSB of Bit Rate (Chip Rate when Manchester encoding is enabled) Page 63 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET RegBitrateLsb

(0x04) 7-0 BitRate(7:0) RegFdevMsb

(0x05) RegFdevLsb

(0x06) RegFrfMsb

(0x07) RegFrfMid

(0x08) RegFrfLsb

(0x09) RegOsc1

(0x0A) RegAfcCtrl

(0x0B)

-

7-6 5-0 Fdev(13:8) 7-0 Fdev(7:0) 7-0 Frf(23:16) 7-0 Frf(15:8) 7-0 Frf(7:0) 7 6 RcCalStart RcCalDone 5-0 7-6 5

-

-

AfcLowBetaOn 4-0 7-0

-

-

Reserved0C

(0x0C) rw 0x0b LSB of Bit Rate (Chip Rate if Manchester encoding is enabled) BitRate = --------F----X----O-----S---C----------

BitRate(15,0) Default value: 4.8 kb/s unused 00 000000 MSB of the frequency deviation LSB of the frequency deviation 0x52 Fdev = Fstep Fdev(15,0) Default value: 5 kHz 0xe4 MSB of the RF carrier frequency 0xc0 Middle byte of the RF carrier frequency 0x00 0 1 LSB of the RF carrier frequency Frf = Fstep Frf 23;0 Default value: Frf = 915 MHz (32 MHz XO) Triggers the calibration of the RC oscillator when set. Always reads 0. RC calibration must be triggered in Standby mode. 0 RC calibration in progress 1 RC calibration is over 00 0 000001 unused unused Improved AFC routine for signals with modulation index lower than 2. Refer to section 3.4.16 for details 0 Standard AFC routine 1 Improved AFC routine 00000 unused unused 0x02 r rw rw rw rw rw w r r r rw r r Page 64 ADVANCED COMMUNICATIONS & SENSING RegListen1

(0x0D) 7-6 ListenResolIdle rw 10 5-4 ListenResolRx rw 01 3 ListenCriteria rw 0 2-1 ListenEnd rw 01 WT1231H DATASHEET Resolution of Listen mode Idle time (calibrated RC osc):

00 reserved 01 64 us 10 4.1 ms 11 262 ms Resolution of Listen mode Rx time (calibrated RC osc):

00 reserved 01 64 us 10 4.1 ms 11 262 ms Criteria for packet acceptance in Listen mode:

0 signal strength is above RssiThreshold 1 signal strength is above RssiThreshold and SyncAddress matched Action taken after acceptance of a packet in Listen mode:

00 chip stays in Rx mode. Listen mode stops and must be disabled (see section 4.3). 01 chip stays in Rx mode until PayloadReady or Timeout interrupt occurs. It then goes to the mode defined by Mode. Listen mode stops and must be disabled (see section 4.3). 10 chip stays in Rx mode until PayloadReady or Timeout interrupt occurs. Listen mode then resumes in Idle state. FIFO content is lost at next Rx wakeup. 11 Reserved unused RegListen2

(0x0E) RegListen3

(0x0F) RegVersion

(0x10) 0 7-0

-

ListenCoefIdle 7-0 ListenCoefRx r rw rw 0 0xf5 Duration of the Idle phase in Listen mode. tListenIdle = ListenCoefIdle ListenResolIdle 0x20 Duration of the Rx phase in Listen mode (startup time included, see section 4.2.3) tListenRx = ListenCoefRx ListenResolRx 7-0 Version r 0x24 Version code of the chip. Bits 7-4 give the full revision number; bits 3-0 give the metal mask revision number. Page 65 ADVANCED COMMUNICATIONS & SENSING 6.3. Transmitter Registers WT1231H DATASHEET Table 25 Transmitter Registers Name

(Address) RegPaLevel

(0x11) Bits Variable Name Pa0On *

Pa1On *

Pa2On *

7 6 5 4-0 OutputPower Mode Default rw rw rw rw 1 0 0 Value Description Enables PA0, connected to RFIO and LNA Enables PA1, on PA_BOOST pin Enables PA2, on PA_BOOST pin 11111 Output power setting, with 1 dB steps RegPaRamp

(0x12)

-

7-4 3-0 PaRamp r rw 0000 1001 Rise/Fall time of ramp up/down in FSK Pout = -18 + OutputPower [dBm] , with PA0 Pout = -18 + OutputPower [dBm] , with PA1**

Pout = -14+ OutputPower [dBm] , with PA1 and PA2**

Pout = -11 + OutputPower [dBm] , with PA1 and PA2, and high Power PA settings (refer to section 3.3.7)**

unused 0000 3.4 ms 0001 2 ms 0010 1 ms 0011 500 us 0100 250 us 0101 125 us 0110 100 us 0111 62 us 1000 50 us 1001 40 us 1010 31 us 1011 25 us 1100 20 us 1101 15 us 1110 12 us 1111 10 us unused Enables overload current protection (OCP) for the PA:

0 OCP disabled 1 OCP enabled Trimming of OCP current:

Imax = 45 + 5 OcpTrim mA 95 mA OCP by default Page 66 RegOcp

(0x13) 7-5 4

-

OcpOn 3-0 OcpTrim r rw rw 000 1 1010 Note

*Power Amplifier truth table is available in Table 10

** Only the16 upper values of OutputPower are accessible ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET Bits Variable Name

-

7-0 6.4. Receiver Registers Table 26 Receiver Registers Name

(Address) Reserved14

(0x14) Reserved15

(0x15) Reserved16

(0x16) Reserved17

(0x17) RegLna

(0x18) LnaZin 7-0 7-0 7-0 7

-

-

-

6 5-3 2-0

-

LnaCurrentGain LnaGainSelect RegRxBw

(0x19) 7-5 DccFreq 4-3 RxBwMant 2-0 RxBwExp RegAfcBw

(0x1A) 7-5 DccFreqAfc 4-3 RxBwMantAfc 2-0 RxBwExpAfc Mode Default Value Description 0x40 unused r r r r rw r r rw rw rw rw rw rw rw 0xB0 unused 0x7B unused 0x9B unused 1

*

0 001 000 010

*

10

*

101

*

LNAs input impedance 0 50 ohms 1 200 ohms unused Current LNA gain, set either manually, or by the AGC LNA gain setting:

000 gain set by the internal AGC loop 001 G1 = highest gain 010 G2 = highest gain 6 dB 011 G3 = highest gain 12 dB 100 G4 = highest gain 24 dB 101 G5 = highest gain 36 dB 110 G6 = highest gain 48 dB 111 reserved Cut-off frequency of the DC offset canceller (DCC):

-----

-----------------

~4% of the RxBw by default Channel filter bandwidth control:

00 RxBwMant = 16 01 RxBwMant = 20 Channel filter bandwidth control:

FSK Mode:

10 RxBwMant = 24 11 reserved RxBw = ------------------------F----X----O----S----C-------------------------

RxBwMant 2RxBwExp + 2 OOK Mode:

RxBw = ------------------------F----X----O----S----C-------------------------

RxBwMant 2RxBwExp + 3 See Table 14 for tabulated values DccFreq parameter used during the AFC 100 01 RxBwMant parameter used during the AFC 011 * RxBwExp parameter used during the AFC Page 67 ADVANCED COMMUNICATIONS & SENSING RegOokPeak

(0x1B) 7-6 OokThreshType 5-3 OokPeakTheshStep rw rw 01 000 2-0 OokPeakThreshDec rw 000 7-6 OokAverageThreshFilt rw 10 RegOokAvg

(0x1C) RegOokFix

(0x1D) RegAfcFei

(0x1E) RegAfcMsb

(0x1F) RegAfcLsb

(0x20) RegFeiMsb

(0x21) RegFeiLsb

(0x22) RegRssiConfig

(0x23) RegRssiValue

(0x24)

-

5-0 7-0 OokFixedThresh 7 6 5 4 3 2

-

FeiDone FeiStart AfcDone AfcAutoclearOn AfcAutoOn AfcClear AfcStart 1 0 7-0 AfcValue(15:8) 7-0 AfcValue(7:0) 7-0 FeiValue(15:8) 7-0 FeiValue(7:0) 7-2 1

-

RssiDone 0 RssiStart 7-0 RssiValue r rw r r w r rw rw w w r r r r r r w r WT1231H DATASHEET 10 average 11 reserved 001 1.0 dB 011 2.0 dB 101 4.0 dB 111 6.0 dB Selects type of threshold in the OOK data slicer:

00 fixed 01 peak Size of each decrement of the RSSI threshold in the OOK demodulator:

000 0.5 dB 010 1.5 dB 100 3.0 dB 110 5.0 dB Period of decrement of the RSSI threshold in the OOK demodulator:

001 once every 2 chips 000 once per chip 011 once every 8 chips 010 once every 4 chips 100 twice in each chip 101 4 times in each chip 110 8 times in each chip 111 16 times in each chip Filter coefficients in average mode of the OOK demodulator:

00 fC chip rate / 32. 10 fC chip rate / 4. 01 fC chip rate / 8. 11 fC chip rate / 2. 000000 unused 0110

(6dB) 0 1 0 0 Fixed threshold value (in dB) in the OOK demodulator. Used when OokThresType = 00 unused 0 FEI is on-going 1 FEI finished Triggers a FEI measurement when set. Always reads 0. 0 AFC is on-going 1 AFC has finished Only valid if AfcAutoOn is set 0 AFC register is not cleared before a new AFC phase 1 AFC register is cleared before a new AFC phase 0 AFC is performed each time AfcStart is set 1 AFC is performed each time Rx mode is entered Clears the AfcValue if set in Rx mode. Always reads 0 Triggers an AFC when set. Always reads 0. 0x00 MSB of the AfcValue, 2s complement format 0 0 0 0 0x00

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LSB of the AfcValue, 2s complement format Frequency correction = AfcValue x Fstep MSB of the measured frequency offset, 2s complement LSB of the measured frequency offset, 2s complement Frequency error = FeiValue x Fstep 000000 unused 1 0 0 RSSI is on-going 1 RSSI sampling is finished, result available Trigger a RSSI measurement when set. Always reads 0. 0xFF Absolute value of the RSSI in dBm, 0.5dB steps. RSSI = -RssiValue/2 [dBm]

Page 68 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET 6.5. IRQ and Pin Mapping Registers Table 27 IRQ and Pin Mapping Registers Name

(Address) RegDioMapping1

(0x25) Bits Variable Name RegDioMapping2

(0x26) 7-6 Dio0Mapping 5-4 Dio1Mapping 3-2 Dio2Mapping 1-0 Dio3Mapping 7-6 Dio4Mapping 5-4 Dio5Mapping 3 2-0 ClkOut

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Mode Default rw rw rw rw rw rw r rw Value Description 00 00 00 00 00 00 0 111

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RegIrqFlags1

(0x27) 7 ModeReady 6 5 4 3 2 1 RxReady TxReady PllLock Rssi Timeout AutoMode r r r r rwc r r 0 SyncAddressMatch r/rwc 1 0 0 0 0 0 0 0 Mapping of pins DIO0 to DIO5 See Table 21 for mapping in Continuous mode See Table 22 for mapping in Packet mode unused Selects CLKOUT frequency:

000 FXOSC 001 FXOSC / 2 010 FXOSC / 4 011 FXOSC / 8 100 FXOSC / 16 101 FXOSC / 32 110 RC (automatically enabled) 111 OFF Set when the operation mode requested in Mode, is ready

- Sleep: Entering Sleep mode

- Standby: XO is running

- FS: PLL is locked

- Rx: RSSI sampling starts

- Tx: PA ramp-up completed Cleared when changing operating mode. Set in Rx mode, after RSSI, AGC and AFC. Cleared when leaving Rx. Set in Tx mode, after PA ramp-up. Cleared when leaving Tx. Set (in FS, Rx or Tx) when the PLL is locked. Cleared when it is not. Set in Rx when the RssiValue exceeds RssiThreshold. Cleared when leaving Rx. Set when a timeout occurs (see TimeoutRxStart and TimeoutRssiThresh) Cleared when leaving Rx or FIFO is emptied. Set when entering Intermediate mode. Cleared when exiting Intermediate mode. Please note that in Sleep mode a small delay can be observed between AutoMode interrupt and the corresponding enter/exit condition. Set when Sync and Address (if enabled) are detected. Cleared when leaving Rx or FIFO is emptied. This bit is read only in Packet mode, rwc in Continuous mode Page 69 ADVANCED COMMUNICATIONS & SENSING RegIrqFlags2

(0x28) RegRssiThresh

(0x29) RegRxTimeout1

(0x2A) RegRxTimeout2

(0x2B) 7 6 5 4 3 2 1 FifoFull FifoNotEmpty FifoLevel FifoOverrun PacketSent PayloadReady CrcOk

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0 7-0 RssiThreshold 7-0 TimeoutRxStart r r r rwc r r r r rw rw 0 0 0 0 0 0 0 0 0xE4

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0x00 7-0 TimeoutRssiThresh rw 0x00 WT1231H DATASHEET Set when FIFO is full (i.e. contains 66 bytes), else cleared. Set when FIFO contains at least one byte, else cleared Set when the number of bytes in the FIFO strictly exceeds FifoThreshold, else cleared. Set when FIFO overrun occurs. (except in Sleep mode) Flag(s) and FIFO are cleared when this bit is set. The FIFO then becomes immediately available for the next transmission / reception. Set in Tx when the complete packet has been sent. Cleared when exiting Tx. Set in Rx when the payload is ready (i.e. last byte received and CRC, if enabled and CrcAutoClearOff is cleared, is Ok). Cleared when FIFO is empty. Set in Rx when the CRC of the payload is Ok. Cleared when FIFO is empty. unused RSSI trigger level for Rssi interrupt :

- RssiThreshold / 2 [dBm]

Timeout interrupt is generated TimeoutRxStart*16*Tbit after switching to Rx mode if Rssi interrupt doesnt occur

(i.e. RssiValue > RssiThreshold) 0x00: TimeoutRxStart is disabled Timeout interrupt is generated TimeoutRssiThresh*16*Tbit after Rssi interrupt if PayloadReady interrupt doesnt occur. 0x00: TimeoutRssiThresh is disabled Page 70 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET Bits Variable Name 6.6. Packet Engine Registers Table 28 Packet Engine Registers Name

(Address) RegPreambleMsb

(0x2c) RegPreambleLsb

(0x2d) RegSyncConfig

(0x2e) SyncOn 7 7-0 PreambleSize(7:0) 7-0 PreambleSize(15:8) 6 FifoFillCondition 5-3 SyncSize 2-0 SyncTol 7-0 SyncValue(63:56) 7-0 SyncValue(55:48) 7-0 SyncValue(47:40) 7-0 SyncValue(39:32) 7-0 SyncValue(31:24) 7-0 SyncValue(23:16) 7-0 SyncValue(15:8) 7-0 SyncValue(7:0) RegSyncValue1

(0x2f) RegSyncValue2

(0x30) RegSyncValue3

(0x31) RegSyncValue4

(0x32) RegSyncValue5

(0x33) RegSyncValue6

(0x34) RegSyncValue7

(0x35) RegSyncValue8

(0x36) Mode Default rw Value Description 0x00 Size of the preamble to be sent (from TxStartCondition fulfilled). (MSB byte) 0x03 Size of the preamble to be sent (from TxStartCondition rw rw rw rw rw rw rw rw rw rw rw rw rw fulfilled). (LSB byte) Enables the Sync word generation and detection:

0 Off 1 On FIFO filling condition:

0 if SyncAddress interrupt occurs 1 as long as FifoFillCondition is set Size of the Sync word:

(SyncSize + 1) bytes Number of tolerated bit errors in Sync word 1st byte of Sync word. (MSB byte) Used if SyncOn is set. 2nd byte of Sync word Used if SyncOn is set and (SyncSize +1) >= 2. 3rd byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 3. 4th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 4. 5th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 5. 6th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 6. 7th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 7. 8th byte of Sync word. Used if SyncOn is set and (SyncSize +1) = 8. 1 0 011 000 0x01

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0x01

*

0x01

*

0x01

*

0x01

*

0x01

*

0x01

*

0x01

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Page 71 ADVANCED COMMUNICATIONS & SENSING RegPacketConfig1

(0x37) 7 PacketFormat 6-5 DcFree 4 3 CrcOn CrcAutoClearOff rw rw rw rw 0 00 1 0 2-1 AddressFiltering rw 00 RegPayloadLength

(0x38) RegNodeAdrs

(0x39) RegBroadcastAdrs

(0x3A) RegAutoModes

(0x3B)

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0 7-0 PayloadLength 7-0 NodeAddress 7-0 BroadcastAddress 7-5 EnterCondition rw rw rw rw rw 0 0x40 000 4-2 ExitCondition rw 000 1-0 IntermediateMode rw 00 WT1231H DATASHEET Defines the packet format used:

0 Fixed length 1 Variable length Defines DC-free encoding/decoding performed:

00 None (Off) 01 Manchester 10 Whitening 11 reserved Enables CRC calculation/check (Tx/Rx):

0 Off 1 On Defines the behavior of the packet handler when CRC check fails:

0 Clear FIFO and restart new packet reception. No PayloadReady interrupt issued. 1 Do not clear FIFO. PayloadReady interrupt issued. Defines address based filtering in Rx:

00 None (Off) 01 Address field must match NodeAddress 10 Address field must match NodeAddress or BroadcastAddress 11 reserved unused If PacketFormat = 0 (fixed), payload length. If PacketFormat = 1 (variable), max length in Rx, not used in Tx. 0x00 Node address used in address filtering. 0x00 Broadcast address used in address filtering. Interrupt condition for entering the intermediate mode:

000 None (AutoModes Off) 001 Rising edge of FifoNotEmpty 010 Rising edge of FifoLevel 011 Rising edge of CrcOk 100 Rising edge of PayloadReady 101 Rising edge of SyncAddress 110 Rising edge of PacketSent 111 Falling edge of FifoNotEmpty (i.e. FIFO empty) Interrupt condition for exiting the intermediate mode:

000 None (AutoModes Off) 001 Falling edge of FifoNotEmpty (i.e. FIFO empty) 010 Rising edge of FifoLevel or Timeout 011 Rising edge of CrcOk or Timeout 100 Rising edge of PayloadReady or Timeout 101 Rising edge of SyncAddress or Timeout 110 Rising edge of PacketSent 111 Rising edge of Timeout Intermediate mode:

00 Sleep mode (SLEEP) 01 Standby mode (STDBY) 10 Receiver mode (RX) 11 Transmitter mode (TX) Page 72 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET RegFifoThresh

(0x3C) 7 TxStartCondition RegPacketConfig2

(0x3D) 6-0 FifoThreshold 7-4 InterPacketRxDelay 3 2 1

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RestartRx AutoRxRestartOn 0 AesOn 7-0 AesKey(127:120) 7-0 AesKey(119:112) 7-0 AesKey(111:104) 7-0 AesKey(103:96) 7-0 AesKey(95:88) 7-0 AesKey(87:80) 7-0 AesKey(79:72) 7-0 AesKey(71:64) 7-0 AesKey(63:56) 7-0 AesKey(55:48) 7-0 AesKey(47:40) 7-0 AesKey(39:32) 7-0 AesKey(31:24) RegAesKey1

(0x3E) RegAesKey2

(0x3F) RegAesKey3

(0x40) RegAesKey4

(0x41) RegAesKey5

(0x42) RegAesKey6

(0x43) RegAesKey7

(0x44) RegAesKey8

(0x45) RegAesKey9

(0x46) RegAesKey10

(0x47) RegAesKey11

(0x48) RegAesKey12

(0x49) RegAesKey13

(0x4A) rw rw rw rw w rw rw w w w w w w w w w w w w w 1

*

Defines the condition to start packet transmission :

0 FifoLevel (i.e. the number of bytes in the FIFO exceeds FifoThreshold) 1 FifoNotEmpty (i.e. at least one byte in the FIFO) 0001111 Used to trigger FifoLevel interrupt. 0000 0 0 1 0 0x00 After PayloadReady occurred, defines the delay between FIFO empty and the start of a new RSSI phase for next packet. Must match the transmitters PA ramp-down time.

- Tdelay = 0 if InterpacketRxDelay >= 12

- Tdelay = (2InterpacketRxDelay) / BitRate otherwise unused Forces the Receiver in WAIT mode, in Continuous Rx mode. Always reads 0. Enables automatic Rx restart (RSSI phase) after PayloadReady occurred and packet has been completely read from FIFO:

0 Off. RestartRx can be used. 1 On. Rx automatically restarted after InterPacketRxDelay. Enable the AES encryption/decryption:

0 Off 1 On (payload limited to 66 bytes maximum) 1st byte of cipher key (MSB byte) 0x00 2nd byte of cipher key 0x00 3rd byte of cipher key 0x00 4th byte of cipher key 0x00 5th byte of cipher key 0x00 6th byte of cipher key 0x00 7th byte of cipher key 0x00 8th byte of cipher key 0x00 9th byte of cipher key 0x00 10th byte of cipher key 0x00 11th byte of cipher key 0x00 12th byte of cipher key 0x00 13th byte of cipher key Page 73 ADVANCED COMMUNICATIONS & SENSING RegAesKey14

(0x4B) RegAesKey15

(0x4C) RegAesKey16

(0x4D) 7-0 AesKey(23:16) 7-0 AesKey(15:8) 7-0 AesKey(7:0) w w w 0x00 14th byte of cipher key 0x00 15th byte of cipher key 0x00 16th byte of cipher key (LSB byte) WT1231H DATASHEET 6.7. Temperature Sensor Registers Table 29 Temperature Sensor Registers Name

(Address) RegTemp1

(0x4E) Bits Variable Name TempMeasStart 7-4 -

3 2 TempMeasRunning RegTemp2

(0x4F) 1-0 -

7-0 TempValue r r r Mode Default Value Description 0000 r w 0 0 01

-

unused Triggers the temperature measurement when set. Always reads 0. Set to 1 while the temperature measurement is running. Toggles back to 0 when the measurement has completed. The receiver can not be used while measuring temperature unused Measured temperature

-1C per Lsb Needs calibration for accuracy 6.8. Test Registers Table 30 Test Registers Name

(Address) RegTestLna

(0x58) Bits Variable Name 7-0 SensitivityBoost Mode Default rw Value Description 0x1B High sensitivity or normal sensitivity mode:

0x1B Normal mode 0x2D High sensitivity mode RegTestPa1

(0x5A) RegTestPa2

(0x5C) RegTestDagc

(0x6F) RegTestAfc

(0x71) 7-0 Pa20dBm1 7-0 Pa20dBm2 7-0 ContinuousDagc 7-0 LowBetaAfcOffset rw rw rw rw 0x55 Set to 0x5D for +20 dBm operation on PA_BOOST. 0x55 Normal mode and Rx mode 0x5D +20 dBm mode Revert to 0x55 when receiving or using PA0 0x70 Set to 0x7C for +20 dBm operation on PA_BOOST 0x70 Normal mode and Rx mode 0x7C +20 dBm mode Revert to 0x70 when receiving or using PA0 Fading Margin Improvement, refer to 3.4.4 0x00 Normal mode 0x20 Improved margin, use if AfcLowBetaOn=1 0x30 Improved margin, use if AfcLowBetaOn=0 0x30

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0x00 AFC offset set for low modulation index systems, used if AfcLowBetaOn=1. Offset = LowBetaAfcOffset x 488 Hz Page 74 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET 7. Application Information 7.1. Crystal Resonator Specification Table 31 shows the crystal resonator specification for the crystal reference oscillator circuit of the WT1231H. This specification covers the full range of operation of the WT1231H and is employed in the reference design. Table 31 Crystal Specification Symbol Description Conditions FXOSC RS C0 XTAL Frequency XTAL Serial Resistance XTAL Shunt Capacitance CLOAD External Foot Capacitance On each pin XTA and XTB Min 26

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8 Typ

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30 2.8 16 Max 32 140 7 22 Unit MHz ohms pF pF Notes - the initial frequency tolerance, temperature stability and ageing performance should be chosen in accordance with the target operating temperature range and the receiver bandwidth selected.

- the loading capacitance should be applied externally, and adapted to the actual Cload specification of the XTAL.

- A minimum XTAL frequency of 28 MHz is required to cover the 863-870 MHz band, 29 MHz for the 902-928 MHz band 7.2. Reset of the Module A power-on reset of the WT1231H is triggered at power up. Additionally, a manual reset can be issued by controlling pin RESET. 7.2.1. POR If the application requires the disconnection of VDD from the WT1231H, despite of the extremely low Sleep Mode current, the user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI bus. Pin 6 (Reset) should be left floating during the POR sequence. VDD Pin Reset

(output) Undefined Wait for 10 ms Module is ready from this point on Figure 39. POR Timing Diagram Please note that any CLKOUT activity can also be used to detect that the module is ready. Page 75 ADVANCED COMMUNICATIONS & SENSING WT1231H DATASHEET 7.2.2. Manual Reset A manual reset of the WT1231H is possible even for applications in which VDD cannot be physically disconnected. Pin RESET should be pulled high for a hundred microseconds, and then released. The user should then wait for 5 ms before using the module. Figure 40. Manual Reset Timing Diagram Note whilst pin RESET is driven high, an over current consumption of up to ten milliamps can be seen on VDD. Page 76 7.3. Reference Design Please contact your representative for evaluation tools, reference designs and design assistance. Note that all schematics shown in this section are full schematics, listing ALL required components, including decoupling capacitors. WT1231H Figure 41:+20dBm Schematic A ADVANCED COMMUNICATIONS & SENSING DATASHEET Page 77 8. Packaging Information 8.1. Package Outline Drawing WT1231H Figure 42. S 2 Package Outline Drawing Page 78 WT1231H A 9. Ordering Information WT1231H433 S2 Package Operation Band Mode Type P/N: WT1231H-315S2 Package P/N: WT1231H-433S2 Package P/N: WT1231H-868S2 Package P/N: WT1231H-915S2 WT1231H module at 315MHz band, SMD WT1231H module at 433MHz band, SMD WT1231H module at 868MHz band, SMD WT1231H module at 915MHz band, SMD PackageV Receiver category: Category 2 is standard performance level of receiver. This device is intended only for OEM integrators under the following conditions:

1)The transmitter module may not be co-located with any other transmitter with gain less than 0dbi 2) For all products market in US, OEM has to limit the operation channels in 915MHz by supplied firmware programming tool. OEM shall not supply any tool or info to the end-user regarding to Regulatory Domain change.As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed The host will Satisfy Class I or Class permissive change based this module FCC ID. If the FCC identification number is not visible when the module is installed inside the host, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains Transmitter Module Contains FCC ID:2AFOSWT1231H-433 or Contains FCC ID:2AFOSWT1231H-433

.Any similar wording that expresses the same meaning may be used. Page 79