User manual of 3G SEP EVDO module User manual of 3G SEP Module
(EVDO version) Wistron NeWeb Corp. Page 1 User manual of 3G SEP EVDO module Revision History Version Ver 0.1 Ver 0.2 Ver 0.3 Ver 0.4 Ver 0.5 Change history Initial version Update EVDO Update IO spec Update FCC/IC warning statement Modify 6.4 FCC Module Integration Restriction Date 2012-10-15 2013-1-16 2013-1-22 2013-5-16 2013-5-29 Page 2 User manual of 3G SEP EVDO module Contents 2. Contents........................................................................................................................ 3 1. introduction ............................................................................................................ 5 productconcept.........................................................................................5 1.1 Termsandabbreviation.............................................................................5 1.2 1.3 Conventions...............................................................................................7 1.4 Productfeaturesoverview.........................................................................7 3GSEP Module Block diagram ............................................................................ 10 2.1 SIM...........................................................................................................12 AUDIO.......................................................................................................13 2.2 Highspeedinterchip(HSIC)Interface....................................................18 2.3 2.4 GeneralpurposeI/O................................................................................18 RESET........................................................................................................19 2.5 2.6 ADC...........................................................................................................19 PowerOUTPUT.....................................................................................................19 POWERSUPPLY&GND............................................................................19 2.7 POWERMANAGEMENT...........................................................................20 2.8 2.9 Sleepmodes.............................................................................................20 2.10 RTCfuncution...........................................................................................22 3. Pinout ................................................................................................................... 23 I/OConnectorPinAssignments...............................................................23 4. Electrical specificationS ....................................................................................... 30 4.1 VPHPwr...................................................................................................30 4.2 Vbackup....................................................................................................30 4.3 VSIM.........................................................................................................31 4.4 Digitalinterface........................................................................................31 4.5 RESET........................................................................................................31 4.6 SIM...........................................................................................................32 I2CInterfacE.........................................................................................................32 I2Chasthefollowingcharacteristics:..................................................................32 4.7 USB...........................................................................................................32 3.1 Page 3 User manual of 3G SEP EVDO module ADC...........................................................................................................32 4.8 UART.........................................................................................................33 4.9 SPI.............................................................................................................33 4.10 SDIO..........................................................................................................34 4.11 4.12 Highspeedinterchip(HSIC)interface....................................................36 4.13 DIGITALAUDIO.........................................................................................36 Theaudiooutputscontainthefollowingcharacteristics:...................................36 4.14 RFSIGNAL.................................................................................................40 5. Environmental specificationS .............................................................................. 41 NormaltemperatureRange.....................................................................41 ExtendedtemperatureRange..................................................................42 6. FCC warning statement ........................................................................................ 43 General.....................................................................................................43 EndProductLabeling(FCC)......................................................................43 RequiredFCCComplianceStatementforHostIntegration.....................43 FCCModuleIntegrationRestriction:........................................................44 6.1 6.2 6.3 6.4 5.1 5.2 Page 4 User manual of 3G SEP EVDO module INTRODUCTION 1. This document describes the specifications of the WNC 3G SEP M2M module used to connect the device application and the air interface. 1.1 PRODUCT CONCEPT The 3G SEP module provides CDMA connectivity for machine-to-machine
(M2M) application over dual frequency bands BC0 and BC1. The markets of application include AMM (Automatic Metering Management), tracking system, and alarm, etc. Application and physical features:
Interface and dimension: LGA; 34X34mm Operating temperature range: -30C to +85C Minimum low power consumption in the standby mode: 1.5mA DC supply: 3.4 V to 4.2 V USB2.0 high speed Supported frequency bands:
BC0 BC1 In addition to the 3G SEP module, a complete development kit can be provided to customers. 1.2 TERMS AND ABBREVIATION ADC CDMA CODEC CLIP COLP CLIR COLR CTS CSD Analog to Digital Converter Code Division Multiple Access Coder-Decoder Calling Line Identification Presentation Connected Line Identification Presentation Calling Line Identification Restriction Connected Line Identification Restriction Clear To Send Circuit Switched Data Page 5 CS DCS DSR DTR EDGE EGSM ENS EONS ESD ETS GNSS GSM GPRS GPS HSCSD HSDPA HSIC HSPA+
HSUPA IC IEEE I/O ISO ITU I2C I2S JTAG Kbps LCD LED LTE Mbps PA PBCCH PCB User manual of 3G SEP EVDO module Coding Scheme Digital Communications System Data Set Ready Data Terminal Ready Enhanced Data Rate for GSM Evolution Extended GSM Enhanced network selection Enhanced operator name string Electrostatic Discharge European Telecommunication Standard Global Navigation Satellite System Global System for Mobile communication General Packet Radio Services Global Positioning System High Speed Circuit Switched Data High Speed Downlink Packet Access High-speed inter-chip Evolved High-Speed Packet Access High Speed Uplink Packet Access Integrated Circuit Institute of Electrical and Electronics Engineers Input / Output International Standards Organization International Telecommunication Union Inter-integrated circuit Inter-IC sound Joint Test Action Group kilobit per second Liquid Crystal Display Light Emitting Diode Long term evolution Megabit per second Power amplifier Packet Broadcast Control Channel Printed Circuit Board Page 6 PCM PCS PMIC PWM RAM RF RI RMS RTS RX SIM SMS TBC TBD TCXO TX UART UIM UMTS USB USSD WCDMA User manual of 3G SEP EVDO module Pulse Code Modulation Personal Communication System Power management integrated circuit Pulse Width Modulation Random Access Memory Radio Frequency Ring Indication Root Mean Square Ready To Send Reception Subscriber Identification Module Short Message Service To Be Confirmed To Be Defined Temperature-compensated crystal oscillator Transmission Universal Asynchronous Receiver and Transmitter User identity module Universal Mobile Telecommunications System Universal Serial Bus Unstructured Supplementary Service Data Wideband Code Division Multiple Access 1.3 CONVENTIONS Throughout this document, DTE (data terminal equipment) indicates the equipment which masters and controls the module device UMC-3GSEP by sending AT commands via its serial interface. DCE (data communication equipment) indicates the UMC-3GSEP module device. 1.4 PRODUCT FEATURES OVERVIEW Page 7 Mechanical & environment Temperature range Weight (g) ESD Physical dimensions Connection Power supply Power consumption1 Cellular technologies CDMA bands Transmit power Main interfaces User manual of 3G SEP EVDO module Normal range: -30C to +70C (fully compliant) Extended range: -30C to +85C (fully functional) Storage: -40C to +105C 6 grams ESD protection :+/- 2 kV 34x34x3 mm 157 pins LGA contact 3.4V to 4.2V range, 4.0V nominal Off mode: 50 A typical Registered idle mode: (cell power -55dBm/1.23MHz) CDMA: 200mA Peak Current CDMA: up to 780mA BC0 : Tx: 824849 MHz; Rx: 869894 MHz BC1 : Tx: 18501910 MHz; Rx: 19301990 MHz 24dBm+/-1dB 1 The power consumption is highly dependent on the customers product design and the module environment. Page 8 USB UART control interface with flow Supported SIM cards SIM slot SIM detect General purpose I/O pins Power on pin Audio Digital audio link Voice codec User manual of 3G SEP EVDO module Supports USB High speed 480Mbps and full speed 12Mbps, with 3 logical Channels. Up to 3.6 Mbit/s for data transmission (no auto-bauding) Full flow control signals (+1.8V) are provided on a 94 pins LGA connector. A reference schematic to build the RS232 interface is provided in the UMC-3GSEP application note. 3V and 1.8V SIM cards Signals for the management of the SIM card are provided on LGA pins. Provides SIM card insert detection. GPIOs can be customized easily from the customers application and they can be configured as input or output Available A digital audio interface PCM/I2S bus is provided. Half Rate, Full Rate, Enhanced Full Rate, Adaptive Multi Rate Data/command multiplexing Software management of data/command multiplexing on the serial link UART. Data services 1xEV-DOrA High-speed peak data rates 3.1 Mbps forward link; 1.8 Mbps reverse link Page 9 User manual of 3G SEP EVDO module 2. 3GSEP MODULE BLOCK DIAGRAM Page 10 User manual of 3G SEP EVDO module Figure 1: 3G SEP Pin-out (Top view) Page 11 2.1 SIM User manual of 3G SEP EVDO module SIM card interface 2.1.1 The SIM Card Interface is compatible with the ISO 7816-3 IC card standard on the issues required by the GSM 11.11 Phase 2+ standard and adapts to 3V and 1.8V SIM cards. To prevent SIM card damage, the power supply of the module must be turned off before any manipulation of the SIM card. The SIM card interface includes:
Power supply output (LDO6) Bi-direction data signal (UIM1_DATA), Clock output (UIM1_CLK) Reset signal (UIM1_RESET) Signal UIM1_RESET UIM1_CLK LDO6 UIM1_DATA Pin N Description 26 90 91 27 SIM reset, provided by Base-band processor SIM clock, provided by Base-band processor SIM supply voltage SIM serial data line, input and output Page 12 2.1.2 User manual of 3G SEP EVDO module SIM CARD CONNECTION Figure 2: SIM connection Note: A reference schematic of the SIM card connection is given in the application note. 2.2 AUDIO Audio interface 2.2.1 The 3G SEP M2M module features a PCM/I2S interface. The PCM/I2S interface is a High speed full duplex interface that can be used to send and receive digital audio data to external audio ICs with the following characteristics:
Audio data could be transferred back and forth (Rx and Tx) using legacy digital audio interface Inter-IC sound (I2S) ports:
No external controller support. Page 13 User manual of 3G SEP EVDO module Pulse-code modulation (PCM) audio ports:
Fixed sampling rate at 8 kHz 8 bits A-Law or -Law 16 bits linear PCM PCM master mode Fixed PCM clock rate at 128 kHz or 2.048 MHz PCM slave mode Fixed PCM clock rate at 2.048 MHz only Signal I2S/PCM_CLK I2S_WS/PCM_SYNC I2S/PCM_RX I2S/PCM_TX I2S_MCLK Pin N Description 113 49 115 50 114 I2S/PCM clock signal I2S word select/ PCM sync signal I2S/PCM data input I2S/PCM data output I2S master clock Data services 2.2.2 The module supports the following services:
Data 1xEV-DOrA:
Standard
- DL: up to 3.1 Mbps
- UL: up to 1.8 Mbps UART interface 2.2.3 The UART interface is provided on external pins of the module with the following signals:
RX/TX RFR/CTS UART Speed AT commands and DATA: up to 4 Mbit/s Page 14 User manua al of 3G SEP EVDO modu ule Software download
: up to 1 M Mbit/s 2-pin Sig UA UA gnal ART2_TX ART2_RX n UART2 fo or PLC P Pin N D Description U 120 UART Tran 57 U UART Rece
(defined in smit eive n Modules s direction)
) 2-pin Sig UA UA gnal ART3_TX ART3_RX nterface n UART3 fo or Meter In Description P Pin N D U UART Tran U UART Rece 58 122
(defined in smit eive n Modules s direction)
) UAR RT CONNEC CTION Figure 4 4: UART co onnection 2.2. 4
.5 USB USB link is available f for the AT command s and the t trace port. s interface eed (12Mbi e is complia it/s) specifi ant with the ications. e USB Hig h Speed (4 480Mbit/s)
) and USB Full 2.2. A U This spe Page 15 User manual of 3G SEP EVDO module If the USB feature is not used in the customers design, it is, however, strongly recommended to leave this interface accessible through test points for debug purposes. Signal USB_DP USB_DM USB Data Positive USB Data Negative Pin N Description 60 124 I2C Interface 2.2.6 I2C pins use GPIOs configured as open-drain outputs; the pull-up resistor is provided by the slave. Two-wire bus for inter-IC communications supporting any IC fabrication process. High-speed mode (3.4 Mbps) is not supported. 10-bit addressing is not supported. Fast mode plus (1 Mbps) is not supported. Note: The MDM supports fast mode up to 400 kbps. Signal I2C_SDA I2C_SCL Pin N Description 53 54 I2C serial data I2C serial clock JTAG Interface 2.2.7 Test ports for debug Figure 5: I2C connection Page 16 gnal Sig SM MPS3 K TAG_RTCK JT JT TAG_SRST T_N JT TAG_TCK JT TAG_TDI JT TAG_TDO JT TAG_TMS JT TAG_TRST T_N User manua al of 3G SEP EVDO modu ule n Modules s direction)
(defined in n clock for debug P Pin N D Description JT TAG VDD JT TAG return JT TAG reset k input JT TAG clock input JT TAG data output JT TAG data TAG mode e select inp JT JT TAG reset 29 30 96 93 94 31 95 32 put 2.2. 8 Seria e SPI allow The MC-3GSEP UM y of the fiv Any Sig gnal PI_MOSI SP PI_MISO SP SP PI_CS_N PI_CLK SP e al Interface al peripher al commu ws synchro onous seria and a pe eripheral, w with the M be configu orts can b ve GSBI p P Pin N D Description 4-
-pin SPI m 4-
-pin SPI m 4-
-pin SPI ch 4-
-pin SPI cl 66 65 2 4 unication MDM devi ured as a
(defined in master out/s master in/sl hip select ock between ce as the n SPI mas n Modules slave in ave out only. the e master o ter. s direction)
) Page 17 User manual of 3G SEP EVDO module Secure digital controller(sdc) ports 2.2.9 The MDM IC provides up to two SD interfaces, which provide the following features or functions:
Up to 25 MB/s data rate 1.8 V / 2.95 V dual-voltage operation on SDC1;
Interface with SD/MMC memory cards up to 2 TB 10k pullup resistor on command pin; placeholder pullups are recommended on the data lines also. SDC1 for HPGP/PLC Signal SDC1_CMD SDC1_CLK SDC1_DATA0 SDC1_DATA1 SDC1_DATA2 SDC1_DATA3 Secure digital controller 1 command Secure digital controller 1 clock Secure digital controller 1 data bit 0 Secure digital controller 1 data bit 1 Secure digital controller 1 data bit 2 Secure digital controller 1 data bit 3 48 46 47 112 111 110 Pin N Description 2.3 HIGH-SPEED INTER-CHIP (HSIC) INTERFACE Eliminates the analog transceiver from a USB interface for lower voltage operation and reduced power dissipation. HSIC_DATA HSIC_STB 69 72 HSIC data HSIC strobe 2.4 GENERAL PURPOSE I/O There are GPIO that can be customized easily from the customers application Page 18 User manual of 3G SEP EVDO module through appropriate AT commands and they can be configured as input or output:
2.5 RESET One reset input pin is available to reset the module in case of undesirable behavior and internal pull up 1.8V with 40K ohm. Signal PERST_N Pin N 97 Description Low level active input signal to reset the module 2.6 ADC ADC input pin is available to measure an external analog voltage through dedicated AT commands. Signal POWER_DETECT1 POWER_DETECT2 XO_THERM Pin N Description 34 99 35 Analog to digital converter input Analog to digital converter input Analog to digital converter input POWER OUTPUT This Voltage pin is the 3V power supply for the peripheral. Signal LDO4 Pin N Description 3V Power supply 39 2.7 POWER SUPPLY & GND 3G SEP power supply & Ground pins. High input voltage range: 3.4 V to 4.2 V. Page 19 User manual of 3G SEP EVDO module Description Pin9/10 (for RF power) Pin37/38/102/103 (for Baseband power) Ground pins Signal VPH_PWR GND Pin N 9,10, 37,38,102,103 5,8,11,12,14,15,20,22,2 5,28,33,36,40,45,51,55, 61,69,72-157 2.8 POWER MANAGEMENT 2.9 SLEEP MODES There are two kinds of sleep modes, the off mode and stand-by mode as described below:
Off mode 2.9.1 When the module is in the off mode it cannot receive any calls or receive any AT commands but can be awakened by using PWON signal. Stand-by Mode Management 2.9.2 There are three stand-by mode management controls:
AT+KSLEEP=0 In this mode the sleep state is controlled by the host DTR and by the firmware:
- DTR = 1 - The module never enters into the sleep mode
- DTR = 0 - The module enters the sleep mode when it is ready and cannot be awakened with an AT command. To wake up the module the user must toggle DTR to 1. Remarks: Even in this mode it is possible to use DTR signals to go from the data mode to the command mode. However, in this case, DTR has to be toggled from 1 to 0 then from 0 to 1. AT+KSLEEP=1 In this mode the sleep mode state is only controlled by the firmware. The module enters the sleep mode when it is ready. The module may be Page 20 User manual of 3G SEP EVDO module awakened with any character received on the UART. However, to be sure to awaken the module, the 0x00 character must be sent. The main interest of the AT+KSLEEP=0 mode is to be able to forbid the sleep mode from using the DTR signal. AT+KSLEEP=2 In this mode the sleep state is never authorized in any DTR state. Detailed descriptions of these modes are given in. Power consumption 2.9.3 The power supply input of ranges from 3.4V to 4.2V and 4V is nominal. All measurements in the communication mode are done at the maximum RF power transmission (PCL max). Off mode Stand-by mode connected to the network (cell power -55dBm/1.23MHz) C2K 1X TX: Maximun power EVDO data mode TX: Maximun power All band All band
-30C Typ. 25C Typ. 50 A Max 100 A
+85C Typ. 150mA 150mA 200mA 150mA 700mA 700mA 780mA 700mA 680mA 680mA 750mA 680mA Page 21 User manual of 3G SEP EVDO module 2.10 RTC FUNCUTION One reset input pin is available to reset the module in case of undesirable behavior and internal pull up 1.8V with 40K ohm. Signal PERST_N Pin N 97 Description Low level active input signal to reset the module Page 22 3. PINOUT User manual of 3G SEP EVDO module 3.1 I/O CONNECTOR PIN ASSIGNMENTS Pin number Category 9 10 37 38 102 103 39 48 46 47 112 111 110 108 42 107 43 VPH_PWR
(4V / 3A) 3V Power for peripheral
(3.075V /
300mA) SDC1 for HPGP/PLC
(SDC1=2.9 5V) SDC2 for Wi-fi
(1.8V) 3G SEP pin definitions RF_VPH_PWR1 RF_VPH_PWR2 BB_VPH_PWR1 BB_VPH_PWR2 BB_VPH_PWR3 BB_VPH_PWR4 MDM9615 pad PM8018 pad name name 104: VDD_S1 LDO4 84: VREG_L4 SDC1_CMD W21: SDC1_CMD SDC1_CLK W23: SDC1_CLK SDC1_DATA0 SDC1_DATA1 SDC1_DATA2 SDC1_DATA3 SDC2_CMD SDC2_CLK SDC1_DATA_0 SDC1_DATA_1 SDC1_DATA_2 W22:
V21:
V22:
V23:
SDC1_DATA_3 AA21: GPIO_29 AC22: GPIO_30 SDC2_DATA0 AB21: GPIO_25 SDC2_DATA1 AB22: GPIO_26 Page 23 Pad type 4V/3A 4V/3A 4V/3A 4V/3A 4V/3A 4V/3A 3.075V /
0.3A B DO B B B B B-PD BH-PD,
/INT B-PD BH-PD,
/INT 44 106 105 41 83 82 81 18 19 62 63 64 126 128 1 127 120 57 56 121 58 122 59 User manual of 3G SEP EVDO module SDC2_DATA2 AA22: GPIO_27 SDC2_DATA3 WLAN_PWR_DO WN AC21: GPIO_28 Y3: GPIO_72 SDC2_GPIO W3: GPIO_73 CAPGOOD M5: GPIO_59 RAD_DC_ON PLC_DC_ON EN_CHG R2: GPIO_60 N1: GPIO_61 AA1: GPIO_32 POWER_FAIL V5: GPIO_45 UART1_TX B7: GPIO_11 UART1_RX A7: GPIO_10 UART1_CTS UART1_RFR ZB_RESET ZB_PA5 ZB_PC6 A6: GPIO_9 B6: GPIO_8 J5: GPIO_67 M2: GPIO_68 H5: GPIO_69 Power Control
(1.8V) 4-pin UART1 for EM357 Zigbee
(1.8V) UART2_TX A12: GPIO_15 2-pin UART2 for UART2_RX A10: GPIO_14 PLC
(1.8V) PLC_RESET E12: GPIO_17 PLC_EN A9: GPIO_16 2-pin UART3 for Meter Interface UART3_TX B12: GPIO_19 UART3_RX C11: GPIO_18 8215_EPF M1: GPIO_62 Page 24 BH-PD,
/INT BH-PD,
/INT B-PD B-PD BH-PD,
/INT B-PD B-PD B-PD BH-PD,
/INT BH-PD,
/INT BH-PD,
/INT B-PU B-PD B-PD B-PD,
/INT BH-PD,
/INT BH-PD,
/INT BH-PD,
/INT BH-PU,
/INT B-PU BH-PU,
/INT BH-PD,
/INT B-PD
(1.8V) I2C for Accelerome ter or LCM
(1.8 V) USB for Debug Port JTAG for Debug Port
(JTAG Power:
1.8V) SPI for 53 54 52 117 118 55 25 60 124 29 30 96 93 94 31 95 32 66 65 2 4 3 68 User manual of 3G SEP EVDO module I2C_SDA I2C_SCL B9: GPIO_13 C8: GPIO_12 I2C_RESET M3: GPIO_82 I2C_INT J3:GPIO_84 TILT_INT J1: GPIO_80 B-PD B-PU BH-PD,
/INT BH-PD,
/INT BH-PD,
/INT AI, AO USB_HS_ID 5V_BOOST_EN F9: USB_HS_ID 60: GPIO_04 USB_HS_DP USB_HS_DM C9: USB_HS_DP E9: USB_HS_DM SMPS3 42: VSW_S3 JTAG_RTCK JTAG_SRST_N JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS AC4: RTCK W6: SRST_N AC3: TCK AC5: TDI AB5: TDO AA5: TMS JTAG_TRST_N AA6: TRST_N SPI_MOSI E3: GPIO_7 SPI_MISO D2: GPIO_6 Water/GAS SPI_CS_N E2: GPIO_5 AMR
(1.8V) SPI_CLK G5: GPIO_4 ISM_IRQ G1: GPIO_78 ISM_RESET_N N3: GPIO_64 AI, AO AI, AO 1.8V /
1.5A DO DISH-PU DIS-PU DIS-PU DO-Z DIS-PU DISH-PD BH-PU,
/INT BH-PD,
/INT BH-PD,
/INT BH-PD,
/INT BH-PD ,/I NT B-PD Page 25 67 27 90 26 91 97 17 34 99 35 24 88 87 23 7 71 6 70 UIM for SIM Card Socket
(1.8V or 2.85V ) Power reset
(1.8V) Heater
(1.8V) ADC_IN Scaling 1
(0.1 to 1.7V) Scaling 1/3
(0.3 to VPH_PWR) LEDs
(1.8V) Other GPIOs
(1.8V) B-PD BH-PU,
/INT BH-PD,
/INT BH-PD,
/INT 1.8 or 2.85V /
0.15A User manual of 3G SEP EVDO module ISM_CC1190_HG M L3: GPIO_65 UIM1_DATA E1: GPIO_3 UIM1_CLK C3: GPIO_2 UIM1_RESET F3: GPIO_1 LDO6 PERST_N HTR_ON POWER_DETECT POWER_DETECT 1 2 XO_THERM LED0_GREEN LED0_RED LED1_GREEN LED1_RED 17: VREG_L6 16: RESIN_N 1.8V 50:GPIO_03 85: MPP_01 AO-Z 67: MPP_02 AO-Z 73: MPP_05 AO-Z W5:GPIO_35 W2:GPIO_38 W1: GPIO_39 60: GPIO_04 B-PD B-PD B-PD B-PD BH-PD ,/I NT BH-PD,
/INT B-PD BH-PD,
/INT BH-PD,
/INT ANT_SEL MAG_SW P2: GPIO_63 K3: GPIO_77 LIMIT_SW AB1:GPIO_40 GPS_LNA_EN K5: GPIO_66 114 50 I2S/PCM Analog Audio for I2S_MCLK C13: GPIO_24 I2S/PCM_TX A13: GPIO_23 Page 26 115 49 113 100 33 75 69 72 5 8 11 12 14 15 20 22 28 36 40 45 51 61 73 74 76 User manual of 3G SEP EVDO module Alarm
(1.8V) I2S/PCM_RX B13: GPIO_22 I2S_WS/PCM_SY NC E13: GPIO_21 I2S/PCM_CLK C12: GPIO_20 BH-PU,
/INT B-PD BH-PD,
/INT VCOIN for RTC for SW download VCOIN DOWNLOAD 57: VCOIN 49: GPIO_06 HSIC HSIC_READY G2: GPIO_79 HSIC_DATA HSIC_STB C2: HSIC_DATA C1: HSIC_STB GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND BH-PD,
/INT Page 27 77 78 79 80 84 85 86 89 92 98 101 104 109 116 119 123 125 129 130 131 132 133 134 135 136 137 138 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND User manual of 3G SEP EVDO module Page 28 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 13 16 21 User manual of 3G SEP EVDO module GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND RF RF_MAIN RF_DRX RF_GPS Page 29 User manual of 3G SEP EVDO module 4. ELECTRICAL SPECIFICATIONS Five system operating states are defined:
NO SUPPLY: No power voltage is present. OFF: Main power voltage is present. ACTIVE: Main power voltage is present Internal power supplies are on. SLEEP: Main power voltage is present Internal power supplies are in the low power mode. If not specified, all electrical values are given for the active state at VPH_PWR=4.0V and an operating temperature of 25C.
Min. Name VPH_PWR (*) VPH_PWR (*) Typ. Max. 4.1 VPH PWR The module is supplied through the VPH_PWR with the following characteristics:
Parameter VPH_PWR maximum voltage (V) VPH_PWR minimum voltage
(V) VPH_PWR drop voltage
(mV) Transient voltage (V) Noise level
(Vrms)@100KHz-1MHz
* See Application Notes for more details.
** This value depends on the power supply serial resistor (plus contact and track serial resistors)
50mV DeltaVbat (*) 300 (**) TBD 4.2 3.4
4.2 VBACKUP Parameter Voltage level(V) Min. 1.2 Typ. Max
. 3.25 3 Remarks Page 30 4.3 VSIM Parameter Output Voltage(V) User manual of 3G SEP EVDO module Min. 2.7 Typ. Max
. 3.15 3 1.65 1.80 1.95 Remarks The appropriate output voltage is auto detected and selected by software. IOUT = MAX Output Current (mA) Line Regulation (mV/V) Power-up Setting Time (us) from power down
10 150 50
10 10 10 Min. Typ. Max. Remarks
-10
-10
4.4 DIGITAL INTERFACE The digital interface has the following characteristics, which includes UART, PCM/I2S,I2C, GPIOs, SPI and SDIO. Parameter Input Current-High(A) Input Current-Low(A) DC Output Current-High(mA) (1) DC Output Current-Low(mA) (1) Input Voltage-High(V) Input Voltage-Low(V) Output Voltage-High(V) Output Voltage-Low(V)
(1) The maximum current for one GPIO is 10mA. 1.7
-0.3 1.7 0 2.0 0.3 2.0 0.3 Pin driving a "1" with output set at "0"
Pin driving a "0" with output set at "1"
-10
4.5 RESET The RESET signal has the following characteristics:
Parameter Min. Typ. Max
. Page 31 User manual of 3G SEP EVDO module Input Voltage-Low (V) Input Voltage-High(V) Power up Period (ms) from RESET falling edge
-0.3 1.2 20 0 1.8
0.3 2.1
4.6 SIM Signal SIM_RST SIM_CLK SIM_DATA VL (V) VH (V) Min. Max. Fully compliant to the GSM11.11 and ISO/IEC 7816-3 standards Max. Min. I2C INTERFACE I2C HAS THE FOLLOWING CHARACTERISTICS:
Applicable standard Feature exceptions I2C Specification, version 2.1, January 2000 (Phillips Semiconductor document number 9398 393 40011)
.High-speed mode (3.4 Mbps) is not supported. 10-bit addressing is not supported. Fast mode plus (1 Mbps) is not supported. Note: The MDM supports fast mode up to 400 kbps MDM variations None 4.7 USB USB signals have the following characteristics:
Signal VL (V) VH (V) USB_HS_DP USB_HS_DM USB_HS_VBUS Min 0 0 0 Max 0.3 0.3 0.3 Min
2.0 Max 5.25 5.25 5.25 4.8 ADC The ADC has the following characteristics. Affiliate PMIC Typical input (V) Scaling Typical output (V) Page 32 pins/function MPP_XX (selectable) MPP_XX (selectable) User manual of 3G SEP EVDO module 0.1 to 1.7 0.3 to VPH_PWR 1 1/3 0.1 to 1.7 0.1 to 1.7 4.9 UART TX, RX, CTS, and RFR have the following characteristics:
Signal VL (V) UART_TX UART_RX UART_RFR UART_CTS Min
-0.3
-0.3
-0.3
-0.3 Max 0.4 0.4 0.4 0.4 Min 1.5 1.5 1.5 1.5 VH (V) Max 2.1 2.1 2.1 2.1 4.10 SPI The SPI allows duplex (or half-duplex) and synchronous serial communication between a master and a slave. 3G SEP can be configured as an SPI master or slave mode. Figure 8: SPI in the master mode Parameter 1/T T t(ch) t(cl) Comments Minimum Maximum Unit SPI clock frequency SPI clock period Clock high Clock low
38 0.45xT 0.45xT 26
0.55xT 0.55xT MHz ns ns ns Page 33 t(mov) t(mis) t(moh) t(tse) t(tsd) User manual of 3G SEP EVDO module Master output data uncertainty Master input setup Master output hold Tri-state enable Tri-state disable
-5 0 0
-5
-5 5 3 3 5 5 ns ns ns ns ns Figure 9: SPI in the slave mode Comments Minimum Maximum SPI clock frequency Clock high Clock low Slave output data uncertainty Slave input setup Slave input hold
0.45xT 0.45xT 0 1.5 1.5 26 0.55xT 0.55xT 15.8
Unit MHz ns ns ns ns ns Parameter 1/T t(ch) t(cl) t(sov) t(sis) t(sih) 4.11 SDIO Only supports the master mode. Page 34 User manual of 3G SEP EVDO module Figure 10: SDIO timing Single data rate (SDR) 1 Parameter t(chrd) t(csurd) t(dhrd) t(dsurd) t(pddwr) t(pdcwr) Comments Command hold Command setup data hold Data setup Propagation delay on data write Propagation delay on command write Minimum Maximum Unit ns 2.5 6.0 2.5 5.0
-7
-7 3 3 ns ns ns ns ns Double data rate (DDR) 2 Parameter t(chrd) Comments Command hold Minimum Maximum Unit ns 1.5 t(csurd) t(dhrd) t(dsurd) t(pddwr) Command setup data hold Data setup Propagation delay on data write 12.3 1.5 4.7 0.8 8.7 Page 35 ns ns ns ns User manual of 3G SEP EVDO module t(pdcwr) Propagation delay on
-10.9 5.7 ns command write 4.12 HIGH-SPEED INTER-CHIP (HSIC) INTERFACE High-Speed Inter-Chip USB Electrical Specification, version 1.0 (a supplement to the USB 2.0 specification, 4.13 DIGITAL AUDIO THE AUDIO OUTPUTS CONTAIN THE FOLLOWING CHARACTERISTICS:
Parameter Maximum input range Maximum output range Typ Max 2.1 1.8V 1.8V 2.1 Min 1.6 1.6 4.14.1 I2S Interface The I2S interface signaling and timing is identical, regardless of whether I2S is selected as the mode of operation for the primary and/or secondary audio interface. Applicable standard Feature exceptions Phillips I2S Bus Specifications, revised No external controller support MDM variations None June 5, 1996 Figure 11: I2S transmitter timing diagram Page 36 User manual of 3G SEP EVDO module Parameter Condition T Clock period I2S requirement: min T = 293 Min Typ Max Unit ns 293 326 359 t(hc) t(lc) t(dtr) t(htr) Clock high Clock low Delay Hold time I2S requirement: min > 0.35T I2S requirement: min > 0.35T I2S requirement: max < 0.8T I2S requirement: min > 0 120 120 100 250 ns ns ns ns Figure 12: I2S receiver timing diagram Parameter Condition T Clock period I2S requirement: min T = 293 Min Typ Max Unit 293 ns 326 359 t(hc) t(lc) t(sr) t(htr) Clock high Clock low Setup time Hold time I2S requirement: min < 0.35T = 103 I2S requirement: min < 0.35T = 103 I2S requirement: min < 0.2T = 59 I2S requirement: min < 0 100 100 40 0
ns ns ns ns 4.14.2 PCM Interface 4.14.2.1 Primary (short sync) PCM interface (2048 kHz clock) Figure 13: PCM_SYNC timing Page 37 User manual of 3G SEP EVDO module Figure 14: PCM_CODEC to MDM timing Figure 15: MDM to PCM_CODEC timing Parameter Condition t(sync) PCM_SYNC cycle time t(synca) t(syncd) t(clk) t(clkh) t(clkl) t(sync_o ffset) t(sudin) t(hdin) PCM_SYNC asserted time PCM_SYNC de-asserted time PCM_CLK cycle time PCM_CLK high time PCM_CLK low time PCM_SYNC offset time to PCM_CLK falling PCM_DIN setup time to PCM_CLK falling PCM_DIN hold time after PCM_CLK falling Mi n
60 60 Typ Max Unit 125 488 124.5 488 244 244 122
us ns us ns ns ns ns ns ns Page 38 User manual of 3G SEP EVDO module t(pdout) Delay from PCM_CLK rising to PCM_DOUT valid t(zdout) Delay from PCM_CLK falling to PCM_DOUT HIGH-Z
60 60 ns ns 4.14.2.2 Auxiliary (long sync) PCM interface (128 kHz clock) Figure 16: AUX_PCM_SYNC timing Figure 17: AUX_PCM_CODEC to MDM timing Figure 18: MDM to AUX_PCM_CODEC timing Parameter Condition t(auxsync) AUX_PCM_SYNC cycle time t(auxsynca) AUX_PCM_SYNC asserted time Min Typ Max Unit us 125
62.4 62.5
us Page 39 User manual of 3G SEP EVDO module t(auxsyncd) t(auxclk) t(auxclkh) t(auxclkl) t(suauxsync) AUX_PCM_SYNC setup time to AUX_PCM_SYNC de-asserted time AUX_PCM_CLK cycle time AUX_PCM_CLK high time AUX_PCM_CLK low time t(hauxsync) t(suauxdin) t(hauxdin) t(pauxdout) AUX_PCM_CLK rising PCM_SYNC hold time after AUX_PCM_CLK rising AUX_PCM_DIN setup time to AUX_PCM_CLK falling AUX_PCM_DIN hold time after AUX_PCM_CLK falling Delay from AUX_PCM_CLK to AUX_PCM_DOUT valid 62.4
3.8 3.8 1.95 1.95 70 20
62.5 7.8 3.9 3.9
50 us us us us ns ns ns ns ns 4.14 RF SIGNAL 4.14.1 Load mismatch The module accepts a VSWR < 20:1 (all phase angles) without damage or permanent degradation. The module accepts a VSWR < 12:1 (all phase angles) without any spurious emission > - 30 dBm. Input VSWR 4.14.2 The typical input VSWR is 1.5:1 (max = 1.5:1). 4.14.3 Antenna matching network A matching network in the UMC-3GSEP module is optimized for a 50 ohm work load. To obtain the best performance in an application, an additional matching circuit and adjustment for actual antenna is required. A -type matching network is recommended in the UMC-3GSEP Application Note. Page 40 User manual of 3G SEP EVDO module Max.
+70C
+85C Min.
-20C 5. ENVIRONMENTAL SPECIFICATIONS Parameter Ambient temperature Normal range Ambient temperature Extended range Storage temperature Long damp heat Operating conditions Short damp heat Storage and transportation conditions
-30C
+105C
-40C Tested at +60C, 95% RH during a 504 hour period Tested at +40C, 95% RH during a 96 hour period 5.1 NORMAL TEMPERATURE RANGE ETSI performances are guaranteed by WNC in the range of -20C to +70C. Conduct RX Sensitivity at the normal temperature range 5.1.1 Enhanced sensitivity performance at 25C is guaranteed as follow:
Frequency bands MAX CDMA 1x0.5% FER EVDO rev A0.5% PER CDMA 1x0.5% FER EVDO rev A0.5% PER
-107dBm
-107dBm
-107dBm
-107dBm BC0 BC1 3GPP2 C.S0033 min. standard
-104dBm
-105.5dBm
-104dBm
-105.5dBm Page 41 User manual of 3G SEP EVDO module Typical transmission values at normal temperature range 5.1.2 Typical transmission values is as below Frequency band BC0 class III BC1 class II Typ. 24dBm +/- 1dB 24dBm +/- 1dB 3GPP2 C.S0033 min. standard ERP 0.2 W EIRP 0.2 W 5.2 EXTENDED TEMPERATURE RANGE Typical Cellular sensitivity at extended temperature range 5.2.1 Frequency band Temperature (C) Typical sensitivity (dBm) Frequency band Temperature (C) Typical sensitivity (dBm) BC0 BC1
-30
(TBD)
-30
(TBD)
+85
(TBD)
+85
(TBD) 3GPP2 C.S0033 min. standard
< -105.5dBm 3GPP2 C.S0033 min. standard
< -105.5dBm Page 42 User manual of 3G SEP EVDO module 6. FCC WARNING STATEMENT 6.1 GENERAL This manual is limited to OEM/Integrators installation only. OEM integrators are responsible for ensuring that the end-user has no manual instructions to remove or install module. 6.2 END PRODUCT LABELING (FCC) When the module is installed in the host device, the FCC ID label must be visible through a window on the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a second label must be placed on the outside of the final device that contains the following text: Contains FCC ID: NKR96E1. The grantee's FCC ID can be used only when all FCC compliance requirements are met. FCC COMPLIANCE STATEMENT 6.3 REQUIRED INTEGRATION To integrate this module into the host, the host manufacturer is responsible for the applicable FCC rules, including the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. In the user manual of the host device, the following statements are required to be included. FOR HOST This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This device has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiated radio frequency energy and, if not installed and used in accordance with the instructions, may Page 43 User manual of 3G SEP EVDO module cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. Changes or modifications not expressly approved by the party responsible for compliance could void the users authority to operate the equipment. 6.4 FCC MODULE INTEGRATION RESTRICTION:
This module has been certified by FCC as single module approval with the following restrictions:
1. The monopole antenna with 2.0 dBi gain was verified in the conformity testing. Radiated transmit power must be equal to or lower than that specified in the FCC Grant of Equipment Authorization for FCC ID: NKR96E1. A separate approval is required for all other operating configurations. 2. This module is limited to be installed in mobile or fixed application. To assure RF Exposure compliance, the antenna used with this module should be installed and operated with minimum distance 20 cm from all persons and must not transmit simultaneously with any other antenna or transmitter, except in accordance with FCC multi transmitter product procedure. 3. If any other simultaneous transmission radio is installed in the host platform together with this module, or above restrictions cannot be kept, a separate RF exposure assessment and FCC equipment authorization is required. Page 44