FG160-NA Hardware Guide V1.1 Copyright Copyright 2022 Fibocom Wireless Inc. All rights reserved. Without the prior written permission of the copyright holder, any company or individual is prohibited to excerpt, copy any part of or the entire document, or transmit the document in any form. Notice The document is subject to update from time to time owing to the product version upgrade or other reasons. Unless otherwise specified, the document only serves as the user guide. All the statements, information and suggestions contained in the document do not constitute any explicit or implicit guarantee. The trademark is registered and owned by Fibocom Wireless Inc. Trademark Contact Website: https://www.fibocom.com/en/
Address: Floor 10, Building A, Shenzhen International Innovation Valley, First Stone Road, Xili Community, Xili Street, Nanshan District, Shenzhen Tel: +86 755-26733555 Contents Contents Applicable Model ............................................................................................... 6 Change History .................................................................................................. 7 1 Foreword ......................................................................................................... 8 1.1 Introduction .................................................................................................................... 8 1.2 Reference Standard ...................................................................................................... 8 1.3 Related Document ......................................................................................................... 9 2 Overview ........................................................................................................ 10 2.1 Introduction ................................................................................................................. 10 2.2 Specification ................................................................................................................. 10 2.2.1 RF Characteristic ................................................................................................... 10 2.2.2 Key Features .......................................................................................................... 12 2.3 Application Framework .............................................................................................. 13 2.4 Antenna Configuration .............................................................................................. 14 2.5 Waring ........................................................................................................................... 16 2.5.1 Important Notice to OEM integrators ............................................................. 16 2.5.2 FCC Statement ...................................................................................................... 18 3 Pin Definition ................................................................................................ 20 3.1 Pin Assignment ............................................................................................................ 20 3.2 Pin Definition ................................................................................................................ 21 4 Electrical Characteristics ............................................................................. 35 4.1 Recommended Operating Conditions .................................................................. 35 4.2 I/O Logic Characteristics ........................................................................................... 36 4.3 Power Consumption .................................................................................................. 36 4.4 Radio Frequency ......................................................................................................... 39 4.4.1 Transmitting Power ............................................................................................. 39 4.4.2 Dual Antenna Receiver Sensitivity .................................................................... 41 4.4.3 Four Antenna Receiver Sensitivity .................................................................... 43 4.4.4 GNSS ........................................................................................................................ 44 4.4.5 Operating Band .................................................................................................... 45 Copyright Fibocom Wireless Inc. 3 Contents 4.4.6 Antenna Requirements ....................................................................................... 47 5 Interface Introduction ................................................................................. 48 5.1 Power ............................................................................................................................. 48 5.1.1 Power Supply ......................................................................................................... 48 5.2 Control Interface ......................................................................................................... 50 5.2.1 Normal Mode ........................................................................................................ 51 5.2.1.1 Module Start-up ............................................................................................. 51 5.2.1.2 Module Shutdown ......................................................................................... 53 5.2.1.3 Module Reset .................................................................................................. 54 5.2.2 PCIe EP Mode ........................................................................................................ 55 5.2.2.1 Module Start-up ............................................................................................. 55 5.2.2.2 Module Shutdown ......................................................................................... 57 5.2.2.3 Module Reset .................................................................................................. 57 5.3 Network Status Indicator Interface ........................................................................ 59 5.3.1 Interface Status Description (Reserved) ......................................................... 59 5.4 SIM Card Interface ...................................................................................................... 60 5.4.1 SIM Card Interface Definition ............................................................................ 60 5.4.2 SIM Card Interface Circuit .................................................................................. 61 5.5 USB Interface ............................................................................................................... 62 5.5.1 USB Interface Definition ..................................................................................... 62 5.5.2 USB Interface Circuit ........................................................................................... 63 5.5.3 USB Routing Rules ............................................................................................... 63 5.5.3.1 USB2.0 Routing Rules ................................................................................... 63 5.5.3.2 USB3.1 Routing Rules ................................................................................... 64 5.6 ADC Interface ............................................................................................................... 64 5.6.1 ADC Interface Definition ..................................................................................... 64 5.6.2 ADC Electrical Characteristics ............................................................................ 64 5.7 Forced-download Interface ...................................................................................... 65 5.7.1 Configuration Signal Interface Circuit ............................................................. 65 5.8 PCIE Boot Control Interface ..................................................................................... 65 5.9 Flight Mode Control Interface (Reserved)............................................................. 66 Copyright Fibocom Wireless Inc. 4 Contents 5.10 GPIO Interface ........................................................................................................... 66 5.11 PCIE Interface ............................................................................................................ 67 5.11.1 PCIe Interface Definition .................................................................................. 67 5.11.2 PCIE Routing Rules ............................................................................................ 68 5.11.3 PCIE Application Circuit .................................................................................... 68 5.12 SD Interface ............................................................................................................... 68 5.12.1 SD Interface Definition ..................................................................................... 68 5.12.2 SD Interface Routing Rules.............................................................................. 69 5.12.3 SD Interface Application Design .................................................................... 69 5.13 I2C Interface .............................................................................................................. 69 5.14 I2S Interface ............................................................................................................... 70 5.15 UART Interface .......................................................................................................... 70 5.16 SPI Interface .............................................................................................................. 72 5.17 Other Interfaces........................................................................................................ 72 6 Electrostatic Protection ............................................................................... 73 7 Thermal Design ............................................................................................ 74 8 Structural Specification ............................................................................... 75 8.1 Product Appearance .................................................................................................. 75 8.2 Dimension of Structure ............................................................................................. 75 8.3 Storage .......................................................................................................................... 76 8.4 Packing .......................................................................................................................... 76 Copyright Fibocom Wireless Inc. 5 Applicable Model Applicable Model No. Applicable Model Description 1 FG160-NA-00 North America version of the 5G communication module which for varieties of eMBB scenarios Copyright Fibocom Wireless Inc. 6 Change History Change History V1.1 (2022-08-11) Chapter 2.2.2, delete support PCIe 4.0 information. Chapter 2.2, add LTE B7, NR N7/N78 and description, updated NSA DL peak rate. Chapter 2.4, add B7/N7/N78 antenna configuration Chapter 4.4, add B7/N7/N78 transmitting power and receiver sensitivity, update 3GPP requirement and note. Chapter 3.2, updated the pin definition of mmW part in Table 7 Chapter 5.1.1 updated the Power supply voltage drop diagram in Figure 4 Chapter 5.2.2, add control sequence about FG160 is configured as PCIe EP mode Chapter 5.8, add PCIe boot control interface chapter Chapter 8.2, updated dimension of structure in Figure 21 V1.0 (2022-02-14) Initial version Copyright Fibocom Wireless Inc. 7 1 Foreword 1 Foreword 1.1 Introduction The document describes the electrical characteristics, RF performance, dimensions and application environment, etc. of FG160-NA-00 (hereinafter referred to as FG160). With the assistance of the document and other instructions, the developers can quickly understand the hardware functions of FG160 modules and develop products. 1.2 Reference Standard The design of the product complies with the following standards:
3GPP TS 38.300 V16.7.0: 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; NR; NR and NG-RAN Overall Description; Stage 2 3GPP TS 38.521-1 V16.7.0: User Equipment (UE) conformance specification; Radio transmission and reception; Part 1: Range 1 Standalone 3GPP TS 38.521-3 V16.7.0: User Equipment (UE) conformance specification; Radio transmission and reception; Part 3: Range 1 and Range 2 Interworking operation with other radios 3GPP TS 34.121-1 V10.8.0: User Equipment (UE) conformance specification; Radio transmission and reception (FDD); Part 1: Conformance specification 3GPP TS 34.122 V11.13.0: Technical Specification Group Radio Access Network; Radio transmission and reception (TDD) 3GPP TS 36.521-1 V16.7.0: User Equipment (UE) conformance specification; Radio transmission and reception; Part 1: Conformance testing 3GPP TS 21.111 V10.0.0: USIM and IC card requirements 3GPP TS 51.011 V4.15.0: Specification of the Subscriber Identity Module -Mobile Equipment (SIM-ME) interface Copyright Fibocom Wireless Inc. 8 1 Foreword 3GPP TS 31.102 V10.11.0: Characteristics of the Universal Subscriber Identity Module
(USIM) application 3GPP TS 31.11 V10.16.0: Universal Subscriber Identity Module (USIM) Application Toolkit(USAT) 3GPP TS 36.124 V10.3.0: Electro Magnetic Compatibility (EMC) requirements for mobile terminals and ancillary equipment 3GPP TS 27.007 V10.0.8: AT command set for User Equipment (UE) 3GPP TS 27.005 V10.0.1: Use of Data Terminal Equipment - Data Circuit terminating Equipment (DTE - DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS) PCI Express Base Specification Revision 3.0 Universal Serial Bus 3.1 Specification 1.3 Related Document FIBOCOM Design Guide_RF Antenna Copyright Fibocom Wireless Inc. 9 2 Overview 2 Overview 2.1 Introduction The FG160 series module is a 5G module which supports NSA and SA network architectures. The FG160 integrates core devices such as Baseband, Memory, PMU, Transceiver, and PA. It supports 5G NR Sub6, FDD-LTE and TDD-LTE long-distance communication modes. Supports uplink 22 MIMO and downlink 44 MIMO multi-antenna configuration in SA mode. It also supports GNSS wireless positioning technology. The FG160 is designed in an LGA package and is suitable for a variety of eMBB scenarios, such as CPE, VR/AR, gateway, TV box, and intelligent monitoring. 2.2 Specification 2.2.1 RF Characteristic Table 1. Operating bands Model FG160-NA FDD-LTE Band 2/4/5/7/12/13/29/30/66/71 TDD-LTE Band 41/48/46LAA SA NSA n2/5/7/12/14/25/30/41/48/66/70/71/77/78 n2/5/7/12/25/30/41/66/71/77/78 GNSS GPS/GLONASS/Galileo/BDS/QZSS Table 2. Data throughput Model FG160-NA LTE DL peak rate 1.6Gbps (CAT19) UL peak rate 211Mbps (CAT18) Copyright Fibocom Wireless Inc. 10 2 Overview DL 44 MIMO (Support Band B2/4/5/7/12/13/30/41/48/66/71) DL peak rate 3.66Gbps UL peak rate 555Mbps NSA DL 44 MIMO LTE (Support Band B2/4/5/7/12/13/30/41/48/66) DL 44 MIMO NR (Support Band n2/5/7/25/30/41/66/71/77/78) DL peak rate 2.47Gbps UL peak rate 900Mbps SA DL 44 MIMO (Support Band n2/5/7/12/14/25/30/41/48/66/70/71/77/78) UL 22 MIMO (n41/77/78) Table 3. Modulation characteristic Model FG160-NA Support max DL 5CA Support max UL 2CA LTE Support 3GPP R16 Support DL 256-QAM, UL 256-QAM Support RF bandwidth 1.4MHz20MHz Support max DL LTE 4CA + NR 1CA Support max DL LTE 4CA + NR 2CA (reserved) NSA Support max UL LTE 1CA + NR 1CA LTE Modulation: DL-256QAM, UL-256QAM NR Modulation: DL-256QAM, UL-256QAM SA Support max DL 2CA Copyright Fibocom Wireless Inc. 11 2 Overview Support max UL 2CA Support DL 256QAM, UL 256QAM Support RF bandwidth 5MHz100MHz Support carrier spacing 15KHz (FDD) and 30KHz (TDD) SRS antenna SA: 2T4R switching NSA: 1T4R 1T2R 2.2.2 Key Features Table 4. Key features Performance Description Power Supply DC: 3.3-4.4V, typical voltage: 3.8V Normal operating temperature: 30 to 751 Temperature Extended operating temperature: 40 to 852 Storage temperature: 40 to 85 Dimension: 41 44 2.75 mm Physical Characteristics Package: 392 pin LGA Weight: about 12g CPU Qualcomm SDX62, 7nm process, ARM Cortex-A7, up to 1.5 GHz Memory 8Gb LPDDR4x + 8Gb NAND Flash Interface USB2.0 high speed (HS) interface, data transmission rate up to USB Interface 480Mbps USB3.1 Gen2 Super-speed (SS) interface, data transmission rate up to Copyright Fibocom Wireless Inc. 12 2 Overview 10Gbps PCIe Interface PCIe Gen3, x2 lanes Dual SIM: 1.8V/3V SIM Interface SIM1: USIM SIM2: USIM/eSIM I2C interface x2 Two A/D conversion channel USB Linux I2Cs ADCs Software Firmware update Operating System 1. When temperature keeps in the range of 30 to 75C, module can work normally. Module performance meets the 3GPP specifications. 2. When temperature keeps in the range of 40 to 85C, module performance may be slightly out of 3GPP specifications. 2.3 Application Framework The application framework below shows the main hardware functions of the FG160 module:
Baseband RF transceiver PMU Copyright Fibocom Wireless Inc. 13 2 Overview Memory Peripheral interface ANT_1 ANT_2 ANT_3 ANT_4 ANT_5 ANT_6 ANT_7 ANT_8 GNSS TRx-mmW VBAT APT TRX Blocks TX RX RFFE ADCs PMU Transceiver x 2 Transceiver x 1
(mmW) MCP LPDDR4X NAND RFFE QLINK RFFE QLINK EBI0 EBI2 SPMI Baseband PWRKEY RESET_N CTL/CLOCK RFCLK--76.8MHz BBCLK--19.2MHz Sleep CLK--32KHz RFCLK 76.8MHz 76.8MHz XO eSIM USIM1 USIM2 JTAG GPIO
/EINT Co-ex UART SDIO RFFE SPI I2C I2S PCIe4.0 USB2.0
/3.1 UART Figure 1. Hardware block diagram 2.4 Antenna Configuration The FG160 supports eight NR/LTE antennas and one GNSS antenna. The antenna interface is defined as shown in the following table. Table 5. Antenna configuration Pin Function Band Configuration Band Configuration Frequency Name Description
(TX) ANT_1 Reserved
ANT_2 Secondary TX B5
/ MIMO PRX n5
(RX)
B5/12/13/71 n5/12/14/71 Range (MHz)
617-960 Main TX / PRX B2/4/7/30/66/41/48 B2/4/7/30/66/41/48 1427-2690 Copyright Fibocom Wireless Inc. 14 2 Overview Pin Function Band Configuration Band Configuration Frequency Name Description
(TX)
(RX) Range (MHz) n2/7/25/30/41/48/6 n2/7/25/30/41/48/66/
3300-4200 6/70/77/78 70/77/78 5150-5925 ANT_3 Reserved ANT_4 MIMO DRX DRX
B5/12/13/71 617-960 n5/12/14/71 B2/4/7/30/66/41 1427-2690 n2/7/25/30/41/66/70 MIMO PRX
B48 3300-4200 PRX ANT_5 Reserved ANT_6 DRX
n48/77/78 B46
5150-5925
B5/12/13/29/46/71 617-960 n5/12/14/71 5150-5925 MIMO DRX
B2/4/7/30/66/41/48 1427-2690 n2/7/25/30/41/48/66/
3300-4200 70/77/78 ANT_7 Reserved
ANT_8 Main TX / PRX B5/12/13/71 B5/12/13/29/71 617-960 n5/12/14/71 n5/12/14/71 Secondary TX B2/4/41/66 B2/4/7/30/41/66 1427-2690
MIMO PRX n2/25/41/66 n2/7/25/30/41/66/70 Secondary TX n48/77/78 B48 3300-4200 Copyright Fibocom Wireless Inc. 15 2 Overview Pin Function Band Configuration Band Configuration Frequency Name Description
(TX)
(RX) Range (MHz)
/ DRX n48/77/78 ANT_10 GNSS
GNSS receive 1559-1607 2.5 Waring 2.5.1 Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.31 (h) and (k): The host manufacturer is responsible for additional testing to verify compliance as a composite system. When testing the host device for compliance with Part 15 Subpart B, the host manufacturer is required to show compliance with Part 15 Subpart B while the transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation should confirm that the module's intentional emissions are compliant (i.e. fundamental and out of band emissions). The host manufacturer must verify that there are no additional unintentional emissions other than what is permitted in Part 15 Subpart B or emissions are complaint with the transmitter(s) rule(s). The Grantee will provide guidance to the host manufacturer for Part 15 B requirements if needed. Important Note notice that any deviation(s) from the defined parameters of the antenna trace, as described by the instructions, require that the host product manufacturer must notify to Fibocom Wireless Copyright Fibocom Wireless Inc. 16 2 Overview Inc. that they wish to change the antenna trace design. In this case, a Class II permissive change application is required to be filed by the USI, or the host manufacturer can take responsibility through the change in FCC ID
(new application) procedure followed by a Class II permissive change application. End Product Labeling When the module is installed in the host device, the FCC ID label must be visible through a window on the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a second label must be placed on the outside of the final device that contains the following text: Contains FCC ID: ZMOFG160NA The FCC ID can be used only when all FCC compliance requirements are met. Antenna Installation
(1) The antenna must be installed such that 20 cm is maintained between the antenna and users,
(2) The transmitter module may not be co-located with any other transmitter or antenna.
(3) Only antennas of the same type and with equal or less gains as shown below may be used with this module. Other types of antennas and/or higher gain antennas may require additional authorization for operation.
(4)The max allowed antenna gain is 3.76dBi for external monopole antenna. In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC authorization is no longer Copyright Fibocom Wireless Inc. 17 considered valid and the FCC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product
(including the transmitter) and obtaining a separate FCC authorization. 2 Overview Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. 2.5.2 FCC Statement Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:
- Reorient or relocate the receiving antenna.
- Increase the separation between the equipment and receiver. Copyright Fibocom Wireless Inc. 18
- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
- Consult the dealer or an experienced radio/TV technician for help. 2 Overview Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. Radiation Exposure Statement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator & your body. Copyright Fibocom Wireless Inc. 19 3 Pin Definition 3 Pin Definition The FG160 module applies LGA interface with 392 pins. 3.1 Pin Assignment 5 9 1 D N G 3 9 1 1 _ T N A 0 9 1 D N G 7 8 1 D N G 4 8 1 2 _ T N A 1 8 1 D N G 8 7 1 D N G 5 7 1 3 _ T N A 2 7 1 D N G 9 6 1 D N G 6 6 1 4 _ T N A 3 6 1 D N G 0 6 1 D N G 7 5 1 5 _ T N A 4 5 1 D N G 1 5 1 D N G 8 4 1 6 _ T N A 5 4 1 D N G 2 4 1 D N G 9 3 1 7 _ T N A 6 3 1 D N G 3 3 1 D N G 4 9 1 D N G 1 9 1 D N G 8 8 1 D N G 5 8 1 D N G 2 8 1 D N G 9 7 1 D N G 6 7 1 D N G 3 7 1 D N G 0 7 1 D N G 7 6 1 D N G 4 6 1 D N G 1 6 1 D N G 8 5 1 D N G 5 5 1 D N G 2 5 1 D N G 9 4 1 D N G 6 4 1 D N G 3 4 1 D N G 0 4 1 D N G 7 3 1 D N G 4 3 1 D N G 2 9 1 D N G 9 8 1 O D T 6 8 1 K C T 3 8 1 I D T 0 8 1 C N 7 7 1 C N 4 7 1 C N 1 7 1 C N 8 6 1 X T _ 9 7 N E _ N 5 6 1 L W _ D D 2 V 1 _ V 8 9 2 7 9 2 N _ T S R S 6 9 2 S M T 5 9 2 N _ T S R T 4 9 2 C N 3 9 2 2 9 2 C N 1 9 2 N _ R _ L B C W P 0 9 2 2 6 1 L 2 V 1 _ W _ D D V L R T C _ W S X M P _ 9 5 1 N E _ _ G T O R W P 6 5 1 C N 3 5 1 E T U A P _ L M _ W A A L _ L X R _ 0 5 1 7 4 1 D N G 4 4 1 _ O T _ L I T _ X D 1 4 1 W S W _ O T _ X D S I T C _ L W 9 8 2 D N G 8 8 2 C N 7 8 2 _ A A L N E _ S A 6 8 2 C N 5 8 2 C N 4 8 2 D N G 3 8 2 2 8 2 299 300 3 01 302 3 03 304 3 05 306 307 308 309 3 10 311 3 12 313 3 14 315 316 317 318 3 19 320 3 21 322 3 23 324 325 326 327 328 3 29 330 331 3 32 333 334 335 336 337 3 38 339 340 3 41 342 343 344 345 346 3 47 348 349 3 50 351 352 353 354 3 55 356 3 57 358 3 59 360 361 362 363 3 64 365 3 66 367 3 68 369 370 371 372 3 73 374 3 75 376 3 77 378 379 380 381 3 82 383 3 84 385 3 86 387 388 3 92 G N D 196 G N D 199 A N T_1 0 202 G N D 205 N C 208 G N D 211 214 G N D 217 220 G N D 223 226 G N D 229 232 G N D 235 238 G N D 241 244 G N D 247 250 G N D 253 256 G N D 259 R E S E R V E D 262 G N D 264 V BA T_B B G N D 3 89 197 G N D 200 G N D 203 G N D 206 G N D 209 1 98 2 01 2 04 W L_E N 2 07 W L_W A K E B T_E N 2 10 212 N C 215 G N D 218 G N D 221 G N D 224 G N D 227 G N D 230 G N D 233 G N D 236 G N D 239 G N D 242 G N D 245 G N D 248 G N D 251 G N D 254 G N D 257 G N D 260 G N D 263 D P R _N 2 13 G N D 2 16 2 19 2 22 G N D 2 25 V D D _E X T_1V 8 2 28 G N D 2 31 V D D _W L _1V 9 2 34 G N D 2 37 2 40 2 43 2 46 2 49 A D C 0 2 52 A D C 1 2 55 V D D _W L _0V 9 2 58 G N D 2 61 V BA T_B B 3 91 G N D 132 G N D 130 A N T_8 127 G N D 124 G N D 121 N C 118 G N D 115 I2C _S D A 0 112 131 G N D 128 G N D 125 G N D 122 G N D 119 G N D 116 N C 113 110 I2C _S C L0 109 106 107 D A C _ P W R _E N 104 8 3 1 5 3 1 129 D B G _ U A R T_T X 126 D B G _ U A R T_R X 123 W P S 120 G P S _P P S 117 IR IG _B 114 111 W IFI_ S TA T U S 108 W W AN _ S TA T U S 105 102 C O _U A R T _R X I2S 0_D I 103 101 I2S 0_D O 99 I2S 0_B C K 100 C O _U A R T _T X 96 93 90 G N D 87 98 95 92 G N D 89 V B A T_R F C D C _ IN T 1_N 97 94 91 G N D 88 V B A T_R F 86 V B A T_R F 84 V B A T_R F 85 V B A T_R F 81 G N D 78 LC D _ P W R _E N 75 B O O T_ O P T IO N 72 N C 69 N C 66 P D _ B S U 3 6 B S U S S P X R _ D I _ B S U 2 6 B S U S S N X R _ 83 G N D 80 B L_C T L 77 U A R T_T X 74 N C 71 N C 68 N C 65 N C V B A T_R F 82 G N D 79 76 N C 73 U A R T_R X 70 N C 67 N C 64 G N D 3 90 M D _ B S U 1 6 5 6 2 6 6 2 D N G 7 6 2 T E D _ 2 M I S 8 6 2 V B A T_B B 3 6 9 2 1 5 1 2 C N 5 8 1 1 4 1 7 1 0 2 1 A D S _ C 2 I 8 1 9 6 2 1 L C S _ C 2 I 1 2 1 _ N E _ R W _ 5 1 6 S P Q P 4 2 0 7 2 S R _ D C L 3 2 N E _ R _ 1 H T E W P 7 2 N E _ R _ 0 H T E W P 3 7 2 0 3 3 3 2 7 2 _ 0 H T E N _ T N I 5 7 2 6 3 D N G 9 3 4 7 2 E T _ D C L 1 7 2 N E _ _ L W R W P 6 2 9 2 2 3 C N 5 3 D N G 8 3 1 N L _ IE C P P X T _ 6 7 2 1 N L _ IE C P N X T _ 1 4 7 7 2 D N G 8 7 2 2 4 D N G 5 4 _ 5 1 6 S N E _ R P Q W P 8 4 9 7 2 L V L _ D S W S _ 0 8 2 N _ T U O S E _ M D M 1 5 _ C D S 2 A T A D T E D _ C D S 4 5 1 8 2 _ C D S 3 A T A D R N E _ W P _ D S 7 5 0 6 R 7 4 0 5 D N G 3 5 _ C D S 1 A T A D 6 5 _ C D S 0 A T A D 9 5 4 4 1 N L _ IE C P N X R _ 1 N L _ IE C P P X R _ 1 Y E K R W P 4 N _ T E S E R 7 0 1 3 1 6 1 9 1 D N G 2 2 5 2 S Y S _ D D 8 V 1 _ V 8 2 N IO T _ G H C P O 1 3 D N G 4 3 7 3 0 4 0 N L _ IE C N X T _ 0 N L _ IE C P X T _ 6 4 3 4 0 N L _ IE C N X R _ P P P 9 4 0 N L _ IE C P X R _ P 2 5 D N G 5 5 B S U S S N X T _ 8 5 B S U S S P X T _ P ow er A na log C ontrol G N D G P IO R eserve d R F N C G e neral lo w -spee d H igh-spee d O the rs Figure 2. Pin assignment Copyright Fibocom Wireless Inc. 20 The pin "RESERVED" means that the position pin is reserved and does not need to be connected. 3 Pin Definition 3.2 Pin Definition Table 6. IO Parameter definition Type PI PO DI DO DIO AI AO AIO OD PU PD Hi-Z Description Power Input Power Output Digital Input Digital Output Digital Input/Output Analog Input Analog Output Analog Input/Output Open Drain Internal pull up Internal pull down High impedance Copyright Fibocom Wireless Inc. 21 Table 7. LGA pin description Pin Name Pin No I/O Level Reset Value Pin Description 3 Pin Definition Power VBAT_BB 261, 263, 264 84, 85, PI
Baseband power input VBAT_RF 86, 87, PI
88, 89 VDD_EXT_1V8 225 PO
VDD_3V1 22 PO
VDD_SYS_1V8 25 PO
VDD_WL_1V2 165, 290 PO
VDD_WL_1V9 231 PO
VDD_WL_0V9 255 PO
USB SSUSB_TXN 55 AO
SSUSB_TXP 58 AO
RF power input 1.8V power output Power for PM7250B USB PHY Power for PM7250B IO Power for WCN6856 RFA and PCIe PHY Power for WCN6856 RFA and PCIe PHY Power for WCN6856 CX,MX,RFA,AON,RFCMN,BT USB super speed transmit data minus USB super speed transmit data plus Copyright Fibocom Wireless Inc. 22 3 Pin Definition Pin Name Pin No I/O Level Reset Value Pin Description SSUSB_RXN 61 AI
SSUSB_RXP 63 AI
USB_DM USB_DP VBUS_DET 59 62 57 AIO
AIO
DI
OTG_PWR_EN 159 DO 1.8V PD USB super speed receive data minus USB super speed receive data plus USB high speed data minus USB high speed data plus USB VBUS detection USB OTG power enable, reserved USB_ID USIM SIM1_VDD SIM1_DATA SIM1_CLK SIM1_RST SIM1_DET SIM2_VDD SIM2_DATA SIM2_CLK SIM2_RST 60 DI 1.8V PD USB ID, reserved 7 10 13 16 14 18 12 15 11 PO
SIM1 power supply, 3V/1.8V DIO 1.8/3.0V PD SIM1 data input/output DO 1.8/3.0V PD SIM1 clock signal DO 1.8/3.0V PD SIM1 reset signal DI 1.8V PD SIM1 detect signal PO
SIM2 power supply, 3V/1.8V DIO 1.8/3.0V PD SIM2 data input/output DO 1.8/3.0V PD SIM2 clock signal DO 1.8/3.0V PD SIM2 reset signal SIM2_DET 267 DI 1.8V PD SIM2 detect signal GPIO Copyright Fibocom Wireless Inc. 23 3 Pin Definition Pin Name Pin No I/O Level Reset Value Pin Description W_DISABLE 109 DI 1.8V PD WAKEUP_IN 113 DI 1.8V PD Module flight mode control signal, reserved Module wake up input from host, reserved 5G_STATUS 106 DO 1.8V 4G_STATUS 110 DO 1.8V PD PD 5G status indicator, reserved 4G status indicator, reserved WIFI_STATUS 111 DO 1.8V PD WWAN_STATUS 108 DO 1.8V PD IRIG_B 117 DO 1.8V GPS_PPS 120 DO 1.8V PD PD LED_SINK 114 AI
Hi-Z DPR_N 210 DI 1.8V PD ANT ANT_1 193 AIO
ANT_2 184 AIO
ANT_3 175 AIO
ANT_4 166 AIO
WIFI status indicator, reserved Module status indicator reserved B code output, reserved PPS signal output, reserved LED negative drive signal, reserved DPR mode control signal, reserved RF antenna interface, ANT_1, reserved RF antenna interface, ANT_2 RF antenna interface, ANT_3, reserved RF antenna interface, ANT_4 Copyright Fibocom Wireless Inc. 24 Pin Name Pin No I/O Level Reset Value Pin Description 3 Pin Definition ANT_5 157 AIO
ANT_6 148 AIO
ANT_7 139 AIO
ANT_8 NC ANT_10 NC 130 AIO
121 199 205
AI
ANT Tuner Control
MIPI0_SDATA 198 DIO 1.8V PD MIPI0_SCLK 201 DO 1.8V PD MIPI1_SDATA 216 DIO 1.8V PD MIPI1_SCLK 219 DO 1.8V PD Module Control PWRKEY RESET_N 1 4 DI 1.8V PU DI 1.8V PU PU CBL_PWR_N 291 DI 1.8V RF antenna interface, ANT_5, reserved RF antenna interface, ANT_6 RF antenna interface, ANT_7, reserved RF antenna interface, ANT_8 NC GNSS antenna NC External Tuner MIPI Control Data Pin External Tuner MIPI Control Clock Pin External Tuner MIPI Control Data Pin External Tuner MIPI Control Clock Pin Module power-key control signal Module reset control signal Module power on signal Copyright Fibocom Wireless Inc. 25 3 Pin Definition Pin Name Pin No I/O Level Reset Value Pin Description WPS 123 DI 1.8V PD for WPS key input signal, Interrupt input signal, used USB_BOOT 273 DI 1.8V PD RESOUT_N 48 DO 1.8V BOOT_CFG 293 DI 1.8V BOOT_PCIE BOOT_OPTION 66 75 DIO 1.8V DIO 1.8V PD PD PD PD PM_FAULT_N 17 DIO 1.8V PD CHG_OPTION 28 AI
SD reserved Force into USB download boot mode Reserved, keep floating PCIE boot configure signal PCIE boot control signal Reserved, keep floating PMIC fault signal used for PM7250B Charger configure option input SDC_CMD 47 DIO 1.8/3.0V PD SDC interface command signal SDC_CLK SDC_DATA0 SDC_DATA1 SDC_DATA2 SDC_DATA3 45 56 53 51 54 DO 1.8/3.0V PD SDC interface clock signal DIO 1.8/3.0V PD SDC interface DATA0 signal DIO 1.8/3.0V PD SDC interface DATA1 signal DIO 1.8/3.0V PD SDC interface DATA2 signal DIO 1.8/3.0V PD SDC interface DATA3 signal SDC_DET 280 DI 1.8V PD SD card insert detection Copyright Fibocom Wireless Inc. 26 Pin Name Pin No I/O Level Reset Value Pin Description 3 Pin Definition SD_PWR_EN 281 DO 1.8V PD SDIO_VDD 211 PI
SD_LVL_SW 279 DO 1.8V PD PCIE PCIE_CLKN PCIE_CLKP PCIE_LN0_TXN PCIE_LN0_TXP PCIE_LN1_TXN PCIE_LN1_TXP PCIE_LN0_RXN PCIE_LN0_RXP PCIE_LN1_RXN PCIE_LN1_RXP 34 37 40 43 39 38 46 49 44 41 AIO
AIO
AO
AO
AO
AO
AI AI AI AI
PCIE_PEWAKEN 274 DIO 1.8V PCIE_PERSTN 275 DIO 1.8V PCIE_CLKREQN 276 DIO 1.8V
PU PD PU SD card power supply enable SDC interface I/O power domain GPIO, used for control SD I/O Power enable signal PCIe reference clock minus PCIe reference clock plus PCIe Tx0 minus PCIe Tx0 plus PCIe Tx1 minus PCIe Tx1 plus PCIe Rx0 minus PCIe Rx0 plus PCIe Rx1 minus PCIe Rx1 plus PCIe wake-up signal PCIe reset signal PCIe clock request signal JTAG TDI 183 DI 1.8V PD JTAG TDIreserved Copyright Fibocom Wireless Inc. 27 Pin Name Pin No I/O Level Reset Value Pin Description 3 Pin Definition TCK TDO 186 DI 1.8V 189 DO 1.8V TRST_N 295 DI 1.8V TMS 296 DI 1.8V SYSRSTB 297 DI 1.8V PS_HOLD 298 DO 1.8V I2C I2C_SDA0 115 DIO 1.8V I2C_SCL0 112 DO 1.8V PD PD PD PD PD PD PU PU I2C_SDA1 268 DIO 1.8V PU I2C_SCL1 269 DO 1.8V PU I2S I2S0_DO 103 DO 1.8V I2S0_MCK 94 DO 1.8V I2S0_DI 104 DI 1.8V I2S0_BCK 101 DO 1.8V I2S0_LRCK 105 DO 1.8V ADC ADC0 ADC1 249 252 AI AI
PD PD PD PD PD
JTAG TCKreserved JTAG TDOreserved JTAG TRSTreserved JTAG TMSreserved System resetreserved Power Supply hold on signal I2C data I2C clock I2C data used for PCIe switch I2C clock used for PCIe switch I2S data output signal I2S clock output signal I2S data input signal I2S data bit clock signal I2S frame clock signal A/D conversion channel 0 A/D conversion channel 1 Copyright Fibocom Wireless Inc. 28 Pin Name Pin No I/O Level Debug UART DBG_UART_TX 129 DO 1.8V DBG_UART_RX 126 DI 1.8V UART Reset Value PU PU 3 Pin Definition Pin Description Debug UART transmit signal Debug UART receive signal UART_CTS 79 DI 1.8V PD UART receive ready signal UART_RTS 64 DO 1.8V PD UART_TX UART_RX SPI SPI0_MISO SPI0_MOSI SPI0_CSB SPI0_CLK LCD LCD_RS LCD_PWR_EN 77 73 DO 1.8V DI 1.8V PD PD PD PD DI 1.8V DO 1.8V DO 1.8V PD 5 8 6 9 21 78 DO 1.8V DO 1.8V PD PD LCD_TE 33 DI 1.8V PD LCD_RST BL_CTL 30 80 DO 1.8V DO 1.8V PD PD UART transmit request signal UART transmit signal UART receive signal SPI interface input signal SPI interface output signal SPI interface chip select signal LCD Command / data select LCD power enable signal LCD frame synchronization signal LCD reset signal LCD Backlight control signal DO 1.8V PD SPI interface clock signal Copyright Fibocom Wireless Inc. 29 3 Pin Definition Pin Name Pin No I/O Level Reset Value Pin Description AUDIO CODEC CDC_RESET_N 98 DO 1.8V PD CDC_INT1_N 100 DI 1.8V PD DAC_PWR_EN 107 DO 1.8V PD CLOCK OUT External CODEC reset signal, reserved External CODEC interrupt signal, reserved External CODEC power enable, reserved SLEEP_CLK 265 AO
CLK_OUT 3 AO
32KHz clock output 76.8MHz clock output WLAN/BT/LAN BT_UTXD 135 DO 1.8V PD BT_URXD 138 DI 1.8V PD BT_URTS 282 DO 1.8V PD BT_UCTS 283 DI 1.8V PD BT_I2S_TX 97 DO 1.8V PD BT_I2S_RX 95 DI 1.8V PD UART TX signal, reserved for BT UART RX signal, reserved for BT UART RTS signal, reserved for BT UART CTS signal, reserved for BT I2S data output, reserved for BT I2S data input, reserved for BT Copyright Fibocom Wireless Inc. 30 Pin Name Pin No I/O Level Reset Value Pin Description 3 Pin Definition BT_I2S_SCK 96 DO 1.8V PD BT_I2S_WS 93 DO 1.8V PD BT_EN 209 DO 1.8V PD ETH0_INT_N ETH1_INT_N 27 29 DI 1.8V DI 1.8V WL_EN 204 DO 1.8V WL_EN_1 WL_PWR_EN 26 24 DO 1.8V DO 1.8V QPS615_PWR_EN 278 DO 1.8V QPS615_PWR_EN_1 270 DO 1.8V ETH0_PWR_EN 272 DO 1.8V ETH1_PWR_EN 271 DO 1.8V PD PD PD PD PD PD PD PD PD SDX_TO_WL_CTI 141 DO 1.8V PD WL_TO_SDX_TI 144 DI 1.8V PD I2S clock output, reserved for BT I2S synchronization signal, reserved for BT GPIO, used for BT control signals GPIO, reserved GPIO, reserved GPIO, reserved GPIO, reserved GPIO, reserved GPIO, reserved GPIO, reserved GPIO, reserved GPIO, reserved Used for WWAN control WLAN, reserved Used for WLAN control WWAN, reserved Used for enable WCN6856 WL_LAA_RX 150 DO 1.8V PD FE High Gain High Isolation for WAN PRX/DRX, reserved Copyright Fibocom Wireless Inc. 31 3 Pin Definition Pin Name Pin No I/O Level Reset Value Pin Description SW_CTRL_PMX 162 DIO 1.8V PD WIFI/BT and RF coexistence control signals, reserved Used for disable WLAN TX WL_PA_MUTE 153 DO 1.8V PD prior to switching to WWAN, LAA_AS_EN 287 DO 1.8V PD N79_TX_EN 168 DO 1.8V PD CO_UART_TX 99 DO 1.8V PD CO_UART_RX 102 DI 1.8V PD reserved Used for enable WCN6856 Front End Control, reserved N79 transmitter indication signal, reserved WIFI/BT and RF coexistence control signals, reserved WIFI/BT and RF coexistence control signals, reserved SPMI SPMI_CLK SPMI_DATA 20 23 DO 1.8V PD SPMI clock signal DIO 1.8V PD SPMI data signal PD Copyright Fibocom Wireless Inc. 32 3 Pin Definition mmW QTM0 IFH3 IFV4 QTM1 IFH1 IFV2 QTM2 IFH2 IFV1 QTM3 IFH4 IFV3 237 223 217 240 235 229 243 247 241 246 259 253
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Copyright Fibocom Wireless Inc. 33 Pin Name Pin No 3 Pin Definition NC NC GND 2, 32, 65, 67, 68, 69, 70, 71, 72, 74, 76, 116, 156, 171, 174, 177, 180, 207, 212, 285, 286, 288, 292, 294 19, 31, 35, 36, 42, 50, 52, 81, 82, 83, 90, 91, 92, 118, 119, 122, 124, 125, 127, 128, 131, 132, 133, 134, 136, 137, 140, 142, 143, 145, 146, 147, 149, 151, 152, 154, 155, 158, 160, 161, 163, 164, 167, 169, 170, 172, 173, 176, 178, 179, 181, 182, 185, 187, 188, 190, 191, 192, 194, 195, 196, 197, 200, 202, 203, 206, 208, 213, 214, 215, 218, 220, 221, 222, 224, 226, 227, 228, 230, 232, 233, 234, 236, 238, 239, 242, 244, 245, 248, 250, 251, 254, 256, GND 257, 258, 260, 262, 266, 277, 284, 289, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, 373, 374, 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392 The PWRKEY, CBL_PWR_N and RESET_N pins have internal pull-up. The pull-
up power supply is in exclusive mode, external pull-up is not required. Copyright Fibocom Wireless Inc. 34 4 Electrical Characteristics 4 Electrical Characteristics 4.1 Recommended Operating Conditions Table 8. Recommended operating voltage Pin Name Type Min (V) Typ (V) Max (V) Current Limit Max (mA) VBAT_BB, VBAT_RF PI 3.31 3.8 1.8 4.41 1.9 3.088
VDD_EXT_1V8 PO VDD_3V1 PO VDD_SYS_1V8 PO VDD_WL_1V2 PO VDD_WL_1V9 PO VDD_WL_0V9 PO SIM1_VDD/
SIM2_VDD PO SDIO_VDD PI PWRKEY RESET_N CBL_PWR_N VBUS_DET2 ADC0 ADC1 DI DI DI DI AI AI 1.7
1.7 1.23 1.83 0.62 1.7 1.8 1.28 1.88 0.85 1.8 2.75 2.95 1.7 1.8 2.75 2.85 0 0 0 0 0 0
4000 50 25 25 TBD TBD TBD 200 200 200 200
1.9 1.3 2 0.98 1.9 3.0 1.9 3.0 1.85 1.85 1.85 5.5 1.875 VBAT_BB Copyright Fibocom Wireless Inc. 35 4 Electrical Characteristics 1. Directly measured at Module. Voltage must stay within the min/max values, including voltage drop, ripple and spikes. 2. When VBUS_DET input voltage 1.3V, USB detection trigger. 4.2 I/O Logic Characteristics Table 9. I/O port logic characteristics Parameters Min Typical Max Unit 1.8V logic level VIH VIL VOH@2mA VOL 3.0V logic level VIH VIL VOH VOL 1.3
-0.3 1.35 0 2.3
-0.3 2.6 0 1.8 1.89 0
3 0
0.6 1.8 0.45 3.1 0.7 3.0 0.45 V V V V V V V V 4.3 Power Consumption Table 10. Power consumption State Mode Condition Typical Current/mA IOFF Power off Power supply, module power-off 0.18 Copyright Fibocom Wireless Inc. 36 State Mode Condition IIDLE TDD LTE DPC (Default Paging Cycle) =#128 FDD LTE DPC (Default Paging Cycle) =#128
(USB SA Long DRX (ms10) Disconnection.) Radio Off AT+CFUN=4 Flight Mode LTE FDD DPC (Default Paging Cycle) =#128 LTE TDD DPC (Default Paging Cycle)=#128 ISLEEP
(USB Disconnection.) SA Long DRX (ms10) Radio Off AT+CFUN=4, Flight mode. LTE FDD Data call Band 2 @+23dBm LTE FDD Data call Band 4 @+23dBm LTE FDD Data call Band 5 @+23dBm 4 Electrical Characteristics Typical Current/mA TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD LTE FDD LTE FDD Data call Band 12 @+23dBm TBD LTE FDD Data call Band 13 @+23dBm TBD ILTE-RMS LTE FDD Data call Band 30 @+22dBm TBD LTE FDD Data call Band 66 @+23dBm TBD LTE FDD Data call Band 71 @+23dBm TBD LTE TDD Data call Band 41 @+23dBm TBD LTE TDD Data call Band 48 @+21dBm TBD LTE TDD LTE HPUE LTE TDD Data call Band 41 @+26dBm TBD INSA-RMS EN-DC EN-DC Data call B2+n5 @20dBm+20dBm TBD Copyright Fibocom Wireless Inc. 37 State Mode Condition 4 Electrical Characteristics Typical Current/mA EN-DC Data call B2+n71 @20dBm+20dBm TBD EN-DC Data call B66+n66 @20dBm+20dBm TBD EN-DC Data call B5+n66 @20dBm+20dBm TBD EN-DC Data call B2+n66 @20dBm+20dBm TBD EN-DC Data call B2+n12 @20dBm+20dBm TBD EN-DC Data call B66+n25 @20dBm+20dBm TBD EN-DC Data call B48+n5 @20dBm+20dBm TBD EN-DC Data call B66+n30 @20dBm+20dBm TBD EN-DC Data call B48+n66 @20dBm+20dBm TBD EN-DC Data call B2+n41 @23dBm+23dBm TBD EN-DC Data call B66+n41 @23dBm+23dBm TBD EN-DC HPUE EN-DC Data call B41+n41 @23dBm+23dBm TBD EN-DC Data call B12+n77 @23dBm+23dBm TBD ISA-RMS SA FDD SA TDD EN-DC Data call B2+n77 @23dBm+23dBm TBD EN-DC Data call B48+n77 @23dBm+23dBm TBD n2@max power (10MHz, Inner full RB) TBD n5@max power (10MHz, Inner full RB) TBD n12@max power (10MHz, Inner full RB) TBD n14@max power (10MHz, Inner full RB) TBD n25@max power (10MHz, Inner full RB) TBD Copyright Fibocom Wireless Inc. 38 State Mode Condition 4 Electrical Characteristics Typical Current/mA n30@max power (10MHz, Inner full RB) TBD n66@max power (10MHz, Inner full RB) TBD n70@max power (10MHz, Inner full RB) TBD n71@max power (10MHz, Inner full RB) TBD n41@max power (100MHz, Inner full RB) TBD n48@max power (40MHz, Inner full RB) TBD n77@max power (100MHz, Inner full RB) TBD n41@max power (100MHz, Inner full RB) TBD n77@max power (100MHz, Inner full RB) TBD n41@max power (100MHz, Inner full RB) TBD n77@max power (100MHz, Inner full RB) TBD SA TDD HPUE SA UL MIMO Test condition: temperature 25, VBAT_BB&VBAT_RF: 3.8V. 4.4 Radio Frequency 4.4.1 Transmitting Power The transmit power for each band of the FG160 module is shown in the following table:
Copyright Fibocom Wireless Inc. 39 4 Electrical Characteristics Table 11. RF transmit power 3GPP Mode Band Requirement
(dBm) Tx Power
(dBm) Note Band 2 232.7 231.5 10MHz BW, 12RB Band 4 232.7 231.5 10MHz BW, 12RB Band 5 232.7 231.5 10MHz BW, 12RB Band 7 232.7 231.5 10MHz BW, 12RB LTE FDD Band 12 232.7 231.5 10MHz BW, 12RB Band 13 232.7 231.5 10MHz BW, 12RB Band 30 232.7 221 10MHz BW, 12RB Band 66 232.7 231.5 10MHz BW, 12RB Band 71 23+2.7/-3.2 231.5 10MHz BW, 12RB Band 41 232.7 231.5 10MHz BW, 12RB LTE TDD Band 41 HPUE 262.7 261.5 10MHz BW, 12RB Band 48 23+3.0/-4.0 211 10MHz BW, 12RB 5G NR n2 n5 n7 n12 n14 n25 n30 n48 232.7 231.5 10MHz BW, inner Full 232.7 232.7 231.5 10MHz BW, inner Full 231.5 10MHz BW, inner Full 232.7 231.5 10MHz BW, inner Full 232.7 231.5 10MHz BW, inner Full 232.7 231.5 10MHz BW, inner Full 232.7 23+3/-4 221 211 10MHz BW, inner Full 10MHz BW, inner Full Copyright Fibocom Wireless Inc. 40 3GPP Mode Band Requirement
(dBm) Tx Power
(dBm) Note 4 Electrical Characteristics n66 n70 n71 n41 232.7 231.5 10MHz BW, inner Full 232.7 231.5 10MHz BW, inner Full 23+2.7/-3.2 231.5 10MHz BW, inner Full 233 231.5 100MHz BW, inner Full n41 HPUE 26+3/-4 261.5 100MHz BW, inner Full n41 UL MIMO 24.5+3/-4 24.51.5 100MHz BW, inner Full n77 23+3/-4 231.5 100MHz BW, inner Full n77 HPUE 26+3/-4 261.5 100MHz BW, inner Full n77 UL MIMO 24.5+3/-4 24.51.5 100MHz BW, inner Full n78 23+3/-4 231.5 100MHz BW, inner Full n78 HPUE 26+3/-4 261.5 100MHz BW, inner Full n78 UL MIMO 24.5+3/-4 24.51.5 100MHz BW, inner Full 4.4.2 Dual Antenna Receiver Sensitivity The receiver sensitivity with dual antenna for each band of FG160 module is shown in below table:
Table 12. RF receiver sensitivity Mode Band 3GPP Requirement Rx Sensitivity
(dBm) Typ (dBm) Note LTE FDD Band 2
-94.3
(10MHz) Band 4
-96.3 TBD TBD 10MHz BW 10MHz BW Copyright Fibocom Wireless Inc. 41 Mode Band 3GPP Requirement Rx Sensitivity
(dBm) Typ (dBm) Note 4 Electrical Characteristics Band 5
-94.3 Band 7
-94.3 Band 12
-93.3 Band 13
-93.3 Band 29 TBD Band 30
-95.3 Band 66
-95.8 Band 71
-93.5 Band 41
-94.3 Band 46 TBD Band 48
-95 n2 n5 n7
-94.8
-94.8
-94.8 n12
-93.8 n14
-93.8 n25
-93.3 n30
-95.8 n41
-84.7 n48
-96.1 n66
-96.3 LTE TDD
(10MHz) NR TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 30KHz 100MHz BW SCS 30KHz 10MHz BW SCS 15KHz 10MHz BW Copyright Fibocom Wireless Inc. 42 4 Electrical Characteristics Mode Band 3GPP Requirement Rx Sensitivity
(dBm) Typ (dBm) Note n70
-96.8 n71
-94 n77
-85.1 n78
-85.6 TBD TBD TBD TBD SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 30KHz 100MHz BW SCS 30KHz 100MHz BW 4.4.3 Four Antenna Receiver Sensitivity The L/M/H bands can support DL 4 MIMO, the receiver sensitivity of L/M/H bands is shown in the following table:
Table 13. RF receiver sensitivity Mode Band 3GPP Requirement Rx Sensitivity
(dBm) Typ (dBm) Note LTE FDD
(10M) Band 2
-97 Band 4
-99 Band 5 TBD Band 7
-97 Band 12 TBD Band 13 TBD Band 30
-98 Band 66
-98.5 Band 71 TBD LTE TDD Band 41
-97
(10M) Band 48 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW 10MHz BW Copyright Fibocom Wireless Inc. 43 Mode Band 3GPP Requirement Rx Sensitivity
(dBm) Typ (dBm) Note 4 Electrical Characteristics 5G NR n2 n5 n7 n12 n14 n25 n30 n66 n70 n71 n41 n48 n77 n78
-97.5 TBD
-97.5 TBD TBD TBD
-98.5
-99
-99.5 TBD 87.4
-98.3 87.3 87.8 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 15KHz 10MHz BW SCS 30KHz100MHz BW SCS 30KHz 10MHz BW SCS 30KHz 100MHz BW SCS 30KHz 100MHz BW 4.4.4 GNSS FG160 module supports GNSS with ANT_10 antenna, the GNSS includes GPS/GLONASS/
Galileo/BDS/QZSS. GNSS performance is shown in below table:
Table 14. GNSS performance Description Condition Test Result (Typ) Current Fixing Tracking TBD TBD Copyright Fibocom Wireless Inc. 44 Description Condition Test Result (Typ) 4 Electrical Characteristics Sleep Cold start TTFF Warm start Sensitivity Hot Start Tracking Acquisition 4.4.5 Operating Band TBD TBD TBD TBD TBD TBD Table 15. Operating band Band Mode Tx (MHz) Rx (MHz) Band 2 LTE FDD 18501910 19301990 Band 4 LTE FDD 17101755 21102155 Band 5 LTE FDD 824849 869894 Band 7 LTE FDD 2500-2570 2620-2690 Band 12 LTE FDD 699716 729746 Band 13 LTE FDD 777787 746756 Band 29 LTE FDD
717728 Band 30 LTE FDD 23052315 23502360 Band 41 LTE TDD 24962690 Band 46 LTE TDD
51505925 Band 48 LTE TDD 35503700 Band 66 LTE FDD 17101780 21102200 Copyright Fibocom Wireless Inc. 45 Band Mode Tx (MHz) Rx (MHz) Band 71 LTE FDD 663698 617652 4 Electrical Characteristics n2 n5 n7 n12 n14 n25 n30 n41 n48 n66 n70 n71 n77 n78 NR FDD NR FDD NR FDD NR FDD NR FDD NR FDD NR FDD NR TDD NR TDD NR FDD NR FDD NR FDD NR TDD NR TDD GPS L1 GPS L5
GLONASS G1
Galileo E1 BDS B1 QZSS
19201980 21102170 703748 758803 2500-2570 2620-2690 699716 729746 788798 758768 18501915 19301995 23052315 23502360 24962690 35503700 17101780 21102200 16951710 19952020 663698 617652 33004200 33004200 33003800 33003800
1575.421.023 1176.4510.23 1602.56254 1575.422.046 1561.0982.046 1575.421.023 Copyright Fibocom Wireless Inc. 46 4 Electrical Characteristics 4.4.6 Antenna Requirements Table 16. Module antenna requirements FG160 module antenna requirements LTE/NR GNSS VSWR: 2:1 Input power (W): > 28dBm average power LTE & NR Input impedance (): 50 Antenna isolation (dB): > 25 Frequency range: 1559MHz1607MHz VSWR: < 2: 1 Copyright Fibocom Wireless Inc. 47 5 Interface Introduction 5 Interface Introduction 5.1 Power The DC power input range of FG160 module is 3.3V to 4.4V, and the recommended value is 3.8V. DC power continuous output ability requires more than 3A. The performance of the power supply, such as load capacity and ripple size, will directly affect the performance and stability of the module. 5.1.1 Power Supply FG160 module provides power supply via VBAT_BB and VBAT_RF. The power supply design is shown in following figure:
Module VBAT VBAT_BB VBAT_RF F p 0 0 1 F n 0 0 1 F u 1 F u 0 2 2
VBAT F p 3 3
. F p 8 6
. F p 8 F p 0 1 F p 3 3 F n 0 0 1 F u 1 F u 0 2 2
The filter capacitor design for power supply as shown in the following table:
Figure 3. Power supply design Copyright Fibocom Wireless Inc. 48 Table 17. Power supply filter capacitor design 5 Interface Introduction Recommended Capacitance Description Reduce power fluctuations of the module in operation, requiring capacitors with low ESR. LDO or DC/DC power supply requires the capacitor no less than 440uF. The capacitor for battery power supply can be reduced to 100-
200uF. Filter out the interference generated from the clock and digital signals Filter out 600/700/850/900MHz frequency band RF interference(low band) Filter out 1700/1800/1900/2100/2300/2500/2600/3500/3700MHz,5GHz frequency band RF interference(high band) 220uF 2 1uF 2,100nF 2 33pF 3.3pF,6.8pF,8pF, 10pF The stable power supply can ensure the normal operation of FG160 module, and the ripple of the power supply should be less than 300mV in design. Because module support 5G NR Sub-6 download, when module operates with the maximum data transfer throughput, the peak current can reach to upper 4000 mA. It requests the power source voltage should not be lower than 3.3V, otherwise module may shut down or restart. The power supply requirement is shown in following figure:
Copyright Fibocom Wireless Inc. 49 5 Interface Introduction Transmit burst Transmit burst VBAT Min:3.3V Ripple Drop Figure 4. Power supply voltage drop diagram The filter capacitor is located near the pin of the power supply and arranged in order of capacity size. It is recommended that the PCB traces of the power supply be as short as possible. It is wide enough power supply traces to ensure that no large voltage drops occur in maximum transmit power status. 5.2 Control Interface The FG160 module provides three control signals for power-on/off and reset operations, the pins are defined in the following table:
Copyright Fibocom Wireless Inc. 50 5 Interface Introduction Table 18. Control signal Pin name Pin No I/O Description CBL_PWR_N 291 DI Pull down CBL_PWR_N for more than some time, Module power on input, internal pull up Module will power on from power off status. Module power on/off input, internal pull up Pull down PWRKEY with pulse, module will power on PWRKEY 1 DI from power off status. Pull down PWRKEY with pulse, module will power off from power on status. RESET_N 4 DI Pull down RESET_N with pulse, module will reset PCIE_PERSTN 275 DIO PCIe link reset signal CBL_PWR_N signal can only be used for module startup, not shutdown. It is mainly used for automatic startup applications 5.2.1 Normal Mode 5.2.1.1 Module Start-up When the module is in shutdown mode, pull down PWRKEY with pulse to enable the module to start. The way to control the PWRKEY pin is directly through a push button switch. A TVS (EGA10402V05AH-A recommended) should be placed near the button for ESD protection. The reference circuit is shown below:
Copyright Fibocom Wireless Inc. 51 5 Interface Introduction KEY PWRKEY TVS Close to the KEY Figure 5. Normal mode start-up circuit The start-up timing sequence is shown in following figure:
VBAT PWRKEY RESET_N Tpr T1 T3 Ton T2 Module State OFF Initialization Activation(AT Command Ready) typical 30s Figure 6. Normal mode timing control for start-up Index Min. Recommended Max. Comments Tpr 0ms
up to 3.3V. If power supply always ready, it can The delay time of power supply rising from 0V T1 T2 0.5ms 75ms T3 0ms be ignored PWRKEY pin ready time after power on. This pin is high when ready due to internal pull-up RESET_N pin ready time after power on. This pin is high when ready due to internal pull-up Delay time from RESET_N pin ready to pulse trigger signal start point. Ton 50ms --
1000ms Power-on pulse signal width Copyright Fibocom Wireless Inc. 52 Before pulling down the PWRKEY pin, ensure that the VBAT voltage is more 5 Interface Introduction than 3.3V. 5.2.1.2 Module Shutdown The module support the following shutdown mode:
Table 19. Shutdown mode Shutdown Type Shutdown Method Remark Hardware shutdown Pull down PWRKEY with pulse
then release The shutdown timing sequence is shown in following figure:
Toff Tpd VBAT PWRKEY RESET_N Module State Activation Tsd Finalization OFF Figure 7. Normal mode shutdown timing Index Min. Recommended Max. Comments Toff 2500ms --
5000s Power-off pulse signal width Tpd 10ms 100ms
VBAT power supply goes down time. If power supply is always on, it can be ignored Copyright Fibocom Wireless Inc. 53 After the PWRKEY signal is released, the next power-on trigger can be performed at least 2s later. This interval is reserved for the module shutdown process and the power release of the peripheral circuit connecting with module interface. 5 Interface Introduction 5.2.1.3 Module Reset There is a type of module reset: hardware reset. Table 20. Reset method Reset type Reset method Hardware reset Pull down the RESET_N pin with pulse, then release The way to control the RESET_N pin is directly through a push button switch. A TVS
(EGA10402V05AH-A recommended) should be placed near the button for ESD protection. The reference circuits are shown in the following figure:
KEY RESET_N TVS Close to the KEY Figure 8. Normal mode reset circuit Reset timing sequence is shown in the following figure:
VBAT PWRKEY RESET_N Toff typical 30s Module State Activation Baseband reset Initialization Activation Copyright Fibocom Wireless Inc. 54 Figure 9. Normal mode reset timing 5 Interface Introduction Index Min. Recommended Max. Comments toff 600ms --
750ms Pull down the RESET_N pin with pulse, then release 50 seconds minimum before next reset operation. The RESET_N pin of module has internal pull-up, no need external pull-up. 5.2.2 PCIe EP Mode When FG160 is configured as PCIe EP mode (slave mode), there will be some differences in control timing, and there are some related design should be applied refer to chapter 5.8 5.2.2.1 Module Start-up It is recommended to use the following OC driver circuit to control the PWRKEY pin. The reference circuit is shown in the following figure:
PWRKEY Turn on pulse 4.7K 10nF 47K Figure 10. PCIe EP mode start-up circuit The start-up timing sequence is shown in following figure:
Copyright Fibocom Wireless Inc. 55 5 Interface Introduction VBAT Tpr PWRKEY RESET_N PERST_N T1 T3 Ton1 T2 Ton2 Module State OFF Initialization Activation(AT Command Ready) typical 30s Figure 11. PCIe EP mode timing control for start-up Index Min. Recommended Max. Comments Tpr 0ms
up to 3.3V. If power supply always ready, it can The delay time of power supply rising from 0V be ignored PWRKEY pin ready time after power supply T1 0.5ms ready. This pin is high when ready due to internal pull-up RESET_N pin ready time after power supply T2 75ms ready. This pin is high when ready due to T3 0ms internal pull-up Delay time from RESET_N pin ready to pulse trigger signal start point. Ton1 50ms --
1000ms Power-on pulse signal width Ton2 50ms 100ms
Delay time from PWRKEY achieved to PERST_N de-asserted Copyright Fibocom Wireless Inc. 56 5 Interface Introduction Before pulling down the PWRKEY pin, ensure that the VBAT voltage is more than 3.3V. 5.2.2.2 Module Shutdown The shutdown timing sequence is shown in following figure:
VBAT PWRKEY RESET_N PERST_N Toff2 Tpd Toff1 Tsd Module State Activation Finalization OFF Figure 12. PCIe EP mode shutdown timing Index Min. Recommended Max. Comments Toff1 16ms 20ms
Delay time from PERST_N assert to pulse trigger signal start point Toff2 2500ms --
5000ms Power-off pulse signal width Tpd 10ms 100ms
VBAT power supply goes down time. If power supply is always on, it can be ignored 5.2.2.3 Module Reset It is recommended to use the following OC driver circuit to control the RESET_N pin. The reference circuit is shown in the following figure:
Copyright Fibocom Wireless Inc. 57 5 Interface Introduction RESET_N Reset pulse 4.7K 47K Figure 13. PCIe EP mode reset circuit Reset timing sequence is shown in the following figure:
VBAT PWRKEY RESET_N Toff PERST_N Toff1 Ton1 typical 30s Activation Reset Initialization Activation Figure 14. PCIe EP mode reset timing Index Min. Recommended Max. Comments Toff1 16ms 20ms
RESET_N should be asserted after PERST_N Toff 600ms --
750ms Pull down the RESET_N pin with pulse, then release Toff2 50ms 100ms
The time delay of PERST_N de-asserted after RESET_N de-asserted Copyright Fibocom Wireless Inc. 58 5 Interface Introduction 50 seconds minimum before next reset operation. The RESET_N pin of module has internal pull-up, no need external pull-up. 5.3 Network Status Indicator Interface The module provides four status indicator signal interfaces. The pin definition is shown in Table 21. Table 21. Status indicator pin Pin Name Pin No I/O Description 5G_STATUS 106 4G_STATUS 110 DO DO 5G status indicator, Reserved 4G status indicator, Reserved Module status indicator, Reserved WWAN_STATUS 108 DO Module power on: high level Module power off: low level WIFI_STATUS 111 DO WIFI status indicator, Reserved 5.3.1 Interface Status Description (Reserved) The network status indicator interface is used to drive the status indicator, which is used to indicate the network status of the module as Table 22. Table 22. Status indicator output mode Mode Module Network Indicator Pin status LED Status Status Copyright Fibocom Wireless Inc. 59 Data T-put transfer 75ms high level / 75ms low Flash, 75ms on /
level 75ms off 5 Interface Introduction 1 2 3 Network ready High level Network not ready Low level The network status indicator reference circuit is as follows:
Module NET_STATUS 4.7K ON OFF VBAT RLED 47K Figure 15. Indicator drive circuit diagram The LED brightness depends on resistance of RLED. 5.4 SIM Card Interface The FG160 module support dual SIM. There are two SIM card interface and can supports 1.8V and 3.0V SIM cards. 5.4.1 SIM Card Interface Definition SIM pin definition is shown in the following table:
Copyright Fibocom Wireless Inc. 60 Table 23. SIM pin definition 5 Interface Introduction Pin name Pin No I/O Description SIM1_VDD SIM1_DATA SIM1_CLK SIM1_RST 7 10 13 16 PO SIM1 power output, 3V/1.8V DIO SIM1 data signal DO DO SIM1 clock signal SIM1 reset signal SIM1_DET 14 DI SIM1 insert detection signal, internal 390K pull-up. Active high, high level indicates SIM card inserted and low level indicates SIM card plugged out. SIM2_VDD SIM2_DATA SIM2_CLK SIM2_RST 18 12 15 11 PO SIM2 power output, 3V/1.8V DIO SIM2 data signal DO DO SIM2 clock signal SIM2 reset signal SIM2_DET 267 DI SIM2 insert detection signal, internal 390K pull-up. Active high, high level indicates SIM card inserted and low level indicates SIM card plugged out. The SIM2 interface is NC (not connected) when module has embedded eSIM. 5.4.2 SIM Card Interface Circuit SIM card interface reference circuit is shown in following figure. Copyright Fibocom Wireless Inc. 61 Module SIM1_VDD SIM1_DATA SIM1_CLK SIM1_RST SIM1_DET SIM2_VDD SIM2_DATA SIM2_CLK SIM2_RST SIM2_DET 7 10 13 16 14 18 12 15 11 267 22R 22R 22R 1K 22R 22R 22R 1K F u 1 0
. F p 3 3 C N C N C N F u 1 0
. F p 3 3 C N C N C N 5 Interface Introduction SIM1 Connector VDD DAT CLK RST VPP CD GND SIM2 Connector VDD DAT CLK RST VPP CD GND TVS capacit ance less t han 33pF Figure 16. SIM interface reference circuit 5.5 USB Interface FG160 module supports USB3.1 Gen2, USB2.0, compatible with USB1.1. 5.5.1 USB Interface Definition Table 24. USB interface pin definition Pin Name Pin No I/O Description SSUSB_TXN 55 AO USB super speed transmit data minus SSUSB_TXP 58 AO USB super speed transmit data plus SSUSB_RXN 61 SSUSB_RXP 63 AI AI USB super speed receive data minus USB super speed receive data plus USB_DM 59 AIO USB high speed data minus Copyright Fibocom Wireless Inc. 62 5 Interface Introduction USB_DP VBUS_DET 62 57 AIO USB high speed data plus DI USB VBUS detection 5.5.2 USB Interface Circuit USB interface reference circuit is shown in the following figure:
VBUS B Z T 5 2 C 6 V 8 S U M S 0 4 A 1 2 T 2 V 2 1uF 0R 0R 0R 0R 0R Module VBUS_DET USB_HS_DM USB_HS_DP USB_SS_TX_M USB_SS_TX_P USB_SS_RX_M USB_SS_RX_P USB Connector SHIELD SHIELD SHIELD SHIELD SHIELD VBUS DATA_N DATA_P USB_ID GND TX_N TX_P GND_DRAIN RX_N RX_P TVS capacit ance less than 0.2pF Figure 17. USB interface reference design 5.5.3 USB Routing Rules 5.5.3.1 USB2.0 Routing Rules The USB_DM / USB_DP trace length mismatch is controlled within 50mil, and the differential impedance is controlled as 90 10%. USB_D- and USB_D+ signal lines should be routed on the layer that is adjacent to the ground layer, and wrapped with GND vertically and horizontally. Copyright Fibocom Wireless Inc. 63 5 Interface Introduction 5.5.3.2 USB3.1 Routing Rules SSUSB _RXP/N and SSUSB_TXP/N are two sets of differential signals, with differential impedance controlled as 90 10%; the length match of the intra differential pair 5mil. The two pairs of differential signal lines should be routed on the layer that is adjacent to the ground layer, and wrapped with GND vertically and horizontally. 5.6 ADC Interface The FG160 module provides two analog-to-digital conversion interfaces. 5.6.1 ADC Interface Definition Table 25. ADC interface definition Pin Name Pin No I/O Description ADC0 249 AI A/D conversion channel 0 ADC1 252 AI A/D conversion channel 1 5.6.2 ADC Electrical Characteristics Table 26. ADC electrical characteristics Pin Name Input Voltage Range (V) Resolution (uV) ADC0 ADC1 0-1.875 0-VBAT_BB 64.879 194.637 Please keep ADC signals connect to ground if not used. Copyright Fibocom Wireless Inc. 64 5 Interface Introduction 5.7 Forced-download Interface The FG160 module has a forced-download signal shown in Table 27. Table 27. Forced-download interface Pin Name Pin No I/O Description USB_BOOT 273 DI Forced into USB download boot mode Default low, high active. 5.7.1 Configuration Signal Interface Circuit Reference circuit is shown in following figure:
Module USB_BOOT VDD_EXT_1V8 KEY 1K TVS Close to the KEY Figure 18. Configuration signal circuit 5.8 PCIE Boot Control Interface Table 28. PCIe boot control pin Pin Name Pin No. I/O Description BOOT_PCIE 66 DIO PCIE boot control signal BOOT_CFG 293 DO PCIE boot configure signal When need to configure as PCIe EP mode, the circuit below should be applied. If not, just keep BOOT_CFG and BOOT_PCIE floating. Copyright Fibocom Wireless Inc. 65 5 Interface Introduction P-MOS 10K BOOT_PCIE VDD_EXT_1V8 BOOT_CFG Figure 19. PCIe boot mode configure circuit 5.9 Flight Mode Control Interface (Reserved) Pull down the W_DISABLE pin to enter flight mode Table 29. Flight mode control pin Pin Name Pin No. I/O Description W_DISABLE 109 DI Module flight mode control signal, reserved 5.10 GPIO Interface Table 30. GPIO table Pin Name Pin No Power Domain Default Pull Type EINT GPIO No WIFI_STATUS 111 1.8V 4G_STATUS 110 1.8V W_DISABLE 109 1.8V 5G_STATUS 106 1.8V WPS 123 1.8V WWAN_STATUS 108 1.8V DAC_PWR_EN 107 1.8V BT_EN WL_EN 209 1.8V 204 1.8V PD PD PD PD PD PD PD PD PD N N Y N N N N N N GPIO97 GPIO01(PMU) GPIO86 GPIO14(PMU) GPIO09(PMU) GPIO04(PMU) GPIO06(PMU) GPIO15(PMU) GPIO91 Copyright Fibocom Wireless Inc. 66 WL_EN_1 WL_PWR_EN 26 24 1.8V 1.8V QPS615_PWR_EN 278 1.8V QPS615_PWR_EN_1 270 1.8V ETH1_PWR_EN 271 1.8V ETH0_PWR_EN 272 1.8V PD PD PD PD PD PD 5 Interface Introduction N N N N N N GPIO87 GPIO102 GPIO101 GPIO107 GPIO106 GPIO105 All GPIO in the table above can be configured according to the requirements. 5.11 PCIE Interface FG160 module support 1 group PCIe Gen3, x2 lanes. Both RC mode and EP mode support. 5.11.1 PCIe Interface Definition Table 31. PCIe signal list Pin Name Pin No I/O Pin Description PCIE_CLKN PCIE_CLKP PCIE_LN0_TXN PCIE_LN0_TXP PCIE_LN1_TXN PCIE_LN1_TXP PCIE_LN0_RXN PCIE_LN0_RXP PCIE_LN1_RXN 34 37 40 43 39 38 46 49 44 AIO AIO AO AO AO AO AI AI AI PCIe reference clock minus PCIe reference clock plus PCIe Tx0 minus PCIe Tx0 plus PCIe Tx1 minus PCIe Tx1 plus PCIe Rx0 minus PCIe Rx0 plus PCIe Rx1 minus Copyright Fibocom Wireless Inc. 67 5 Interface Introduction Pin Name Pin No I/O Pin Description PCIE_LN1_RXP 41 AI PCIe Rx1 plus PCIE_PEWAKEN 274 DIO PCIe wake-up signal PCIE_PERSTN 275 DIO PCIe reset signal PCIE_CLKREQN 276 DIO PCIe clock request signal 5.11.2 PCIE Routing Rules The PCIe bus can up to 8 GT/s speed. The following rules should be followed strictly in PCB layout:
The impedance of differential pair lines are recommended to be 85 10%. The length match of the intra differential pair 5mil;
The differential signal pair lines shall be short if possible and be controlled within 180 mm. 5.11.3 PCIE Application Circuit Please refer to FIBOCOM FG160_Reference Design HDK for PCIE application circuit. 5.12 SD Interface FG160 module supports SD interface, the standard is as follows:
Physical Layer Specification version 3.0, SDIO Card Specification version 3.0 5.12.1 SD Interface Definition Table 32. SD signal list Pin Name Pin No I/O Pin Description SDC_CMD 47 DIO SDC interface command signal Copyright Fibocom Wireless Inc. 68 5 Interface Introduction Pin Name Pin No I/O Pin Description SDC_CLK SDC_DATA0 SDC_DATA1 SDC_DATA2 SDC_DATA3 45 56 53 51 54 DO SDC interface clock signal DIO SDC interface DATA0 signal DIO SDC interface DATA1 signal DIO SDC interface DATA2 signal DIO SDC interface DATA3 signal SDC_DET 280 DI SD card insert detection SD_PWR_EN 281 DO SD card power supply enable SDIO_VDD 211 PI SDC interface I/O power domain SD_LVL_SW 279 DO GPIO, used for control SD I/O Power enable signal 5.12.2 SD Interface Routing Rules The length of the signal line is controlled to 100mm, and the difference between the length of the clock signal and the data signal is controlled to 6mm. 5.12.3 SD Interface Application Design Refer to FIBOCOM FG160_Reference Design HDK for detail information including Block Diagram and Schematic. 5.13 I2C Interface The FG160 module supports one I2C interface, applying the standard I2C Specification, version 3.0 Copyright Fibocom Wireless Inc. 69 Table 33. I2C Interface Definition 5 Interface Introduction Pin Name Pin No I/O Pin Description I2C_SDA0 115 DIO I2C data I2C_SCL0 112 DO I2C clock I2C_SDA1 268 DIO I2C data used for PCIe switch I2C_SCL1 269 DO I2C clock used for PCIe switch 5.14 I2S Interface The FG160 module supports one I2S interface and default mode is PCM. The default sampling rate is 8KHz. Table 34. I2S interface definition Pin Name Pin No I/O Pin Description I2S0_DO 103 DO I2S data output signal, can be defined as PCM_OUT I2S0_DI 104 DI I2S data input signal, can be defined as PCM_IN I2S0_BCK 101 DO I2S0_LRCK 105 DO I2S data bit clock signal, can be defined as PCM_CLK I2S frame clock signal, can be defined as PCM_SYNC I2S0_MCK 94 DO I2S main clock output, used for external audio codec 5.15 UART Interface The FG160 module supports three UART interfaces which defined in the following tables. Copyright Fibocom Wireless Inc. 70 5 Interface Introduction Table 35. UART interface 1 Pin Name Pin No I/O Pin Description DBG_UART_TX 129 DO UART transmit signal DBG_UART_RX 126 DI UART receive signal Table 36. UART interface 2 Pin Name Pin No I/O Pin Description UART_CTS UART_RTS UART_TX UART_RX 79 64 77 73 DI DO DO DI UART receive ready signal UART transmit request signal UART transmit signal UART receive signal Table 37. UART interface 3 Pin Name Pin No I/O Pin Description BT_UTXD 135 DO UART transmit signal, Reserved for BT BT_URXD 138 DI UART receive signal, Reserved for BT BT_URTS 282 DO UART transmit request signal, Reserved for BT BT_UCTS 283 DI UART receive ready signal, Reserved for BT UART interface 1 is debug UART port, used to access the main chip kernel and print log information, and default baud rate is 115200. UART interface 2 is general UART port used to send AT command and transmission of information UART interface 3 is BT UART port, used to transmission of BT information Copyright Fibocom Wireless Inc. 71 5 Interface Introduction 5.16 SPI Interface The FG160 module supports 1 SPI interface, works in master mode, and the clock supports up to 50MHz. Table 38. SPI interface definition Pin Name Pin No I/O Pin Description SPI0_MISO SPI0_MOSI SPI0_CSB SPI0_CLK 5 8 6 9 DI DO DO DO SPI interface input signal SPI interface output signal SPI interface chip select signal SPI interface clock signal 5.17 Other Interfaces For the application of other interfaces, please refer to the recommended design. If the application scenario and the recommended design are not consistent, please contact our technicians for confirmation. Copyright Fibocom Wireless Inc. 72 6 Electrostatic Protection 6 Electrostatic Protection In the application of the module, due to static electricity generated by human body and charged friction between micro-electronics, etc. discharging to the module through various channels that may cause damage, so ESD protection should be taken seriously attention. In the process of R&D, production assembly and testing, especially in product design, ESD protection measures should be taken. For example, anti-static protection should be added at the designed circuit interface and the points susceptible to electrostatic discharge or impact. Anti-static gloves should be worn during production. ESD performance parameters are as follows (temperature: 25 C, humidity: 45%) Table 39. ESD performance Test Point Contact Discharge Air Discharge Unit GND TBD RF Antenna Interface TBD GNSS Antenna Interface TBD TBD
KV KV KV The data is based on the test of FIBOCOM ADP-FG160-NA-00-00 development board. ESD performance is related to PCB design. Pay special attention to the protection of important control signals such as reset signals and the preservation of the complete ground plane. Copyright Fibocom Wireless Inc. 73 7 Thermal Design 7 Thermal Design FG160 is designed to work on an extreme temperature range, to make sure the module can work properly for a long time and achieve a better performance on conditions such as maximum power or high data transmission. Copyright Fibocom Wireless Inc. 74 8 Structural Specification 8 Structural Specification 8.1 Product Appearance The appearance of the FG160 module product is as shown:
Figure 20. Module product appearance 8.2 Dimension of Structure The structural dimensions of the FG160 module are shown in the following figure:
Figure 21. Structure size chart Copyright Fibocom Wireless Inc. 75 8 Structural Specification Unmarked dimensional tolerances are 0.1 mm. 8.3 Storage Refer to FIBOCOM FG160-NA Series SMT Design Guide. 8.4 Packing Refer to FIBOCOM FG160-NA Series SMT Design Guide. Copyright Fibocom Wireless Inc. 76