FCC ID: U8D-FBL700BC-01 Bluetooth Embedded Modul

 

OEM/Integrators Installation Manual Bluetooth Low Energy Embedded Module FBL700BC User Guide Version 1.0 FIRMTECH Co., Ltd. Homepage : http://www.firmtech.co.kr Cafe : http://cafe.naver.com/firmtech7 Mail : contact@firmtech.co.kr Tel : 031-719-4812 Fax : 031-719-4834 FBL700BC User Guide Version 1.0 Revision History Revision History Revision Ver 1.0 Date Change Descriptions 2020-09-10

- Write a draft 2 / 12 FBL700BC User Guide Version 1.0

(C) Copyright FIRMTECH Co., Ltd. 2005

(C) Copyright FIRMTECH Co., Ltd. 2005 All rights reserved The products and operation descriptions contained herein shall be protected by copyright law. Any part or whole of products or operation description shall not be copied, reproduced, translated, nor transformed into readable form by electronic device or machines, without prior consent in writing by FIRMTECH Co., Ltd. There might be some misprinting or technical faults in the products and operation description which are subject to change without prior notice. 3 / 12 FBL700BC User Guide Version 1.0 List of Content List of Content Revision History ........................................................................................................................... 2

(C) Copyright FIRMTECH Co., Ltd. 2005 ....................................................................................... 3 List of Content ............................................................................................................................. 4 1 What is Bluetooth? ................................................................................................................... 5 1.1 Features of Bluetooth ...................................................................................................... 5 1.2 Operation of Bluetooth ................................................................................................... 5 2 Product Overview ..................................................................................................................... 6 3 Product Components ................................................................................................................ 6 3.1 FBL700BC ....................................................................................................................... 6 3.2 Interface Board (Option) ................................................................................................. 6 4 FBL700BC Appearance ............................................................................................................. 7 4.1 FBL700BC Dimension ...................................................................................................... 7 4.2 FBL700BC PIN Assign ...................................................................................................... 8 5 Interface (Pin Connection) ........................................................................................................ 9 6 Interface Board (Jig Board) ...................................................................................................... 10 7 Specification of FBL700BC ...................................................................................................... 11 8 Current Consumption ............................................................................................................. 12 9 Preliminary Product Components ............................................................................................ 12 4 / 12 FBL700BC User Guide Version 1.0 1 What is Bluetooth?

1 What is Bluetooth?

1.1 Features of Bluetooth Objectives of Bluetooth : To Realize Wireless Communication for Short Distance with Low Power Consumption, High Reliability, and Low Cost. Frequency in Use: To Use ISM(Industrial, Scientific, Medical) Band which does not require any permission to use.

2.400 2.4835 GHz, 79 channels 2.465 2.4835 GHz, 23 channels (in France)

Transmission Rate : 1Mbps ~ 3Mbps Transmission Output : 1mW (10m, Class2), 100mW (100m Class1) Network Configuration : Configured with Master and Slave relation. A Bluetooth unit shall allow simultaneous connections up to 7 devices (in case of ACL). Reliability : To Guarantee stable wireless communication even under severe noisy environment through adopting the technique of FHSS (Frequency Hopping Spread Spectrum). 1.2 Operation of Bluetooth

<Feature 1-1 Bluetooth Operation>

Bluetooth operates based on the connection between Master and Slave. Masters are simply supposed to do Inquiry and Page. Slaves are supposed to do Inquiry Scan and Page Scan. If a Master finds a Slave and so inquiry is successful, a Slave responds to the Master with its information. Interconnection between the Master and the Slave is achieved only if the information from the Slave is corresponded with the Master, and the Slave sends data to the Master. 5 / 12 FBL700BC User Guide Version 1.0 2 Product Overview 2 Product Overview Major Features of FBL700BC 1. Bluetooth Specification 5.1 Low Energy Support 2. Easily Applicable to the Product with 8 Pins Header Type 3. Support AT Command, and capable to control FBL700BC by using AT Command 4. UART can be used as an interface We request the new users of FBL700BC to read the information on this description carefully before they start to use the products. 3 Product Components 3.1 FBL700BC FBL700BC

(On-board Chip Antenna) MODEL PICTURE QTY (EA)

<Table 3-1 Basic Components of FBL700BC >

3.2 Interface Board (Option) MODEL PICTURE QTY (EA) 1 1 Interface Board If you find any of above components is defective, or not included in the package, please contact the seller

<Table 3-2 Components of Interface Board >

you purchased. 6 / 12 FBL700BC User Guide Version 1.0 4 FBL700BC Appearance 4 FBL700BC Appearance 4.1 FBL700BC Dimension

[Top View]

[Side View]

<Figure 4-1 FBL700BC Dimension>

7 / 12 FBL700BC User Guide Version 1.0 4 FBL700BC Appearance 4.2 FBL700BC PIN Assign NO Name of Signal I / O Level

<Figure 4-2 FBL700BC PIN Assign>

Features Ground DC 3.3V Operation Status Factory Reset Transfer Data (Data out) Received Data (Data in)

<Table 4-1 Pin Description>

CONFIG_SELECT Configuration Select Power Save Control Power Save On/Off Control Power Save Status Power Save Operation Status 1 2 3 4 5 6 7 8 GND VCC STATUS FA_SET TXD RXD TTL TTL TTL TTL TTL TTL Output Input Input Output Output Input

- STATUS port To be used to monitor the status of FBL700BC It keeps LOW (0V) when the Bluetooth wireless section is connected smoothly and both devices can communicate In standby mode for connection with Bluetooth, or connection trial, or searching for around Bluetooth device will repeat LOW and HIGH. 8 / 12 FBL700BC User Guide Version 1.0 5 Interface (Pin Connection)

-FA_SET / CONFIG_SELECT If you want to enter the configuration mode, turn on the power to the module while inputting LOW Signal

(0V) to Configuration Select (No. 4 pin). If you want to change to the factory default value, enter the LOW Signal (0V) for more than 4 seconds into the Factory Reset (Pin No. 4) after entering the configuration mode and all setting values will be changed to the original purchase status.

- Power Save Control Port Select FBL700BC's Power Save ON/OFF

- Power Save Status Port It is used to monitor the power save status of FBL700BC. 5 Interface (Pin Connection)

<Figure 5-1 Pin Connection Control>

9 / 12 FBL700BC User Guide Version 1.0 6 Interface Board (Jig Board) 6 Interface Board (Jig Board)

<Figure 6-1 Interface Board>

No. Title Description 1 UART communication & power port UART communication interface terminal for PC connection 5V power input terminal 2 Power ON/OFF Switch Interface Board Power On/Off Switch 3 STATUS LED Configuration Select Switch 4 Factory Reset Switch USB LED: USB port status LED POWER LED: 3.3V power supply LED STATUS LED: Status confirmation LED RX LED: UART input confirmation LED TX LED: UART Output confirmation LED Switch for enter the configuration mode The configuration entry mode method is as follows. Hold CONFIG switch and power on.. Enter the configuration mode completed Factory initialization switch The Factory initialization is as follows. Enter the configuration mode After entering configuration mode, press the FASET switch Hold for 4 seconds. Factory initialization completed 5 Connection connector FBL700BC Connection connector

<Table 6-1 PC Interface Board>

10 / 12 FBL700BC User Guide Version 1.0 7 Specification of FBL700BC 7 Specification of FBL700BC No. Part Specification Bluetooth Spec. Bluetooth Specification 5.1 Low Energy Support Communication distance 10 M Frequency Range 2402 ~ 2480 MHz ISM Band Sensitivity Transmit Power Size

-79dBm (Typical) 0dBm(Typical) 18 x 20 mm Support Low Energy Service Serial Service Input Power 3.3V Current Consumption

(Max) 10 Temperature Operating

-10 ~ 50 Limit Operating

-30 ~ 80 Communication Speed 9,600bps 115,200bps Antenna Interface Chip Antenna UART (TTL Level)

<Table 7-1 FBL700BC Specification>

1 2 3 4 5 6 7 8 9 11 12 13 11 / 12 20mA FBL700BC User Guide Version 1.0 8 Current Consumption 8 Current Consumption Status Status Ready Advertising Connection Ready Scanning Connection

< Table 8-1 Peripheral Current Consumption of FBL700BC>

Current Consumption (mA) MIN MAX AVG 0.73 0.77 0.73 0.82 0.99 0.88 1.15 1.21 1.17 Current Consumption (mA) MIN MAX AVG 0.73 0.77 0.73 10.40 10.53 10.47 1.11 1.17 1.13

< Table 8-2 Central Current Consumption of FBL700BC>

TEST CONDITIONS Baud Rate : 9600 bps, Input Voltage : DC 3.3V The power consumption will change depending on transmission speed and volume of data. 9 Preliminary Product Components The preliminary value of product is set as on the <Table 9-1>. Please be sure of basic set value and so on before using the product. Type Set Value Device Name FBL700(XXXXXX) Uart (baud rate-data bit-parity bit-stop bit) 9600-8-N-1 ROLE Peripheral

<Table 9-1 Preliminary Configuration Setting Value for FBL700BC>

FBL700BCcan change the setting value by using AT command of Bluetooth setting. 12 / 12 FCCMODULARAPPROVALINFORMATIONEXAMPLESforManual ThisdevicecomplieswithPart15oftheFCCRules.Operationissubjecttothefollowingtwoconditions:

(1)Thisdevicemaynotcauseharmfulinterference.

(2)Thisdevicemustacceptanyinterferencereceived,includinginterferencethatmaycause undesiredoperation. CAUTION:Changesormodificationsnotexpresslyapprovedbythepartyresponsiblefor compliancecouldvoidtheuser'sauthoritytooperatetheequipment. NOTE:ThisequipmenthasbeentestedandfoundtocomplywiththelimitsforaClassBdigitaldevice, pursuanttoPart15oftheFCCRules.Theselimitsaredesignedtoprovidereasonableprotectionagainst harmfulinterferenceinaresidentialinstallation.Thisequipmentgeneratesusesandcanradiateradio frequencyenergyand,ifnotinstalledandusedinaccordancewiththeinstructions,maycauseharmful interferencetoradiocommunications.However,thereisnoguaranteethatinterferencewillnotoccur in a particular installation. If this equipment does cause harmful interference to radio or television reception,whichcanbedeterminedbyturningtheequipmentoffandon,theuserisencouragedtotry tocorrecttheinterferencebyoneormoreofthefollowingmeasures:

Reorientorrelocatethereceivingantenna. Increasetheseparationbetweentheequipmentandreceiver. Connecttheequipmentintoanoutletonacircuitdifferentfromthattowhichthereceiveris connected. Consultthedealeroranexperiencedradio/TVtechnicianforhelp. FCCRadiationExposureStatement:

ThisequipmentcomplieswithFCCradiationexposurelimitssetforthforanuncontrolledenvironment. Thisequipmentshouldbeinstalledandoperatedwithminimumdistance20cmbetweentheradiator&

yourbody. OEMINTEGRATIONINSTRUCTIONS:

ThisdeviceisintendedonlyforOEMintegratorsunderthefollowingconditions:

The module must be installed in the host equipment such that 20cm is maintained between the antenna and users, and the transmitter module may not be colocated with any other transmitter or antenna. The module shall be only used with the internal onboard antenna that has been originally tested and certified with this module. External antennas are not supported. As long as these 3 conditionsabovearemet,furthertransmittertestwillnotberequired. However, the OEM integrator is still responsible for testing their endproduct for any additional compliancerequirementsrequiredwiththismoduleinstalled(forexample,digitaldeviceemissions,PC peripheral requirements, etc.). The endproduct may need Verification testing, Declaration of Conformitytesting,aPermissiveClassIIChangeornewCertification.PleaseinvolveaFCCcertification specialistinordertodeterminewhatwillbeexactlyapplicablefortheendproduct. Validityofusingthemodulecertification:

In the event that these conditions cannot be met (for example certain laptop configurations or co locationwithanothertransmitter),thentheFCCauthorizationforthismoduleincombinationwiththe hostequipmentisnolongerconsideredvalidandtheFCCIDofthemodulecannotbeusedonthefinal product. In these circumstances, the OEM integrator will be responsible for reevaluating the end product (including the transmitter) and obtaining a separate FCC authorization. In such cases, please involve a FCC certification specialist in order to determine if a Permissive Class II Change or new Certificationisrequired. ThesoftwareprovidedforfirmwareupgradewillnotbecapabletoaffectanyRFparametersascertified fortheFCCforthismodule,inordertopreventcomplianceissues. UpgradeFirmware:

Endproductlabeling:

Thistransmittermoduleisauthorizedonlyforuseindevicewheretheantennamaybeinstalledsuch that20cmmaybemaintainedbetweentheantennaandusers.Thefinalendproductmustbelabeledin avisible area with the following:

U8D-FBL700BC-01. Contains FCC ID:

Informationthatmustbeplacedintheendusermanual:

TheOEMintegratorhastobeawarenottoprovideinformationtotheenduserregardinghowtoinstall orremovethisRFmoduleintheuser'smanualoftheendproductwhichintegratesthismodule.The endusermanualshallincludeallrequiredregulatoryinformation/warningasshowinthismanual.

 

 

 

 

 

 

 

 

 

 

FCC ID: U8D-FBL700BC-01 SAMPLE LABEL & LOCATION Firmtech Co., Ltd M/N : FBL700BC-01 FCC ID: U8D-FBL700BC-01 Copyright 2020, KRL Co., Ltd.

 

 

 

 

 

 

Firmtech Co., Ltd Federal Communications Commission Authorization and Evaluation Division 1435 Oakland Mills Road Columbia, MD 21046 Date: 2020-09-22 SUBJECT: FCC Application for (FCC ID: U8D-FBL700BC-01) To Whom It May Concern:

We, the undersigned, hereby authorize David Zhang in Vista Laboratories, Inc. on our behalf, to apply to the Federal Communications Commission on our equipment. Any and all acts carried out by Vista Laboratories, Inc. on our behalf shall have the same effect as acts of our own. This is to advise that we are in full compliance with the Anti- Drug Abuse Act. We, the applicant, are not subject to a denial of federal benefits pursuant to Section 5301 of the Anti-Drug Act of 1988, 21 USC853a, and no party to the application is subject to a denial of federal benefits pursuant to that section. Sincerely,

(Must be signed by the person that is listed on the FCC Website) Clients signature:

Clients name & title: Taek Jong Roh / Manager Contact information / address: +82-31-719-4812 /

807, 555, Dunchon-daero, Jungwon-gu, Seongnam-si, Gyeonggi-do, Korea Date: 04/17/2018 VCB_F-01: Operating Procedures Form FCC Authorization v02 Page 1 of 1

 

 

Firmtech Co., Ltd Federal Communications Commission Authorization and Evaluation Division Confidentiality Request regarding application for certification of FCC ID: U8D-FBL700BC-

01 Pursuant to Sections 0.457 and 0.459 of the Commissions Rules, we hereby request confidential treatment of information accompanying this application as outlined below:

Type of Confidentiality Requested Short Term Short Term Short Term Short Term Short Term Short Term Short Term Short Term

*Requires further justification before permanent confidentiality will be allowed. The above materials contain trade secrets and proprietary information not customarily released to the public. The public disclosure of these materials may be harmful to the applicant and provide unjustified benefits to its competitors. Permanent Confidentiality:

The applicant requests the exhibits listed above as permanently confidential be withheld from public review due to materials that contain trade secrets and proprietary information not customarily released to the public. Short-Term Confidentiality:

Pursuant to DA04-1705 June 15, 2004 of the Commissions public notice, we also request temporary confidential treatment of information accompanying this application as outlined below for an initial period of 180 days. Sincerely, Exhibit Type Block Diagrams External Photos Internal Photos Operation Description Parts List/BOM Schematics Test Setup Photos User manual Permanent Permanent*

Permanent Permanent Permanent Permanent*

Clients signature:

Clients name & title: Taek Jong Roh / Manager Contact information / address: +82-31-719-4812 /

807, 555, Dunchon-daero, Jungwon-gu, Seongnam-si, Gyeonggi-do, Korea Date: 04/17/2018 VCB_F-01: Operating Procedures Form FCC Confidentiality v03 Page 1 of 1

 

 

Firmtech Co., Ltd MODULAR APPROVAL LETTER

(Product name) FCC ID : U8D-FBL700BC-01, is seeking FCC Authorization as a Single Modular transmitter /

Single Limited Modular Approval (Please check one) The EUT meets the requirements for Single Modular approval / Single Limited Modular Approval (please check one) as detailed in KDB 996369. Compliance to each of the requirements is described below:

Modular Approval Requirement Yes No Please provide a detailed explanation if the answer is No.

(i) The radio elements of the modular transmitter must have their own shielding. The physical crystal and tuning capacitors may be located external to the shielded radio elements.

(ii) The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with part 15 requirements under conditions of excessive data rates or over-modulation.

(iii) The modular transmitter must have its own power supply regulation.

(iv) The modular transmitter must comply with the antenna and transmission system requirements of 15.203, 15.204(b) and 15.204(c). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph (b) of this section.

(v) The modular transmitter must be tested in a stand-alone configuration

(vi) The modular transmitter must be equipped with either a permanently affixed label or must be capable of electronically displaying its FCC identification number.

(vii) The modular transmitter must comply with any specific rules or operating requirements that ordinarily apply to a complete transmitter and the manufacturer must provide adequate instructions along with the module to explain any such requirements. A copy of these instructions must be included in the application for equipment authorization.

(viii) The modular transmitter must comply with any applicable RF exposure requirements in its final configuration. X X X X X X X X Clients signature:

Clients name & title: Taek Jong Roh / Manager Contact information / address: +82-31-719-4812 / 807, 555, Dunchon-daero, Jungwon-gu, Seongnam-si, Gyeonggi-do, Korea Date: 04/17/2018 VCB_F-01: Operating Procedures Form FCC Modular v02 Page 1 of 1

 

 

Firmtech Co., Ltd 807, 555, Dunchon-daero, Jungwon-gu, Seongnam-si, Gyeonggi-do, Korea Tel. +82-31-719-4812 Sep 22, 2019 Vista Laboratories, Inc. 1261 Puerta Del Sol San Clemente, CA 92673 Family Model Letter The difference between basic and derivative model is External Type. Header Type SMD Type FBL700BC-01, FBL700BC-02, FBL700BC-

03, FBL700BC-11, FBL700BC-12, FBL700BC-13, FBL700BC-21, FBL700BC-

22, FBL700BC-23 FBL701BC-01, FBL701BC-02, FBL701BC-

03, FBL701BC-11, FBL701BC-12, FBL701BC-13, FBL701BC-21, FBL701BC-

22, FBL701BC-23 Sincerely, Clients signature:

Clients name & title: Taek Jong, Lho/ Manager Contact information / address: +82-31-719-4812/ 807, 555, Dunchon-daero, Jungwon-gu, Seongnam-si, Gyeonggi-do, Korea (Sunil Technopia)

 

 

nRF52833 Product Specification v1.3 4452_021 v1.3 / 2020-08-07 Feature list Features:

Bluetooth 5.1, IEEE 802.15.4-2006, 2.4 GHz transceiver

-96 dBm sensitivity in 1 Mbps Bluetooth low energy mode 512 kB flash and 128 kB RAM Advanced on-chip interfaces

-103 dBm sensitivity in 125 kbps Bluetooth low energy mode (long range) USB 2.0 full speed (12 Mbps) controller

-20 to +8 dBm TX power, configurable in 4 dB steps High-speed 32 MHz SPI On-air compatible with nRF52, nRF51, nRF24L, and nRF24AP Series Type 2 near field communication (NFC-A) tag with wake-on Supported data rates:

field Bluetooth 5.1 2 Mbps, 1 Mbps, 500 kbps, and 125 kbps Touch-to-pair support IEEE 802.15.4-2006 250 kbps Proprietary 2.4 GHz 2 Mbps, 1 Mbps Programmable peripheral interconnect (PPI) 42 general purpose I/O pins Angle-of-arrival (AoA) and angle-of-departure (AoD) direction finding using EasyDMA automated data transfer between memory and Bluetooth Single-ended antenna output (on-chip balun) Nordic SoftDevice ready with support for concurrent multiprotocol 128-bit AES/ECB/CCM/AAR co-processor (on-the-fly packet encryption) 12-bit, 200 ksps ADC 8 configurable channels with peripherals programmable gain 64 level comparator mode Temperature sensor 15 level low-power comparator with wake-up from System OFF 4x four channel pulse width modulator (PWM) unit with EasyDMA Audio peripherals I2S, digital microphone interface (PDM) 5x 32-bit timer with counter mode Up to 4x SPI master/3x SPI slave with EasyDMA Up to 2x I2C compatible two-wire master/slave 2x UART (CTS/RTS) with EasyDMA Quadrature decoder (QDEC) 3x real-time counter (RTC) Single crystal operation Operating temperature from -40 to 105 C Package variants aQFN 73 package, 7 x 7 mm QFN40 package, 5 x 5 mm 4.9 mA peak current in TX (0 dBm) 4.6 mA peak current in RX RSSI (1 dB resolution) ARM Cortex

-M4 32-bit processor with FPU, 64 MHz 217 EEMBC CoreMark score running from flash memory 52 A/MHz running CoreMark from flash memory 38 A/MHz running CoreMark from RAM Watchpoint and trace debug modules (DWT, ETM, and ITM) Serial wire debug (SWD) Rich set of security features Secure boot ready Flash access control list (ACL) Debug control and configuration Access port protection (CTRL-AP) Secure erase Flexible power management 1.7 V to 5.5 V supply voltage range On-chip DC/DC and LDO regulators with automated low current modes WLCSP package, 3.175 x 3.175 mm Automated peripheral power management Fast wake-up using 64 MHz internal oscillator 0.6 A at 3 V in System OFF mode, no RAM retention 1.5 A at 3 V in System ON mode, no RAM retention, wake on RTC 4452_021 v1.3 ii Feature list Advanced computer peripherals and I/O devices Internet of things (IoT) Applications:

Mouse Keyboard Multi-touch trackpad Advanced wearables Health/fitness sensor and monitor devices Wireless payment enabled devices Smart home sensors and controllers Industrial IoT sensors and controllers Interactive entertainment devices Remote controls Gaming controllers 4452_021 v1.3 iii Contents Feature list. 1 Revision history. 2.4.1 DUMMY . 2 About this document. 2.1 Document status . 2.2 Peripheral chapters . 2.3 Register tables . 2.3.1 Fields and values . 2.3.2 Permissions . 2.4 Registers . 3 Block diagram. 4 Core components. 4.1 CPU . 4.2 Memory . 4.1.1 Floating point interrupt . 4.1.2 CPU and support module configuration . 4.1.3 Electrical specification . 4.2.1 RAM - Random access memory . 4.2.2 Flash - Non-volatile memory . 4.2.3 Memory map . 4.2.4 Instantiation . 4.3 NVMC Non-volatile memory controller . 4.3.1 Writing to flash . 4.3.2 Erasing a page in flash . 4.3.3 Writing to user information configuration registers (UICR) . 4.3.4 Erasing user information configuration registers (UICR) . 4.3.5 Erase all . 4.3.6 Access port protection behavior . 4.3.7 NVMC power failure protection . 4.3.8 Partial erase of a page in flash . 4.3.9 Cache . 4.3.10 Registers . 4.3.11 Electrical specification . 4.4.1 Registers . 4.4 FICR Factory information configuration registers . 4.5 UICR User information configuration registers . 4.5.1 Registers . 4.6 EasyDMA . 4.7 AHB multilayer . 4.8 Debug and trace . 4.6.1 EasyDMA error handling . 4.6.2 EasyDMA array list . 4.8.1 DAP - Debug access port . 4.8.2 CTRL-AP - Control access port . 4.8.3 Debug interface mode . 4.8.4 Real-time debug . 4452_021 v1.3 iv ii 12

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. 4.8.5 Trace . 5 Power and clock management. 5.1 Power management unit (PMU) . 5.2 Current consumption . 5.2.1 Electrical specification . 51

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. 5.3 POWER Power supply . 5.3.1 Main supply . 5.3.2 USB supply . 5.3.3 System OFF mode . 5.3.4 System ON mode . 5.3.5 RAM power control . 5.3.6 Reset . 5.3.7 Registers . 5.3.8 Electrical specification . 5.4 CLOCK Clock control . 5.4.1 HFCLK controller . 5.4.2 LFCLK controller . 5.4.3 Registers . 5.4.4 Electrical specification . 6

. Peripherals. 6.1 Peripheral interface . 6.1.1 Peripheral ID . 6.1.2 Peripherals with shared ID . 6.1.3 Peripheral registers . 6.1.4 Bit set and clear . 6.1.5 Tasks . 6.1.6 Events . 6.1.7 Shortcuts . 6.1.8 Interrupts . 96 96

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. 99 6.2 AAR Accelerated address resolver . 99

. 6.2.1 EasyDMA . 6.2.2 Resolving a resolvable address . 99

. 6.2.3 Use case example for chaining RADIO packet reception with address resolution using AAR . 100 100

. 6.2.4 IRK data structure . 100 6.2.5 Registers . 104 6.2.6 Electrical specification . 104 6.3 ACL Access control lists . 106

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. 122 6.4.1 Key-steam generation . 6.4.2 Encryption . 6.4.3 Decryption . 6.4.4 AES CCM and RADIO concurrent operation . 6.4.5 Encrypting packets on-the-fly in radio transmit mode . 6.4.6 Decrypting packets on-the-fly in radio receive mode . 6.4.7 CCM data structure . 6.4.8 EasyDMA and ERROR event . 6.4.9 Registers . 6.4.10 Electrical specification . 6.4 CCM AES CCM mode encryption . 6.5 COMP Comparator . 6.5.1 Differential mode . 6.3.1 Registers . 4452_021 v1.3 v 6.5.2 Single-ended mode . 6.5.3 Registers . 6.5.4 Electrical specification . 6.6 ECB AES electronic codebook mode encryption . 6.6.1 Shared resources . 6.6.2 EasyDMA . 6.6.3 ECB data structure . 6.6.4 Registers . 6.6.5 Electrical specification . 6.7 EGU Event generator unit . 6.7.1 Registers . 6.7.2 Electrical specification . 6.8 GPIO General purpose input/output . 6.8.1 Pin configuration . 6.8.2 Registers . 6.8.3 Electrical specification . 6.9 GPIOTE GPIO tasks and events . 6.9.1 Pin events and tasks . 6.9.2 Port event . 6.9.3 Tasks and events pin configuration . 6.9.4 Registers . 6.9.5 Electrical specification . 6.10 I2S Inter-IC sound interface . 6.10.1 Mode . 6.10.2 Transmitting and receiving . 6.10.3 Left right clock (LRCK) . 6.10.4 Serial clock (SCK) . 6.10.5 Master clock (MCK) . 6.10.6 Width, alignment and format . 6.10.7 EasyDMA . 6.10.8 Module operation . 6.10.9 Pin configuration . 6.10.10 Registers . 6.10.11 Electrical specification . 6.11 LPCOMP Low-power comparator . 6.11.1 Shared resources . 6.11.2 Pin configuration . 6.11.3 Registers . 6.11.4 Electrical specification . 6.12 MWU Memory watch unit . 6.13 NFCT Near field communication tag . 6.12.1 Registers . 6.13.1 Overview . 6.13.2 Operating states . 6.13.3 Pin configuration . 6.13.4 EasyDMA . 6.13.5 Frame assembler . 6.13.6 Frame disassembler . 6.13.7 Frame timing controller . 6.13.8 Collision resolution . 6.13.9 Antenna interface . 6.13.10 NFCT antenna recommendations . 6.13.11 Battery protection . 6.13.12 Digital Modulation Signal . 122 124

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. 198 199 200 201 202 203 203 204 204 4452_021 v1.3 vi 6.13.13 References . 6.13.14 Registers . 6.13.15 Electrical specification . 6.14 PDM Pulse density modulation interface . 6.14.1 Master clock generator . 6.14.2 Module operation . 6.14.3 Decimation filter . 6.14.4 EasyDMA . 6.14.5 Hardware example . 6.14.6 Pin configuration . 6.14.7 Registers . 6.14.8 Electrical specification . 6.15 PPI Programmable peripheral interconnect . 6.15.1 Pre-programmed channels . 6.15.2 Registers . 6.16 PWM Pulse width modulation . 6.16.1 Wave counter . 6.16.2 Decoder with EasyDMA . 6.16.3 Limitations . 6.16.4 Pin configuration . 6.16.5 Registers . 6.17 QDEC Quadrature decoder . 6.17.1 Sampling and decoding . 6.17.2 LED output . 6.17.3 Debounce filters . 6.17.4 Accumulators . 6.17.5 Output/input pins . 6.17.6 Pin configuration . 6.17.7 Registers . 6.17.8 Electrical specification . 6.18 RADIO 2.4 GHz radio . 6.18.1 Packet configuration . 6.18.2 Address configuration . 6.18.3 Data whitening . 6.18.4 CRC . 6.18.5 Radio states . 6.18.6 Transmit sequence . 6.18.7 Receive sequence . 6.18.8 Received signal strength indicator (RSSI) . 6.18.9 Interframe spacing (IFS) . 6.18.10 Device address match . 6.18.11 Bit counter . 6.18.12 Direction finding . 6.18.13 IEEE 802.15.4 operation . 6.18.14 EasyDMA . 6.18.15 Registers . 6.18.16 Electrical specification . 6.19 RNG Random number generator . 6.19.1 Bias correction . 6.19.2 Speed . 6.19.3 Registers . 6.19.4 Electrical specification . 6.20 RTC Real-time counter . 6.20.1 Clock source . 205 205

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. 6.20.2 Resolution versus overflow and the PRESCALER . 6.20.3 COUNTER register . 6.20.4 Overflow features . 6.20.5 TICK event . 6.20.6 Event control feature . 6.20.7 Compare feature . 6.20.8 TASK and EVENT jitter/delay . 6.20.9 Reading the COUNTER register . 6.20.10 Registers . 6.20.11 Electrical specification . 6.21 SAADC Successive approximation analog-to-digital converter . 6.21.1 Input configuration . 6.21.2 Reference voltage and gain settings . 6.21.3 Digital output . 6.21.4 EasyDMA . 6.21.5 Continuous sampling . 6.21.6 Oversampling . 6.21.7 Event monitoring using limits . 6.21.8 Calibration . 6.21.9 Registers . 6.21.10 Electrical specification . 6.22 SPI Serial peripheral interface master . 6.22.1 Functional description . 6.22.2 Registers . 6.22.3 Electrical specification . 6.23 SPIM Serial peripheral interface master with EasyDMA . 6.23.1 SPI master transaction sequence . 6.23.2 D/CX functionality . 6.23.3 Pin configuration . 6.23.4 EasyDMA . 6.23.5 Low power . 6.23.6 Registers . 6.23.7 Electrical specification . 6.24 SPIS Serial peripheral interface slave with EasyDMA . 6.24.1 Shared resources . 6.24.2 EasyDMA . 6.24.3 SPI slave operation . 6.24.4 Pin configuration . 6.24.5 Registers . 6.24.6 Electrical specification . 6.25 SWI Software interrupts . 6.26 TEMP Temperature sensor . 6.26.1 Registers . 6.26.2 Electrical specification . 6.25.1 Registers . 6.27 TWI I2C compatible two-wire interface . 6.27.1 Functional description . 6.27.2 Master mode pin configuration . 6.27.3 Shared resources . 6.27.4 Master write sequence . 6.27.5 Master read sequence . 6.27.6 Master repeated start sequence . 6.27.7 Low power . 6.27.8 Registers . 346

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. 4452_021 v1.3 viii 6.27.9 Electrical specification . 6.28 TIMER Timer/counter . 6.28.1 Capture . 6.28.2 Compare . 6.28.3 Task delays . 6.28.4 Task priority . 6.28.5 Registers . 6.29 TWIM I2C compatible two-wire interface master with EasyDMA . 6.29.1 EasyDMA . 6.29.2 Master write sequence . 6.29.3 Master read sequence . 6.29.4 Master repeated start sequence . 6.29.5 Low power . 6.29.6 Master mode pin configuration . 6.29.7 Registers . 6.29.8 Electrical specification . 6.29.9 Pullup resistor . 6.30 TWIS I2C compatible two-wire interface slave with EasyDMA . 6.30.1 EasyDMA . 6.30.2 TWI slave responding to a read command . 6.30.3 TWI slave responding to a write command . 6.30.4 Master repeated start sequence . 6.30.5 Terminating an ongoing TWI transaction . 6.30.6 Low power . 6.30.7 Slave mode pin configuration . 6.30.8 Registers . 6.30.9 Electrical specification . 6.31 UART Universal asynchronous receiver/transmitter . 6.31.1 Functional description . 6.31.2 Pin configuration . 6.31.3 Shared resources . 6.31.4 Transmission . 6.31.5 Reception . 6.31.6 Suspending the UART . 6.31.7 Error conditions . 6.31.8 Using the UART without flow control . 6.31.9 Parity and stop bit configuration . 6.31.10 Registers . 6.31.11 Electrical specification . 6.32 UARTE Universal asynchronous receiver/transmitter with EasyDMA . 6.32.1 EasyDMA . 6.32.2 Transmission . 6.32.3 Reception . 6.32.4 Error conditions . 6.32.5 Using the UARTE without flow control . 6.32.6 Parity and stop bit configuration . 6.32.7 Low power . 6.32.8 Pin configuration . 6.32.9 Registers . 6.32.10 Electrical specification . 6.33 USBD Universal serial bus device . 6.33.1 USB device states . 6.33.2 USB terminology . 6.33.3 USB pins . 4452_021 v1.3 ix

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. 6.33.4 USBD power-up sequence . 6.33.5 USB pull-up . 6.33.6 USB reset . 6.33.7 USB suspend and resume . 6.33.8 EasyDMA . 6.33.9 Control transfers . 6.33.10 Bulk and interrupt transactions . 6.33.11 Isochronous transactions . 6.33.12 USB register access limitations . 6.33.13 Registers . 6.33.14 Electrical specification . 6.34 WDT Watchdog timer . 6.34.1 Reload criteria . 6.34.2 Temporarily pausing the watchdog . 6.34.3 Watchdog reset . 6.34.4 Registers . 6.34.5 Electrical specification . 7 Hardware and layout. 7.1 Pin assignments . 7.2 Mechanical specifications . 7.1.1 aQFN73 ball assignments . 7.1.2 QFN40 pin assignments . 7.1.3 WLCSP ball assignments . 7.2.1 aQFN73 7 x 7 mm package . 7.2.2 QFN40 5 x 5 mm package . 7.2.3 WLCSP 3.175 x 3.175 mm package . 7.3 Reference circuitry . 7.3.1 Circuit configuration no. 1 for QIAA aQFN73 . 7.3.2 Circuit configuration no. 2 for QIAA aQFN73 . 7.3.3 Circuit configuration no. 3 for QIAA aQFN73 . 7.3.4 Circuit configuration no. 4 for QIAA aQFN73 . 7.3.5 Circuit configuration no. 5 for QIAA aQFN73 . 7.3.6 Circuit configuration no. 6 for QIAA aQFN73 . 7.3.7 Circuit configuration no. 1 for QDAA QFN40 . 7.3.8 Circuit configuration no. 2 for QDAA QFN40 . 7.3.9 Circuit configuration no. 3 for QDAA QFN40 . 7.3.10 Circuit configuration no. 4 for QDAA QFN40 . 7.3.11 Circuit configuration no. 5 for QDAA QFN40 . 7.3.12 Circuit configuration no. 6 for QDAA QFN40 . 7.3.13 Circuit configuration no. 1 for CJAA WLCSP . 7.3.14 Circuit configuration no. 2 for CJAA WLCSP . 7.3.15 Circuit configuration no. 3 for CJAA WLCSP . 7.3.16 Circuit configuration no. 4 for CJAA WLCSP . 7.3.17 Circuit configuration no. 5 for CJAA WLCSP . 7.3.18 Circuit configuration no. 6 for CJAA WLCSP . 7.3.19 PCB guidelines . 7.3.20 PCB layout example . 7.4 Package thermal characteristics . 7.5 Package Variation . 7.5.1 aQFN73 . 515 516 516

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. 616 4452_021 v1.3 xi 1 Revision history Date August 2020 Version 1.3 Description The following content has been added or updated:

April 2020 1.2 The following content has been added or updated since the last released Added WLCSP package information Editorial changes version:

Added information for the QFN40 package variant in Pin assignments on page 557, Mechanical specifications on page 565, Reference circuitry on page 567, Package thermal characteristics on page 607, Absolute maximum ratings on page 609 and Ordering information on page 611. Corrected minimum valid value for EasyDMA MAXCNT and AMOUNT registers in SPIM Serial peripheral interface master with EasyDMA on page 388, SPIS Serial peripheral interface slave with EasyDMA on page 405, TWIM I2C compatible two-wire interface master with EasyDMA on page 448, TWIS I2C compatible two-wire interface slave with EasyDMA on page 465 and UARTE Universal asynchronous receiver/transmitter with EasyDMA on page 495. Current consumption on page 52 - Added missing compounded currents. POWER Power supply on page 58 - Clarified REG0 elspec parameters, by renaming and adding several parameters. RADIO 2.4 GHz radio on page 277 - Corrected Sensitivity plot. SPIM Serial peripheral interface master with EasyDMA on page 388 -

Corrected parameter tSPIM,CSK. Reference circuitry on page 567 - Added optional 4.7 resistor to USB supply in configuration 1 for QIAA package. Recommended operating conditions on page 608 - Added parameter TJ (juntion temperature), moved from Absolute maximum ratings on page 609. Absolute maximum ratings on page 609 - Increased aQFN73 CDM to 750 V. Removed parameter TJ (juntion temperature), moved to Recommended operating conditions on page 608. Added footnote regarding supply voltages used in HTOL. Legal notices on page 616 - Updated copyright date. January 2020 November 2019 1.1 1.0 Not released First release 4452_021 v1.3 12 2 About this document This document is organized into chapters that are based on the modules and peripherals available in the IC. 2.1 Document status The document status reflects the level of maturity of the document. Document name Description Objective Product Specification (OPS) Applies to document versions up to 1.0. Product Specification (PS) This document contains target specifications for product development. Applies to document versions 1.0 and higher. This document contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Table 1: Defined document names 2.2 Peripheral chapters Every peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used for identification and reference. This name is used in chapter headings and references, and it will appear in the ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to identify the peripheral. The peripheral instance name, which is different from the peripheral name, is constructed using the peripheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix is normally only used if a peripheral can be instantiated more than once. The peripheral instance name is also used in the CMSIS to identify the peripheral instance. The chapters describing peripherals may include the following information:

A detailed functional description of the peripheral Register configuration for the peripheral Electrical specification tables, containing performance data which apply for the operating conditions described in Recommended operating conditions on page 608. 2.3 Register tables Individual registers are described using register tables. These tables are built up of two sections. The first three colored rows describe the position and size of the different fields in the register. The following rows describe the fields in more detail. 4452_021 v1.3 13 About this document 2.3.1 Fields and values The Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field has enumerated values, then every value will be identified with a unique value id in the Value Id column. A blank space means that the field is reserved and read as undefined, and it also must be written as 0 to secure forward compatibility. If a register is divided into more than one field, a unique field name is specified for each field in the Field column. The Value Id may be omitted in the single-bit bit fields when values can be substituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/

off, and so on. Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimal values have no prefix. The Value column can be populated in the following ways:

Individual enumerated values, for example 1, 3, 9. Range of values, e.g. [0..4], indicating all values from and including 0 and 4. Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or alternatively the field's translation and limitations are described in the text instead. If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but the first field. Subsequent fields will indicate inheritance with '..'. A feature marked Deprecated should not be used for new designs. 2.3.2 Permissions Different fields in a register might have different access permissions enforced by hardware. The access permission for each register field is documented in the Access column in the following ways:

Access Description Hardware behavior RO WO RW W1 Read-only Write-only Read-write Write-once Field can only be read. A write will be ignored. Field can only be written. A read will return an undefined value. Field can be read and written multiple times. RW1 Read-write-once Field can be read multiple times, but only written once per reset. Any subsequent write will be ignored. Field can only be written once per reset. Any subsequent write will be ignored. A read will return an undefined value. Table 2: Register field permission schemes 2.4 Registers Register DUMMY Offset 0x514 Description Example of a register controlling a dummy feature Table 3: Register overview 2.4.1 DUMMY Address offset: 0x514 Example of a register controlling a dummy feature 4452_021 v1.3 14 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D D D D C C C B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value ID Value Description About this document B RW FIELD_B Example of a deprecated read-write field Deprecated Disabled NormalMode ExtendedMode Disabled Enabled 0 1 2 0 1 Example of a read-write field with several enumerated values The example feature is disabled The example feature is enabled in normal mode The example feature is enabled along with extra functionality The override feature is disabled The override feature is enabled Example of a read-write field with a valid range of values Example of a read-write field with no restriction on the values ValidRange

[2..7]

Example of allowed values for this field ID ID A C D Reset 0x00050002 AccessField RW FIELD_A RW FIELD_C RW FIELD_D 4452_021 v1.3 15 3 Block diagram This block diagram illustrates the overall system. Arrows with white heads indicate signals that share physical pins with other signals. 4452_021 v1.3 16 Block diagram nRF52833 RAM0 RAM1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8 GPIO P0.0 P0.31 P1.0 P1.09 TP TPIU e v a l s e v a l s e v a l s e v a l s e v a l s e v a l s e v a l s e v a l s e v a l s e v a l s SWCLK SWDIO SW-DP CTRL-AP AHB multilayer r e t s a m e v a l s AHB TO APB BRIDGE AHB-AP ETM CPU ARM CORTEX-M4 NVIC SysTick nRESET POWER e v a l s e v a l s FICR UICR e v a l s e v a l s I-Cache CODE XC1 XC2 XL1 XL2 ANT VBUS D+

D-

NFC2 NFC1 P0.0 P0.31 P1.0 P1.09 AIN0 AIN7 OUT0 OUT3 LED A B MCK LRCK SCL SDOUT SDIN CLK DIN WDT PPI CLOCK RADIO EasyDMA USBD EasyDMA NFCT EasyDMA GPIOTE COMP LPCOMP SAADC QDEC PWM [0..3]

EasyDMA I2S EasyDMA PDM EasyDMA master master 0 B P A master master master master NVMC RNG RTC [0..2]

TIMER [0..4]

TEMP ECB EasyDMA CCM EasyDMA AAR EasyDMA SPIM [0..3]

TWIS [0..1]

EasyDMA TWIM [0..1]

master master master master master EasyDMA master EasyDMA UARTE [0..1]

SPIS [0..2]

master EasyDMA EasyDMA master master EasyDMA Figure 1: Block diagram SCK MOSI MISO SCL SDA SCL SDA RTS CTS TXD RXD CSN MISO MOSI SCK 4452_021 v1.3 17 4 Core components 4.1 CPU The ARM Cortex-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb-2 technology) that implements a superset of 16- and 32-bit instructions to maximize code density and performance. This processor implements the following features that enable energy-efficient arithmetic and high-

performance signal processing. Digital signal processing (DSP) instructions Single-cycle multiply and accumulate (MAC) instructions Hardware divide 8- and 16-bit single instruction multiple data (SIMD) instructions Single-precision floating-point unit (FPU) The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the ARMCortex processor series is implemented and available for the M4 CPU. Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling events at configurable priority levels via the nested vectored interrupt controller (NVIC). Executing code from flash memory will have a wait state penalty on the nRF52 Series. An instruction cache can be enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache on page 25. The Electrical specification on page 19 shows CPU performance parameters including wait states in different modes, CPU current and efficiency, and processing power and efficiency based on the CoreMark benchmark. The ARM system timer (SysTick) is present on nRF52833. The SysTick's clock will only tick when the CPU is running or when the system is in debug interface mode. 4.1.1 Floating point interrupt The floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow, which in turn will trigger the FPU interrupt. See Instantiation on page 22 for more information about the exceptions triggering the FPU interrupt. To clear the IRQ (interrupt request) line when an exception has occurred, the relevant exception bit within the floating-point status and control register (FPSCR) needs to be cleared. For more information about the FPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide. 4.1.2 CPU and support module configuration The ARM Cortex-M4 processor has a number of CPU options and support modules implemented on the IC. 4452_021 v1.3 18 Option / Module Core options Description NVIC WIC PRIORITIES Endianness Bit-banding DWT SysTick Modules MPU FPU DAP ETM ITM TPIU ETB FPB HTM Nested vector interrupt controller Priority bits Wakeup interrupt controller Memory system endianness Bit banded memory Data watchpoint and trace System tick timer Memory protection unit Floating-point unit Debug access port Embedded trace macrocell Instrumentation trace macrocell Trace port interface unit Embedded trace buffer Flash patch and breakpoint unit AMBA AHB trace macrocell 4.1.3 Electrical specification 4.1.3.1 CPU performance Core components Implemented 48 vectors Little endian 3 NO NO YES YES YES YES YES YES YES YES NO YES NO The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is executing the CoreMark benchmark. It includes power regulator and clock base currents. All other blocks are IDLE. CPU wait states, running CoreMark from flash, cache Symbol WFLASH WRAM CMFLASH Description disabled enabled enabled enabled, DCDC 3V WFLASHCACHE CPU wait states, running CoreMark from flash, cache CPU wait states, running CoreMark from RAM CoreMark, running CoreMark from flash, cache enabled CMFLASH/MHz CoreMark per MHz, running CoreMark from flash, cache CMFLASH/mA CoreMark per mA, running CoreMark from flash, cache Min. Typ. Max. Units 2 3 0 217 3.4 65.8 CoreMark CoreMark/

MHz mA CoreMark/

4.2 Memory The nRF52833 contains 512 kB of flash memory and 128 kB of RAM that can be used for code and data storage. The CPU and peripherals with EasyDMA can access memory via the AHB multilayer interconnect. In additon, peripherals are accessed by the CPU via the AHB multilayer interconnect, as shown in the following figure. 4452_021 v1.3 19 Core components APB AHB2APB Peripheral Peripheral EasyDMA EasyDMA s u b A M D s u b A M D CPU ARM Cortex-M4 E D O C D E D O C I s u b m e t s y S AHB AHB multilayer interconnect RAM8 AHB slave RAM7 AHB slave RAM6 AHB slave RAM5 AHB slave RAM4 AHB slave RAM3 AHB slave RAM2 AHB slave RAM1 AHB slave RAM0 AHB slave Section 1 Section 0 Section 1 Section 0 Section 1 Section 0 Section 1 Section 0 Section 1 Section 0 Section 1 Section 0 Section 1 Section 0 Section 1 Section 0 Section 1 Section 0 Data RAM System Code RAM ICODE / DCODE 0x2001 8000 0x0081 8000 0x2001 0000 0x0081 0000 0x2000 F000 0x0080 F000 0x2000 E000 0x0080 E000 0x2000 D000 0x0080 D000 0x2000 C000 0x0080 C000 0x2000 B000 0x0080 B000 0x2000 A000 0x0080 A000 0x2000 9000 0x0080 9000 0x2000 8000 0x0080 8000 0x2000 7000 0x0080 7000 0x2000 6000 0x0080 6000 0x2000 5000 0x0080 5000 0x2000 4000 0x0080 4000 0x2000 3000 0x0080 3000 0x2000 2000 0x0080 2000 0x2000 1000 0x0080 1000 0x2000 0000 0x0080 0000 ICODE DCODE B H A e v a s l e h c a C

I B H A e v a s l C M V N Page 127 Page 3..126 Page 2 Page 1 Page 0 Flash ICODE/DCODE 0x0007 F000 0x0000 3000 0x0000 2000 0x0000 1000 0x0000 0000 Figure 2: Memory layout See AHB multilayer on page 46 and EasyDMA on page 44 for more information about the AHB multilayer interconnect and EasyDMA. The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to the application to partition the RAM within these regions so that one does not corrupt the other. 4.2.1 RAM - Random access memory The RAM interface is divided into nine RAM AHB slaves. RAM AHB slaves 0 to 7 are connected to two 4 kB RAM sections each, while RAM AHB slave 8 is connected to two 32 kB sections, as shown in Memory layout on page 20. Each RAM section has separate power control for System ON and System OFF mode operation, which is configured via RAM register (see the POWER Power supply on page 58). 4.2.2 Flash - Non-volatile memory The CPU can read from flash memory an unlimited number of times, but is restricted in how it writes to flash and the number of writes and erases it can perform. Writing to flash memory is managed by the non-volatile memory controller (NVMC), see NVMC Non-

volatile memory controller on page 23. Flash memory is divided into 128 pages of 4 kB each that can be accessed by the CPU via the ICODE and DCODE buses as shown in Memory layout on page 20. 4.2.3 Memory map The complete memory map for the nRF52833 is shown in the following figure. As described in Memory on page 19, Code RAM and Data RAM are the same physical RAM. 4452_021 v1.3 20 System address map Address map Core components Private peripheral bus 0xE0000000 0xFFFFFFFF 0xE0000000 0xC0000000 0xA0000000 0x80000000 0x60000000 0x40000000 0x20000000 0x00000000 Device Device Device RAM RAM SRAM Code Peripheral Figure 3: Memory map 4452_021 v1.3 21 AHB peripherals APB peripherals 0x50000000 0x40000000 Data RAM 0x20000000 UICR FICR Code RAM Flash 0x10001000 0x10000000 0x00800000 0x00000000 4.2.4 Instantiation ID Base address Peripheral 0 0 0 0 0 1 2 2 3 3 3 3 3 3 4 4 4 4 4 4 5 6 7 8 9 10 11 12 13 14 15 15 16 17 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 0x40000000 0x40000000 0x50000000 0x50000000 0x50000300 0x40001000 0x40002000 0x40002000 0x40003000 0x40003000 0x40003000 0x40003000 0x40003000 0x40003000 0x40004000 0x40004000 0x40004000 0x40004000 0x40004000 0x40004000 0x40005000 0x40006000 0x40007000 0x40008000 0x40009000 0x4000A000 0x4000B000 0x4000C000 0x4000D000 0x4000E000 0x4000F000 0x4000F000 0x40010000 0x40011000 0x40012000 0x40013000 0x40013000 0x40014000 0x40014000 0x40015000 0x40015000 0x40016000 0x40016000 0x40017000 0x40017000 0x40018000 0x40018000 0x40019000 0x40019000 CLOCK POWER GPIO GPIO GPIO RADIO UART UARTE SPI SPIM SPIS TWI TWIM TWIS SPI SPIM SPIS TWI TWIM TWIS NFCT GPIOTE SAADC TIMER TIMER TIMER RTC TEMP RNG ECB AAR CCM WDT RTC QDEC COMP LPCOMP EGU SWI EGU SWI EGU SWI EGU SWI EGU SWI EGU SWI Instance CLOCK POWER GPIO P0 P1 RADIO UART0 UARTE0 SPI0 SPIM0 SPIS0 TWI0 TWIM0 TWIS0 SPI1 SPIM1 SPIS1 TWI1 TWIM1 TWIS1 NFCT GPIOTE SAADC TIMER0 TIMER1 TIMER2 RTC0 TEMP RNG ECB AAR CCM WDT RTC1 QDEC COMP LPCOMP EGU0 SWI0 EGU1 SWI1 EGU2 SWI2 EGU3 SWI3 EGU4 SWI4 EGU5 SWI5 Core components Description Clock control Power control General purpose input and output Deprecated General purpose input and output, port 0 General purpose input and output, port 1 2.4 GHz radio Universal asynchronous receiver/transmitter Deprecated Universal asynchronous receiver/transmitter with EasyDMA, Deprecated Deprecated Deprecated Deprecated AES electronic code book (ECB) mode block encryption Accelerated address resolver AES counter with CBC-MAC (CCM) mode block encryption unit 0 SPI master 0 SPI master 0 SPI slave 0 SPI master 1 SPI master 1 SPI slave 1 Two-wire interface master 0 Two-wire interface master 0 Two-wire interface slave 0 Two-wire interface master 1 Two-wire interface master 1 Two-wire interface slave 1 Near field communication tag GPIO tasks and events Analog to digital converter Timer 0 Timer 1 Timer 2 Real-time counter 0 Temperature sensor Random number generator Watchdog timer Real-time counter 1 Quadrature decoder General purpose comparator Low power comparator Event generator unit 0 Software interrupt 0 Event generator unit 1 Software interrupt 1 Event generator unit 2 Software interrupt 2 Event generator unit 3 Software interrupt 3 Event generator unit 4 Software interrupt 4 Event generator unit 5 Software interrupt 5 4452_021 v1.3 22 Base address Peripheral ID 26 27 28 29 30 30 31 32 33 34 35 35 35 36 37 38 39 40 45 47 N/A N/A 0x4001A000 0x4001B000 0x4001C000 0x4001D000 0x4001E000 0x4001E000 0x4001F000 0x40020000 0x40021000 0x40022000 0x40023000 0x40023000 0x40023000 0x40024000 0x40025000 0x40026000 0x40027000 0x40028000 0x4002D000 0x4002F000 0x10000000 0x10001000 TIMER TIMER PWM PDM ACL NVMC PPI MWU PWM PWM SPI SPIM SPIS RTC I2S FPU USBD UARTE PWM SPIM FICR UICR Instance TIMER3 TIMER4 PWM0 PDM ACL NVMC PPI MWU PWM1 PWM2 SPI2 SPIM2 SPIS2 RTC2 I2S FPU USBD PWM3 SPIM3 FICR UICR Core components Description Timer 3 Timer 4 Pulse width modulation unit 0 Pulse Density modulation (digital microphone) interface Deprecated Access control lists Non-volatile memory controller Programmable peripheral interconnect Memory watch unit Pulse width modulation unit 1 Pulse width modulation unit 2 SPI master 2 SPI master 2 SPI slave 2 Real-time counter 2 Inter-IC sound interface FPU interrupt Universal serial bus device unit 1 SPI master 3 Pulse width modulation unit 3 Factory information configuration User information configuration UARTE1 Universal asynchronous receiver/transmitter with EasyDMA, Table 4: Instantiation table 4.3 NVMC Non-volatile memory controller The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory and the UICR (user information configuration registers). The CONFIG on page 26 is used to enable the NVMC for writing (CONFIG.WEN = Wen) and erasing

(CONFIG.WEN = Een). The CPU must be halted before initiating a NVMC operation from the debug system. 4.3.1 Writing to flash When write is enabled, full 32-bit words can be written to word-aligned addresses in flash memory. As illustrated in Memory on page 19, the flash is divided into multiple pages. The same 32-bit word in flash memory can only be written n WRITE number of times before a page erase must be performed. The NVMC is only able to write 0 to bits in flash memory that are erased (set to 1). It cannot rewrite a bit back to 1. Only full 32-bit words can be written to flash memory using the NVMC interface. To write less than 32 bits, write the data as a full 32-bit word and set all the bits that should remain unchanged in the word to 1. The restriction on the number of writes (nWRITE) still applies in this case. Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault. The time it takes to write a word to flash is specified by tWRITE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the flash. NVM writing time can be reduced by using READYNEXT. If this status bit is set to 1, code can perform the next data write to the flash. This write will be buffered and will be taken into account as soon as the ongoing write operation is completed. 4452_021 v1.3 23 Core components 4.3.2 Erasing a page in flash When erase is enabled, the flash memory can be erased page by page using the ERASEPAGE on page 27. After erasing a flash page, all bits in the page are set to 1. The time it takes to erase a page is specified by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the flash. See Partial erase of a page in flash on page 25 for information on dividing the page erase time into shorter chunks. 4.3.3 Writing to user information configuration registers (UICR) User information configuration registers (UICR) are written in the same way as flash. After UICR has been written, the new UICR configuration will only take effect after a reset. UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR on page 28 or ERASEALL on page 27. The time it takes to write a word to UICR is specified by tWRITE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the UICR. 4.3.4 Erasing user information configuration registers (UICR) When erase is enabled, UICR can be erased using the ERASEUICR on page 28. After erasing UICR, all bits in UICR are set to 1. The time it takes to erase UICR is specified by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation. 4.3.5 Erase all When erase is enabled, flash and UICR can be erased completely in one operation by using the ERASEALL on page 27. This operation will not erase the factory information configuration registers (FICR). The time it takes to perform an ERASEALL command is specified by tERASEALL. The CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation. 4.3.6 Access port protection behavior When access port protection is enabled, parts of the NVMC functionality will be blocked in order to prevent intentional or unintentional erase of UICR. CTRL-AP ERASEALL NVMC ERASEPAGE NVMC ERASEPAGE NVMC ERASEALL NVMC ERASEUICR APPROTECT Disabled Enabled Allowed Allowed Allowed Allowed Allowed Allowed Allowed Blocked PARTIAL Allowed Allowed Table 5: NVMC Protection 4.3.7 NVMC power failure protection NVMC power failure protection is possible through use of power-fail comparator that is monitoring power supply. If the power-fail comparator is enabled, and the power supply voltage is below VPOF threshold, the power-

fail comparator will prevent the NVMC from performing erase or write operations in non-volatile memory

(NVM). If a power failure warning is present at the start of an NVM erase operation, the NVMC operation will be ignored. 4452_021 v1.3 24 Core components If a power failure warning is present at the start of an NVM write operation, the CPU will hardfault. 4.3.8 Partial erase of a page in flash Partial erase is a feature in the NVMC to split a page erase time into shorter chunks to prevent longer CPU stalls in time-critical applications. Partial erase is only applicable to the code area in flash memory and does not work with UICR. When erase is enabled, the partial erase of a flash page can be started by writing to ERASEPAGEPARTIAL on page 28. The duration of a partial erase can be configured in ERASEPAGEPARTIALCFG on page 28. A flash page is erased when its erase time reaches tERASEPAGE. Use ERASEPAGEPARTIAL N number of times so that N * ERASEPAGEPARTIALCFG tERASEPAGE, where N * ERASEPAGEPARTIALCFG gives the cumulative (total) erase time. Every time the cumulative erase time reaches tERASEPAGE, it counts as one erase cycle. After the erase is complete, all bits in the page are set to 1. The CPU is halted if the CPU executes code from the flash while the NVMC performs the partial erase operation. The bits in the page are undefined if the flash page erase is incomplete, i.e. if a partial erase has started but the total erase time is less than tERASEPAGE. 4.3.9 Cache An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC. A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-

states for a cache miss, where the instruction is not available in the cache and needs to be fetched from flash, is shown in CPU on page 18. Enabling the cache can increase CPU performance and reduce power consumption by reducing the number of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will use some current when enabled. If the reduction in average current due to reduced flash accesses is larger than the cache power requirement, the average current to execute the program code will decrease. When disabled, the cache does not use current and does not retain its content. It is possible to enable cache profiling to analyze the performance of the cache for your program using the ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for every instruction cache hit or miss, respectively. The hit and miss profiling registers do not wrap around after reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to get correct numbers. Base address Peripheral Description Configuration 0x4001E000 NVMC Non-volatile memory controller Instance NVMC 4.3.10 Registers Register READY READYNEXT CONFIG ERASEPAGE ERASEPCR1 ERASEALL ERASEPCR0 ERASEUICR Offset 0x400 0x408 0x504 0x508 0x508 0x50C 0x510 0x514 Table 6: Instances Description Ready flag Ready flag Configuration register Register for erasing a page in code area Register for erasing a page in code area, equivalent to ERASEPAGE Deprecated Register for erasing all non-volatile user memory Register for erasing a page in code area, equivalent to ERASEPAGE Deprecated Register for erasing user information configuration registers 4452_021 v1.3 25 Core components Register ERASEPAGEPARTIAL ERASEPAGEPARTIALCFG ICACHECNF IHIT IMISS Offset 0x518 0x51C 0x540 0x548 0x54C Description Register for partial erase of a page in code area Register for partial erase configuration I-code cache configuration register I-code cache hit counter I-code cache miss counter Table 7: Register overview 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Busy Ready NVMC is ready or busy NVMC is busy (on-going write or erase operation) NVMC is ready 4.3.10.1 READY Address offset: 0x400 Ready flag Bit number ID ID A Reset 0x00000001 AccessField R READY 4.3.10.2 READYNEXT Address offset: 0x408 Ready flag R READYNEXT Busy Ready 4.3.10.3 CONFIG Address offset: 0x504 Configuration register ID ID A ID ID A Ren Wen Een 0 1 0 1 0 1 2 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 AccessField Value ID Value Description NVMC can accept a new write operation NVMC cannot accept any write operation NVMC is ready Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW WEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Program memory access mode. It is strongly recommended to only activate erase and write modes when they are Enabling write or erase will invalidate the cache and keep it actively used. invalidated. Read only access Write enabled Erase enabled 4452_021 v1.3 26 A A A A Core components 4.3.10.4 ERASEPAGE Address offset: 0x508 Register for erasing a page in code area ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W ERASEPAGE Register for starting erase of a page in code area The value is the address to the page to be erased.

(Addresses of first word in page). The erase must be enabled using CONFIG.WEN before the page can be erased. Attempts to erase pages that are outside the code area may result in undesirable behavior, e.g. the wrong page may be erased. 4.3.10.5 ERASEPCR1 ( Deprecated ) Address offset: 0x508 Register for erasing a page in code area, equivalent to ERASEPAGE Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W ERASEPCR1 Register for erasing a page in code area, equivalent to ERASEPAGE 4.3.10.6 ERASEALL Address offset: 0x50C Register for erasing all non-volatile user memory Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description A Reset 0x00000000 AccessField W ERASEALL Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-

volatile memory can be erased. NoOperation Erase 0 1 No operation Start chip erase 4.3.10.7 ERASEPCR0 ( Deprecated ) Address offset: 0x510 Register for erasing a page in code area, equivalent to ERASEPAGE 4452_021 v1.3 27 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W ERASEPCR0 Register for starting erase of a page in code area, equivalent to ERASEPAGE 4.3.10.8 ERASEUICR Address offset: 0x514 Register for erasing user information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W ERASEUICR Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN NoOperation Erase 0 1 before the UICR can be erased. No operation Start erase of UICR 4.3.10.9 ERASEPAGEPARTIAL Address offset: 0x518 Register for partial erase of a page in code area Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W ERASEPAGEPARTIAL Register for starting partial erase of a page in code area ID ID A ID ID A ID ID A The value is the address to the page to be partially erased

(address of the first word in page). The erase must be enabled using CONFIG.WEN before every erase page partial and disabled using CONFIG.WEN after every erase page partial. Attempts to erase pages that are outside the code area may result in undesirable behavior, e.g. the wrong page may be erased. 4.3.10.10 ERASEPAGEPARTIALCFG Address offset: 0x51C Register for partial erase configuration 4452_021 v1.3 28 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x0000000A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 AccessField Value ID Value Description RW DURATION Duration of the partial erase in milliseconds The user must ensure that the total erase time is long enough for a complete erase of the flash page. Core components A A A A A A A 4.3.10.11 ICACHECNF Address offset: 0x540 I-code cache configuration register Bit number ID ID A Reset 0x00000000 AccessField RW CACHEEN B RW CACHEPROFEN 4.3.10.12 IHIT Address offset: 0x548 I-code cache hit counter Bit number ID ID A Reset 0x00000000 AccessField RW HITS 4.3.10.13 IMISS Address offset: 0x54C I-code cache miss counter Bit number ID ID A Reset 0x00000000 AccessField RW MISSES 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Disabled Enabled Disabled Enabled 0 1 0 1 Disable cache. Invalidates all cache entries. Description Cache enable Enable cache Cache profiling enable Disable cache profiling Enable cache profiling 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Number of cache hits. Register is writable, but only to '0'. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Number of cache misses. Register is writable, but only to '0'. 4452_021 v1.3 29 Core components 2 42.51 87.51 1731 1.091 s ms ms Description Min. Typ. Max. Units Number of times a 32-bit word can be written before erase nENDURANCE Erase cycles per page 10000 4.3.11 Electrical specification 4.3.11.1 Flash programming Symbol nWRITE tWRITE tERASEPAGE tERASEALL Time to write one 32-bit word Time to erase one page Time to erase all flash tERASEPAGEPARTIAL,acc Accuracy of the partial page erase duration. Total execution time for one partial page erase is defined as ERASEPAGEPARTIALCFG * tERASEPAGEPARTIAL,acc. 4.3.11.2 Cache size Symbol SizeICODE Description I-Code cache size Min. Max. Units Typ. 2048 Bytes 4.4 FICR Factory information configuration registers Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by the user. These registers contain chip-specific information and configuration. 4.4.1 Registers Base address Peripheral Instance Description Configuration 0x10000000 FICR FICR Factory information configuration Table 8: Instances Register CODEPAGESIZE CODESIZE DEVICEID[0]

DEVICEID[1]

ER[0]

ER[1]

ER[2]

ER[3]

IR[0]

IR[1]

IR[2]

IR[3]

DEVICEADDRTYPE DEVICEADDR[0]

DEVICEADDR[1]

INFO.PART Offset 0x010 0x014 0x060 0x064 0x080 0x084 0x088 0x08C 0x090 0x094 0x098 0x09C 0x0A0 0x0A4 0x0A8 0x100 Description Code memory page size Code memory size Device identifier Device identifier Encryption root, word 0 Encryption root, word 1 Encryption root, word 2 Encryption root, word 3 Identity Root, word 0 Identity Root, word 1 Identity Root, word 2 Identity Root, word 3 Device address type Device address 0 Device address 1 Part code 1 Applies when HFXO is used. Timing varies according to HFINT accuracy when HFINT is used. 4452_021 v1.3 30 Core components Reserved Reserved Reserved Offset Description Build code (hardware version and production configuration) Register INFO.VARIANT INFO.PACKAGE INFO.RAM INFO.FLASH INFO.UNUSED8[0]

INFO.UNUSED8[1]

INFO.UNUSED8[2]

PRODTEST[0]

PRODTEST[1]

PRODTEST[2]

TEMP.A0 TEMP.A1 TEMP.A2 TEMP.A3 TEMP.A4 TEMP.A5 TEMP.B0 TEMP.B1 TEMP.B2 TEMP.B3 TEMP.B4 TEMP.B5 TEMP.T0 TEMP.T1 TEMP.T2 TEMP.T3 TEMP.T4 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x350 0x354 0x358 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 0x424 0x428 0x42C 0x430 0x434 0x438 0x43C 0x440 0x444 0x450 Package option RAM variant Flash variant Production test signature 0 Production test signature 1 Production test signature 2 Slope definition A0 Slope definition A1 Slope definition A2 Slope definition A3 Slope definition A4 Slope definition A5 Y-intercept B0 Y-intercept B1 Y-intercept B2 Y-intercept B3 Y-intercept B4 Y-intercept B5 Segment end T0 Segment end T1 Segment end T2 Segment end T3 Segment end T4 NFC.TAGHEADER0 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFC.TAGHEADER1 0x454 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFC.TAGHEADER2 0x458 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFC.TAGHEADER3 0x45C Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. NFCID1_2ND_LAST, and NFCID1_LAST. NFCID1_2ND_LAST, and NFCID1_LAST. NFCID1_2ND_LAST, and NFCID1_LAST. Table 9: Register overview Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AccessField Value ID Value Description R CODEPAGESIZE Code memory page size 4.4.1.1 CODEPAGESIZE Address offset: 0x010 Code memory page size ID ID A 4.4.1.2 CODESIZE Address offset: 0x014 Code memory size 4452_021 v1.3 31 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Reset 0xFFFFFFFF AccessField R CODESIZE Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE 4.4.1.3 DEVICEID[n] (n=0..1) Address offset: 0x060 + (n 0x4) Device identifier Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Reset 0xFFFFFFFF AccessField R DEVICEID 64 bit unique device identifier DEVICEID[0] contains the least significant bits of the device identifier. DEVICEID[1] contains the most significant bits of the device identifier. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xFFFFFFFF AccessField R ER Value ID Value Description Encryption root, word n A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xFFFFFFFF AccessField R IR Value ID Value Description Identity Root, word n A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID ID A ID ID A ID ID A ID ID A 4.4.1.4 ER[n] (n=0..3) Address offset: 0x080 + (n 0x4) Encryption root, word n 4.4.1.5 IR[n] (n=0..3) Address offset: 0x090 + (n 0x4) Identity Root, word n 4.4.1.6 DEVICEADDRTYPE Address offset: 0x0A0 Device address type 4452_021 v1.3 32 ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AccessField Value ID Value Description R DEVICEADDRTYPE Public Random 0 1 Device address type Public address Random address Core components A 4.4.1.7 DEVICEADDR[n] (n=0..1) Address offset: 0x0A4 + (n 0x4) Device address n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AccessField Value ID Value Description R DEVICEADDR 48 bit device address DEVICEADDR[0] contains the least significant bits of the device address. DEVICEADDR[1] contains the most significant bits of the device address. Only bits [15:0] of DEVICEADDR[1] are used. 4.4.1.8 INFO.PART Address offset: 0x100 Part code Bit number ID ID A Reset 0x00052833 AccessField R PART Value ID Value N52833 N52840 0x52833 0x52840 Description Part code nRF52833 nRF52840 Unspecified 0xFFFFFFFF Unspecified 4.4.1.9 INFO.VARIANT Address offset: 0x104 Build code (hardware version and production configuration) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 1 0 0 1 1 Bit number ID ID A Reset 0xFFFFFFFF AccessField R VARIANT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Build code (hardware version and production configuration). Encoded as ASCII. AAAA AAAB Unspecified 0x41414141 0x41414142 0xFFFFFFFF AAAA AAAB Unspecified 4452_021 v1.3 33 Core components 4.4.1.10 INFO.PACKAGE Address offset: 0x108 Package option Bit number ID ID A Reset 0xFFFFFFFF AccessField R PACKAGE 4.4.1.11 INFO.RAM Address offset: 0x10C RAM variant Bit number ID ID A Reset 0xFFFFFFFF AccessField R RAM 4.4.1.12 INFO.FLASH Address offset: 0x110 Flash variant Bit number ID ID A Reset 0xFFFFFFFF AccessField R FLASH K16 K32 K64 K128 K256 K128 K256 K512 K1024 K2048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value QD QI CJ 0x2007 0x2004 0x2008 Unspecified 0xFFFFFFFF Description Package option QDxx - 40-pin QFN QIxx - 73-pin aQFN CJxx - WLCSP Unspecified 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Unspecified 0xFFFFFFFF Unspecified Description RAM variant 16 kByte RAM 32 kByte RAM 64 kByte RAM 128 kByte RAM 256 kByte RAM Description Flash variant 128 kByte FLASH 256 kByte FLASH 512 kByte FLASH 1 MByte FLASH 2 MByte FLASH 0x10 0x20 0x40 0x80 0x100 0x80 0x100 0x200 0x400 0x800 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Unspecified 0xFFFFFFFF Unspecified 4.4.1.13 PRODTEST[n] (n=0..2) Address offset: 0x350 + (n 0x4) 4452_021 v1.3 34 Core components Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Done NotDone 0xBB42319F 0xFFFFFFFF Production test signature n Production tests done Production tests not done Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A A A Value ID Value Description A (slope definition) register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A A A Value ID Value Description A (slope definition) register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A A A Value ID Value Description A (slope definition) register. Production test signature n ID ID A ID ID A ID ID A ID ID A Reset 0xFFFFFFFF AccessField R PRODTEST 4.4.1.14 TEMP.A0 Address offset: 0x404 Slope definition A0 Reset 0xFFFFFFFF AccessField R A 4.4.1.15 TEMP.A1 Address offset: 0x408 Slope definition A1 Reset 0xFFFFFFFF AccessField R A 4.4.1.16 TEMP.A2 Address offset: 0x40C Slope definition A2 Reset 0xFFFFFFFF AccessField R A 4.4.1.17 TEMP.A3 Address offset: 0x410 Slope definition A3 4452_021 v1.3 35 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A A A Value ID Value Description A (slope definition) register. Core components Reset 0xFFFFFFFF AccessField R A 4.4.1.18 TEMP.A4 Address offset: 0x414 Slope definition A4 Reset 0xFFFFFFFF AccessField R A 4.4.1.19 TEMP.A5 Address offset: 0x418 Slope definition A5 Reset 0xFFFFFFFF AccessField R A 4.4.1.20 TEMP.B0 Address offset: 0x41C Y-intercept B0 Reset 0xFFFFFFFF AccessField R B 4.4.1.21 TEMP.B1 Address offset: 0x420 Y-intercept B1 ID ID A ID ID A ID ID A ID ID A ID ID A Reset 0xFFFFFFFF AccessField R B 4452_021 v1.3 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A A A Value ID Value Description A (slope definition) register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A A A Value ID Value Description A (slope definition) register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A A A A A Value ID Value Description B (y-intercept) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A A A A A Value ID Value Description B (y-intercept) 36 Core components 4.4.1.22 TEMP.B2 Address offset: 0x424 Y-intercept B2 Reset 0xFFFFFFFF AccessField R B 4.4.1.23 TEMP.B3 Address offset: 0x428 Y-intercept B3 Reset 0xFFFFFFFF AccessField R B 4.4.1.24 TEMP.B4 Address offset: 0x42C Y-intercept B4 Reset 0xFFFFFFFF AccessField R B 4.4.1.25 TEMP.B5 Address offset: 0x430 Y-intercept B5 Reset 0xFFFFFFFF AccessField R B 4.4.1.26 TEMP.T0 Address offset: 0x434 Segment end T0 ID ID A ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A A A A A Value ID Value Description B (y-intercept) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A A A A A Value ID Value Description B (y-intercept) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A A A A A Value ID Value Description B (y-intercept) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A A A A A A A Value ID Value Description B (y-intercept) 4452_021 v1.3 37 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description T (segment end) register Core components A A A A A A A A Reset 0xFFFFFFFF AccessField R T 4.4.1.27 TEMP.T1 Address offset: 0x438 Segment end T1 Reset 0xFFFFFFFF AccessField R T 4.4.1.28 TEMP.T2 Address offset: 0x43C Segment end T2 Reset 0xFFFFFFFF AccessField R T 4.4.1.29 TEMP.T3 Address offset: 0x440 Segment end T3 Reset 0xFFFFFFFF AccessField R T 4.4.1.30 TEMP.T4 Address offset: 0x444 Segment end T4 ID ID A ID ID A ID ID A ID ID A ID ID A Reset 0xFFFFFFFF AccessField R T 4452_021 v1.3 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A Value ID Value Description T (segment end) register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A Value ID Value Description T (segment end) register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A Value ID Value Description T (segment end) register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A A Value ID Value Description T (segment end) register 38 Core components 4.4.1.31 NFC.TAGHEADER0 Address offset: 0x450 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 Value ID Value Description Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F Unique identifier byte 1 Unique identifier byte 2 Unique identifier byte 3 4.4.1.32 NFC.TAGHEADER1 Address offset: 0x454 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A-D R UD[i] (i=4..7) Unique identifier byte i Value ID Value Description 4.4.1.33 NFC.TAGHEADER2 Address offset: 0x458 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A-D R UD[i] (i=8..11) Unique identifier byte i Value ID Value Description 4.4.1.34 NFC.TAGHEADER3 Address offset: 0x45C Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A-D R UD[i] (i=12..15) Unique identifier byte i Value ID Value Description 4452_021 v1.3 39 ID ID A B C D Reset 0xFFFFFF5F AccessField R MFGID R R R UD1 UD2 UD3 Bit number ID Reset 0xFFFFFFFF ID AccessField Bit number ID Reset 0xFFFFFFFF ID AccessField Bit number ID Reset 0xFFFFFFFF ID AccessField 4.5 UICR User information configuration registers The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring user-specific settings. For information on writing UICR registers, see the NVMC Non-volatile memory controller on page 23 and Memory on page 19 chapters. 4.5.1 Registers Base address Peripheral Instance Description Configuration 0x10001000 UICR UICR User information configuration Table 10: Instances Offset Description Core components Reserved Reserved Reserved Reserved Register UNUSED0 UNUSED1 UNUSED2 UNUSED3 NRFFW[0]

NRFFW[1]

NRFFW[2]

NRFFW[3]

NRFFW[4]

NRFFW[5]

NRFFW[6]

NRFFW[7]

NRFFW[8]

NRFFW[9]

NRFFW[10]

NRFFW[11]

NRFFW[12]

NRFHW[0]

NRFHW[1]

NRFHW[2]

NRFHW[3]

NRFHW[4]

NRFHW[5]

NRFHW[6]

NRFHW[7]

NRFHW[8]

NRFHW[9]

NRFHW[10]

NRFHW[11]

CUSTOMER[0]

CUSTOMER[1]

CUSTOMER[2]

CUSTOMER[3]

CUSTOMER[4]

CUSTOMER[5]

CUSTOMER[6]

0x000 0x004 0x008 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x050 0x054 0x058 0x05C 0x060 0x064 0x068 0x06C 0x070 0x074 0x078 0x07C 0x080 0x084 0x088 0x08C 0x090 0x094 0x098 Reserved for Nordic firmware design Reserved for Nordic firmware design Reserved for Nordic firmware design Reserved for Nordic firmware design Reserved for Nordic firmware design Reserved for Nordic firmware design Reserved for Nordic firmware design Reserved for Nordic firmware design Reserved for Nordic firmware design Reserved for Nordic firmware design Reserved for Nordic firmware design Reserved for Nordic firmware design Reserved for Nordic firmware design Reserved for Nordic hardware design Reserved for Nordic hardware design Reserved for Nordic hardware design Reserved for Nordic hardware design Reserved for Nordic hardware design Reserved for Nordic hardware design Reserved for Nordic hardware design Reserved for Nordic hardware design Reserved for Nordic hardware design Reserved for Nordic hardware design Reserved for Nordic hardware design Reserved for Nordic hardware design Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer 4452_021 v1.3 40 Core components Register CUSTOMER[7]

CUSTOMER[8]

CUSTOMER[9]

CUSTOMER[10]

CUSTOMER[11]

CUSTOMER[12]

CUSTOMER[13]

CUSTOMER[14]

CUSTOMER[15]

CUSTOMER[16]

CUSTOMER[17]

CUSTOMER[18]

CUSTOMER[19]

CUSTOMER[20]

CUSTOMER[21]

CUSTOMER[22]

CUSTOMER[23]

CUSTOMER[24]

CUSTOMER[25]

CUSTOMER[26]

CUSTOMER[27]

CUSTOMER[28]

CUSTOMER[29]

CUSTOMER[30]

CUSTOMER[31]

PSELRESET[0]

PSELRESET[1]

APPROTECT NFCPINS DEBUGCTRL REGOUT0 Description Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Reserved for customer Offset 0x09C 0x0A0 0x0A4 0x0A8 0x0AC 0x0B0 0x0B4 0x0B8 0x0BC 0x0C0 0x0C4 0x0C8 0x0CC 0x0D0 0x0D4 0x0D8 0x0DC 0x0E0 0x0E4 0x0E8 0x0EC 0x0F0 0x0F4 0x0F8 0x0FC 0x200 0x204 0x208 0x20C 0x210 0x304 4.5.1.1 NRFFW[n] (n=0..12) Address offset: 0x014 + (n 0x4) Reserved for Nordic firmware design Mapping of the nRESET function (see POWER chapter for details) Mapping of the nRESET function (see POWER chapter for details) Setting of pins dedicated to NFC functionality: NFC antenna or GPIO Access port protection Processor debug control given as VDDH - VREG0DROP. Table 11: Register overview Output voltage from REG0 regulator stage. The maximum output voltage from this stage is Bit number ID ID A Reset 0xFFFFFFFF AccessField RW NRFFW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Reserved for Nordic firmware design 4.5.1.2 NRFHW[n] (n=0..11) Address offset: 0x050 + (n 0x4) Reserved for Nordic hardware design 4452_021 v1.3 41 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xFFFFFFFF AccessField RW NRFHW Value ID Value Description Reserved for Nordic hardware design A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Core components 4.5.1.3 CUSTOMER[n] (n=0..31) Address offset: 0x080 + (n 0x4) Reserved for customer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AccessField Value ID Value Description RW CUSTOMER Reserved for customer 4.5.1.4 PSELRESET[n] (n=0..1) Address offset: 0x200 + (n 0x4) Mapping of the nRESET function (see POWER chapter for details) All PSELRESET registers have to contain the same value for a pin mapping to be valid. If values are not the same, there will be no nRESET function exposed on a GPIO. As a result, the device will always start independently of the levels present on any of the GPIOs. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value ID Description GPIO pin number onto which nRESET is exposed Port number onto which nRESET is exposed Disconnected Connected Connection Disconnect Connect Value 18 C 0 1 0 ID ID A ID ID A ID A B C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Enable or disable access port protection. See Debug and trace on page 47 for more information. Disabled Enabled 0xFF 0x00 Disable Enable 4452_021 v1.3 42 Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 4.5.1.5 APPROTECT Address offset: 0x208 Access port protection Bit number ID ID A Reset 0xFFFFFFFF AccessField RW PALL Core components Setting of pins dedicated to NFC functionality: NFC antenna or GPIO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Setting of pins dedicated to NFC functionality Operation as GPIO pins. Same protection as normal GPIO pins for NFC operation Operation as NFC antenna pins. Configures the protection 4.5.1.6 NFCPINS Address offset: 0x20C Bit number ID ID A Reset 0xFFFFFFFF AccessField RW PROTECT 4.5.1.7 DEBUGCTRL Address offset: 0x210 Processor debug control ID ID A RW CPUNIDEN B RW CPUFPBEN 4.5.1.8 REGOUT0 Address offset: 0x304 Disabled NFC Enabled Disabled Enabled Disabled 1V8 2V1 2V4 2V7 3V0 3V3 Value 0xFF 0x00 0xFF 0x00 0 1 0 1 2 3 4 5 7 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B B B B B B B B A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AccessField Value ID Description Configure CPU non-intrusive debug features Enable CPU ITM and ETM functionality (default behavior) Disable CPU ITM and ETM functionality Configure CPU flash patch and breakpoint (FPB) unit Enable CPU FPB unit (default behavior) Disable CPU FPB unit. Writes into the FPB registers will be behavior ignored. Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH

- VREG0DROP. Bit number ID ID A Reset 0xFFFFFFFF AccessField RW VOUT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Output voltage from REG0 regulator stage. 1.8 V 2.1 V 2.4 V 2.7 V 3.0 V 3.3 V DEFAULT Default voltage: 1.8 V 4452_021 v1.3 43 Core components 4.6 EasyDMA EasyDMA is a module implemented by some peripherals to gain direct access to Data RAM. EasyDMA is an AHB bus master similar to CPU and is connected to the AHB multilayer interconnect for direct access to Data RAM. EasyDMA is not able to access flash. A peripheral can implement multiple EasyDMA instances to provide dedicated channels. For example, for reading and writing of data between the peripheral and RAM. This concept is illustrated in EasyDMA example on page 44. AHB multilayer Peripheral RAM RAM RAM AHB AHB READER EasyDMA WRITER EasyDMA Peripheral core An EasyDMA channel is implemented in the following way, but some variations may occur:

Figure 4: EasyDMA example READERBUFFER_SIZE 5 WRITERBUFFER_SIZE 6 uint8_t readerBuffer[READERBUFFER_SIZE] __at__ 0x20000000;

uint8_t writerBuffer[WRITERBUFFER_SIZE] __at__ 0x20000005;

// Configuring the READER channel MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE;

MYPERIPHERAL->READER.PTR = &readerBuffer;

// Configure the WRITER channel MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE;

MYPERIPHERAL->WRITER.PTR = &writerBuffer;

This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels - one for reading called READER, and one for writing called WRITER. When the peripheral is started, it is assumed that the peripheral will perform the following tasks:

Read 5 bytes from the readerBuffer located in RAM at address 0x20000000 Process the data Write no more than 6 bytes back to the writerBuffer located in RAM at address 0x20000005 The memory layout of these buffers is illustrated in EasyDMA memory layout on page 45. 4452_021 v1.3 44 Core components 0x20000000 0x20000004 0x20000008 readerBuffer[0]

readerBuffer[1]

readerBuffer[2]

readerBuffer[3]

readerBuffer[4]

writerBuffer[0]

writerBuffer[1]

writerBuffer[2]

writerBuffer[3]

writerBuffer[4]

writerBuffer[5]

Figure 5: EasyDMA memory layout The WRITER.MAXCNT register should not be specified larger than the actual size of the buffer

(writerBuffer). Otherwise, the channel would overflow the writerBuffer. Once an EasyDMA transfer is completed, the AMOUNT register can be read by the CPU to see how many bytes were transferred. For example, CPU can read MYPERIPHERAL->WRITER.AMOUNT register to see how many bytes WRITER wrote to RAM. Note: The PTR register of a READER or WRITER must point to a valid memory region before use. The reset value of a PTR register is not guaranteed to point to valid memory. See Memory on page 19 for more information about the different memory regions and EasyDMA connectivity. 4.6.1 EasyDMA error handling Some errors may occur during DMA handling. If READER.PTR or WRITER.PTR is not pointing to a valid memory region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. If several AHB bus masters try to access the same AHB slave at the same time, AHB bus congestion might occur. An EasyDMA channel is an AHB master. Depending on the peripheral, the peripheral may either stall and wait for access to be granted, or lose data. 4.6.2 EasyDMA array list EasyDMA is able to operate in Array List mode. The Array List mode is implemented in channels where the LIST register is available. The array list does not provide a mechanism to explicitly specify where the next item in the list is located. Instead, it assumes that the list is organized as a linear array where items are located one after the other in RAM. 4452_021 v1.3 45 The EasyDMA Array List can be implemented by using the data structure ArrayList_type as illustrated in the code example below using a READER EasyDMA channel as an example:

Core components

#define BUFFER_SIZE 4 typedef struct ArrayList uint8_t buffer[BUFFER_SIZE];

} ArrayList_type;

ArrayList_type ReaderList[3] __at__ 0x20000000;

MYPERIPHERAL->READER.MAXCNT = BUFFER_SIZE;

MYPERIPHERAL->READER.PTR = &ReaderList;

MYPERIPHERAL->READER.LIST = MYPERIPHERAL_READER_LIST_ArrayList;

The data structure only includes a buffer with size equal to the size of READER.MAXCNT register. EasyDMA uses the READER.MAXCNT register to determine when the buffer is full. READER.PTR = &ReaderList 0x20000000 : ReaderList[0]

0x20000004 : ReaderList[1]

0x20000008 : ReaderList[2]

buffer[0]

buffer[0]

buffer[0]

buffer[1]

buffer[1]

buffer[1]

buffer[2]

buffer[2]

buffer[2]

buffer[3]

buffer[3]

buffer[3]

Figure 6: EasyDMA array list 4.7 AHB multilayer AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access is resolved using priorities. Each bus master is connected to all the slave devices using an interconnection matrix. The bus masters are assigned priorities, which are used to resolve access when two (or more) bus masters request access to the same slave device. When that occurs, the following rules apply:

If two (or more) bus masters request access to the same slave device, the master with the highest Bus masters with lower priority are stalled until the higher priority master has completed its priority is granted the access first. transaction. If the higher priority master pauses at any point during its transaction, the lower priority master in queue is temporarily granted access to the slave device until the higher priority master resumes its activity. Bus masters that have the same priority are mutually exclusive, thus cannot be used concurrently. Some peripherals, such as RADIO, do not have a safe stalling mechanism (no internal data buffering, or opportunity to pause incoming data). Being a low priority bus master might cause loss of data for such peripherals upon bus contention. To avoid AHB bus contention when using multiple bus masters, follow these guidelines:

4452_021 v1.3 46 Avoid situations where more than one bus master is accessing the same slave. If more than one bus master is accessing the same slave, make sure that the bus bandwidth is not Core components Below is a list of bus masters in the system and their priorities. Description SPIM1/SPIS1/TWIM1/TWIS1 Same priority and mutually exclusive Same priority and mutually exclusive SPIM0/SPIS0/TWIM0/TWIS0 SPIM2/SPIS2 Same priority and mutually exclusive Same priority and mutually exclusive exhausted. Bus master name CPU CTRL-AP USB RADIO CCM/ECB/AAR SAADC UARTE0 NFCT I2S PDM PWM0 PWM1 PWM2 PWM3 UARTE1 SPIM3 Table 12: AHB bus masters (listed from highest to lowest priority) Defined bus masters are the CPU and peripherals with implemented EasyDMA. The available slaves are RAM AHB slaves. How the bus masters and slaves are connected using the interconnection matrix is illustrated in Memory on page 19. 4.8 Debug and trace Debug and trace system offers a flexible and powerful mechanism for non-intrusive debugging. External debugger DAP SWDCLK SWDIO SW-DP DAP bus interconnect CTRL-AP APPROTECT.PALL NVMC UICR AHB-AP AHB RAM & flash CxxxPWRUPREQ CxxxPWRUPRACK POWER Power CPU ARM Cortex-M4 TRACECLK TRACEDATA[0] / SWO TRACEDATA[1]

TRACEDATA[2]

TRACEDATA[3]

TPIU Trace ETM Trace ITM APB/AHB Peripherals Figure 7: Debug and trace overview 4452_021 v1.3 47 Core components The main features of the debug and trace system are the following:

Two-pin serial wire debug (SWD) interface Flash patch and breakpoint (FPB) unit that supports:

Two literal comparators Six instruction comparators Data watchpoint and trace (DWT) unit with four comparators Instrumentation trace macrocell (ITM) Embedded trace macrocell (ETM) Trace port interface unit (TPIU) 4-bit parallel trace of ITM and ETM trace data Serial wire output (SWO) trace of ITM data 4.8.1 DAP - Debug access port An external debugger can access the device via the DAP. The debug access port (DAP) implements a standard ARM CoreSight serial wire debug port (SW-DP), which implements the serial wire debug protocol (SWD). SWD is a two-pin serial interface, see SWDCLK and SWDIO in Debug and trace overview on page 47. In addition to the default access port in CPU (AHB-AP), the DAP includes a custom control access port

(CTRL-AP). The CTRL-AP is described in more detail in CTRL-AP - Control access port on page 48. Note:

The SWDIO line has an internal pull-up resistor. The SWDCLK line has an internal pull-down resistor. 4.8.2 CTRL-AP - Control access port The control access port (CTRL-AP) is a custom access port that enables control of the device when other access ports in the DAP are disabled by the access port protection. Access port protection blocks the debugger from read and write access to all CPU registers and memory-

mapped addresses. See the UICR register APPROTECT on page 42 for more information on enabling access port protection. Control access port has the following features:

Soft reset, see Reset on page 67 for more information Disabling of access port protection, which is the reason why CTRL-AP allows control of the device even when all other access ports in the DAP are disabled by the access port protection Access port protection is disabled by issuing an ERASEALL command via CTRL-AP. This command will erase the flash, UICR, and RAM. 4452_021 v1.3 48 Core components 4.8.2.1 Registers Register RESET ERASEALL ERASEALLSTATUS APPROTECTSTATUS IDR Offset 0x000 0x004 0x008 0x00C 0x0FC Description Erase all Soft reset triggered through CTRL-AP Status register for the ERASEALL operation Status register for access port protection CTRL-AP identification register, IDR Table 13: Register overview 4.8.2.1.1 RESET Address offset: 0x000 Soft reset triggered through CTRL-AP Bit number ID ID A Reset 0x00000000 AccessField RW RESET 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NoReset Reset Soft reset triggered through CTRL-AP. See Reset behavior in POWER chapter for more details. Reset is not active Reset is active. Device is held in reset. 4.8.2.1.2 ERASEALL Address offset: 0x004 Erase all Bit number Reset 0x00000000 AccessField W ERASEALL ID ID A ID ID A 4.8.2.1.3 ERASEALLSTATUS Address offset: 0x008 Status register for the ERASEALL operation 0 1 0 1 0 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NoOperation Erase Erase all flash and RAM No operation Erase all flash and RAM Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R ERASEALLSTATUS Status register for the ERASEALL operation Ready Busy ERASEALL is ready ERASEALL is busy (on-going) 4452_021 v1.3 49 A A A Core components 4.8.2.1.4 APPROTECTSTATUS Address offset: 0x00C Status register for access port protection ID ID A ID ID A B C D E Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R APPROTECTSTATUS Enabled Disabled 0 1 Status register for access port protection Access port protection enabled Access port protection not enabled 4.8.2.1.5 IDR Address offset: 0x0FC CTRL-AP identification register, IDR Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E E E E D D D D C C C C C C C B B B B A A A A A A A A Reset 0x02880000 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R R R R R APID CLASS JEP106ID JEP106CONT REVISION NotDefined MEMAP 0x0 0x8 AP identification Access port (AP) class No defined class Memory access port JEDEC JEP106 identity code JEDEC JEP106 continuation code Revision 4.8.2.2 Electrical specification 4.8.2.2.1 Control access port Symbol Rpull fSWDCLK Description SWDCLK frequency Internal SWDIO and SWDCLK pull up/down resistance Min. Typ. Max. Units 13 0.125 8 k MHz 4.8.3 Debug interface mode Before an external debugger can access either CPU's access port (AHB-AP) or the control access port

(CTRL-AP), the debugger must first request the device to power up via CxxxPWRUPREQ in the SWJ-DP. If the device is in System OFF when power is requested via CxxxPWRUPREQ, the system will wake up and the DIF flag in RESETREAS on page 73 will be set. The device is in the debug interface mode as long as the debugger is requesting power via CxxxPWRUPREQ. Once the debugger stops requesting power via CxxxPWRUPREQ, the device is back in normal mode. Some peripherals behave differently in Debug Interface mode compared to normal mode. These differences are described in more detail in the chapters of the peripherals that are affected. When a debug session is over, the external debugger must make sure to put the device back into normal mode since the overall power consumption is higher in debug interface mode than in normal mode. For details on how to use the debug capabilities, read the debug documentation of your IDE. 4452_021 v1.3 50 Core components 4.8.4 Real-time debug The nRF52833 supports real-time debugging. Real-time debugging allows interrupts to execute to completion in real time when breakpoints are set in thread mode or lower priority interrupts. This enables developers to set breakpoints and single-step through the code without the risk of real-time event-driven threads running at higher priority failing. For example, this enables the device to continue to service the high-priority interrupts of an external controller or sensor without failure or loss of state synchronization while the developer steps through code in a low-priority thread. 4.8.5 Trace The device supports ETM and ITM trace. Trace data from the ETM and the ITM is sent to an external debugger via a 4-bit wide parallel trace port interface unit (TPIU), see TRACEDATA[0] through TRACEDATA[3] and TRACECLK in Debug and trace overview on page 47. In addition to parallel trace, the TPIU supports serial trace via the serial wire output (SWO) trace protocol. Parallel and serial trace cannot be used at the same time. ETM trace is only supported in Parallel Trace mode, while ITM trace is supported in both Parallel and Serial Trace modes. For details on how to use the trace capabilities, read the debug documentation of your IDE. TPIU's trace pins are multiplexed with GPIOs. SWO and TRACEDATA[0] use the same GPIO. See Pin assignments on page 557 for more information. Trace speed is configured in register TRACECONFIG on page 93. The speed of the trace pins depends on the DRIVE setting of the GPIOs that the trace pins are multiplexed with. Only S0S1 and H0H1 drives are suitable for debugging. S0S1 is the default DRIVE setting at reset. If parallel or serial trace port signals are not fast enough with the default settings, all GPIOs in use for tracing should be set to high drive (H0H1). The DRIVE setting for these GPIOs should not be overwritten by firmware during the debugging session. 4.8.5.1 Electrical specification 4.8.5.1.1 Trace port Symbol Tcyc Description Clock period as defined by Arm in the Timing specifications for Trace Port Physical Interface of the Embedded Trace Macrocell Architecture Specification Min. 62.5 Typ. Max. Units 500 ns 4452_021 v1.3 51 5 Power and clock management 5.1 Power management unit (PMU) Power and clock management in nRF52833 is designed to automatically ensure maximum power efficiency. The core of the power and clock management system is the power management unit (PMU) illustrated in the following figure. MCU External power sources Internal voltage regulators External crystals Internal oscillators PMU CPU Memory Peripheral Figure 8: Power management unit The PMU automatically detects which power and clock resources are required by the different system components at any given time. The PMU will then automatically start/stop and choose operation modes in supply regulators and clock sources, to achieve the lowest power consumption possible. 5.2 Current consumption Because the system is continually being tuned by the Power management unit (PMU) on page 52, estimating an application's current consumption can be challenging when measurements cannot be directly performed on the hardware. To facilitate the estimation process, a set of current consumption scenarios are provided to show the typical current drawn from the VDD supply. Each scenario specifies a set of operations and conditions applying to the given scenario. The following table shows a set of common conditions used in all scenarios, unless otherwise stated in the description of a given scenario. All scenarios are listed in Electrical specification on page 53. 4452_021 v1.3 52 Power and clock management 3 V on VDD/VDDH (Normal voltage mode) CPU WFI (wait for interrupt)/WFE (wait for event) sleep Condition Supply Value Temperature 25C Peripherals All idle Not running LDO Clock Regulator RAM Compiler In System ON, full 128 kB powered. In System OFF, full 128 kB retention. GCC v7.3.1 20180622 (release) [ARM/embedded-7-branch revision 261907]

(GNU Tools for Arm Embedded Processors 7-2018-q3-update). Compiler flags: -O0 -falign-functions=16 -fno-strict-

aliasing -mthumb -mcpu=cortex-m4 -mfloat-abi=hard

-mfpu=fpv4-sp-d16. Compiler flags: -xc -std=gnu99 --target=arm-arm-none-

eabi -mcpu=cortex-m4 -mfpu=none -mfloat-abi=soft

-c -fno-rtti -funsigned-char -gdwarf-3 -fropi -

Ofast -ffunction-sections -Omax Linker flags: --cpu=Cortex-M4 --fpu=SoftVFP --strict -

Compiler for CPU Running and Compounded ARMCC v6.13. Omax Yes Cache enabled2 32 MHz crystal3 SMD 2520, 32 MHz, 10 pF +/- 10 ppm Table 14: Current consumption scenarios, common conditions Symbol Description Min. Typ. Max. Units 5.2.1 Electrical specification 5.2.1.1 Sleep ION_RAMOFF_EVENT System ON, no RAM retention, wake on any event ION_RAMON_EVENT System ON, full 128 kB RAM retention, wake on any event ION_RAMON_POF System ON, full 128 kB RAM retention, wake on any event, power-fail comparator enabled ION_RAMON_GPIOTE System ON, full 128 kB RAM retention, wake on GPIOTE ION_RAMON_GPIOTEPORTSystem ON, full 128 kB RAM retention, wake on GPIOTE ION_RAMOFF_RTC System ON, no RAM retention, wake on RTC (running from input (event mode) PORT event LFRC clock) ION_RAMON_RTC System ON, full 128 kB RAM retention, wake on RTC

(running from LFRC clock) 2 Applies only when CPU is running from flash memory 3 Applies only when HFXO is running 4452_021 v1.3 53 1.1 1.8 1.9 7.4 1.8 1.5 2.6 A A A A A A A Symbol Description Min. Typ. Max. Units IOFF_RAMOFF_RESET System OFF, no RAM retention, wake on reset IOFF_RAMOFF_LPCOMP System OFF, no RAM retention, wake on LPCOMP IOFF_RAMON_RESET System OFF, full 128 kB RAM retention, wake on reset ION_RAMOFF_EVENT_5V System ON, no RAM retention, wake on any event, 5 V supply on VDDH, REG0 output = 3.3 V IOFF_RAMOFF_RESET_5V System OFF, no RAM retention, wake on reset, 5 V supply on VDDH, REG0 output = 3.3 V Power and clock management 0.6 0.9 1.3 1.3 1.0 A A A A A

A

n o i t p m u s n o c t n e r r u C 9 8 7 6 5 4 3 2 1 0

-40

-20 0 20 40 60 80 100 120 Temperature Range [C]

1.7 V 3 V 3.6 V Figure 9: System OFF, no RAM retention, wake on reset (typical values) 4452_021 v1.3 54 Power and clock management

A

n o i t p m u s n o c t n e r r u C 16 14 12 10 8 6 4 2 0

-40

-20 0 20 40 60 80 100 120 Temperature Range [C]

1.7 V 3 V 3.6 V Figure 10: System ON, no RAM retention, wake on any event (typical values) 5.2.1.2 COMP active Symbol ICOMP,LP ICOMP,NORM ICOMP,HS Description COMP enabled, low power mode COMP enabled, normal mode COMP enabled, high-speed mode 5.2.1.3 CPU running Symbol ICPU0 ICPU1 ICPU2 ICPU3 ICPU4 Description Regulator = DC/DC Regulator = DC/DC Regulator = DC/DC CPU running CoreMark @64 MHz from flash, Clock = HFXO, CPU running CoreMark @64 MHz from flash, Clock = HFXO CPU running CoreMark @64 MHz from RAM, Clock = HFXO, CPU running CoreMark @64 MHz from RAM, Clock = HFXO CPU running CoreMark @64 MHz from flash, Clock = HFINT, 5.2.1.4 NFCT active Symbol Isense Iactivated Description Current in SENSE STATE4 Current in ACTIVATED STATE 4 This current does not apply when in NFC field 4452_021 v1.3 55 Min. Max. Units Min. Max. Units Typ. 22.7 26.4 33.0 Typ. 3.3 5.6 2.4 4.7 3.1 100 400 A A A mA mA mA mA mA nA A Min. Typ. Max. Units 5.2.1.5 Radio transmitting/receiving Symbol IRADIO_TX0 Description

= DC/DC Radio transmitting @ 8 dBm output power, 1 Mbps Bluetooth low energy (BLE) mode, Clock = HFXO, Regulator IRADIO_TX1 Radio transmitting @ 0 dBm output power, 1 Mbps BLE mode, Clock = HFXO, Regulator = DC/DC IRADIO_TX2 Radio transmitting @ -40 dBm output power, 1 Mbps BLE mode, Clock = HFXO, Regulator = DC/DC IRADIO_TX3 Radio transmitting @ 0 dBm output power, 1 Mbps BLE IRADIO_TX4 Radio transmitting @ -40 dBm output power, 1 Mbps BLE mode, Clock = HFXO mode, Clock = HFXO IRADIO_TX5 Radio transmitting @ 0 dBm output power, 250 kbit/s IEE 802.15.4-2006 mode, Clock = HFXO, Regulator = DC/DC IRADIO_RX0 Radio receiving @ 1 Mbps BLE mode, Clock = HFXO, Regulator = DC/DC IRADIO_RX1 IRADIO_RX2 Radio receiving @ 1 Mbps BLE mode, Clock = HFXO Radio receiving @ 250 kbit/s IEE 802.15.4-2006 mode, Clock

= HFXO, Regulator = DC/DC Power and clock management Min. Max. Units Typ. 15.5 6.0 3.5 11.0 5.4 6.0 6.0 10.5 6.2 mA mA mA mA mA mA mA mA mA

A m

n o i t p m u s n o c t n e r r u C 28 26 24 22 20 18 16 14 12 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

-40 C 25 C 85 C 105 C Supply voltage [V]

Figure 11: Radio transmitting @ 8 dBm output power, 1 Mbps BLE mode, Clock = HFXO, Regulator = DC/DC (typical values) 4452_021 v1.3 56 Power and clock management

A m

n o i t p m u s n o c t n e r r u C 9.5 8.5 7.5 6.5 9 8 7 6 5 5.5 5.2.1.6 RNG active Symbol IRNG0 Description RNG running 5.2.1.7 SAADC active 5.2.1.8 TEMP active Symbol ITEMP0 Description TEMP started 5.2.1.9 TIMER running 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

-40 C 25 C 85 C 105 C Supply voltage [V]

Figure 12: Radio transmitting @ 0 dBm output power, 1 Mbps BLE mode, Clock = HFXO, Regulator = DC/DC (typical values) Min. Max. Units Typ. 539 Typ. 1.37 Typ. 0.92 342 341 573 497 729 A mA mA A A A A A Min. Max. Units Symbol ISAADC,RUN Description SAADC sampling @ 16 ksps, Acquisition time = 20 s, Clock =

HFXO, Regulator = DC/DC Min. Max. Units Symbol Description Min. Typ. Max. Units ITIMER0 ITIMER1 ITIMER2 ITIMER3 ITIMER4 One TIMER instance running @ 1 MHz, Clock = HFINT Two TIMER instances running @ 1 MHz, Clock = HFINT One TIMER instance running @ 1 MHz, Clock = HFXO One TIMER instance running @ 16 MHz, Clock = HFINT One TIMER instance running @ 16 MHz, Clock = HFXO 4452_021 v1.3 57 5.2.1.10 USBD running Symbol Description IUSB,ACTIVE,VBUS Current from VBUS supply, USB active IUSB,SUSPEND,VBUS Current from VBUS supply, USB suspended, CPU sleeping IUSB,ACTIVE,VDD Current from VDD supply (normal voltage mode), all RAM retained, regulator=LDO, CPU running, USB active IUSB,SUSPEND,VDD Current from VDD supply (normal voltage mode), all RAM retained, regulator=LDO, CPU sleeping, USB suspended IUSB,ACTIVE,VDDH Current from VDDH supply (high voltage mode), VDD=3 V (REG0 output), all RAM retained, regulator=LDO, CPU running, USB active IUSB,SUSPEND,VDDH Current from VDDH supply (high voltage mode), VDD=3 V (REG0 output), all RAM retained, regulator=LDO, CPU sleeping, USB suspended IUSB,DISABLED,VDD Current from VDD supply, USB disabled, VBUS supply connected, all RAM retained, regulator=LDO, CPU sleeping 5.2.1.11 WDT active Symbol Description IWDT,STARTED WDT started 5.2.1.12 Compounded IS0 IS1 IS2 IS3 CPU running CoreMark from flash, Radio transmitting @

0 dBm output power, 1 Mbps Bluetooth low energy (BLE) mode, Clock = HFXO, Regulator = DC/DC CPU running CoreMark from flash, Radio receiving @ 1 Mbps BLE mode, Clock = HFXO, Regulator = DC/DC CPU running CoreMark from flash, Radio transmitting @ 0 dBm output power, 1 Mbps BLE mode, Clock = HFXO CPU running CoreMark from flash, Radio receiving @ 1 Mbps BLE mode, Clock = HFXO Power and clock management Min. Typ. Max. Units 2.4 262 7.73 173 7.46 178 7 Typ. 2.5 Typ. 8.5 8.3 16.7 16.2 mA A mA A mA A A A mA mA mA mA Min. Max. Units Symbol Description Min. Max. Units 5.3 POWER Power supply The power supply consists of a number of LDO and DC/DC regulators that are utilized to maximize the system's power efficiency. This device has the following power supply features:

On-chip LDO and DC/DC regulators Global System ON/OFF modes Individual RAM section power control for all system modes Analog or digital pin wakeup from System OFF Supervisor hardware to manage power-on reset, brownout, and power failure Auto-controlled refresh modes for LDO and DC/DC regulators to maximize efficiency Separate USB supply 4452_021 v1.3 58 Power and clock management 5.3.1 Main supply The main supply voltage is connected to the VDD/VDDH pins. The system will enter one of two supply voltage modes, Normal or High Voltage mode, depending on how the supply voltage is connected to these pins. The system enters Normal Voltage mode when the supply voltage is connected to both the VDD and VDDH pins (pin VDD shorted to pin VDDH). For the supply voltage range to connect to both VDD and VDDH pins, see parameter VDD. The system enters High Voltage mode when the supply voltage is only connected to the VDDH pin and the VDD pin is not connected to any voltage supply. For the supply voltage range to connect to the VDDH pin, see parameter VDDH. The register MAINREGSTATUS on page 76 can be used to read the current supply voltage mode. 5.3.1.1 Main voltage regulators The system contains two main supply regulator stages, REG0 and REG1. REG1 regulator stage has the regulator type options of Low-droput regulator (LDO) and Buck regulator

(DC/DC). REG0 regulator stage has only the option of Low-dropout regulator (LDO). In Normal Voltage mode, only the REG1 regulator stage is used, and the REG0 stage is automatically disabled. In High Voltage mode, both regulator stages (REG0 and REG1) are used. The output voltage of REG0 can be configured in register REGOUT0 on page 43. This output voltage is connected to VDD and is the input voltage to REG1. Note: In High Voltage mode, the configured output voltage for REG0 (REGOUT0 on page 43) must not be greater than REG0 input voltage minus the voltage drop in REG0 (VDDH - VREG0,DROP). By default, the LDO regulators are enabled and the DC/DC regulator of REG1 stage is disabled. Register DCDCEN on page 76 is used to enable the DC/DC regulator for REG1 stage. When the REG1 DC/DC converter is enabled, the LDO for the REG1 stage will be disabled. External LC filters must be connected for the DC/DC regulator if it is being used. The advantage of using the DC/DC regulator is that the overall power consumption is normally reduced as the efficiency of such a regulator is higher than that of a LDO. The efficiency gained by using the DC/DC regulator is best seen when the regulator voltage drop (difference between input and output voltage) is high. The efficiency of internal regulators vary with the supply voltage and the current drawn from the regulators. Note: Do not enable the DC/DC regulator without an external LC filter being connected as this will inhibit device operation, including debug access, until an LC filter is connected. 5.3.1.2 GPIO levels The GPIO high reference voltage is equal to the level on the VDD pin. In Normal Voltage mode, the GPIO high level equals the voltage supplied to the VDD pin. In High Voltage mode, it equals the level specified in register REGOUT0 on page 43. 5.3.1.3 Regulator configuration examples The voltage regulators can be configured in several ways, depending on the selected supply voltage mode

(Normal/High) and the regulator type option for REG1 (LDO or DC/DC). Four configuration examples are illustrated in the following figures. 4452_021 v1.3 59 Power and clock management Main supply REGOUT0 DCDCEN Supply REG0 REG1 VDDH LDO 1.3V System power VDD DCC DEC4 GND Figure 13: Normal Voltage mode, REG1 LDO Main supply REGOUT0 DCDCEN REG0 REG1 Supply VDDH LDO 1.3V System power VDD DCC DEC4 GND LDO DC/DC LDO DC/DC Figure 14: Normal Voltage mode, REG1 DC/DC 4452_021 v1.3 60 Power and clock management Main supply REGOUT0 DCDCEN REG0 REG1 Supply VDDH LDO LDO DC/DC 1.3V System power VDD DCC DEC4 GND Figure 15: High Voltage mode, REG1 LDO Main supply REGOUT0 DCDCEN REG0 REG1 Supply VDDH LDO LDO DC/DC 1.3V System power VDD DCC DEC4 GND Figure 16: High Voltage mode, REG1 DC/DC 5.3.1.4 Power supply supervisor The power supply supervisor enables monitoring of the connected power supply. The power supply supervisor provides the following functionality:

Power-on reset - signals the circuit when a supply is connected 4452_021 v1.3 61 Power and clock management An optional power-fail comparator (POF) - signals the application when the supply voltages drop below A fixed brownout reset detector - holds the system in reset when the voltage is too low for safe a configured threshold operation The power supply supervisor is illustrated in the following figure. 4452_021 v1.3 62 Power and clock management VDD Brownout reset VBOR C R Power-on reset POFCON.THRESHOLDVDDH POFCON.POF

(VDDH>VDD) VDDH VDD MUX VPOFH MUX VPOF 4.2 V

. 2.8 V 2.7 V 2.8 V

. 1.8 V 1.7 V POFCON.THRESHOLD POFCON.POF Figure 17: Power supply supervisor 4452_021 v1.3 63 POFWARN Power and clock management 5.3.1.5 Power-fail comparator Using the power-fail comparator (POF) is optional. When enabled, it can provide an early warning to the CPU of an impending power supply failure. To enable and configure the power-fail comparator, see the register POFCON on page 75. When the supply voltage falls below the defined threshold, the power-fail comparator generates an event

(POFWARN) that can be used by an application to prepare for power failure. This event is also generated when the supply voltage is already below the threshold at the time the power-fail comparator is enabled, or if the threshold is re-configured to a level above the supply voltage. If the power failure warning is enabled, and the supply voltage is below the threshold, the power-fail comparator will prevent the NVMC from performing write operations to the flash. The comparator features a hysteresis of VHYST, as illustrated in the following figure. Supply (VDD or VDDH) VPOF+VHYST VPOF 1.7V U C M N R A W F O P t N R A W F O P BOR Figure 18: Power-fail comparator (BOR = brownout reset) To save power, the power-fail comparator is not active in System OFF or System ON when HFCLK is not running. 5.3.2 USB supply When using the USB peripheral, a 5 V USB supply needs to be provided to the VBUS pin. The USB peripheral has a dedicated internal voltage regulator for converting the VBUS supply to 3.3 V used by the USB signalling interface (D+ and D- lines, and pull-up on D+). The remainder of the USB peripheral

(USBD) is supplied through the main supply like other on-chip features. As a consequence, VBUS and either VDDH or VDD supplies are required for USB peripheral operation. When VBUS rises into its valid range, the software is notified through a USBDETECTED event. A USBREMOVED event is sent when VBUS goes below its valid range. Use these events to implement the USBD start-up sequence described in the USBD chapter. When VBUS rises into its valid range while the device is in System OFF, the device resets and transitions to System ON mode. The RESETREAS register will have the VBUS bit set to indicate the source of the wake-up. See VBUS detection specifications on page 80 for the levels at which the events are sent (VBUS,DETECT and VBUS,REMOVE) or at which the system is woken up from System OFF (VBUS,DETECT). 4452_021 v1.3 64 Power and clock management When the USBD peripheral is enabled through the ENABLE register, and VBUS is detected, the regulator is turned on. A USBPWRRDY event is sent when the regulator's worst case settling time has elapsed, indicating to the software that it can enable the USB pull-up to signal a USB connection to the host. The software can read the state of the VBUS detection and regulator output readiness at any time through the USBREGSTATUS register. USB supply 5 V USB supply VBUS LDO 3.3 V USB power DECUSB Figure 19: USB voltage regulator To ensure stability, the input and output of the USB regulator need to be decoupled with a suitable decoupling capacitor. See Reference circuitry on page 567 for the recommended values. 5.3.3 System OFF mode System OFF is the deepest power saving mode the system can enter. In this mode, the systems core functionality is powered down and all ongoing tasks are terminated. The device can be put into System OFF mode using the register SYSTEMOFF on page 74. When in System OFF mode, the device can be woken up through one of the following signals:

The DETECT signal, optionally generated by the GPIO peripheral. The ANADETECT signal, optionally generated by the LPCOMP module. The SENSE signal, optionally generated by the NFC module to wake-on-field. Detecting a valid USB voltage on the VBUS pin (VBUS,DETECT). A reset. The system is reset when it wakes up from System OFF mode. One or more RAM sections can be retained in System OFF mode, depending on the settings in the RAM[n].POWER registers. RAM[n].POWER are retained registers. These registers are usually overwritten by the start-up code provided with the nRF application examples. Before entering System OFF mode, all on-going EasyDMA transactions need to have completed. See peripheral specific chapters for more information about how to acquire the status of EasyDMA transactions. 4452_021 v1.3 65 Power and clock management 5.3.3.1 Emulated System OFF mode If the device is in Debug Interface mode, System OFF will be emulated to secure that all required resources needed for debugging are available during System OFF. Required resources needed for debugging include the following key components:

Debug and trace on page 47 CLOCK Clock control on page 80 POWER Power supply on page 58 NVMC Non-volatile memory controller on page 23 CPU on page 18 Flash memory RAM See Debug and trace on page 47 for more information. Because the CPU is kept on in an emulated System OFF mode, it is recommended to add an infinite loop directly after entering System OFF, to prevent the CPU from executing code that normally should not be executed. 5.3.4 System ON mode System ON is the default state after power-on reset. In System ON mode, all functional blocks such as the CPU or peripherals can be in IDLE or RUN mode, depending on the configuration set by the software and the state of the application executing. Register RESETREAS on page 73 provides information about the source causing the wakeup or reset. The system can switch the appropriate internal power sources on and off, depending on the amount of power needed at any given time. The power requirement of a peripheral is directly related to its activity level, and the activity level of a peripheral fluctuates when specific tasks are triggered or events are generated. 5.3.4.1 Sub-power modes In System ON mode, when the CPU and all peripherals are in IDLE mode, the system can reside in one of the two sub-power modes. The sub-power modes are:

Constant Latency Low-power In Constant Latency mode, the CPU wakeup latency and the PPI task response are constant and kept at a minimum. This is secured by forcing a set of basic resources to be turned on while in sleep. The cost of constant and predictable latency is increased power consumption. Constant Latency mode is selected by triggering the CONSTLAT task. In Low-power mode, the automatic power management system described in System ON mode on page 66 ensures that the most efficient supply option is chosen to save power. The cost of having the lowest possible power consumption is a varying CPU wakeup latency and PPI task response. Low-power mode is selected by triggering the LOWPWR task. When the system enters System ON mode, it is by default in the sub-power mode Low-power. 5.3.5 RAM power control The RAM power control registers are used for configuring the following:

The RAM sections to be retained during System OFF The RAM sections to be retained and accessible during System ON 4452_021 v1.3 66 Power and clock management In System OFF, retention of a RAM section is configured in the RETENTION field of the corresponding register RAM[n].POWER (n=0..8) on page 77. In System ON, retention and accessibility of a RAM section is configured in the RETENTION and POWER fields of the corresponding register RAM[n].POWER (n=0..8) on page 77. The following table summarizes the behavior of these registers. Configuration System on/off Off Off On On On x x Off Off5 On RAM[n].POWER.POWER RAM[n].POWER.RETENTION Accessible Retained RAM section status Off On Off On x No No No No Yes No Yes No Yes Yes Table 15: RAM section configuration The advantage of not retaining RAM contents is that the overall current consumption is reduced. See Memory on page 19 for more information on RAM sections. 5.3.6 Reset Several sources may trigger a reset. After a reset has occurred, register RESETREAS can be read to determine which source triggered the reset. 5.3.6.1 Power-on reset The power-on reset generator initializes the system at power-on. The system is held in reset state until the supply has reached the minimum operating voltage and the internal voltage regulators have started. 5.3.6.2 Pin reset A pin reset is generated when the physical reset pin on the device is asserted. Pin reset is configured via both registers PSELRESET[n] (n=0..1) on page 42. 5.3.6.3 Wakeup from System OFF mode reset The device is reset when it wakes up from System OFF mode. The debug access port (DAP) is not reset following a wake up from System OFF mode if the device is in Debug Interface mode. See chapter Debug and trace on page 47 for more information. 5.3.6.4 Soft reset A soft reset is generated when the SYSRESETREQ bit of the application interrupt and reset control register

(AIRCR) in the ARM core is set. See ARM documentation for more details. A soft reset can also be generated via the register RESET on page 49 in the CTRL-AP. 5.3.6.5 Watchdog reset A Watchdog reset is generated when the watchdog times out. 5 Not useful. RAM section power off gives negligible reduction in current consumption when retention is on. 4452_021 v1.3 67 Power and clock management See chapter WDT Watchdog timer on page 552 for more information. 5.3.6.6 Brownout reset The brownout reset generator puts the system in a reset state if VDD drops below the brownout reset

(BOR) threshold. See section Power fail comparator on page 79 for more information. 5.3.6.7 Retained registers A retained register is one that will retain its value in System OFF mode and through a reset, depending on the reset source. See the individual peripheral chapters for information on which of their registers are retained. 5.3.6.8 Reset behavior The various reset sources and their targets are summarized in the table below. Reset source Reset target CPU Peripherals GPIO SWJ-DP RAM WDT Retained RESETREAS Debug6 CPU lockup 7 Soft reset Wakeup from System OFF mode reset Watchdog reset 10 Pin reset Brownout reset Power-on reset x x x x x x x x x x x x x x x x x x x x x 8 x x x x x x x 9 x x x x x x x x x registers x x x x x x Note: The RAM is never reset, but depending on a reset source the content of RAM may be corrupted. 5.3.7 Registers Base address Peripheral 0x40000000 POWER Instance POWER Description Power control Configuration Table 16: Instances Register Offset Description TASKS_CONSTLAT TASKS_LOWPWR 0x78 0x7C Enable Constant Latency mode Enable Low-power mode (variable latency) 6 All debug components excluding SWJ-DP. See Debug and trace on page 47 for more information about the different debug components. 7 Reset from CPU lockup is disabled if the device is in Debug Interface mode. CPU lockup is not possible in System OFF. 8 The debug components will not be reset if the device is in Debug Interface mode. 9 RAM is not reset on wakeup from System OFF mode. RAM, or certain parts of RAM, may not be retained after the device has entered System OFF mode, depending on the settings in the RAM registers. 10 Watchdog reset is not available in System OFF. 4452_021 v1.3 68 Power and clock management Deprecated Register EVENTS_POFWARN EVENTS_SLEEPENTER EVENTS_SLEEPEXIT EVENTS_USBDETECTED EVENTS_USBREMOVED EVENTS_USBPWRRDY INTENSET INTENCLR RESETREAS RAMSTATUS USBREGSTATUS SYSTEMOFF POFCON GPREGRET GPREGRET2 DCDCEN MAINREGSTATUS RAM[0].POWER RAM[0].POWERSET RAM[0].POWERCLR RAM[1].POWER RAM[1].POWERSET RAM[1].POWERCLR RAM[2].POWER RAM[2].POWERSET RAM[2].POWERCLR RAM[3].POWER RAM[3].POWERSET RAM[3].POWERCLR RAM[4].POWER RAM[4].POWERSET RAM[4].POWERCLR RAM[5].POWER RAM[5].POWERSET RAM[5].POWERCLR RAM[6].POWER RAM[6].POWERSET RAM[6].POWERCLR RAM[7].POWER RAM[7].POWERSET RAM[7].POWERCLR RAM[8].POWER RAM[8].POWERSET RAM[8].POWERCLR Offset 0x108 0x114 0x118 0x11C 0x120 0x124 0x304 0x308 0x400 0x428 0x438 0x500 0x510 0x51C 0x520 0x578 0x640 0x900 0x904 0x908 0x910 0x914 0x918 0x920 0x924 0x928 0x930 0x934 0x938 0x940 0x944 0x948 0x950 0x954 0x958 0x960 0x964 0x968 0x970 0x974 0x978 0x980 0x984 0x988 Description Power failure warning CPU entered WFI/WFE sleep CPU exited WFI/WFE sleep Voltage supply detected on VBUS Voltage supply removed from VBUS USB 3.3 V supply ready Enable interrupt Disable interrupt Reset reason RAM status register USB supply status System OFF register Power-fail comparator configuration General purpose retention register General purpose retention register Enable DC/DC converter for REG1 stage Main supply status RAM0 power control register RAM0 power control set register RAM0 power control clear register RAM1 power control register RAM1 power control set register RAM1 power control clear register RAM2 power control register RAM2 power control set register RAM2 power control clear register RAM3 power control register RAM3 power control set register RAM3 power control clear register RAM4 power control register RAM4 power control set register RAM4 power control clear register RAM5 power control register RAM5 power control set register RAM5 power control clear register RAM6 power control register RAM6 power control set register RAM6 power control clear register RAM7 power control register RAM7 power control set register RAM7 power control clear register RAM8 power control register RAM8 power control set register RAM8 power control clear register Table 17: Register overview 5.3.7.1 TASKS_CONSTLAT Address offset: 0x78 Enable Constant Latency mode 4452_021 v1.3 69 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_CONSTLAT Enable Constant Latency mode Trigger 1 Trigger task ID ID A ID ID A ID ID A ID ID A 5.3.7.2 TASKS_LOWPWR Address offset: 0x7C Enable Low-power mode (variable latency) 5.3.7.3 EVENTS_POFWARN Address offset: 0x108 Power failure warning 0 1 0 1 5.3.7.4 EVENTS_SLEEPENTER Address offset: 0x114 CPU entered WFI/WFE sleep RW EVENTS_SLEEPENTER NotGenerated Generated 5.3.7.5 EVENTS_SLEEPEXIT Address offset: 0x118 CPU exited WFI/WFE sleep Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_LOWPWR Enable Low-power mode (variable latency) Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_POFWARN NotGenerated Generated Power failure warning Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description CPU entered WFI/WFE sleep Event not generated Event generated A A A A 4452_021 v1.3 70 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_SLEEPEXIT NotGenerated Generated CPU exited WFI/WFE sleep Event not generated Event generated 5.3.7.6 EVENTS_USBDETECTED Address offset: 0x11C Voltage supply detected on VBUS Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_USBDETECTED Voltage supply detected on VBUS NotGenerated Generated Event not generated Event generated 5.3.7.7 EVENTS_USBREMOVED Address offset: 0x120 Voltage supply removed from VBUS Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_USBREMOVED Voltage supply removed from VBUS NotGenerated Generated Event not generated Event generated 5.3.7.8 EVENTS_USBPWRRDY Address offset: 0x124 USB 3.3 V supply ready Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_USBPWRRDY NotGenerated Generated USB 3.3 V supply ready Event not generated Event generated ID ID A ID ID A ID ID A ID ID A A A A A 0 1 0 1 0 1 0 1 5.3.7.9 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.3 71 ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW POFWARN Write '1' to enable interrupt for event POFWARN Power and clock management F E D C B A B RW SLEEPENTER Write '1' to enable interrupt for event SLEEPENTER C RW SLEEPEXIT Write '1' to enable interrupt for event SLEEPEXIT D RW USBDETECTED Write '1' to enable interrupt for event USBDETECTED E RW USBREMOVED Write '1' to enable interrupt for event USBREMOVED F RW USBPWRRDY Write '1' to enable interrupt for event USBPWRRDY 5.3.7.10 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW POFWARN Write '1' to disable interrupt for event POFWARN B RW SLEEPENTER Write '1' to disable interrupt for event SLEEPENTER C RW SLEEPEXIT Write '1' to disable interrupt for event SLEEPEXIT D RW USBDETECTED Write '1' to disable interrupt for event USBDETECTED 4452_021 v1.3 72 Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Power and clock management Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value E RW USBREMOVED Write '1' to disable interrupt for event USBREMOVED F RW USBPWRRDY Write '1' to disable interrupt for event USBPWRRDY Value ID Enabled Clear Disabled Enabled Clear Disabled Enabled NotDetected Detected NotDetected Detected NotDetected Detected NotDetected Detected NotDetected Detected NotDetected Detected NotDetected Detected NotDetected 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 5.3.7.11 RESETREAS Address offset: 0x400 Reset reason Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it. If none of the reset sources are flagged, this indicates that the chip was reset from the on-chip reset generator, which will indicate a power-on-reset or a brownout reset. Bit number ID ID A Reset 0x00000000 AccessField RW RESETPIN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Reset from pin-reset detected B RW DOG Reset from watchdog detected C RW SREQ Reset from soft reset detected D RW LOCKUP Reset from CPU lock-up detected E RW OFF F RW LPCOMP G RW DIF Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode H RW NFC Reset due to wake up from System OFF mode by NFC field 4452_021 v1.3 73 Description Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Not detected Detected Not detected Detected Not detected Detected Not detected Detected Not detected Detected Not detected Detected Not detected Detected detect Not detected Power and clock management Bit number ID Reset 0x00000000 ID AccessField I RW VBUS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Detected NotDetected Detected Value 1 0 1 Description Detected into valid range Not detected Detected Reset due to wake up from System OFF mode by VBUS rising 5.3.7.12 RAMSTATUS ( Deprecated ) Address offset: 0x428 RAM status register Since this register is deprecated the following substitutions have been made: RAM block 0 is equivalent to a block comprising RAM0.S0 and RAM1.S0, RAM block 1 is equivalent to a block comprising RAM2.S0 and RAM3.S0, RAM block 2 is equivalent to a block comprising RAM4.S0 and RAM5.S0 and RAM block 3 is equivalent to a block comprising RAM6.S0 and RAM7.S0. A RAM block field will indicate ON as long as any of the RAM sections associated with a block are on. Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-D R RAMBLOCK[i] (i=0..3) RAM block i is on or off/powering up Value ID Value Description Off On Off On Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) VBUS voltage below valid threshold VBUS voltage above valid threshold USB supply output settling time elapsed USBREG output settling time not elapsed USBREG output settling time elapsed (same information as USBPWRRDY event) 0 1 0 1 0 1 5.3.7.13 USBREGSTATUS Address offset: 0x438 USB supply status ID ID A R VBUSDETECT B R OUTPUTRDY NoVbus VbusPresent NotReady Ready 5.3.7.14 SYSTEMOFF Address offset: 0x500 System OFF register 4452_021 v1.3 74 ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W SYSTEMOFF Enter 1 Enable System OFF mode Enable System OFF mode Power and clock management A 5.3.7.15 POFCON Address offset: 0x510 Power-fail comparator configuration Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D D D D B B B B A Reset 0x00000000 AccessField RW POF B RW THRESHOLD Value ID Value Description Enable or disable power failure warning Disabled Enabled Disable Enable Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. 0 1 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V27 V28 V29 V30 V31 V32 V33 V34 V35 V36 V37 V38 Set threshold to 1.7 V Set threshold to 1.8 V Set threshold to 1.9 V Set threshold to 2.0 V Set threshold to 2.1 V Set threshold to 2.2 V Set threshold to 2.3 V Set threshold to 2.4 V Set threshold to 2.5 V Set threshold to 2.6 V Set threshold to 2.7 V Set threshold to 2.8 V both VDD and VDDH). Set threshold to 2.7 V Set threshold to 2.8 V Set threshold to 2.9 V Set threshold to 3.0 V Set threshold to 3.1 V Set threshold to 3.2 V Set threshold to 3.3 V Set threshold to 3.4 V Set threshold to 3.5 V Set threshold to 3.6 V Set threshold to 3.7 V Set threshold to 3.8 V 4452_021 v1.3 75 D RW THRESHOLDVDDH Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to Power and clock management 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D D D D B B B B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit number ID Reset 0x00000000 ID AccessField 5.3.7.16 GPREGRET Address offset: 0x51C General purpose retention register Value ID Value Description V39 V40 V41 V42 12 13 14 15 Set threshold to 3.9 V Set threshold to 4.0 V Set threshold to 4.1 V Set threshold to 4.2 V Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW GPREGRET General purpose retention register This register is a retained register 5.3.7.17 GPREGRET2 Address offset: 0x520 General purpose retention register 5.3.7.18 DCDCEN Address offset: 0x578 Enable DC/DC converter for REG1 stage ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW GPREGRET General purpose retention register This register is a retained register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A Reset 0x00000000 AccessField RW DCDCEN Value ID Value Description Enable DC/DC converter for REG1 stage. Disabled Enabled 0 1 Disable Enable 5.3.7.19 MAINREGSTATUS Address offset: 0x640 Main supply status 4452_021 v1.3 76 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R MAINREGSTATUS Main supply status Normal High Normal voltage mode. Voltage supplied on VDD. High voltage mode. Voltage supplied on VDDH. Power and clock management A 5.3.7.20 RAM[n].POWER (n=0..8) Address offset: 0x900 + (n 0x10) RAMn power control register Bit number ID Reset 0x0000FFFF ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A-P RW S[i]POWER (i=0..15) Keep RAM section Si on or off in System ON mode. Value ID Value Description RAM sections are always retained when on, but can also be retained when off depending on the settings in SiRETENTION. All RAM sections will be off in System OFF Q-f RW S[i]RETENTION (i=0..15) Keep retention on RAM section Si when RAM section is off 5.3.7.21 RAM[n].POWERSET (n=0..8) Address offset: 0x904 + (n 0x10) RAMn power control set register When read, this register will return the value of the POWER register. Bit number ID Reset 0x0000FFFF ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A-P W S[i]POWER (i=0..15) Keep RAM section Si of RAMn on or off in System ON mode Value ID Value Description Q-f W S[i]RETENTION (i=0..15) Keep retention on RAM section Si when RAM section is mode. Off On Off On On On switched off Off On Off On On On 0 1 0 1 0 1 1 1 5.3.7.22 RAM[n].POWERCLR (n=0..8) Address offset: 0x908 + (n 0x10) RAMn power control clear register When read, this register will return the value of the POWER register. 4452_021 v1.3 77 Power and clock management 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit number ID Reset 0x0000FFFF ID AccessField A-P W S[i]POWER (i=0..15) Keep RAM section Si of RAMn on or off in System ON mode Q-f W S[i]RETENTION (i=0..15) Keep retention on RAM section Si when RAM section is Value ID Value Description Off Off 1 1 Off Off switched off 5.3.8 Electrical specification 5.3.8.1 Regulator operating conditions Symbol VDD,POR VDD VDDH CVDD CDEC4 Description VDD supply voltage needed during power-on reset Normal voltage mode operating voltage High voltage mode operating voltage Effective decoupling capacitance on the VDD pin Effective decoupling capacitance on the DEC4 pin 5.3.8.2 Regulator specifications, REG0 stage Symbol VREG0OUT Description REG0 output voltage VREG0OUT,ERR REG0 output voltage error (deviation from setting in REGOUT0 on page 43) VREG0OUT,ERR,EXT REG0 output voltage error (deviation from setting in REGOUT0 on page 43), extended temperature range VVDDH-VDD Required difference between input voltage (VDDH) and output voltage (VDD, configured in REGOUT0 on page 43), VDDH > VDD 5.3.8.3 Device startup times Symbol tPOR tPOR,10s tPOR,10ms tPOR,60ms Time in power-on reset after supply reaches minimum operating voltage, depending on supply rise time VDD rise time 10 s11 VDD rise time 10 ms11 VDD rise time 60 ms11 VDDH supply voltage11 tRISE,REG0OUT REG0 output (VDD) rise time after VDDH reaches minimum tRISE,REG0OUT,10s VDDH rise time 10 s11 tRISE,REG0OUT,10ms VDDH rise time 10 ms11 tRISE,REG0OUT,100ms VDDH rise time 100 ms11 tPINR Reset time when using pin reset, depending on pin capacitance tPINR,500nF 500 nF capacitance at reset pin Min. Typ. Max. Units Min. 1.75 1.7 2.5 2.7 0.7 1.8

-10

-10 0.3 Typ. Max. Units 3.6 5.5 5.5 1.3 3.3 5 7 10 110 V V V F F V

V ms ms ms ms ms ms 3.0 3.7 4.7 1 1 9 23 5 50 0.22 1.55 30 80 32.5 ms Description Min. Typ. Max. Units 11 See Recommended operating conditions on page 608 for more information. 4452_021 v1.3 78 VPOFTOL Threshold voltage tolerance (applies in both Normal voltage 5

VPOFHYST Threshold voltage hysteresis (applies in both Normal voltage 50 60 mV VBOR,OFF Brownout reset voltage range System OFF mode. Brownout 1.62 VBOR,ON Brownout reset voltage range System ON mode. Brownout 1.57 1.6 1.63 mode and High voltage mode) mode and High voltage mode) only applies to the voltage on VDD only applies to the voltage on VDD Power and clock management Min. Typ. Max. Units 650 ms tPOR tPOR +

tPINR 16.5 3.0 0.0625 0.0625 ms ms s s s s V V V V V V A ms V F Min. Typ. Max. Units 2.8 4.2 1.7 2.7

-5 40 1.2 Typ. Max. Units 5 5.5 Min. 4.35 VSS - 0.3 VUSB33

+ 0.3 Min. Max. Units Typ. 170 1 3.0 3.3 2.35 4.7 3.6 2 5.5 Description 10 F capacitance at reset pin Time from power-on reset to System ON tR2ON,NOTCONF If reset pin not configured tR2ON,CONF If reset pin configured Symbol tPINR,10F tR2ON tOFF2ON tIDLE2CPU tEVTSET,CL1 Time from OFF to CPU execute Time from IDLE to CPU execute Time from HW event to PPI event in Constant Latency tEVTSET,CL0 Time from HW event to PPI event in Low Power System ON System ON mode mode 5.3.8.4 Power fail comparator Symbol VPOF,NV Description Nominal power level warning thresholds (falling supply voltage) in Normal voltage mode (supply on VDD). Levels are configurable between Min. and Max. in 100 mV increments VPOF,HV Nominal power level warning thresholds (falling supply voltage) in High voltage mode (supply on VDDH). Levels are configurable in 100 mV increments 5.3.8.5 USB operating conditions Symbol VBUS VDPDM Description Supply voltage on VBUS pin Voltage on D+ and D- lines 5.3.8.6 USB regulator specifications Symbol IUSB,QUIES Description enabled) USB regulator quiescent current drawn from VBUS (USBD tUSBPWRRDY Time from USB enabled to USBPWRRDY event triggered, VBUS supply provided VUSB33 RSOURCE,VBUS CDECUSB On voltage at the USB regulator output (DECUSB pin) Maximum source resistance on VBUS, including cable Decoupling capacitor on the DECUSB pin 4452_021 v1.3 79 Power and clock management 5.3.8.7 VBUS detection specifications Symbol Description VBUS,DETECT VBUS,REMOVE Voltage at which rising VBUS gets reported by USBDETECTED Voltage at which decreasing VBUS gets reported by USBREMOVED Min. Typ. Max. Units 3.4 3.0 4.0 3.6 4.3 3.9 V V 5.4 CLOCK Clock control The clock control system can source the system clocks from a range of internal or external high and low frequency oscillators and distribute them to modules based upon a modules individual requirements. Clock distribution is automated and grouped independently by module to limit current consumption in unused branches of the clock tree. Listed here are the main features for CLOCK:

64 MHz on-chip oscillator 64 MHz crystal oscillator, using external 32 MHz crystal 32.768 kHz +/-500 ppm RC oscillator 32.768 kHz crystal oscillator, using external 32.768 kHz crystal 32.768 kHz oscillator synthesized from 64 MHz oscillator Firmware (FW) override control of crystal oscillator activity for low latency start up Automatic internal oscillator and clock control, and distribution for ultra-low power HFCLKSTART HFCLKSTOP LFCLKSTART LFCLKSTOP CLOCK HFINT Internal oscillator 32 MHz HFXO Crystal oscillator XC1 XC2 XL1 XL2 PCLK1M PCLK16M PCLK32M HCLK64M HFCLK Clock control CAL LFRC RC oscillator SYNT 32.768 kHz LFXO Crystal oscillator LFCLK Clock control PCLK32KI HFCLKSTARTED LFCLKSTARTED Figure 20: Clock control 5.4.1 HFCLK controller The HFCLK controller provides several clock signals in the system. These are as follows:

4452_021 v1.3 80 Power and clock management HCLK64M: 64 MHz CPU clock PCLK1M: 1 MHz peripheral clock PCLK16M: 16 MHz peripheral clock PCLK32M: 32 MHz peripheral clock 64 MHz internal oscillator (HFINT) 64 MHz crystal oscillator (HFXO) For illustration, see Clock control on page 80. The HFCLK controller uses the following high frequency clock (HFCLK) sources:

The HFCLK controller will automatically provide the clock(s) requested by the system. If the system does not request any clocks from the HFCLK controller, the controller will enter a power saving mode. The HFINT source will be used when HFCLK is requested and HFXO has not been started. The HFXO is started by triggering the HFCLKSTART task and stopped by triggering the HFCLKSTOP task. When the HFCLKSTART task is triggered, the HFCLKSTARTED event is generated once the HFXO startup time has elapsed. The HFXO startup time is given as the sum of the following:

HFXO power-up time, as specified in 64 MHz crystal oscillator (HFXO) on page 93. HFXO debounce time, as specified in register HFXODEBOUNCE on page 92. The HFXO must be running to use the RADIO or the calibration mechanism associated with the 32.768 kHz RC oscillator. 5.4.1.1 64 MHz crystal oscillator (HFXO) The 64 MHz crystal oscillator (HFXO) is controlled by a 32 MHz external crystal. The crystal oscillator is designed for use with an AT-cut quartz crystal in parallel resonant mode. To achieve correct oscillation frequency, the load capacitance must match the specification in the crystal data sheet. Circuit diagram of the 64 MHz crystal oscillator on page 81 shows how the 32 MHz crystal is connected to the 64 MHz crystal oscillator. XC1 C1 32 MHz crystal XC2 C2 Figure 21: Circuit diagram of the 64 MHz crystal oscillator The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by:

4452_021 v1.3 81 Power and clock management C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. For more information, see Reference circuitry on page 567. Cpcb1 and Cpcb2 are stray capacitances on the PCB. Cpin is the pin input capacitance on the XC1 and XC2 pins. See table 64 MHz crystal oscillator (HFXO) on page 93. The load capacitors C1 and C2 should have the same value. For reliable operation, the crystal load capacitance, shunt capacitance, equivalent series resistance, and drive level must comply with the specifications in table 64 MHz crystal oscillator (HFXO) on page 93. It is recommended to use a crystal with lower than maximum load capacitance and/or shunt capacitance. A low load capacitance will reduce both start up time and current consumption. 5.4.2 LFCLK controller The system supports several low frequency clock sources. As illustrated in Clock control on page 80, the system supports the following low frequency clock sources:

32.768 kHz RC oscillator (LFRC) 32.768 kHz crystal oscillator (LFXO) 32.768 kHz synthesized from HFCLK (LFSYNT) The LFCLK controller and all of the LFCLK clock sources are always switched off when in System OFF mode. The LFCLK clock is started by first selecting the preferred clock source in register LFCLKSRC on page 91 and then triggering the LFCLKSTART task. If the LFXO is selected as the clock source, the LFCLK will initially start running from the 32.768 kHz LFRC while the LFXO is starting up and automatically switch to using the LFXO once this oscillator is running. The LFCLKSTARTED event will be generated when the LFXO has been started. The register LFXODEBOUNCE on page 92 is used to configure the LFXO debounce time. The register must be modified if operating in the Extended Operating Conditions temperature range, see Recommended operating conditions on page 608. The LFXO start up time will be increased as a result. The LFCLK clock is stopped by triggering the LFCLKSTOP task. Register LFCLKSRC on page 91 controls the clock source, and its allowed swing. The truth table for various situations is as follows:

4452_021 v1.3 82 Power and clock management SRC EXTERNAL BYPASS Comment 0 0 0 1 1 1 1 2 2 2 0 0 1 0 1 1 0 0 0 1 0 1 X 0 0 1 1 0 1 X Normal operation, LFRC is source DO NOT USE DO NOT USE Normal XTAL operation Normal operation, LFSYNT is source DO NOT USE DO NOT USE DO NOT USE Apply external low swing signal to XL1, ground XL2 Apply external full swing signal to XL1, leave XL2 grounded or unconnected Table 18: LFCLKSRC configuration depending on clock source It is not allowed to write to register LFCLKSRC on page 91 when the LFCLK is running. A LFCLKSTOP task will stop the LFCLK oscillator. However, the LFCLKSTOP task can only be triggered after the STATE field in register LFCLKSTAT on page 91 indicates LFCLK running state. The synthesized 32.768 kHz clock depends on the HFCLK to run. If high accuracy is required for the LFCLK running off the synthesized 32.768 kHz clock, the HFCLK must running from the HFXO source. 5.4.2.1 32.768 kHz RC oscillator (LFRC) The default source of the low frequency clock (LFCLK) is the 32.768 kHz RC oscillator (LFRC). The LFRC oscillator does not require additional external components. The LFRC frequency will be affected by variation in temperature. The LFRC oscillator can be calibrated to improve accuracy by using the HFXO as a reference oscillator during calibration. 5.4.2.2 Calibrating the 32.768 kHz RC oscillator After the LFRC oscillator is started and running, it can be calibrated by triggering the CAL task. The LFRC oscillator will then temporarily request the HFCLK to be used as a reference for the calibration. A DONE event will be generated when calibration has finished. The HFCLK crystal oscillator has to be started

(by triggering the HFCLKSTART task) in order for the calibration mechanism to work. It is not allowed to stop the LFRC during an ongoing calibration. 5.4.2.3 Calibration timer The calibration timer can be used to time the calibration interval of the 32.768 kHz RC oscillator. The calibration timer is started by triggering the CTSTART task and stopped by triggering the CTSTOP task. The calibration timer will always start counting down from the value specified in CTIV ( Retained ) on page 93 and generate a CTTO event when it reaches 0. The calibration timer will automatically stop when it reaches 0. CTSTART CTSTARTED CTSTOP CTSTOPPED CTTO Calibration timer CTIV Figure 22: Calibration timer After a CTSTART task has been triggered, the calibration timer will ignore further tasks until it has returned the CTSTARTED event. Likewise, after a CTSTOP task has been triggered, the calibration timer will ignore further tasks until it has returned a CTSTOPPED event. Triggering CTSTART while the calibration timer 4452_021 v1.3 83 Power and clock management is running will immediately return a CTSTARTED event. Triggering CTSTOP when the calibration timer is stopped will immediately return a CTSTOPPED event. 5.4.2.4 32.768 kHz crystal oscillator (LFXO) For higher LFCLK accuracy (when better than +/- 500 ppm accuracy is required), the low frequency crystal oscillator (LFXO) must be used. The following external clock sources are supported:

Low swing clock signal applied to the XL1 pin. The XL2 pin shall then be grounded. Rail-to-rail clock signal applied to the XL1 pin. The XL2 pin shall then be grounded or left unconnected. To achieve correct oscillation frequency, the load capacitance must match the specification in the crystal data sheet. Circuit diagram of the 32.768 kHz crystal oscillator on page 84 shows the LFXO circuitry. XL1 C1 32.768 kHz crystal XL2 C2 Figure 23: Circuit diagram of the 32.768 kHz crystal oscillator The load capacitance (CL) is the total capacitance seen by the crystal across its terminals and is given by:

C1 and C2 are ceramic SMD capacitors connected between each crystal terminal and ground. Cpcb1 and Cpcb2 are stray capacitances on the PCB. Cpin is the pin input capacitance on the XC1 and XC2 pins (see Low frequency crystal oscillator (LFXO) on page 94). The load capacitors C1 and C2 should have the same value. For more information, see Reference circuitry on page 567. 5.4.2.5 32.768 kHz synthesized from HFCLK (LFSYNT) LFCLK can also be synthesized from the HFCLK clock source. The accuracy of LFCLK will then be the accuracy of the HFCLK. Using the LFSYNT clock avoids the requirement for a 32.768 kHz crystal, but increases average power consumption as the HFCLK will need to be requested in the system. 4452_021 v1.3 84 Power and clock management 5.4.3 Registers Base address Peripheral 0x40000000 CLOCK Instance CLOCK Description Clock control Configuration Table 19: Instances Register Offset Description Start HFXO crystal oscillator Stop HFXO crystal oscillator Start LFCLK Stop LFCLK Start calibration of LFRC Start calibration timer Stop calibration timer HFXO crystal oscillator started LFCLK started Calibration of LFRC completed Calibration timer timeout TASKS_HFCLKSTART TASKS_HFCLKSTOP TASKS_LFCLKSTART TASKS_LFCLKSTOP TASKS_CAL TASKS_CTSTART TASKS_CTSTOP EVENTS_HFCLKSTARTED EVENTS_LFCLKSTARTED EVENTS_DONE EVENTS_CTTO EVENTS_CTSTARTED EVENTS_CTSTOPPED INTENSET INTENCLR HFCLKRUN HFCLKSTAT LFCLKRUN LFCLKSTAT LFCLKSRCCOPY LFCLKSRC HFXODEBOUNCE LFXODEBOUNCE CTIV TRACECONFIG 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x100 0x104 0x10C 0x110 0x128 0x12C 0x304 0x308 0x408 0x40C 0x414 0x418 0x41C 0x518 0x528 0x52C 0x538 0x55C 5.4.3.1 TASKS_HFCLKSTART Address offset: 0x000 Start HFXO crystal oscillator Calibration timer has been started and is ready to process new tasks Calibration timer has been stopped and is ready to process new tasks Enable interrupt Disable interrupt HFCLK status LFCLK status Status indicating that HFCLKSTART task has been triggered Status indicating that LFCLKSTART task has been triggered Copy of LFCLKSRC register, set when LFCLKSTART task was triggered Clock source for the LFCLK HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. LFXO debounce time. The LFXO is started by triggering the TASKS_LFCLKSTART task when the LFCLKSRC register is configured for Xtal. Calibration timer interval Clocking options for the trace port debug interface Table 20: Register overview Retained Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_HFCLKSTART Start HFXO crystal oscillator Trigger 1 Trigger task ID ID A 5.4.3.2 TASKS_HFCLKSTOP Address offset: 0x004 4452_021 v1.3 85 Power and clock management Stop HFXO crystal oscillator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_HFCLKSTOP Stop HFXO crystal oscillator Trigger 1 Trigger task ID ID A ID ID A ID ID A ID ID A 5.4.3.3 TASKS_LFCLKSTART Address offset: 0x008 Start LFCLK 5.4.3.4 TASKS_LFCLKSTOP Address offset: 0x00C Stop LFCLK 5.4.3.5 TASKS_CAL Address offset: 0x010 Start calibration of LFRC 5.4.3.6 TASKS_CTSTART Address offset: 0x014 Start calibration timer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value W TASKS_LFCLKSTART Trigger 1 Description Start LFCLK Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value W TASKS_LFCLKSTOP Trigger 1 Description Stop LFCLK Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_CAL Start calibration of LFRC Trigger 1 Trigger task A A A A 4452_021 v1.3 86 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_CTSTART Start calibration timer Trigger 1 Trigger task 5.4.3.7 TASKS_CTSTOP Address offset: 0x018 Stop calibration timer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_CTSTOP Stop calibration timer Trigger 1 Trigger task 5.4.3.8 EVENTS_HFCLKSTARTED Address offset: 0x100 HFXO crystal oscillator started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_HFCLKSTARTED HFXO crystal oscillator started NotGenerated Generated Event not generated Event generated 5.4.3.9 EVENTS_LFCLKSTARTED Address offset: 0x104 LFCLK started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value RW EVENTS_LFCLKSTARTED NotGenerated Generated Description LFCLK started Event not generated Event generated 0 1 0 1 ID ID A ID ID A ID ID A ID ID A A A A A 5.4.3.10 EVENTS_DONE Address offset: 0x10C Calibration of LFRC completed 4452_021 v1.3 87 ID ID A ID ID A ID ID A ID ID A Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_DONE NotGenerated Generated Calibration of LFRC completed Event not generated Event generated 5.4.3.11 EVENTS_CTTO Address offset: 0x110 Calibration timer timeout Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CTTO NotGenerated Generated Calibration timer timeout Event not generated Event generated 5.4.3.12 EVENTS_CTSTARTED Address offset: 0x128 Calibration timer has been started and is ready to process new tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CTSTARTED Calibration timer has been started and is ready to process NotGenerated Generated new tasks Event not generated Event generated 5.4.3.13 EVENTS_CTSTOPPED Address offset: 0x12C Calibration timer has been stopped and is ready to process new tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CTSTOPPED Calibration timer has been stopped and is ready to process NotGenerated Generated new tasks Event not generated Event generated 5.4.3.14 INTENSET Address offset: 0x304 4452_021 v1.3 88 A A A A 0 1 0 1 0 1 0 1 ID ID A ID ID A Power and clock management Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW HFCLKSTARTED Write '1' to enable interrupt for event HFCLKSTARTED B RW LFCLKSTARTED Write '1' to enable interrupt for event LFCLKSTARTED C RW DONE Write '1' to enable interrupt for event DONE D RW CTTO Write '1' to enable interrupt for event CTTO E RW CTSTARTED Write '1' to enable interrupt for event CTSTARTED F RW CTSTOPPED Write '1' to enable interrupt for event CTSTOPPED 5.4.3.15 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW HFCLKSTARTED Write '1' to disable interrupt for event HFCLKSTARTED B RW LFCLKSTARTED Write '1' to disable interrupt for event LFCLKSTARTED C RW DONE Write '1' to disable interrupt for event DONE D RW CTTO 4452_021 v1.3 Write '1' to disable interrupt for event CTTO 89 Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Power and clock management Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value E RW CTSTARTED Write '1' to disable interrupt for event CTSTARTED F RW CTSTOPPED Write '1' to disable interrupt for event CTSTOPPED Value ID Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Description Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled 5.4.3.16 HFCLKRUN Address offset: 0x408 Status indicating that HFCLKSTART task has been triggered 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotTriggered Triggered HFCLKSTART task triggered or not Task not triggered Task triggered A A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RC Xtal NotRunning Running Source of HFCLK 64 MHz internal oscillator (HFINT) 64 MHz crystal oscillator (HFXO) HFCLK state HFCLK not running HFCLK running 5.4.3.17 HFCLKSTAT Address offset: 0x40C Bit number ID ID A Reset 0x00000000 AccessField R STATUS HFCLK status Bit number ID ID A Reset 0x00000000 AccessField R SRC B R STATE 5.4.3.18 LFCLKRUN Address offset: 0x414 Status indicating that LFCLKSTART task has been triggered 4452_021 v1.3 90 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 Power and clock management 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotTriggered Triggered LFCLKSTART task triggered or not Task not triggered Task triggered 5.4.3.19 LFCLKSTAT Address offset: 0x418 Bit number ID ID A Reset 0x00000000 AccessField R STATUS LFCLK status Bit number ID ID A Reset 0x00000000 AccessField R SRC B R STATE Bit number ID ID A Reset 0x00000000 AccessField R SRC 5.4.3.21 LFCLKSRC Address offset: 0x518 Clock source for the LFCLK 0 1 0 1 2 0 1 0 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RC Xtal Synth NotRunning Running Source of LFCLK 32.768 kHz RC oscillator (LFRC) 32.768 kHz crystal oscillator (LFXO) 32.768 kHz synthesized from HFCLK (LFSYNT) LFCLK state LFCLK not running LFCLK running 5.4.3.20 LFCLKSRCCOPY Address offset: 0x41C Copy of LFCLKSRC register, set when LFCLKSTART task was triggered 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clock source RC Xtal Synth 32.768 kHz RC oscillator (LFRC) 32.768 kHz crystal oscillator (LFXO) 32.768 kHz synthesized from HFCLK (LFSYNT) 4452_021 v1.3 91 Bit number ID ID A Reset 0x00000000 AccessField RW SRC B RW BYPASS C RW EXTERNAL Power and clock management 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value RC Xtal Synth Disabled Enabled Disabled Enabled 0 1 2 0 1 0 1 Description Clock source 32.768 kHz RC oscillator (LFRC) 32.768 kHz crystal oscillator (LFXO) 32.768 kHz synthesized from HFCLK (LFSYNT) Enable or disable bypass of LFCLK crystal oscillator with external clock source Disable (use with Xtal or low-swing external source) Enable (use with rail-to-rail external source) Enable or disable external source for LFCLK Disable external source (use with Xtal) Enable use of external source instead of Xtal (SRC needs to be set to Xtal) 5.4.3.22 HFXODEBOUNCE Address offset: 0x528 HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. The EVENTS_HFCLKSTARTED event is generated after the HFXO power up time + the HFXO debounce time has elapsed. It is not allowed to change the value of this register while the HFXO is starting. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A Reset 0x00000010 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 AccessField Value ID Value Description RW HFXODEBOUNCE 0x01..0xFF HFXO debounce time. Debounce time = HFXODEBOUNCE *

Db256us Db1024us 0x10 0x40 16 s. crystals and larger. 256 s debounce time. Recommended for 1.6 mm x 2.0 mm 1024 s debounce time. Recommended for 1.6 mm x 1.2 mm crystals and smaller. 5.4.3.23 LFXODEBOUNCE Address offset: 0x52C LFXO debounce time. The LFXO is started by triggering the TASKS_LFCLKSTART task when the LFCLKSRC register is configured for Xtal. The EVENTS_LFCLKSTARTED event is generated after the LFXO debounce time has elapsed. It is not allowed to change the value of this register while the LFXO is starting. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW LFXODEBOUNCE LFXO debounce time. Normal Extended 0 1 8192 32.768 kHz periods, or 0.25 s. Recommended for normal Operating Temperature conditions. 16384 32.768 kHz periods, or 0.5 s. Recommended for Extended Operating Temperature conditions. 4452_021 v1.3 92 ID ID A ID ID A Power and clock management 5.4.3.24 CTIV ( Retained ) Address offset: 0x538 This register is a retained register Calibration timer interval Bit number ID ID A Reset 0x00000000 AccessField RW CTIV 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. 5.4.3.25 TRACECONFIG Address offset: 0x55C Clocking options for the trace port debug interface This register is a retained register. Reset behavior is the same as debug components. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B B A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW TRACEPORTSPEED Speed of trace port clock. Note that the TRACECLK pin will ID ID A B RW TRACEMUX Pin multiplexing of trace signals. See pin assignment chapter 32MHz 16MHz 8MHz 4MHz GPIO Serial Parallel 0 1 2 3 0 1 2 output this clock divided by two. 32 MHz trace port clock (TRACECLK = 16 MHz) 16 MHz trace port clock (TRACECLK = 8 MHz) 8 MHz trace port clock (TRACECLK = 4 MHz) 4 MHz trace port clock (TRACECLK = 2 MHz) No trace signals routed to pins. All pins can be used as SWO trace signal routed to pin. Remaining pins can be used All trace signals (TRACECLK and TRACEDATA[n]) routed to for more details. regular GPIOs. as regular GPIOs. pins. 5.4.4 Electrical specification 5.4.4.1 64 MHz internal oscillator (HFINT) Symbol fNOM_HFINT fTOL_HFINT Description Nominal output frequency Frequency tolerance fTOL_HFINT,EXT Frequency tolerance, extended temperature range 5.4.4.2 64 MHz crystal oscillator (HFXO) 4452_021 v1.3 93 Min. Typ. Max. Units 64 1.5 8 9 MHz

ISTBY_X32M_X1 Typical parameters for a given 1.6mm x 1.2mm crystal:

110 A Symbol fNOM_HFXO fXTAL_HFXO fTOL_HFXO Description Nominal output frequency External crystal frequency radio applications Frequency tolerance requirement for 2.4 GHz proprietary fTOL_HFXO_BLE Frequency tolerance requirement, Bluetooth low energy applications, packet length 200 bytes fTOL_HFXO_BLE_LP Frequency tolerance requirement, Bluetooth low energy CL_HFXO C0_HFXO RS_HFXO_7PF RS_HFXO_3PF PD_HFXO CPIN_HFXO ISTBY_X32M applications, packet length > 200 bytes Load capacitance Shunt capacitance Equivalent series resistance 3 pF < C0 7 pF Equivalent series resistance C0 3 pF Drive level Input capacitance XC1 and XC2 Core standby current for various crystals ISTBY_X32M_X0 Typical parameters for a given 2.5mm x 2.0mm crystal:

CL_HFXO = 8 pF, C0_HFXO = 1 pF, LM_HFXO = 7 mH, RS_HFXO = 20 CL_HFXO = 8 pF, C0_HFXO = 0.4 pF, LM_HFXO = 20 mH, RS_HFXO = 40 ISTART_X32M Average startup current for various crystals, first 1 ms ISTART_X32M_X0 Typical parameters for a given 2.5mm x 2.0mm crystal:

CL_HFXO = 8 pF, C0_HFXO = 1 pF, LM_HFXO = 7 mH, RS_HFXO = 20 ISTART_X32M_X1 Typical parameters for a given 1.6mm x 1.2mm crystal:

CL_HFXO = 8 pF, C0_HFXO = 0.4 pF, LM_HFXO = 20 mH, RS_HFXO = 40 tPOWERUP_X32M Power-up time for various crystals tPOWERUP_X32M_X0 Typical parameters for a given 2.5mm x 2.0mm crystal:

CL_HFXO = 8 pF, C0_HFXO = 1 pF, LM_HFXO = 7 mH, RS_HFXO = 20 tPOWERUP_X32M_X1 Typical parameters for a given 1.6mm x 1.2mm crystal:

CL_HFXO = 8 pF, C0_HFXO = 0.4 pF, LM_HFXO = 20 mH, RS_HFXO = 40 5.4.4.3 Low frequency crystal oscillator (LFXO) Description Crystal frequency Frequency tolerance requirement for BLE stack Frequency tolerance requirement for ANT stack Load capacitance Shunt capacitance Equivalent series resistance Drive level Symbol fNOM_LFXO fTOL_LFXO_BLE fTOL_LFXO_ANT CL_LFXO C0_LFXO RS_LFXO PD_LFXO Cpin ILFXO Input capacitance on XL1 and XL2 pads Run current for 32.768 kHz crystal oscillator tSTART_LFXO Startup time for 32.768 kHz crystal oscillator 4452_021 v1.3 94 Power and clock management Min. Typ. Max. Units 64 32 3 65 360 785 60 200 4 0.23 0.25 40 ppm 30 ppm 60 12 7 60 100 100 MHz MHz ppm pF pF W pF A A A s s kHz ppm ppm pF pF k W pF A s Min. Typ. Max. Units 32.768 500 50 12.5 2 100 0.5 Symbol Description tSTART_LFXO_EXT Startup time for 32.768 kHz crystal oscillator when CLOCK.LFXODEBOUNCE configured for Extended debounce time 5.4.4.4 Low frequency RC oscillator (LFRC) Power and clock management Min. Max. Units Typ. 0.5 s Symbol fNOM_LFRC fTOL_LFRC ILFRC tSTART_LFRC Description Nominal frequency Frequency tolerance, uncalibrated Run current Startup time fTOL_CAL_LFRC Frequency tolerance after calibration12 Min. Typ. Max. Units 32.768 0.7 1000 5 500 ppm kHz

A s 5.4.4.5 Synthesized low frequency clock (LFSYNT) Symbol Description fNOM_LFSYNT Nominal frequency Min. Typ. Max. Units 32.768 kHz 12 Constant temperature within 0.5 C, calibration performed at least every 8 seconds, averaging interval > 7.5 ms, defined as 3 sigma 4452_021 v1.3 95 6 Peripherals 6.1 Peripheral interface Peripherals are controlled by the CPU by writing to configuration registers and task registers. Peripheral events are indicated to the CPU by event registers and interrupts if they are configured for a given event. Peripheral Task signal from PPI TASK write k SHORTS OR task Peripheral core event INTEN m EVENT m IRQ signal to NVIC Event signal to PPI Figure 24: Tasks, events, shortcuts, and interrupts 6.1.1 Peripheral ID Every peripheral is assigned a fixed block of 0x1000 bytes of address space, which is equal to 1024 x 32 bit registers. See Instantiation on page 22 for more information about which peripherals are available and where they are located in the address map. There is a direct relationship between peripheral ID and base address. For example, a peripheral with base address 0x40000000 is assigned ID=0, a peripheral with base address 0x40001000 is assigned ID=1, and a peripheral with base address 0x4001F000 is assigned ID=31. Peripherals may share the same ID, which may impose one or more of the following limitations:

Some peripherals share some registers or other common resources. Operation is mutually exclusive. Only one of the peripherals can be used at a time. Switching from one peripheral to another must follow a specific pattern (disable the first, then enable the second peripheral). 4452_021 v1.3 96 Peripherals 6.1.2 Peripherals with shared ID In general (with the exception of ID 0), peripherals sharing an ID and base address may not be used simultaneously. The user can only enable one peripheral at the time on this specific ID. When switching between two peripherals sharing an ID, the user should do the following to prevent unwanted behavior:

1. Disable the previously used peripheral. 2. Remove any programmable peripheral interconnect (PPI) connections set up for the peripheral that is being disabled. 3. Clear all bits in the INTEN register, i.e. INTENCLR = 0xFFFFFFFF. 4. Explicitly configure the peripheral that you are about to enable and do not rely on configuration values that may be inherited from the peripheral that was disabled. 5. Enable the now configured peripheral. See which peripherals are sharing ID in Instantiation on page 22. 6.1.3 Peripheral registers Most peripherals feature an ENABLE register. Unless otherwise specified in the relevant chapter, the peripheral registers (in particular the PSEL registers) must be configured before enabling the peripheral. The peripheral must be enabled before tasks and events can be used. 6.1.4 Bit set and clear Registers with multiple single-bit bit fields may implement the set-and-clear pattern. This pattern enables firmware to set and clear individual bits in a register without having to perform a read-modify-write operation on the main register. This pattern is implemented using three consecutive addresses in the register map, where the main register is followed by dedicated SET and CLR registers (in that exact order). The SET register is used to set individual bits in the main register while the CLR register is used to clear individual bits in the main register. Writing 1 to a bit in SET or CLR register will set or clear the same bit in the main register respectively. Writing 0 to a bit in SET or CLR register has no effect. Reading the SET or CLR register returns the value of the main register. Note: The main register may not be visible and hence not directly accessible in all cases. 6.1.5 Tasks Tasks are used to trigger actions in a peripheral, for example to start a particular behavior. A peripheral can implement multiple tasks with each task having a separate register in that peripheral's task register group. A task is triggered when firmware writes 1 to the task register, or when the peripheral itself or another peripheral toggles the corresponding task signal. See Tasks, events, shortcuts, and interrupts on page 96. 6.1.6 Events Events are used to notify peripherals and the CPU about events that have happened, for example a state change in a peripheral. A peripheral may generate multiple events with each event having a separate register in that peripherals event register group. An event is generated when the peripheral itself toggles the corresponding event signal, and the event register is updated to reflect that the event has been generated. See Tasks, events, shortcuts, and interrupts on page 96. An event register is only cleared when firmware writes 0 to it. 4452_021 v1.3 97 Peripherals Events can be generated by the peripheral even when the event register is set to 1. 6.1.7 Shortcuts A shortcut is a direct connection between an event and a task within the same peripheral. If a shortcut is enabled, the associated task is automatically triggered when its associated event is generated. Using a shortcut is the equivalent to making the same connection outside the peripheral and through the PPI. However, the propagation delay through the shortcut is usually shorter than the propagation delay through the PPI. Shortcuts are predefined, which means their connections cannot be configured by firmware. Each shortcut can be individually enabled or disabled through the shortcut register, one bit per shortcut, giving a maximum of 32 shortcuts for each peripheral. 6.1.8 Interrupts All peripherals support interrupts. Interrupts are generated by events. A peripheral only occupies one interrupt, and the interrupt number follows the peripheral ID. For example, the peripheral with ID=4 is connected to interrupt number 4 in the nested vectored interrupt controller

(NVIC). Using the INTEN, INTENSET, and INTENCLR registers, every event generated by a peripheral can be configured to generate that peripheral's interrupt. Multiple events can be enabled to generate interrupts simultaneously. To resolve the correct interrupt source, the event registers in the event group of peripheral registers will indicate the source. Some peripherals implement only INTENSET and INTENCLR registers, and the INTEN register is not available on those peripherals. See the individual peripheral chapters for details. In all cases, reading back the INTENSET or INTENCLR register returns the same information as in INTEN. Each event implemented in the peripheral is associated with a specific bit position in the INTEN, INTENSET, and INTENCLR registers. The relationship between tasks, events, shortcuts, and interrupts is shown in Tasks, events, shortcuts, and interrupts on page 96. Interrupt clearing Clearing an interrupt by writing 0 to an event register, or disabling an interrupt using the INTENCLR register, can take up to four CPU clock cycles to take effect. This means that an interrupt may reoccur immediately, even if a new event has not come, if the program exits an interrupt handler after the interrupt is cleared or disabled but before four clock cycles have passed. Note: To avoid an interrupt reoccurring before a new event has come, the program should perform a read from one of the peripheral registers. For example, the event register that has been cleared, or the INTENCLR register that has been used to disable the interrupt. This will cause a one to three-

cycle delay and ensure the interrupt is cleared before exiting the interrupt handler. Care should be taken to ensure the compiler does not remove the read operation as an optimization. If the program can guarantee a four-cycle delay after an event is cleared or an interrupt is disabled, then a read of a register is not required. 4452_021 v1.3 98 Peripherals 6.2 AAR Accelerated address resolver Accelerated address resolver is a cryptographic support function for implementing the Resolvable Private Address Resolution Procedure described in the Bluetooth Core specification v4.0. Resolvable Private Address generation should be achieved using ECB and is not supported by AAR. The procedure allows two devices that share a secret key to generate and resolve a hash based on their device address. The AAR block enables real-time address resolution on incoming packets when configured as described in this chapter. This allows real-time packet filtering (whitelisting) using a list of known shared keys (Identity Resolving Keys (IRK) in Bluetooth). 6.2.1 EasyDMA The AAR implements EasyDMA for reading and writing to the RAM. The EasyDMA will have finished accessing the RAM when the END, RESOLVED, and NOTRESOLVED events are generated. If the IRKPTR on page 104, ADDRPTR on page 104, and the SCRATCHPTR on page 104 is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. 6.2.2 Resolving a resolvable address As per Bluetooth specification, a private resolvable address is composed of six bytes. LSB MSB random 1 0 hash

(24-bit) prand

(24-bit) Figure 25: Resolvable address To resolve an address the register ADDRPTR on page 104 must point to the start of the packet. The resolver is started by triggering the START task. A RESOLVED event is generated when the AAR manages to resolve the address using one of the Identity Resolving Keys (IRK) found in the IRK data structure. The AAR will use the IRK specified in the register IRK0 to IRK15 starting from IRK0. The register NIRK on page 103 specifies how many IRKs should be used. The AAR module will generate a NOTRESOLVED event if it is not able to resolve the address using the specified list of IRKs. The AAR will go through the list of available IRKs in the IRK data structure and for each IRK try to resolve the address according to the Resolvable Private Address Resolution Procedure described in the Bluetooth Core specification v4.0 [Vol 3] chapter 10.8.2.3. The time it takes to resolve an address varies due to the location in the list of the resolvable address. The resolution time will also be affected by RAM accesses performed by other peripherals and the CPU. See the Electrical specifications for more information about resolution time. The AAR only compares the received address to those programmed in the module without checking the address type. The AAR will stop as soon as it has managed to resolve the address, or after trying to resolve the address using NIRK number of IRKs from the IRK data structure. The AAR will generate an END event after it has stopped. 4452_021 v1.3 99 Peripherals ADDR: resolvable address ADDRPTR START RESOLVED AAR S0 L S1 ADDR SCRATCHPTR Scratch area IRK data structure IRKPTR Figure 26: Address resolution with packet preloaded into RAM 6.2.3 Use case example for chaining RADIO packet reception with address resolution using AAR The AAR may be started as soon as the 6 bytes required by the AAR have been received by the RADIO and stored in RAM. The ADDRPTR pointer must point to the start of packet. SCRATCHPTR PACKETPTR ADDRPTR START RESOLVED AAR S0 L S1 ADDR S0: S0 field of RADIO (optional) L: Length field of RADIO (optional) S1: S1 field of RADIO (optional) ADDR: resolvable address Scratch area IRK data structure IRKPTR From remote transmitter RXEN RADIO Figure 27: Address resolution with packet loaded into RAM by the RADIO 6.2.4 IRK data structure The IRK data structure is located in RAM at the memory location specified by the IRKPTR register. Property Address offset Description IRK0 IRK1

.. IRK15 0 16

.. 240 IRK number 0 (16 bytes) IRK number 1 (16 bytes)

.. IRK number 15 (16 bytes) Table 21: IRK data structure overview 6.2.5 Registers Base address Peripheral Instance Description Configuration 0x4000F000 AAR AAR Accelerated address resolver Table 22: Instances Register TASKS_START TASKS_STOP EVENTS_END Offset 0x000 0x008 0x100 Description Start resolving addresses based on IRKs specified in the IRK data structure Stop resolving addresses Address resolution procedure complete 4452_021 v1.3 100 Peripherals EVENTS_NOTRESOLVED Address not resolved Description Address resolved Enable interrupt Disable interrupt Resolution status Enable AAR Number of IRKs Register EVENTS_RESOLVED INTENSET INTENCLR STATUS ENABLE NIRK IRKPTR ADDRPTR SCRATCHPTR Offset 0x104 0x108 0x304 0x308 0x400 0x500 0x504 0x508 0x510 0x514 6.2.5.1 TASKS_START Address offset: 0x000 Pointer to IRK data structure Pointer to the resolvable address Pointer to data area used for temporary storage Table 23: Register overview Start resolving addresses based on IRKs specified in the IRK data structure ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_START Start resolving addresses based on IRKs specified in the IRK Trigger 1 data structure Trigger task 6.2.5.2 TASKS_STOP Address offset: 0x008 Stop resolving addresses Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Stop resolving addresses Trigger 1 Trigger task 6.2.5.3 EVENTS_END Address offset: 0x100 Address resolution procedure complete Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_END Address resolution procedure complete NotGenerated Generated 0 1 Event not generated Event generated 4452_021 v1.3 101 A A A Peripherals A A 6.2.5.4 EVENTS_RESOLVED Address offset: 0x104 Address resolved ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RESOLVED NotGenerated Generated Address resolved Event not generated Event generated 6.2.5.5 EVENTS_NOTRESOLVED Address offset: 0x108 Address not resolved Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_NOTRESOLVED NotGenerated Generated Address not resolved Event not generated Event generated 6.2.5.6 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW END Value ID Value Description Write '1' to enable interrupt for event END 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C B A B RW RESOLVED Write '1' to enable interrupt for event RESOLVED C RW NOTRESOLVED Write '1' to enable interrupt for event NOTRESOLVED Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled 0 1 0 1 1 0 1 1 0 1 1 0 1 6.2.5.7 INTENCLR Address offset: 0x308 Disable interrupt 4452_021 v1.3 102 Bit number ID ID A Reset 0x00000000 AccessField RW END 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event END Peripherals C B A B RW RESOLVED Write '1' to disable interrupt for event RESOLVED C RW NOTRESOLVED Write '1' to disable interrupt for event NOTRESOLVED Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 1 0 1 Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Description Value

[0..15]

The IRK that was used last time an address was resolved A A A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A Value ID Value Description Disabled Enabled 0 3 Enable or disable AAR Disable Enable 6.2.5.8 STATUS Address offset: 0x400 Resolution status Reset 0x00000000 AccessField R STATUS 6.2.5.9 ENABLE Address offset: 0x500 Enable AAR Reset 0x00000000 AccessField RW ENABLE 6.2.5.10 NIRK Address offset: 0x504 Number of IRKs ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000001 AccessField RW NIRK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A A A A A Value ID Value

[1..16]

Description structure Number of Identity root keys available in the IRK data 4452_021 v1.3 103 Peripherals 6.2.5.11 IRKPTR Address offset: 0x508 Pointer to IRK data structure 6.2.5.12 ADDRPTR Address offset: 0x510 Pointer to the resolvable address ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW IRKPTR Value ID Value Description Pointer to the IRK data structure A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pointer to the resolvable address (6-bytes) Reset 0x00000000 AccessField RW ADDRPTR 6.2.5.13 SCRATCHPTR Address offset: 0x514 Pointer to data area used for temporary storage Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW SCRATCHPTR Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. 6.2.6 Electrical specification 6.2.6.1 AAR Electrical Specification Symbol tAAR Description Address resolution time per IRK. Total time for several IRKs is given as (1 s + n * t_AAR), where n is the number of IRKs.

(Given priority to the actual destination RAM block). Min. Typ. Max. Units 6 s tAAR,8 Time for address resolution of 8 IRKs. (Given priority to the 49 s actual destination RAM block). 6.3 ACL Access control lists The Access control lists (ACL) peripheral is designed to assign and enforce access permissions to different regions of the on-chip flash memory map. 4452_021 v1.3 104 Peripherals Flash memory regions can be assigned individual ACL permission schemes. The following registers are involved:

PERM register, where the permissions are configured. ADDR register, where the word-aligned start address for the flash page is defined. SIZE register, where the size of the region the permissions are applied to is determined. Note: The size of the region in bytes is restricted to a multiple of the flash page size, and the maximum region size is limited to half the flash size. See Memory on page 19 for more information. On-chip flash memory

... Page N+1 Page N

... Page 3 Page 2 Page 1 Page 0 Write protect Read/

Write protect l l l l ACL[7].ADDR ACL[7].SIZE ACL[7].PERM ACL[0].ADDR ACL[0].SIZE ACL[0].PERM l 00 1 0 0 0 0 0 000000 0 0 l 00 1 1 0 0 0 0 000000 0 0 0 0 0 0 0 0 0 1 1 1 Figure 28: Protected regions of on-chip flash memory There are four defined ACL permission schemes, with different combinations of read/write permissions:

Read Write Protection description 0 1 0 1 No protection. Entire region can be executed, read, written or erased. Region can be executed and read, but not written or erased. Region can be written and erased, but not executed or read. Region is locked for all access until next reset. Table 24: Permission schemes Note: If a permission violation to a protected region is detected by the ACL peripheral, the request is blocked and a Bus Fault exception is triggered. 4452_021 v1.3 105 31 31 31 31 31 31 0 0 1 1 Peripherals Access control to a configured region is enforced by the hardware two CPU clock cycles after the ADDR, SIZE, and PERM registers for an ACL instance have been successfully written. The protection is only enforced if a valid start address of the flash page boundary is written into the ADDR register, and the values of the SIZE and PERM registers are not zero. The ADDR, SIZE, and PERM registers can only be written once. All ACL configuration registers are cleared on reset (by resetting the device from any reset source), which is also the only way of clearing the configuration registers. To ensure that the desired permission schemes are always enforced by the ACL peripheral, the device boot sequence must perform the necessary configuration. Debugger read access to a read-protected region will be Read-As-Zero (RAZ), while debugger write access to a write-protected region will be Write-Ignored (WI). 6.3.1 Registers Base address Peripheral Instance Description Configuration 0x4001E000 ACL ACL Access control lists Table 25: Instances Offset Description 0x800 0x804 0x808 0x80C 0x810 0x814 0x818 0x81C 0x820 0x824 0x828 0x82C 0x830 0x834 0x838 0x83C 0x840 0x844 0x848 0x84C 0x850 0x854 0x858 0x85C 0x860 0x864 0x868 0x86C 0x870 0x874 0x878 Start address of region to protect. The start address must be word-aligned. Size of region to protect counting from address ACL[0].ADDR. Write '0' as no effect. Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE Start address of region to protect. The start address must be word-aligned. Size of region to protect counting from address ACL[1].ADDR. Write '0' as no effect. Access permissions for region 1 as defined by start address ACL[1].ADDR and size ACL[1].SIZE Start address of region to protect. The start address must be word-aligned. Size of region to protect counting from address ACL[2].ADDR. Write '0' as no effect. Access permissions for region 2 as defined by start address ACL[2].ADDR and size ACL[2].SIZE Start address of region to protect. The start address must be word-aligned. Size of region to protect counting from address ACL[3].ADDR. Write '0' as no effect. Access permissions for region 3 as defined by start address ACL[3].ADDR and size ACL[3].SIZE Start address of region to protect. The start address must be word-aligned. Size of region to protect counting from address ACL[4].ADDR. Write '0' as no effect. Access permissions for region 4 as defined by start address ACL[4].ADDR and size ACL[4].SIZE Start address of region to protect. The start address must be word-aligned. Size of region to protect counting from address ACL[5].ADDR. Write '0' as no effect. Access permissions for region 5 as defined by start address ACL[5].ADDR and size ACL[5].SIZE Start address of region to protect. The start address must be word-aligned. Size of region to protect counting from address ACL[6].ADDR. Write '0' as no effect. Access permissions for region 6 as defined by start address ACL[6].ADDR and size ACL[6].SIZE Start address of region to protect. The start address must be word-aligned. Size of region to protect counting from address ACL[7].ADDR. Write '0' as no effect. Access permissions for region 7 as defined by start address ACL[7].ADDR and size ACL[7].SIZE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register ACL[0].ADDR ACL[0].SIZE ACL[0].PERM ACL[0].UNUSED0 ACL[1].ADDR ACL[1].SIZE ACL[1].PERM ACL[1].UNUSED0 ACL[2].ADDR ACL[2].SIZE ACL[2].PERM ACL[2].UNUSED0 ACL[3].ADDR ACL[3].SIZE ACL[3].PERM ACL[3].UNUSED0 ACL[4].ADDR ACL[4].SIZE ACL[4].PERM ACL[4].UNUSED0 ACL[5].ADDR ACL[5].SIZE ACL[5].PERM ACL[5].UNUSED0 ACL[6].ADDR ACL[6].SIZE ACL[6].PERM ACL[6].UNUSED0 ACL[7].ADDR ACL[7].SIZE ACL[7].PERM 4452_021 v1.3 106 Peripherals Reserved Register ACL[7].UNUSED0 Offset 0x87C Description 6.3.1.1 ACL[n].ADDR (n=0..7) Address offset: 0x800 + (n 0x10) Table 26: Register overview Start address of region to protect. The start address must be word-aligned. This register can only be written once. Bit number ID ID A Reset 0x00000000 AccessField RW1 ADDR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Start address of flash region n. The start address must point to a flash page boundary. 6.3.1.2 ACL[n].SIZE (n=0..7) Address offset: 0x804 + (n 0x10) This register can only be written once. Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. Bit number ID ID A Reset 0x00000000 AccessField RW1 SIZE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Size of flash region n in bytes. Must be a multiple of the flash page size. 6.3.1.3 ACL[n].PERM (n=0..7) Address offset: 0x808 + (n 0x10) This register can only be written once. Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE Bit number ID ID B Reset 0x00000000 AccessField RW1 WRITE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description C RW1 READ Configure read permissions for region n. Write '0' has no Enable Disable Enable Disable 0 1 0 1 Configure write and erase permissions for region n. Write '0'

has no effect. Allow write and erase instructions to region n Block write and erase instructions to region n effect. Allow read instructions to region n Block read instructions to region n 4452_021 v1.3 107 Peripherals 6.4 CCM AES CCM mode encryption Cipher block chaining - message authentication code (CCM) mode is an authenticated encryption algorithm designed to provide both authentication and confidentiality during data transfer. CCM combines counter mode encryption and CBC-MAC authentication. The CCM terminology "Message authentication code (MAC)" is called the "Message integrity check (MIC)" in Bluetooth terminology and also in this document. The CCM block generates an encrypted keystream that is applied to input data using the XOR operation and generates the 4 byte MIC field in one operation. The CCM and radio can be configured to work synchronously. The CCM will encrypt in time for transmission and decrypt after receiving bytes into memory from the radio. All operations can complete within the packet RX or TX time. CCM on this device is implemented according to Bluetooth requirements and the algorithm as defined in IETF RFC3610, and depends on the AES-128 block cipher. A description of the CCM algorithm can also be found in NIST Special Publication 800-38C. The Bluetooth specification describes the configuration of counter mode blocks and encryption blocks to implement compliant encryption for BLE. The CCM block uses EasyDMA to load key, counter mode blocks (including the nonce required), and to read/write plain text and cipher text. The AES CCM supports three operations: key-stream generation, packet encryption, and packet decryption. All these operations are done in compliance with the Bluetooth specification.13 key-stream generation encryption / decryption KSGEN ENDKSGEN CRYPT ENDCRYPT SHORTCUT Figure 29: Key-stream generation followed by encryption or decryption. The shortcut is optional. 6.4.1 Key-steam generation A new key-stream needs to be generated before a new packet encryption or packet decryption operation can be started. A key-stream is generated by triggering the KSGEN task and an ENDKSGEN event will be generated when the key-stream has been generated. Key-stream generation, packet encryption, and packet decryption operations utilize the configuration specified in the data structure pointed to by CNFPTR on page 118. It is necessary to configure this pointer and its underlying data structure, and the MODE on page 117 register before the KSGEN task is triggered. The key-stream will be stored in the AES CCMs temporary memory area, specified by the SCRATCHPTR on page 118, where it will be used in subsequent encryption and decryption operations. For default length packets (MODE.LENGTH = Default) the size of the generated key-stream is 27 bytes. When using extended length packets (MODE.LENGTH = Extended) the MAXPACKETSIZE on page 119 register specifies the length of the key-stream to be generated. The length of the generated key-stream must be greater or equal to the length of the subsequent packet payload to be encrypted or decrypted. The maximum length of the key-stream in extended mode is 251 bytes, which means that the maximum packet payload size is 251. 13 Bluetooth AES CCM 128 bit block encryption, see Bluetooth Core specification Version 4.0. 4452_021 v1.3 108 Peripherals If a shortcut is used between ENDKSGEN event and CRYPT task, the INPTR on page 118 pointer and the OUTPTR on page 118 pointers must also be configured before the KSGEN task is triggered. 6.4.2 Encryption During packet encryption, the AES CCM will read the unencrypted packet located in RAM at the address specified in the INPTR pointer, encrypt the packet and append a four byte long Message Integrity Check

(MIC) field to the packet. Encryption is started by triggering the CRYPT task with the MODE on page 117 register set to ENCRYPTION. An ENDCRYPT event will be generated when packet encryption is completed The AES CCM will also modify the length field of the packet to adjust for the appended MIC field, that is, add four bytes to the length, and store the resulting packet back into RAM at the address specified in the OUTPTR on page 118 pointer, see Encryption on page 109. Empty packets (length field is set to 0) will not be encrypted but instead moved unmodified through the AES CCM. The CCM supports different widths of the LENGTH field in the data structure for encrypted packets. This is configured in the MODE on page 117 register. INPTR OUTPTR Unencrypted packet H L RFU PL Encrypted packet MODE = ENCRYPTION AES CCM H L+4 RFU EPL MIC SCRATCHPTR H: Header (S0) L: Length RFU: reserved for future use (S1) PL: unencrypted payload EPL: encrypted payload Scratch area CCM data structure CNFPTR Figure 30: Encryption 6.4.3 Decryption During packet decryption, the AES CCM will read the encrypted packet located in RAM at the address specified in the INPTR pointer, decrypt the packet, authenticate the packets MIC field and generate the appropriate MIC status. Decryption is started by triggering the CRYPT task with the MODE on page 117 register set to DECRYPTION. An ENDCRYPT event will be generated when packet decryption is completed The AES CCM will also modify the length field of the packet to adjust for the MIC field, that is, subtract four bytes from the length, and then store the decrypted packet into RAM at the address pointed to by the OUTPTR pointer, see Decryption on page 110. The CCM is only able to decrypt packet payloads that are at least 5 bytes long, that is, 1 byte or more encrypted payload (EPL) and 4 bytes of MIC. The CCM will therefore generate a MIC error for packets where the length field is set to 1, 2, 3 or 4. Empty packets (length field is set to 0) will not be decrypted but instead moved unmodified through the AES CCM, these packets will always pass the MIC check. The CCM supports different widths of the LENGTH field in the data structure for decrypted packets. This is configured in the MODE on page 117 register. 4452_021 v1.3 109 Peripherals OUTPTR INPTR Unencrypted packet H L RFU PL Encrypted packet MODE = DECRYPTION AES CCM H L+4 RFU EPL MIC SCRATCHPTR H: Header (S0) L: Length RFU: reserved for future use (S1) PL: unencrypted payload EPL: encrypted payload Scratch area CCM data structure CNFPTR Figure 31: Decryption 6.4.4 AES CCM and RADIO concurrent operation The CCM module is able to encrypt/decrypt data synchronously to data being transmitted or received on the radio. In order for the CCM module to run synchronously with the radio, the data rate setting in the MODE on page 117 register needs to match the radio data rate. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. The data rate setting of the MODE on page 117 register can also be overridden on-the-fly during an ongoing encrypt/decrypt operation by the contents of the RATEOVERRIDE on page 119 register. The data rate setting in this register applies whenever the RATEOVERRIDE task is triggered. This feature can be useful in cases where the radio data rate is changed during an ongoing packet transaction. 6.4.5 Encrypting packets on-the-fly in radio transmit mode When the AES CCM is encrypting a packet on-the-fly at the same time as the radio is transmitting it, the radio must read the encrypted packet from the same memory location as the AES CCM is writing to. The OUTPTR on page 118 pointer in the AES CCM must therefore point to the same memory location as the PACKETPTR pointer in the radio, see Configuration of on-the-fly encryption on page 110. INPTR OUTPTR

PACKETPTR Unencrypted packet H L RFU PL Encrypted packet MODE = ENCRYPTION AES CCM H L+4 RFU EPL MIC SCRATCHPTR H: Header (S0) L: Length RFU: reserved for future use (S1) PL: unencrypted payload EPL: encrypted payload Scratch area CCM data structure CNFPTR To remote receiver TXEN RADIO Figure 32: Configuration of on-the-fly encryption In order to match the RADIOs timing, the KSGEN task must be triggered early enough to allow the key-

stream generation to complete before the encryption of the packet shall start. For short packets (MODE.LENGTH = Default) the KSGEN task must be triggered no later than when the START task in the RADIO is triggered. In addition the shortcut between the ENDKSGEN event and the CRYPT task must be enabled. This use-case is illustrated in On-the-fly encryption of short packets

(MODE.LENGTH = Default) using a PPI connection on page 111 using a PPI connection between the READY event in the RADIO and the KSGEN task in the AES CCM. For long packets (MODE.LENGTH = Extended) the key-stream generation will need to be started even earlier, for example at the time when the TXEN task in the RADIO is triggered. Important: Refer to Timing specification on page 120 for information about the time needed for generating a key-stream. 4452_021 v1.3 110 Peripherals SHORTCUT ENDKSGEN CRYPT key-stream generation PPI READY AES CCM encryption KSGEN ENDCRYPT RADIO RU P A H L RFU EPL MIC CRC TXEN END READY START RU: Ramp-up of RADIO P: Preamble A: Address SHORTCUT H: Header (S0) L: Length RFU: reserved for future use (S1) EPL: encrypted payload Figure 33: On-the-fly encryption of short packets (MODE.LENGTH = Default) using a PPI connection 6.4.6 Decrypting packets on-the-fly in radio receive mode When the AES CCM is decrypting a packet on-the-fly at the same time as the RADIO is receiving it, the AES CCM must read the encrypted packet from the same memory location as the RADIO is writing to. The INPTR on page 118 pointer in the AES CCM must therefore point to the same memory location as the PACKETPTR pointer in the RADIO, see Configuration of on-the-fly decryption on page 111. OUTPTR INPTR

PACKETPTR Unencrypted packet H L RFU PL Encrypted packet MODE = DECRYPTION AES CCM H L+4 RFU EPL MIC SCRATCHPTR H: Header (S0) L: Length RFU: reserved for future use (S1) PL: unencrypted payload EPL: encrypted payload Scratch area CCM data structure CNFPTR From remote transmitter RXEN RADIO Figure 34: Configuration of on-the-fly decryption In order to match the RADIOs timing, the KSGEN task must be triggered early enough to allow the key-

stream generation to complete before the decryption of the packet shall start. For short packets (MODE.LENGTH = Default) the KSGEN task must be triggered no later than when the START task in the RADIO is triggered. In addition, the CRYPT task must be triggered no earlier than when the ADDRESS event is generated by the RADIO. If the CRYPT task is triggered exactly at the same time as the ADDRESS event is generated by the RADIO, the AES CCM will guarantee that the decryption is completed no later than when the END event in the RADIO is generated. This use-case is illustrated in On-the-fly decryption of short packets (MODE.LENGTH = Default) using a PPI connection on page 112 using a PPI connection between the ADDRESS event in the RADIO and the CRYPT task in the AES CCM. The KSGEN task is triggered from the READY event in the RADIO through a PPI connection. For long packets (MODE.LENGTH = Extended) the key-stream generation will need to be started even earlier, for example at the time when the RXEN task in the RADIO is triggered. 4452_021 v1.3 111 Peripherals Important: Refer to Timing specification on page 120 for information about the time needed for generating a key-stream. AES CCM decryption KSGEN ENDKSGEN CRYPT ENDCRYPT key-stream generation PPI READY PPI ADDRESS RADIO RU P A H L RFU EPL MIC CRC RXEN END READY START RU: Ramp-up of RADIO P: Preamble A: Address SHORTCUT H: Header (S0) L: Length RFU: reserved for future use (S1) EPL: encrypted payload

: RADIO receiving noise Figure 35: On-the-fly decryption of short packets (MODE.LENGTH = Default) using a PPI connection 6.4.7 CCM data structure The CCM data structure is located in Data RAM at the memory location specified by the CNFPTR pointer register. Property KEY PKTCTR Address offset Description 16 byte AES key Octet0 (LSO) of packet counter Octet1 of packet counter Octet2 of packet counter Octet3 of packet counter significant bit) Bit7: Ignored Ignored Ignored Ignored Bit 6 Bit 0: Octet4 (7 most significant bits of packet counter, with Bit 6 being the most IV 8 byte initialization vector (IV) Octet0 (LSO) of IV, Octet1 of IV, , Octet7 (MSO) of IV Bit 0: Direction bit Bit 7 Bit 1: Zero padded Table 27: CCM data structure overview The NONCE vector (as specified by the Bluetooth Core Specification) will be generated by hardware based on the information specified in the CCM data structure from CCM data structure overview on page 112 . Property HEADER LENGTH RFU PAYLOAD Address offset Description Packet Header Number of bytes in unencrypted payload Reserved Future Use Unencrypted payload Table 28: Data structure for unencrypted packet 0 16 17 18 19 20 21 22 23 24 25 0 1 2 3 4452_021 v1.3 112 Peripherals Property HEADER LENGTH RFU MIC PAYLOAD 0 1 2 3 Address offset Description Packet Header Number of bytes in encrypted payload including length of MIC Important: LENGTH will be 0 for empty packets since the MIC is not added to empty packets Reserved Future Use Encrypted payload 3 + payload length ENCRYPT: 4 bytes encrypted MIC Important: MIC is not added to empty packets Table 29: Data structure for encrypted packet 6.4.8 EasyDMA and ERROR event The CCM implements an EasyDMA mechanism for reading and writing to the RAM. In cases where the CPU and other EasyDMA enabled peripherals are accessing the same RAM block at the same time, a high level of bus collisions may cause too slow operation for correct on the fly encryption. In this case the ERROR event will be generated. The EasyDMA will have finished accessing the RAM when the ENDKSGEN and ENDCRYPT events are generated. If the CNFPTR, SCRATCHPTR, INPTR and the OUTPTR are not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. 6.4.9 Registers Base address Peripheral Instance Description Configuration 0x4000F000 CCM CCM AES counter with CBC-MAC (CCM) mode block encryption Table 30: Instances Description Start generation of key-stream. This operation will stop by itself when completed. Start encryption/decryption. This operation will stop by itself when completed. Stop encryption/decryption TASKS_RATEOVERRIDE Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register Register TASKS_KSGEN TASKS_CRYPT TASKS_STOP EVENTS_ENDKSGEN EVENTS_ENDCRYPT EVENTS_ERROR SHORTS INTENSET INTENCLR MICSTATUS ENABLE MODE CNFPTR INPTR OUTPTR Offset 0x000 0x004 0x008 0x00C 0x100 0x104 0x108 0x200 0x304 0x308 0x400 0x500 0x504 0x508 0x50C 0x510 for any ongoing encryption/decryption Key-stream generation complete Encrypt/decrypt complete CCM error event Shortcuts between local events and tasks Enable interrupt Disable interrupt MIC check result Enable Operation mode Input pointer Output pointer Pointer to data structure holding AES key and NONCE vector 4452_021 v1.3 113 Deprecated Peripherals Register SCRATCHPTR MAXPACKETSIZE RATEOVERRIDE Offset 0x514 0x518 0x51C Description Pointer to data area used for temporary storage Length of key-stream generated when MODE.LENGTH = Extended. Data rate override setting. Table 31: Register overview 6.4.9.1 TASKS_KSGEN Address offset: 0x000 Start generation of key-stream. This operation will stop by itself when completed. ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_KSGEN Start generation of key-stream. This operation will stop by Trigger 1 Trigger task itself when completed. 6.4.9.2 TASKS_CRYPT Address offset: 0x004 Start encryption/decryption. This operation will stop by itself when completed. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_CRYPT Start encryption/decryption. This operation will stop by Trigger 1 Trigger task itself when completed. 6.4.9.3 TASKS_STOP Address offset: 0x008 Stop encryption/decryption Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Stop encryption/decryption Trigger 1 Trigger task 6.4.9.4 TASKS_RATEOVERRIDE Address offset: 0x00C Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption A A A 4452_021 v1.3 114 ID ID A ID ID A ID ID A ID ID A Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_RATEOVERRIDE Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption Trigger 1 Trigger task 6.4.9.5 EVENTS_ENDKSGEN Address offset: 0x100 Key-stream generation complete 6.4.9.6 EVENTS_ENDCRYPT Address offset: 0x104 Encrypt/decrypt complete Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ENDKSGEN Key-stream generation complete NotGenerated Generated Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ENDCRYPT NotGenerated Generated Encrypt/decrypt complete Event not generated Event generated 6.4.9.7 EVENTS_ERROR ( Deprecated ) Address offset: 0x108 CCM error event Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ERROR Deprecated NotGenerated Generated CCM error event Event not generated Event generated 6.4.9.8 SHORTS Address offset: 0x200 Shortcuts between local events and tasks 4452_021 v1.3 115 A A A A 0 1 0 1 0 1 ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW ENDKSGEN_CRYPT Shortcut between event ENDKSGEN and task CRYPT Disabled Enabled Disable shortcut Enable shortcut Peripherals A 6.4.9.9 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW ENDKSGEN Write '1' to enable interrupt for event ENDKSGEN B RW ENDCRYPT Write '1' to enable interrupt for event ENDCRYPT C RW ERROR Write '1' to enable interrupt for event ERROR Deprecated 6.4.9.10 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW ENDKSGEN Write '1' to disable interrupt for event ENDKSGEN B RW ENDCRYPT Write '1' to disable interrupt for event ENDCRYPT C RW ERROR Write '1' to disable interrupt for event ERROR Deprecated C B A C B A Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 4452_021 v1.3 116 Peripherals A A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R MICSTATUS The result of the MIC check performed during the previous CheckFailed CheckPassed decryption operation MIC check failed MIC check passed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled Enabled Enable or disable CCM Disable Enable 6.4.9.11 MICSTATUS Address offset: 0x400 MIC check result 6.4.9.12 ENABLE Address offset: 0x500 Enable Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 6.4.9.13 MODE Address offset: 0x504 Operation mode Bit number ID ID A Reset 0x00000001 AccessField RW MODE B RW DATARATE Radio data rate that the CCM shall run synchronous with 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Encryption Decryption 1Mbit 2Mbit 125Kbps 500Kbps Default The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. AES CCM packet encryption mode AES CCM packet decryption mode 1 Mbps 2 Mbps 125 Kbps 500 Kbps Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. C RW LENGTH Packet length configuration 4452_021 v1.3 117 0 1 0 2 0 1 0 1 2 3 0 Peripherals Bit number ID Reset 0x00000001 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Extended Value 1 Description generated. Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be Pointer to data structure holding AES key and NONCE vector 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Input pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Output pointer 6.4.9.14 CNFPTR Address offset: 0x508 Bit number ID ID A Reset 0x00000000 AccessField RW CNFPTR 6.4.9.15 INPTR Address offset: 0x50C Input pointer Reset 0x00000000 AccessField RW INPTR 6.4.9.16 OUTPTR Address offset: 0x510 Output pointer ID ID A ID ID A Reset 0x00000000 AccessField RW OUTPTR 6.4.9.17 SCRATCHPTR Address offset: 0x514 Pointer to data area used for temporary storage 4452_021 v1.3 118 ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW SCRATCHPTR Peripherals Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. The scratch area is used for temporary storage of data during key-stream generation and encryption. When MODE.LENGTH = Default, a space of 43 bytes is required for this temporary storage. MODE.LENGTH

= Extended (16 + MAXPACKETSIZE) bytes of storage is required. 6.4.9.18 MAXPACKETSIZE Address offset: 0x518 Length of key-stream generated when MODE.LENGTH = Extended. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A Reset 0x000000FB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 AccessField Value ID Value Description RW MAXPACKETSIZE

[0x001B..0x00FB]

Length of key-stream generated when MODE.LENGTH

= Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. 6.4.9.19 RATEOVERRIDE Address offset: 0x51C Data rate override setting. Override value to be used instead of the setting of MODE.DATARATE. This override value applies when the RATEOVERRIDE task is triggered. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW RATEOVERRIDE Data rate override setting. 1Mbit 2Mbit 125Kbps 500Kbps 0 1 2 3 1 Mbps 2 Mbps 125 Kbps 500 Kbps 4452_021 v1.3 119 Peripherals 6.4.10 Electrical specification 6.4.10.1 Timing specification Symbol tkgen Description Time needed for key-stream generation (given priority access to destination RAM block). Min. Typ. Max. Units 50 s 6.5 COMP Comparator The comparator (COMP) compares an input voltage (VIN+) against a second input voltage (VIN-). VIN+ can be derived from an analog input pin (AIN0-AIN7). VIN- can be derived from multiple sources depending on the operation mode of the comparator. Main features of the comparator are:

Input range from 0 V to VDD Single-ended mode Differential mode Configurable hysteresis Reference inputs (VREF):

Fully flexible hysteresis using a 64-level reference ladder VDD External reference from AIN0 to AIN7 (between 0 V and VDD) Internal references 1.2 V, 1.8 V and 2.4 V Three speed/power consumption modes: low-power, normal and high-speed Event generation on output changes UP event on VIN- > VIN+

DOWN event on VIN- < VIN+

CROSS event on VIN+ and VIN- crossing READY event on core and internal reference (if used) ready 4452_021 v1.3 120 Peripherals 0 N A I 1 N A I 2 N A I 3 N A I 4 N A I 5 N A I 6 N A I 7 N A I MUX PSEL S T A R T S T O P S A M P L E VIN+

VIN-

Comparator core HYST MODE RESULT Output 0 = BELOW (VIN+ < VIN-) 1 = ABOVE (VIN+ > VIN-) U P D O W N C R O S S R E A D Y Figure 36: Comparator overview Once enabled (using the ENABLE register), the comparator is started by triggering the START task and stopped by triggering the STOP task. The comparator will generate a READY event to indicate when it is ready for use and the output is correct. The delay between START and READY is tINT_REF,START if an internal reference is selected, or t COMP,START if an external reference is used. When the COMP module is started, events will be generated every time VIN+ crosses VIN-. Operation modes The comparator can be configured to operate in two main operation modes, differential mode and single-

ended mode. See the MODE register for more information. In both operation modes, the comparator can operate in different speed and power consumption modes (low-power, normal and high-speed). High-

speed mode will consume more power compared to low-power mode, and low-power mode will result in slower response time compared to high-speed mode. Use the PSEL register to select any of the AIN0-AIN7 pins as VIN+ input, regardless of the operation mode selected for the comparator. The source of VIN- depends on which operation mode is used:

Differential mode: Derived directly from AIN0 to AIN7 Single-ended mode: Derived from VREF. VREF can be derived from VDD, AIN0-AIN7 or internal 1.2 V, 1.8 V and 2.4 V references. The selected analog pins will be acquired by the comparator once it is enabled. An optional hysteresis on VIN+ and VIN- can be enabled when the module is used in differential mode through the HYST register. In single-ended mode, VUP and VDOWN thresholds can be set to implement a hysteresis using the reference ladder (see Comparator in single-ended mode on page 123). This hysteresis is in the order of magnitude of VDIFFHYST, and shall prevent noise on the signal to create unwanted events. See Hysteresis example where VIN+ starts below VUP on page 124 for illustration of the effect of an active hysteresis on a noisy input signal. An upward crossing will generate an UP event and a downward crossing will generate a DOWN event. The CROSS event will be generated every time there is a crossing, independent of direction. The immediate value of the comparator can be sampled to RESULT register by triggering the SAMPLE task. 4452_021 v1.3 121 6.5.1 Differential mode In differential mode, the reference input VIN- is derived directly from one of the AINx pins. Before enabling the comparator via the ENABLE register, the following registers must be configured for the differential mode:

Peripherals PSEL MODE EXTREFSEL 0 N A I 1 N A I 2 N A I 3 N A I 4 N A I 5 N A I 6 N A I 7 N A I 0 N A I 1 N A I 2 N A I 3 N A I 4 N A I 5 N A I 6 N A I 7 N A I MUX PSEL EXTREFSEL MUX S T A R T S T O P S A M P L E VIN+

VIN-

Comparator core MODE RESULT Output 0 = BELOW (VIN+ < VIN-) 1 = ABOVE (VIN+ > VIN-) U P D O W N C R O S S R E A D Y Figure 37: Comparator in differential mode Note: Depending on the device, not all the analog inputs may be available for each MUX. See definitions for PSEL and EXTREFSEL for more information about which analog pins are available on a particular device. When HYST register is turned on while in this mode, the output of the comparator (and associated events) will change from ABOVE to BELOW whenever VIN+ becomes lower than VIN- - (VDIFFHYST / 2). It will also change from BELOW to ABOVE whenever VIN+ becomes higher than VIN- + (VDIFFHYST / 2). This behavior is illustrated in Hysteresis enabled in differential mode on page 122. VIN+

VIN- + (VDIFFHYST / 2) VIN- - (VDIFFHYST / 2) Output ABOVE

(VIN+ > (VIN- + VDIFFHYST /2)) BELOW

(VIN+ < (VIN- - VDIFFHYST /2)) ABOVE

(VIN+ > (VIN- + VDIFFHYST /2)) BELOW Figure 38: Hysteresis enabled in differential mode t 6.5.2 Single-ended mode In single-ended mode, VIN- is derived from the reference ladder. 4452_021 v1.3 122 Before enabling the comparator via the ENABLE register, the following registers must be configured for the single-ended mode:

Peripherals PSEL MODE REFSEL EXTREFSEL TH The reference ladder uses the reference voltage (VREF) to derive two new voltage references, VUP and VDOWN. VUP and VDOWN are configured using THUP and THDOWN respectively in the TH register. VREF can be derived from any of the available reference sources, configured using the EXTREFSEL and REFSEL registers as illustrated in Comparator in single-ended mode on page 123. When AREF is selected in the REFSEL register, the EXTREFSEL register is used to select one of the AIN0-AIN7 analog input pins as reference input. The selected analog pins will be acquired by the comparator once it is enabled. 0 N A I 1 N A I 2 N A I 3 N A I 4 N A I 5 N A I 6 N A I 7 N A I 0 N A I 1 N A I 2 N A I 3 N A I 4 N A I 5 N A I 6 N A I 7 N A I MUX PSEL TH REFSEL EXTREFSEL MUX S T A R T S T O P S A M P L E VIN+

VIN-

MUX VUP VDOWN 0 1 Comparator core HYST Reference ladder VREF MUX MODE RESULT VDD AREF 1V2 1V8 2V4 Output 0 = BELOW (VIN+ < VIN-) 1 = ABOVE (VIN+ > VIN-) U P D O W N C R O S S R E A D Y Figure 39: Comparator in single-ended mode Note: Depending on the device, not all the analog inputs may be available for each MUX. See definitions for PSEL and EXTREFSEL for more information about which analog pins are available on a particular device. When the comparator core detects that VIN+ > VIN-, i.e. ABOVE as per the RESULT register, VIN- will switch to VDOWN. When VIN+ falls below VIN- again, VIN- will be switched back to VUP. By specifying VUP larger than VDOWN, a hysteresis can be generated as illustrated in Hysteresis example where VIN+ starts below VUP on page 124 and Hysteresis example where VIN+ starts above VUP on page 124. Writing to HYST has no effect in single-ended mode, and the content of this register is ignored. 4452_021 v1.3 123 Peripherals t t VIN+

VUP VDOWN t t u p u O

N V I T L U S E R U P C t t u p u O

N V I T L U S E R U P C VUP VDOWN Y D A E R 1 T R A T S VIN+

Y D A E R 1 T R A T S BELOW ( VIN+ < VIN-) ABOVE (VIN+ > VIN-) BELOW VUP VDOWN VUP BELOW P U 2 3 ABOVE N W O D E L P M A S E L P M A S Figure 40: Hysteresis example where VIN+ starts below VUP ABOVE (VIN+ > VIN-) BELOW ( VIN+ < VIN-) ABOVE (VIN+ > VIN-) BELOW VDOWN VUP VDOWN VUP ABOVE BELOW N W O D 2 E L P M A S P U 3 E L P M A S ABOVE N W O D Figure 41: Hysteresis example where VIN+ starts above VUP 6.5.3 Registers Base address Peripheral Description Configuration 0x40013000 COMP General purpose comparator Instance COMP Table 32: Instances Register TASKS_START Offset 0x000 Description Start comparator 4452_021 v1.3 124 Peripherals A A Register TASKS_STOP TASKS_SAMPLE EVENTS_READY EVENTS_DOWN EVENTS_UP EVENTS_CROSS SHORTS INTEN INTENSET INTENCLR RESULT ENABLE PSEL REFSEL EXTREFSEL TH MODE HYST Offset Description 0x004 0x008 0x100 0x104 0x108 0x10C 0x200 0x300 0x304 0x308 0x400 0x500 0x504 0x508 0x50C 0x530 0x534 0x538 Stop comparator Sample comparator value COMP is ready and output is valid Downward crossing Upward crossing Downward or upward crossing Shortcuts between local events and tasks Enable or disable interrupt Enable interrupt Disable interrupt Compare result COMP enable Pin select Reference source select for single-ended mode External reference select Threshold configuration for hysteresis unit Mode configuration Comparator hysteresis enable Table 33: Register overview 6.5.3.1 TASKS_START Address offset: 0x000 Start comparator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_START Trigger 1 Start comparator Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Trigger 1 Stop comparator Trigger task ID ID A ID ID A 6.5.3.2 TASKS_STOP Address offset: 0x004 Stop comparator 6.5.3.3 TASKS_SAMPLE Address offset: 0x008 Sample comparator value 4452_021 v1.3 125 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_SAMPLE Sample comparator value Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_READY COMP is ready and output is valid NotGenerated Generated Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_DOWN NotGenerated Generated Downward crossing Event not generated Event generated 6.5.3.4 EVENTS_READY Address offset: 0x100 COMP is ready and output is valid 6.5.3.5 EVENTS_DOWN Address offset: 0x104 Downward crossing 6.5.3.6 EVENTS_UP Address offset: 0x108 Upward crossing ID ID A ID ID A ID ID A ID ID A 0 1 0 1 0 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_UP NotGenerated Generated Upward crossing Event not generated Event generated 6.5.3.7 EVENTS_CROSS Address offset: 0x10C Downward or upward crossing 4452_021 v1.3 126 A A A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CROSS NotGenerated Generated Downward or upward crossing Event not generated Event generated Peripherals A 6.5.3.8 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW READY_SAMPLE Shortcut between event READY and task SAMPLE ID ID A ID ID A B RW READY_STOP Shortcut between event READY and task STOP C RW DOWN_STOP Shortcut between event DOWN and task STOP D RW UP_STOP Shortcut between event UP and task STOP E RW CROSS_STOP Shortcut between event CROSS and task STOP 6.5.3.9 INTEN Address offset: 0x300 Enable or disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW READY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event READY B RW DOWN Enable or disable interrupt for event DOWN C RW UP Enable or disable interrupt for event UP D RW CROSS Enable or disable interrupt for event CROSS 4452_021 v1.3 127 Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable Enable Disable Enable Disable Enable Disable Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Peripherals D C B A Value ID Enabled Value 1 Description Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event READY B RW DOWN Write '1' to enable interrupt for event DOWN C RW UP Write '1' to enable interrupt for event UP D RW CROSS Write '1' to enable interrupt for event CROSS Bit number ID Reset 0x00000000 ID AccessField 6.5.3.10 INTENSET Address offset: 0x304 Enable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW READY 6.5.3.11 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW READY Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event READY B RW DOWN Write '1' to disable interrupt for event DOWN C RW UP Write '1' to disable interrupt for event UP 4452_021 v1.3 128 Peripherals D C B A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event CROSS Clear Disabled Enabled Disable Read: Disabled Read: Enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Result of last compare. Decision point SAMPLE task. Input voltage is below the threshold (VIN+ < VIN-) Input voltage is above the threshold (VIN+ > VIN-) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable COMP Disable Enable A A A Bit number ID ID D Reset 0x00000000 AccessField RW CROSS 6.5.3.12 RESULT Address offset: 0x400 Compare result Bit number ID ID A Reset 0x00000000 AccessField R RESULT 6.5.3.13 ENABLE Address offset: 0x500 COMP enable Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 6.5.3.14 PSEL Address offset: 0x504 Pin select Bit number ID ID A Reset 0x00000000 AccessField RW PSEL Below Above Disabled Enabled AnalogInput0 AnalogInput1 AnalogInput2 AnalogInput3 AnalogInput4 AnalogInput5 AnalogInput6 1 0 1 0 1 0 2 0 1 2 3 4 5 6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Analog pin select AIN0 selected as analog input AIN1 selected as analog input AIN2 selected as analog input AIN3 selected as analog input AIN4 selected as analog input AIN5 selected as analog input AIN6 selected as analog input 4452_021 v1.3 129 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID AnalogInput7 Value 7 Description AIN7 selected as analog input Peripherals A A A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Value ID Value Description Reference select VREF = internal 1.2 V reference (VDD >= 1.7 V) VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) VREF = VDD VREF = AREF Reference source select for single-ended mode Bit number ID Reset 0x00000000 ID AccessField 6.5.3.15 REFSEL Address offset: 0x508 Bit number ID ID A Reset 0x00000004 AccessField RW REFSEL Int1V2 Int1V8 Int2V4 VDD ARef 6.5.3.16 EXTREFSEL Address offset: 0x50C External reference select ID ID A ID ID A B Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EXTREFSEL AnalogReference0 AnalogReference1 AnalogReference2 AnalogReference3 AnalogReference4 AnalogReference5 AnalogReference6 AnalogReference7 External analog reference select Use AIN0 as external analog reference Use AIN1 as external analog reference Use AIN2 as external analog reference Use AIN3 as external analog reference Use AIN4 as external analog reference Use AIN5 as external analog reference Use AIN6 as external analog reference Use AIN7 as external analog reference 6.5.3.17 TH Address offset: 0x530 Threshold configuration for hysteresis unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B B B B B B A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField RW THDOWN RW THUP Value ID Description Value

[63:0]

[63:0]

VDOWN = (THDOWN+1)/64*VREF VUP = (THUP+1)/64*VREF 4452_021 v1.3 130 0 1 2 4 5 0 1 2 3 4 5 6 7 Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Speed and power modes Low-power mode Normal mode High-speed mode Main operation modes Single-ended mode Differential mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NoHyst Hyst50mV Comparator hysteresis Comparator hysteresis disabled Comparator hysteresis enabled 6.5.3.18 MODE Address offset: 0x534 Mode configuration Low Normal High SE Diff 6.5.3.19 HYST Address offset: 0x538 Comparator hysteresis enable Bit number ID ID A Reset 0x00000000 AccessField RW SP B RW MAIN Bit number ID ID A Reset 0x00000000 AccessField RW HYST 0 1 2 0 1 0 1 6.5.4 Electrical specification 6.5.4.1 COMP Electrical Specification Symbol tPROPDLY,LP tPROPDLY,N tPROPDLY,HS VDIFFHYST VVDD-VREF tINT_REF,START EINT_REF VINPUTOFFSET tCOMP,START Description Propagation delay, low-power mode1 Propagation delay, normal mode1 Propagation delay, high-speed mode1 Optional hysteresis applied to differential input Required difference between VDD and a selected VREF, VDD

> VREF Startup time for the internal bandgap reference Internal bandgap reference error Input offset Startup time for the comparator core 1 Propagation delay is with 10 mV overdrive. 4452_021 v1.3 131 Min. Typ. Max. Units 0.6 0.2 0.1 30 50 3 90 80 3 15 s s s mV V s

mV s 10 0.3

-3

-15 Peripherals 6.6 ECB AES electronic codebook mode encryption The AES electronic codebook mode encryption (ECB) can be used for a range of cryptographic functions like hash generation, digital signatures, and keystream generation for data encryption/decryption. The ECB encryption block supports 128 bit AES encryption (encryption only, not decryption). AES ECB operates with EasyDMA access to system Data RAM for in-place operations on cleartext and ciphertext during encryption. ECB uses the same AES core as the CCM and AAR blocks and is an asynchronous operation which may not complete if the AES core is busy. AES ECB features:

128 bit AES encryption Supports standard AES ECB block encryption Memory pointer support DMA data transfer AES ECB performs a 128 bit AES block encrypt. At the STARTECB task, data and key is loaded into the algorithm by EasyDMA. When output data has been written back to memory, the ENDECB event is triggered. AES ECB can be stopped by triggering the STOPECB task. 6.6.1 Shared resources The ECB, CCM, and AAR share the same AES module. The ECB will always have lowest priority and if there is a sharing conflict during encryption, the ECB operation will be aborted and an ERRORECB event will be generated. 6.6.2 EasyDMA The ECB implements an EasyDMA mechanism for reading and writing to the Data RAM. This DMA cannot access the program memory or any other parts of the memory area except RAM. If the ECBDATAPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. The EasyDMA will have finished accessing the Data RAM when the ENDECB or ERRORECB is generated. 6.6.3 ECB data structure Input to the block encrypt and output from the block encrypt are stored in the same data structure. ECBDATAPTR should point to this data structure before STARTECB is initiated. Property KEY CLEARTEXT CIPHERTEXT Address offset 0 16 32 Description 16 byte AES key 16 byte AES cleartext input block 16 byte AES ciphertext output block Table 34: ECB data structure overview 4452_021 v1.3 132 Peripherals 6.6.4 Registers Base address Peripheral Instance Description Configuration 0x4000E000 ECB ECB AES electronic code book (ECB) mode block encryption Table 35: Instances Register TASKS_STARTECB TASKS_STOPECB EVENTS_ENDECB INTENSET INTENCLR ECBDATAPTR Offset 0x000 0x004 0x100 0x104 0x304 0x308 0x504 Description Start ECB block encrypt Abort a possible executing ECB operation ECB block encrypt complete Enable interrupt Disable interrupt ECB block encrypt memory pointers EVENTS_ERRORECB ECB block encrypt aborted because of a STOPECB task or due to an error Table 36: Register overview 6.6.4.1 TASKS_STARTECB Address offset: 0x000 Start ECB block encrypt ID ID A ID ID A If a crypto operation is already running in the AES core, the STARTECB task will not start a new encryption and an ERRORECB event will be triggered Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTECB Start ECB block encrypt If a crypto operation is already running in the AES core, the STARTECB task will not start a new encryption and an ERRORECB event will be triggered Trigger 1 Trigger task 6.6.4.2 TASKS_STOPECB Address offset: 0x004 Abort a possible executing ECB operation If a running ECB operation is aborted by STOPECB, the ERRORECB event is triggered. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOPECB Abort a possible executing ECB operation Trigger 1 Trigger task If a running ECB operation is aborted by STOPECB, the ERRORECB event is triggered. 4452_021 v1.3 133 A A 6.6.4.3 EVENTS_ENDECB Address offset: 0x100 ECB block encrypt complete ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ENDECB NotGenerated Generated 6.6.4.4 EVENTS_ERRORECB Address offset: 0x104 ECB block encrypt complete Event not generated Event generated ECB block encrypt aborted because of a STOPECB task or due to an error Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ERRORECB ECB block encrypt aborted because of a STOPECB task or NotGenerated Generated due to an error Event not generated Event generated Peripherals A A 6.6.4.5 INTENSET Address offset: 0x304 Enable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW ENDECB 6.6.4.6 INTENCLR Address offset: 0x308 Disable interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event ENDECB B RW ERRORECB Write '1' to enable interrupt for event ERRORECB Set Disabled Enabled Set Disabled Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled 0 1 0 1 1 0 1 1 0 1 4452_021 v1.3 134 Bit number ID ID A Reset 0x00000000 AccessField RW ENDECB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event ENDECB Peripherals B A B RW ERRORECB Write '1' to disable interrupt for event ERRORECB Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled 6.6.4.7 ECBDATAPTR Address offset: 0x504 ECB block encrypt memory pointers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW ECBDATAPTR Pointer to the ECB data structure (see Table 1 ECB data ID ID A structure overview) 6.6.5 Electrical specification 6.6.5.1 ECB Electrical Specification Symbol tECB Description Run time per 16 byte block in all modes Min. Typ. Max. Units 7.2 s 6.7 EGU Event generator unit Event generator unit (EGU) provides support for interlayer signaling. This means providing support for atomic triggering of both CPU execution and hardware tasks, from both firmware (by CPU) and hardware

(by PPI). This feature can be used for triggering CPU execution at a lower priority execution from a higher priority execution, or to handle a peripheral's interrupt service routine (ISR) execution at a lower priority for some of its events. However, triggering any priority from any priority is possible. Listed here are the main EGU features:

Software-enabled interrupt triggering Separate interrupt vectors for every EGU instance Up to 16 separate event flags per interrupt for multiplexing Each instance of EGU implements a set of tasks which can individually be triggered to generate the corresponding event. For example, the corresponding event for TASKS_TRIGGER[n] is EVENTS_TRIGGERED[n]. See Instances on page 136 for a list of EGU instances. 4452_021 v1.3 135 Peripherals Base address Peripheral Instance Description Configuration 6.7.1 Registers 0x40014000 0x40015000 0x40016000 0x40017000 0x40018000 0x40019000 EGU EGU EGU EGU EGU EGU EGU0 EGU1 EGU2 EGU3 EGU4 EGU5 Register Offset Description Event generator unit 0 Event generator unit 1 Event generator unit 2 Event generator unit 3 Event generator unit 4 Event generator unit 5 Table 37: Instances TASKS_TRIGGER[0]

TASKS_TRIGGER[1]

TASKS_TRIGGER[2]

TASKS_TRIGGER[3]

TASKS_TRIGGER[4]

TASKS_TRIGGER[5]

TASKS_TRIGGER[6]

TASKS_TRIGGER[7]

TASKS_TRIGGER[8]

TASKS_TRIGGER[9]

TASKS_TRIGGER[10]

TASKS_TRIGGER[11]

TASKS_TRIGGER[12]

TASKS_TRIGGER[13]

TASKS_TRIGGER[14]

TASKS_TRIGGER[15]

EVENTS_TRIGGERED[0]

EVENTS_TRIGGERED[1]

EVENTS_TRIGGERED[2]

EVENTS_TRIGGERED[3]

EVENTS_TRIGGERED[4]

EVENTS_TRIGGERED[5]

EVENTS_TRIGGERED[6]

EVENTS_TRIGGERED[7]

EVENTS_TRIGGERED[8]

EVENTS_TRIGGERED[9]

EVENTS_TRIGGERED[10]

EVENTS_TRIGGERED[11]

EVENTS_TRIGGERED[12]

EVENTS_TRIGGERED[13]

EVENTS_TRIGGERED[14]

EVENTS_TRIGGERED[15]

INTEN INTENSET INTENCLR 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C 0x300 0x304 0x308 Trigger 0 for triggering the corresponding TRIGGERED[0] event Trigger 1 for triggering the corresponding TRIGGERED[1] event Trigger 2 for triggering the corresponding TRIGGERED[2] event Trigger 3 for triggering the corresponding TRIGGERED[3] event Trigger 4 for triggering the corresponding TRIGGERED[4] event Trigger 5 for triggering the corresponding TRIGGERED[5] event Trigger 6 for triggering the corresponding TRIGGERED[6] event Trigger 7 for triggering the corresponding TRIGGERED[7] event Trigger 8 for triggering the corresponding TRIGGERED[8] event Trigger 9 for triggering the corresponding TRIGGERED[9] event Trigger 10 for triggering the corresponding TRIGGERED[10] event Trigger 11 for triggering the corresponding TRIGGERED[11] event Trigger 12 for triggering the corresponding TRIGGERED[12] event Trigger 13 for triggering the corresponding TRIGGERED[13] event Trigger 14 for triggering the corresponding TRIGGERED[14] event Trigger 15 for triggering the corresponding TRIGGERED[15] event Event number 0 generated by triggering the corresponding TRIGGER[0] task Event number 1 generated by triggering the corresponding TRIGGER[1] task Event number 2 generated by triggering the corresponding TRIGGER[2] task Event number 3 generated by triggering the corresponding TRIGGER[3] task Event number 4 generated by triggering the corresponding TRIGGER[4] task Event number 5 generated by triggering the corresponding TRIGGER[5] task Event number 6 generated by triggering the corresponding TRIGGER[6] task Event number 7 generated by triggering the corresponding TRIGGER[7] task Event number 8 generated by triggering the corresponding TRIGGER[8] task Event number 9 generated by triggering the corresponding TRIGGER[9] task Event number 10 generated by triggering the corresponding TRIGGER[10] task Event number 11 generated by triggering the corresponding TRIGGER[11] task Event number 12 generated by triggering the corresponding TRIGGER[12] task Event number 13 generated by triggering the corresponding TRIGGER[13] task Event number 14 generated by triggering the corresponding TRIGGER[14] task Event number 15 generated by triggering the corresponding TRIGGER[15] task Enable or disable interrupt Enable interrupt Disable interrupt Table 38: Register overview 6.7.1.1 TASKS_TRIGGER[n] (n=0..15) Address offset: 0x000 + (n 0x4) 4452_021 v1.3 136 Trigger n for triggering the corresponding TRIGGERED[n] event Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_TRIGGER Trigger n for triggering the corresponding TRIGGERED[n]

Trigger 1 event Trigger task 6.7.1.2 EVENTS_TRIGGERED[n] (n=0..15) Address offset: 0x100 + (n 0x4) Event number n generated by triggering the corresponding TRIGGER[n] task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_TRIGGERED Event number n generated by triggering the corresponding NotGenerated Generated TRIGGER[n] task Event not generated Event generated ID ID A ID ID A Peripherals A A 6.7.1.3 INTEN Address offset: 0x300 Enable or disable interrupt Bit number ID Reset 0x00000000 ID AccessField 6.7.1.4 INTENSET Address offset: 0x304 Enable interrupt Bit number ID Reset 0x00000000 ID AccessField 0 1 0 1 1 0 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-P RW TRIGGERED[i] (i=0..15) Enable or disable interrupt for event TRIGGERED[i]

Value ID Value Description Disabled Enabled Disable Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-P RW TRIGGERED[i] (i=0..15) Write '1' to enable interrupt for event TRIGGERED[i]

Value ID Value Description Set Disabled Enabled Enable Read: Disabled Read: Enabled 4452_021 v1.3 137 Peripherals 6.7.1.5 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-P RW TRIGGERED[i] (i=0..15) Write '1' to disable interrupt for event TRIGGERED[i]

Value ID Value Description Clear Disabled Enabled 1 0 1 Disable Read: Disabled Read: Enabled 6.7.2 Electrical specification 6.7.2.1 EGU Electrical Specification Symbol tEGU,EVT Description setting an interrupt Latency between setting an EGU event flag and the system 1 cycles Min. Typ. Max. Units 6.8 GPIO General purpose input/output The general purpose input/output pins (GPIOs) are grouped as one or more ports, with each port having up to 32 GPIOs. The number of ports and GPIOs per port varies with product variant and package. Refer to Registers on page 141 and Pin assignments on page 557 for more information about the number of GPIOs that are supported. GPIO has the following user-configurable features:

Up to 32 GPIO pins per GPIO port Output drive strength Internal pull-up and pull-down resistors Wake-up from high or low level triggers on all pins Trigger interrupt on state changes on any pin All pins can be used by the PPI task/event system One or more GPIO outputs can be controlled through the PPI and GPIOTE channels Any pin can be mapped to a peripheral for layout flexibility GPIO state changes captured on the SENSE signal can be stored by the LATCH register The GPIO port peripheral implements up to 32 pins, PIN0 through PIN31. Each of these pins can be individually configured in the PIN_CNF[n] registers (n=0..31). The following parameters can be configured through these registers:

Direction Drive strength Enabling of pull-up and pull-down resistors Pin sensing Input buffer disconnect 4452_021 v1.3 138 Peripherals Analog input (for selected pins) The PIN_CNF registers are retained registers. See POWER Power supply on page 58 for more information about retained registers. 6.8.1 Pin configuration Pins can be individually configured through the SENSE field in the PIN_CNF[n] register to detect either a high or low level input. When the correct level is detected on a configured pin, the sense mechanism will set the DETECT signal high. Each pin has a separate DETECT signal. Default behavior, defined by the DETECTMODE register, combines all DETECT signals from the pins in the GPIO port into one common DETECT signal and routes it through the system to be utilized by other peripherals. This mechanism is functional in both System ON and System OFF mode. See GPIO port and the GPIO pin details on page 139. The following figure illustrates the GPIO port containing 32 individual pins, where PIN0 is shown in more detail for reference. All signals on the left side of the illustration are used by other peripherals in the system and therefore not directly available to the CPU. LDETECT DETECTMODE DETECT LATCH PIN0 PIN[0].CNF.DRIVE O PIN[0].OUT Sense PIN[0].CNF.DIR PIN[0].CNF.SENSE PIN[0].CNF.PULL PIN[0].IN I PIN[0].CNF.INPUT ANAEN DIR_OVERRIDE OUT_OVERRIDE OUT PIN0.DETECT PIN1.DETECT PIN31.DETECT INPUT_OVERRIDE IN ANAIN O: output buffer I: input buffer Figure 42: GPIO port and the GPIO pin details GPIO port PIN0 PIN[0].OUT PIN[0].IN PIN[0].CNF

.. PIN31 PIN[31].OUT PIN[31].IN PIN[31].CNF PIN0 PIN31 Pins should be in a level that cannot trigger the sense mechanism before being enabled. If the SENSE condition configured in the PIN_CNF registers is met when the sense mechanism is enabled, the DETECT signal will immediately go high. A PORT event is triggered if the DETECT signal was low before enabling the sense mechanism. See GPIOTE GPIO tasks and events on page 146. See the following peripherals for more information about how the DETECT signal is used:

POWER Power supply on page 58 - uses the DETECT signal to exit from System OFF mode. GPIOTE GPIO tasks and events on page 146 - uses the DETECT signal to generate the PORT event. When a pin's PINx.DETECT signal goes high, a flag is set in the LATCH register. For example, when the PIN0.DETECT signal goes high, bit 0 in the LATCH register is set to 1. If the CPU performs a clear operation on a bit in the LATCH register when the associated PINx.DETECT signal is high, the bit in the LATCH register will not be cleared. The LATCH register will only be cleared if the CPU explicitly clears it by writing a 1 to the bit that shall be cleared, i.e. the LATCH register will not be affected by a PINx.DETECT signal being set low. The LDETECT signal will be set high when one or more bits in the LATCH register are 1. The LDETECT signal will be set low when all bits in the LATCH register are successfully cleared to 0. If one or more bits in the LATCH register are 1 after the CPU has performed a clear operation on the LATCH register, a rising edge will be generated on the LDETECT signal. This is illustrated in DETECT signal behavior on page 140. 4452_021 v1.3 139 Peripherals Note: The CPU can read the LATCH register at any time to check if a SENSE condition has been met on any of the GPIO pins. This is still valid if that condition is no longer met at the time the CPU queries the LATCH register. This mechanism will work even if the LDETECT signal is not used as the DETECT signal. The LDETECT signal is by default not connected to the GPIO port's DETECT signal, but via the DETECTMODE register. It is possible to change from default behavior to the DETECT signal that is derived directly from the LDETECT signal. See GPIO port and the GPIO pin details on page 139. The following figure illustrates the DETECT signal behavior for these two alternatives. PIN31.DETECT PIN1.DETECT PIN0.DETECT DETECT

(Default mode) LATCH.31 LATCH.1 LATCH.0 DETECT

(LDETECT mode) U P C 1 2 3 4

) 0

1

H C T A L

) 1

1

H C T A L

) 1

1

H C T A L

) 1 3

1

H C T A L Figure 43: DETECT signal behavior A GPIO pin input buffer can be disconnected from the pin to enable power savings when the pin is not used as an input, see GPIO port and the GPIO pin details on page 139. Input buffers must be connected to get a valid input value in the IN register, and for the sense mechanism to get access to the pin. Other peripherals in the system can connect to GPIO pins and override their output value and configuration, or read their analog or digital input value. See GPIO port and the GPIO pin details on page 139. Selected pins also support analog input signals, see ANAIN in GPIO port and the GPIO pin details on page 139. The assignment of the analog pins can be found in Pin assignments on page 557. Note: When a pin is configured as digital input, increased current consumption occurs when the input voltage is between VIL and VIH. It is good practice to ensure that the external circuitry does not drive that pin to levels between VIL and VIH for a long period of time. 4452_021 v1.3 140 Peripherals 6.8.2 Registers Base address Peripheral Instance Description Configuration 0x50000000 0x50000000 GPIO GPIO GPIO General purpose input and output Deprecated General purpose input and output, port P0.00 to P0.31 implemented 0x50000300 GPIO General purpose input and output, port P1.00 to P1.09 implemented Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE DETECTMODE Select between default DETECT signal behavior and LDETECT mode P0 P1 0 1 Table 39: Instances Description Write GPIO port Set individual bits in GPIO port Clear individual bits in GPIO port Offset 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0x520 0x524 0x700 0x704 0x708 0x70C 0x710 0x714 0x718 0x71C 0x720 0x724 0x728 0x72C 0x730 0x734 0x738 0x73C 0x740 0x744 0x748 0x74C 0x750 0x754 0x758 0x75C 0x760 0x764 0x768 0x76C 0x770 0x774 0x778 Read GPIO port Direction of GPIO pins DIR set register DIR clear register registers Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Configuration of GPIO pins Register OUT OUTSET OUTCLR IN DIR DIRSET DIRCLR LATCH PIN_CNF[0]

PIN_CNF[1]

PIN_CNF[2]

PIN_CNF[3]

PIN_CNF[4]

PIN_CNF[5]

PIN_CNF[6]

PIN_CNF[7]

PIN_CNF[8]

PIN_CNF[9]

PIN_CNF[10]

PIN_CNF[11]

PIN_CNF[12]

PIN_CNF[13]

PIN_CNF[14]

PIN_CNF[15]

PIN_CNF[16]

PIN_CNF[17]

PIN_CNF[18]

PIN_CNF[19]

PIN_CNF[20]

PIN_CNF[21]

PIN_CNF[22]

PIN_CNF[23]

PIN_CNF[24]

PIN_CNF[25]

PIN_CNF[26]

PIN_CNF[27]

PIN_CNF[28]

PIN_CNF[29]

PIN_CNF[30]

4452_021 v1.3 141 Register PIN_CNF[31]

Offset 0x77C Description Configuration of GPIO pins Table 40: Register overview Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pin i Pin driver is low Pin driver is high Bit number ID Reset 0x00000000 ID AccessField A-f RW PIN[i] (i=0..31) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pin i Read: pin driver is low Read: pin driver is high Write: a '1' sets the pin high; a '0' has no effect 6.8.2.1 OUT Address offset: 0x504 Write GPIO port Bit number ID Reset 0x00000000 ID AccessField A-f RW PIN[i] (i=0..31) 6.8.2.2 OUTSET Address offset: 0x508 Set individual bits in GPIO port Read: reads value of OUT register. 6.8.2.3 OUTCLR Address offset: 0x50C Clear individual bits in GPIO port Read: reads value of OUT register. Bit number ID Reset 0x00000000 ID AccessField A-f RW PIN[i] (i=0..31) 6.8.2.4 IN Address offset: 0x510 Low High Low High Set Low High Clear 0 1 0 1 1 0 1 1 4452_021 v1.3 142 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pin i Read: pin driver is low Read: pin driver is high Write: a '1' sets the pin low; a '0' has no effect Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Low High Description Pin i Pin input is low Pin input is high 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Input Output Description Pin i Pin set as input Pin set as output 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Input Output Set Set as output pin i Read: pin set as input Read: pin set as output Write: a '1' sets pin to output; a '0' has no effect Read GPIO port Bit number ID Reset 0x00000000 ID AccessField A-f R PIN[i] (i=0..31) 6.8.2.5 DIR Address offset: 0x514 Direction of GPIO pins Bit number ID Reset 0x00000000 ID AccessField A-f RW PIN[i] (i=0..31) 6.8.2.6 DIRSET Address offset: 0x518 DIR set register Read: reads value of DIR register. Bit number ID Reset 0x00000000 ID AccessField A-f RW PIN[i] (i=0..31) 6.8.2.7 DIRCLR Address offset: 0x51C DIR clear register Read: reads value of DIR register. 0 1 0 1 0 1 1 4452_021 v1.3 143 Bit number ID Reset 0x00000000 ID AccessField A-f RW PIN[i] (i=0..31) 6.8.2.8 LATCH Address offset: 0x520 Bit number ID Reset 0x00000000 ID AccessField A-f RW PIN[i] (i=0..31) Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Input Output Clear Set as input pin i Read: pin set as input Read: pin set as output Write: a '1' sets pin to input; a '0' has no effect 0 1 1 0 1 0 1 0 1 0 1 Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Status on whether PINi has met criteria set in PIN_CNFi.SENSE register. Write '1' to clear. Criteria has not been met Criteria has been met NotLatched Latched 6.8.2.9 DETECTMODE Address offset: 0x524 Select between default DETECT signal behavior and LDETECT mode Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW DETECTMODE Select between default DETECT signal behavior and A Default LDETECT LDETECT mode DETECT directly connected to PIN DETECT signals Use the latched LDETECT behavior 6.8.2.10 PIN_CNF[n] (n=0..31) Address offset: 0x700 + (n 0x4) Configuration of GPIO pins Bit number ID ID A Reset 0x00000002 AccessField RW DIR B RW INPUT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E E D D D C C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value ID Value Description Input Output Connect Disconnect Pin direction. Same physical register as DIR register Configure pin as an input pin Configure pin as an output pin Connect or disconnect input buffer Connect input buffer Disconnect input buffer 4452_021 v1.3 144 Bit number ID ID C Reset 0x00000002 AccessField RW PULL D RW DRIVE E RW SENSE VIH VIL VOH,SD VOH,HDH VOH,HDL VOL,SD VOL,HDH VOL,HDL IOL,SD IOL,HDH IOL,HDL IOH,SD IOH,HDH IOH,HDL Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E E D D D C C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value ID Value Description Disabled Pulldown Pullup S0S1 H0S1 S0H1 H0H1 D0S1 D0H1 S0D1 H0D1 Disabled High Low 0 1 3 0 1 2 3 4 5 6 7 0 2 3 Pull configuration No pull Pull down on pin Pull up on pin Drive configuration Standard '0', standard '1'

High drive '0', standard '1'

Standard '0', high drive '1'

High drive '0', high 'drive '1''

Disconnect '0' standard '1' (normally used for wired-or Disconnect '0', high drive '1' (normally used for wired-or Standard '0'. disconnect '1' (normally used for wired-and High drive '0', disconnect '1' (normally used for wired-and connections) connections) connections) connections) Pin sensing mechanism Disabled Sense for high level Sense for low level Symbol Description Typ. Max. Units 6.8.3 Electrical specification 6.8.3.1 GPIO Electrical Specification Input high voltage Input low voltage Output high voltage, standard drive, 0.5 mA, VDD 1.7 Output high voltage, high drive, 5 mA, VDD 2.7 V Output high voltage, high drive, 3 mA, VDD 1.7 V Output low voltage, standard drive, 0.5 mA, VDD 1.7 Output low voltage, high drive, 5 mA, VDD 2.7 V Output low voltage, high drive, 3 mA, VDD 1.7 V Current at VSS+0.4 V, output set low, standard drive, VDD Min. 0.7 x VDD VSS VDD - 0.4 VDD - 0.4 VDD - 0.4 VSS VSS VSS 1 6 3 1 6 3 2 2 9 VDD 0.3 x VDD VDD VDD VDD 4 4 VSS + 0.4 V VSS + 0.4 V VSS + 0.4 V V V V V V mA mA mA mA mA Current at VSS+0.4 V, output set low, high drive, VDD 2.7 V 10 15 Current at VSS+0.4 V, output set low, high drive, VDD 1.7 V Current at VDD-0.4 V, output set high, standard drive, VDD Current at VDD-0.4 V, output set high, high drive, VDD 2.7 14 mA Current at VDD-0.4 V, output set high, high drive, VDD 1.7 1.7 1.7 V V 4452_021 v1.3 145 Description Min. Typ. Max. Units Symbol tRF,15pF tRF,25pF tRF,50pF tHRF,15pF tHRF,25pF tHRF,50pF RPU RPD CPAD Symbol CPAD_NFC INFC_LEAK Rise/fall time, standard drive mode, 10-90%, 15 pF load14 Rise/fall time, standard drive mode, 10-90%, 25 pF load14 Rise/fall time, standard drive mode, 10-90%, 50 pF load14 Rise/Fall time, high drive mode, 10-90%, 15 pF load14 Rise/Fall time, high drive mode, 10-90%, 25 pF load14 Rise/Fall time, high drive mode, 10-90%, 50 pF load14 Pull-up resistance Pull-down resistance Pad capacitance 6.8.3.2 NFC Pads Electrical Specification Description Pad capacitance on NFC pads states Leakage current between NFC pads when driven to different INFC_LEAK_EXT Leakage current between NFC pads when driven to different states, extended temperature range Peripherals 11 11 9 13 25 4 5 8 13 13 3 4 1 1 16 16 10 15 ns ns ns ns ns ns k k pF pF A A Min. Typ. Max. Units 6.9 GPIOTE GPIO tasks and events The GPIO tasks and events (GPIOTE) module provides functionality for accessing GPIO pins using tasks and events. Each GPIOTE channel can be assigned to one pin. A GPIOTE block enables GPIOs to generate events on pin state change which can be used to carry out tasks through the PPI system. A GPIO can also be driven to change state on system events using the PPI system. Tasks and events are briefly introduced in Peripheral interface on page 96, and GPIO is described in more detail in GPIO General purpose input/output on page 138. Low power detection of pin state changes is possible when in System ON or System OFF. Number of GPIOTE channels 8 Table 41: GPIOTE properties Up to three tasks can be used in each GPIOTE channel for performing write operations to a pin. Two tasks are fixed (SET and CLR), and one (OUT) is configurable to perform following operations:

An event can be generated in each GPIOTE channel from one of the following input conditions:

Instance GPIOTE Set Clear Toggle Rising edge Falling edge Any change 14 Rise and fall times based on simulations 4452_021 v1.3 146 Peripherals 6.9.1 Pin events and tasks The GPIOTE module has a number of tasks and events that can be configured to operate on individual GPIO pins. The tasks SET[n], CLR[n], and OUT[n] can write to individual pins, and events IN[n] can be generated from input changes of individual pins. The SET task will set the pin selected in GPIOTE.CONFIG[n].PSEL to high. The CLR task will set the pin low. The effect of the OUT task on the pin is configurable in CONFIG[n].POLARITY. It can set the pin high, set it low, or toggle it. Tasks and events are configured using the CONFIG[n] registers. One CONFIG[n] register is associated with a set of SET[n], CLR[n], and OUT[n] tasks and IN[n] events. As long as a SET[n], CLR[n], and OUT[n] task or an IN[n] event is configured to control pin n, the pin's output value will only be updated by the GPIOTE module. The pin's output value, as specified in the GPIO, will be ignored as long as the pin is controlled by GPIOTE. Attempting to write to the pin as a normal GPIO pin will have no effect. When the GPIOTE is disconnected from a pin, the associated pin gets the output and configuration values specified in the GPIO module, see MODE field in CONFIG[n] register. When conflicting tasks are triggered simultaneously (i.e. during the same clock cycle) in one channel, the priority of the tasks is as described in the following table. Priority 1 2 3 Task OUT CLR SET Table 42: Task priorities When setting the CONFIG[n] registers, MODE=Disabled does not have the same effect as MODE=Task and POLARITY=None. In the latter case, a CLR or SET task occurring at the exact same time as OUT will end up with no change on the pin, based on the priorities described in the table above. When a GPIOTE channel is configured to operate on a pin as a task, the initial value of that pin is configured in the OUTINIT field of CONFIG[n]. 6.9.2 Port event PORT is an event that can be generated from multiple input pins using the GPIO DETECT signal. The event will be generated on the rising edge of the DETECT signal. See GPIO General purpose input/

output on page 138 for more information about the DETECT signal. The GPIO DETECT signal will not wake the system up again if the system is put into System ON IDLE while the DETECT signal is high. Clear all DETECT sources before entering sleep. If the LATCH register is used as a source, a new rising edge will be generated on DETECT if any bit in LATCH is still high after clearing all or part of the register. This could occur if one of the PINx.DETECT signals is still high, for example. See Pin configuration on page 139 for more information. Setting the system to System OFF while DETECT is high will cause a wakeup from System OFF reset. This feature is always enabled even if the peripheral itself appears to be IDLE, meaning no clocks or other power intensive infrastructure have to be requested to keep this feature enabled. This feature can therefore be used to wake up the CPU from a WFI or WFE type sleep in System ON when all peripherals and the CPU are idle, meaning the lowest power consumption in System ON mode. In order to prevent spurious interrupts from the PORT event while configuring the sources, the following must be performed:

4452_021 v1.3 147 Peripherals 1. Disable interrupts on the PORT event (through INTENCLR.PORT). 2. Configure the sources (PIN_CNF[n].SENSE). 3. Clear any potential event that could have occurred during configuration (write '0' to EVENTS_PORT). 4. Enable interrupts (through INTENSET.PORT). 6.9.3 Tasks and events pin configuration Each GPIOTE channel is associated with one physical GPIO pin through the CONFIG.PSEL field. When Event mode is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will be configured as an input, overriding the DIR setting in GPIO. Similarly, when Task mode is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will be configured as an output overriding the DIR setting and OUT value in GPIO. When Disabled is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will use its configuration from the PIN[n].CNF registers in GPIO. Note: A pin can only be assigned to one GPIOTE channel at a time. Failing to do so may result in unpredictable behavior. 6.9.4 Registers Base address Peripheral Description Configuration 0x40006000 GPIOTE GPIO tasks and events Instance GPIOTE Table 43: Instances Register TASKS_OUT[0]

Offset 0x000 Description Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in TASKS_OUT[1]

0x004 Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is configured in TASKS_OUT[2]

0x008 Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is configured in TASKS_OUT[3]

0x00C Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is configured in TASKS_OUT[4]

0x010 Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is configured in TASKS_OUT[5]

0x014 Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is configured in TASKS_OUT[6]

0x018 Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is configured in TASKS_OUT[7]

0x01C Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is configured in CONFIG[0].POLARITY. CONFIG[1].POLARITY. CONFIG[2].POLARITY. CONFIG[3].POLARITY. CONFIG[4].POLARITY. CONFIG[5].POLARITY. CONFIG[6].POLARITY. CONFIG[7].POLARITY. TASKS_SET[0]

TASKS_SET[1]

TASKS_SET[2]

TASKS_SET[3]

TASKS_SET[4]

TASKS_SET[5]

TASKS_SET[6]

TASKS_SET[7]

TASKS_CLR[0]

TASKS_CLR[1]

TASKS_CLR[2]

0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x060 0x064 0x068 Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high. Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is to set it high. Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is to set it high. Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is to set it high. Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is to set it high. Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is to set it high. Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is to set it high. Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is to set it high. Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low. Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is to set it low. Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is to set it low. 4452_021 v1.3 148 Peripherals Register TASKS_CLR[3]

TASKS_CLR[4]

TASKS_CLR[5]

TASKS_CLR[6]

TASKS_CLR[7]

EVENTS_IN[0]

EVENTS_IN[1]

EVENTS_IN[2]

EVENTS_IN[3]

EVENTS_IN[4]

EVENTS_IN[5]

EVENTS_IN[6]

EVENTS_IN[7]

EVENTS_PORT INTENSET INTENCLR CONFIG[0]

CONFIG[1]

CONFIG[2]

CONFIG[3]

CONFIG[4]

CONFIG[5]

CONFIG[6]

CONFIG[7]

Offset 0x06C 0x070 0x074 0x078 0x07C 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x17C 0x304 0x308 0x510 0x514 0x518 0x51C 0x520 0x524 0x528 0x52C Description Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is to set it low. Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is to set it low. Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is to set it low. Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is to set it low. Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is to set it low. Event generated from pin specified in CONFIG[0].PSEL Event generated from pin specified in CONFIG[1].PSEL Event generated from pin specified in CONFIG[2].PSEL Event generated from pin specified in CONFIG[3].PSEL Event generated from pin specified in CONFIG[4].PSEL Event generated from pin specified in CONFIG[5].PSEL Event generated from pin specified in CONFIG[6].PSEL Event generated from pin specified in CONFIG[7].PSEL Event generated from multiple input GPIO pins with SENSE mechanism enabled Enable interrupt Disable interrupt Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event Table 44: Register overview 6.9.4.1 TASKS_OUT[n] (n=0..7) Address offset: 0x000 + (n 0x4) Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_OUT Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. Trigger 1 Trigger task 6.9.4.2 TASKS_SET[n] (n=0..7) Address offset: 0x030 + (n 0x4) Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_SET Task for writing to pin specified in CONFIG[n].PSEL. Action Trigger 1 Trigger task on pin is to set it high. ID ID A ID ID A A A 4452_021 v1.3 149 Peripherals 6.9.4.3 TASKS_CLR[n] (n=0..7) Address offset: 0x060 + (n 0x4) Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_CLR Task for writing to pin specified in CONFIG[n].PSEL. Action Trigger 1 Trigger task on pin is to set it low. 6.9.4.4 EVENTS_IN[n] (n=0..7) Address offset: 0x100 + (n 0x4) Event generated from pin specified in CONFIG[n].PSEL Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_IN Event generated from pin specified in CONFIG[n].PSEL NotGenerated Generated Event not generated Event generated 6.9.4.5 EVENTS_PORT Address offset: 0x17C Event generated from multiple input GPIO pins with SENSE mechanism enabled Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_PORT Event generated from multiple input GPIO pins with SENSE NotGenerated Generated mechanism enabled Event not generated Event generated 0 1 0 1 ID ID A ID ID A ID ID A A A A 6.9.4.6 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.3 150 Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Bit number ID Reset 0x00000000 ID AccessField A-H RW IN[i] (i=0..7) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event IN[i]

Peripherals H G F E D C B A I RW PORT Write '1' to enable interrupt for event PORT 6.9.4.7 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID Reset 0x00000000 ID AccessField A-H RW IN[i] (i=0..7) Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event IN[i]

I RW PORT Write '1' to disable interrupt for event PORT 6.9.4.8 CONFIG[n] (n=0..7) Address offset: 0x510 + (n 0x4) Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event Bit number ID ID A Reset 0x00000000 AccessField RW MODE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E D D C B B B B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Disabled Event Description Mode GPIOTE module. Event mode Disabled. Pin specified by PSEL will not be acquired by the The pin specified by PSEL will be configured as an input and the IN[n] event will be generated if operation specified in POLARITY occurs on the pin. I 1 0 1 1 0 1 I 1 0 1 1 0 1 0 1 4452_021 v1.3 151 Bit number ID Reset 0x00000000 ID AccessField B C D RW PSEL RW PORT RW POLARITY E RW OUTINIT Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E D D C B B B B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Task Value 3 Description Task mode The GPIO specified by PSEL will be configured as an output and triggering the SET[n], CLR[n] or OUT[n] task will perform the operation specified by POLARITY on the pin. When enabled as a task the GPIOTE module will acquire the pin and the pin can no longer be written as a regular output pin from the GPIO module.

[0..31]

GPIO number associated with SET[n], CLR[n], and OUT[n]

tasks and IN[n] event

[0..1]

Port number When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode:

Operation on input that shall trigger IN[n] event. Task mode: No effect on pin from OUT[n] task. Event mode:

no IN[n] event generated on pin activity. Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. Task mode: Clear pin from OUT[n] task. Event mode:

Generate IN[n] event when falling edge on pin. Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. Task mode: Initial value of pin before task triggering is low Task mode: Initial value of pin before task triggering is high None LoToHi HiToLo Toggle Low High 0 1 2 3 0 1 6.9.5 Electrical specification 6.10 I2S Inter-IC sound interface The I2S (Inter-IC Sound) module, supports the original two-channel I2S format, and left or right-aligned formats. It implements EasyDMA for sample transfer directly to and from RAM without CPU intervention. The I2S peripheral has the following main features:

Master and Slave mode Simultaneous bi-directional (TX and RX) audio streaming Original I2S and left- or right-aligned format 8, 16 and 24-bit sample width Low-jitter Master Clock generator Various sample rates 4452_021 v1.3 152 Peripherals PSEL.MCK PSEL.LRCK PSEL.SCK PSEL.SDIN PSEL.SDOUT CONFIG.MCKEN I2S CONFIG.MCKFREQ Master clock generator MCK CONFIG.RATIO Div Div CONFIG.FORMAT L R C K S C K S D N I S D O U T CONFIG.ALIGN Serial tranceiever CONFIG.MODE TXD.PTR RXD.PTR RXTXD.MAXCNT EasyDMA RAM Figure 44: I2S master 6.10.1 Mode The I2S protocol specification defines two modes of operation, Master and Slave. The I2S mode decides which of the two sides (Master or Slave) shall provide the clock signals LRCK and SCK, and these signals are always supplied by the Master to the Slave. 6.10.2 Transmitting and receiving The I2S module supports both transmission (TX) and reception (RX) of serial data. In both cases the serial data is shifted synchronously to the clock signals SCK and LRCK. TX data is written to the SDOUT pin on the falling edge of SCK, and RX data is read from the SDIN pin on the rising edge of SCK. The most significant bit (MSB) is always transmitted first. TX and RX are available in both Master and Slave modes and can be enabled/disabled independently in the CONFIG.TXEN on page 166 and CONFIG.RXEN on page 166. Transmission and/or reception is started by triggering the START task. When started and transmission is enabled (in CONFIG.TXEN on page 166), the TXPTRUPD event will be generated for every RXTXD.MAXCNT on page 169 number of transmitted data words (containing one or more samples). Similarly, when started and reception is enabled (in CONFIG.RXEN on page 166), the RXPTRUPD event will be generated for every RXTXD.MAXCNT on page 169 received data words. 4452_021 v1.3 153 Peripherals RXTXD.MAXCNT RXTXD.MAXCNT Left 0 Right 0 Left 1 RIght 1 Left 2 Right 2 Left 3 Right 3 Left 4 A B A B A B A B C D C D C D C D E F T U O D S I N D S K C S K C R L U P C D P U R T P X T D P U R T P X R T R A T S A

R T P D X T

. B

R T P D X R

. C

R T P D X T

. D

R T P D X R

. D P U R T P X T D P U R T P X R E

R T P D X T

. F

R T P D X R

. D P U R T P X T D P U R T P X R G

R T P D X T

. H

R T P D X R

. Figure 45: Transmitting and receiving. CONFIG.FORMAT = Aligned, CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo, RXTXD.MAXCNT = 1. 6.10.3 Left right clock (LRCK) The Left Right Clock (LRCK), often referred to as "word clock", "sample clock" or "word select" in I2S context, is the clock defining the frames in the serial bit streams sent and received on SDOUT and SDIN, respectively. In I2S mode, each frame contains one left and right sample pair, with the left sample being transferred during the low half period of LRCK followed by the right sample being transferred during the high period of LRCK. In Aligned mode, each frame contains one left and right sample pair, with the left sample being transferred during the high half period of LRCK followed by the right sample being transferred during the low period of LRCK. Consequently, the LRCK frequency is equivalent to the audio sample rate. When operating in Master mode, the LRCK is generated from the MCK, and the frequency of LRCK is then given as:

LRCK = MCK / CONFIG.RATIO LRCK always toggles around the falling edge of the serial clock SCK. 6.10.4 Serial clock (SCK) The serial clock (SCK), often referred to as the serial bit clock, pulses once for each data bit being transferred on the serial data lines SDIN and SDOUT. When operating in Master mode the SCK is generated from the MCK, and the frequency of SCK is then given as:

SCK = 2 * LRCK * CONFIG.SWIDTH The falling edge of the SCK falls on the toggling edge of LRCK. When operating in Slave mode SCK is provided by the external I2S master. 4452_021 v1.3 154 Peripherals 6.10.5 Master clock (MCK) The master clock (MCK) is the clock from which LRCK and SCK are derived when operating in Master mode. The MCK is generated by an internal MCK generator. This generator always needs to be enabled when in Master mode, but the generator can also be enabled when in Slave mode. Enabling the generator when in slave mode can be useful in the case where the external Master is not able to generate its own master clock. The MCK generator is enabled/disabled in the register CONFIG.MCKEN on page 166, and the generator is started or stopped by the START or STOP tasks. In Master mode the LRCK and the SCK frequencies are closely related, as both are derived from MCK and set indirectly through CONFIG.RATIO on page 167 and CONFIG.SWIDTH on page 168. When configuring these registers, the user is responsible for fulfilling the following requirements:

1. SCK frequency can never exceed the MCK frequency, which can be formulated as:

CONFIG.RATIO >= 2 * CONFIG.SWIDTH 2. The MCK/LRCK ratio shall be a multiple of 2 * CONFIG.SWIDTH, which can be formulated as:

Integer = (CONFIG.RATIO / (2 * CONFIG.SWIDTH)) The MCK signal can be routed to an output pin (specified in PSEL.MCK) to supply external I2S devices that require the MCK to be supplied from the outside. When operating in Slave mode, the I2S module does not use the MCK and the MCK generator does not need to be enabled. RATIO =

MCK LRCK MCK LRCK SCK SWIDTH Figure 46: Relation between RATIO, MCK and LRCK. Desired LRCK

[Hz]

CONFIG.SWIDTHCONFIG.RATIO CONFIG.MCKFREQMCK [Hz]

LRCK [Hz]

LRCK error

16000 16000 16000 32000 32000 44100 44100 16Bit 16Bit 16Bit 16Bit 16Bit 16Bit 16Bit 32X 64X 256X 32X 64X 32X 64X 32MDIV63 507936.5 15873.0 32MDIV31 1032258.1 16129.0 32MDIV8 4000000.0 15625.0 32MDIV31 1032258.1 32258.1 32MDIV16 2000000.0 31250.0 32MDIV23 1391304.3 43478.3 32MDIV11 2909090.9 45454.5

-0.8 0.8

-2.3 0.8

-2.3

-1.4 3.1 Table 45: Configuration examples 6.10.6 Width, alignment and format The CONFIG.SWIDTH register primarily defines the sample width of the data written to memory. In master mode, it then also sets the amount of bits per frame. In Slave mode it controls padding/trimming if required. Left, right, transmitted, and received samples always have the same width. The CONFIG.FORMAT 4452_021 v1.3 155 Peripherals register specifies the position of the data frames with respect to the LRCK edges in both Master and Slave modes. When using I2S format, the first bit in a half-frame (containing one left or right sample) gets sampled on the second rising edge of the SCK after a LRCK edge. When using Aligned mode, the first bit in a half-frame gets sampled on the first rising edge of SCK following a LRCK edge. For data being received on SDIN the sample value can be either right or left-aligned inside a half-frame, as specified in CONFIG.ALIGN on page 168. CONFIG.ALIGN on page 168 affects only the decoding of the incoming samples (SDIN), while the outgoing samples (SDOUT) are always left-aligned (or justified). When using left-alignment, each half-frame starts with the MSB of the sample value (both for data being sent on SDOUT and received on SDIN). When using right-alignment, each half-frame of data being received on SDIN ends with the LSB of the sample value, while each half-frame of data being sent on SDOUT starts with the MSB of the sample value

(same as for left-alignment). In Master mode, the size of a half-frame (in number of SCK periods) equals the sample width (in number of bits), and in this case the alignment setting does not care as each half-frame in any case will start with the MSB and end with the LSB of the sample value. In slave mode, however, the sample width does not need to equal the frame size. This means you might have extra or fewer SCK pulses per half-frame than what the sample width specified in CONFIG.SWIDTH requires. In the case where we use left-alignment and the number of SCK pulses per half-frame is higher than the sample width, the following will apply:

For data received on SDIN, all bits after the LSB of the sample value will be discarded. For data sent on SDOUT, all bits after the LSB of the sample value will be 0. In the case where we use left-alignment and the number of SCK pulses per frame is lower than the sample width, the following will apply:

Data sent and received on SDOUT and SDIN will be truncated with the LSBs being removed first. In the case where we use right-alignment and the number of SCK pulses per frame is higher than the sample width, the following will apply:

For data received on SDIN, all bits before the MSB of the sample value will be discarded. For data sent on SDOUT, all bits after the LSB of the sample value will be 0 (same behavior as for left-

alignment). memory. alignment). In the case where we use right-alignment and the number of SCK pulses per frame is lower than the sample width, the following will apply:

Data received on SDIN will be sign-extended to "sample width" number of bits before being written to Data sent on SDOUT will be truncated with the LSBs being removed first (same behavior as for left-

frame left right left LRCK SCK SDIN or SDOUT Figure 47: I2S format. CONFIG.SWIDTH equalling half-frame size. 4452_021 v1.3 156 Peripherals frame left right left LRCK SCK SDATA Figure 48: Aligned format. CONFIG.SWIDTH equalling half-frame size. 6.10.7 EasyDMA The I2S module implements EasyDMA for accessing internal Data RAM without CPU intervention. The source and destination pointers for the TX and RX data are configured in TXD.PTR on page 169 and RXD.PTR on page 169. The memory pointed to by these pointers will only be read or written when TX or RX are enabled in CONFIG.TXEN on page 166 and CONFIG.RXEN on page 166. The addresses written to the pointer registers TXD.PTR on page 169 and RXD.PTR on page 169 are double-buffered in hardware, and these double buffers are updated for every RXTXD.MAXCNT on page 169 words (containing one or more samples) read/written from/to memory. The events TXPTRUPD and RXPTRUPD are generated whenever the TXD.PTR and RXD.PTR are transferred to these double buffers. If TXD.PTR on page 169 is not pointing to the Data RAM region when transmission is enabled, or RXD.PTR on page 169 is not pointing to the Data RAM region when reception is enabled, an EasyDMA transfer may result in a HardFault and/or memory corruption. See Memory on page 19 for more information about the different memory regions. Due to the nature of I2S, where the number of transmitted samples always equals the number of received samples (at least when both TX and RX are enabled), one common register RXTXD.MAXCNT on page 169 is used for specifying the sizes of these two memory buffers. The size of the buffers is specified in a number of 32-bit words. Such a 32-bit memory word can either contain four 8-bit samples, two 16-bit samples or one right-aligned 24-bit sample sign extended to 32 bit. In stereo mode (CONFIG.CHANNELS=Stereo), the samples are stored as "left and right sample pairs" in memory. Figure Memory mapping for 8 bit stereo. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo. on page 158, Memory mapping for 16 bit stereo. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Stereo. on page 158 and Memory mapping for 24 bit stereo. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS =

Stereo. on page 159 show how the samples are mapped to memory in this mode. The mapping is valid for both RX and TX. In mono mode (CONFIG.CHANNELS=Left or Right), RX sample from only one channel in the frame is stored in memory, the other channel sample is ignored. Illustrations Memory mapping for 8 bit mono. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left. on page 158, Memory mapping for 16 bit mono, left channel only. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Left. on page 158 and Memory mapping for 24 bit mono, left channel only. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Left. on page 159 show how RX samples are mapped to memory in this mode. For TX, the same outgoing sample read from memory is transmitted on both left and right in a frame, resulting in a mono output stream. 4452_021 v1.3 157 Peripherals Figure 49: Memory mapping for 8 bit stereo. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo. 31 24 23 16 15 8 7 0 Right sample 1 Left sample 1 Right sample 0 Left sample 0 Right sample 3 Left sample 3 Right sample 2 Left sample 2 x.PTR x.PTR + 4 x.PTR + (n*2) - 4 Right sample n-1 Left sample n-1 Right sample n-2 Left sample n-2 31 24 23 16 15 8 7 0 Left sample 3 Left sample 2 Left sample 1 Left sample 0 Left sample 7 Left sample 6 Left sample 5 Left sample 4 x.PTR x.PTR + 4 x.PTR + n - 4 Left sample n-1 Left sample n-2 Left sample n-3 Left sample n-4 31 16 15 x.PTR Right sample 0 Left sample 0 x.PTR + 4 Right sample 1 Left sample 1 0 0 31 16 15 x.PTR Left sample 1 Left sample 0 x.PTR + 4 Left sample 3 Left sample 2 x.PTR + (n*2) - 4 Left sample n - 1 Left sample n - 2 Figure 52: Memory mapping for 16 bit mono, left channel only. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Left. Figure 50: Memory mapping for 8 bit mono. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left. x.PTR + (n*4) - 4 Right sample n - 1 Left sample n - 1 Figure 51: Memory mapping for 16 bit stereo. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Stereo. 4452_021 v1.3 158 Peripherals Figure 53: Memory mapping for 24 bit stereo. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Stereo. 31 23 x.PTR Sign ext. Left sample 0 x.PTR + 4 Sign ext. Right sample 0 x.PTR + (n*8) - 8 Sign ext. Left sample n - 1 x.PTR + (n*8) - 4 Sign ext. Right sample n - 1 31 23 x.PTR Sign ext. Left sample 0 x.PTR + 4 Sign ext. Left sample 1 0 0 x.PTR + (n*4) - 4 Sign ext. Left sample n - 1 Figure 54: Memory mapping for 24 bit mono, left channel only. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Left. 6.10.8 Module operation Described here is a typical operating procedure for the I2S module. 4452_021 v1.3 159 Peripherals 1. Configure the I2S module using the CONFIG registers

// Enable reception NRF_I2S->CONFIG.RXEN = (I2S_CONFIG_RXEN_RXEN_Enabled <<

I2S_CONFIG_RXEN_RXEN_Pos);

// Enable transmission NRF_I2S->CONFIG.TXEN = (I2S_CONFIG_TXEN_TXEN_Enabled <<

I2S_CONFIG_TXEN_TXEN_Pos);

// Enable MCK generator NRF_I2S->CONFIG.MCKEN = (I2S_CONFIG_MCKEN_MCKEN_Enabled <<

I2S_CONFIG_MCKEN_MCKEN_Pos);

// MCKFREQ = 4 MHz

// Ratio = 256 NRF_I2S->CONFIG.MCKFREQ = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 <<

I2S_CONFIG_MCKFREQ_MCKFREQ_Pos;

NRF_I2S->CONFIG.RATIO = I2S_CONFIG_RATIO_RATIO_256X <<

I2S_CONFIG_RATIO_RATIO_Pos;

// MCKFREQ = 4 MHz and Ratio = 256 gives sample rate = 15.625 ks/s

// Sample width = 16 bit NRF_I2S->CONFIG.SWIDTH = I2S_CONFIG_SWIDTH_SWIDTH_16Bit <<

I2S_CONFIG_SWIDTH_SWIDTH_Pos;

// Alignment = Left NRF_I2S->CONFIG.ALIGN = I2S_CONFIG_ALIGN_ALIGN_Left <<

I2S_CONFIG_ALIGN_ALIGN_Pos;

// Format = I2S

// Use stereo NRF_I2S->CONFIG.FORMAT = I2S_CONFIG_FORMAT_FORMAT_I2S <<

I2S_CONFIG_FORMAT_FORMAT_Pos;

NRF_I2S->CONFIG.CHANNELS = I2S_CONFIG_CHANNELS_CHANNELS_Stereo <<

I2S_CONFIG_CHANNELS_CHANNELS_Pos;

2. Map IO pins using the PINSEL registers

// MCK routed to pin 0 NRF_I2S->PSEL.MCK = (0 << I2S_PSEL_MCK_PIN_Pos) |

(I2S_PSEL_MCK_CONNECT_Connected <<

// SCK routed to pin 1 NRF_I2S->PSEL.SCK = (1 << I2S_PSEL_SCK_PIN_Pos) |

(I2S_PSEL_SCK_CONNECT_Connected <<

I2S_PSEL_MCK_CONNECT_Pos);

I2S_PSEL_SCK_CONNECT_Pos);

// LRCK routed to pin 2 NRF_I2S->PSEL.LRCK = (2 << I2S_PSEL_LRCK_PIN_Pos) |

(I2S_PSEL_LRCK_CONNECT_Connected <<

I2S_PSEL_LRCK_CONNECT_Pos);

// SDOUT routed to pin 3 NRF_I2S->PSEL.SDOUT = (3 << I2S_PSEL_SDOUT_PIN_Pos) |

(I2S_PSEL_SDOUT_CONNECT_Connected <<

I2S_PSEL_SDOUT_CONNECT_Pos);

// SDIN routed on pin 4 NRF_I2S->PSEL.SDIN = (4 << I2S_PSEL_SDIN_PIN_Pos) |

(I2S_PSEL_SDIN_CONNECT_Connected <<

I2S_PSEL_SDIN_CONNECT_Pos);

4452_021 v1.3 160 3. Configure TX and RX data pointers using the TXD, RXD and RXTXD registers Peripherals 6. Handle received and transmitted data when receiving the TXPTRUPD and RXPTRUPD events NRF_I2S->TXD.PTR = my_tx_buf;

NRF_I2S->RXD.PTR = my_rx_buf;

NRF_I2S->TXD.MAXCNT = MY_BUF_SIZE;

4. Enable the I2S module using the ENABLE register NRF_I2S->ENABLE = 1;

5. Start audio streaming using the START task NRF_I2S->TASKS_START = 1;

if(NRF_I2S->EVENTS_TXPTRUPD != 0) NRF_I2S->TXD.PTR = my_next_tx_buf;

NRF_I2S->EVENTS_TXPTRUPD = 0;

if(NRF_I2S->EVENTS_RXPTRUPD != 0) NRF_I2S->RXD.PTR = my_next_rx_buf;

NRF_I2S->EVENTS_RXPTRUPD = 0;

6.10.9 Pin configuration The MCK, SCK, LRCK, SDIN and SDOUT signals associated with the I2S module are mapped to physical pins according to the pin numbers specified in the PSEL.x registers. These pins are acquired whenever the I2S module is enabled through the register ENABLE on page 165. When a pin is acquired by the I2S module, the direction of the pin (input or output) will be configured automatically, and any pin direction setting done in the GPIO module will be overridden. The directions for the various I2S pins are shown below in GPIO configuration before enabling peripheral (master mode) on page 161 and GPIO configuration before enabling peripheral (slave mode) on page 162. To secure correct signal levels on the pins when the system is in OFF mode, and when the I2S module is disabled, these pins must be configured in the GPIO peripheral directly. I2S signal MCK LRCK SCK SDIN SDOUT I2S pin As specified in PSEL.MCK As specified in PSEL.LRCK As specified in PSEL.SCK Direction Output Output Output Output value Comment 0 0 0 0 As specified in PSEL.SDIN Input Not applicable As specified in PSEL.SDOUT Output Table 46: GPIO configuration before enabling peripheral (master mode) 4452_021 v1.3 161 Peripherals I2S signal MCK LRCK SCK SDIN SDOUT I2S pin Direction Output value Comment As specified in PSEL.MCK Output As specified in PSEL.LRCK As specified in PSEL.SCK As specified in PSEL.SDIN Input Input Input As specified in PSEL.SDOUT Output Not applicable Not applicable Not applicable 0 0 Table 47: GPIO configuration before enabling peripheral (slave mode) 6.10.10 Registers Base address Peripheral Instance Description Configuration 0x40025000 I2S I2S Inter-IC sound interface Table 48: Instances Description to be generated. Starts continuous I2S transfer. Also starts MCK generator when this is enabled. Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event EVENTS_RXPTRUPD 0x104 The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that Register TASKS_START TASKS_STOP EVENTS_STOPPED EVENTS_TXPTRUPD INTEN INTENSET INTENCLR ENABLE CONFIG.MODE CONFIG.RXEN CONFIG.TXEN CONFIG.MCKEN CONFIG.MCKFREQ CONFIG.RATIO CONFIG.SWIDTH CONFIG.ALIGN CONFIG.FORMAT CONFIG.CHANNELS RXD.PTR TXD.PTR PSEL.MCK PSEL.SCK PSEL.LRCK PSEL.SDIN PSEL.SDOUT Offset 0x000 0x004 0x108 0x114 0x300 0x304 0x308 0x500 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0x520 0x524 0x528 0x538 0x540 0x550 0x560 0x564 0x568 0x56C 0x570 are received on the SDIN pin. I2S transfer stopped. are sent on the SDOUT pin. Enable or disable interrupt Enable interrupt Disable interrupt Enable I2S module. I2S mode. Reception (RX) enable. Transmission (TX) enable. Master clock generator enable. Master clock generator frequency. MCK / LRCK ratio. Sample width. Frame format. Enable channels. Alignment of sample within a frame. Receive buffer RAM start address. Transmit buffer RAM start address. Pin select for MCK signal. Pin select for SCK signal. Pin select for LRCK signal. Pin select for SDIN signal. Pin select for SDOUT signal. Table 49: Register overview RXTXD.MAXCNT Size of RXD and TXD buffers. 4452_021 v1.3 162 Peripherals 6.10.10.1 TASKS_START Address offset: 0x000 Starts continuous I2S transfer. Also starts MCK generator when this is enabled. ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_START Starts continuous I2S transfer. Also starts MCK generator Trigger 1 Trigger task when this is enabled. 6.10.10.2 TASKS_STOP Address offset: 0x004 Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. Trigger 1 Trigger task 6.10.10.3 EVENTS_RXPTRUPD Address offset: 0x104 The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RXPTRUPD The RXD.PTR register has been copied to internal double-

buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. NotGenerated Generated 0 1 Event not generated Event generated A A A 6.10.10.4 EVENTS_STOPPED Address offset: 0x108 I2S transfer stopped. 4452_021 v1.3 163 ID ID A ID ID A ID ID B Peripherals A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_STOPPED NotGenerated Generated 0 1 I2S transfer stopped. Event not generated Event generated 6.10.10.5 EVENTS_TXPTRUPD Address offset: 0x114 The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_TXPTRUPD The TDX.PTR register has been copied to internal double-

buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. NotGenerated Generated Event not generated Event generated 0 1 0 1 0 1 0 1 6.10.10.6 INTEN Address offset: 0x300 Enable or disable interrupt 6.10.10.7 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F C B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW RXPTRUPD Enable or disable interrupt for event RXPTRUPD C RW STOPPED Enable or disable interrupt for event STOPPED F RW TXPTRUPD Enable or disable interrupt for event TXPTRUPD Disabled Enabled Disabled Enabled Disabled Enabled Disable Enable Disable Enable Disable Enable 4452_021 v1.3 164 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW RXPTRUPD Write '1' to enable interrupt for event RXPTRUPD Peripherals F C B C RW STOPPED Write '1' to enable interrupt for event STOPPED F RW TXPTRUPD Write '1' to enable interrupt for event TXPTRUPD Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled ID ID B ID ID B Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Disabled Enabled 6.10.10.8 INTENCLR Address offset: 0x308 Disable interrupt 6.10.10.9 ENABLE Address offset: 0x500 Enable I2S module. Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F C B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW RXPTRUPD Write '1' to disable interrupt for event RXPTRUPD C RW STOPPED Write '1' to disable interrupt for event STOPPED F RW TXPTRUPD Write '1' to disable interrupt for event TXPTRUPD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable I2S module. Disable Enable 4452_021 v1.3 165 Peripherals A A A 6.10.10.10 CONFIG.MODE Address offset: 0x504 I2S mode. Bit number ID ID A Reset 0x00000000 AccessField RW MODE Bit number ID ID A Reset 0x00000000 AccessField RW RXEN Bit number ID ID A Reset 0x00000001 AccessField RW TXEN 6.10.10.11 CONFIG.RXEN Address offset: 0x508 Reception (RX) enable. 6.10.10.12 CONFIG.TXEN Address offset: 0x50C Transmission (TX) enable. Master Slave Disabled Enabled Disabled Enabled 6.10.10.13 CONFIG.MCKEN Address offset: 0x510 Master clock generator enable. 0 1 0 1 0 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description I2S mode. Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Reception disabled and now data will be written to the Reception (RX) enable. RXD.PTR address. Reception enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Transmission disabled and now data will be read from the Transmission (TX) enable. RXD.TXD address. Transmission enabled. 4452_021 v1.3 166 Bit number ID ID A Reset 0x00000001 AccessField RW MCKEN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Disabled Enabled 0 1 Master clock generator enable. Master clock generator disabled and PSEL.MCK not connected(available as GPIO). Master clock generator running and MCK output on PSEL.MCK. Peripherals A 6.10.10.14 CONFIG.MCKFREQ Address offset: 0x514 Master clock generator frequency. Bit number ID ID A Reset 0x20000000 AccessField RW MCKFREQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description 32MDIV8 32MDIV10 32MDIV11 32MDIV15 32MDIV16 32MDIV21 32MDIV23 32MDIV30 32MDIV31 32MDIV32 32MDIV42 32MDIV63 32MDIV125 0x20000000 0x18000000 0x16000000 0x11000000 0x10000000 0x0C000000 0x0B000000 0x08800000 0x08400000 0x08000000 0x06000000 0x04100000 0x020C0000 Master clock generator frequency. 32 MHz / 8 = 4.0 MHz 32 MHz / 10 = 3.2 MHz 32 MHz / 11 = 2.9090909 MHz 32 MHz / 15 = 2.1333333 MHz 32 MHz / 16 = 2.0 MHz 32 MHz / 21 = 1.5238095 32 MHz / 23 = 1.3913043 MHz 32 MHz / 30 = 1.0666667 MHz 32 MHz / 31 = 1.0322581 MHz 32 MHz / 32 = 1.0 MHz 32 MHz / 42 = 0.7619048 MHz 32 MHz / 63 = 0.5079365 MHz 32 MHz / 125 = 0.256 MHz 6.10.10.15 CONFIG.RATIO Address offset: 0x518 MCK / LRCK ratio. Bit number ID ID A Reset 0x00000006 AccessField RW RATIO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Value ID Value Description 32X 48X 64X 96X 128X 192X 256X 384X 512X 0 1 2 3 4 5 6 7 8 MCK / LRCK ratio. LRCK = MCK / 32 LRCK = MCK / 48 LRCK = MCK / 64 LRCK = MCK / 96 LRCK = MCK / 128 LRCK = MCK / 192 LRCK = MCK / 256 LRCK = MCK / 384 LRCK = MCK / 512 4452_021 v1.3 167 Peripherals A A 6.10.10.16 CONFIG.SWIDTH Address offset: 0x51C Sample width. 8Bit 16Bit 24Bit Left Right 6.10.10.17 CONFIG.ALIGN Address offset: 0x520 Alignment of sample within a frame. 6.10.10.18 CONFIG.FORMAT Address offset: 0x524 Frame format. Bit number ID ID A Reset 0x00000001 AccessField RW SWIDTH Bit number ID ID A Reset 0x00000000 AccessField RW ALIGN Bit number ID ID A Reset 0x00000000 AccessField RW FORMAT 6.10.10.19 CONFIG.CHANNELS Address offset: 0x528 Enable channels. 0 1 2 0 1 0 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Sample width. 8 bit. 16 bit. 24 bit. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Alignment of sample within a frame. Left-aligned. Right-aligned. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value I2S Aligned Description Frame format. Original I2S format. Alternate (left- or right-aligned) format. 4452_021 v1.3 168 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW CHANNELS Stereo Left Right 0 1 2 Enable channels. Stereo. Left only. Right only. Peripherals A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Reset 0x00000000 AccessField RW PTR Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Reset 0x00000000 AccessField RW PTR Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. ID ID A ID ID A ID ID A 6.10.10.20 RXD.PTR Address offset: 0x538 Receive buffer RAM start address. 6.10.10.21 TXD.PTR Address offset: 0x540 Transmit buffer RAM start address. 6.10.10.22 RXTXD.MAXCNT Address offset: 0x550 Size of RXD and TXD buffers. Bit number ID ID A Reset 0x00000000 AccessField RW MAXCNT 6.10.10.23 PSEL.MCK Address offset: 0x560 Pin select for MCK signal. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Size of RXD and TXD buffers in number of 32 bit words. 4452_021 v1.3 169 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Peripherals B A A A A A C 1 0 C 1 0 C 1 0 ID A B C ID A B C ID A B C 6.10.10.24 PSEL.SCK Address offset: 0x564 Pin select for SCK signal. 6.10.10.25 PSEL.LRCK Address offset: 0x568 Pin select for LRCK signal. 6.10.10.26 PSEL.SDIN Address offset: 0x56C Pin select for SDIN signal. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 4452_021 v1.3 170 C 1 0 C 1 0 ID A B C ID A B C Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Peripherals B A A A A A 6.10.10.27 PSEL.SDOUT Address offset: 0x570 Pin select for SDOUT signal. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 6.10.11 Electrical specification 6.10.11.1 I2S timing specification Symbol tS_SDIN tH_SDIN tS_SDOUT tH_SDOUT tSCK_LRCK fMCK fLRCK fSCK DCCK Description SDIN setup time before SCK rising SDIN hold time after SCK rising SDOUT setup time after SCK falling SDOUT hold time before SCK falling SCLK falling to LRCK edge MCK frequency LRCK frequency SCK frequency Clock duty cycle (MCK, LRCK, SCK) Min. Typ. Max. Units 20 15 40 6

-5 45 ns ns ns ns ns kHz kHz kHz

0 5 4000 48 55 2000 tSCK_LRCK tS_SDIN tH_SDIN LRCK SCK SDIN SDOUT tH_SDOUT tS_SDOUT Figure 55: I2S timing diagram 4452_021 v1.3 171 Peripherals 6.11 LPCOMP Low-power comparator Low-power comparator (LPCOMP) compares an input voltage against a reference voltage. Listed here are the main features of LPCOMP:

0 - VDD input range Ultra-low power Eight input options (AIN0 to AIN7) Reference voltage options:

Two external analog reference inputs, or 15-level internal reference ladder (VDD/16) Optional hysteresis enable on input Can be used as a wakeup source from System OFF mode In System ON, the LPCOMP can generate separate events on rising and falling edges of a signal, or sample the current state of the pin as being above or below the selected reference. The block can be configured to use any of the analog inputs on the device. Additionally, the low-power comparator can be used as an analog wakeup source from System OFF or System ON. The comparator threshold can be programmed to a range of fractions of the supply voltage. Note: LPCOMP cannot be used (STARTed) at the same time as COMP. Only one comparator can be used at a time. EXTREFSEL REFSEL PSEL HYST RESULT AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 MUX VIN+

MUX

VIN-

Comparator core ANADETECT

(signal to POWER module) AIN0 AIN1 MUX AREF VDD*1/16 VDD*1/8 VDD*3/16 VDD*2/8 VDD*5/16 VDD*3/8 VDD*7/16 VDD*4/8 VDD*9/16 VDD*5/8 VDD*11/16 VDD*6/8 VDD*13/16 VDD*7/8 VDD*15/16 tasks S T A R T S T O P S A M P L E U P C R O S S D O W N R E A D Y events Figure 56: Low-power comparator The wakeup comparator (LPCOMP) compares an input voltage (VIN+), which comes from an analog input pin selected via the PSEL register, against a reference voltage (VIN-) selected via registers REFSEL on page 178 and EXTREFSEL. The PSEL, REFSEL, and EXTREFSEL registers must be configured before the LPCOMP is enabled through the ENABLE register. The HYST register allows enabling an optional hysteresis in the comparator core. This hysteresis shall prevent noise on the signal to create unwanted events. Figure below illustrates the effect of an active hysteresis on a noisy input signal. It is disabled by default, and shall be configured before enabling LPCOMP as well. 4452_021 v1.3 172 Peripherals t VIN+

VIN- + VHYST/2 VIN- - VHYST/2 Output ABOVE

(VIN+ > (VIN- + VHYST/2)) BELOW

(VIN+ < (VIN- - VHYST/2)) ABOVE

(VIN+ > (VIN- + VHYST/2)) BELOW Figure 57: Effect of hysteresis on a noisy input signal The LPCOMP is started by triggering the START task. After a startup time of tLPCOMP,STARTUP, the LPCOMP will generate a READY event to indicate that the comparator is ready to use and the output of the LPCOMP is correct. The LPCOMP will generate events every time VIN+ crosses VIN-. More specifically, every time VIN+ rises above VIN- (upward crossing) an UP event is generated along with a CROSS event. Every time VIN+ falls below VIN- (downward crossing), a DOWN event is generated along with a CROSS event. When hysteresis is enabled, the upward crossing level becomes (VIN- + VHYST/2), and the downward crossing level becomes (VIN- - VHYST/2). The LPCOMP is stopped by triggering the STOP task. LPCOMP will be operational in both System ON and System OFF mode when it is enabled through the ENABLE register. See POWER Power supply on page 58 for more information about power modes. Note that it is not allowed to go to System OFF when a READY event is pending to be generated. All LPCOMP registers, including ENABLE, are classified as retained registers when the LPCOMP is enabled. However, when the device wakes up from System OFF, all LPCOMP registers will be reset. The LPCOMP can wake up the system from System OFF by asserting the ANADETECT signal. The ANADETECT signal can be derived from any of the event sources that generate the UP, DOWN and CROSS events. In case of wakeup from System OFF, no events will be generated, only the ANADETECT signal. See the ANADETECT register (ANADETECT on page 179) for more information on how to configure the ANADETECT signal. The immediate value of the LPCOMP can be sampled to RESULT on page 177 by triggering the SAMPLE task. See RESETREAS on page 73 for more information on how to detect a wakeup from LPCOMP. 6.11.1 Shared resources The LPCOMP shares analog resources with SAADC. While it is possible to use the SAADC at the same time as the LPCOMP, selecting the same analog input pin for both modules is not supported. Additionally, LPCOMP shares registers and other resources with other peripherals that have the same ID as the LPCOMP. See Peripherals with shared ID on page 97 for more information. The LPCOMP peripheral shall not be disabled (by writing to the ENABLE register) before the peripheral has been stopped. Failing to do so may result in unpredictable behavior. 6.11.2 Pin configuration You can use the LPCOMP.PSEL register to select one of the analog input pins, AIN0 through AIN7, as the analog input pin for the LPCOMP. See GPIO General purpose input/output on page 138 for more information about the pins. Similarly, you can use EXTREFSEL on page 179 to select one of the analog reference input pins, AIN0 and AIN1, 4452_021 v1.3 173 Peripherals as input for AREF in case AREF is selected in EXTREFSEL on page 179. The selected analog pins will be acquired by the LPCOMP when it is enabled through ENABLE on page 178. 6.11.3 Registers Base address Peripheral 0x40013000 LPCOMP Instance LPCOMP Description Configuration Low power comparator Table 50: Instances Offset Description Start comparator Stop comparator 0x000 0x004 0x008 0x100 0x104 0x108 0x10C 0x200 0x304 0x308 0x400 0x500 0x504 0x508 0x50C 0x520 0x538 Sample comparator value LPCOMP is ready and output is valid Downward crossing Upward crossing Downward or upward crossing Shortcuts between local events and tasks Enable interrupt Disable interrupt Compare result Enable LPCOMP Input pin select Reference select External reference select Analog detect configuration Comparator hysteresis enable Table 51: Register overview Register TASKS_START TASKS_STOP TASKS_SAMPLE EVENTS_READY EVENTS_DOWN EVENTS_UP EVENTS_CROSS SHORTS INTENSET INTENCLR RESULT ENABLE PSEL REFSEL EXTREFSEL ANADETECT HYST ID ID A 6.11.3.1 TASKS_START Address offset: 0x000 Start comparator 6.11.3.2 TASKS_STOP Address offset: 0x004 Stop comparator 4452_021 v1.3 174 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_START Trigger 1 Start comparator Trigger task Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Trigger 1 Stop comparator Trigger task ID ID A ID ID A ID ID A ID ID A 6.11.3.3 TASKS_SAMPLE Address offset: 0x008 Sample comparator value 6.11.3.4 EVENTS_READY Address offset: 0x100 LPCOMP is ready and output is valid 0 1 0 1 6.11.3.5 EVENTS_DOWN Address offset: 0x104 Downward crossing 6.11.3.6 EVENTS_UP Address offset: 0x108 Upward crossing Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_SAMPLE Sample comparator value Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_READY LPCOMP is ready and output is valid NotGenerated Generated Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_DOWN NotGenerated Generated Downward crossing Event not generated Event generated A A A A 4452_021 v1.3 175 Peripherals A A ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_UP NotGenerated Generated Upward crossing Event not generated Event generated 6.11.3.7 EVENTS_CROSS Address offset: 0x10C Downward or upward crossing Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CROSS NotGenerated Generated Downward or upward crossing Event not generated Event generated 6.11.3.8 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW READY_SAMPLE Shortcut between event READY and task SAMPLE B RW READY_STOP Shortcut between event READY and task STOP C RW DOWN_STOP Shortcut between event DOWN and task STOP D RW UP_STOP Shortcut between event UP and task STOP E RW CROSS_STOP Shortcut between event CROSS and task STOP Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6.11.3.9 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.3 176 Bit number ID ID A Reset 0x00000000 AccessField RW READY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event READY Peripherals D C B A B RW DOWN Write '1' to enable interrupt for event DOWN C RW UP Write '1' to enable interrupt for event UP D RW CROSS Write '1' to enable interrupt for event CROSS 6.11.3.10 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW READY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event READY B RW DOWN Write '1' to disable interrupt for event DOWN C RW UP Write '1' to disable interrupt for event UP D RW CROSS Write '1' to disable interrupt for event CROSS Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled 6.11.3.11 RESULT Address offset: 0x400 Compare result 4452_021 v1.3 177 Peripherals A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Result of last compare. Decision point SAMPLE task. Input voltage is below the reference threshold (VIN+ < VIN-) Input voltage is above the reference threshold (VIN+ > VIN-) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable LPCOMP Disable Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description AnalogInput0 AnalogInput1 AnalogInput2 AnalogInput3 AnalogInput4 AnalogInput5 AnalogInput6 AnalogInput7 Analog pin select AIN0 selected as analog input AIN1 selected as analog input AIN2 selected as analog input AIN3 selected as analog input AIN4 selected as analog input AIN5 selected as analog input AIN6 selected as analog input AIN7 selected as analog input Below Above Disabled Enabled Bit number ID ID A Reset 0x00000000 AccessField R RESULT 6.11.3.12 ENABLE Address offset: 0x500 Enable LPCOMP Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 6.11.3.13 PSEL Address offset: 0x504 Input pin select Bit number ID ID A Reset 0x00000000 AccessField RW PSEL 6.11.3.14 REFSEL Address offset: 0x508 Reference select Bit number ID ID A Reset 0x00000004 AccessField RW REFSEL 0 1 0 1 0 1 2 3 4 5 6 7 0 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Value ID Value Description Ref1_8Vdd Ref2_8Vdd Reference select VDD * 1/8 selected as reference VDD * 2/8 selected as reference 4452_021 v1.3 178 Bit number ID Reset 0x00000004 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Value Description Peripherals A A A A Value ID Ref3_8Vdd Ref4_8Vdd Ref5_8Vdd Ref6_8Vdd Ref7_8Vdd ARef Ref1_16Vdd Ref3_16Vdd Ref5_16Vdd Ref7_16Vdd Ref9_16Vdd Ref11_16Vdd Ref13_16Vdd Ref15_16Vdd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VDD * 3/8 selected as reference VDD * 4/8 selected as reference VDD * 5/8 selected as reference VDD * 6/8 selected as reference VDD * 7/8 selected as reference External analog reference selected VDD * 1/16 selected as reference VDD * 3/16 selected as reference VDD * 5/16 selected as reference VDD * 7/16 selected as reference VDD * 9/16 selected as reference VDD * 11/16 selected as reference VDD * 13/16 selected as reference VDD * 15/16 selected as reference 6.11.3.15 EXTREFSEL Address offset: 0x50C External reference select 6.11.3.16 ANADETECT Address offset: 0x520 Analog detect configuration ID ID A ID ID A 6.11.3.17 HYST Address offset: 0x538 Comparator hysteresis enable Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EXTREFSEL AnalogReference0 AnalogReference1 0 1 External analog reference select Use AIN0 as external analog reference Use AIN1 as external analog reference Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW ANADETECT Analog detect configuration Cross Up Down 0 1 2 Generate ANADETECT on crossing, both upward crossing and downward crossing Generate ANADETECT on upward crossing only Generate ANADETECT on downward crossing only A A A 4452_021 v1.3 179 Bit number ID ID A Reset 0x00000000 AccessField RW HYST 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Peripherals A Value ID Value Description Disabled Enabled 0 1 Comparator hysteresis enable Comparator hysteresis disabled Comparator hysteresis enabled 6.11.4 Electrical specification 6.11.4.1 LPCOMP Electrical Specification Symbol tLPCANADET VINPOFFSET VHYST tSTARTUP Time from VIN crossing (>=50 mV above threshold) to ANADETECT signal generated Optional hysteresis Startup time for LPCOMP Description Min. Typ. Max. Units Input offset including reference ladder error

-40 40 5 35 140 s mV mV s 6.12 MWU Memory watch unit The Memory watch unit (MWU) can be used to generate events when a memory region is accessed by the CPU. The MWU can be configured to trigger events for access to Data RAM and Peripheral memory segments. The MWU allows an application developer to generate memory access events during development for debugging or during production execution for failure detection and recovery. Listed here are the main features for MWU:

Six memory regions, four user-configurable and two fixed regions in peripheral address space Flexible configuration of regions with START and END addresses Generate events on CPU read and/or write to a defined region of Data RAM or peripheral memory Programmable maskable or non-maskable (NMI) interrupt on events Peripheral interfaces can be watched for read and write access using subregions of the two fixed START address Configurable 0x40000000 0x40020000 END address Configurable 0x4001FFFF 0x4003FFFF Table 52: Memory regions Each MWU region is defined by a start address and an end address, configured by the START and END registers respectively. These addresses are byte aligned and inclusive. The END register value has to be greater or equal to the START register value. Each region is associated with a pair of events that indicate that either a write access or a read access from the CPU has been detected inside the region. For regions containing subregions (see below), a set of status registers PERREGION[0..1].SUBSTATWA and PERREGION[0..1].SUBSTATRA indicate which subregion(s) caused the EVENT_PREGION[0..1].WA and EVENT_PREGION[0..1].RA respectively. The MWU is only able to detect memory accesses in the Data RAM and Peripheral memory segments from the CPU, see Memory on page 19 for more information about the different memory segments. EasyDMA 4452_021 v1.3 180 address space memory regions Memory region REGION[0..3]

PREGION[0]

PREGION[1]

Peripherals accesses are not monitored by the MWU. The MWU requires two HCLK cycles to detect and generate the event. The peripheral regions, PREGION[0...1], are divided into 32 equally sized subregions, SR[0...31]. All subregions are excluded in the main region by default, and any can be included by specifying them in the SUBS register. When a subregion is excluded from the main region, the memory watch mechanism will not trigger any events when that subregion is accessed. Subregions in PREGION[0..1] cannot be individually configured for read or write access watch. Watch configuration is only possible for a region as a whole. The PRGNiRA and PRGNiWA (i=0..1) fields in the REGIONEN register control watching read and write access. REGION[0..3] can be individually enabled for read and/or write access watching through their respective RGNiRA and RGNiWA (i=0..3) fields in the REGIONEN register. REGIONENSET and REGIONENCLR allow respectively enabling and disabling one or multiple REGIONs or PREGIONs watching in a single write access. 6.12.1 Registers Base address Peripheral Instance Description Configuration 0x40020000 MWU MWU Memory watch unit Register Offset Description EVENTS_REGION[0].WA EVENTS_REGION[0].RA EVENTS_REGION[1].WA EVENTS_REGION[1].RA EVENTS_REGION[2].WA EVENTS_REGION[2].RA EVENTS_REGION[3].WA EVENTS_REGION[3].RA EVENTS_PREGION[0].WA EVENTS_PREGION[0].RA EVENTS_PREGION[1].WA EVENTS_PREGION[1].RA INTEN INTENSET INTENCLR NMIEN NMIENSET NMIENCLR 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x160 0x164 0x168 0x16C 0x300 0x304 0x308 0x320 0x324 0x328 Table 53: Instances Write access to region 0 detected Read access to region 0 detected Write access to region 1 detected Read access to region 1 detected Write access to region 2 detected Read access to region 2 detected Write access to region 3 detected Read access to region 3 detected Write access to peripheral region 0 detected Read access to peripheral region 0 detected Write access to peripheral region 1 detected Read access to peripheral region 1 detected Enable or disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable or disable interrupt was enabled for watching enabled for watching was enabled for watching REGIONEN REGIONENSET REGIONENCLR 4452_021 v1.3 0x510 0x514 0x518 enabled for watching Enable/disable regions watch Enable regions watch Disable regions watch 181 PERREGION[0].SUBSTATWA 0x400 Source of event/interrupt in region 0, write access detected while corresponding subregion PERREGION[0].SUBSTATRA 0x404 Source of event/interrupt in region 0, read access detected while corresponding subregion was PERREGION[1].SUBSTATWA 0x408 Source of event/interrupt in region 1, write access detected while corresponding subregion PERREGION[1].SUBSTATRA 0x40C Source of event/interrupt in region 1, read access detected while corresponding subregion was Peripherals Register REGION[0].START REGION[0].END REGION[1].START REGION[1].END REGION[2].START REGION[2].END REGION[3].START REGION[3].END PREGION[0].START PREGION[0].END PREGION[0].SUBS PREGION[1].START PREGION[1].END PREGION[1].SUBS Offset 0x600 0x604 0x610 0x614 0x620 0x624 0x630 0x634 0x6C0 0x6C4 0x6C8 0x6D0 0x6D4 0x6D8 Description Start address for region 0 End address of region 0 Start address for region 1 End address of region 1 Start address for region 2 End address of region 2 Start address for region 3 End address of region 3 Reserved for future use Reserved for future use Subregions of region 0 Reserved for future use Reserved for future use Subregions of region 1 Table 54: Register overview 6.12.1.1 EVENTS_REGION[n].WA (n=0..3) Address offset: 0x100 + (n 0x8) Write access to region n detected ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW WA Value ID Value Description NotGenerated Generated Write access to region n detected Event not generated Event generated 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6.12.1.2 EVENTS_REGION[n].RA (n=0..3) Address offset: 0x104 + (n 0x8) Read access to region n detected Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW RA Value ID Value Description NotGenerated Generated Read access to region n detected Event not generated Event generated 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6.12.1.3 EVENTS_PREGION[n].WA (n=0..1) Address offset: 0x160 + (n 0x8) Write access to peripheral region n detected 0 1 0 1 A A 4452_021 v1.3 182 ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW WA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write access to peripheral region n detected NotGenerated Generated Event not generated Event generated 6.12.1.4 EVENTS_PREGION[n].RA (n=0..1) Address offset: 0x164 + (n 0x8) Read access to peripheral region n detected Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW RA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Read access to peripheral region n detected NotGenerated Generated Event not generated Event generated Peripherals A A 6.12.1.5 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW REGION0WA Enable or disable interrupt for event REGION0WA B RW REGION0RA Enable or disable interrupt for event REGION0RA C RW REGION1WA Enable or disable interrupt for event REGION1WA D RW REGION1RA Enable or disable interrupt for event REGION1RA E RW REGION2WA Enable or disable interrupt for event REGION2WA F RW REGION2RA Enable or disable interrupt for event REGION2RA G RW REGION3WA Enable or disable interrupt for event REGION3WA H RW REGION3RA Enable or disable interrupt for event REGION3RA Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable 4452_021 v1.3 183 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW REGION0WA Write '1' to enable interrupt for event REGION0WA Peripherals Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Enable RW PREGION0WA Enable or disable interrupt for event PREGION0WA RW PREGION0RA Enable or disable interrupt for event PREGION0RA K RW PREGION1WA Enable or disable interrupt for event PREGION1WA L RW PREGION1RA Enable or disable interrupt for event PREGION1RA I J ID ID A 6.12.1.6 INTENSET Address offset: 0x304 Enable interrupt Value ID Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 B RW REGION0RA Write '1' to enable interrupt for event REGION0RA C RW REGION1WA Write '1' to enable interrupt for event REGION1WA D RW REGION1RA Write '1' to enable interrupt for event REGION1RA E RW REGION2WA Write '1' to enable interrupt for event REGION2WA F RW REGION2RA Write '1' to enable interrupt for event REGION2RA G RW REGION3WA Write '1' to enable interrupt for event REGION3WA 4452_021 v1.3 184 Disable Enable Disable Enable Disable Enable Disable Enable Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Peripherals Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value H RW REGION3RA Write '1' to enable interrupt for event REGION3RA RW PREGION0WA Write '1' to enable interrupt for event PREGION0WA RW PREGION0RA Write '1' to enable interrupt for event PREGION0RA K RW PREGION1WA Write '1' to enable interrupt for event PREGION1WA L RW PREGION1RA Write '1' to enable interrupt for event PREGION1RA 6.12.1.7 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW REGION0WA Write '1' to disable interrupt for event REGION0WA I J ID ID A B RW REGION0RA Write '1' to disable interrupt for event REGION0RA C RW REGION1WA Write '1' to disable interrupt for event REGION1WA D RW REGION1RA Write '1' to disable interrupt for event REGION1RA E RW REGION2WA Write '1' to disable interrupt for event REGION2WA 4452_021 v1.3 185 Value ID Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Description Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Peripherals F RW REGION2RA Write '1' to disable interrupt for event REGION2RA G RW REGION3WA Write '1' to disable interrupt for event REGION3WA H RW REGION3RA Write '1' to disable interrupt for event REGION3RA RW PREGION0WA Write '1' to disable interrupt for event PREGION0WA RW PREGION0RA Write '1' to disable interrupt for event PREGION0RA K RW PREGION1WA Write '1' to disable interrupt for event PREGION1WA L RW PREGION1RA Write '1' to disable interrupt for event PREGION1RA 6.12.1.8 NMIEN Address offset: 0x320 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW REGION0WA Enable or disable interrupt for event REGION0WA B RW REGION0RA Enable or disable interrupt for event REGION0RA C RW REGION1WA Enable or disable interrupt for event REGION1WA 4452_021 v1.3 186 Value ID Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Disabled Enabled Disabled Enabled Disabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 Description Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Enable Disable Enable Disable I J ID ID A Peripherals Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Enable D RW REGION1RA Enable or disable interrupt for event REGION1RA E RW REGION2WA Enable or disable interrupt for event REGION2WA F RW REGION2RA Enable or disable interrupt for event REGION2RA G RW REGION3WA Enable or disable interrupt for event REGION3WA H RW REGION3RA Enable or disable interrupt for event REGION3RA RW PREGION0WA Enable or disable interrupt for event PREGION0WA RW PREGION0RA Enable or disable interrupt for event PREGION0RA K RW PREGION1WA Enable or disable interrupt for event PREGION1WA L RW PREGION1RA Enable or disable interrupt for event PREGION1RA Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable 6.12.1.9 NMIENSET Address offset: 0x324 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW REGION0WA Write '1' to enable interrupt for event REGION0WA B RW REGION0RA Write '1' to enable interrupt for event REGION0RA C RW REGION1WA Write '1' to enable interrupt for event REGION1WA Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled 4452_021 v1.3 187 Value ID Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 I J ID ID A Peripherals Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value D RW REGION1RA Write '1' to enable interrupt for event REGION1RA Value ID Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 E RW REGION2WA Write '1' to enable interrupt for event REGION2WA F RW REGION2RA Write '1' to enable interrupt for event REGION2RA G RW REGION3WA Write '1' to enable interrupt for event REGION3WA H RW REGION3RA Write '1' to enable interrupt for event REGION3RA RW PREGION0WA Write '1' to enable interrupt for event PREGION0WA RW PREGION0RA Write '1' to enable interrupt for event PREGION0RA K RW PREGION1WA Write '1' to enable interrupt for event PREGION1WA L RW PREGION1RA Write '1' to enable interrupt for event PREGION1RA Description Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled 6.12.1.10 NMIENCLR Address offset: 0x328 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW REGION0WA Write '1' to disable interrupt for event REGION0WA Clear 1 Disable 4452_021 v1.3 188 I J ID ID A Peripherals Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value B RW REGION0RA Write '1' to disable interrupt for event REGION0RA C RW REGION1WA Write '1' to disable interrupt for event REGION1WA D RW REGION1RA Write '1' to disable interrupt for event REGION1RA E RW REGION2WA Write '1' to disable interrupt for event REGION2WA F RW REGION2RA Write '1' to disable interrupt for event REGION2RA G RW REGION3WA Write '1' to disable interrupt for event REGION3WA H RW REGION3RA Write '1' to disable interrupt for event REGION3RA I J RW PREGION0WA Write '1' to disable interrupt for event PREGION0WA RW PREGION0RA Write '1' to disable interrupt for event PREGION0RA K RW PREGION1WA Write '1' to disable interrupt for event PREGION1WA L RW PREGION1RA Write '1' to disable interrupt for event PREGION1RA Description Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Value ID Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 6.12.1.11 PERREGION[n].SUBSTATWA (n=0..1) Address offset: 0x400 + (n 0x8) 4452_021 v1.3 189 Peripherals Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching Bit number ID Reset 0x00000000 ID AccessField A-f RW SR[i] (i=0..31) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NoAccess Access Subregion i in region n (write '1' to clear) No write access occurred in this subregion Write access(es) occurred in this subregion 6.12.1.12 PERREGION[n].SUBSTATRA (n=0..1) Address offset: 0x404 + (n 0x8) Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NoAccess Access Subregion i in region n (write '1' to clear) No read access occurred in this subregion Read access(es) occurred in this subregion 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bit number ID Reset 0x00000000 ID AccessField A-f RW SR[i] (i=0..31) 6.12.1.13 REGIONEN Address offset: 0x510 Enable/disable regions watch Bit number ID ID A Reset 0x00000000 AccessField RW RGN0WA B RW RGN0RA C RW RGN1WA D RW RGN1RA E RW RGN2WA F RW RGN2RA Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable 4452_021 v1.3 190 Enable/disable write access watch in region[0]

Disable write access watch in this region Enable write access watch in this region Enable/disable read access watch in region[0]

Disable read access watch in this region Enable read access watch in this region Enable/disable write access watch in region[1]

Disable write access watch in this region Enable write access watch in this region Enable/disable read access watch in region[1]

Disable read access watch in this region Enable read access watch in this region Enable/disable write access watch in region[2]

Disable write access watch in this region Enable write access watch in this region Enable/disable read access watch in region[2]

Disable read access watch in this region Enable read access watch in this region 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Peripherals 6.12.1.14 REGIONENSET Address offset: 0x514 Enable regions watch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description ID ID G I J Reset 0x00000000 AccessField RW RGN3WA H RW RGN3RA RW PRGN0WA RW PRGN0RA K RW PRGN1WA L RW PRGN1RA Bit number ID ID A Reset 0x00000000 AccessField RW RGN0WA B RW RGN0RA C RW RGN1WA D RW RGN1RA E RW RGN2WA F RW RGN2RA Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 4452_021 v1.3 191 Enable/disable write access watch in region[3]

Disable write access watch in this region Enable write access watch in this region Enable/disable read access watch in region[3]

Disable read access watch in this region Enable read access watch in this region Enable/disable write access watch in PREGION[0]

Disable write access watch in this PREGION Enable write access watch in this PREGION Enable/disable read access watch in PREGION[0]

Disable read access watch in this PREGION Enable read access watch in this PREGION Enable/disable write access watch in PREGION[1]

Disable write access watch in this PREGION Enable write access watch in this PREGION Enable/disable read access watch in PREGION[1]

Disable read access watch in this PREGION Enable read access watch in this PREGION Enable write access watch in region[0]

Enable write access watch in this region Write access watch in this region is disabled Write access watch in this region is enabled Enable read access watch in region[0]

Enable read access watch in this region Read access watch in this region is disabled Read access watch in this region is enabled Enable write access watch in region[1]

Enable write access watch in this region Write access watch in this region is disabled Write access watch in this region is enabled Enable read access watch in region[1]

Enable read access watch in this region Read access watch in this region is disabled Read access watch in this region is enabled Enable write access watch in region[2]

Enable write access watch in this region Write access watch in this region is disabled Write access watch in this region is enabled Enable read access watch in region[2]

Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Bit number ID Reset 0x00000000 ID AccessField G RW RGN3WA H RW RGN3RA I J RW PRGN0WA RW PRGN0RA K RW PRGN1WA L RW PRGN1RA Bit number ID ID A Reset 0x00000000 AccessField RW RGN0WA B RW RGN0RA C RW RGN1WA Value ID Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 4452_021 v1.3 192 Enable read access watch in this region Read access watch in this region is disabled Read access watch in this region is enabled Enable write access watch in region[3]

Enable write access watch in this region Write access watch in this region is disabled Write access watch in this region is enabled Enable read access watch in region[3]

Enable read access watch in this region Read access watch in this region is disabled Read access watch in this region is enabled Enable write access watch in PREGION[0]

Enable write access watch in this PREGION Write access watch in this PREGION is disabled Write access watch in this PREGION is enabled Enable read access watch in PREGION[0]

Enable read access watch in this PREGION Read access watch in this PREGION is disabled Read access watch in this PREGION is enabled Enable write access watch in PREGION[1]

Enable write access watch in this PREGION Write access watch in this PREGION is disabled Write access watch in this PREGION is enabled Enable read access watch in PREGION[1]

Enable read access watch in this PREGION Read access watch in this PREGION is disabled Read access watch in this PREGION is enabled Disable write access watch in region[0]

Disable write access watch in this region Write access watch in this region is disabled Write access watch in this region is enabled Disable read access watch in region[0]

Disable read access watch in this region Read access watch in this region is disabled Read access watch in this region is enabled Disable write access watch in region[1]

Disable write access watch in this region Write access watch in this region is disabled Write access watch in this region is enabled 6.12.1.15 REGIONENCLR Address offset: 0x518 Disable regions watch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Bit number ID ID D Reset 0x00000000 AccessField RW RGN1RA E RW RGN2WA F RW RGN2RA G RW RGN3WA H RW RGN3RA I J RW PRGN0WA RW PRGN0RA K RW PRGN1WA L RW PRGN1RA Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Disable read access watch in region[1]

Disable read access watch in this region Read access watch in this region is disabled Read access watch in this region is enabled Disable write access watch in region[2]

Disable write access watch in this region Write access watch in this region is disabled Write access watch in this region is enabled Disable read access watch in region[2]

Disable read access watch in this region Read access watch in this region is disabled Read access watch in this region is enabled Disable write access watch in region[3]

Disable write access watch in this region Write access watch in this region is disabled Write access watch in this region is enabled Disable read access watch in region[3]

Disable read access watch in this region Read access watch in this region is disabled Read access watch in this region is enabled Disable write access watch in PREGION[0]

Disable write access watch in this PREGION Write access watch in this PREGION is disabled Write access watch in this PREGION is enabled Disable read access watch in PREGION[0]

Disable read access watch in this PREGION Read access watch in this PREGION is disabled Read access watch in this PREGION is enabled Disable write access watch in PREGION[1]

Disable write access watch in this PREGION Write access watch in this PREGION is disabled Write access watch in this PREGION is enabled Disable read access watch in PREGION[1]

Disable read access watch in this PREGION Read access watch in this PREGION is disabled Read access watch in this PREGION is enabled 6.12.1.16 REGION[n].START (n=0..3) Address offset: 0x600 + (n 0x10) Start address for region n Bit number ID ID A Reset 0x00000000 AccessField RW START 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Start address for region 4452_021 v1.3 193 Peripherals 6.12.1.17 REGION[n].END (n=0..3) Address offset: 0x604 + (n 0x10) End address of region n ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW END Value ID Value Description End address of region. A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6.12.1.18 PREGION[n].START (n=0..1) Address offset: 0x6C0 + (n 0x10) Reserved for future use Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R START Value ID Value Description Reserved for future use A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6.12.1.19 PREGION[n].END (n=0..1) Address offset: 0x6C4 + (n 0x10) Reserved for future use Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R END Value ID Value Description Reserved for future use A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6.12.1.20 PREGION[n].SUBS (n=0..1) Address offset: 0x6C8 + (n 0x10) Subregions of region n Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-f RW SR[i] (i=0..31) Include or exclude subregion i in region Value ID Value Description Exclude Include 0 1 Exclude Include 6.13 NFCT Near field communication tag The NFCT peripheral is an implementation of an NFC Forum compliant listening device NFC-A. 4452_021 v1.3 194 Peripherals With appropriate software, the NFCT peripheral can be used as the listening device NFC-A as specified by the NFC Forum. Listed here are the main features for the NFCT peripheral:

NFC-A listen mode operation 13.56 MHz input frequency Bit rate 106 kbps Wake-on-field low power field detection (SENSE) mode Frame assemble and disassemble for the NFC-A frames specified by the NFC Forum Programmable frame timing controller Integrated automatic collision resolution, cyclic redundancy check (CRC), and parity functions TASKS_ A C T I V A T E S E N S E D I S A B L E S T A R T T X I G O D L E G O S L E E P E N A B L E R X D A T A NFCT EasyDMA Frame assemble/

disassemble Modulator/

receiver NFC1 NFC2 EVENTS_ R E A D Y F I E L D L O S T F I E L D D E T E C T E D T X F R A M E E N D T X F R A M E S T A R T R X F R A M E S T A R T R X F R A M E E N D E R R O R R X E R R O R E N D R X E N D T X C O L L I S I O N S E L E C T E D S T A R T E D A U T O C O L R E S S T A R T E D Figure 58: NFCT block diagram 6.13.1 Overview The NFCT peripheral contains a 13.56 MHz AM receiver and a 13.56 MHz load modulator with 106 kbps data rate as defined by the NFC Forum. 4452_021 v1.3 195 NFCT PACKETPTR MAXLEN TXD.FRAMECONFIG Frame assemble SoF/EoF/parity/CRC On-the-air symbol coder 13.56 MHz NFC-A load modulator EasyDMA Collision resolution STARTTX ENABLERXDATA FRAMEDELAYxxx Frame timing controller Clock recovery Frame disassemble SoF/EoF/parity/CRC On-the-air symbol decoder 13.56 MHz NFC-A receiver NFCID1_xxx SENSRES SELRES FRAMESTATUS.RX RXD.FRAMECONFIG Field detector Peripherals NFC1 NFC2 Figure 59: NFCT overview When transmitting, the frame data will be transferred directly from RAM and transmitted with configurable frame type and delay timing. The system will be notified by an event whenever a complete frame is received or sent. The received frames will be automatically disassembled and the data part of the frame transferred to RAM. The NFCT peripheral also supports the collision detection and resolution ("anticollision") as defined by the NFC Forum. Wake-on-field is supported in SENSE mode while the device is either in System OFF or System ON mode. When the antenna enters an NFC field, an event will be triggered notifying the system to activate the NFCT functionality for incoming frames. In System ON, if the energy detected at the antenna increases beyond a threshold value, the module will generate a FIELDDETECTED event. When the strength of the field no longer supports NFC communication, the module will generate a FIELDLOST event. For the Low Power Field Detect threshold values, refer to NFCT Electrical Specification on page 224. In System OFF, the NFCT Low Power Field Detect function can wake the system up through a reset. See RESETREAS on page 73 for more information on how to detect a wakeup from NFCT. If the system is put into System OFF mode while a field is already present, the NFCT Low Power Field Detect function will wake the system up right away and generate a reset. Important: As a consequence of a reset, NFCT is disabled, and therefore the reset handler will have to activate NFCT again and set it up properly. The HFXO must be running before the NFCT peripheral goes into ACTIVATED state. Note that the NFCT peripheral calibration is automatically done on ACTIVATE task. The HFXO can be turned off when the NFCT peripheral goes into SENSE mode. The shortcut FIELDDETECTED_ACTIVATE can be used when the HFXO is already running while in SENSE mode. Outgoing data will be collected from RAM with the EasyDMA function and assembled according to theTXD.FRAMECONFIG on page 219 register. Incoming data will be disassembled according to the RXD.FRAMECONFIG register and the data section in the frame will be written to RAM via the EasyDMA function. 4452_021 v1.3 196 Peripherals The NFCT peripheral includes a frame timing controller that can be used to accurately control the inter-

frame delay between the incoming frame and a corresponding outgoing frame. It also includes optional CRC functionality. 6.13.2 Operating states Tasks and events are used to control the operating state of the peripheral. The module can change state by triggering a task, or when specific operations are finalized. Events and tasks allow software to keep track of and change the current state. See NFCT block diagram on page 195 and NFCT state diagram, automatic collision resolution enabled on page 197 for more information. See NFC Forum, NFC Activity Technical Specification for description on NFCT operating states. Activated GOIDLE NFC (OTHER)

/ COLLISION NFC (ALL_REQ)

/ AUTOCOLRESSTARTED NFC (SENS_REQ)

/ AUTOCOLRESSTARTED NFC (OTHER)

/ COLLISION NFC (ALL_REQ)

/ AUTOCOLRESSTARTED IDLERU IDLE

/ READY READY_A

/ SELECTED GOSLEEP NFC (SLP_REQ) SLEEP_A READY_A*

/ SELECTED DISABLE DISABLE ACTIVATE DISABLE SENSE SENSE_FIELD SENSE ACTIVE_A ENABLERXDATA STARTTX RECEIVE TRANSMIT STARTTX

/ TXFRAMEEND ACTIVATE

/ RXFRAMEEND

/ RXERROR Figure 60: NFCT state diagram, automatic collision resolution enabled DISABLE DISABLE ACTIVATE DISABLE SENSE Activated IDLERU

/ READY ACTIVE_A SENSE_FIELD SENSE ENABLERXDATA STARTTX RECEIVE TRANSMIT STARTTX

/TXFRAMEEND ACTIVATE

/RXFRAMEEND

/ RXERROR Figure 61: NFCT state diagram, automatic collision resolution disabled 4452_021 v1.3 197 Peripherals Important:

FIELDLOST event is not generated in SENSE mode. Sending SENSE task while field is still present does not generate FIELDDETECTED event. If the FIELDDETECTED event is cleared before sending the ACTIVATE task, then the FIELDDETECTED event shows up again after sending the ACTIVATE task. The shortcut FIELDDETECTED_ACTIVATE can be used to avoid this condition. 6.13.3 Pin configuration NFCT uses two pins to connect the antenna and these pins are shared with GPIOs. The PROTECT field in the NFCPINS register in UICR defines the usage of these pins and their protection level against excessive voltages. The content of the NFCPINS register is reloaded at every reset. See Pin assignments on page 557 for the pins used by the NFCT peripheral. When NFCPINS.PROTECT=NFC, a protection circuit will be enabled on the dedicated pins, preventing the chip from being damaged in the presence of a strong NFC field. The protection circuit will short the two pins together if voltage difference exceeds approximately 2V. The GPIO function on those pins will also be disabled. When NFCPINS.PROTECT=Disabled, the device will not be protected against strong NFC field damages caught by a connected NFCT antenna, and the NFCT peripheral will not operate as expected, as it will never leave the DISABLE state. The pins dedicated to the NFCT antenna function will have some limitation when the pins are configured for normal GPIO operation. The pin capacitance will be higher on those (refer to CPAD_NFC in the Electrical Specification of GPIO General purpose input/output on page 138), and some increased leakage current between the two pins is to be expected if they are used in GPIO mode, and are driven to different logical values. To save power, the two pins should always be set to the same logical value whenever entering one of the device power saving modes. For details, refer to INFC_LEAK in the Electrical Specification of GPIO General purpose input/output on page 138. 6.13.4 EasyDMA The NFCT peripheral implements EasyDMA for reading and writing of data packets from and to the Data RAM. The NFCT EasyDMA utilizes a pointer called PACKETPTR on page 219 for receiving and transmitting packets. The NFCT peripheral uses EasyDMA to read or write RAM, but not both at the same time. The event RXFRAMESTART indicates that the EasyDMA has started writing to the RAM for a receive frame and the event RXFRAMEND indicates that the EasyDMA has completed writing to the RAM. Similarly, the event TXFRAMESTART indicates that the EasyDMA has started reading from the RAM for a transmit frame and the event TXFRAMEND indicates that the EasyDMA has completed reading from the RAM. If a transmit and a receive operation is issued at the same time, the transmit operation would be prioritized. Starting a transmit operation while the EasyDMA is writing a receive frame to the RAM will result in unpredictable behavior. Starting an EasyDMA operation when there is an ongoing EasyDMA operation may result in unpredictable behavior. It is recommended to wait for the TXFRAMEEND or RXFRAMEEND event for the ongoing transmit or receive before starting a new receive or transmit operation. The MAXLEN on page 219 register determines the maximum number of bytes that can be read from or written to the RAM. This feature can be used to ensure that the NFCT peripheral does not overwrite, or read beyond, the RAM assigned to a packet. Note that if the RXD.AMOUNT or TXD.AMOUNT register indicates longer data packets than set in MAXLEN, the frames sent to or received from the physical layer 4452_021 v1.3 198 Peripherals will be incomplete. In that situation, in RX, the OVERRUN bit in the FRAMESTATUS.RX register will be set and an RXERROR event will be triggered. Important: The RXD.AMOUNT and TXD.AMOUNT define a frame length in bytes and bits excluding start of frame (SoF), end of frame (EoF), and parity, but including CRC for RXD.AMOUNT only. Make sure to take potential additional bits into account when setting MAXLEN. Only sending task ENABLERXDATA ensures that a new value in PACKETPTR pointing to the RX buffer in Data RAM is taken into account. If PACKETPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a hard fault or RAM corruption. For more information about the different memory regions, see Chapter Memory on page 19. The NFCT peripherals normally do alternative receive and transmit frames. Therefore, to prepare for the next frame, the PACKETPTR, MAXLEN, TXD.FRAMECONFIG and TXD.AMOUNT can be updated while the receive is in progress, and, similarly, the PACKETPTR, MAXLEN and RXD.FRAMECONFIG can be updated while the transmit is in progress. They can be updated and prepared for the next NFC frame immediately after the STARTED event of the current frame has been received. Updating the TXD.FRAMECONFIG and TXD.AMOUNT during the current transmit frame or updating RXD.FRAMECONFIG during current receive frame may cause unpredictable behaviour. In accordance with NFC Forum, NFC Digital Protocol Technical Specification, the least significant bit (LSB) from the least significant byte (LSByte) is sent on air first. The bytes are stored in increasing order, starting at the lowest address in the EasyDMA buffer in RAM. 6.13.5 Frame assembler The NFCT peripheral implements a frame assembler in hardware. When the NFCT peripheral is in the ACTIVE_A state, the software can decide to enter RX or TX mode. For RX, see Frame disassembler on page 200. For TX, the software must indicate the address of the source buffer in Data RAM and its size through programming the PACKETPTR and MAXLEN registers respectively, then issuing a STARTTX task. MAXLEN must be set so that it matches the size of the frame to be sent. The STARTED event indicates that the PACKETPTR and MAXLEN registers have been captured by the frame assembler EasyDMA. When asserting the STARTTX task, the frame assembler module will start reading TXD.AMOUNT.TXDATABYTES bytes (plus one additional byte if TXD.AMOUNT.TXDATABITS > 0) from the RAM position set by the PACKETPTR. The NFCT peripheral transmits the data as read from RAM, adding framing and the CRC calculated on the fly if set in TXD.FRAMECONFIG. The NFCT peripheral will take (8*TXD.AMOUNT.TXDATABYTES +

TXD.AMOUNT.TXDATABITS) bits and assemble a frame according to the settings in TXD.FRAMECONFIG. Both short frames, standard frames, and bit-oriented SDD frames as specified in the NFC Forum, NFC Digital Protocol Technical Specification can be assembled by the correct setting of the TXD.FRAMECONFIG register. The bytes will be transmitted on air in the same order as they are read from RAM with a rising bit order within each byte, least significant bit (LSB) first. That is, b0 will be transmitted on air before b1, and so on. The bits read from RAM will be coded into symbols as defined in the NFC Forum, NFC Digital Protocol Technical Specification. 4452_021 v1.3 199 Peripherals Important: Some NFC Forum documents, such as NFC Forum, NFC Digital Protocol Technical Specification, define bit numbering in a byte from b1 (LSB) to b8 (most significant bit (MSB)), while most other technical documents from the NFC Forum, and also the Nordic Semiconductor documentation, traditionally number them from b0 to b7. The present document uses the b0 b7 numbering scheme. Be aware of this when comparing the NFC Forum, NFC Digital Protocol Technical Specification to others. The frame assembler can be configured in TXD.FRAMECONFIG to add SoF symbol, calculate and add parity bits, and calculate and add CRC to the data read from RAM when assembling the frame. The total frame will then be longer than what is defined by TXD.AMOUNT.TXDATABYTES. TXDATABITS. DISCARDMODE will select if the first bits in the first byte read from RAM or the last bits in the last byte read from RAM will be discarded if TXD.AMOUNT.TXDATABITS are not equal to zero. Note that if TXD.FRAMECONFIG.PARITY

= Parity and TXD.FRAMECONFIG.DISCARDMODE=DiscardStart, a parity bit will be included after the non-

complete first byte. No parity will be added after a non-complete last byte. The frame assemble operation is illustrated in Frame assemble illustration on page 200 for different settings in TXD.FRAMECONFIG. All shaded bit fields are added by the frame assembler. Some of these bits are optional and appearances are configured in TXD.FRAMECONFIG. Note that the frames illustrated do not necessarily comply with the NFC specification. The figure is only to illustrate the behavior of the NFCT peripheral. Byte 1: PACKETPTR + 0 b0 .. b7 Byte 2: PACKETPTR + 1 b0 .. b7 Byte (TXDATABYTES) b0 .. b7 Byte (TXDATABYTES + 1) b0 .. b7

(only if TXDATABITS > 0) Data from RAM Frame on air PARITY = Parity TXDATABITS = 0 CRCMODETX = CRC16TX SoF Byte 1 b0 .. b7 PARITY = Parity TXDATABITS = 4 CRCMODETX = NoCRCTX DISCARDMODE = DiscardStart PARITY = Parity TXDATABITS = 0 CRCMODETX = NoCRCTX SoF Byte 1 b0 .. b7 P P Byte 2 b0 .. b7 Byte (TXDATABYTES) b0 .. b7 P P CRC 1 (8 bit) P CRC 2 (8 bit) P EoF Byte 1 b4 .. b7 P SoF Byte 2 b0 .. b7 P Byte (TXDATABYTES) b0 .. b7 Byte (TXDATABYTES + 1) b0 .. b7 P P EoF Byte TXDATABYTES b0 .. b7 P EoF Figure 62: Frame assemble illustration The accurate timing for transmitting the frame on air is set using the frame timing controller settings. 6.13.6 Frame disassembler The NFCT peripheral implements a frame disassembler in hardware. When the NFCT peripheral is in the ACTIVE_A state, the software can decide to enter RX or TX mode. For TX, see Frame assembler on page 199. For RX, the software must indicate the address and size of the destination buffer in Data RAM through programming the PACKETPTR and MAXLEN registers before issuing an ENABLERXDATA task. The STARTED event indicates that the PACKETPTR and MAXLEN registers have been captured by the frame disassembler EasyDMA. When an incoming frame starts, the RXFRAMESTART event will get issued and data will be written to the buffer in Data RAM. The frame disassembler will verify and remove any parity bits, start of frame (SoF) and 4452_021 v1.3 200 Peripherals end of frame (EoF) symbols on the fly based on RXD.FRAMECONFIG register configuration. It will, however, verify and transfer the CRC bytes into RAM, if the CRC is enabled through RXD.FRAMECONFIG. When an EoF symbol is detected, the NFCT peripheral will assert the RXFRAMEEND event and write the RXD.AMOUNT register to indicate numbers of received bytes and bits in the data packet. The module does not interpret the content of the data received from the remote NFC device, except for SoF, EoF, parity, and CRC checking, as described above. The frame disassemble operation is illustrated below. P P Frame on air PARITY = Parity RXDATABITS = 0 CRCMODERX = CRC16RX SoF SoF SoF PARITY = Parity CRCMODERX = NoCRCTR RXDATABITS = 4 PARITY = NoParity CRCMODERX = NoCRCRX RXDATABITS = 0 Data to RAM Byte 1 b0 .. b7 Byte 2 b0 .. b7 b0 .. b7 P CRC 1 (8 bit) P CRC 2 (8 bit) P EoF Byte (RXDATABYTES) P P Byte 1 b0 .. b7 Byte 2 b0 .. b7 Byte (RXDATABYTES) b0 .. b7 Byte (RXDATABYTES + 1) b4 .. b7 EoF P Byte 1 b0 .. b7 Byte 2 b0 .. b7 b0 .. b7 Byte RXDATABYTES b0 .. b7 EoF Byte 1: PACKETPTR + 0 b0 .. b7 Byte 2: PACKETPTR + 1 b0 .. b7 Byte (RXDATABYTES) b0 .. b7 Byte (RXDATABYTES + 1) b0 .. b7

(only if RXDATABITS > 0) Figure 63: Frame disassemble illustration Per NFC specification, the time between EoF to the next SoF can be as short as 86 s, and thefore care must be taken that PACKETPTR and MAXLEN are ready and ENABLERXDATA is issued on time after the end of previous frame. The use of a PPI shortcut from TXFRAMEEND to ENABLERXDATA is recommended. 6.13.7 Frame timing controller The NFCT peripheral includes a frame timing controller that continuously keeps track of the number of the 13.56 MHz RF carrier clock periods since the end of the EoF of the last received frame. The NFCT peripheral can be programmed to send a responding frame within a time window or at an exact count of RF carrier periods. In case of FRAMEDELAYMODE = Window, a STARTTX task triggered before the frame timing controller counter is equal to FRAMEDELAYMIN will force the transmission to halt until the counter is equal to FRAMEDELAYMIN. If the counter is within FRAMEDELAYMIN and FRAMEDELAYMAX when the STARTTX task is triggered, the NFCT peripheral will start the transmission straight away. In case of FRAMEDELAYMODE = ExactVal, a STARTTX task triggered before the frame delay counter is equal to FRAMEDELAYMAX will halt the actual transmission start until the counter is equal to FRAMEDELAYMAX. In case of FRAMEDELAYMODE = WindowGrid, the behaviour is similar to the FRAMEDELAYMODE =

Window, but the actual transmission between FRAMEDELAYMIN and FRAMEDELAYMAX starts on a bit grid as defined for NFC-A Listen frames (slot duration of 128 RF carrier periods). An ERROR event (with FRAMEDELAYTIMEOUT cause in ERRORSTATUS) will be asserted if the frame timing controller counter reaches FRAMEDELAYMAX without any STARTTX task triggered. This may happen even when the response is not required as per NFC Forum, NFC Digital Protocol Technical Specification. Any commands handled by the automatic collision resolution that don't involve a response being generated may also result in an ERROR event (with FRAMEDELAYTIMEOUT cause in ERRORSTATUS). The FRAMEDELAYMIN and FRAMEDELAYMAX values shall only be updated before the STARTTX task is triggered. Failing to do so may cause unpredictable behaviour. 4452_021 v1.3 201 The frame timing controller operation is illustrated in Frame timing controller

(FRAMEDELAYMODE=Window) on page 202. The frame timing controller automatically adjusts the frame timing counter based on the last received data bit according to NFC-A technology in the NFC Forum, NFC Digital Protocol Technical Specification. Peripherals Logic 0 Subcarrier continues in the 3 cases below FRAMEDELAYMIN FRAMEDELAYMAX Transmit SoF Receive Last data bit EoF Logic 1 Before Min 20/fc 84/fc STARTTX task Subcarrier modulation Between Min and Max STARTTX task Subcarrier modulation After Max (or missing) STARTTX task Subcarrier modulation ERROR event SoF Figure 64: Frame timing controller (FRAMEDELAYMODE=Window) 6.13.8 Collision resolution The NFCT peripheral implements an automatic collision resolution function as defined by the NFC Forum. Automatic collision resolution is enabled by default, and it is recommended that the feature is used since it is power efficient and reduces the complexity of software handling the collision resolution sequence. This feature can be disabled through the MODE field in the AUTOCOLRESCONFIG register. When the automatic collision resolution is disabled, all commands will be sent over EasyDMA as defined in frame disassembler. The SENSRES and SELRES registers need to be programmed upfront in order for the collision resolution to behave correctly. Depending on the NFCIDSIZE field in SENSRES, the following registers also need to be programmed upfront:

NFCID1_LAST if NFCID1SIZE=NFCID1Single (ID = 4 bytes);

NFCID1_2ND_LAST and NFCID1_LAST if NFCID1SIZE=NFCID1Double (ID = 7 bytes);

NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST if NFCID1SIZE=NFCID1Triple (ID = 10 bytes);

A pre-defined set of registers, NFC.TAGHEADER0..3, containing a valid NFCID1 value, is available in FICR and can be used by software to populate the NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST registers. NFCID1 byte allocation (top sent first on air) on page 203 explains the position of the ID bytes in NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST, depending on the ID size, and as compared to the definition used in the NFC Forum, NFC Digital Protocol Technical Specification. 4452_021 v1.3 202 Peripherals ID = 4 bytes ID = 7 bytes ID = 10 bytes NFCID1_Q NFCID1_R NFCID1_S NFCID1_T NFCID1_U NFCID1_V NFCID1_W nfcid10 NFCID1_X NFCID1_Y NFCID1_Z nfcid11 nfcid12 nfcid13 nfcid10 nfcid11 nfcid12 nfcid13 nfcid14 nfcid15 nfcid16 nfcid10 nfcid11 nfcid12 nfcid13 nfcid14 nfcid15 nfcid16 nfcid17 nfcid18 nfcid19 Table 55: NFCID1 byte allocation (top sent first on air) The hardware implementation can handle the states from IDLE to ACTIVE_A automatically as defined in the NFC Forum, NFC Activity Technical Specification, and the other states are to be handled by software. The software keeps track of the state through events. The collision resolution will trigger an AUTOCOLRESSTARTED event when it has started. Reaching the ACTIVE_A state is indicated by the SELECTED event. If collision resolution fails, a COLLISION event is triggered. Note that errors occurring during automatic collision resolution may also cause ERROR and/or RXERROR events to be generated. Other events may also get generated. It is recommended that the software ignores any event except COLLISION, SELECTED and FIELDLOST during automatic collision resolution. Software shall also make sure that any unwanted SHORT or PPI shortcut is disabled during automatic collision resolution. The automatic collision resolution will be restarted, if the packets are received with CRC or parity errors while in ACTIVE_A state. The automatic collision resolution feature can be disabled while in ACTIVE_A state to avoid this. The SLP_REQ is automatically handled by the NFCT peripheral when the automatic collision resolution is enabled. However, this results in an ERROR event (with FRAMEDELAYTIMEOUT cause in ERRORSTATUS) since the SLP_REQ has no response. This error must be ignored until the SELECTED event is triggered and this error should be cleared by the software when the SELECTED event is triggered. 6.13.9 Antenna interface In ACTIVATED state, an amplitude regulator will adjust the voltage swing on the antenna pins to a value that is within the Vswing limit. Refer to NFCT Electrical Specification on page 224. 6.13.10 NFCT antenna recommendations The NFCT antenna coil must be connected differential between NFC1 and NFC2 pins of the device. Two external capacitors should be used to tune the resonance of the antenna circuit to 13.56 MHz. 4452_021 v1.3 203 Peripherals ANTENNA Lant Rin Cp1 Ctune1 Cint1 NFC1 NFC2 Cp2 Ctune2 Cint2 Figure 65: NFCT antenna recommendations The required tuning capacitor value is given by the below equations:

An antenna inductance of Lant = 2 H will give tuning capacitors in the range of 130 pF on each pin. The total capacitance on NFC1 and NFC2 must be matched. 6.13.11 Battery protection If the antenna is exposed to a strong NFC field, current may flow in the opposite direction on the supply due to parasitic diodes and ESD structures. If the battery used does not tolerate return current, a series diode must be placed between the battery and the device in order to protect the battery. 6.13.12 Digital Modulation Signal Support for external analog frontends or antenna architectures is possible by optionally outputting the digital modulation signal to a GPIO. The NFCT peripheral is designed to connect directly to a loop antenna, receive a modulated signal from an NFC Reader with its internal analog frontend and transmit data back by changing the input resistance that is then seen as modulated load by the NFC Reader. In addition, the peripheral has an option to output the digital modulation signal to a GPIO. Reception still occurs through the internal analog frontend, whereas transmission can be done by one of the following:

The internal analog frontend through the loop antenna (default) An external frontend using the digital modulation signal The combination of both above 4452_021 v1.3 204 Peripherals There are two registers that allow configuration of the modulation signal (i.e. of the response from NFCT to the NFC Reader), MODULATIONCTRL and MODULATIONPSEL. The registers need to be programmed before NFCT sends a response to a request from a reader. Ideally, this configuration is performed during startup and whenever the NFCT peripheral is powered up. The selected GPIO needs to be configured as output in the corresponding GPIO configuration register. It is recommended to set an output value in the corresponding GPIO.OUT register this value will be driven whenever the NFCT peripheral is disabled. NFCT drives the pin low when there is no modulation, and drives it with On-Off Keying (OOK) modulation of an 847 kHz subcarrier (derived from the carrier frequency) when it responds to commands from an NFC Reader. 6.13.13 References NFC Forum, NFC Analog Specification version 1.0, www.nfc-forum.org NFC Forum, NFC Digital Protocol Technical Specification version 1.1, www.nfc-forum.org NFC Forum, NFC Activity Technical Specification version 1.1, www.nfc-forum.org 6.13.14 Registers Base address Peripheral Instance Description Configuration 0x40005000 NFCT NFCT Near field communication tag Table 56: Instances TASKS_ENABLERXDATA Initializes the EasyDMA for receive. EVENTS_FIELDDETECTED Remote NFC field detected Description Disable NFCT peripheral Activate NFCT peripheral for incoming and outgoing frames, change state to activated Enable NFC sense field mode, change state to sense mode Start transmission of an outgoing frame, change state to transmit Force state machine to IDLE state Force state machine to SLEEP_A state The NFCT peripheral is ready to receive and send frames Remote NFC field lost Marks the start of the first symbol of a transmitted frame Marks the end of the last transmitted on-air symbol of a frame Marks the end of the first symbol of a received frame Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer NFC error reported. The ERRORSTATUS register contains details on the source of the error. NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer Register TASKS_ACTIVATE TASKS_DISABLE TASKS_SENSE TASKS_STARTTX TASKS_GOIDLE TASKS_GOSLEEP EVENTS_READY EVENTS_FIELDLOST EVENTS_TXFRAMESTART EVENTS_TXFRAMEEND EVENTS_RXFRAMESTART EVENTS_RXFRAMEEND EVENTS_ERROR EVENTS_RXERROR EVENTS_ENDRX EVENTS_ENDTX EVENTS_COLLISION EVENTS_SELECTED EVENTS_STARTED SHORTS INTEN Offset 0x000 0x004 0x008 0x00C 0x01C 0x024 0x028 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x128 0x12C 0x130 0x148 0x14C 0x150 0x200 0x300 EVENTS_AUTOCOLRESSTARTED 0x138 Auto collision resolution process has started NFC auto collision resolution error reported. NFC auto collision resolution successfully completed EasyDMA is ready to receive or send frames. Shortcuts between local events and tasks Enable or disable interrupt 4452_021 v1.3 205 Peripherals Register INTENSET INTENCLR ERRORSTATUS FRAMESTATUS.RX NFCTAGSTATE SLEEPSTATE FIELDPRESENT FRAMEDELAYMIN FRAMEDELAYMAX FRAMEDELAYMODE PACKETPTR MAXLEN TXD.FRAMECONFIG TXD.AMOUNT RXD.FRAMECONFIG RXD.AMOUNT MODULATIONCTRL MODULATIONPSEL NFCID1_LAST NFCID1_2ND_LAST NFCID1_3RD_LAST SENSRES SELRES Offset 0x304 0x308 0x404 0x40C 0x410 0x420 0x43C 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0x520 0x524 0x52C 0x538 0x590 0x594 0x598 0x59C 0x5A0 0x5A4 Description Enable interrupt Disable interrupt NFC Error Status register Result of last incoming frame NfcTag state register Sleep state during automatic collision resolution Indicates the presence or not of a valid field Minimum frame delay Maximum frame delay Configuration register for the Frame Delay Timer Packet pointer for TXD and RXD data storage in Data RAM Size of the RAM buffer allocated to TXD and RXD data storage each Configuration of outgoing frames Size of outgoing frame Configuration of incoming frames Size of last incoming frame antenna. Pin select for Modulation control. Last NFCID1 part (4, 7 or 10 bytes ID) Second last NFCID1 part (7 or 10 bytes ID) Third last NFCID1 part (10 bytes ID) peripheral is activated. NFC-A SENS_RES auto-response settings NFC-A SEL_RES auto-response settings Table 57: Register overview AUTOCOLRESCONFIG Controls the auto collision resolution function. This setting must be done before the NFCT Enables the modulation output to a GPIO pin which can be connected to a second external 6.13.14.1 TASKS_ACTIVATE Address offset: 0x000 Activate NFCT peripheral for incoming and outgoing frames, change state to activated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_ACTIVATE Activate NFCT peripheral for incoming and outgoing frames, A Trigger 1 Trigger task change state to activated 6.13.14.2 TASKS_DISABLE Address offset: 0x004 Disable NFCT peripheral 4452_021 v1.3 206 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_DISABLE Disable NFCT peripheral Trigger 1 Trigger task 6.13.14.3 TASKS_SENSE Address offset: 0x008 Enable NFC sense field mode, change state to sense mode Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_SENSE Enable NFC sense field mode, change state to sense mode Trigger 1 Trigger task 6.13.14.4 TASKS_STARTTX Address offset: 0x00C Start transmission of an outgoing frame, change state to transmit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTTX Start transmission of an outgoing frame, change state to Trigger 1 transmit Trigger task 6.13.14.5 TASKS_ENABLERXDATA Address offset: 0x01C Initializes the EasyDMA for receive. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_ENABLERXDATA Initializes the EasyDMA for receive. Trigger 1 Trigger task ID ID A ID ID A ID ID A ID ID A A A A A 6.13.14.6 TASKS_GOIDLE Address offset: 0x024 Force state machine to IDLE state 4452_021 v1.3 207 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_GOIDLE Force state machine to IDLE state Trigger 1 Trigger task 6.13.14.7 TASKS_GOSLEEP Address offset: 0x028 Force state machine to SLEEP_A state Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_GOSLEEP Force state machine to SLEEP_A state Trigger 1 Trigger task 6.13.14.8 EVENTS_READY Address offset: 0x100 The NFCT peripheral is ready to receive and send frames Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_READY The NFCT peripheral is ready to receive and send frames NotGenerated Generated Event not generated Event generated 6.13.14.9 EVENTS_FIELDDETECTED Address offset: 0x104 Remote NFC field detected Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_FIELDDETECTED NotGenerated Generated Remote NFC field detected Event not generated Event generated 0 1 0 1 ID ID A ID ID A ID ID A ID ID A A A A A 6.13.14.10 EVENTS_FIELDLOST Address offset: 0x108 Remote NFC field lost 4452_021 v1.3 208 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Peripherals AccessField Value ID Value Description RW EVENTS_FIELDLOST NotGenerated Generated Remote NFC field lost Event not generated Event generated 6.13.14.11 EVENTS_TXFRAMESTART Address offset: 0x10C Marks the start of the first symbol of a transmitted frame Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_TXFRAMESTART Marks the start of the first symbol of a transmitted frame NotGenerated Generated Event not generated Event generated 6.13.14.12 EVENTS_TXFRAMEEND Address offset: 0x110 Marks the end of the last transmitted on-air symbol of a frame Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_TXFRAMEEND Marks the end of the last transmitted on-air symbol of a NotGenerated Generated frame Event not generated Event generated 6.13.14.13 EVENTS_RXFRAMESTART Address offset: 0x114 Marks the end of the first symbol of a received frame Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RXFRAMESTART Marks the end of the first symbol of a received frame NotGenerated Generated Event not generated Event generated ID ID A ID ID A ID ID A ID ID A A A A A 0 1 0 1 0 1 0 1 6.13.14.14 EVENTS_RXFRAMEEND Address offset: 0x118 4452_021 v1.3 209 Peripherals Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RXFRAMEEND Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the NotGenerated Generated RX buffer Event not generated Event generated 6.13.14.15 EVENTS_ERROR Address offset: 0x11C NFC error reported. The ERRORSTATUS register contains details on the source of the error. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ERROR NFC error reported. The ERRORSTATUS register contains NotGenerated Generated details on the source of the error. Event not generated Event generated 6.13.14.16 EVENTS_RXERROR Address offset: 0x128 NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RXERROR NFC RX frame error reported. The FRAMESTATUS.RX register NotGenerated Generated contains details on the source of the error. Event not generated Event generated ID ID A ID ID A ID ID A A A A 0 1 0 1 0 1 6.13.14.17 EVENTS_ENDRX Address offset: 0x12C RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. 4452_021 v1.3 210 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ENDRX RX buffer (as defined by PACKETPTR and MAXLEN) in Data NotGenerated Generated RAM full. Event not generated Event generated 6.13.14.18 EVENTS_ENDTX Address offset: 0x130 Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ENDTX Transmission of data in RAM has ended, and EasyDMA has NotGenerated Generated ended accessing the TX buffer Event not generated Event generated 6.13.14.19 EVENTS_AUTOCOLRESSTARTED Address offset: 0x138 Auto collision resolution process has started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_AUTOCOLRESSTARTED Auto collision resolution process has started NotGenerated Generated Event not generated Event generated 6.13.14.20 EVENTS_COLLISION Address offset: 0x148 NFC auto collision resolution error reported. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_COLLISION NFC auto collision resolution error reported. NotGenerated Generated Event not generated Event generated ID ID A ID ID A ID ID A ID ID A A A A A 0 1 0 1 0 1 0 1 4452_021 v1.3 211 Peripherals A A 6.13.14.21 EVENTS_SELECTED Address offset: 0x14C NFC auto collision resolution successfully completed ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_SELECTED NFC auto collision resolution successfully completed NotGenerated Generated Event not generated Event generated 6.13.14.22 EVENTS_STARTED Address offset: 0x150 EasyDMA is ready to receive or send frames. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_STARTED EasyDMA is ready to receive or send frames. NotGenerated Generated Event not generated Event generated 6.13.14.23 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW FIELDDETECTED_ACTIVATE Shortcut between event FIELDDETECTED and task ACTIVATE B RW FIELDLOST_SENSE Shortcut between event FIELDLOST and task SENSE F RW TXFRAMEEND_ENABLERXDATA Shortcut between event TXFRAMEEND and task Disabled Enabled Disabled Enabled Disabled Enabled Disable shortcut Enable shortcut Disable shortcut Enable shortcut ENABLERXDATA Disable shortcut Enable shortcut 0 1 0 1 0 1 0 1 0 1 6.13.14.24 INTEN Address offset: 0x300 Enable or disable interrupt 4452_021 v1.3 212 Bit number ID ID A Reset 0x00000000 AccessField RW READY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T S R N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event READY Peripherals B RW FIELDDETECTED Enable or disable interrupt for event FIELDDETECTED C RW FIELDLOST Enable or disable interrupt for event FIELDLOST D RW TXFRAMESTART Enable or disable interrupt for event TXFRAMESTART E RW TXFRAMEEND Enable or disable interrupt for event TXFRAMEEND F RW RXFRAMESTART Enable or disable interrupt for event RXFRAMESTART G RW RXFRAMEEND Enable or disable interrupt for event RXFRAMEEND H RW ERROR Enable or disable interrupt for event ERROR K RW RXERROR Enable or disable interrupt for event RXERROR L RW ENDRX Enable or disable interrupt for event ENDRX M RW ENDTX Enable or disable interrupt for event ENDTX N RW AUTOCOLRESSTARTED Enable or disable interrupt for event AUTOCOLRESSTARTED R RW COLLISION Enable or disable interrupt for event COLLISION S RW SELECTED Enable or disable interrupt for event SELECTED T RW STARTED Enable or disable interrupt for event STARTED Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6.13.14.25 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.3 213 Bit number ID ID A Reset 0x00000000 AccessField RW READY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T S R N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event READY Peripherals Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled B RW FIELDDETECTED Write '1' to enable interrupt for event FIELDDETECTED C RW FIELDLOST Write '1' to enable interrupt for event FIELDLOST D RW TXFRAMESTART Write '1' to enable interrupt for event TXFRAMESTART E RW TXFRAMEEND Write '1' to enable interrupt for event TXFRAMEEND F RW RXFRAMESTART Write '1' to enable interrupt for event RXFRAMESTART G RW RXFRAMEEND Write '1' to enable interrupt for event RXFRAMEEND H RW ERROR Write '1' to enable interrupt for event ERROR K RW RXERROR Write '1' to enable interrupt for event RXERROR L RW ENDRX Write '1' to enable interrupt for event ENDRX M RW ENDTX Write '1' to enable interrupt for event ENDTX N RW AUTOCOLRESSTARTED Write '1' to enable interrupt for event AUTOCOLRESSTARTED R RW COLLISION Write '1' to enable interrupt for event COLLISION 4452_021 v1.3 214 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T S R N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Peripherals S RW SELECTED Write '1' to enable interrupt for event SELECTED T RW STARTED Write '1' to enable interrupt for event STARTED 6.13.14.26 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW READY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T S R N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event READY B RW FIELDDETECTED Write '1' to disable interrupt for event FIELDDETECTED C RW FIELDLOST Write '1' to disable interrupt for event FIELDLOST D RW TXFRAMESTART Write '1' to disable interrupt for event TXFRAMESTART E RW TXFRAMEEND Write '1' to disable interrupt for event TXFRAMEEND F RW RXFRAMESTART Write '1' to disable interrupt for event RXFRAMESTART G RW RXFRAMEEND Write '1' to disable interrupt for event RXFRAMEEND 4452_021 v1.3 215 Value ID Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Description Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Bit number ID ID H Reset 0x00000000 AccessField RW ERROR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T S R N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event ERROR Peripherals K RW RXERROR Write '1' to disable interrupt for event RXERROR L RW ENDRX Write '1' to disable interrupt for event ENDRX M RW ENDTX Write '1' to disable interrupt for event ENDTX N RW AUTOCOLRESSTARTED Write '1' to disable interrupt for event AUTOCOLRESSTARTED R RW COLLISION Write '1' to disable interrupt for event COLLISION S RW SELECTED Write '1' to disable interrupt for event SELECTED T RW STARTED Write '1' to disable interrupt for event STARTED Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 6.13.14.27 ERRORSTATUS Address offset: 0x404 NFC Error Status register Write a bit to '1' to clear it. Writing '0' has no effect. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW FRAMEDELAYTIMEOUT No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX A 4452_021 v1.3 216 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description 6.13.14.28 FRAMESTATUS.RX Address offset: 0x40C Result of last incoming frame Write a bit to '1' to clear it. Writing '0' has no effect. ID ID A ID ID A RW CRCERROR B RW PARITYSTATUS C RW OVERRUN 6.13.14.29 NFCTAGSTATE Address offset: 0x410 NfcTag state register CRCCorrect CRCError ParityOK ParityError NoOverrun Overrun Disabled RampUp Idle Receive FrameDelay Transmit 0 1 0 1 0 1 0 2 3 4 5 6 6.13.14.30 SLEEPSTATE Address offset: 0x420 Sleep state during automatic collision resolution No valid end of frame (EoF) detected Valid CRC detected CRC received does not match local check Parity status of received frame Frame received with parity OK Frame received with parity error Overrun detected No overrun detected Overrun error Description NfcTag state Disabled or sense RampUp Idle Receive FrameDelay Transmit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value R NFCTAGSTATE 4452_021 v1.3 217 ID ID A ID ID A ID ID A ID ID A Peripherals A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R SLEEPSTATE Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP Idle SleepA task. State is IDLE. State is SLEEP_A. 6.13.14.31 FIELDPRESENT Address offset: 0x43C Indicates the presence or not of a valid field Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R FIELDPRESENT Indicates if a valid field is present. Available only in the B R LOCKDETECT Indicates if the low level has locked to the field NoField FieldPresent NotLocked Locked activated state. No valid field detected Valid field detected Not locked to field Locked to field 0 1 0 1 0 1 6.13.14.32 FRAMEDELAYMIN Address offset: 0x504 Minimum frame delay 6.13.14.33 FRAMEDELAYMAX Address offset: 0x508 Maximum frame delay Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A Reset 0x00000480 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 AccessField Value ID Value Description RW FRAMEDELAYMIN Minimum frame delay in number of 13.56 MHz clocks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A Reset 0x00001000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW FRAMEDELAYMAX Maximum frame delay in number of 13.56 MHz clocks 4452_021 v1.3 218 Peripherals A A 6.13.14.34 FRAMEDELAYMODE Address offset: 0x50C Configuration register for the Frame Delay Timer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 AccessField Value ID Value Description RW FRAMEDELAYMODE Configuration register for the Frame Delay Timer FreeRun Window ExactVal WindowGrid 0 1 2 3 Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX Frame is transmitted exactly at FRAMEDELAYMAX Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX 6.13.14.35 PACKETPTR Address offset: 0x510 Packet pointer for TXD and RXD data storage in Data RAM Bit number ID ID A Reset 0x00000000 AccessField RW PTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. Note: See the memory chapter for details about which memories are available for EasyDMA. 6.13.14.36 MAXLEN Address offset: 0x514 Size of the RAM buffer allocated to TXD and RXD data storage each Bit number ID ID A Reset 0x00000000 AccessField RW MAXLEN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value

[0..257]

Description storage each Size of the RAM buffer allocated to TXD and RXD data 6.13.14.37 TXD.FRAMECONFIG Address offset: 0x518 Configuration of outgoing frames 4452_021 v1.3 219 Bit number ID ID A Reset 0x00000017 AccessField RW PARITY B RW DISCARDMODE C RW SOF D RW CRCMODETX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 Value ID Value Description Peripherals D C B A NoParity Parity DiscardEnd DiscardStart NoSoF SoF NoCRCTX CRC16TX 0 1 0 1 0 1 0 1 Indicates if parity is added to the frame Parity is not added to TX frames Parity is added to TX frames Discarding unused bits at start or end of a frame Unused bits are discarded at end of frame (EoF) Unused bits are discarded at start of frame (SoF) Adding SoF or not in TX frames SoF symbol not added SoF symbol added CRC mode for outgoing frames CRC is not added to the frame 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame 6.13.14.38 TXD.AMOUNT Address offset: 0x51C Size of outgoing frame Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID ID A RW TXDATABITS AccessField Value ID Description Value

[0..7]

B B B B B B B B B A A A B RW TXDATABYTES

[0..257]

Number of complete bytes that shall be included in the Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). The DISCARDMODE field in FRAMECONFIG.TX selects if unused bits is discarded at the start or at the end of a frame. A value of 0 data bytes and 0 data bits is invalid. frame, excluding CRC, parity and framing 6.13.14.39 RXD.FRAMECONFIG Address offset: 0x520 Configuration of incoming frames 4452_021 v1.3 220 Bit number ID ID A Reset 0x00000015 AccessField RW PARITY B RW SOF C RW CRCMODERX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 Value ID Value Description Peripherals C B A NoParity Parity NoSoF SoF NoCRCRX CRC16RX 0 1 0 1 0 1 Indicates if parity expected in RX frame Parity is not expected in RX frames Parity is expected in RX frames SoF expected or not in RX frames SoF symbol is not expected in RX frames SoF symbol is expected in RX frames CRC mode for incoming frames CRC is not expected in RX frames Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated 6.13.14.40 RXD.AMOUNT Address offset: 0x524 Size of last incoming frame ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B B B B B B B B B A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R RXDATABITS Number of bits in the last byte in the frame, if less than 8

(including CRC, but excluding parity and SoF/EoF framing). Frames with 0 data bytes and less than 7 data bits are invalid and are not received properly. CRC, but excluding parity and SoF/EoF framing) B R RXDATABYTES Number of complete bytes received in the frame (including 6.13.14.41 MODULATIONCTRL Address offset: 0x52C Enables the modulation output to a GPIO pin which can be connected to a second external antenna. See MODULATIONPSEL for GPIO configuration. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 AccessField Value ID Value Description RW MODULATIONCTRL Invalid Internal ModToGpio 0x0 0x1 0x2 Configuration of modulation control. Invalid, defaults to same behaviour as for Internal Use internal modulator only Output digital modulation signal to a GPIO pin. to a GPIO pin. InternalAndModToGpio 0x3 Use internal modulator and output digital modulation signal 6.13.14.42 MODULATIONPSEL Address offset: 0x538 Pin select for Modulation control. 4452_021 v1.3 221 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

[0..31]

[0..1]

C 1 0 Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Peripherals B A A A A A 6.13.14.43 NFCID1_LAST Address offset: 0x590 Last NFCID1 part (4, 7 or 10 bytes ID) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 Value ID Value Description NFCID1 byte Z (very last byte sent) NFCID1 byte Y NFCID1 byte X NFCID1 byte W 6.13.14.44 NFCID1_2ND_LAST Address offset: 0x594 Second last NFCID1 part (7 or 10 bytes ID) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C C C C C C C C B B B B B B B B A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value 6.13.14.45 NFCID1_3RD_LAST Address offset: 0x598 Third last NFCID1 part (10 bytes ID) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C C C C C C C C B B B B B B B B A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value ID A B C ID A B C D ID A B C ID A B C Reset 0x00006363 ID AccessField RW NFCID1_Z RW NFCID1_Y RW NFCID1_X RW NFCID1_W Reset 0x00000000 ID AccessField RW NFCID1_V RW NFCID1_U RW NFCID1_T Reset 0x00000000 ID AccessField RW NFCID1_S RW NFCID1_R RW NFCID1_Q Description NFCID1 byte V NFCID1 byte U NFCID1 byte T Description NFCID1 byte S NFCID1 byte R NFCID1 byte Q 4452_021 v1.3 222 Peripherals 6.13.14.46 AUTOCOLRESCONFIG Address offset: 0x59C Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. When modifiying this register bit 1 must be written to '1'. Bit number ID ID A Reset 0x00000002 AccessField RW MODE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value ID Value Description Enabled Disabled 0 1 Enables/disables auto collision resolution Auto collision resolution enabled Auto collision resolution disabled 6.13.14.47 SENSRES Address offset: 0x5A0 NFC-A SENS_RES auto-response settings Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E E E E D D D D C C B A A A A A Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 AccessField Value ID Value Description ID ID A RW BITFRAMESDD Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol SDD00000 SDD00001 SDD00010 SDD00100 SDD01000 SDD10000 NFCID1Single NFCID1Double NFCID1Triple 16 0 1 2 4 8 0 1 2 Technical Specification SDD pattern 00000 SDD pattern 00001 SDD pattern 00010 SDD pattern 00100 SDD pattern 01000 SDD pattern 10000 resolution engine. NFCID1 size: single (4 bytes) NFCID1 size: double (7 bytes) NFCID1 size: triple (10 bytes) B C RW RFU5 RW NFCIDSIZE Reserved for future use. Shall be 0. NFCID1 size. This value is used by the auto collision Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification Reserved for future use. Shall be 0. D RW PLATFCONFIG E RW RFU74 6.13.14.48 SELRES Address offset: 0x5A4 NFC-A SEL_RES auto-response settings 4452_021 v1.3 223 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Peripherals E D D C C B A A Reserved for future use. Shall be 0. Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification

(controlled by hardware, shall be 0) Reserved for future use. Shall be 0. Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification Reserved for future use. Shall be 0. ID ID A B C D E AccessField RW RFU10 RW CASCADE RW RFU43 RW PROTOCOL RW RFU7 6.13.15 Electrical specification 6.13.15.1 NFCT Electrical Specification fc CMI DR Vsense Imax Frequency of operation Carrier modulation index Data Rate NFC215 Peak differential Field detect threshold level on NFC1-

6.13.15.2 NFCT Timing Parameters Symbol tactivate Description Time from task_ACTIVATE in SENSE or DISABLE state to ACTIVATE_A or IDLE state16 tsense Time from remote field is present in SENSE mode to FIELDDETECTED event is asserted Symbol Description Min. Typ. Max. Units Maximum input current on NFCT pins 80 mA 95 13.56 106 1.2 MHz

kbps Vp Min. Typ. Max. Units 500 s 20 s S E N S E A C T I V A T E tsense tactivate tsense D I S A B L E MODES DISABLE SENSE_FIELD IDLERU Activated DISABLE F I E L D D E T E C T E D R E A D Y F I E L D L O S T F I E L D D E T E C T E D RF-Carrier T A S K S E V E N T S Figure 66: NFCT timing parameters (Shortcuts for FIELDDETECTED and FIELDLOST are disabled) 6.14 PDM Pulse density modulation interface The pulse density modulation (PDM) module enables input of pulse density modulated signals from external audio frontends, for example, digital microphones. The PDM module generates the PDM clock 15 Input is high impedance in sense mode 16 Does not account for voltage supply and oscillator startup times 4452_021 v1.3 224 CLK DIN Peripherals and supports single-channel or dual-channel (left and right) data input. Data is transferred directly to RAM buffers using EasyDMA. Listed here are the main features for PDM:

Up to two PDM microphones configured as a left/right pair using the same data input 16 kHz output sample rate, 16-bit samples EasyDMA support for sample buffering HW decimation filters Selectable ratio of 64 or 80 between PDM_CLK and output sample rate The PDM module illustrated below is interfacing up to two digital microphones with the PDM interface. EasyDMA is implemented to relieve the real-time requirements associated with controlling of the PDM slave from a low priority CPU execution context. It also includes all the necessary digital filter elements to produce pulse code modulation (PCM) samples. The PDM module allows continuous audio streaming. Master clock generator g n i l p m a S PDM to PCM PDM to PCM Bandpass and decimation (left) Bandpass and decimation (right) Figure 67: PDM module A M D y s a E M A R 6.14.1 Master clock generator The master clock generator's PDMCLKCTRL register allows adjusting the PDM clock's frequency. The master clock generator does not add any jitter to the HFCLK source chosen. It is recommended (but not mandatory) to use the Xtal as HFCLK source. 6.14.2 Module operation By default, bits from the left PDM microphone are sampled on PDM_CLK falling edge, and bits for the right are sampled on the rising edge of PDM_CLK, resulting in two bitstreams. Each bitstream is fed into a digital filter which converts the PDM stream into 16-bit PCM samples, then filters and down-samples them to reach the appropriate sample rate. The EDGE field in the MODE register allows swapping left and right, so that left will be sampled on rising edge, and right on falling. The PDM module uses EasyDMA to store the samples coming out from the filters into one buffer in RAM. Depending on the mode chosen in the OPERATION field in the MODE register, memory either contains alternating left and right 16-bit samples (Stereo), or only left 16-bit samples (Mono). To ensure continuous PDM sampling, it is up to the application to update the EasyDMA destination address pointer as the previous buffer is filled. The continuous transfer can be started or stopped by sending the START and STOP tasks. STOP becomes effective after the current frame has finished transferring, which will generate the STOPPED event. The STOPPED event indicates that all activity in the module is finished, and that the data is available in RAM

(EasyDMA has finished transferring as well). Attempting to restart before receiving the STOPPED event may result in unpredictable behavior. 4452_021 v1.3 225 Peripherals 6.14.3 Decimation filter In order to convert the incoming data stream into PCM audio samples, a decimation filter is included in the PDM interface module. The input of the filter is the two-channel PDM serial stream (with left channel on clock high, right channel on clock low). Depending on the RATIO selected, its output is 2 16-bit PCM samples at a sample rate either 64 times or 80 times (depending on the RATIO register) lower than the PDM clock rate. The filter stage of each channel is followed by a digital volume control, to attenuate or amplify the output samples in a range of -20 dB to +20 dB around the default (reset) setting, defined by GPDM,default. The gain is controlled by the GAINL and GAINR registers. As an example, if the goal is to achieve 2500 RMS output samples (16-bit) with a 1 kHz 90 dBA signal into a

-26 dBFS sensitivity PDM microphone, do the following:

Sum the PDM module's default gain ( GPDM,default ) and the gain introduced by the microphone and acoustic path of his implementation (an attenuation would translate into a negative gain) Adjust GAINL and GAINR by the above summed amount. Assuming that only the PDM module influences the gain, GAINL and GAINR must be set to -GPDM,default dB to achieve the requirement. With GPDM,default=3.2 dB, and as GAINL and GAINR are expressed in 0.5 dB steps, the closest value to program would be 3.0 dB, which can be calculated as:

GAINL = GAINR = (DefaultGain - (2 * 3)) Remember to check that the resulting values programmed into GAINL and GAINR fall within MinGain and MaxGain. 6.14.4 EasyDMA Samples will be written directly to RAM, and EasyDMA must be configured accordingly. The address pointer for the EasyDMA channel is set in SAMPLE.PTR register. If the destination address set in SAMPLE.PTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. DMA supports Stereo (Left+Right 16-bit samples) and Mono (Left only) data transfer, depending on the setting in the OPERATION field in the MODE register. The samples are stored little endian. MODE.OPERATION Bits per sample Result stored per RAM Physical RAM allocated Result boundary indexes Note Stereo Mono 32 (2x16) 16 word L+R 2xL

(32-bit words) in RAM ceil(SAMPLE.MAXCNT/2) R0=[31:16]; L0=[15:0]

Default ceil(SAMPLE.MAXCNT/2) L1=[31:16]; L0=[15:0]

Table 58: DMA sample storage The destination buffer in RAM consists of one block, the size of which is set in SAMPLE.MAXCNT register. Format is number of 16-bit samples. The physical RAM allocated is always:

(RAM allocation, in bytes) = SAMPLE.MAXCNT * 2;

(but the mapping of the samples depends on MODE.OPERATION. If OPERATION=Stereo, RAM will contain a succession of left and right samples. If OPERATION=Mono, RAM will contain a succession of left only samples. 4452_021 v1.3 226 Peripherals For a given value of SAMPLE.MAXCNT, the buffer in RAM can contain half the stereo sampling time as compared to the mono sampling time. The PDM acquisition can be started by the START task, after the SAMPLE.PTR and SAMPLE.MAXCNT registers have been written. When starting the module, it will take some time for the filters to start outputting valid data. Transients from the PDM microphone itself may also occur. The first few samples

(typically around 50) might hence contain invalid values or transients. It is therefore advised to discard the first few samples after a PDM start. As soon as the STARTED event is received, the firmware can write the next SAMPLE.PTR value (this register is double-buffered), to ensure continuous operation. When the buffer in RAM is filled with samples, an END event is triggered. The firmware can start processing the data in the buffer. Meanwhile, the PDM module starts acquiring data into the new buffer pointed to by SAMPLE.PTR, and sends a new STARTED event, so that the firmware can update SAMPLE.PTR to the next buffer address. 6.14.5 Hardware example PDM can be configured with a single microphone (mono), or with two microphones. When a single microphone is used, connect the microphone clock to CLK, and data to DIN. Figure 69: Example of a single PDM microphone, wired as right Note that in a single-microphone (mono) configuration, depending on the microphones implementation, either the left or the right channel (sampled at falling or rising CLK edge respectively) will contain reliable data. If two microphones are used, one of them has to be set as left, the other as right (L/R pin tied high or to GND on the respective microphone). It is strongly recommended to use two microphones of exactly the same brand and type so that their timings in left and right operation match. Figure 68: Example of a single PDM microphone, wired as left Vdd CLK L/R DATA Vdd CLK L/R DATA L/R DATA Vdd CLK Vdd CLK L/R DATA nRFxxxxx CLK DIN nRFxxxxx CLK DIN nRFxxxxx CLK DIN CLK DIN CLK DIN CLK DIN Figure 70: Example of two PDM microphones 4452_021 v1.3 227 Peripherals 6.14.6 Pin configuration The CLK and DIN signals associated to the PDM module are mapped to physical pins according to the configuration specified in the PSEL.CLK and PSEL.DIN registers respectively. If the CONNECT field in any PSEL register is set to Disconnected, the associated PDM module signal will not be connected to the required physical pins, and will not operate properly. The PSEL.CLK and PSEL.DIN registers and their configurations are only used as long as the PDM module is enabled, and retained only as long as the device is in System ON mode. See POWER Power supply on page 58 for more information about power modes. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register. To ensure correct behavior in the PDM module, the pins used by the PDM module must be configured in the GPIO peripheral as described in GPIO configuration before enabling peripheral on page 228 before enabling the PDM module. This is to ensure that the pins used by the PDM module are driven correctly if the PDM module itself is temporarily disabled or the device temporarily enters System OFF. This configuration must be retained in the GPIO for the selected I/Os as long as the PDM module is supposed to be connected to an external PDM circuit. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. PDM signal PDM pin Output value Comment CLK DIN As specified in PSEL.CLK As specified in PSEL.DIN 0 Not applicable Direction Output Input Table 59: GPIO configuration before enabling peripheral 6.14.7 Registers Base address Peripheral Instance Description Configuration 0x4001D000 PDM PDM Pulse Density modulation (digital microphone) interface Table 60: Instances Description Starts continuous PDM transfer Stops PDM transfer PDM transfer has started PDM transfer has finished Enable or disable interrupt Enable interrupt Disable interrupt PDM module enable register PDM clock generator control Left output gain adjustment Right output gain adjustment Register TASKS_START TASKS_STOP EVENTS_STARTED EVENTS_STOPPED EVENTS_END INTEN INTENSET INTENCLR ENABLE PDMCLKCTRL MODE GAINL GAINR RATIO PSEL.CLK PSEL.DIN SAMPLE.PTR Offset 0x000 0x004 0x100 0x104 0x108 0x300 0x304 0x308 0x500 0x504 0x508 0x518 0x51C 0x520 0x540 0x544 0x560 4452_021 v1.3 228 The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM Defines the routing of the connected PDM microphones' signals Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. Pin number configuration for PDM CLK signal Pin number configuration for PDM DIN signal RAM address pointer to write samples to with EasyDMA Peripherals A A A Register SAMPLE.MAXCNT Offset 0x564 Description Number of samples to allocate memory for in EasyDMA mode Table 61: Register overview 6.14.7.1 TASKS_START Address offset: 0x000 Starts continuous PDM transfer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_START Starts continuous PDM transfer Trigger 1 Trigger task ID ID A ID ID A ID ID A 6.14.7.2 TASKS_STOP Address offset: 0x004 Stops PDM transfer 6.14.7.3 EVENTS_STARTED Address offset: 0x100 PDM transfer has started 6.14.7.4 EVENTS_STOPPED Address offset: 0x104 PDM transfer has finished Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Stops PDM transfer Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_STARTED NotGenerated Generated 0 1 PDM transfer has started Event not generated Event generated 4452_021 v1.3 229 ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_STOPPED NotGenerated Generated 0 1 PDM transfer has finished Event not generated Event generated 6.14.7.5 EVENTS_END Address offset: 0x108 The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_END The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM Event not generated Event generated Peripherals A A NotGenerated Generated 6.14.7.6 INTEN Address offset: 0x300 Enable or disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW STARTED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event STARTED B RW STOPPED Enable or disable interrupt for event STOPPED C RW END Enable or disable interrupt for event END Disabled Enabled Disabled Enabled Disabled Enabled Disable Enable Disable Enable Disable Enable 0 1 0 1 0 1 0 1 6.14.7.7 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.3 230 Bit number ID ID A Reset 0x00000000 AccessField RW STARTED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event STARTED Peripherals C B A B RW STOPPED Write '1' to enable interrupt for event STOPPED C RW END Write '1' to enable interrupt for event END Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Disabled Enabled 6.14.7.8 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW STARTED 6.14.7.9 ENABLE Address offset: 0x500 PDM module enable register Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event STARTED B RW STOPPED Write '1' to disable interrupt for event STOPPED C RW END Write '1' to disable interrupt for event END 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable PDM module Disable Enable 4452_021 v1.3 231 Peripherals 6.14.7.10 PDMCLKCTRL Address offset: 0x504 PDM clock generator control Bit number ID ID A Reset 0x08400000 AccessField RW FREQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description 1000K Default 1067K 1231K 1280K 1333K 0x08000000 0x08400000 0x08800000 0x09800000 0x0A000000 PDM_CLK frequency configuration PDM_CLK = 32 MHz / 32 = 1.000 MHz PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. PDM_CLK = 32 MHz / 30 = 1.067 MHz PDM_CLK = 32 MHz / 26 = 1.231 MHz PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. 0x0A800000 PDM_CLK = 32 MHz / 24 = 1.333 MHz 6.14.7.11 MODE Address offset: 0x508 Defines the routing of the connected PDM microphones' signals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW OPERATION Mono or stereo operation Stereo Mono LeftFalling LeftRising 0 1 0 1 Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0]

Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0]

Defines on which PDM_CLK edge left (or mono) is sampled Left (or mono) is sampled on falling edge of PDM_CLK Left (or mono) is sampled on rising edge of PDM_CLK ID ID A B RW EDGE 6.14.7.12 GAINL Address offset: 0x518 Left output gain adjustment 4452_021 v1.3 232 Bit number ID ID A Reset 0x00000028 AccessField RW GAINL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 Value ID Value Description Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) Peripherals A A A A A A A 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust

(...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust

-20 dB gain adjustment (minimum) 0 dB gain adjustment

+20 dB gain adjustment (maximum) MinGain DefaultGain MaxGain 0x00 0x28 0x50 6.14.7.13 GAINR Address offset: 0x51C Right output gain adjustment Bit number ID ID A Reset 0x00000028 AccessField RW GAINR 6.14.7.14 RATIO Address offset: 0x520 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 Value ID Value Description Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) MinGain DefaultGain MaxGain 0x00 0x28 0x50

-20 dB gain adjustment (minimum) 0 dB gain adjustment

+20 dB gain adjustment (maximum) Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. Bit number ID ID A Reset 0x00000000 AccessField RW RATIO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Ratio64 Ratio80 0 1 Ratio of 64 Ratio of 80 Selects the ratio between PDM_CLK and output sample rate 6.14.7.15 PSEL.CLK Address offset: 0x540 4452_021 v1.3 233 Pin number configuration for PDM CLK signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Peripherals B A A A A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A C 1 0 C 1 0 Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 6.14.7.16 PSEL.DIN Address offset: 0x544 Pin number configuration for PDM DIN signal Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 6.14.7.17 SAMPLE.PTR Address offset: 0x560 RAM address pointer to write samples to with EasyDMA ID A B C ID A B C ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW SAMPLEPTR Address to write PDM samples to over DMA Note: See the memory chapter for details about which memories are available for EasyDMA. 6.14.7.18 SAMPLE.MAXCNT Address offset: 0x564 Number of samples to allocate memory for in EasyDMA mode Bit number ID ID A Reset 0x00000000 AccessField RW BUFFSIZE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description

[0..32767]

Length of DMA RAM allocation in number of samples 4452_021 v1.3 234 6.14.8 Electrical specification 6.14.8.1 PDM Electrical Specification Symbol fPDM,CLK,64 Description PDM clock speed. PDMCLKCTRL = Default (Setting needed for 16 MHz sample frequency @ RATIO = Ratio64) fPDM,CLK,80 PDM clock speed. PDMCLKCTRL = 1280K (Setting needed for 16 MHz sample frequency @ RATIO = Ratio80) tPDM,JITTER TdPDM,CLK tPDM,DATA tPDM,cv tPDM,ci tPDM,s tPDM,h Jitter in PDM clock output PDM clock duty cycle Decimation filter delay Allowed clock edge to data valid Allowed (other) clock edge to data invalid Data setup time at fPDM,CLK=1.024 MHz or 1.280 MHz Data hold time at fPDM,CLK=1.024 MHz or 1.280 MHz Peripherals Min. Typ. Max. Units 1.032 1.280 20 60 5 125 40 50 0 65 0 MHz MHz ns

ms ns ns ns ns dB GPDM,default Default (reset) absolute gain of the PDM module 3.2 CLK DIN (L) DIN(R) tPDM,CLK tPDM,cv tPDM,s tPDM,h=tPDM,ci tPDM,cv tPDM,s tPDM,h=tPDM,ci Figure 71: PDM timing diagram 6.15 PPI Programmable peripheral interconnect The programmable peripheral interconnect (PPI) enables peripherals to interact autonomously with each other using tasks and events independent of the CPU. The PPI allows precise synchronization between peripherals when real-time application constraints exist and eliminates the need for CPU activity to implement behavior which can be predefined using PPI. 4452_021 v1.3 235 CH[1].EEP CH[0].EEP CH[n].EEP Peripherals Peripheral 1 Peripheral 2 Event 1 Event 2 Event 1 Event 2 Event 3 0 1 n CHEN CHG[0]

... CHG[m]

0 1 n 0 1 n 16MHz Task 1 Task 1 Task 2 Task 3 Peripheral 1 Peripheral 2 CH[0].TEP FORK[0].TEP Figure 72: PPI block diagram The PPI system has, in addition to the fully programmable peripheral interconnections, a set of channels where the event end point (EEP) and task end points (TEP) are fixed in hardware. These fixed channels can be individually enabled, disabled, or added to PPI channel groups (see CHG[n] registers), in the same way as ordinary PPI channels. Instance PPI PPI (fixed) Channel 0-19 20-31 Number of channels 20 12 Table 62: Configurable and fixed PPI channels The PPI provides a mechanism to automatically trigger a task in one peripheral as a result of an event occurring in another peripheral. A task is connected to an event through a PPI channel. The PPI channel is composed of three end point registers, one EEP, and two TEPs. A peripheral task is connected to a TEP using the address of the task register associated with the task. Similarly, a peripheral event is connected to an EEP using the address of the event register associated with the event. On each PPI channel, the signals are synchronized to the 16 MHz clock to avoid any internal violation of setup and hold timings. As a consequence, events that are synchronous to the 16 MHz clock will be delayed by one clock period, while other asynchronous events will be delayed by up to one 16 MHz clock period. Note: Shortcuts (as defined in the SHORTS register in each peripheral) are not affected by this 16 MHz synchronization, and are therefore not delayed. 4452_021 v1.3 236 Peripherals Each TEP implements a fork mechanism that enables a second task to be triggered at the same time as the task specified in the TEP is triggered. This second task is configured in the task end point register in the FORK registers groups, e.g. FORK.TEP[0] is associated with PPI channel CH[0]. There are two ways of enabling and disabling PPI channels:

Enable or disable PPI channels individually using the CHEN, CHENSET, and CHENCLR registers. Enable or disable PPI channels in PPI channel groups through the groups ENABLE and DISABLE tasks. Prior to these tasks being triggered, the PPI channel group must be configured to define which PPI channels belong to which groups. Note: When a channel belongs to two groups m and n, and the tasks CHG[m].EN and CHG[n].DIS occur simultaneously (m and n can be equal or different), the CHG[m].EN on that channel has priority. PPI tasks (for example, CHG[0].EN) can be triggered through the PPI like any other task, which means they can be hooked to a PPI channel as a TEP. One event can trigger multiple tasks by using multiple channels and one task can be triggered by multiple events in the same way. 6.15.1 Pre-programmed channels Some of the PPI channels are pre-programmed. These channels cannot be configured by the CPU, but can be added to groups and enabled and disabled like the general purpose PPI channels. The FORK TEP for these channels are still programmable and can be used by the application. For a list of pre-programmed PPI channels, see the following table. Channel EEP 20 21 22 23 24 25 26 27 28 29 30 31 TIMER0->EVENTS_COMPARE[1]

RADIO->TASKS_DISABLE TIMER0->EVENTS_COMPARE[0]

TIMER0->EVENTS_COMPARE[0]

RADIO->EVENTS_BCMATCH RADIO->EVENTS_READY RADIO->EVENTS_ADDRESS RADIO->EVENTS_ADDRESS RADIO->EVENTS_END RTC0->EVENTS_COMPARE[0]

RTC0->EVENTS_COMPARE[0]

RTC0->EVENTS_COMPARE[0]

RTC0->EVENTS_COMPARE[0]

TEP RADIO->TASKS_TXEN RADIO->TASKS_RXEN AAR->TASKS_START CCM->TASKS_KSGEN CCM->TASKS_CRYPT TIMER0->TASKS_CAPTURE[1]

TIMER0->TASKS_CAPTURE[2]

RADIO->TASKS_TXEN RADIO->TASKS_RXEN TIMER0->TASKS_CLEAR TIMER0->TASKS_START Table 63: Pre-programmed channels 6.15.2 Registers Base address Peripheral Instance Description Configuration 0x4001F000 PPI PPI Programmable peripheral interconnect Table 64: Instances Register TASKS_CHG[0].EN TASKS_CHG[0].DIS TASKS_CHG[1].EN TASKS_CHG[1].DIS 4452_021 v1.3 Offset 0x000 0x004 0x008 0x00C Description Enable channel group 0 Disable channel group 0 Enable channel group 1 Disable channel group 1 237 Register Offset Description Peripherals TASKS_CHG[2].EN TASKS_CHG[2].DIS TASKS_CHG[3].EN TASKS_CHG[3].DIS TASKS_CHG[4].EN TASKS_CHG[4].DIS TASKS_CHG[5].EN TASKS_CHG[5].DIS CHEN CHENSET CHENCLR CH[0].EEP CH[0].TEP CH[1].EEP CH[1].TEP CH[2].EEP CH[2].TEP CH[3].EEP CH[3].TEP CH[4].EEP CH[4].TEP CH[5].EEP CH[5].TEP CH[6].EEP CH[6].TEP CH[7].EEP CH[7].TEP CH[8].EEP CH[8].TEP CH[9].EEP CH[9].TEP CH[10].EEP CH[10].TEP CH[11].EEP CH[11].TEP CH[12].EEP CH[12].TEP CH[13].EEP CH[13].TEP CH[14].EEP CH[14].TEP CH[15].EEP CH[15].TEP CH[16].EEP CH[16].TEP CH[17].EEP CH[17].TEP CH[18].EEP CH[18].TEP CH[19].EEP CH[19].TEP CHG[0]

CHG[1]

0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x500 0x504 0x508 0x510 0x514 0x518 0x51C 0x520 0x524 0x528 0x52C 0x530 0x534 0x538 0x53C 0x540 0x544 0x548 0x54C 0x550 0x554 0x558 0x55C 0x560 0x564 0x568 0x56C 0x570 0x574 0x578 0x57C 0x580 0x584 0x588 0x58C 0x590 0x594 0x598 0x59C 0x5A0 0x5A4 0x5A8 0x5AC 0x800 0x804 Enable channel group 2 Disable channel group 2 Enable channel group 3 Disable channel group 3 Enable channel group 4 Disable channel group 4 Enable channel group 5 Disable channel group 5 Channel enable register Channel enable set register Channel enable clear register Channel 0 event endpoint Channel 0 task endpoint Channel 1 event endpoint Channel 1 task endpoint Channel 2 event endpoint Channel 2 task endpoint Channel 3 event endpoint Channel 3 task endpoint Channel 4 event endpoint Channel 4 task endpoint Channel 5 event endpoint Channel 5 task endpoint Channel 6 event endpoint Channel 6 task endpoint Channel 7 event endpoint Channel 7 task endpoint Channel 8 event endpoint Channel 8 task endpoint Channel 9 event endpoint Channel 9 task endpoint Channel 10 event endpoint Channel 10 task endpoint Channel 11 event endpoint Channel 11 task endpoint Channel 12 event endpoint Channel 12 task endpoint Channel 13 event endpoint Channel 13 task endpoint Channel 14 event endpoint Channel 14 task endpoint Channel 15 event endpoint Channel 15 task endpoint Channel 16 event endpoint Channel 16 task endpoint Channel 17 event endpoint Channel 17 task endpoint Channel 18 event endpoint Channel 18 task endpoint Channel 19 event endpoint Channel 19 task endpoint Channel group 0 Channel group 1 4452_021 v1.3 238 Peripherals Register CHG[2]

CHG[3]

CHG[4]

CHG[5]

FORK[0].TEP FORK[1].TEP FORK[2].TEP FORK[3].TEP FORK[4].TEP FORK[5].TEP FORK[6].TEP FORK[7].TEP FORK[8].TEP FORK[9].TEP FORK[10].TEP FORK[11].TEP FORK[12].TEP FORK[13].TEP FORK[14].TEP FORK[15].TEP FORK[16].TEP FORK[17].TEP FORK[18].TEP FORK[19].TEP FORK[20].TEP FORK[21].TEP FORK[22].TEP FORK[23].TEP FORK[24].TEP FORK[25].TEP FORK[26].TEP FORK[27].TEP FORK[28].TEP FORK[29].TEP FORK[30].TEP FORK[31].TEP Offset 0x808 0x80C 0x810 0x814 0x910 0x914 0x918 0x91C 0x920 0x924 0x928 0x92C 0x930 0x934 0x938 0x93C 0x940 0x944 0x948 0x94C 0x950 0x954 0x958 0x95C 0x960 0x964 0x968 0x96C 0x970 0x974 0x978 0x97C 0x980 0x984 0x988 0x98C Description Channel group 2 Channel group 3 Channel group 4 Channel group 5 Channel 0 task endpoint Channel 1 task endpoint Channel 2 task endpoint Channel 3 task endpoint Channel 4 task endpoint Channel 5 task endpoint Channel 6 task endpoint Channel 7 task endpoint Channel 8 task endpoint Channel 9 task endpoint Channel 10 task endpoint Channel 11 task endpoint Channel 12 task endpoint Channel 13 task endpoint Channel 14 task endpoint Channel 15 task endpoint Channel 16 task endpoint Channel 17 task endpoint Channel 18 task endpoint Channel 19 task endpoint Channel 20 task endpoint Channel 21 task endpoint Channel 22 task endpoint Channel 23 task endpoint Channel 24 task endpoint Channel 25 task endpoint Channel 26 task endpoint Channel 27 task endpoint Channel 28 task endpoint Channel 29 task endpoint Channel 30 task endpoint Channel 31 task endpoint Table 65: Register overview 6.15.2.1 TASKS_CHG[n].EN (n=0..5) Address offset: 0x000 + (n 0x8) Enable channel group n Bit number ID ID A Reset 0x00000000 AccessField W EN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Trigger 1 Trigger task Enable channel group n 4452_021 v1.3 239 Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Trigger 1 Trigger task Disable channel group n 6.15.2.2 TASKS_CHG[n].DIS (n=0..5) Address offset: 0x004 + (n 0x8) Disable channel group n Bit number ID ID A Reset 0x00000000 AccessField W DIS 6.15.2.3 CHEN Address offset: 0x500 Channel enable register Bit number ID Reset 0x00000000 ID AccessField Disabled Enabled Disabled Enabled Disabled Enabled Set Disabled Enabled Set 0 1 0 1 0 1 1 0 1 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-T RW CH[i] (i=0..19) Enable or disable channel i Value ID Value Description U-f RW CH[i] (i=20..31) Enable or disable channel i Disable channel Enable channel Disable channel Enable channel 6.15.2.4 CHENSET Address offset: 0x504 Channel enable set register Read: reads value of CH{i} field in CHEN register. Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-T RW CH[i] (i=0..19) Channel i enable set register. Writing '0' has no effect. Value ID Value Description U-f RW CH[i] (i=20..31) Channel i enable set register. Writing '0' has no effect. Read: channel disabled Read: channel enabled Write: Enable channel Read: channel disabled Read: channel enabled Write: Enable channel 6.15.2.5 CHENCLR Address offset: 0x508 Channel enable clear register 4452_021 v1.3 240 Peripherals Read: reads value of CH{i} field in CHEN register. Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-T RW CH[i] (i=0..19) Channel i enable clear register. Writing '0' has no effect. Value ID Value Description U-f RW CH[i] (i=20..31) Channel i enable clear register. Writing '0' has no effect. Disabled Enabled Clear Disabled Enabled Clear 0 1 1 0 1 1 Read: channel disabled Read: channel enabled Write: disable channel Read: channel disabled Read: channel enabled Write: disable channel 6.15.2.6 CH[n].EEP (n=0..19) Address offset: 0x510 + (n 0x8) Channel n event endpoint 6.15.2.7 CH[n].TEP (n=0..19) Address offset: 0x514 + (n 0x8) Channel n task endpoint ID ID A ID ID A 6.15.2.8 CHG[n] (n=0..5) Address offset: 0x800 + (n 0x4) Channel group n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW EEP A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pointer to event register. Accepts only addresses to registers from the Event group. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW TEP A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pointer to task register. Accepts only addresses to registers from the Task group. 4452_021 v1.3 241 Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit number ID Reset 0x00000000 ID AccessField A-T RW CH[i] (i=0..19) Include or exclude channel i Value ID Value Description U-f RW CH[i] (i=20..31) Include or exclude channel i Excluded Included Excluded Included 0 1 0 1 Exclude Include Exclude Include 6.15.2.9 FORK[n].TEP (n=0..19, 20..31) Address offset: 0x910 + (n 0x4) Channel n task endpoint Bit number ID ID A Reset 0x00000000 AccessField RW TEP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pointer to task register 6.16 PWM Pulse width modulation The pulse with modulation (PWM) module enables the generation of pulse width modulated signals on GPIO. The module implements an up or up-and-down counter with four PWM channels that drive assigned GPIOs. The following are the main features of a PWM module:

Programmable PWM frequency Up to four PWM channels with individual polarity and duty cycle values Edge or center-aligned pulses across PWM channels Multiple duty cycle arrays (sequences) defined in RAM Autonomous and glitch-free update of duty cycle values directly from memory through EasyDMA (no CPU involvement) Change of polarity, duty cycle, and base frequency possibly on every PWM period RAM sequences can be repeated or connected into loops 4452_021 v1.3 242 Peripherals DATA RAM PWM START STOP SEQSTART[0]

SEQSTART[1]

SEQ[n].REFRESH NEXTSTEP Sequence 0 Sequence 1 A M D y s a E Decoder STARTED STOPPED SEQSTARTED[0]

SEQSTARTED[1]

SEQEND[0]

SEQEND[1]

COMP0 PSEL.OUT[0]

COMP1 PSEL.OUT[1]

COMP2 PSEL.OUT[2]

COMP3 PSEL.OUT[3]

Carry/Reload Wave Counter COUNTERTOP PWM_CLK PRESCALER Figure 73: PWM module 6.16.1 Wave counter The wave counter is responsible for generating the pulses at a duty cycle that depends on the compare values, and at a frequency that depends on COUNTERTOP. There is one common 15-bit counter with four compare channels. Thus, all four channels will share the same period (PWM frequency), but can have individual duty cycle and polarity. The polarity is set by a value read from RAM (see figure Decoder memory access modes on page 246). Whether the counter counts up, or up and down, is controlled by the MODE register. The timer top value is controlled by the COUNTERTOP register. This register value, in conjunction with the selected PRESCALER of the PWM_CLK, will result in a given PWM period. A COUNTERTOP value smaller than the compare setting will result in a state where no PWM edges are generated. OUT[n] is held high, given that the polarity is set to FallingEdge. All compare registers are internal and can only be configured through decoder presented later. COUNTERTOP can be safely written at any time. Sampling follows the START task. If DECODER.LOAD=WaveForm, the register value is ignored and taken from RAM instead (see section Decoder with EasyDMA on page 246 for more details). If DECODER.LOAD is anything else than the WaveForm, it is sampled following a STARTSEQ[n] task and when loading a new value from RAM during a sequence playback. The following figure shows the counter operating in up mode (MODE=PWM_MODE_Up), with three PWM channels with the same frequency but different duty cycle:

4452_021 v1.3 243 Peripherals COUNTERTOP COMP1 COMP0 OUT[0]

OUT[1]

Figure 74: PWM counter in up mode example - FallingEdge polarity The counter is automatically reset to zero when COUNTERTOP is reached and OUT[n] will invert. OUT[n]

is held low if the compare value is 0 and held high if set to COUNTERTOP, given that the polarity is set to FallingEdge. Counter running in up mode results in pulse widths that are edge-aligned. The following is the code for the counter in up mode example:

uint16_t pwm_seq[4] = {PWM_CH0_DUTY, PWM_CH1_DUTY, PWM_CH2_DUTY, PWM_CH3_DUTY};

NRF_PWM0->PSEL.OUT[0] = (first_pin << PWM_PSEL_OUT_PIN_Pos) |

(PWM_PSEL_OUT_CONNECT_Connected <<

PWM_PSEL_OUT_CONNECT_Pos);

NRF_PWM0->PSEL.OUT[1] = (second_pin << PWM_PSEL_OUT_PIN_Pos) |

(PWM_PSEL_OUT_CONNECT_Connected <<

PWM_PSEL_OUT_CONNECT_Pos);

NRF_PWM0->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);

NRF_PWM0->MODE = (PWM_MODE_UPDOWN_Up << PWM_MODE_UPDOWN_Pos);

NRF_PWM0->PRESCALER = (PWM_PRESCALER_PRESCALER_DIV_1 <<

PWM_PRESCALER_PRESCALER_Pos);

NRF_PWM0->COUNTERTOP = (16000 << PWM_COUNTERTOP_COUNTERTOP_Pos); //1 msec NRF_PWM0->LOOP = (PWM_LOOP_CNT_Disabled << PWM_LOOP_CNT_Pos);

NRF_PWM0->DECODER = (PWM_DECODER_LOAD_Individual << PWM_DECODER_LOAD_Pos) |

(PWM_DECODER_MODE_RefreshCount << PWM_DECODER_MODE_Pos);

NRF_PWM0->SEQ[0].PTR = ((uint32_t)(pwm_seq) << PWM_SEQ_PTR_PTR_Pos);

NRF_PWM0->SEQ[0].CNT = ((sizeof(pwm_seq) / sizeof(uint16_t)) <<

PWM_SEQ_CNT_CNT_Pos);

NRF_PWM0->SEQ[0].REFRESH = 0;

NRF_PWM0->SEQ[0].ENDDELAY = 0;

NRF_PWM0->TASKS_SEQSTART[0] = 1;

When the counter is running in up mode, the following formula can be used to compute the PWM period and the step size:

PWM period: TPWM(Up)= TPWM_CLK

* COUNTERTOP 4452_021 v1.3 244 Peripherals Step width/Resolution: Tsteps= TPWM_CLK The following figure shows the counter operating in up-and-down mode

(MODE=PWM_MODE_UpAndDown), with two PWM channels with the same frequency but different duty cycle and output polarity:

COUNTERTOP COMP1 COMP0 OUT[0]

OUT[1]

Figure 75: PWM counter in up-and-down mode example The counter starts decrementing to zero when COUNTERTOP is reached and will invert the OUT[n] when compare value is hit for the second time. This results in a set of pulses that are center-aligned. The following is the code for the counter in up-and-down mode example:

uint16_t pwm_seq[4] = {PWM_CH0_DUTY, PWM_CH1_DUTY, PWM_CH2_DUTY, PWM_CH3_DUTY};

NRF_PWM0->PSEL.OUT[0] = (first_pin << PWM_PSEL_OUT_PIN_Pos) |

(PWM_PSEL_OUT_CONNECT_Connected <<

PWM_PSEL_OUT_CONNECT_Pos);

NRF_PWM0->PSEL.OUT[1] = (second_pin << PWM_PSEL_OUT_PIN_Pos) |

(PWM_PSEL_OUT_CONNECT_Connected <<

PWM_PSEL_OUT_CONNECT_Pos);

NRF_PWM0->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);

NRF_PWM0->MODE = (PWM_MODE_UPDOWN_UpAndDown << PWM_MODE_UPDOWN_Pos);

NRF_PWM0->PRESCALER = (PWM_PRESCALER_PRESCALER_DIV_1 <<

PWM_PRESCALER_PRESCALER_Pos);

NRF_PWM0->COUNTERTOP = (16000 << PWM_COUNTERTOP_COUNTERTOP_Pos); //1 msec NRF_PWM0->LOOP = (PWM_LOOP_CNT_Disabled << PWM_LOOP_CNT_Pos);

NRF_PWM0->DECODER = (PWM_DECODER_LOAD_Individual << PWM_DECODER_LOAD_Pos) |

(PWM_DECODER_MODE_RefreshCount << PWM_DECODER_MODE_Pos);

NRF_PWM0->SEQ[0].PTR = ((uint32_t)(pwm_seq) << PWM_SEQ_PTR_PTR_Pos);

NRF_PWM0->SEQ[0].CNT = ((sizeof(pwm_seq) / sizeof(uint16_t)) <<

PWM_SEQ_CNT_CNT_Pos);

NRF_PWM0->SEQ[0].REFRESH = 0;

NRF_PWM0->SEQ[0].ENDDELAY = 0;

NRF_PWM0->TASKS_SEQSTART[0] = 1;

4452_021 v1.3 245 Peripherals When the counter is running in up-and-down mode, the following formula can be used to compute the PWM period and the step size:

TPWM(Up And Down) = TPWM_CLK * 2 * COUNTERTOP Step width/Resolution: Tsteps = TPWM_CLK * 2 6.16.2 Decoder with EasyDMA The decoder uses EasyDMA to take PWM parameters stored in RAM and update the internal compare registers of the wave counter, based on the mode of operation. PWM parameters are organized into a sequence containing at least one half word (16 bit). Its most significant bit[15] denotes the polarity of the OUT[n] while bit[14:0] is the 15-bit compare value. Bit number Id Id A Reset 0x00000000 RW Field RW COMPARE B RW POLARITY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Duty cycle setting - value loaded to internal compare register Edge polarity of GPIO. RisingEdge FallingEdge 0 1 First edge within the PWM period is rising First edge within the PWM period is falling The DECODER register controls how the RAM content is interpreted and loaded into the internal compare registers. The LOAD field controls if the RAM values are loaded to all compare channels, or to update a group or all channels with individual values. The following figure illustrates how parameters stored in RAM are organized and routed to various compare channels in different modes:

DECODER.LOAD=Common DECODER.LOAD=Grouped DECODER.LOAD=Single SEQ[n].PTR COMPARE COMPARE COMP0 Increasing Data RAM address COMPARE

... COMPARE COMP0 COMP1 COMP2 COMP3 COMP0 COMP1 COMP2 COMP3 COMP0 COMP1 COMP2 COMP3 COMPARE COMPARE

... P O L P O L P O L COMP0 COMP1 COMP2 COMP3 P O L P O L P O L P O L COMPARE COMP1 COMPARE COMP2 COMPARE COMP0 COMP1 COMPARE COMP3 P O L P O L P O L P O L P O L P O L DECODER.LOAD=WaveForm COMPARE COMP0 COMPARE COMP1 COMPARE COMP2 TOP COUNTERTOP Figure 76: Decoder memory access modes A special mode of operation is available when DECODER.LOAD is set to WaveForm. In this mode, up to three PWM channels can be enabled - OUT[0] to OUT[2]. In RAM, four values are loaded at a time: the first, second and third location are used to load the values, and the fourth RAM location is used to load 4452_021 v1.3 246 Peripherals the COUNTERTOP register. This way one can have up to three PWM channels with a frequency base that changes on a per PWM period basis. This mode of operation is useful for arbitrary wave form generation in applications, such as LED lighting. The register SEQ[n].REFRESH=N (one per sequence n=0 or 1) will instruct a new RAM stored pulse width value on every (N+1)th PWM period. Setting the register to zero will result in a new duty cycle update every PWM period, as long as the minimum PWM period is observed. Note that registers SEQ[n].REFRESH and SEQ[n].ENDDELAY are ignored when DECODER.MODE=NextStep. The next value is loaded upon every received NEXTSTEP task. SEQ[n].PTR is the pointer used to fetch COMPARE values from RAM. If the SEQ[n].PTR is not pointing to a RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. After the SEQ[n].PTR is set to the desired RAM location, the SEQ[n].CNT register must be set to number of 16-bit half words in the sequence. It is important to observe that the Grouped mode requires one half word per group, while the Single mode requires one half word per channel, thus increasing the RAM size occupation. If PWM generation is not running when the SEQSTART[n] task is triggered, the task will load the first value from RAM and then start the PWM generation. A SEQSTARTED[n] event is generated as soon as the EasyDMA has read the first PWM parameter from RAM and the wave counter has started executing it. When LOOP.CNT=0, sequence n=0 or 1 is played back once. After the last value in the sequence has been loaded and started executing, a SEQEND[n] event is generated. The PWM generation will then continue with the last loaded value. The following figure illustrates an example of such simple playback:

SEQ[0].CNT=4, SEQ[0].REFRESH=0, SEQ[0].ENDDELAY=0, LOOP.CNT=0 Continues with last setting SEQ[0].PTR P O L COMPARE 0 P O L COMPARE 1 P O L COMPARE 2 P O L COMPARE 3 Event/Tasks PWM pulse period SEQSTART[0]

SEQSTARTED[0]

SEQEND[0]

Figure 77: Simple sequence example 4452_021 v1.3 247 Figure depicts the source code used for configuration and timing details in a sequence where only sequence 0 is used and only run once with a new PWM duty cycle for each period. Peripherals NRF_PWM0->PSEL.OUT[0] = (first_pin << PWM_PSEL_OUT_PIN_Pos) |

(PWM_PSEL_OUT_CONNECT_Connected <<

PWM_PSEL_OUT_CONNECT_Pos);

NRF_PWM0->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);

NRF_PWM0->MODE = (PWM_MODE_UPDOWN_Up << PWM_MODE_UPDOWN_Pos);

NRF_PWM0->PRESCALER = (PWM_PRESCALER_PRESCALER_DIV_1 <<

PWM_PRESCALER_PRESCALER_Pos);

NRF_PWM0->COUNTERTOP = (16000 << PWM_COUNTERTOP_COUNTERTOP_Pos); //1 msec NRF_PWM0->LOOP = (PWM_LOOP_CNT_Disabled << PWM_LOOP_CNT_Pos);

NRF_PWM0->DECODER = (PWM_DECODER_LOAD_Common << PWM_DECODER_LOAD_Pos) |

(PWM_DECODER_MODE_RefreshCount << PWM_DECODER_MODE_Pos);

NRF_PWM0->SEQ[0].PTR = ((uint32_t)(seq0_ram) << PWM_SEQ_PTR_PTR_Pos);

NRF_PWM0->SEQ[0].CNT = ((sizeof(seq0_ram) / sizeof(uint16_t)) <<

PWM_SEQ_CNT_CNT_Pos);

NRF_PWM0->SEQ[0].REFRESH = 0;

NRF_PWM0->SEQ[0].ENDDELAY = 0;

NRF_PWM0->TASKS_SEQSTART[0] = 1;

To completely stop the PWM generation and force the associated pins to a defined state, a STOP task can be triggered at any time. A STOPPED event is generated when the PWM generation has stopped at the end of currently running PWM period, and the pins go into their idle state as defined in GPIO OUT register. PWM generation can then only be restarted through a SEQSTART[n] task. SEQSTART[n] will resume PWM generation after having loaded the first value from the RAM buffer defined in the SEQ[n].PTR register. The table below indicates when specific registers get sampled by the hardware. Care should be taken when updating these registers to avoid that values are applied earlier than expected. 4452_021 v1.3 248 Peripherals Register Taken into account by hardware Recommended (safe) update SEQ[n].PTR When sending the SEQSTART[n] task After having received the SEQSTARTED[n] event SEQ[n].CNT When sending the SEQSTART[n] task After having received the SEQSTARTED[n] event SEQ[0].ENDDELAY When sending the SEQSTART[0] task Before starting sequence [0] through a SEQSTART[0] task Every time a new value from sequence [0] has been loaded from When no more value from sequence [0] gets loaded from RAM RAM and gets applied to the Wave Counter (indicated by the

(indicated by the SEQEND[0] event) PWMPERIODEND event) At any time during sequence [1] (which starts when the SEQSTARTED[1] event is generated) SEQ[1].ENDDELAY When sending the SEQSTART[1] task Before starting sequence [1] through a SEQSTART[1] task Every time a new value from sequence [1] has been loaded from When no more value from sequence [1] gets loaded from RAM RAM and gets applied to the Wave Counter (indicated by the

(indicated by the SEQEND[1] event) PWMPERIODEND event) At any time during sequence [0] (which starts when the SEQSTARTED[0] event is generated) SEQ[0].REFRESH When sending the SEQSTART[0] task Before starting sequence [0] through a SEQSTART[0] task Every time a new value from sequence [0] has been loaded from At any time during sequence [1] (which starts when the RAM and gets applied to the Wave Counter (indicated by the SEQSTARTED[1] event is generated) SEQ[1].REFRESH When sending the SEQSTART[1] task Before starting sequence [1] through a SEQSTART[1] task Every time a new value from sequence [1] has been loaded from At any time during sequence [0] (which starts when the RAM and gets applied to the Wave Counter (indicated by the SEQSTARTED[0] event is generated) PWMPERIODEND event) PWMPERIODEND event) COUNTERTOP In DECODER.LOAD=WaveForm: this register is ignored. Before starting PWM generation through a SEQSTART[n] task In all other LOAD modes: at the end of current PWM period After a STOP task has been triggered, and the STOPPED event has

(indicated by the PWMPERIODEND event) been received. MODE Immediately Before starting PWM generation through a SEQSTART[n] task After a STOP task has been triggered, and the STOPPED event has DECODER Immediately Before starting PWM generation through a SEQSTART[n] task After a STOP task has been triggered, and the STOPPED event has PRESCALER Immediately Before starting PWM generation through a SEQSTART[n] task After a STOP task has been triggered, and the STOPPED event has LOOP Immediately Before starting PWM generation through a SEQSTART[n] task After a STOP task has been triggered, and the STOPPED event has been received. been received. been received. been received. PSEL.OUT[n]

Immediately Before enabling the PWM instance through the ENABLE register Table 66: When to safely update PWM registers Note: SEQ[n].REFRESH and SEQ[n].ENDDELAY are ignored at the end of a complex sequence, indicated by a LOOPSDONE event. The reason for this is that the last value loaded from RAM is maintained until further action from software (restarting a new sequence, or stopping PWM generation). A more complex example, where LOOP.CNT>0, is shown in the following figure:

4452_021 v1.3 249 Peripherals SEQ[0].CNT=2, SEQ[1].CNT=3, SEQ[0].REFRESH=1, SEQ[1].REFRESH=0, SEQ[0].ENDDELAY=1, SEQ[1].ENDDELAY=0, LOOP.CNT=1 SEQ[0].PTR COMPARE P O L P O L COMPARE Event/Tasks PWM clock period

(continued below) SEQSTART[0]

SEQSTARTED[0]

SEQEND[0]

SEQ[1].PTR COMPARE COMPARE P O L P O L 1 PWM period SEQ[0].ENDDELAY=1 PWM generation maintains last played value

(continuation) Event/Tasks SEQSTARTED[1]

SEQEND[1]

LOOPSDONE Figure 78: Example using two sequences In this case, an automated playback takes place, consisting of SEQ[0], delay 0, SEQ[1], delay 1, then again SEQ[0], etc. The user can choose to start a complex playback with SEQ[0] or SEQ[1] through sending the SEQSTART[0] or SEQSTART[1] task. The complex playback always ends with delay 1. The two sequences 0 and 1 are defined by the addresses of value tables in RAM (pointed to by SEQ[n].PTR) and the buffer size (SEQ[n].CNT). The rate at which a new value is loaded is defined individually for each sequence by SEQ[n].REFRESH. The chaining of sequence 1 following the sequence 0 is implicit, the LOOP.CNT register allows the chaining of sequence 1 to sequence 0 for a determined number of times. In other words, it allows to repeat a complex sequence a number of times in a fully automated way. In the following code example, sequence 0 is defined with SEQ[0].REFRESH set to 1, meaning that a new PWM duty cycle is pushed every second PWM period. This complex sequence is started with the SEQSTART[0] task, so SEQ[0] is played first. Since SEQ[0].ENDDELAY=1 there will be one PWM period delay between last period on sequence 0 and the first period on sequence 1. Since SEQ[1].ENDDELAY=0 there is no delay 1, so SEQ[0] would be started immediately after the end of SEQ[1]. However, as LOOP.CNT is 4452_021 v1.3 250 1, the playback stops after having played SEQ[1] only once, and both SEQEND[1] and LOOPSDONE are generated (their order is not guaranteed in this case). Peripherals NRF_PWM0->PSEL.OUT[0] = (first_pin << PWM_PSEL_OUT_PIN_Pos) |

(PWM_PSEL_OUT_CONNECT_Connected <<

PWM_PSEL_OUT_CONNECT_Pos);

NRF_PWM0->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);

NRF_PWM0->MODE = (PWM_MODE_UPDOWN_Up << PWM_MODE_UPDOWN_Pos);

NRF_PWM0->PRESCALER = (PWM_PRESCALER_PRESCALER_DIV_1 <<

PWM_PRESCALER_PRESCALER_Pos);

NRF_PWM0->COUNTERTOP = (16000 << PWM_COUNTERTOP_COUNTERTOP_Pos); //1 msec NRF_PWM0->LOOP = (1 << PWM_LOOP_CNT_Pos);

NRF_PWM0->DECODER = (PWM_DECODER_LOAD_Common << PWM_DECODER_LOAD_Pos) |

(PWM_DECODER_MODE_RefreshCount << PWM_DECODER_MODE_Pos);

NRF_PWM0->SEQ[0].PTR = ((uint32_t)(seq0_ram) << PWM_SEQ_PTR_PTR_Pos);

NRF_PWM0->SEQ[0].CNT = ((sizeof(seq0_ram) / sizeof(uint16_t)) <<

PWM_SEQ_CNT_CNT_Pos);

NRF_PWM0->SEQ[0].REFRESH = 1;

NRF_PWM0->SEQ[0].ENDDELAY = 1;

NRF_PWM0->SEQ[1].PTR = ((uint32_t)(seq1_ram) << PWM_SEQ_PTR_PTR_Pos);

NRF_PWM0->SEQ[1].CNT = ((sizeof(seq1_ram) / sizeof(uint16_t)) <<

PWM_SEQ_CNT_CNT_Pos);

NRF_PWM0->SEQ[1].REFRESH = 0;

NRF_PWM0->SEQ[1].ENDDELAY = 0;

NRF_PWM0->TASKS_SEQSTART[0] = 1;

The decoder can also be configured to asynchronously load new PWM duty cycle. If the DECODER.MODE register is set to NextStep, then the NEXTSTEP task will cause an update of internal compare registers on the next PWM period. The following figures provide an overview of each part of an arbitrary sequence, in various modes

(LOOP.CNT=0 and LOOP.CNT>0). In particular, the following are represented:

Initial and final duty cycle on the PWM output(s) Chaining of SEQ[0] and SEQ[1] if LOOP.CNT>0 Influence of registers on the sequence Events generated during a sequence DMA activity (loading of next value and applying it to the output(s)) 4452_021 v1.3 251 Peripherals last loaded duty cycle maintained A L E D D N E

0 Q E S Y T N C

0 Q E S last loaded duty cycle maintained 100% duty cycle Previously loaded duty cycle 0% duty cycle New value load

0 D N E Q E S _ S T N E V E

0 T R A T S Q E S _ S K S A T

0 D E T R A T S Q E S _ S T N E V E Figure 79: Single shot (LOOP.CNT=0) Note: The single-shot example also applies to SEQ[1]. Only SEQ[0] is represented for simplicity. Loop counter LOOP.CNT

(LOOP.CNT - 1)

... 1 A L E D D N E

0 Q E S T N C

1 Q E Y S A L E D D N E

1 Q E S Y T N C

0 Q E S A L E D D N E

0 Q E S T N C

1 Q E Y S T N C

0 Q E S A L E D D N E

0 Q E S T N C

1 Q E Y S A L E D D N E

1 Q E S Y T N C

0 Q E S 100% duty cycle Previously loaded duty cycle 0% duty cycle New value load

0 T R A T S Q E S _ S K S A T

0 D E T R A T S Q E S _ S T N E V E

0 D N E Q E S _ S T N E V E

1 D N E Q E S _ S T N E V E

1 D E T R A T S Q E S _ S T N E V E

0 D E T R A T S Q E S _ S T N E V E

0 D N E Q E S _ S T N E V E

1 D N E Q E S _ S T N E V E

1 D E T R A T S Q E S _ S T N E V E

0 D E T R A T S Q E S _ S T N E V E

0 D N E Q E S _ S T N E V E

1 D N E Q E S _ S T N E V E E N O D S P O O L _ S T N E V E

1 D E T R A T S Q E S _ S T N E V E Figure 80: Complex sequence (LOOP.CNT>0) starting with SEQ[0]

4452_021 v1.3 252 Loop counter LOOP.CNT

(LOOP.CNT - 1)

... 1 A L E D D N E

1 Q E S Y T N C

1 Q E S A L E D D N E

0 Q E S T N C

1 Q E Y S T N C

0 Q E S A L E D D N E

0 Q E S T N C

1 Q E Y S A L E D D N E

1 Q E S Y T N C

0 Q E S 100% duty cycle Previously loaded duty cycle 0% duty cycle New value load Peripherals last loaded duty cycle maintained

1 D N E Q E S _ S T N E V E

1 T R A T S Q E S _ S K S A T

1 D E T R A T S Q E S _ S T N E V E

0 D E T R A T S Q E S _ S T N E V E

0 D N E Q E S _ S T N E V E

1 D N E Q E S _ S T N E V E

1 D E T R A T S Q E S _ S T N E V E

0 D E T R A T S Q E S _ S T N E V E

0 D N E Q E S _ S T N E V E

1 D N E Q E S _ S T N E V E E N O D S P O O L _ S T N E V E

1 D E T R A T S Q E S _ S T N E V E Figure 81: Complex sequence (LOOP.CNT>0) starting with SEQ[1]

Note: If a sequence is in use in a simple or complex sequence, it must have a length of SEQ[n].CNT

> 0. 6.16.3 Limitations Previous compare value is repeated if the PWM period is shorter than the time it takes for the EasyDMA to retrieve from RAM and update the internal compare registers. This is to ensure a glitch-free operation even for very short PWM periods. 6.16.4 Pin configuration The OUT[n] (n=0..3) signals associated with each PWM channel are mapped to physical pins according to the configuration of PSEL.OUT[n] registers. If PSEL.OUT[n].CONNECT is set to Disconnected, the associated PWM module signal will not be connected to any physical pins. The PSEL.OUT[n] registers and their configurations are used as long as the PWM module is enabled and the PWM generation active (wave counter started). They are retained only as long as the device is in System ON mode (see section POWER for more information about power modes). To ensure correct behavior in the PWM module, the pins that are used must be configured in the GPIO peripheral in the following way before the PWM module is enabled:

PWM signal OUT[n]

PWM pin Direction Output value Comment As specified in PSEL.OUT[n]

Output 0 Idle state defined in GPIO OUT

(n=0..3) register Table 67: Recommended GPIO configuration before starting PWM generation 4452_021 v1.3 253 Peripherals The idle state of a pin is defined by the OUT register in the GPIO module, to ensure that the pins used by the PWM module are driven correctly. If PWM generation is stopped by triggering a STOP task, the PWM module itself is temporarily disabled or the device temporarily enters System OFF. This configuration must be retained in the GPIO for the selected pins (I/Os) for as long as the PWM module is supposed to be connected to an external PWM circuit. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. Base address Peripheral Instance Description Configuration 6.16.5 Registers 0x4001C000 0x40021000 0x40022000 0x4002D000 PWM PWM PWM PWM PWM0 PWM1 PWM2 PWM3 Pulse width modulation unit 0 Pulse width modulation unit 1 Pulse width modulation unit 2 Pulse width modulation unit 3 Table 68: Instances Register TASKS_STOP Offset 0x004 Description sequence playback Stops PWM pulse generation on all channels at the end of current PWM period, and stops TASKS_SEQSTART[0]

0x008 Loads the first PWM value on all enabled channels from sequence 0, and starts playing TASKS_SEQSTART[1]

0x00C Loads the first PWM value on all enabled channels from sequence 1, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. that sequence at the rate defined in SEQ[1]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. TASKS_NEXTSTEP 0x010 Steps by one value in the current sequence on all enabled channels if EVENTS_STOPPED EVENTS_SEQSTARTED[0]

EVENTS_SEQSTARTED[1]

EVENTS_SEQEND[0]

DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. Response to STOP task, emitted when PWM pulses are no longer generated First PWM period started on sequence 0 First PWM period started on sequence 1 Emitted at end of every sequence 0, when last value from RAM has been applied to wave EVENTS_SEQEND[1]

0x114 Emitted at end of every sequence 1, when last value from RAM has been applied to wave counter counter EVENTS_PWMPERIODEND Emitted at the end of each PWM period EVENTS_LOOPSDONE Concatenated sequences have been played the amount of times defined in LOOP.CNT SHORTS INTEN INTENSET INTENCLR ENABLE MODE COUNTERTOP PRESCALER DECODER LOOP SEQ[0].PTR SEQ[0].CNT SEQ[0].REFRESH SEQ[0].ENDDELAY SEQ[1].PTR 4452_021 v1.3 Shortcuts between local events and tasks Enable or disable interrupt Enable interrupt Disable interrupt PWM module enable register Selects operating mode of the wave counter Value up to which the pulse generator counter counts Configuration for PWM_CLK Configuration of the decoder Number of playbacks of a loop Beginning address in RAM of this sequence Number of values (duty cycles) in this sequence Time added after the sequence Beginning address in RAM of this sequence 254 Number of additional PWM periods between samples loaded into compare register 0x104 0x108 0x10C 0x110 0x118 0x11C 0x200 0x300 0x304 0x308 0x500 0x504 0x508 0x50C 0x510 0x514 0x520 0x524 0x528 0x52C 0x540 Peripherals Description Number of values (duty cycles) in this sequence Number of additional PWM periods between samples loaded into compare register Time added after the sequence Output pin select for PWM channel 0 Output pin select for PWM channel 1 Output pin select for PWM channel 2 Output pin select for PWM channel 3 Table 69: Register overview Register SEQ[1].CNT SEQ[1].REFRESH SEQ[1].ENDDELAY PSEL.OUT[0]

PSEL.OUT[1]

PSEL.OUT[2]

PSEL.OUT[3]

Offset 0x544 0x548 0x54C 0x560 0x564 0x568 0x56C 6.16.5.1 TASKS_STOP Address offset: 0x004 ID ID A ID ID A Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback Trigger 1 Trigger task 6.16.5.2 TASKS_SEQSTART[n] (n=0..1) Address offset: 0x008 + (n 0x4) Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_SEQSTART Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. Trigger 1 Trigger task 6.16.5.3 TASKS_NEXTSTEP Address offset: 0x010 Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. A A 4452_021 v1.3 255 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_NEXTSTEP Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. Trigger 1 Trigger task 6.16.5.4 EVENTS_STOPPED Address offset: 0x104 Response to STOP task, emitted when PWM pulses are no longer generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_STOPPED Response to STOP task, emitted when PWM pulses are no NotGenerated Generated longer generated Event not generated Event generated 6.16.5.5 EVENTS_SEQSTARTED[n] (n=0..1) Address offset: 0x108 + (n 0x4) First PWM period started on sequence n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_SEQSTARTED First PWM period started on sequence n NotGenerated Generated Event not generated Event generated 6.16.5.6 EVENTS_SEQEND[n] (n=0..1) Address offset: 0x110 + (n 0x4) Emitted at end of every sequence n, when last value from RAM has been applied to wave counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_SEQEND Emitted at end of every sequence n, when last value from NotGenerated Generated RAM has been applied to wave counter Event not generated Event generated ID ID A ID ID A ID ID A ID ID A A A A A 0 1 0 1 0 1 4452_021 v1.3 256 Peripherals 6.16.5.7 EVENTS_PWMPERIODEND Address offset: 0x118 Emitted at the end of each PWM period ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_PWMPERIODEND Emitted at the end of each PWM period NotGenerated Generated Event not generated Event generated 6.16.5.8 EVENTS_LOOPSDONE Address offset: 0x11C Concatenated sequences have been played the amount of times defined in LOOP.CNT Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_LOOPSDONE Concatenated sequences have been played the amount of NotGenerated Generated times defined in LOOP.CNT Event not generated Event generated A A 6.16.5.9 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW SEQEND0_STOP Shortcut between event SEQEND[0] and task STOP B RW SEQEND1_STOP Shortcut between event SEQEND[1] and task STOP C RW LOOPSDONE_SEQSTART0 Shortcut between event LOOPSDONE and task SEQSTART[0]

D RW LOOPSDONE_SEQSTART1 Shortcut between event LOOPSDONE and task SEQSTART[1]

E RW LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled 4452_021 v1.3 257 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H G F E D C B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event STOPPED C-D RW SEQSTARTED[i] (i=0..1) Enable or disable interrupt for event SEQSTARTED[i]

E-F RW SEQEND[i] (i=0..1) Enable or disable interrupt for event SEQEND[i]

G RW PWMPERIODEND Enable or disable interrupt for event PWMPERIODEND H RW LOOPSDONE Enable or disable interrupt for event LOOPSDONE 6.16.5.10 INTEN Address offset: 0x300 Enable or disable interrupt Bit number ID ID B Reset 0x00000000 AccessField RW STOPPED 6.16.5.11 INTENSET Address offset: 0x304 Enable interrupt Bit number ID ID B Reset 0x00000000 AccessField RW STOPPED Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H G F E D C B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event STOPPED C-D RW SEQSTARTED[i] (i=0..1) Write '1' to enable interrupt for event SEQSTARTED[i]

E-F RW SEQEND[i] (i=0..1) Write '1' to enable interrupt for event SEQEND[i]

G RW PWMPERIODEND Write '1' to enable interrupt for event PWMPERIODEND H RW LOOPSDONE Write '1' to enable interrupt for event LOOPSDONE 4452_021 v1.3 258 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Peripherals H G F E D C B Value ID Enabled Value 1 Description Read: Enabled Bit number ID Reset 0x00000000 ID AccessField 6.16.5.12 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID B Reset 0x00000000 AccessField RW STOPPED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H G F E D C B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event STOPPED C-D RW SEQSTARTED[i] (i=0..1) Write '1' to disable interrupt for event SEQSTARTED[i]

E-F RW SEQEND[i] (i=0..1) Write '1' to disable interrupt for event SEQEND[i]

G RW PWMPERIODEND Write '1' to disable interrupt for event PWMPERIODEND H RW LOOPSDONE Write '1' to disable interrupt for event LOOPSDONE Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled 6.16.5.13 ENABLE Address offset: 0x500 PWM module enable register Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 6.16.5.14 MODE Address offset: 0x504 Selects operating mode of the wave counter 4452_021 v1.3 259 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable PWM module Disabled Enable Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW UPDOWN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Up UpAndDown 0 1 Selects up mode or up-and-down mode for the counter Up counter, edge-aligned PWM duty cycle Up and down counter, center-aligned PWM duty cycle Peripherals A 6.16.5.15 COUNTERTOP Address offset: 0x508 Value up to which the pulse generator counter counts Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A Reset 0x000003FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 AccessField Value ID Value Description RW COUNTERTOP

[3..32767]

Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. 6.16.5.16 PRESCALER Address offset: 0x50C Configuration for PWM_CLK Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW PRESCALER DIV_1 DIV_2 DIV_4 DIV_8 DIV_16 DIV_32 DIV_64 DIV_128 0 1 2 3 4 5 6 7 Prescaler of PWM_CLK Divide by 1 (16 MHz) Divide by 2 (8 MHz) Divide by 4 (4 MHz) Divide by 8 (2 MHz) Divide by 16 (1 MHz) Divide by 32 (500 kHz) Divide by 64 (250 kHz) Divide by 128 (125 kHz) 6.16.5.17 DECODER Address offset: 0x510 Configuration of the decoder 4452_021 v1.3 260 Bit number ID ID A Reset 0x00000000 AccessField RW LOAD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Peripherals B A A Common Grouped Individual WaveForm 0 1 2 3 0 1 How a sequence is read from RAM and spread to the compare register 1st half word (16-bit) used in all PWM channels 0..3 1st half word (16-bit) used in channel 0..1; 2nd word in 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in channel 2..3 COUNTERTOP compare registers compare registers B RW MODE Selects source for advancing the active sequence RefreshCount SEQ[n].REFRESH is used to determine loading internal NextStep NEXTSTEP task causes a new value to be loaded to internal 6.16.5.18 LOOP Address offset: 0x514 Number of playbacks of a loop ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description Disabled 0 Looping disabled (stop at the end of the sequence) Number of playbacks of pattern cycles 6.16.5.19 SEQ[n].PTR (n=0..1) Address offset: 0x520 + (n 0x20) Beginning address in RAM of this sequence Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Reset 0x00000000 AccessField RW PTR Beginning address in RAM of this sequence Note: See the memory chapter for details about which memories are available for EasyDMA. 6.16.5.20 SEQ[n].CNT (n=0..1) Address offset: 0x524 + (n 0x20) Number of values (duty cycles) in this sequence 4452_021 v1.3 261 ID ID A ID ID A ID ID A ID A B C Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A Value ID Value Description Disabled 0 Sequence is disabled, and shall not be started as it is empty Number of values (duty cycles) in this sequence 6.16.5.21 SEQ[n].REFRESH (n=0..1) Address offset: 0x528 + (n 0x20) Number of additional PWM periods between samples loaded into compare register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Reset 0x00000001 AccessField RW CNT Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) Continuous 0 Update every PWM period 6.16.5.22 SEQ[n].ENDDELAY (n=0..1) Address offset: 0x52C + (n 0x20) Time added after the sequence Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW CNT A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Time added after the sequence in PWM periods 6.16.5.23 PSEL.OUT[n] (n=0..3) Address offset: 0x560 + (n 0x4) Output pin select for PWM channel n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

[0..31]

[0..1]

C 1 0 Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 6.17 QDEC Quadrature decoder The Quadrature decoder (QDEC) provides buffered decoding of quadrature-encoded sensor signals. It is suitable for mechanical and optical sensors. 4452_021 v1.3 262 Peripherals The sample period and accumulation are configurable to match application requirements. The QDEC provides the following:

Digital waveform decoding from off-chip quadrature encoder Sample accumulation eliminating hard real-time requirements to be enforced on application Optional input de-bounce filters. Optional LED output signal for optical encoders ACCREAD ACCDBLREAD ACC

SAMPLE ACCDBL

Quadrature decoder IO router On-chip Off-chip Phase A Phase B LED Mechanical to electrical Mechanical device Quadrature Encoder Figure 82: Quadrature decoder configuration 6.17.1 Sampling and decoding The QDEC decodes the output from an incremental motion encoder by sampling the QDEC phase input pins (A and B). The off-chip quadrature encoder is an incremental motion encoder outputting two waveforms, phase A and phase B. The two output waveforms are always 90 degrees out of phase, meaning that one always changes level before the other. The direction of movement is indicated by the waveform that changes level first. Invalid transitions may occur, meaning the two waveforms simultaneously switch. This may occur if the wheel rotates too fast relative to the sample rate set for the decoder. The QDEC decodes the output from the off-chip encoder by sampling the QDEC phase input pins (A and B) at a fixed rate as specified in the SAMPLEPER register. If the SAMPLEPER value needs to be changed, the QDEC shall be stopped using the STOP task. SAMPLEPER can be then changed upon receiving the STOPPED event, and QDEC can be restarted using the START task. Failing to do so may result in unpredictable behavior. 4452_021 v1.3 263 Peripherals It is good practice to only change registers LEDPOL, REPORTPER, DBFEN, and LEDPRE when the QDEC is stopped. When started, the decoder continuously samples the two input waveforms and decodes these by comparing the current sample pair (n) with the previous sample pair (n-1). The decoding of the sample pairs is described in the table below. Previous Current SAMPLE ACC operation ACCDBL Description sample pair(n samples register operation

- 1) A pair(n) B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1

-1 2

-1 0 2 1 1 2 0

-1 2

-1 1 0 No change No change No movement Increment No change Movement in positive direction Decrement No change Movement in negative direction No change Increment Error: Double transition Decrement No change Movement in negative direction No change No change No movement No change Increment Error: Double transition Increment No change Movement in positive direction Increment No change Movement in positive direction No change Increment Error: Double transition No change No change No movement Decrement No change Movement in negative direction No change Increment Error: Double transition Decrement No change Movement in negative direction Increment No change Movement in positive direction No change No change No movement Table 70: Sampled value encoding 6.17.2 LED output The LED output follows the sample period. The LED is switched on for a set period before sampling and then switched off immediately after. The period the LED is switched on before sampling is given in the LEDPRE register. The LED output pin polarity is specified in the LEDPOL register. When using off-chip mechanical encoders not requiring an LED, the LED output can be disabled by writing value 'Disconnected' to the CONNECT field of the PSEL.LED register. In this case, the QDEC will not acquire access to a pin for the LED output. 6.17.3 Debounce filters Each of the two-phase inputs have digital debounce filters. When enabled through the DBFEN register, the filter inputs are sampled at a fixed 1 MHz frequency during the entire sample period (which is specified in the SAMPLEPER register). The filters require all of the samples within this sample period to equal before the input signal is accepted and transferred to the output of the filter. As a result, only input signal with a steady state longer than twice the period specified in SAMPLEPER are guaranteed to pass through the filter. Any signal with a steady state shorter than SAMPLEPER will always be suppressed by the filter. It is assumed that the frequency during the debounce period never exceeds 500 kHz (as required by the Nyquist theorem when using a 1 MHz sample frequency). The LED will always be ON when the debounce filters are enabled, as the inputs in this case will be sampled continuously. 4452_021 v1.3 264 Peripherals When the debounce filters are enabled, displacements reported by the QDEC peripheral are delayed by one SAMPLEPER period. 6.17.4 Accumulators The quadrature decoder contains two accumulator registers, ACC and ACCDBL. These registers accumulate valid motion sample values and the number of detected invalid samples (double transitions), respectively. The ACC register accumulates all valid values (1/-1) written to the SAMPLE register. This can be useful for preventing hard real-time requirements from being enforced on the application. When using the ACC register, the application can fetch data when necessary instead of reading all SAMPLE register output. The ACC register holds the relative movement of the external mechanical device from the previous clearing of the ACC register. Sample values indicating a double transition (2) will not be accumulated in the ACC register. An ACCOF event is generated if the ACC receives a SAMPLE value that would cause the register to overflow or underflow. Any SAMPLE value that would cause an ACC overflow or underflow will be discarded, but any samples that do not cause the ACC to overflow or underflow will still be accepted. The accumulator ACCDBL accumulates the number of detected double transitions since the previous clearing of the ACCDBL register. The ACC and ACCDBL registers can be cleared by the READCLRACC and subsequently read using the ACCREAD and ACCDBLREAD registers. The ACC register can be separately cleared by the RDCLRACC and subsequently read using the ACCREAD registers. The ACCDBL register can be separately cleared by the RDCLRDBL and subsequently read using the ACCDBLREAD registers. The REPORTPER register allows automated capture of multiple samples before sending an event. When a non-null displacement is captured and accumulated, a REPORTRDY event is sent. When one or more double-displacements are captured and accumulated, a DBLRDY event is sent. The REPORTPER field in this register determines how many samples must be accumulated before the contents are evaluated and a REPORTRDY or DBLRDY event is sent. Using the RDCLRACC task (manually sent upon receiving the event, or using the DBLRDY_RDCLRACC shortcut), ACCREAD can then be read. When a double transition has been captured and accumulated, a DBLRDY event is sent. Using the RDCLRDBL task (manually sent upon receiving the event, or using the DBLRDY_RDCLRDBL shortcut), ACCDBLREAD can then be read. 6.17.5 Output/input pins The QDEC uses a three-pin interface to the off-chip quadrature encoder. These pins are acquired when the QDEC is enabled in the ENABLE register. The pins acquired by the QDEC cannot be written by the CPU, but they can still be read by the CPU. The pin numbers used for the QDEC are selected using the PSEL.n registers. 6.17.6 Pin configuration The Phase A, Phase B, and LED signals are mapped to physical pins according to the configuration specified in the PSEL.A, PSEL.B, and PSEL.LED registers respectively. If the CONNECT field value 'Disconnected' is specified in any of these registers, the associated signal will not be connected to any physical pin. The PSEL.A, PSEL.B, and PSEL.LED registers and their configurations are only used as long as the QDEC is enabled, and retained only as long as the device is in ON mode. 4452_021 v1.3 265 Peripherals When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register. To secure correct behavior in the QDEC, the pins used by the QDEC must be configured in the GPIO peripheral as described in GPIO configuration before enabling peripheral on page 266 before enabling the QDEC. This configuration must be retained in the GPIO for the selected I/Os as long as the QDEC is enabled. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. QDEC signal QDEC pin Direction Comment Phase A Phase B LED As specified in PSEL.A As specified in PSEL.B As specified in PSEL.LED Input Input Input Output value Not applicable Not applicable Not applicable Table 71: GPIO configuration before enabling peripheral 6.17.7 Registers Base address Peripheral Instance Description Configuration 0x40012000 QDEC QDEC Quadrature decoder Event being generated for every new sample value written to the SAMPLE register Table 72: Instances Offset Description Task starting the quadrature decoder Task stopping the quadrature decoder Read and clear ACC and ACCDBL Read and clear ACC Read and clear ACCDBL Non-null report ready ACC or ACCDBL register overflow Double displacement(s) detected QDEC has been stopped Shortcuts between local events and tasks Enable interrupt Disable interrupt Enable the quadrature decoder LED output pin polarity Sample period Motion sample value Register TASKS_START TASKS_STOP TASKS_READCLRACC TASKS_RDCLRACC TASKS_RDCLRDBL EVENTS_SAMPLERDY EVENTS_REPORTRDY EVENTS_ACCOF EVENTS_DBLRDY EVENTS_STOPPED SHORTS INTENSET INTENCLR ENABLE LEDPOL SAMPLEPER SAMPLE REPORTPER ACC ACCREAD PSEL.LED PSEL.A PSEL.B DBFEN LEDPRE ACCDBL 0x000 0x004 0x008 0x00C 0x010 0x100 0x104 0x108 0x10C 0x110 0x200 0x304 0x308 0x500 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0x520 0x524 0x528 0x540 0x544 4452_021 v1.3 266 Number of samples to be taken before REPORTRDY and DBLRDY events can be generated Register accumulating the valid transitions Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task Pin select for LED signal Pin select for A signal Pin select for B signal Enable input debounce filters Time period the LED is switched ON prior to sampling Register accumulating the number of detected double transitions Peripherals Register ACCDBLREAD Offset 0x548 Description Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task Table 73: Register overview 6.17.7.1 TASKS_START Address offset: 0x000 Task starting the quadrature decoder When started, the SAMPLE register will be continuously updated at the rate given in the SAMPLEPER register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_START Task starting the quadrature decoder Trigger 1 Trigger task When started, the SAMPLE register will be continuously updated at the rate given in the SAMPLEPER register. 6.17.7.2 TASKS_STOP Address offset: 0x004 Task stopping the quadrature decoder 6.17.7.3 TASKS_READCLRACC Address offset: 0x008 Read and clear ACC and ACCDBL Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Task stopping the quadrature decoder Trigger 1 Trigger task Task transferring the content of ACC to ACCREAD and the content of ACCDBL to ACCDBLREAD, and then clearing the ACC and ACCDBL registers. These read-and-clear operations will be done atomically. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_READCLRACC Read and clear ACC and ACCDBL Task transferring the content of ACC to ACCREAD and the content of ACCDBL to ACCDBLREAD, and then clearing the ACC and ACCDBL registers. These read-and-clear operations will be done atomically. Trigger 1 Trigger task 4452_021 v1.3 267 ID ID A ID ID A ID ID A A A A Peripherals 6.17.7.4 TASKS_RDCLRACC Address offset: 0x00C Read and clear ACC Task transferring the content of ACC to ACCREAD, and then clearing the ACC register. This read-and-clear operation will be done atomically. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_RDCLRACC Read and clear ACC Task transferring the content of ACC to ACCREAD, and then clearing the ACC register. This read-and-clear operation will be done atomically. Trigger 1 Trigger task 6.17.7.5 TASKS_RDCLRDBL Address offset: 0x010 Read and clear ACCDBL Task transferring the content of ACCDBL to ACCDBLREAD, and then clearing the ACCDBL register. This read-

and-clear operation will be done atomically. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_RDCLRDBL Read and clear ACCDBL Task transferring the content of ACCDBL to ACCDBLREAD, and then clearing the ACCDBL register. This read-and-clear operation will be done atomically. Trigger 1 Trigger task 6.17.7.6 EVENTS_SAMPLERDY Address offset: 0x100 Event being generated for every new sample value written to the SAMPLE register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_SAMPLERDY Event being generated for every new sample value written NotGenerated Generated 0 1 to the SAMPLE register Event not generated Event generated ID ID A ID ID A ID ID A A A A 6.17.7.7 EVENTS_REPORTRDY Address offset: 0x104 4452_021 v1.3 268 Peripherals Non-null report ready Event generated when REPORTPER number of samples has been accumulated in the ACC register and the content of the ACC register is not equal to 0. (Thus, this event is only generated if a motion is detected since the previous clearing of the ACC register). Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_REPORTRDY Non-null report ready Event generated when REPORTPER number of samples has been accumulated in the ACC register and the content of the ACC register is not equal to 0. (Thus, this event is only generated if a motion is detected since the previous clearing NotGenerated Generated of the ACC register). Event not generated Event generated ID ID A ID ID A 0 1 0 1 6.17.7.8 EVENTS_ACCOF Address offset: 0x108 ACC or ACCDBL register overflow 6.17.7.9 EVENTS_DBLRDY Address offset: 0x10C Double displacement(s) detected Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ACCOF ACC or ACCDBL register overflow NotGenerated Generated Event not generated Event generated Event generated when REPORTPER number of samples has been accumulated and the content of the ACCDBL register is not equal to 0. (Thus, this event is only generated if a double transition is detected since the previous clearing of the ACCDBL register). A A 4452_021 v1.3 269 Peripherals A A ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_DBLRDY Double displacement(s) detected Event generated when REPORTPER number of samples has been accumulated and the content of the ACCDBL register is not equal to 0. (Thus, this event is only generated if a double transition is detected since the previous clearing of NotGenerated Generated the ACCDBL register). Event not generated Event generated 6.17.7.10 EVENTS_STOPPED Address offset: 0x110 QDEC has been stopped Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_STOPPED NotGenerated Generated QDEC has been stopped Event not generated Event generated 6.17.7.11 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW REPORTRDY_READCLRACC Shortcut between event REPORTRDY and task READCLRACC B RW SAMPLERDY_STOP Shortcut between event SAMPLERDY and task STOP C RW REPORTRDY_RDCLRACC Shortcut between event REPORTRDY and task RDCLRACC D RW REPORTRDY_STOP Shortcut between event REPORTRDY and task STOP E RW DBLRDY_RDCLRDBL Shortcut between event DBLRDY and task RDCLRDBL F RW DBLRDY_STOP Shortcut between event DBLRDY and task STOP Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled 4452_021 v1.3 270 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value G RW SAMPLERDY_READCLRACC Shortcut between event SAMPLERDY and task READCLRACC Description Enable shortcut Disable shortcut Enable shortcut Peripherals G F E D C B A 6.17.7.12 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW SAMPLERDY Write '1' to enable interrupt for event SAMPLERDY ID ID A B RW REPORTRDY Write '1' to enable interrupt for event REPORTRDY Event generated when REPORTPER number of samples has been accumulated in the ACC register and the content of the ACC register is not equal to 0. (Thus, this event is only generated if a motion is detected since the previous clearing C RW ACCOF Write '1' to enable interrupt for event ACCOF D RW DBLRDY Write '1' to enable interrupt for event DBLRDY Event generated when REPORTPER number of samples has been accumulated and the content of the ACCDBL register is not equal to 0. (Thus, this event is only generated if a double transition is detected since the previous clearing of the ACCDBL register). E RW STOPPED Write '1' to enable interrupt for event STOPPED Value ID Enabled Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Enable Read: Disabled Read: Enabled of the ACC register). Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled 6.17.7.13 INTENCLR Address offset: 0x308 Disable interrupt 4452_021 v1.3 271 Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Disable Read: Disabled Read: Enabled of the ACC register). Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW SAMPLERDY Write '1' to disable interrupt for event SAMPLERDY Peripherals E D C B A B RW REPORTRDY Write '1' to disable interrupt for event REPORTRDY Event generated when REPORTPER number of samples has been accumulated in the ACC register and the content of the ACC register is not equal to 0. (Thus, this event is only generated if a motion is detected since the previous clearing C RW ACCOF Write '1' to disable interrupt for event ACCOF D RW DBLRDY Write '1' to disable interrupt for event DBLRDY Event generated when REPORTPER number of samples has been accumulated and the content of the ACCDBL register is not equal to 0. (Thus, this event is only generated if a double transition is detected since the previous clearing of the ACCDBL register). E RW STOPPED Write '1' to disable interrupt for event STOPPED 6.17.7.14 ENABLE Address offset: 0x500 Enable the quadrature decoder Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable the quadrature decoder When enabled the decoder pins will be active. When disabled the quadrature decoder pins are not active and can Disabled Enabled be used as GPIO . Disable Enable 4452_021 v1.3 272 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description ActiveLow ActiveHigh 0 1 LED output pin polarity Led active on output pin low Led active on output pin high 6.17.7.15 LEDPOL Address offset: 0x504 LED output pin polarity Bit number ID ID A Reset 0x00000000 AccessField RW LEDPOL 6.17.7.16 SAMPLEPER Address offset: 0x508 Sample period Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW SAMPLEPER Sample period. The SAMPLE register will be updated for ID ID A 128us 256us 512us 1024us 2048us 4096us 8192us 16384us 32ms 65ms 131ms 0 1 2 3 4 5 6 7 8 9 10 every new sample 128 s 256 s 512 s 1024 s 2048 s 4096 s 8192 s 16384 s 32768 s 65536 s 131072 s 6.17.7.17 SAMPLE Address offset: 0x50C Motion sample value Bit number ID ID A Reset 0x00000000 AccessField R SAMPLE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value

[-1..2]

Description Last motion sample The value is a 2's complement value, and the sign gives the direction of the motion. The value '2' indicates a double transition. 4452_021 v1.3 273 6.17.7.18 REPORTPER Address offset: 0x510 Number of samples to be taken before REPORTRDY and DBLRDY events can be generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A RW REPORTPER Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description Peripherals A A A A Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. The report period in [s] is given as: RPUS = SP * RP Where RPUS is the report period in [s/report], SP is the sample period in [s/sample] specified in SAMPLEPER, and RP is the report period in [samples/report] specified in REPORTPER . 10Smpl 40Smpl 80Smpl 120Smpl 160Smpl 200Smpl 240Smpl 280Smpl 1Smpl 0 1 2 3 4 5 6 7 8 10 samples/report 40 samples/report 80 samples/report 120 samples/report 160 samples/report 200 samples/report 240 samples/report 280 samples/report 1 sample/report 6.17.7.19 ACC Address offset: 0x514 Register accumulating the valid transitions Bit number ID ID A Reset 0x00000000 AccessField R ACC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description

[-1024..1023]

Register accumulating all valid samples (not double transition) read from the SAMPLE register. Double transitions ( SAMPLE = 2 ) will not be accumulated in this register. The value is a 32 bit 2's complement value. If a sample that would cause this register to overflow or underflow is received, the sample will be ignored and an overflow event ( ACCOF ) will be generated. The ACC register is cleared by triggering the READCLRACC or the RDCLRACC task. 6.17.7.20 ACCREAD Address offset: 0x518 Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task 4452_021 v1.3 274 Peripherals Bit number ID ID A Reset 0x00000000 AccessField R ACCREAD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description

[-1024..1023]

Snapshot of the ACC register. The ACCREAD register is updated when the READCLRACC or RDCLRACC task is triggered. 6.17.7.21 PSEL.LED Address offset: 0x51C Pin select for LED signal ID A B C ID A B C Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.17.7.22 PSEL.A Address offset: 0x520 Pin select for A signal Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.17.7.23 PSEL.B Address offset: 0x524 Pin select for B signal C 1 0 C 1 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 4452_021 v1.3 275 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Peripherals B A A A A A Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect ID A B C Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.17.7.24 DBFEN Address offset: 0x528 Enable input debounce filters Bit number ID ID A Reset 0x00000000 AccessField RW DBFEN C 1 0 0 1 6.17.7.25 LEDPRE Address offset: 0x540 Time period the LED is switched ON prior to sampling 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled Enabled Enable input debounce filters Debounce input filters disabled Debounce input filters enabled Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 A A A A A A A A A Value ID Description Value

[1..511]

Period in s the LED is switched on prior to sampling Register accumulating the number of detected double transitions Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R ACCDBL Value ID Description Value

[0..15]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A Reset 0x00000010 AccessField RW LEDPRE 6.17.7.26 ACCDBL Address offset: 0x544 ID ID A ID ID A Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). When this register has reached its maximum value, the accumulation of double/illegal transitions will stop. An overflow event (ACCOF) will be generated if any double or illegal transitions are detected after the maximum value was reached. This field is cleared by triggering the READCLRACC or RDCLRDBL task. 4452_021 v1.3 276 Peripherals A A A A 6.17.7.27 ACCDBLREAD Address offset: 0x548 Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Description Value

[0..15]

R ACCDBLREAD Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. 6.17.8 Electrical specification 6.17.8.1 QDEC Electrical Specification Symbol tSAMPLE tLED Description Time between sampling signals from quadrature decoder Time from LED is turned on to signals are sampled Min. 128 0 Typ. Max. Units 131072 511 s s 6.18 RADIO 2.4 GHz radio The 2.4 GHz radio transceiver is compatible with multiple radio standards such as 1 Mbps and 2 Mbps Bluetooth Low Energy modes, Long Range (125 kbps and 500 kbps) Bluetooth Low Energy modes, IEEE 802.15.4 250 kbps mode, as well as Nordic's proprietary 1 Mbps and 2 Mbps modes. Listed here are main features for the RADIO:

Multidomain 2.4 GHz radio transceiver 1 Mbps and 2 Mbps Bluetooth Low Energy modes Long Range (125 kbps and 500 kbps) Bluetooth Low Energy modes Angle-of-arrival (AoA) and angle-of-departure (AoD) direction finding using Bluetooth Low Energy IEEE 802.15.4 250 kbps mode 1 Mbps and 2 Mbps Nordic proprietary modes Best in class link budget and low power operation Efficient data interface with EasyDMA support Automatic address filtering and pattern matching EasyDMA, in combination with an automated packet assembler, packet disassembler, automated CRC generator and CRC checker, makes it easy to configure and use the RADIO. See the following figure for details. 4452_021 v1.3 277 RAM RADIO PACKETPTR Packet synch Device address match Address match Packet disassembler CRC Dewhitening Payload EasyDMA Bit counter S0 L S1 S0 L S1 Payload MAXLEN Packet assembler CRC Whitening 2.4 GHz transmitter ANT1 Peripherals RSSI 2.4 GHz receiver IFS control unit Figure 83: RADIO block diagram The RADIO includes a device address match unit and an interframe spacing control unit that can be utilized to simplify address whitelisting and interframe spacing respectively in Bluetooth low energy and similar applications. The RADIO also includes a received signal strength indicator (RSSI) and a bit counter. The bit counter generates events when a preconfigured number of bits are sent or received by the RADIO. 6.18.1 Packet configuration A RADIO packet contains the fields PREAMBLE, ADDRESS, S0, LENGTH, S1, PAYLOAD, and CRC. For Long Range (125 kbps and 500 kbps) Bluetooth Low Energy modes, fields CI, TERM1 and TERM2 are also included. The content of a RADIO packet is illustrated in the figures below. The RADIO sends the fields in the packet according to the order illustrated in the figures, starting on the left. 0x55 0xAA 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 t i B S L PREAMBLE L t i B S LSByte ADDRESS BASE t i B S L PREFIX S0 LENGTH S1 PAYLOAD t i B S M CRC MSByte Figure 84: On-air packet layout LSByte LSByte t i B S L PREAMBLE L t i B S BASE t i B S L PREFIX CI TERM1 S0 LENGTH S1 PAYLOAD t i B S M CRC MSByte TERM t i B S 2L LSByte ADDRESS Figure 85: On-air packet layout for Long Range (125 kbps and 500 kbps) Bluetooth Low Energy modes Not shown in the figures is the static payload add-on (the length of which is defined in PCNF1.STATLEN, and which is 0 bytes in a standard BLE packet). The static payload add-on is sent between PAYLOAD and CRC fields. The RADIO sends the different fields in the packet in the order they are illustrated above, from left to right. PREAMBLE is sent with least significant bit first on air. The size of the PREAMBLE depends on the mode selected in the MODE register:

The PREAMBLE is one byte for MODE = Ble_1Mbit as well as all Nordic proprietary operating modes

(MODE = Nrf_1Mbit and MODE = Nrf_2Mbit), and PCNF0.PLEN has to be set accordingly. If the first bit of the ADDRESS is 0, the preamble will be set to 0xAA. Otherwise the PREAMBLE will be set to 0x55. 4452_021 v1.3 278 Peripherals For MODE = Ble_2Mbit, the PREAMBLE must be set to 2 byte through PCNF0.PLEN. If the first bit of the ADDRESS is 0, the preamble will be set to 0xAAAA. Otherwise the PREAMBLE will be set to 0x5555. For MODE = Ble_LR125Kbit and MODE = Ble_LR500Kbit, the PREAMBLE is 10 repetitions of 0x3C. For MODE = Ieee802154_250Kbit, the PREAMBLE is 4 bytes and set to all zeros. Radio packets are stored in memory inside instances of a RADIO packet data structure as illustrated below. The PREAMBLE, ADDRESS, CI, TERM1, TERM2, and CRC fields are omitted in this data structure. Fields S0, LENGTH, and S1 are optional. S0 0 LENGTH S1 PAYLOAD LSByte n Figure 86: In-RAM representation of RADIO packet The byte ordering on air is always least significant byte first for the ADDRESS and PAYLOAD fields, and most significant byte first for the CRC field. The ADDRESS fields are always transmitted and received least significant bit first. The CRC field is always transmitted and received most significant bit first. The endianness, i.e. the order in which the bits are sent and received, of the S0, LENGTH, S1, and PAYLOAD fields can be configured via PCNF1.ENDIAN. The sizes of the S0, LENGTH and S1 fields can be individually configured via S0LEN, LFLEN, and S1LEN in PCNF0 respectively. If any of these fields are configured to be less than 8 bits, the least significant bits of the fields are used. If S0, LENGTH, or S1 are specified with zero length, their fields will be omitted in memory. Otherwise each field will be represented as a separate byte, regardless of the number of bits in their on-air counterpart. Independent of the configuration of PCNF1.MAXLEN, the combined length of S0, LENGTH, S1, and PAYLOAD cannot exceed 258 bytes. 6.18.2 Address configuration The on-air radio ADDRESS field is composed of two parts, the base address field and the address prefix field. The size of the base address field is configurable via PCNF1.BALEN. The base address is truncated from the least significant byte if the PCNF1.BALEN is less than 4. See Definition of logical addresses on page 279. Logical address Base address 0 1 2 3 4 5 6 7 BASE0 BASE1 BASE1 BASE1 BASE1 BASE1 BASE1 BASE1 Prefix byte PREFIX0.AP0 PREFIX0.AP1 PREFIX0.AP2 PREFIX0.AP3 PREFIX1.AP4 PREFIX1.AP5 PREFIX1.AP6 PREFIX1.AP7 Table 74: Definition of logical addresses The on-air addresses are defined in the BASE0/BASE1 and PREFIX0/PREFIX1 registers. It is only when writing these registers that the user must relate to the actual on-air addresses. For other radio address registers, such as the TXADDRESS, RXADDRESSES, and RXMATCH registers, logical radio addresses ranging from 0 to 7 are being used. The relationship between the on-air radio addresses and the logical addresses is described in Definition of logical addresses on page 279. 4452_021 v1.3 279 Peripherals 6.18.3 Data whitening The RADIO is able to do packet whitening and de-whitening, enabled in PCNF1.WHITEEN. When enabled, whitening and de-whitening will be handled by the RADIO automatically as packets are sent and received. The whitening word is generated using polynomial g(D) = D7+ D4 + 1, which then is XORed with the data packet that is to be whitened, or de-whitened. See the figure below. D0 D4 D7 Data out Position 0 1 2 3 4 5 6

Data in Figure 87: Data whitening and de-whitening Whitening and de-whitening will be performed over the whole packet except for the preamble and the address fields. The linear feedback shift register in the figure above is initialized via DATAWHITEIV. 6.18.4 CRC The CRC generator in the RADIO calculates the CRC over the whole packet excluding the preamble. If desirable, the address field can be excluded from the CRC calculation as well. See CRCCNF register for more information. The CRC polynomial is configurable as illustrated in the following figure, where bit 0 in the CRCPOLY register corresponds to X0 and bit 1 corresponds to X1 etc. See CRCPOLY on page 325 for more information. Xn Xn-1 X2 X1 X0 Packet

(Clocked in serially)

bn b0 Figure 88: CRC generation of an n bit CRC The figure shows that the CRC is calculated by feeding the packet serially through the CRC generator. Before the packet is clocked through the CRC generator, the CRC generator's latches b0 through bn will be initialized with a predefined value specified in the CRCINIT register. After the whole packet has been clocked through the CRC generator, b0 through bn will hold the resulting CRC. This value will be used by the RADIO during both transmission and reception. Latches b0 through bn are not available to be read by the CPU at any time. However, a received CRC can be read by the CPU via the RXCRC register. The length (n) of the CRC is configurable, see CRCCNF for more information. Once the entire packet, including the CRC, has been received and no errors were detected, the RADIO generates a CRCOK event. If CRC errors were detected, a CRCERROR event is generated. 4452_021 v1.3 280 The status of the CRC check can be read from the CRCSTATUS register after a packet has been received. Peripherals 6.18.5 Radio states Tasks and events are used to control the operating state of the RADIO. The RADIO can enter the states described the table below. Description No operations are going on inside the RADIO and the power consumption is at a minimum State DISABLED RXRU RXIDLE RX TXRU TXIDLE TX RXDISABLE TXDISABLE The RADIO is ramping up and preparing for reception The RADIO is ready for reception to start The RADIO is ramping up and preparing for transmission The RADIO is ready for transmission to start The RADIO is transmitting a packet The RADIO is disabling the receiver The RADIO is disabling the transmitter Reception has been started and the addresses enabled in the RXADDRESSES register are being monitored A state diagram showing an overview of the RADIO is shown in the following figure. Table 75: RADIO state diagram TXDISABLE TXRU TXIDLE TX

/ DISABLED DISABLED RXEN

/ DISABLED TXEN TXEN Packet sent / END Last bit sent / PHYEND Last bit received / PHYEND Packet received / END RXDISABLE RXRU RXIDLE RX Ramp-up complete

/ READY Ramp-up complete

/ READY START STOP START STOP DISABLE DISABLE Address sent

/ ADDRESS Payload sent

[payload length >=0]

/ PAYLOAD Address received

[Address match]

/ ADDRESS Payload received

[payload length >=0]

/ PAYLOAD Figure 89: Radio states This figure shows how the tasks and events relate to the RADIO's operation. The RADIO does not prevent a task from being triggered from the wrong state. If a task is triggered from the wrong state, for example if the RXEN task is triggered from the RXDISABLE state, this may lead to incorrect behavior. The PAYLOAD event is always generated even if the payload is zero. The END to START shortcut should not be used with IEEE 802.15.4 250 kbps mode. Use the PHYEND to START shortcut instead. The END to START shortcut should not be used with Long Range (125 kbps and 500 kbps) Bluetooth Low Energy modes. Use the PHYEND to START shortcut instead. 6.18.6 Transmit sequence Before the RADIO is able to transmit a packet, it must first ramp-up in TX mode. See TXRU in Radio states on page 281 and Transmit sequence on page 282. A TXRU ramp-up sequence is initiated when the 4452_021 v1.3 281 Peripherals TXEN task is triggered. After the RADIO has successfully ramped up it will generate the READY event indicating that a packet transmission can be initiated. A packet transmission is initiated by triggering the START task. The START task can first be triggered after the RADIO has entered into the TXIDLE state. The following figure illustrates a single packet transmission where the CPU manually triggers the different tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If shortcuts are not used, a certain amount of delay caused by CPU execution is expected between READY and START, and between END and DISABLE. As illustrated in Transmit sequence on page 282 the RADIO will by default transmit

'1's between READY and START, and between END and DISABLED. What is transmitted can be programmed through the DTX field in the MODECNF0 register. TXRU TXIDLE TX TXIDLE TXDISABLE

(carrier) P A S0 L S1 PAYLOAD CRC

(carrier) Y D A E R S S E R D D A 2 T R A T S Figure 90: Transmit sequence D N E Y H P D N E D A O L Y A P D E L B A S D I 3 E L B A S D I The following figure shows a slightly modified version of the transmit sequence where the RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which means that no delay is introduced. TXRU TX TXDISABLE P A S0 L S1 PAYLOAD CRC

(carrier) Y D A E R S S E R D D A T R A T S D N E Y H P D N E D A O L Y A P D E L B A S D I 2 E L B A S D I Figure 91: Transmit sequence using shortcuts to avoid delays The RADIO is able to send multiple packets one after the other without having to disable and re-enable the RADIO between packets, as illustrated in the following figure. t e a S t r e t t i m s n a r T e n i l e f i L t e a S t r e t t i m s n a r T e n i l e f i L 1 N E X T 1 N E X T 4452_021 v1.3 282 t e a S t r e t t i m s n a r T e n i l e f i L 1 N E X T e t a t S n o i t p e c e R e n i l e f i L 1 N E X R Peripherals TXRU TX TXIDLE TX TXDISABLE P A S0 L S1 PAYLOAD CRC

(carrier) P A S0 L S1 PAYLOAD CRC

(carrier) Y D A E R S S E R D D A T R A T S D N E Y H P D N E D A O L Y A P S S E R D D A 2 T R A T S D A O L Y A P D N E D N E Y H P D E L B A S D I 3 E L B A S D I Figure 92: Transmission of multiple packets 6.18.7 Receive sequence Before the RADIO is able to receive a packet, it must first ramp up in RX mode, see RXRU in Radio states on page 281 and Receive sequence on page 283. An RXRU ramp up sequence is initiated when the RXEN task is triggered. After the RADIO has successfully ramped up it will generate the READY event indicating that a packet reception can be initiated. A packet reception is initiated by triggering the START task. As illustrated in Radio states on page 281, the START task can first be triggered after the RADIO has entered into the RXIDLE state. The following figure shows a single packet reception where the CPU manually triggers the different tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If shortcuts are not used, a certain amount of delay caused by CPU execution is expected between READY and START, and between END and DISABLE. The RADIO will be listening and possibly receiving undefined data, represented with an 'X', from START and until a packet with valid preamble (P) is received. RXRU RXIDLE RX RXIDLE RXDISABLE X P A S0 L S1 PAYLOAD CRC Y D A E R 2 T R A T S S S E R D D A D A O L Y A P D N E Y H P D N E D E L B A S I D 3 E L B A S I D Figure 93: Receive sequence The following figure shows a slightly modified version of the receive sequence, where the RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which means that no delay is introduced. 4452_021 v1.3 283 e t a t S n o i t p e c e R e n i l e f i L e t a t S r e v i e c e R e n i l e f i L Peripherals RXRU RX RXDISABLE X P A S0 L S1 PAYLOAD CRC Y D A E R T R A T S 1 N E X R S S E R D D A D A O L Y A P D N E Y H P D N E D E L B A S I D 2 E L B A S I D Figure 94: Receive sequence using shortcuts to avoid delays The RADIO is able to receive consecutive packets without having to disable and re-enable the RADIO between packets, as illustrated in the figure below. RXRU RX RXIDLE RX RXDISABLE X P A S0 L S1 PAYLOAD CRC X P A S0 L S1 PAYLOAD CRC Y D A E R S S E R D D A D A O L Y A P D N E Y H P D N E S S E R D D A D A O L Y A P D N E Y H P D N E 1 N E X R T R A T S 2 T R A T S Figure 95: Reception of multiple packets D E L B A S I D 3 E L B A S I D 6.18.8 Received signal strength indicator (RSSI) The RADIO implements a mechanism for measuring the power in the received signal. This feature is called received signal strength indicator (RSSI). The RSSI is measured continuously and the value filtered using a single-pole IIR filter. After a signal level change, the RSSI will settle after approximately RSSISETTLE. Sampling of the received signal strength is started by using the RSSISTART task. The sample can be read from the RSSISAMPLE register. The sample period of the RSSI is defined by RSSIPERIOD. The RSSISAMPLE will hold the filtered received signal strength after this sample period. For the RSSI sample to be valid, the RADIO has to be enabled in receive mode (RXEN task) and the reception has to be started (READY event followed by START task). 6.18.9 Interframe spacing (IFS) Interframe spacing (IFS) is defined as the time, in microseconds, between two consecutive packets, starting from when the end of the last bit of the previous packet is received, to the beginning of the first bit of the subsequent packet that is transmitted. The RADIO is able to enforce this interval, as specified in the TIFS register, as long as the TIFS is not specified to be shorter than the RADIO's turnaround time, i.e. 4452_021 v1.3 284 t e a S t r i a n O e n i l e f i L the time needed to switch off the receiver, and then switch the transmitter back on. The TIFS register can be written any time before the last bit on air is received. Peripherals This timing is illustrated in the figure below. Change to MODE OK Change to SHORTS and TIFS OK RX RXDISABLE TXRU TX PAYLOAD CRC P A S0 L S1 PAYLOAD D A O L Y A P D N E D E L B A S D I TIFS E L B A S D I N E X T Y D A E R S S E R D D A T R A T S Figure 96: IFS timing detail The TIFS duration starts after the last bit on air (just before the END event), and elapses with first bit being transmitted on air (just after READY event). TIFS is only enforced if the shortcuts END to DISABLE and DISABLED to TXEN or END to DISABLE and DISABLED to RXEN are enabled. TIFS is qualified for use in IEEE 802.15.4 250kbps mode, Long Range (125 kbps and 500 kbps) Bluetooth Low Energy modes, 1 Mbps and 2 Mbps Bluetooth Low Energy modes, using the default ramp-up mode. SHORTS and TIFS registers are not double-buffered, and can be updated at any point before the last bit on air is received. The MODE register is double-buffered and sampled at the TXEN or RXEN task. 6.18.10 Device address match The device address match feature is tailored for address whitelisting in Bluetooth low energy and similar implementations. This feature enables on-the-fly device address matching while receiving a packet on air. This feature only works in receive mode and when the RADIO is configured for little endian, see PCNF1.ENDIAN. The device address match unit assumes that the first 48 bits of the payload are the device address and that bit number 6 in S0 is the TxAdd bit. See the Bluetooth Core Specification for more information about device addresses, TxAdd, and whitelisting. The RADIO is able to listen for eight different device addresses at the same time. These addresses are specified in a DAB/DAP register pair, one pair per address, in addition to a TxAdd bit configured in the DACNF register. The DAB register specifies the 32 least significant bits of the device address, while the DAP register specifies the 16 most significant bits of the device address. Each of the device addresses can be individually included or excluded from the matching mechanism. This is configured in the DACNF register. 4452_021 v1.3 285 Peripherals 6.18.11 Bit counter The RADIO implements a simple counter that can be configured to generate an event after a specific number of bits have been transmitted or received. By using shortcuts, this counter can be started from different events generated by the RADIO and count relative to these. The bit counter is started by triggering the BCSTART task, and stopped by triggering the BCSTOP task. A BCMATCH event will be generated when the bit counter has counted the number of bits specified in the BCC register. The bit counter will continue to count bits until the DISABLED event is generated or until the BCSTOP task is triggered. The CPU can therefore, after a BCMATCH event, reconfigure the BCC value for new BCMATCH events within the same packet. The bit counter can only be started after the RADIO has received the ADDRESS event. The bit counter will stop and reset on either the BCSTOP, STOP, or DISABLE task, or the END event. The figure below illustrates how the bit counter can be used to generate a BCMATCH event in the beginning of the packet payload, and again generate a second BCMATCH event after sending 2 bytes (16 bits) of the payload. RXRU RX RXDISABLE t e a S t n o i t p e c e R e n i l e f i L 0 1 2 X P A S0 L S1 PAYLOAD CRC Assuming that the combined length of S0, length (L) and S1 is 12 bits. 1 N E X R 2 1

C C B Y D A E R T R A T S S S E R D D A T R A T S C B H C T A M C B 3 P O T S C B H C T A M C B 2 6 1

2 1

C C B Figure 97: Bit counter example D A O L Y A P D N E D E L B A S D I E L B A S D I 6.18.12 Direction finding The RADIO implements the Angle-of-Arrival (AoA) and Angle-of-Departure (AoD) Bluetooth Low Energy feature, which can be used to determine the direction of a peer device. The feature is available for the BLE 1 Mbps and BLE 2 Mbps modes. When using this feature, the transmitter sends a packet with a continuous tone extension (CTE) appended to the packet, after the CRC. During the CTE, the receiver can take IQ samples of the incoming signal. An antenna array is employed at the transmitter (AoD) or at the receiver (AoA). The AoD transmitter, or AoA receiver, switches between the antennas, in order to collect IQ samples from the different antenna pairs. The IQ samples can be used to calculate the relative path lengths between the antenna pairs, which can be used to estimate the direction of the transmitter. 6.18.12.1 CTE format The CTE is from 16 s to 160 s and consists of an unwhitened sequence of 1's, equivalent to a continuous tone nominally offset from the carrier by +250 kHz for the 1 Mbps PHY and +500 kHz for the 2 Mbps BLE PHYs. The format of the CTE, when switching and/or sampling, is shown below. 4452_021 v1.3 286 Peripherals REFERENCE PERIOD SWITCH SLOT SAMPLE SLOT SWITCH SLOT SAMPLE SLOT

... SWITCH SLOT SAMPLE SLOT GUARD PERIOD 4 s 8 s 1 or 2 s 1 or 2 s 16-160 s Figure 98: Constant tone extension (CTE) structure Antenna switching is performed during switch slots and the guard period. The AoA/AoD feature requires that one IQ sample is taken for each microsecond within the reference period, and once for each sample slot. Oversampling is possible by changing the sample spacing as described in IQ sampling on page 290. The switch slot and sample slot durations are either 1 or 2 s, but must be equal. The format of the CTE and switching and sampling procedures may be configured prior to, or during, packet transmission and reception. Alternatively, during packet reception, these operations can be configured by reading specific fields of the packet contents. 6.18.12.2 Mode Depending on the DFEMODE, the device performs the following procedures:

DFEMODE AOA AOD TX x RX x x TX x x RX x AoA/AoD Procedure Receiving, interpreting, and sampling CTE Generating and transmitting CTE Antenna switching Table 76: AoA/AoD Procedures performed as a function of DFEMODE and TX/RX mode 6.18.12.3 Inline configuration When inline configuration is enabled during RX, further configuration of the AoA/AoD procedures is performed based on the values of the CP bit and the CTEInfo octet within the packet. This is enabled by setting CTEINLINECONF.CTEINLINECTRLEN. The CTEInfo octet is present only if the CP bit is set. The position of the CP bit and CTEInfo octet depends on whether the packet has a Data Channel PDU (CTEINLINECONF.CTEINFOINS1=InS1), or an Advertising Channel PDU

(CTEINLINECONF.CTEINFOINS1=NotInS1). Data channel PDU For Data Channel PDUs, PCNF0.S0LEN must be 1 byte, and PCNF0.LFLEN must be 8 bits. To determine if S1 is present, the registers CTEINLINECONF.S0MASK and CTEINLINECONF.S0CONF forms a bitwise mask-and-

test for the S0 field. If the bitwise AND between S0 and S0MASK equals S0CONF, then S1 is determined to be present. When present, the value of PCNF0.S1LEN will be ignored, as this is decided by the CP bit in the the following figure. S0 LENGTH S1

... CP

... Length CTEInfo 5 bits 1 bit 2 bits 8 bits 0 or 8 bits Figure 99: Data channel PDU header When encrypting and decrypting BLE packets using the CCM peripheral, it is also required to set PCNF0.S1INCL=1. The CCM mode must be configured to use an 8-bit length field. The value of the CP bit is included in the calculation of the MIC, while the S1 field is ignored by the CCM calculation. 4452_021 v1.3 287 Peripherals Advertising channel PDU For advertising channel PDUs, the CTEInfo Flag replaces the CP bit. The CTEInfo Flag is within the extended header flag field in some of the advertising PDUs that employ the common extended advertising payload format (i.e. AUX_SYNC_IND, AUX_CHAIN_IND). The format of such packets is shown in the following figure. S0 LENGTH PAYLOAD PDU Type

... Length AdvMode

... .. AdvA TargetA CTEInfo CRC CTE Extended Header Length CTEInfo flag 4 bits 4 bits 8 bits 6 bits 2 bits 1 bit 6 octets 6 octets 8 bits 2 bits 5 bits Extended Header Flags Figure 100: Advertising channel PDU header

... .. The CTEINLINECONF.S0CONF and CTEINLINECONF.S0MASK fields can be configured to accept only certain advertising PDU Types. If the extended header length is non-zero, the CTEInfo extended header flag is checked to determine whether CTEInfo is present. If a bit before the CTEInfo flag within the extended header flags is set, then the CTEInfo position is postponed 6 octets. CTEInfo parsing The CTEInfo field is shown in the following figure. CTETime RFU CTEType 5 bits 1 bit 2 bits Figure 101: CTEInfo field The CTETIME field defines the length of the CTE in 8 s units. The valid upper bound of values can be adjusted using CTEINLINECONF.CTETIMEVALIDRANGE, including allowing use of the RFU bit within this field. If the CTETIME field is an invalid value of either 0 or 1, the CTE is assumed to be the minimum valid length of 16 s. The slot duration is determined by the CTEType field. In RX this determines whether the sample spacing as defined in CTEINLINECONF.CTEINLINERXMODE1US or CTEINLINECONF.CTEINLINERXMODE2US is used. CTEType Description TX switch spacing RX sample spacing during Sample spacing RX during

2 s 4 s reference period reference period TSAMPLESPACING1 TSAMPLESPACING2 TSAMPLESPACING1 CTEINLINERXMODE1US TSAMPLESPACING1 CTEINLINERXMODE2US 0 1 2 3 AoA, no switching AoD, 1 s slots AoD, 2 s slots Reserved for future use 6.18.12.4 Manual configuration Table 77: Switching and sampling spacing based on CTEType If CTEINLINECONF.CTEINLINECTRLEN is not set, then the packet is not parsed to determine the CTE parameters, and the antenna switching and sampling is controlled by other registers, see Antenna switching on page 289. The length of the CTE is given in 8 s units by DFECTRL1.NUMBEROF8US. The start of the antenna switching and/or sampling (denoted as an AoA/AoD procedure), can be configured to start at some trigger with an additional offset. Using DFECTRL1.DFEINEXTENSION, the trigger can be configured to be the end of the CRC, or alternatively, the ADDRESS event. The additional offset for antenna switching is configured using DFECTRL2.TSWITCHOFFSET. Similarly, the additional offset for antenna sampling is configured using DFECTRL2.TSAMPLEOFFSET. 4452_021 v1.3 288 6.18.12.5 Receive- and transmit sequences The addition of the CTE to the transmitted packet is illustrated in the following figure. TXRU TXIDLE TX TXIDLE TXDISABLE Peripherals t e a S t r e t t i m s n a r T e n i l e f i L e t a t S n o i t p e c e R e n i l e f i L 1 N E X T 1 N E X R

(carrier) P A S0 L S1 PAYLOAD CRC CTE

(carrier) D A O L Y A P D N E D N E Y H P D E L B A S D I Y D A E R S S E R D D A 2 T R A T S 3 E L B A S D I 3 E L B A S I D Figure 102: Transmit sequence with DFE The prescence of CTE within a received packet is signalled by the CTEPRESENT event illustrated in the figure below. RXRU RXIDLE RX RXIDLE RXDISABLE X P A S0 L S1 PAYLOAD CRC CTE S S E R D D A T N E S E R P E T C D A O L Y A P D N E D N E Y H P D E L B A S I D Y D A E R 2 T R A T S Figure 103: Receive sequence with DFE 6.18.12.6 Antenna switching The RADIO can control up to 8 GPIO pins in order to control external antenna switches used in direction finding. Pin configuration The eight antenna selection signals are mapped to physical pins according to the pin numbers specified in the PSEL.DFEGPIO[n] registers. Only pins that have the PSEL.DFEGPIO[n].CONNECTED field set to Connected will be controlled by the RADIO. Pins that are Disconnected will be controlled by GPIO. During transmission in AoD TX mode or reception in AoA RX mode, the RADIO automatically acquires the pins as needed. At times when the RADIO does not use the pin, the pin is released to its default state and controlled by the GPIO configuration. Thus, the pin must be configured using the GPIO peripheral. 4452_021 v1.3 289 Peripherals Pin acquired by RADIO Direction Value Comment Yes No Output Specified in SWITCHPATTERN Pin acquired by RADIO, and in use for DFE. Specified by GPIO Specified by GPIO DFE not in progress. Pin has not been acquired by RADIO, but is available for DFE use. Table 78: Pin configuration matrix for a connected and enabled pin [n]

Switch pattern configuration The values of the GPIOs while switching during the CTE are configured by writing successively to the SWITCHPATTERN register. The first write to SWITCHPATTERN is the GPIO pattern applied from the call of TASKS_TXEN or TASKS_RXEN until the first antenna switch is triggered. The second write sets the pattern for the reference period and is applied at the start of the guard period. The following writes set the pattern for the remaining switch slots and are applied at the start of each switch slot. If writing beyond the total number of antenna slots, the pattern will wrap to SWITCHPATTERN[2] and start over again. During operation, when the end of the SWITCHPATTERN buffer is reached, the RADIO cycles back to SWITCHPATTERN[2]. At the end of the AoA/AoD procedure, SWITCHPATTERN[0] is applied to DFECTRL1.TSWITCHSPACING after the previous antenna switch. The SWITCHPATTERN buffer can be erased/cleared using CLEARPATTERN. A minimum number of three patterns must be written to the SWITCHPATTERN register. If CTEINLINECONF.CTEINLINECTRLEN is not set, then the antenna switch spacing is determined by DFECTRL1.TSWITCHSPACING (otherwise described by Switching and sampling spacing based on CTEType on page 288). DFECTRL2.TSWITCHOFFSET determines the position of the first switch compared to the configurable start of CTE (see DFECTRL1.DFEINEXTENSION). 6.18.12.7 IQ sampling The RADIO uses DMA to write IQ samples recorded during the CTE to RAM. Alternatively, the magnitude and phase of the samples can be recorded using the DFECTRL1.SAMPLETYPE field. The samples are written to the location in RAM specified by DFEPACKET.PTR. The maximum number of samples to transfer are specified by DFEPACKET.MAXCNT and the number of samples transferred are given in DFEPACKET.AMOUNT. The IQ samples are recorded with respect to the RX carrier frequency. The format of the samples is provided in the following table. SAMPLETYPE Field Description 0: I_Q (default) 12 bits signed, sign extended to 16 bits 1: MagPhase reserved Always zero Q I magnitude phase Bits 31:16 15:0 31:29 28:16 15:0 13 bits unsigned. Equals 1.646756*sqrt(I^2+Q^2) 9 bits signed, sign extended to 16 bits. Equals 64*atan2(Q, I) in the range [-201,201]

Table 79: Format of samples Oversampling is configured separately for the reference period and for the time after the reference period. During the reference period, the sample spacing is determined by DFECTRL1.TSAMPLESPACINGREF. DFECTRL2.TSAMPLEOFFSET determines the position of the first sample relative to the end of the last bit of the CRC. For the time after the reference period, if CTEINLINECONF.CTEINLINECTRLEN is disabled, the sample spacing is set in DFECTRL1.TSAMPLESPACING. However, when CTEINLINECONF.CTEINLINECTRLEN is enabled, the sample spacing are determined by two different registers, depending on whether the device is in AoA or AoD RX-mode, as follows. For AoD RX mode, the sample spacing after the reference period is determined by the CTEType in the packet, as listed in the table below. 4452_021 v1.3 290 Peripherals Sample spacing CTEINLINECONF.CTEINLINERXMODE1US CTEINLINECONF.CTEINLINERXMODE2US DFECTRL1.TSAMPLESPACING CTEType AoD 1 s slots AoD 2 s slots Other 2 s 4 s Other Table 80: Sample spacing when CTEINLINECONF.CTEINLINECTRLEN is set and the device is in AoD RX mode For AoA RX mode, the sample spacing after the reference period is determined by DFECTRL1.TSWITCHSPACING, as listed in the table below. DFECTRL1.TSWITCHSPACING Sample spacing CTEINLINECONF.CTEINLINERXMODE1US CTEINLINECONF.CTEINLINERXMODE2US DFECTRL1.TSAMPLESPACING Table 81: Sample spacing when CTEINLINECONF.CTEINLINECTRLEN is set and the device is in AoA RX mode For the reference- and switching periods, DFECTRL1.TSAMPLESPACINGREF and DFECTRL1.TSAMPLESPACING can be used to achieve oversampling. 6.18.13 IEEE 802.15.4 operation With the MODE=Ieee802154_250kbit the RADIO will comply with the IEEE 802.15.4-2006 standard implementing its 250 kbps, 2450 MHz, O-QPSK PHY. The IEEE 802.15.4 standard differs from Nordic's proprietary and Bluetooth low energy modes. Notable differences include modulation scheme, channel structure, packet structure, security, and medium access control. The main features of the IEEE 802.15.4 mode are:

Ultra-low power 250 kbps, 2450 MHz, IEEE 802.15.4-2006 compliant link Clear channel assessment Energy detection scan CRC generation 6.18.13.1 Packet structure The IEEE 802.15.4 standard defines an on-the-air frame/packet that is different from what is used in BLE mode. The following figure provides an overview of the physical frame structure and its timing. 160 s Preamble sequence 32 s PHY protocol data unit (PPDU) Length SFD

<=4064 s PHY payload 5 octets synchronization header (SHR) Maximum 127 octets (PSDU) 1 octet

(PHR) MAC protocol data unit (MPDU) Figure 104: IEEE 802.15.4 frame format (PPDU) The standard uses the term octet for an 8-bit storage unit within the PPDU. For timing, the value symbol is used, and it has a duration of 16 s. The total usable payload (PSDU) is 127 octets, but when CRC is in use, this is reduced to 125 octets of usable payload. 4452_021 v1.3 291 Peripherals The preamble sequence consists of four octets that are all zero, and are used for synchronizing the RADIO's receiver. Following the preamble is the single octet start of frame delimiter (SFD), with a fixed value of 0xA7. An alternate SFD can be programmed through the SFD register, providing an initial level of frame filtering for those who choose non-standard compliance. It is a valuable feature when operating in a congested or private network. The preamble sequence and the SFD are generated by the RADIO, and are not programmed by the user into the frame buffer. Following the five octet synchronization header (SHR) is the single octet phy header (PHR). The least significant seven bits of PHR denote the frame length of the following PSDU. The most significant bit is reserved and is set to zero for frames that are standard compliant. The RADIO reports all eight bits which can be used to carry additional information. The PHR is the first byte written to the frame data memory pointed to by PACKETPTR. Frames with zero length are discarded, and the FRAMESTART event is not generated in this case. The next N octets carry the data of the PHY packet, where N equals the value of the PHR. For an implementation also using the IEEE 802.15.4 MAC layer, the PHY data is a MAC frame of N-2 octets, since two octets occupy a CRC field. As illustrated in the figure below, an IEEE 802.15.4 MAC layer frame always consists of A header:

The frame control field (FCF) The sequence number Addressing fields A payload The 16-bit frame control sequence (FCS) FCF Seq Addressing fields MAC header (MHR) MAC payload MAC service data unit (MSDU) FCS

(MFR) MAC protocol data unit (MPDU) Dst PAN ID Dst address Src PAN ID Src address Security 0/4/6/8/10/12/14/16/18/20 octets 0/5/6/10/14 octets CRC-16 2 octets 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Frame type Sec Pend Dst A mode Frame ver Src A mode Comp ACK Frame control field (FCF) 2 octets Reserved Figure 105: IEEE 802.15.4 frame format (MPDU) The two FCF octets contain information about the frame type, addressing, and other control flags. This field is decoded when using the assisted operating modes offered by the RADIO. The sequence number is a single octet in size and is unique for a frame. It is used in the associated acknowledgement frame sent upon successful frame reception. The addressing field can be zero (acknowledgement frame) or up to 20 octets in size. The field is used to direct packets to the correct recipient and denote its origin. IEEE 802.15.4 bases its addressing on networks being organized in PANs with 16-bit identifier and nodes having a 16-bit or 64-bit address. In the assisted receive mode, these parameters are analyzed for address matching and acknowledgement. The MAC payload carries the data of the next higher layer, or in the case of a MAC command frame, information used by the MAC layer itself. 4452_021 v1.3 292 Peripherals The two last octets contain the 16-bit ITU-T CRC. The FCS is calculated over the MAC header (MHR) and MAC payload (MSDU) parts of the frame. This field is calculated automatically when sending a frame, or indicated in the CRCSTATUS register when a frame is received. If configured, this feature is taken care of autonomously by the CRC module. 6.18.13.2 Operating frequencies The IEEE 802.15.4 standard defines 16 channels, 11 - 26, of 5 MHz each, in the 2450 MHz frequency band. To choose the correct channel center frequency, the FREQUENCY register must be programmed according to the table below. IEEE 802.15.4 channel Center frequency (MHz) FREQUENCY setting Channel 11 Channel 12 Channel 13 Channel 14 Channel 15 Channel 16 Channel 17 Channel 18 Channel 19 Channel 20 Channel 21 Channel 22 Channel 23 Channel 24 Channel 25 Channel 26 2405 2410 2415 2420 2425 2430 2435 2440 2445 2450 2455 2460 2465 2470 2475 2480 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Table 82: IEEE 802.15.4 center frequency definition 6.18.13.3 Energy detection (ED) As required by the IEEE 802.15.4 standard, it must be possible to sample the received signal power within the bandwidth of a channel, for the purpose of determining presence of activity. To prevent the channel signal from being decoded, the shortcut between the READY event and the START task should be disabled before putting the RADIO in receive mode. The energy detection (ED) measurement time, where RSSI samples are averaged, is 8 symbol periods, corresponding to 128 s. The standard further specifies the measurement to be a number between 0 and 255, where 0 shall indicate received power less than 10 dB above the selected receiver sensitivity. The power range of the ED values must be at least a 40 dB linear mapping with accuracy of 6 dB. See section 6.9.7 Receiver ED in the IEEE 802.15.4 standard for further details. The following example shows how to perform a single energy detection measurement and convert to IEEE 802.15.4 scale. 4452_021 v1.3 293 Peripherals IEEE 802.15.4 ED measurement example

#define ED_RSSISCALE 4 // From electrical specifications uint8_t sample_ed(void) int val;

NRF_RADIO->TASKS_EDSTART = 1; // Start while (NRF_RADIO->EVENTS_EDEND != 1) {

// CPU can sleep here or do something else

// Use of interrupts are encouraged

val = NRF_RADIO->EDSAMPLE; // Read level

return (uint8_t)(val>63 ? 255 : val*ED_RSSISCALE); // Convert to IEEE 802.15.4 scale For scaling between hardware value and dBm, see equation Conversion between hardware value and dBm on page 296. The mlme-scan.req primitive of the MAC layer uses the ED measurement to detect channels where there might be wireless activity. To assist this primitive, a tailored mode of operation is available where the ED measurement runs for a defined number of iterations keeping track of the maximum ED level. This is enganged by writing the EDCNT register to a value different from 0, where it will run the specified number of iterations and report the maximum energy measurement in the EDSAMPLE register. The scan is started with EDSTART task and its end indicated with the EDEND event. This significantly reduces the interrupt frequency and therefore power consumption. The following figure shows how the ED measurement will operate depending on the EDCNT register. EDCNT = 0 EDSTART EDEND 128 s EDCNT = N-1 EDSTART EDEND Scan 0 Scan 1

... Scan N-1 128*(N) s Figure 106: Energy detection measurement examples The scan is stopped by writing the EDSTOP task. It will be followed by the EDSTOPPED event when the module has terminated. 6.18.13.4 Clear channel assessment (CCA) 4452_021 v1.3 294 Peripherals IEEE 802.15.4 implements a listen-before-talk channel access method to avoid collisions when transmitting, known as carrier sense multiple access with collision avoidance (CSMA-CA). The key part of this is measuring if the wireless medium is busy or not. The following clear channel assesment modes are supported:

CCA Mode 1 (energy above threshold): The medium is reported busy upon detecting any energy above the ED threshold. CCA Mode 2 (carrier sense only): The medium is reported busy upon detection of a signal compliant with the IEEE 802.15.4 standard with the same modulation and spreading characteristics. CCA Mode 3 (carrier sense with energy above threshold): The medium is reported busy using a logical combination (AND/OR) between the results from CCA Mode 1 and CCA Mode 2. The clear channel assessment should survey a period equal to 8 symbols or 128 s. The RADIO must be in receive mode and be able to receive correct packets when performing the CCA. The shortcut between READY and START must be disabled if baseband processing is not to be performed while the measurement is running. CCA Mode 1 is enabled by first configuring the field CCACTRL.CCAMODE=EdMode and writing the CCACTRL.CCAEDTHRES field to a chosen value. Once the CCASTART task is written, the RADIO will perform a ED measurement for 8 symbols and compare the measured level with that found in the CCACTRL.CCAEDTHRES field. If the measured value is higher than or equal to this threshold, the CCABUSY event is generated. If the measured level is less than the threshold, the CCAIDLE event is generated. CCA Mode 2 is enabled by configuring CCACTRL.CCAMODE=CarrierMode. The RADIO will sample to see if a valid SFD is found during the 8 symbols. If a valid SFD is detected, the CCABUSY event is generated and the device should not send any data. The CCABUSY event is also generated if the scan was performed during an ongoing frame reception. In the case where the measurement period completes with no SFD detection, the CCAIDLE event is generated. With CCACTRL.CCACORRCNT not being zero, the algorithm will look at the correlator output in addition to the SFD detection signal. If a SFD is reported during the scan period, it will terminate immidiately indicating busy medium. Similarly, if the number of peaks above CCACTRL.CCACORRTHRES crosses the CCACTRL.CCACORRCNT, the CCACTRL.CCABUSY event is generated. If less than CCACORRCOUNT crossings are found and no SFD is reported, the CCAIDLE event will be generated and the device can send data. CCA Mode 3 is enabled by configuring CCACTRL.CCAMODE=CarrierAndEdMode or CCACTRL.CCAMODE=CarrierOrEdMode, performing the required logical combination of the result from CCA Mode 1 and 2. The CCABUSY or CCAIDLE events are generated by ANDing or ORing the energy above threshold and carrier detection scans. CCA Mode 1 CCA Mode 2 CCA Mode 3 Shortcuts An ongoing CCA can always be stopped by issuing the CCASTOP task. This will trigger the associated CCASTOPPED event. For CCA mode automation, a number of shortcuts are available. To automatically switch between RX (when performing the CCA) and to TX where the packet is sent, the shortcut between CCAIDLE and TXEN, in conjunction with the short between CCAIDLE and STOP muse be used. 4452_021 v1.3 295 Peripherals To automatically disable the RADIO whenever the CCA reports a busy medium, the shortcut between CCABUSY and DISABLE can be used. To immediately start a CCA after ramping up into RX mode, the shortcut between RXREADY and CCASTART can be used. Conversion The conversion from a CCAEDTHRES, CCA, or EDLEVEL value to dBm can be done with the following equation, where VALHARDWARE is the hardware-reported values, being either CCAEDTHRES, CCA or EDLEVEL, and constants ED_RSSISCALE and ED_RSSIOFFS are from electrical specifications. PRF[dBm] = ED_RSSIOFFS + ED_RSSISCALE x VALHARDWARE Figure 107: Conversion between hardware value and dBm 6.18.13.5 Cyclic redundancy check (CRC) IEEE 802.15.4 uses a 16-bit ITU-T cyclic redundancy check (CRC) calculated over the MAC header (MHR) and MAC service data unit (MSDU). The standard defines the following generator polynomial:

G(x) = x16 + x12 + x5 + 1 In receive mode the RADIO will trigger the CRC module when the first octet after the frame length (PHR) is received. The CRC will then update on each consecutive octet received. When a complete frame is received the CRCSTATUS register will be updated accordingly and the CRCOK or CRCERROR events generated. When the CRC module is enabled it will not write the two last octets (CRC) to the frame Data RAM. When transmitting, the CRC will be computed on the fly, starting with the first octet after PHR, and inserted as the two last octets in the frame. The EasyDMA will fetch frame length minus 2 octets from RAM and insert the CRC octets insitu. Below is a code snippet for configuring the CRC module for correct operation when in IEEE 802.15.4 mode. The CRCCNF is written to 16-bit CRC and the CRCPOLY is written to 0x11021. The start value used by IEEE 802.15.4 is zero and CRCINIT is configured to reflect this.

/* 16-bit CRC with ITU-T polynomial with 0 as start condition*/

NRF_RADIO->CRCCNF = ((RADIO_CRCCNF_SKIPADDR_Ieee802154 << RADIO_CRCCNF_SKIPADDR_Pos) |

(RADIO_CRCCNF_LEN_Two << RADIO_CRCCNF_LEN_Pos));

NRF_RADIO->CRCPOLY = 0x11021;

NRF_RADIO->CRCINIT = 0;

The ENDIANESS subregister must be set to little-endian since the FCS field is transmitted from left bit to right. 6.18.13.6 Transmit sequence The transmission is started by first putting the RADIO in receive mode and triggering the RXEN task. An outline of the IEEE 802.15.4 transmission is illustrated in the figure below. 4452_021 v1.3 296 Peripherals t e a S t i r e v e c e R

r e t t i m s n a r T e n i l e f i L N E X R RXRU RXIDLE RX TXRU TXIDLE TX TXIDLE TXDISABLE Clear channel SHR PAYLOAD CRC P H R T R A T S E M A R F Y D A E R T R A T S A C C I E L D A C C N E X T Y D A E R T R A T S Figure 108: IEEE 802.15.4 transmit sequence D N E D E L B A S D I E L B A S D I The receiver will ramp up and enter the RXIDLE state where the READY event is generated. Upon receiving the ready event, the CCA is started by triggering the CCASTART task. The chosen mode of assessment

(CCACTRL.CCAMODE register) will be performed and signal the CCAIDLE or CCABUSY event 128 s later. If the CCABUSY event is received, the RADIO will have to retry the CCA after a specific back-off period. This is outlined in the IEEE 802.15.4 standard, Figure 69 in section 7.5.1.4 The CSMA-CA algorithm. If the CCAIDLE event is generated, a write to the TXEN task register enters the RADIO in TXRU state. The READY event will be generated when the RADIO is in TXIDLE state and ready to transmit. With the PACKETPTR pointing to the length (PHR) field of the frame, the START task can be written. The RADIO will send the four octet preamble sequence followed by the start of frame delimiter (SFD register). The first byte read from the Data RAM is the length field (PHR) followed by the transmission of the number of bytes indicated as the frame length. If the CRC module is configured it will run for PHR-2 octets. The last two octets will be substituted with the results from running the CRC. The necessary CRC parameters are sampled on the START task. The FCS field of the frame is little endian. In addition to the already available shortcuts, one is provided between READY event and CCASTART task so that a CCA can automatically start when the receiver is ready. A second shortcut has been added between CCAIDLE event and the TXEN task, so that upon detecting a clear channel the RADIO can immediately enter transmit mode. 6.18.13.7 Receive sequence The reception is started by first putting the RADIO in receive mode. After writing to the RXEN task, the RADIO will start ramping up and enter the RXRU state. When the READY event is generated, the RADIO enters the RXIDLE mode. For the baseband processing to be enabled, the START task must be written. An outline of the IEEE 802.15.4 reception can be found in the figure below. 4452_021 v1.3 297 Peripherals t e a S t n o i t p e c e R e n i l e f i L RXRU RXIDLE RX RXIDLE RXDISABLE X SHR PAYLOAD CRC P H R T R A T S E M A R F D N E D E L B A S D I E L B A S D I Y D A E R N E X R T R A T S Figure 109: IEEE 802.15.4 receive sequence When a valid SHR is received the RADIO will start storing future octets (starting with PHR) to the data memory pointed to by PACKETPTR. After the SFD octet is received the FRAMESTART event is generated. If the CRC module is enabled it will start updating with the second byte received (first byte in payload) and run for the full frame length. The two last bytes in the frame are not written to RAM when CRC is configured. However, if the result of the CRC after running the full frame is zero, the CRCOK event will be generated. The END event is generated when the last octet has been received and is available in data memory. When a packet is received a link quality indicator (LQI) is also generated and appended immediately after the last received octet. When using an IEEE 802.15.4 compliant frame, this will be just after the MSDU since the FCS is not reported. In the case of a non-complient frame it will be appended after the full frame. The LQI reported by hardware must be converted to IEEE 802.15.4 range by an 8-bit saturating multiplication by 4, as shown in IEEE 802.15.4 ED measurement example on page 294. The LQI is only valid for frames equal to or longer than three octets. When receiving a frame the RSSI (reported as negative dB) will be measured at three points during the reception. These three values will be sorted and the middle one selected (median 3) to be remapped within the LQI range. The following figure illustrates the LQI measurement and how the data is arranged in data memory. 4452_021 v1.3 298 Peripherals On air frame 160 s Preamble sequence SFD PHY protocol data unit (PPDU) 5 octets synchronization header (SHR) Maximum 127 octets (PSDU)

<=4064 s PHY payload In RAM frame MAC protocol data unit (MPDU) R S S I Median 3 R S S I 32 s Length 1 octet

(PHR) R S S I Length 1 octet

(PHR) PHY payload Maximum 127 octets (PSDU) LQI 1 octet FCF 2 octets MAC protocol data unit (MPDU) Figure 110: IEEE 802.15.4 frame in data memory Omitted if CRC enabled A shortcut has been added between the FRAMESTART event and the BCSTART task. This can be used to trigger a BCMATCH event after N bits, such as when inspecting the MAC addressing fields. 6.18.13.8 Interframe spacing (IFS) The IEEE 802.15.4 standard defines a specific time that is alotted for the MAC sublayer to process received data. Interframe spacing (IFS) is used to prevent that two frames are transmitted too close together. If the transmission is requesting an acknowledgement, the space before the second frame shall be at least one IFS period. The IFS is determined to be one of the following:

IFS equals macMinSIFSPeriod (12 symbols) if the MPDU is less than or equal to aMaxSIFSFrameSize (18 octets) octets IFS equals macMinLIFSPeriod (40 symbols) if the MPDU is larger than aMaxSIFSFrameSize Using the efficient assisted modes in the RADIO, the TIFS will be programmed with the correct value based on the frame being transmitted. If the assisted modes are not being used the user must update the TIFS register manually. The figure below provides details on what IFS period is valid in both acknowledged and unacknowledged transmissions. 4452_021 v1.3 299 Peripherals Acknowledged transmission Long frame ACK Short frame ACK tack = 32 symbols tlifs = 40 symbols tack = 32 symbols tsifs = 12 symbols Unacknowledged transmission Long frame Short frame tlifs = 40 symbols tsifs = 12 symbols Figure 111: Interframe spacing examples 6.18.14 EasyDMA The RADIO uses EasyDMA to read and write packets to RAM without CPU involvement. As illustrated in RADIO block diagram on page 278, the RADIO's EasyDMA utilizes the same PACKETPTR for receiving and transmitting packets. This pointer should be reconfigured by the CPU each time before RADIO is started by the START task. The PACKETPTR register is double-buffered, meaning that it can be updated and prepared for the next transmission. The END event indicates that the last bit has been processed by the RADIO. The DISABLED event is issued to acknowledge that a DISABLE task is done. The structure of a packet is described in detail in Packet configuration on page 278. The data that is stored in Data RAM and transported by EasyDMA consists of the following fields:

S0 LENGTH S1 PAYLOAD In addition, a static add-on is sent immediately after the payload. The size of each of the above fields in the frame is configurable (see Packet configuration on page 278), and the space occupied in RAM depends on these settings. The size of the field can be zero, as long as the resulting frame complies with the chosen RF protocol. All fields are extended in size to align with a byte boundary in RAM. For instance, a 3-bit long field on air will occupy 1 byte in RAM while a 9-bit long field will be extended to 2 bytes. The packet's elements can be configured as follows:

CI, TERM1, and TERM2 fields are only present in Bluetooth Low Energy Long Range mode S0 is configured through the PCNF0.S0LEN field LENGTH is configured through the PCNF0.LFLEN field S1 is configured through the PCNF0.S1LEN field Payload size is configured through the value in RAM corresponding to the LENGTH field Static add-on size is configured through the PCNF1.STATLEN field The PCNF1.MAXLEN field configures the maximum packet payload plus add-on size in number of bytes that can be transmitted or received by the RADIO. This feature can be used to ensure that the RADIO does not overwrite, or read beyond, the RAM assigned to the packet payload. This means that if the LENGTH field of the packet payload exceedes PCNF1.STATLEN, and the LENGTH field in the packet specifies a packet larger than configured in PCNF1.MAXLEN, the payload will be truncated to the length specified in PCNF1.MAXLEN. 4452_021 v1.3 300 Peripherals Note: The PCNF1.MAXLEN field includes the payload and the add-on, but excludes the size occupied by the S0, LENGTH, and S1 fields. This has to be taken into account when allocating RAM. If the payload and add-on length is specified larger than PCNF1.MAXLEN, the RADIO will still transmit or receive in the same way as before, except the payload is now truncated to PCNF1.MAXLEN. The packet's LENGTH field will not be altered when the payload is truncated. The RADIO will calculate CRC as if the packet length is equal to PCNF1.MAXLEN. Note: If PACKETPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. The END event indicates that the last bit has been processed by the RADIO. The DISABLED event is issued to acknowledge that an DISABLE task is done. Base address Peripheral 0x40001000 RADIO Instance RADIO Description 2.4 GHz radio Configuration Table 83: Instances Offset Description 6.18.15 Registers Register TASKS_TXEN TASKS_RXEN TASKS_START TASKS_STOP TASKS_DISABLE TASKS_RSSISTART TASKS_RSSISTOP TASKS_BCSTART TASKS_BCSTOP TASKS_EDSTART TASKS_EDSTOP TASKS_CCASTART TASKS_CCASTOP EVENTS_READY EVENTS_ADDRESS EVENTS_PAYLOAD EVENTS_END EVENTS_DISABLED EVENTS_DEVMATCH EVENTS_DEVMISS EVENTS_RSSIEND EVENTS_BCMATCH EVENTS_CRCOK EVENTS_CRCERROR EVENTS_FRAMESTART EVENTS_EDEND EVENTS_EDSTOPPED EVENTS_CCAIDLE EVENTS_CCABUSY 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x128 0x130 0x134 0x138 0x13C 0x140 0x144 0x148 Enable RADIO in TX mode Enable RADIO in RX mode Start RADIO Stop RADIO Disable RADIO Stop the RSSI measurement Start the bit counter Stop the bit counter Start the RSSI and take one single sample of the receive signal strength Start the energy detect measurement used in IEEE 802.15.4 mode Stop the energy detect measurement Start the clear channel assessment used in IEEE 802.15.4 mode Stop the clear channel assessment RADIO has ramped up and is ready to be started Address sent or received Packet payload sent or received Packet sent or received RADIO has been disabled A device address match occurred on the last received packet No device address match occurred on the last received packet Sampling of receive signal strength complete Bit counter reached bit count value Packet received with CRC ok Packet received with CRC error IEEE 802.15.4 length field received RADIO.EDSAMPLE register The sampling of energy detection has stopped Wireless medium in idle - clear to send Wireless medium busy - do not send Sampling of energy detection complete. A new ED sample is ready for readout from the 4452_021 v1.3 301 Peripherals Register EVENTS_CCASTOPPED EVENTS_RATEBOOST EVENTS_TXREADY EVENTS_RXREADY EVENTS_SYNC EVENTS_PHYEND Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. Description The CCA has stopped RADIO has ramped up and is ready to be started TX path RADIO has ramped up and is ready to be started RX path Preamble indicator Generated when last bit is sent on air, or received from air EVENTS_MHRMATCH MAC header match found EVENTS_CTEPRESENT CTE is present (early warning right after receiving CTEInfo byte) Shortcuts between local events and tasks Offset 0x14C 0x150 0x154 0x158 0x15C 0x168 0x16C 0x170 0x200 0x304 0x308 0x400 0x408 0x40C 0x410 0x414 0x44C 0x458 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0x520 0x524 0x528 0x52C 0x530 0x534 0x538 0x53C 0x544 0x548 0x550 0x554 0x560 0x600 0x620 0x640 0x644 0x648 0x650 0x660 0x664 0x668 0x66C 0x900 0x904 0x910 0x914 0x928 SHORTS INTENSET INTENCLR CRCSTATUS RXMATCH RXCRC DAI PDUSTAT CTESTATUS DFESTATUS PACKETPTR FREQUENCY TXPOWER MODE PCNF0 PCNF1 BASE0 BASE1 PREFIX0 PREFIX1 TXADDRESS RXADDRESSES CRCCNF CRCPOLY CRCINIT TIFS RSSISAMPLE STATE DATAWHITEIV BCC DAB[n]

DAP[n]

DACNF MHRMATCHCONF MHRMATCHMAS MODECNF0 SFD EDCNT EDSAMPLE CCACTRL DFEMODE CTEINLINECONF DFECTRL1 DFECTRL2 SWITCHPATTERN Enable interrupt Disable interrupt CRC status Received address CRC field of previously received packet Device address match index Payload status CTEInfo parsed from received packet DFE status information Packet pointer Frequency Output power Data rate and modulation Packet configuration register 0 Packet configuration register 1 Base address 0 Base address 1 Prefixes bytes for logical addresses 0-3 Prefixes bytes for logical addresses 4-7 Transmit address select Receive address select CRC configuration CRC polynomial CRC initial value Interframe spacing in s RSSI sample Current radio state Data whitening initial value Bit counter compare Device address base segment n Device address prefix n Device address match configuration Search pattern configuration Pattern mask Radio mode configuration register 0 IEEE 802.15.4 start of frame delimiter IEEE 802.15.4 energy detect loop count IEEE 802.15.4 energy detect level IEEE 802.15.4 clear channel assessment control Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) Configuration for CTE inline mode Various configuration for Direction finding Start offset for Direction finding GPIO patterns to be used for each antenna 4452_021 v1.3 302 Clear the GPIO pattern array for antenna control Register CLEARPATTERN PSEL.DFEGPIO[0]

PSEL.DFEGPIO[1]

PSEL.DFEGPIO[2]

PSEL.DFEGPIO[3]

PSEL.DFEGPIO[4]

PSEL.DFEGPIO[5]

PSEL.DFEGPIO[6]

PSEL.DFEGPIO[7]

DFEPACKET.PTR DFEPACKET.MAXCNT DFEPACKET.AMOUNT POWER Offset 0x92C 0x930 0x934 0x938 0x93C 0x940 0x944 0x948 0x94C 0x950 0x954 0x958 0xFFC Description Pin select for DFE pin 0 Pin select for DFE pin 1 Pin select for DFE pin 2 Pin select for DFE pin 3 Pin select for DFE pin 4 Pin select for DFE pin 5 Pin select for DFE pin 6 Pin select for DFE pin 7 Data pointer Maximum number of buffer words to transfer Number of samples transferred in the last transaction Peripheral power control Table 84: Register overview 6.18.15.1 TASKS_TXEN Address offset: 0x000 Enable RADIO in TX mode Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_TXEN Enable RADIO in TX mode Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_RXEN Enable RADIO in RX mode Trigger 1 Trigger task 6.18.15.2 TASKS_RXEN Address offset: 0x004 Enable RADIO in RX mode 6.18.15.3 TASKS_START Address offset: 0x008 Start RADIO ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value W TASKS_START Trigger 1 Description Start RADIO Trigger task 4452_021 v1.3 303 Peripherals A A A Peripherals A A A A 6.18.15.4 TASKS_STOP Address offset: 0x00C Stop RADIO 6.18.15.5 TASKS_DISABLE Address offset: 0x010 Disable RADIO Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value W TASKS_STOP Trigger 1 Description Stop RADIO Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value W TASKS_DISABLE Trigger 1 Description Disable RADIO Trigger task 6.18.15.6 TASKS_RSSISTART Address offset: 0x014 Start the RSSI and take one single sample of the receive signal strength Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_RSSISTART Start the RSSI and take one single sample of the receive Trigger 1 signal strength Trigger task 6.18.15.7 TASKS_RSSISTOP Address offset: 0x018 Stop the RSSI measurement Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_RSSISTOP Stop the RSSI measurement Trigger 1 Trigger task 4452_021 v1.3 304 ID ID A ID ID A ID ID A ID ID A Peripherals A A A A 6.18.15.8 TASKS_BCSTART Address offset: 0x01C Start the bit counter 6.18.15.9 TASKS_BCSTOP Address offset: 0x020 Stop the bit counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_BCSTART Start the bit counter Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_BCSTOP Stop the bit counter Trigger 1 Trigger task 6.18.15.10 TASKS_EDSTART Address offset: 0x024 Start the energy detect measurement used in IEEE 802.15.4 mode Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_EDSTART Start the energy detect measurement used in IEEE 802.15.4 Trigger 1 mode Trigger task 6.18.15.11 TASKS_EDSTOP Address offset: 0x028 Stop the energy detect measurement Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_EDSTOP Stop the energy detect measurement Trigger 1 Trigger task 4452_021 v1.3 305 ID ID A ID ID A ID ID A ID ID A Peripherals 6.18.15.12 TASKS_CCASTART Address offset: 0x02C Start the clear channel assessment used in IEEE 802.15.4 mode Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_CCASTART Start the clear channel assessment used in IEEE 802.15.4 Trigger 1 mode Trigger task 6.18.15.13 TASKS_CCASTOP Address offset: 0x030 Stop the clear channel assessment Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_CCASTOP Stop the clear channel assessment Trigger 1 Trigger task 6.18.15.14 EVENTS_READY Address offset: 0x100 RADIO has ramped up and is ready to be started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_READY RADIO has ramped up and is ready to be started NotGenerated Generated Event not generated Event generated 6.18.15.15 EVENTS_ADDRESS Address offset: 0x104 Address sent or received Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ADDRESS NotGenerated Generated Address sent or received Event not generated Event generated 4452_021 v1.3 306 0 1 0 1 ID ID A ID ID A ID ID A ID ID A A A A A Peripherals A A A 6.18.15.16 EVENTS_PAYLOAD Address offset: 0x108 Packet payload sent or received 6.18.15.17 EVENTS_END Address offset: 0x10C Packet sent or received Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_PAYLOAD Packet payload sent or received NotGenerated Generated Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_END NotGenerated Generated Packet sent or received Event not generated Event generated 6.18.15.18 EVENTS_DISABLED Address offset: 0x110 RADIO has been disabled Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_DISABLED NotGenerated Generated RADIO has been disabled Event not generated Event generated 6.18.15.19 EVENTS_DEVMATCH Address offset: 0x114 A device address match occurred on the last received packet ID ID A ID ID A ID ID A 0 1 0 1 0 1 4452_021 v1.3 307 ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_DEVMATCH A device address match occurred on the last received Peripherals NotGenerated Generated packet Event not generated Event generated 6.18.15.20 EVENTS_DEVMISS Address offset: 0x118 No device address match occurred on the last received packet Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_DEVMISS No device address match occurred on the last received 0 1 0 1 NotGenerated Generated packet Event not generated Event generated 6.18.15.21 EVENTS_RSSIEND Address offset: 0x11C Sampling of receive signal strength complete A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RSSIEND Sampling of receive signal strength complete NotGenerated Generated 0 1 A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register Event not generated Event generated A A A 6.18.15.22 EVENTS_BCMATCH Address offset: 0x128 Bit counter reached bit count value Bit counter value is specified in the RADIO.BCC register 4452_021 v1.3 308

 

 

Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_BCMATCH Bit counter reached bit count value NotGenerated Generated Event not generated Event generated Bit counter value is specified in the RADIO.BCC register 6.18.15.23 EVENTS_CRCOK Address offset: 0x130 Packet received with CRC ok Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CRCOK NotGenerated Generated Packet received with CRC ok Event not generated Event generated 6.18.15.24 EVENTS_CRCERROR Address offset: 0x134 Packet received with CRC error Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CRCERROR Packet received with CRC error NotGenerated Generated Event not generated Event generated 6.18.15.25 EVENTS_FRAMESTART Address offset: 0x138 IEEE 802.15.4 length field received Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_FRAMESTART IEEE 802.15.4 length field received NotGenerated Generated Event not generated Event generated ID ID A ID ID A ID ID A ID ID A A A A A 0 1 0 1 0 1 0 1 6.18.15.26 EVENTS_EDEND Address offset: 0x13C 4452_021 v1.3 309 Peripherals Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_EDEND Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register NotGenerated Generated Event not generated Event generated 6.18.15.27 EVENTS_EDSTOPPED Address offset: 0x140 The sampling of energy detection has stopped Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_EDSTOPPED The sampling of energy detection has stopped NotGenerated Generated Event not generated Event generated 6.18.15.28 EVENTS_CCAIDLE Address offset: 0x144 Wireless medium in idle - clear to send 6.18.15.29 EVENTS_CCABUSY Address offset: 0x148 Wireless medium busy - do not send Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CCAIDLE Wireless medium in idle - clear to send NotGenerated Generated Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CCABUSY Wireless medium busy - do not send NotGenerated Generated Event not generated Event generated 4452_021 v1.3 310 ID ID A ID ID A ID ID A ID ID A A A A A 0 1 0 1 0 1 0 1 Peripherals 6.18.15.30 EVENTS_CCASTOPPED Address offset: 0x14C The CCA has stopped ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CCASTOPPED NotGenerated Generated The CCA has stopped Event not generated Event generated 6.18.15.31 EVENTS_RATEBOOST Address offset: 0x150 Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RATEBOOST Ble_LR CI field received, receive mode is changed from NotGenerated Generated Ble_LR125Kbit to Ble_LR500Kbit. Event not generated Event generated 6.18.15.32 EVENTS_TXREADY Address offset: 0x154 RADIO has ramped up and is ready to be started TX path Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_TXREADY RADIO has ramped up and is ready to be started TX path NotGenerated Generated Event not generated Event generated A A A 0 1 0 1 0 1 6.18.15.33 EVENTS_RXREADY Address offset: 0x158 RADIO has ramped up and is ready to be started RX path 4452_021 v1.3 311 0 1 0 1 ID ID A ID ID A ID ID A Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RXREADY RADIO has ramped up and is ready to be started RX path NotGenerated Generated Event not generated Event generated 6.18.15.34 EVENTS_MHRMATCH Address offset: 0x15C MAC header match found Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_MHRMATCH NotGenerated Generated 6.18.15.35 EVENTS_SYNC Address offset: 0x168 Preamble indicator MAC header match found Event not generated Event generated A possible preamble has been received in Ble_LR125Kbit, Ble_LR500Kbit or Ieee802154_250Kbit modes during an RX transaction. False triggering of the event is possible. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_SYNC Preamble indicator A possible preamble has been received in Ble_LR125Kbit, Ble_LR500Kbit or Ieee802154_250Kbit modes during an RX transaction. False triggering of the event is possible. NotGenerated Generated 0 1 Event not generated Event generated 6.18.15.36 EVENTS_PHYEND Address offset: 0x16C Generated when last bit is sent on air, or received from air A A A 4452_021 v1.3 312 ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_PHYEND Generated when last bit is sent on air, or received from air NotGenerated Generated Event not generated Event generated 6.18.15.37 EVENTS_CTEPRESENT Address offset: 0x170 CTE is present (early warning right after receiving CTEInfo byte) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CTEPRESENT CTE is present (early warning right after receiving CTEInfo NotGenerated Generated byte) Event not generated Event generated Peripherals A A 6.18.15.38 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 U T S R Q P O N M L K H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW READY_START Shortcut between event READY and task START Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled B RW END_DISABLE Shortcut between event END and task DISABLE C RW DISABLED_TXEN Shortcut between event DISABLED and task TXEN D RW DISABLED_RXEN Shortcut between event DISABLED and task RXEN E RW ADDRESS_RSSISTART Shortcut between event ADDRESS and task RSSISTART F RW END_START Shortcut between event END and task START G RW ADDRESS_BCSTART Shortcut between event ADDRESS and task BCSTART H RW DISABLED_RSSISTOP Shortcut between event DISABLED and task RSSISTOP 4452_021 v1.3 313 Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 U T S R Q P O N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Peripherals K RW RXREADY_CCASTART Shortcut between event RXREADY and task CCASTART L RW CCAIDLE_TXEN Shortcut between event CCAIDLE and task TXEN M RW CCABUSY_DISABLE Shortcut between event CCABUSY and task DISABLE N RW FRAMESTART_BCSTART Shortcut between event FRAMESTART and task BCSTART O RW READY_EDSTART Shortcut between event READY and task EDSTART P RW EDEND_DISABLE Shortcut between event EDEND and task DISABLE Q RW CCAIDLE_STOP Shortcut between event CCAIDLE and task STOP R RW TXREADY_START Shortcut between event TXREADY and task START S RW RXREADY_START Shortcut between event RXREADY and task START T RW PHYEND_DISABLE Shortcut between event PHYEND and task DISABLE U RW PHYEND_START Shortcut between event PHYEND and task START Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Value ID Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled 6.18.15.39 INTENSET Address offset: 0x304 Enable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW READY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a Z Y V U T S R Q P O N M L K I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event READY Set Disabled Enabled Enable Read: Disabled Read: Enabled 4452_021 v1.3 314 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 Bit number ID ID B Reset 0x00000000 AccessField RW ADDRESS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a Z Y V U T S R Q P O N M L K I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event ADDRESS Peripherals C RW PAYLOAD Write '1' to enable interrupt for event PAYLOAD D RW END Write '1' to enable interrupt for event END E RW DISABLED Write '1' to enable interrupt for event DISABLED F RW DEVMATCH Write '1' to enable interrupt for event DEVMATCH G RW DEVMISS Write '1' to enable interrupt for event DEVMISS H RW RSSIEND Write '1' to enable interrupt for event RSSIEND A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register I RW BCMATCH Write '1' to enable interrupt for event BCMATCH Bit counter value is specified in the RADIO.BCC register K RW CRCOK Write '1' to enable interrupt for event CRCOK L RW CRCERROR Write '1' to enable interrupt for event CRCERROR M RW FRAMESTART Write '1' to enable interrupt for event FRAMESTART N RW EDEND Write '1' to enable interrupt for event EDEND 4452_021 v1.3 315 Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 Peripherals Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a Z Y V U T S R Q P O N M L K I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value O RW EDSTOPPED Write '1' to enable interrupt for event EDSTOPPED P RW CCAIDLE Write '1' to enable interrupt for event CCAIDLE Q RW CCABUSY Write '1' to enable interrupt for event CCABUSY R RW CCASTOPPED Write '1' to enable interrupt for event CCASTOPPED S RW RATEBOOST Write '1' to enable interrupt for event RATEBOOST T RW TXREADY Write '1' to enable interrupt for event TXREADY U RW RXREADY Write '1' to enable interrupt for event RXREADY V RW MHRMATCH Write '1' to enable interrupt for event MHRMATCH Y RW SYNC Write '1' to enable interrupt for event SYNC A possible preamble has been received in Ble_LR125Kbit, Ble_LR500Kbit or Ieee802154_250Kbit modes during an RX transaction. False triggering of the event is possible. Z RW PHYEND Write '1' to enable interrupt for event PHYEND a RW CTEPRESENT Write '1' to enable interrupt for event CTEPRESENT Description Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Value ID Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 4452_021 v1.3 316 Peripherals 6.18.15.40 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW READY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a Z Y V U T S R Q P O N M L K I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event READY Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled B RW ADDRESS Write '1' to disable interrupt for event ADDRESS C RW PAYLOAD Write '1' to disable interrupt for event PAYLOAD D RW END Write '1' to disable interrupt for event END E RW DISABLED Write '1' to disable interrupt for event DISABLED F RW DEVMATCH Write '1' to disable interrupt for event DEVMATCH G RW DEVMISS Write '1' to disable interrupt for event DEVMISS H RW RSSIEND Write '1' to disable interrupt for event RSSIEND A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register I RW BCMATCH Write '1' to disable interrupt for event BCMATCH Bit counter value is specified in the RADIO.BCC register K RW CRCOK Write '1' to disable interrupt for event CRCOK L RW CRCERROR Write '1' to disable interrupt for event CRCERROR 4452_021 v1.3 317 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a Z Y V U T S R Q P O N M L K I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Peripherals M RW FRAMESTART Write '1' to disable interrupt for event FRAMESTART N RW EDEND Write '1' to disable interrupt for event EDEND O RW EDSTOPPED Write '1' to disable interrupt for event EDSTOPPED P RW CCAIDLE Write '1' to disable interrupt for event CCAIDLE Q RW CCABUSY Write '1' to disable interrupt for event CCABUSY R RW CCASTOPPED Write '1' to disable interrupt for event CCASTOPPED S RW RATEBOOST Write '1' to disable interrupt for event RATEBOOST T RW TXREADY Write '1' to disable interrupt for event TXREADY U RW RXREADY Write '1' to disable interrupt for event RXREADY V RW MHRMATCH Write '1' to disable interrupt for event MHRMATCH Y RW SYNC Write '1' to disable interrupt for event SYNC A possible preamble has been received in Ble_LR125Kbit, Ble_LR500Kbit or Ieee802154_250Kbit modes during an RX transaction. False triggering of the event is possible. Description Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Value ID Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 4452_021 v1.3 318 Peripherals Bit number ID ID Z Reset 0x00000000 AccessField RW PHYEND 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a Z Y V U T S R Q P O N M L K I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event PHYEND a RW CTEPRESENT Write '1' to disable interrupt for event CTEPRESENT Clear Disabled Enabled Clear Disabled Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description CRC status of packet received Packet received with CRC error Packet received with CRC ok 1 0 1 1 0 1 0 1 6.18.15.41 CRCSTATUS Address offset: 0x400 CRC status R CRCSTATUS CRCError CRCOk 6.18.15.42 RXMATCH Address offset: 0x408 Received address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A Value ID Value Description Reset 0x00000000 AccessField R RXMATCH Received address Logical address of which previous packet was received 6.18.15.43 RXCRC Address offset: 0x40C CRC field of previously received packet Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Reset 0x00000000 AccessField R RXCRC CRC field of previously received packet CRC field of previously received packet 4452_021 v1.3 319 ID ID A ID ID A ID ID A Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Device address match index Index (n) of device address, see DAB[n] and DAP[n], that got an address match 6.18.15.44 DAI Address offset: 0x410 Device address match index Bit number ID ID A Reset 0x00000000 AccessField R DAI 6.18.15.45 PDUSTAT Address offset: 0x414 Payload status Bit number ID ID A Reset 0x00000000 AccessField R PDUSTAT 6.18.15.46 CTESTATUS Address offset: 0x44C CTEInfo parsed from received packet ID A B C Reset 0x00000000 ID AccessField R R R CTETIME RFU CTETYPE 6.18.15.47 DFESTATUS Address offset: 0x458 DFE status information 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B R CISTAT Status on what rate packet is received with in Long Range Value ID Value Description LessThan GreaterThan LR125kbit LR500kbit 0 1 0 1 Status on payload length vs. PCNF1.MAXLEN Payload less than PCNF1.MAXLEN Payload greater than PCNF1.MAXLEN Frame is received at 125 kbps Frame is received at 500 kbps Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C C B A A A A A Value ID Value Description CTETime parsed from packet RFU parsed from packet CTEType parsed from packet 4452_021 v1.3 320 ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R SWITCHINGSTATE Internal state of switching state machine Peripherals B A A A Idle Offset Guard Ref Switching Ending Idle Sampling Switching state Idle Switching state Offset Switching state Guard Switching state Ref Switching state Switching Switching state Ending Sampling state Idle Sampling state Sampling B R SAMPLINGSTATE Internal state of sampling state machine 6.18.15.48 PACKETPTR Address offset: 0x504 Packet pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value RW PACKETPTR Description Packet pointer Packet address to be used for the next transmission or reception. When transmitting, the packet pointed to by this address will be transmitted and when receiving, the received packet will be written to this address. This address is a byte aligned RAM address. Note: See the memory chapter for details about which memories are available for EasyDMA. 6.18.15.49 FREQUENCY Address offset: 0x508 Frequency Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A A A A A A A Reset 0x00000002 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 AccessField Value ID RW FREQUENCY Value

[0..100]

Description Radio channel frequency B RW MAP Default Low Frequency = 2400 + FREQUENCY (MHz). Channel map selection. Channel map between 2400 MHZ .. 2500 MHz Frequency = 2400 + FREQUENCY (MHz) Channel map between 2360 MHZ .. 2460 MHz Frequency = 2360 + FREQUENCY (MHz) 4452_021 v1.3 321 0 1 2 3 4 5 0 1 0 1 6.18.15.50 TXPOWER Address offset: 0x50C Output power Bit number ID ID A Reset 0x00000000 AccessField RW TXPOWER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RADIO output power Output power in number of dBm, i.e. if the value -20 is specified the output power will be set to -20 dBm. Pos8dBm Pos7dBm Pos6dBm Pos5dBm Pos4dBm Pos3dBm Pos2dBm 0dBm Neg4dBm Neg8dBm Neg12dBm Neg16dBm Neg20dBm Neg30dBm Neg40dBm 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x0 0xFC 0xF8 0xF4 0xF0 0xEC 0xE2 0xD8

+8 dBm

+7 dBm

+6 dBm

+5 dBm

+4 dBm

+3 dBm

+2 dBm 0 dBm

-4 dBm

-8 dBm

-12 dBm

-16 dBm

-20 dBm

-40 dBm

-40 dBm Peripherals Deprecated 6.18.15.51 MODE Address offset: 0x510 Data rate and modulation Bit number ID ID A Reset 0x00000000 AccessField RW MODE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Nrf_1Mbit Nrf_2Mbit Ble_1Mbit Ble_2Mbit Ble_LR125Kbit Ble_LR500Kbit 0 1 3 4 5 6 Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. 1 Mbps Nordic proprietary radio mode 2 Mbps Nordic proprietary radio mode 1 Mbps BLE 2 Mbps BLE Long range 125 kbps TX, 125 kbps and 500 kbps RX Long range 500 kbps TX, 125 kbps and 500 kbps RX Ieee802154_250Kbit 15 IEEE 802.15.4-2006 250 kbps 6.18.15.52 PCNF0 Address offset: 0x514 Packet configuration register 0 4452_021 v1.3 322 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 J J I H H G G F E E E E C A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Peripherals Reset 0x00000000 ID AccessField RW LFLEN RW S0LEN RW S1LEN RW S1INCL RW CILEN RW PLEN RW CRCINC ID A C E F G H I J ID ID A Length on air of LENGTH field in number of bits. Length on air of S0 field in number of bytes. Length on air of S1 field in number of bits. Include or exclude S1 field in RAM Include S1 field in RAM only if S1LEN > 0 Always include S1 field in RAM independent of S1LEN Length of code indicator - long range Length of preamble on air. Decision point: TASKS_START task 8-bit preamble 16-bit preamble 32-bit zero preamble - used for IEEE 802.15.4 Preamble - used for BLE long range Indicates if LENGTH field contains CRC or not LENGTH does not contain CRC LENGTH includes CRC Automatic Include 8bit 16bit 32bitZero LongRange Exclude Include RW TERMLEN Length of TERM field in Long Range operation 6.18.15.53 PCNF1 Address offset: 0x518 Packet configuration register 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW MAXLEN Value ID Description Value

[0..255]

E D C C C B B B B B B B B A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B RW STATLEN

[0..255]

Static length in number of bytes Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. The static length parameter is added to the total length of the payload when sending and receiving packets, e.g. if the static length is set to N the radio will receive or send N bytes more than what is defined in the LENGTH field of the packet. The address field is composed of the base address and the one byte long address prefix, e.g. set BALEN=2 to get a total address of 3 bytes. S1, and the PAYLOAD fields. Least significant bit on air first Most significant bit on air first Enable or disable packet whitening Disable Enable C RW BALEN

[2..4]

Base address length in number of bytes D RW ENDIAN On-air endianness of packet, this applies to the S0, LENGTH, E RW WHITEEN Little Big Disabled Enabled 4452_021 v1.3 323 0 1 0 1 2 3 0 1 0 1 0 1 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Base address 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW BASE1 Value ID Value Description Base address 1 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit number ID Reset 0x00000000 ID AccessField A-D RW AP[i] (i=0..3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Address prefix i. 6.18.15.54 BASE0 Address offset: 0x51C Base address 0 Reset 0x00000000 AccessField RW BASE0 6.18.15.55 BASE1 Address offset: 0x520 Base address 1 ID ID A ID ID A 6.18.15.56 PREFIX0 Address offset: 0x524 Prefixes bytes for logical addresses 0-3 6.18.15.57 PREFIX1 Address offset: 0x528 Prefixes bytes for logical addresses 4-7 Bit number ID Reset 0x00000000 ID AccessField A-D RW AP[i] (i=4..7) 6.18.15.58 TXADDRESS Address offset: 0x52C Transmit address select 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Address prefix i. 4452_021 v1.3 324 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW TXADDRESS Transmit address select Logical address to be used when transmitting a packet Peripherals A A A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-H RW ADDR[i] (i=0..7) Enable or disable reception on logical address i. Value ID Value Description Disabled Enabled Disable Enable 6.18.15.59 RXADDRESSES Address offset: 0x530 Receive address select Bit number ID Reset 0x00000000 ID AccessField 6.18.15.60 CRCCNF Address offset: 0x534 CRC configuration Bit number ID ID A Reset 0x00000000 AccessField RW LEN B RW SKIPADDR Disabled One Two Three Include Skip 6.18.15.61 CRCPOLY Address offset: 0x538 CRC polynomial 0 1 0 1 2 3 0 1 2 4452_021 v1.3 325 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Description Value

[1..3]

CRC length in number of bytes. Note: For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported CRC length is zero and CRC calculation is disabled CRC length is one byte and CRC calculation is enabled CRC length is two bytes and CRC calculation is enabled CRC length is three bytes and CRC calculation is enabled Include or exclude packet address field out of CRC calculation. CRC calculation includes address field CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. Ieee802154 CRC calculation as per 802.15.4 standard. Starting at first byte after length field. Bit number ID ID A Reset 0x00000000 AccessField RW CRCPOLY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description CRC polynomial Peripherals Each term in the CRC polynomial is mapped to a bit in this register which index corresponds to the term's exponent. The least significant term/bit is hardwired internally to 1, and bit number 0 of the register content is ignored by the hardware. The following example is for an 8 bit CRC polynomial: x8 + x7 + x3 + x2 + 1 = 1 1000 1101 . 6.18.15.62 CRCINIT Address offset: 0x53C CRC initial value Reset 0x00000000 AccessField RW CRCINIT 6.18.15.63 TIFS Address offset: 0x544 Interframe spacing in s ID ID A ID ID A 6.18.15.64 RSSISAMPLE Address offset: 0x548 RSSI sample Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description CRC initial value Initial value for CRC calculation Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A Value ID Value Description Reset 0x00000000 AccessField RW TIFS Interframe spacing in s Interframe space is the time interval between two consecutive packets. It is defined as the time, in microseconds, from the end of the last bit of the previous packet to the start of the first bit of the subsequent packet. 4452_021 v1.3 326 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID R RSSISAMPLE Value

[0..127]

Description RSSI sample Peripherals A A A A A A A RSSI sample result. The value of this register is read as a positive value while the actual received signal strength is a negative value. Actual received signal strength is therefore as follows: received signal strength = -A dBm 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled RxRu RxIdle Rx TxRu TxIdle Tx RxDisable TxDisable 0 1 2 3 4 9 10 11 12 Current radio state RADIO is in the Disabled state RADIO is in the RXRU state RADIO is in the RXIDLE state RADIO is in the RX state RADIO is in the RXDISABLED state RADIO is in the TXRU state RADIO is in the TXIDLE state RADIO is in the TX state RADIO is in the TXDISABLED state ID ID A ID ID A 6.18.15.65 STATE Address offset: 0x550 Current radio state Bit number ID ID A Reset 0x00000000 AccessField R STATE 6.18.15.66 DATAWHITEIV Address offset: 0x554 Data whitening initial value Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A Reset 0x00000040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 AccessField Value ID Value Description RW DATAWHITEIV Data whitening initial value. Bit 6 is hardwired to '1', writing

'0' to it has no effect, and it will always be read back and used by the device as '1'. Bit 0 corresponds to Position 6 of the LSFR, Bit 1 to Position 5, etc. 6.18.15.67 BCC Address offset: 0x560 Bit counter compare 4452_021 v1.3 327 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Reset 0x00000000 AccessField RW BCC Bit counter compare Bit counter compare register ID ID A ID ID A ID ID A 6.18.15.68 DAB[n] (n=0..7) Address offset: 0x600 + (n 0x4) Device address base segment n 6.18.15.69 DAP[n] (n=0..7) Address offset: 0x620 + (n 0x4) Device address prefix n 6.18.15.70 DACNF Address offset: 0x640 Device address match configuration Bit number ID Reset 0x00000000 ID AccessField 6.18.15.71 MHRMATCHCONF Address offset: 0x644 Search pattern configuration Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW DAB Value ID Value Description Device address base segment n A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW DAP Value ID Value Description Device address prefix n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-H RW ENA[i] (i=0..7) Enable or disable device address matching using device Value ID Value Description Disabled Enabled 0 1 address i Disabled Enabled I-P RW TXADD[i] (i=0..7) TxAdd for device address i 4452_021 v1.3 328 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW MHRMATCHCONF Search pattern configuration Peripherals ID ID A ID ID A ID ID A 6.18.15.72 MHRMATCHMAS Address offset: 0x648 Pattern mask 6.18.15.73 MODECNF0 Address offset: 0x650 Radio mode configuration register 0 Reset 0x00000200 AccessField RW RU Default Fast Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value RW MHRMATCHMAS Description Pattern mask Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 C C A Value ID Value Description C RW DTX Default TX value Radio ramp-up time Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information When enabled, TIFS is not enforced by hardware and software needs to control when to turn on the Radio. Specifies what the RADIO will transmit when it is not started, i.e. between:

RADIO.EVENTS_READY and RADIO.TASKS_START RADIO.EVENTS_END and RADIO.TASKS_START RADIO.EVENTS_END and RADIO.EVENTS_DISABLED Note: For IEEE 802.15.4 250 kbps mode only Center is a valid setting Note: For Bluetooth Low Energy Long Range mode only Center is a valid setting 0 1 0 1 B1 B0 Transmit '1'

Transmit '0'

4452_021 v1.3 329 Peripherals Bit number ID Reset 0x00000200 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C C A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Value ID Center Value 2 Description Transmit center frequency When tuning the crystal for center frequency, the RADIO must be set in DTX = Center mode to be able to achieve the expected accuracy ID ID A ID ID A ID ID A 6.18.15.74 SFD Address offset: 0x660 IEEE 802.15.4 start of frame delimiter AccessField RW SFD 6.18.15.75 EDCNT Address offset: 0x664 IEEE 802.15.4 energy detect loop count Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A Reset 0x000000A7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 Value ID Value Description IEEE 802.15.4 start of frame delimiter Number of iterations to perform an ED scan. If set to 0 one scan is performed, otherwise the specified number + 1 of ED scans will be performed and the max ED value tracked in EDSAMPLE. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A A A A A A Value ID Value Description IEEE 802.15.4 energy detect loop count Reset 0x00000000 AccessField RW EDCNT 6.18.15.76 EDSAMPLE Address offset: 0x668 IEEE 802.15.4 energy detect level Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R EDLVL Value ID Description Value

[0..127]

IEEE 802.15.4 energy detect level 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A Register value must be converted to IEEE 802.15.4 range by an 8-bit saturating multiplication by factor ED_RSSISCALE, as shown in the code example for ED sampling 6.18.15.77 CCACTRL Address offset: 0x66C IEEE 802.15.4 clear channel assessment control 4452_021 v1.3 330 ID ID A C D ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D D D D D D D D C C C C C C C C B B B B B B B B A A A Reset 0x052D0000 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW CCAMODE Peripherals EdMode CarrierMode CarrierAndEdMode CarrierOrEdMode EdModeTest1 B RW CCAEDTHRES RW CCACORRTHRES RW CCACORRCNT 6.18.15.78 DFEMODE Address offset: 0x900 Will report busy whenever energy is detected above CCA mode of operation Energy above threshold CCAEDTHRES Carrier seen seen Will report busy whenever compliant IEEE 802.15.4 signal is Energy above threshold AND carrier seen Energy above threshold OR carrier seen Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. CCA energy busy threshold. Used in all the CCA modes except CarrierMode. Must be converted from IEEE 802.15.4 range by dividing by factor ED_RSSISCALE - similar to EDSAMPLE register CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW DFEOPMODE Disabled AoD AoA Direction finding operation mode Direction finding mode disabled Direction finding mode set to AoD Direction finding mode set to AoA 6.18.15.79 CTEINLINECONF Address offset: 0x904 Configuration for CTE inline mode Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I I I I I I I I H H H H H H H H G G G F F F E E C B A Reset 0x00002800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW CTEINLINECTRLEN Enable parsing of CTEInfo from received packet in BLE Enabled Disabled B RW CTEINFOINS1 modes Parsing of CTEInfo is enabled Parsing of CTEInfo is disabled CTEInfo is S1 byte or not 4452_021 v1.3 331 0 1 2 3 4 0 2 3 1 0 Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I I I I I I I I H H H H H H H H G G G F F F E E C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Value Description E RW CTETIMEVALIDRANGE Max range of CTETime Bit number ID Reset 0x00002800 ID AccessField C RW CTEERRORHANDLING F RW CTEINLINERXMODE1US G RW CTEINLINERXMODE2US Value ID InS1 NotInS1 Yes No 20 31 63 4us 2us 1us 500ns 250ns 125ns 4us 2us 1us 500ns 250ns 125ns 1 0 1 0 0 1 2 1 2 3 4 5 6 1 2 3 4 5 6 CTEInfo is in S1 byte (data PDU) CTEInfo is NOT in S1 byte (advertising PDU) Sampling/switching if CRC is not OK Sampling and antenna switching also when CRC is not OK No sampling and antenna switching when CRC is not OK Note: Valid range is 2-20 in BLE core spec. If larger than 20, it can be an indication of an error in the received packet. 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 31 in 8us unit 63 in 8us unit Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set When the device is in AoD mode, this is used when the received CTEType is "AoD 1 us". When in AoA mode, this is used when TSWITCHSPACING is 2 us. Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set When the device is in AoD mode, this is used when the received CTEType is "AoD 2 us". When in AoA mode, this is used when TSWITCHSPACING is 4 us. 4us 2us 1us 0.5us 0.25us 0.125us 4us 2us 1us 0.5us 0.25us 0.125us The least significant bit always corresponds to the first bit of S0 received. S0 bit mask to set which bit to match The least significant bit always corresponds to the first bit of S0 received. H RW S0CONF S0 bit pattern to match I RW S0MASK 6.18.15.80 DFECTRL1 Address offset: 0x910 Various configuration for Direction finding 4452_021 v1.3 332 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I I I I H H H H G G G F E E E C C C B A A A A A A Reset 0x00023282 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 AccessField Value ID Value Description RW NUMBEROF8US Length of the AoA/AoD procedure in number of 8 us units ID ID A Peripherals B RW DFEINEXTENSION Add CTE extension and do antenna switching/sampling in Always used in TX mode, but in RX mode only when CTEINLINECTRLEN is 0 this extension AoA/AoD procedure triggered at end of CRC Antenna switching/sampling is done in the packet payload Interval between every time the antenna is changed in the SWITCHING state E RW TSAMPLESPACINGREF Interval between samples in the REFERENCE period C RW TSWITCHSPACING F RW SAMPLETYPE G RW TSAMPLESPACING Interval between samples in the SWITCHING period when 4us 2us 1us 4us 2us 1us 0.5us 0.25us 0.125us 4us 2us 1us 0.5us 0.25us 0.125us Whether to sample I/Q or magnitude/phase Complex samples in I and Q Complex samples as magnitude and phase CTEINLINECTRLEN is 0 Note: Not used when CTEINLINECTRLEN is set. Then either CTEINLINERXMODE1US or CTEINLINERXMODE2US are used. CRC Payload 4us 2us 1us 4us 2us 1us 500ns 250ns 125ns IQ MagPhase 4us 2us 1us 500ns 250ns 125ns 1 0 1 2 3 1 2 3 4 5 6 0 1 1 2 3 4 5 6 0 H RW REPEATPATTERN Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. I RW AGCBACKOFFGAIN Gain will be lowered by the specified number of gain steps NoRepeat Do not repeat (1 time in total) at the start of CTE Note: First LNAGAIN gain drops, then MIXGAIN, then AAFGAIN 6.18.15.81 DFECTRL2 Address offset: 0x914 Start offset for Direction finding 4452_021 v1.3 333 ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B B B B B B B B B B B B A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW TSWITCHOFFSET Signed value offset after the end of the CRC before starting Peripherals switching in number of 16M cycles Note: Decreasing TSWITCHOFFSET beyond the trigger of the AoA/AoD procedure will have no effect effect Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state

- 12 us after switching start Note: Decreasing TSAMPLEOFFSET beyond the trigger of the AoA/AoD procedure will have no B RW TSAMPLEOFFSET 6.18.15.82 SWITCHPATTERN Address offset: 0x928 GPIO patterns to be used for each antenna Maximum 8 GPIOs can be controlled. To secure correct signal levels on the pins, the pins must be configured in the GPIO peripheral as described in Pin configuration. If, during switching, the total number of antenna slots is bigger than the number of written patterns, the RADIO loops back to the pattern used after the reference pattern. A minimum number of 3 patterns must be written. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW SWITCHPATTERN Fill array of GPIO patterns for antenna control The GPIO pattern array size is 40 entries. When written, bit n corresponds to the GPIO configured in PSEL.DFEGPIO[n]. When read, returns the number of GPIO patterns written since the last time the array was cleared. Use CLEARPATTERN to clear the array. 6.18.15.83 CLEARPATTERN Address offset: 0x92C Clear the GPIO pattern array for antenna control 4452_021 v1.3 334 ID ID A ID A B C ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW CLEARPATTERN Clears GPIO pattern array for antenna control Clear 1 Clear the GPIO pattern Peripherals A 6.18.15.84 PSEL.DFEGPIO[n] (n=0..7) Address offset: 0x930 + (n 0x4) Pin select for DFE pin n Must be set before enabling the radio Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

[0..31]

[0..1]

C 1 0 Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 6.18.15.85 DFEPACKET.PTR Address offset: 0x950 Data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW PTR Value ID Value Description Data pointer A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note: See the memory chapter for details about which memories are available for EasyDMA. 6.18.15.86 DFEPACKET.MAXCNT Address offset: 0x954 Maximum number of buffer words to transfer Bit number ID ID A Reset 0x00001000 AccessField RW MAXCNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Maximum number of buffer words to transfer 6.18.15.87 DFEPACKET.AMOUNT Address offset: 0x958 4452_021 v1.3 335 Peripherals Number of samples transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description Number of samples transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000001 AccessField RW POWER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description A Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral Disabled Enabled 0 1 off and then back on again. Peripheral is powered off Peripheral is powered on Reset 0x00000000 AccessField R AMOUNT 6.18.15.88 POWER Address offset: 0xFFC Peripheral power control ID ID A ID ID A 6.18.16 Electrical specification 6.18.16.1 General radio characteristics Symbol fOP fPLL,CH,SP fDELTA,1M fDELTA,BLE,1M fDELTA,2M fDELTA,BLE,2M fskBPS Description Operating frequencies PLL channel spacing Frequency deviation @ 1 Mbps Frequency deviation @ BLE 1 Mbps Frequency deviation @ 2 Mbps Frequency deviation @ BLE 2 Mbps On-the-air data rate fchip, IEEE 802.15.4 Chip rate in IEEE 802.15.4 mode ITX,PLUS8dBM,DCDC TX only run current (DC/DC, 3 V) PRF = +8 dBm ITX,PLUS8dBM TX only run current PRF = +8 dBm ITX,PLUS4dBM,DCDC TX only run current (DC/DC, 3 V) PRF = +4 dBm ITX,PLUS4dBM TX only run current PRF = +4 dBm ITX,0dBM,DCDC TX only run current (DC/DC, 3 V)PRF = 0 dBm ITX,0dBM TX only run current PRF = 0 dBm ITX,MINUS4dBM,DCDC TX only run current DC/DC, 3 V PRF = -4 dBm ITX,MINUS4dBM TX only run current PRF = -4 dBm ITX,MINUS8dBM,DCDC TX only run current DC/DC, 3 V PRF = -8 dBm ITX,MINUS8dBM TX only run current PRF = -8 dBm 4452_021 v1.3 336 Min. 2360 Max. 2500 125 2000 kbps Typ. 1 170 250 320 500 2000 Typ. 14.2 30.4 9.6 20.7 4.9 10.3 3.8 8.0 3.4 7.1 Units MHz MHz kHz kHz kHz kHz kchip/

s mA mA mA mA mA mA mA mA mA mA 6.18.16.2 Radio current consumption (transmitter) Symbol Description Min. Max. Units Symbol Description Min. Typ. Max. Units Peripherals ITX,MINUS12dBM,DCDC TX only run current DC/DC, 3 V PRF = -12 dBm ITX,MINUS12dBM TX only run current PRF = -12 dBm ITX,MINUS16dBM,DCDC TX only run current DC/DC, 3 V PRF = -16 dBm ITX,MINUS16dBM TX only run current PRF = -16 dBm ITX,MINUS20dBM,DCDC TX only run current DC/DC, 3 V PRF = -20 dBm ITX,MINUS20dBM TX only run current PRF = -20 dBm ITX,MINUS40dBM,DCDC TX only run current DC/DC, 3 V PRF = -40 dBm ITX,MINUS40dBM TX only run current PRF = -40 dBm ISTART,TX,DCDC TX start-up current DC/DC, 3 V, PRF = 4 dBm ISTART,TX TX start-up current, PRF = 4 dBm Symbol IRX,1M,DCDC IRX,1M IRX,2M,DCDC IRX,2M RX only run current (DC/DC, 3 V) 1 Mbps/1 Mbps BLE RX only run current (LDO, 3 V) 1 Mbps/1 Mbps BLE RX only run current (DC/DC, 3 V) 2 Mbps/2 Mbps BLE RX only run current (LDO, 3 V) 2 Mbps/2 Mbps BLE ISTART,RX,1M,DCDC RX start-up current (DC/DC, 3 V) 1 Mbps/1 Mbps BLE ISTART,RX,1M RX start-up current 1 Mbps/1 Mbps BLE 6.18.16.4 Transmitter specification PRF PRFC PRFCR PRF1,1 PRF2,1 PRF1,2 PRF2,2 Evm Maximum output power RF power control range RF power accuracy 1st Adjacent Channel Transmit Power 1 MHz (1 Mbps) 2nd Adjacent Channel Transmit Power 2 MHz (1 Mbps) 1st Adjacent Channel Transmit Power 2 MHz (2 Mbps) 2nd Adjacent Channel Transmit Power 4 MHz (2 Mbps) Error vector magnitude IEEE 802.15.4 Pharm2nd, IEEE 802.15.4 2nd harmonics in IEEE 802.15.4 mode Pharm3rd, IEEE 802.15.4 3rd harmonics in IEEE 802.15.4 6.18.16.3 Radio current consumption (Receiver) Description Min. Typ. Max. Units Symbol Description Min. Typ. Max. Units 3.1 6.4 2.9 5.9 2.7 5.5 2.3 4.5 4.3 8.9 4.6 9.6 5.2 10.7 3.4 6.8 8 28

-25

-54

-26

-54 9

-51

-51 4 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA dBm dB dB dBc dBc dBc dBc

%rms dBm dBm 4452_021 v1.3 337 Peripherals 4452_021 v1.3 338

5

7

8

T

1

7

C

5

7

8

T

1

0

7

C

Description Min. Typ. Max. Units 6.18.16.5 Receiver operation Symbol PRX,MAX PSENS,IT,1M PSENS,IT,2M Maximum received signal strength at < 0.1% PER Sensitivity, 1 Mbps nRF mode ideal transmitter17 Sensitivity, 2 Mbps nRF mode ideal transmitter18 PSENS,IT,SP,1M,BLE Sensitivity, 1 Mbps BLE ideal transmitter, packet length 37 PSENS,IT,LP,1M,BLE Sensitivity, 1 Mbps BLE ideal transmitter, packet length 128 PSENS,IT,SP,2M,BLE Sensitivity, 2 Mbps BLE ideal transmitter, packet length 37 bytes BER=1E-319 bytes BER=1E-4 20 bytes PSENS,IT,BLE LE125k Sensitivity, 125 kbps BLE mode PSENS,IT,BLE LE500k Sensitivity, 500 kbps BLE mode PSENS,IEEE 802.15.4 Sensitivity in IEEE 802.15.4 mode Peripherals 0

-93

-89

-96

-94

-92

-103

-98

-100 dBm dBm dBm dBm dBm dBm dBm dBm dBm 6.18.16.6 RX selectivity RX selectivity with equal modulation on interfering signal21 17 Typical sensitivity applies when ADDR0 is used for receiver address correlation. When ADDR[1...7]

are used for receiver address correlation, the typical sensitivity for this mode is degraded by 3 dB. 18 Typical sensitivity applies when ADDR0 is used for receiver address correlation. When ADDR[1..7] are used for receiver address correlation, the typical sensitivity for this mode is degraded by 3 dB. 19 As defined in the 20 Equivalent BER limit < 10E-04 21 Desired signal level at PIN = -67 dBm. One interferer is used, having equal modulation as the desired signal. The input power of the interferer where the sensitivity equals BER = 0.1% is presented 4452_021 v1.3 339

3

7

7

8

T

1

5

3

4

0

9

4

3

4

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Symbol Description Min. Typ. Max. Units Peripherals C/I1M,co-channel 1Mbps mode, Co-Channel interference C/I1M,-1MHz C/I1M,+1MHz C/I1M,-2MHz C/I1M,+2MHz C/I1M,-3MHz C/I1M,+3MHz C/I1M,6MHz 1 Mbps mode, Adjacent (-1 MHz) interference 1 Mbps mode, Adjacent (+1 MHz) interference 1 Mbps mode, Adjacent (-2 MHz) interference 1 Mbps mode, Adjacent (+2 MHz) interference 1 Mbps mode, Adjacent (-3 MHz) interference 1 Mbps mode, Adjacent (+3 MHz) interference 1 Mbps mode, Adjacent (6 MHz) interference C/I1MBLE,co-channel 1 Mbps BLE mode, Co-Channel interference C/I1MBLE,-1MHz C/I1MBLE,+1MHz C/I1MBLE,-2MHz C/I1MBLE,+2MHz C/I1MBLE,>3MHz 1 Mbps BLE mode, Adjacent (-1 MHz) interference 1 Mbps BLE mode, Adjacent (+1 MHz) interference 1 Mbps BLE mode, Adjacent (-2 MHz) interference 1 Mbps BLE mode, Adjacent (+2 MHz) interference 1 Mbps BLE mode, Adjacent (3 MHz) interference C/I1MBLE,image Image frequency interference C/I1MBLE,image,1MHz Adjacent (1 MHz) interference to in-band image frequency C/I2M,co-channel 2 Mbps mode, Co-Channel interference C/I2M,-2MHz C/I2M,+2MHz C/I2M,-4MHz C/I2M,+4MHz C/I2M,-6MHz C/I2M,+6MHz 2 Mbps mode, Adjacent (-2 MHz) interference 2 Mbps mode, Adjacent (+2 MHz) interference 2 Mbps mode, Adjacent (-4 MHz) interference 2 Mbps mode, Adjacent (+4 MHz) interference 2 Mbps mode, Adjacent (-6 MHz) interference 2 Mbps mode, Adjacent (+6 MHz) interference C/I2M,12MHz 2 Mbps mode, Adjacent (12 MHz) interference C/I2MBLE,co-channel 2 Mbps BLE mode, Co-Channel interference C/I2MBLE,-2MHz C/I2MBLE,+2MHz C/I2MBLE,-4MHz C/I2MBLE,+4MHz C/I2MBLE,6MHz 2 Mbps BLE mode, Adjacent (-2 MHz) interference 2 Mbps BLE mode, Adjacent (+2 MHz) interference 2 Mbps BLE mode, Adjacent (-4 MHz) interference 2 Mbps BLE mode, Adjacent (+4 MHz) interference 2 Mbps BLE mode, Adjacent (6 MHz) interference C/I2MBLE,image Image frequency interference C/I2MBLE,image, 2MHz Adjacent (2 MHz) interference to in-band image frequency C/I125k BLE LR,co-

125 kbps BLE LR mode, Co-Channel interference channel C/I125k BLE LR,-1MHz 125 kbps BLE LR mode, Adjacent (-1 MHz) interference C/I125k BLE LR,+1MHz 125 kbps BLE LR mode, Adjacent (+1 MHz) interference C/I125k BLE LR,-2MHz 125 kbps BLE LR mode, Adjacent (-2 MHz) interference C/I125k BLE LR,+2MHz 125 kbps BLE LR mode, Adjacent (+2 MHz) interference C/I125k BLE LR,>3MHz 125 kbps BLE LR mode, Adjacent (3 MHz) interference C/I125k BLE LR,image Image frequency interference C/IIEEE 802.15.4,-5MHz IEEE 802.15.4 mode, Adjacent (-5 MHz) rejection C/IIEEE 802.15.4,+5MHz IEEE 802.15.4 mode, Adjacent (+5 MHz) rejection C/IIEEE 802.15.4,10MHz IEEE 802.15.4 mode, Alternate (10 MHz) rejection 6.18.16.7 RX intermodulation RX intermodulation22 10

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-49 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 22 Desired signal level at PIN = -64 dBm. Two interferers with equal input power are used. The interferer closest in frequency is not modulated, the other interferer is modulated equal with the desired signal. The input power of the interferers where the sensitivity equals BER = 0.1% is presented. 4452_021 v1.3 340 Peripherals Typ.

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-32 dBm dBm dBm dBm s s s s s s s s s s s s s s s 140 40 140 40 6 0 4 0 130 40 21 130 40 0.5 Min. 140 40 140 40 6 0 4 0 130 40 21 130 40 0.5 Symbol Description Min. Max. Units PIMD,5TH,1M IMD performance, 1 Mbps, 5th offset channel, packet length Symbol Description Typ. Max. Units PIMD,5TH,1M,BLE IMD performance, BLE 1 Mbps, 5th offset channel, packet PIMD,5TH,2M IMD performance, 2 Mbps, 5th offset channel, packet length PIMD,5TH,2M,BLE IMD performance, BLE 2 Mbps, 5th offset channel, packet 37 bytes length 37 bytes 37 bytes length 37 bytes 6.18.16.8 Radio timing tTXEN,BLE,1M Time between TXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE and 150 s TIFS) tTXEN,FAST,BLE,1M Time between TXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE with fast ramp-up and 150 s TIFS) tTXDIS,BLE,1M When in TX, delay between DISABLE task and DISABLED event for MODE = Nrf_1Mbit and MODE = Ble_1Mbit tRXEN,BLE,1M Time between the RXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE) tRXEN,FAST,BLE,1M Time between the RXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE with fast ramp-up) tRXDIS,BLE,1M When in RX, delay between DISABLE task and DISABLED event for MODE = Nrf_1Mbit and MODE = Ble_1Mbit tTXDIS,BLE,2M When in TX, delay between DISABLE task and DISABLED event for MODE = Nrf_2Mbit and MODE = Ble_2Mbit tRXDIS,BLE,2M When in RX, delay between DISABLE task and DISABLED event for MODE = Nrf_2Mbit and MODE = Ble_2Mbit tTXEN,IEEE 802.15.4 Time between TXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4) tTXEN,FAST,IEEE 802.15.4 Time between TXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4 with fast ramp-up) tTXDIS,IEEE 802.15.4 When in TX, delay between DISABLE task and DISABLED event (IEEE 802.15.4) tRXEN,IEEE 802.15.4 Time between the RXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4) tRXEN,FAST,IEEE 802.15.4 Time between the RXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4 with fast ramp-up) tRXDIS,IEEE 802.15.4 When in RX, delay between DISABLE task and DISABLED event (IEEE 802.15.4) 802.15.4 mode 4452_021 v1.3 341 tRX-to-TX turnaround Maximum TX-to-RX or RX-to-TX turnaround time in IEEE 40 Peripherals Min. Typ. Max. Units dB dB s s s s 2 1 0.25 15 Typ. 0.25 0.25 5

-93 6.18.16.9 Received signal strength indicator (RSSI) specifications Description RSSI accuracy 23 RSSIRESOLUTION RSSI resolution Symbol RSSIACC RSSIPERIOD RSSISETTLE 6.18.16.10 Jitter RSSI sampling time from RSSI_START task RSSI settling time after signal level change Symbol Description Min. Max. Units tDISABLEDJITTER Jitter on DISABLED event relative to END event when shortcut between END and DISABLE is enabled tREADYJITTER Jitter on READY event relative to TXEN and RXEN task 6.18.16.11 IEEE 802.15.4 energy detection constants Symbol Description Min. Typ. Max. Units ED_RSSISCALE Scaling value when converting between hardware-reported ED_RSSIOFFS Offset value when converting between hardware-reported value and dBm value and dBm 6.19 RNG Random number generator The Random number generator (RNG) generates true non-deterministic random numbers based on internal thermal noise that are suitable for cryptographic purposes. The RNG does not require a seed value. The RNG is started by triggering the START task and stopped by triggering the STOP task. When started, new random numbers are generated continuously and written to the VALUE register when ready. A VALRDY event is generated for every new random number that is written to the VALUE register. This means that after a VALRDY event is generated, the CPU has the time until the next VALRDY event to read out the random number from the VALUE register before it is overwritten by a new random number. 6.19.1 Bias correction A bias correction algorithm is employed on the internal bit stream to remove any bias toward bits are then queued into an eight-bit register for parallel readout from the VALUE register. or

. The It is possible to enable bias correction in the CONFIG register. This will result in slower value generation, but will ensure a statistically uniform distribution of the random values. 23 Valid range -90 to -30 dBm 4452_021 v1.3 342

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Peripherals 6.19.2 Speed The time needed to generate one random byte of data is unpredictable, and may vary from one byte to the next. This is especially true when bias correction is enabled. 6.19.3 Registers Base address Peripheral Instance Description Configuration 0x4000D000 RNG RNG Random number generator Description Task starting the random number generator Task stopping the random number generator Event being generated for every new random number written to the VALUE register Shortcuts between local events and tasks Register TASKS_START TASKS_STOP EVENTS_VALRDY SHORTS INTENSET INTENCLR CONFIG VALUE Offset 0x000 0x004 0x100 0x200 0x304 0x308 0x504 0x508 Enable interrupt Disable interrupt Configuration register Output random number 6.19.3.1 TASKS_START Address offset: 0x000 Task starting the random number generator ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_START Task starting the random number generator Trigger 1 Trigger task 6.19.3.2 TASKS_STOP Address offset: 0x004 Task stopping the random number generator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Task stopping the random number generator Trigger 1 Trigger task 6.19.3.3 EVENTS_VALRDY Address offset: 0x100 Event being generated for every new random number written to the VALUE register 4452_021 v1.3 343 A A

Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_VALRDY Event being generated for every new random number NotGenerated Generated written to the VALUE register Event not generated Event generated 6.19.3.4 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW VALRDY_STOP Shortcut between event VALRDY and task STOP Disabled Enabled Disable shortcut Enable shortcut ID ID A ID ID A 6.19.3.5 INTENSET Address offset: 0x304 Enable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW VALRDY 6.19.3.6 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW VALRDY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event VALRDY Set Disabled Enabled Enable Read: Disabled Read: Enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event VALRDY Clear Disabled Enabled Disable Read: Disabled Read: Enabled A A A A 0 1 0 1 1 0 1 1 0 1 4452_021 v1.3 344 Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Disabled Enabled 0 1 Description Bias correction Disabled Enabled 6.19.3.7 CONFIG Address offset: 0x504 Configuration register Bit number ID ID A Reset 0x00000000 AccessField RW DERCEN 6.19.3.8 VALUE Address offset: 0x508 Output random number Bit number ID ID A Reset 0x00000000 AccessField R VALUE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Description Value

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Generated random number 6.19.4 Electrical specification 6.19.4.1 RNG Electrical Specification Symbol tRNG,START Description Time from setting the START task to generation begins. This is a one-time delay on START signal and does not apply between samples. tRNG,RAW Run time per byte without bias correction. Uniform distribution of 0 and 1 is not guaranteed. tRNG,BC Run time per byte with bias correction. Uniform distribution of 0 and 1 is guaranteed. Time to generate a byte cannot be guaranteed. Min. Max. Units Typ. 128 30 120 s s s 6.20 RTC Real-time counter The Real-time counter (RTC) module provides a generic, low power timer on the low-frequency clock source (LFCLK). 4452_021 v1.3 345 Peripherals The RTC module features a 24-bit COUNTER, a 12-bit (1/X) prescaler, capture/compare registers, and a tick event generator for low power, tickless RTOS implementation. 6.20.1 Clock source The RTC will run off the LFCLK. The COUNTER resolution will therefore be 30.517 s. Depending on the source, the RTC is able to run while the HFCLK is OFF and PCLK16M is not available. The software has to explicitely start LFCLK before using the RTC. See CLOCK Clock control on page 80 for more information about clock sources. 6.20.2 Resolution versus overflow and the PRESCALER Counter increment frequency:

The PRESCALER register is read/write when the RTC is stopped. The PRESCALER register is read-only once the RTC is STARTed. Writing to the PRESCALER register when the RTC is started has no effect. The PRESCALER is restarted on START, CLEAR and TRIGOVRFLW, that is, the prescaler value is latched to an internal register (<<PRESC>>) on these tasks. Examples:

1. Desired COUNTER frequency 100 Hz (10 ms counter period) PRESCALER = round(32.768 kHz / 100 Hz) - 1 = 327 fRTC = 99.9 Hz 10009.576 s counter period 2. Desired COUNTER frequency 8 Hz (125 ms counter period) PRESCALER = round(32.768 kHz / 8 Hz) 1 = 4095 fRTC = 8 Hz 4452_021 v1.3 346

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Peripherals 125 ms counter period Prescaler 0 28-1 212-1 Counter resolution 30.517 s 7812.5 s 125 ms Overflow 512 seconds 131072 seconds 582.542 hours 6.20.3 COUNTER register The COUNTER increments on LFCLK when the internal PRESCALER register (<<PRESC>>) is 0x00.

<<PRESC>> is reloaded from the PRESCALER register. If enabled, the TICK event occurs on each increment of the COUNTER. The TICK event is disabled by default. 6.20.4 Overflow features The TRIGOVRFLW task sets the COUNTER value to 0xFFFFF0 to allow SW test of the overflow condition. OVRFLW occurs when COUNTER overflows from 0xFFFFFF to 0. Important: The OVRFLW event is disabled by default. 6.20.5 TICK event The TICK event enables low power "tick-less" RTOS implementation as it optionally provides a regular interrupt source for a RTOS without the need to use the ARM SysTick feature. Using the RTC TICK event rather than the SysTick allows the CPU to be powered down while still keeping RTOS scheduling active. 4452_021 v1.3 347

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Peripherals Important: The TICK event is disabled by default. 6.20.6 Event control feature To optimize RTC power consumption, events in the RTC can be individually disabled to prevent PCLK16M and HFCLK being requested when those events are triggered. This is managed using the EVTEN register. For example, if the TICK event is not required for an application, this event should be disabled as it is frequently occurring and may increase power consumption if HFCLK otherwise could be powered down for long durations. This means that the RTC implements a slightly different task and event system compared to the standard system described in Peripheral interface on page 96. The RTC task and event system is illustrated in Tasks, events and interrupts in the RTC on page 348. 6.20.7 Compare feature There are a number of Compare registers. For more information, see Registers on page 353. When setting a compare register, the following behavior of the RTC compare event should be noted:

If a CC register value is 0 when a CLEAR task is set, this will not trigger a COMPARE event. 4452_021 v1.3 348

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4 Peripherals If a CC register is N and the COUNTER value is N when the START task is set, this will not trigger a COMPARE event. COMPARE occurs when a CC register is N and the COUNTER value transitions from N-1 to N. If the COUNTER is N, writing N+2 to a CC register is guaranteed to trigger a COMPARE event at N+2. 4452_021 v1.3 349

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Peripherals If the COUNTER is N, writing N or N+1 to a CC register may not trigger a COMPARE event. If the COUNTER is N and the current CC register value is N+1 or N+2 when a new CC value is written, a match may trigger on the previous CC value before the new value takes effect. If the current CC value greater than N+2 when the new value is written, there will be no event due to the old value. 6.20.8 TASK and EVENT jitter/delay Jitter or delay in the RTC is due to the peripheral clock being a low frequency clock (LFCLK) which is not synchronous to the faster PCLK16M. Registers in the peripheral interface, part of the PCLK16M domain, have a set of mirrored registers in the LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain and is latched on read from an internal register called COUNTER in the LFCLK domain. COUNTER is the register which is actually modified each time the RTC ticks. These registers must be synchronised between clock domains (PCLK16M and LFCLK). 4452_021 v1.3 350

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The following is a summary of the jitter introduced on tasks and events. Figures illustrating jitter follow. Peripherals Task CLEAR, STOP, START, TRIGOVRFLOW Operation/Function START to COUNTER increment COMPARE to COMPARE 24 Delay Jitter

+15 to 46 s

+/- 15 s

+/- 62.5 ns 1. CLEAR and STOP (and TRIGOVRFLW; not shown) will be delayed as long as it takes for the peripheral to clock a falling edge and rising of the LFCLK. This is between 15.2585 s and 45.7755 s rounded to 15 s and 46 s for the remainder of the section. 2. The START task will start the RTC. Assuming that the LFCLK was previously running and stable, the first increment of COUNTER (and instance of TICK event) will be typically after 30.5 s +/-15 s. In some cases, in particular if the RTC is STARTed before the LFCLK is running, that timing can be up to

~250 s. The software should therefore wait for the first TICK if it has to make sure the RTC is running. 24 Assumes RTC runs continuously between these events. Note: 32.768 kHz clock jitter is additional to the numbers provided above. 4452_021 v1.3 351

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Sending a TRIGOVRFLW task sets the COUNTER to a value close to overflow. However, since the update of COUNTER relies on a stable LFCLK, sending this task while LFCLK is not running will start LFCLK, but the update will then be delayed by the same amount of time of up to ~250 us. The figures show the smallest and largest delays to on the START task which appears as a +/-15 s jitter on the first COUNTER increment. Peripherals 6.20.9 Reading the COUNTER register To read the COUNTER register, the internal <<COUNTER>> value is sampled. To ensure that the <<COUNTER>> is safely sampled (considering an LFCLK transition may occur during a read), the CPU and core memory bus are halted for three cycles by lowering the core PREADY signal. The Read takes the CPU 2 cycles in addition resulting in the COUNTER register read taking a fixed five PCLK16M clock cycles. 4452_021 v1.3 352

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Peripherals 6.20.10 Registers Base address Peripheral Instance Description Configuration 0x4000B000 RTC Real-time counter 0 CC[0..2] implemented, CC[3] not 0x40011000 0x40024000 RTC RTC Real-time counter 1 Real-time counter 2 implemented CC[0..3] implemented CC[0..3] implemented RTC0 RTC1 RTC2 Register TASKS_START TASKS_STOP TASKS_CLEAR TASKS_TRIGOVRFLW EVENTS_TICK EVENTS_OVRFLW EVENTS_COMPARE[0]

EVENTS_COMPARE[1]

EVENTS_COMPARE[2]

EVENTS_COMPARE[3]

INTENSET INTENCLR EVTEN EVTENSET EVTENCLR COUNTER PRESCALER CC[0]

CC[1]

CC[2]

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Offset Description 0x000 0x004 0x008 0x00C 0x100 0x104 0x140 0x144 0x148 0x14C 0x304 0x308 0x340 0x344 0x348 0x504 0x508 0x540 0x544 0x548 0x54C Start RTC COUNTER Stop RTC COUNTER Clear RTC COUNTER Set COUNTER to 0xFFFFF0 Event on COUNTER increment Event on COUNTER overflow Compare event on CC[0] match Compare event on CC[1] match Compare event on CC[2] match Compare event on CC[3] match Enable interrupt Disable interrupt Enable or disable event routing Enable event routing Disable event routing Current COUNTER value stopped Compare register 0 Compare register 1 Compare register 2 Compare register 3 6.20.10.1 TASKS_START Address offset: 0x000 Start RTC COUNTER 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_START Start RTC COUNTER Trigger 1 Trigger task ID ID A 6.20.10.2 TASKS_STOP Address offset: 0x004 Stop RTC COUNTER 4452_021 v1.3 353

ID ID A ID ID A ID ID A ID ID A Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Stop RTC COUNTER Trigger 1 Trigger task 6.20.10.3 TASKS_CLEAR Address offset: 0x008 Clear RTC COUNTER Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_CLEAR Clear RTC COUNTER Trigger 1 Trigger task 6.20.10.4 TASKS_TRIGOVRFLW Address offset: 0x00C Set COUNTER to 0xFFFFF0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_TRIGOVRFLW Set COUNTER to 0xFFFFF0 Trigger 1 Trigger task 6.20.10.5 EVENTS_TICK Address offset: 0x100 Event on COUNTER increment 6.20.10.6 EVENTS_OVRFLW Address offset: 0x104 Event on COUNTER overflow Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_TICK NotGenerated Generated 0 1 Event on COUNTER increment Event not generated Event generated A A A A 4452_021 v1.3 354 ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_OVRFLW NotGenerated Generated Event on COUNTER overflow Event not generated Event generated 6.20.10.7 EVENTS_COMPARE[n] (n=0..3) Address offset: 0x140 + (n 0x4) Compare event on CC[n] match Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_COMPARE Compare event on CC[n] match NotGenerated Generated Event not generated Event generated Peripherals A A 6.20.10.8 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW TICK Value ID Value Description Write '1' to enable interrupt for event TICK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F E D C B A B RW OVRFLW Write '1' to enable interrupt for event OVRFLW C-F RW COMPARE[i] (i=0..3) Write '1' to enable interrupt for event COMPARE[i]

Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled 0 1 0 1 1 0 1 1 0 1 1 0 1 6.20.10.9 INTENCLR Address offset: 0x308 Disable interrupt 4452_021 v1.3 355 Bit number ID ID A Reset 0x00000000 AccessField RW TICK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event TICK Peripherals B RW OVRFLW Write '1' to disable interrupt for event OVRFLW C-F RW COMPARE[i] (i=0..3) Write '1' to disable interrupt for event COMPARE[i]

Bit number ID ID A Reset 0x00000000 AccessField RW TICK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable event routing for event TICK B RW OVRFLW Enable or disable event routing for event OVRFLW C-F RW COMPARE[i] (i=0..3) Enable or disable event routing for event COMPARE[i]

6.20.10.10 EVTEN Address offset: 0x340 Enable or disable event routing 6.20.10.11 EVTENSET Address offset: 0x344 Enable event routing Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Set Disabled Enabled Set 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Disable Disable Disable Disable Disable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Bit number ID ID A Reset 0x00000000 AccessField RW TICK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable event routing for event TICK B RW OVRFLW Write '1' to enable event routing for event OVRFLW 4452_021 v1.3 356 Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C-F RW COMPARE[i] (i=0..3) Write '1' to enable event routing for event COMPARE[i]

Value ID Value Description Disabled Enabled Set Read: Disabled Read: Enabled Enable Bit number ID Reset 0x00000000 ID AccessField 6.20.10.12 EVTENCLR Address offset: 0x348 Disable event routing Bit number ID ID A Reset 0x00000000 AccessField RW TICK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable event routing for event TICK B RW OVRFLW Write '1' to disable event routing for event OVRFLW C-F RW COMPARE[i] (i=0..3) Write '1' to disable event routing for event COMPARE[i]

Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable 0 1 1 0 1 1 0 1 1 0 1 1 6.20.10.13 COUNTER Address offset: 0x504 Current COUNTER value 6.20.10.14 PRESCALER Address offset: 0x508 ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R COUNTER Value ID Value Description Counter value A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value RW PRESCALER Description Prescaler value 4452_021 v1.3 357 Peripherals 6.20.10.15 CC[n] (n=0..3) Address offset: 0x540 + (n 0x4) Compare register n Bit number ID ID A Reset 0x00000000 AccessField RW COMPARE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Compare value 6.20.11 Electrical specification 6.21 SAADC Successive approximation analog-to-

digital converter The SAADC is a differential successive approximation register (SAR) analog-to-digital converter. It supports up to eight external analog input channels, depending on package variant. The following lists the main features of the SAADC:

Multiple input channels Each channel can use pins AIN0 through AIN7, the VDD pin, or the VDDH pin as input Eight channels for single-ended inputs and four channels for differential inputs Full scale input range Individual reference selection for each channel VDD Internal reference Continuous sampling Output samples are automatically written to RAM using EasyDMA Samples are stored as 16-bit 2's complement values 8/10/12-bit resolution, 14-bit resolution with oversampling 4452_021 v1.3 358 PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A CH[X].PSELP PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A CH[X].CONFIG Peripherals NC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDD VDDHDIV5 NC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDD VDDHDIV5 MUX MUX CH[X].PSELN PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A RESP RESN GAIN VDD Internal reference REFSEL An input channel is enabled and connected to an analog input pin using the registers CH[n].PSELP (n=0..7) on page 375 and CH[n].PSELN (n=0..7) on page 375. Before any sampling can take place, the length and the location of the memory buffer in RAM where output values shall be written need to be configured, and the START task has to be triggered to apply the configuration. See EasyDMA on page 361 for details on memory configuration and how the results are placed in memory. Sampling of all enabled channels is started by triggering the SAMPLE task, and the sample results are automatically written to memory using EasyDMA. When multiple channels are enabled, they are sampled successively in a sequence starting with the lowest channel number. The time it takes to sample all enabled channels is given as follows:

A DONE event is generated for every single completed conversion, and an END event is generated when multiple samples, as specified in RESULT.MAXCNT on page 378, have been written to memory. 6.21.1 Input configuration Each SAADC channel can be configured to use either single-ended or differential input mode. The configuration is done using the registers CH[n].CONFIG (n=0..7) on page 376. In single-ended mode, the negative channel input is shorted to ground internally and the setting in the corresponding register CH[n].PSELN (n=0..7) on page 375 will not apply. The assumption in single-ended mode is that the internal ground of the SAADC is the same as the external ground that the measured voltage is referred to. The SAADC is thus sensitive to ground bounce on the PCB in single-ended mode. If this is a concern, using differential measurement is recommended. In differential mode, both positive and negative input has to be configured in registersCH[n].PSELP (n=0..7) on page 375 and CH[n].PSELN (n=0..7) on page 375 respectively. 6.21.1.1 Acquisition time To sample input voltage, the SAADC connects a capacitor to the input. This is illustrated in the following figure:

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Peripherals The acquisition time indicates how long the capacitor is connected, see TACQ field in CH[n].CONFIG register. The required acquisition time depends on the source resistance (Rsource). For high source resistance the acquisition time should be increased:

TACQ [s]

Maximum source resistance [k]

3 5 10 15 20 40 10 40 100 200 400 800 When using as input, the acquisition time needs to be 10 s or higher. 6.21.1.2 Internal resistor string (resistor ladder) The SAADC has an internal resistor string for positive and negative input. The resistors are controlled in registers CH[n].CONFIG.RESP and CH[n].CONFIG.RESN. The following figure illustrates the resistor ladder for positive (and negative) input:

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Peripherals 6.21.2 Reference voltage and gain settings Each SAADC channel can have individual reference and gain settings. This is configured in registers CH[n].CONFIG (n=0..7) on page 376. Available configuration options are:

VDD/4 or internal 0.6 V reference Gain ranging from 1/6 to 4 The gain setting can be used to control the effective input range of the SAADC:

For example, selecting VDD as reference, single-ended input (grounded negative input), and a gain of 1/4 will result in the following input range:

With internal reference, single-ended input (grounded negative input) and a gain of 1/6, the input range will be:

Inputs AIN0 through AIN7 cannot exceed VDD or be lower than VSS. 6.21.3 Digital output The digital output value from the SAADC is calculated using a formula. where V(P) V(N) GAIN REFERENCE RESOLUTION m is the voltage at input P is the voltage at input N is the selected gain is the selected reference voltage is 0 for single-ended channels is 1 for differential channels is output resolution in bits, as configured in register RESOLUTION on page 377 Results are sign extended to 16 bits and stored as little-endian byte order in RAM. 6.21.4 EasyDMA The SAADC resources are started by triggering the START task. The SAADC is using EasyDMA to store results in a result buffer in RAM. 4452_021 v1.3 361

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I Peripherals Registers RESULT.PTR on page 378 and RESULT.MAXCNT on page 378 must be configured before SAADC is started. The result buffer is located at the address specified in register RESULT.PTR on page 378. This register is double-buffered, and it can be updated and prepared for the next START task immediately after the STARTED event is generated. The size of the result buffer is specified in register RESULT.MAXCNT on page 378, and the SAADC will generate an END event when it has filled up the result buffer, as illustrated in the following figure:

The following figure shows how results are placed in RAM when multiple channels are enabled, and value in RESULT.MAXCNT on page 378 is an even number:

The following figure shows how results are placed in RAM when multiple channels are enabled and value in RESULT.MAXCNT on page 378 is an odd number:

31 16 15 0 RESULT.PTR CH[2] 1st result CH[1] 1st result RESULT.PTR + 4 CH[1] 2nd result CH[5] 1st result RESULT.PTR + 8 CH[5] 2nd result CH[2] 2nd result RESULT.PTR + 2*RESULT.MAXCNT 4 CH[5] last result CH[2] last result 31 16 15 0 RESULT.PTR CH[2] 1st result CH[1] 1st result RESULT.PTR + 4 CH[1] 2nd result CH[5] 1st result RESULT.PTR + 8 CH[5] 2nd result CH[2] 2nd result RESULT.PTR + 2*RESULT.MAXCNT 2 CH[5] last result

() The last 32-bit word is populated only with one 16-bit result. In both examples, channels 1, 2 and 5 are enabled, and all others are disabled. See Memory on page 19 for more information about the different memory regions. 4452_021 v1.3 362

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Peripherals EasyDMA is finished with accessing RAM when events END or STOPPED are generated. The register RESULT.AMOUNT on page 379 can then be read, to see how many results have been transferred to the result buffer in RAM since the START task was triggered. 6.21.5 Continuous sampling When using continuous sampling, new samples are automatically taken at a fixed sample rate. Continuous sampling of both single and multiple channels can be implemented using a general purpose timer connecting a timer event to SAADC's SAMPLE task via PPI. Alternatively, continuous sampling can be implemented by using the internal timer in the SAADC by setting the MODE field in register SAMPLERATE on page 378 to

. The sample rate (frequency at which the SAMPLE task is triggered) is configured in the same register. The internal timer and the continuous sampling are started by triggering the START task and stopped using the STOP task. Note: Note that the internal timer can only be used when a single input channel is enabled. For continuous sampling, ensure that the sample rate fullfills the following criteria:

SAMPLE ACQ conv 6.21.6 Oversampling An accumulator in the SAADC can be used to find the average of several analog input samples. In general, oversampling improves the signal-to-noise ratio (SNR). Oversampling does not improve the integral non-

linearity (INL) or differential non-linearity (DNL). The accumulator is controlled in the OVERSAMPLE register. When using oversampling, 2OVERSAMPLE input samples are averaged before the sample result is transferred to memory. Hence, the SAMPLE task must be triggered 2OVERSAMPLE times for each output value. The following events are relevant:

DONE event is generated for every input sample taken RESULTDONE event is generated for every averaged value ready to be transferred into RAM END event is generated when averaged values defined in RESULT.MAXCNT on page 378 have been written to memory. END event is generated every 2OVERSAMPLE time the DONE event is generated. If value in OVERSAMPLE is set to 0, the DONE and RESULTDONE events will be generated at the same rate. Note: Oversampling should only be used when a single input channel is enabled, as averaging is performed over all enabled channels. 6.21.7 Event monitoring using limits A channel can be event monitored by using limits. Limits are configured in CH[n].LIMIT register, with high limit and low limit. Note: High limit shall always be higher than or equal to low limit. Appropriate events are generated whenever the conversion results (sampled input signals) are outside of the two defined limits. It is not possible to generate an event when the input signal is inside a defined range by swapping high and low limits. An example of event montitoring using limits is illustrated in the following figure:

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Peripherals The comparison to limits always takes place, it does not need to be specifically enabled. If comparison is not required on a channel, the software ignores the related events. In that situation, the value of the limits defined in register is irrelevant, i.e. it does not matter if the low limit is lower than the high limit or not. 6.21.8 Calibration The SAADC has a temperature dependent offset. Therefore, it is recommended to calibrate the SAADC at least once before use, and to re-run calibration every time the ambient temperature has changed by more than 10 C. Offset calibration is started by triggering the CALIBRATEOFFSET task, and the CALIBRATEDONE event is generated when calibration is done. 6.21.9 Registers Base address Peripheral Description Configuration 0x40007000 SAADC Analog to digital converter Instance SAADC Register TASKS_START TASKS_SAMPLE TASKS_STOP EVENTS_STARTED EVENTS_END EVENTS_DONE Offset 0x000 0x004 0x008 0x00C 0x100 0x104 0x108 Description Starts the SAADC and prepares the result buffer in RAM Takes one SAADC sample Stops the SAADC and terminates all on-going conversions The SAADC has started The SAADC has filled up the result buffer TASKS_CALIBRATEOFFSET Starts offset auto-calibration EVENTS_RESULTDONE 0x10C Result ready for transfer to RAM A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. 4452_021 v1.3 364

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Peripherals Register Offset Description EVENTS_CALIBRATEDONE Calibration is complete The SAADC has stopped EVENTS_STOPPED EVENTS_CH[0].LIMITH EVENTS_CH[0].LIMITL EVENTS_CH[1].LIMITH EVENTS_CH[1].LIMITL EVENTS_CH[2].LIMITH EVENTS_CH[2].LIMITL EVENTS_CH[3].LIMITH EVENTS_CH[3].LIMITL EVENTS_CH[4].LIMITH EVENTS_CH[4].LIMITL EVENTS_CH[5].LIMITH EVENTS_CH[5].LIMITL EVENTS_CH[6].LIMITH EVENTS_CH[6].LIMITL EVENTS_CH[7].LIMITH EVENTS_CH[7].LIMITL INTEN INTENSET INTENCLR STATUS ENABLE CH[0].PSELP CH[0].PSELN CH[0].CONFIG CH[0].LIMIT CH[1].PSELP CH[1].PSELN CH[1].CONFIG CH[1].LIMIT CH[2].PSELP CH[2].PSELN CH[2].CONFIG CH[2].LIMIT CH[3].PSELP CH[3].PSELN CH[3].CONFIG CH[3].LIMIT CH[4].PSELP CH[4].PSELN CH[4].CONFIG CH[4].LIMIT CH[5].PSELP CH[5].PSELN CH[5].CONFIG CH[5].LIMIT CH[6].PSELP CH[6].PSELN CH[6].CONFIG CH[6].LIMIT CH[7].PSELP CH[7].PSELN 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C 0x140 0x144 0x148 0x14C 0x150 0x154 0x300 0x304 0x308 0x400 0x500 0x510 0x514 0x518 0x51C 0x520 0x524 0x528 0x52C 0x530 0x534 0x538 0x53C 0x540 0x544 0x548 0x54C 0x550 0x554 0x558 0x55C 0x560 0x564 0x568 0x56C 0x570 0x574 0x578 0x57C 0x580 0x584 Last result is equal or above CH[0].LIMIT.HIGH Last result is equal or below CH[0].LIMIT.LOW Last result is equal or above CH[1].LIMIT.HIGH Last result is equal or below CH[1].LIMIT.LOW Last result is equal or above CH[2].LIMIT.HIGH Last result is equal or below CH[2].LIMIT.LOW Last result is equal or above CH[3].LIMIT.HIGH Last result is equal or below CH[3].LIMIT.LOW Last result is equal or above CH[4].LIMIT.HIGH Last result is equal or below CH[4].LIMIT.LOW Last result is equal or above CH[5].LIMIT.HIGH Last result is equal or below CH[5].LIMIT.LOW Last result is equal or above CH[6].LIMIT.HIGH Last result is equal or below CH[6].LIMIT.LOW Last result is equal or above CH[7].LIMIT.HIGH Last result is equal or below CH[7].LIMIT.LOW Enable or disable interrupt Enable interrupt Disable interrupt Status Enable or disable SAADC Input positive pin selection for CH[0]

Input negative pin selection for CH[0]

Input configuration for CH[0]

High/low limits for event monitoring of a channel Input positive pin selection for CH[1]

Input negative pin selection for CH[1]

Input configuration for CH[1]

High/low limits for event monitoring of a channel Input positive pin selection for CH[2]

Input negative pin selection for CH[2]

Input configuration for CH[2]

High/low limits for event monitoring of a channel Input positive pin selection for CH[3]

Input negative pin selection for CH[3]

Input configuration for CH[3]

High/low limits for event monitoring of a channel Input positive pin selection for CH[4]

Input negative pin selection for CH[4]

Input configuration for CH[4]

High/low limits for event monitoring of a channel Input positive pin selection for CH[5]

Input negative pin selection for CH[5]

Input configuration for CH[5]

High/low limits for event monitoring of a channel Input positive pin selection for CH[6]

Input negative pin selection for CH[6]

Input configuration for CH[6]

High/low limits for event monitoring of a channel Input positive pin selection for CH[7]

Input negative pin selection for CH[7]

4452_021 v1.3 365 Peripherals Register CH[7].CONFIG CH[7].LIMIT RESOLUTION OVERSAMPLE SAMPLERATE RESULT.PTR RESULT.MAXCNT RESULT.AMOUNT Offset 0x588 0x58C 0x5F0 0x5F4 0x5F8 0x62C 0x630 0x634 Description Input configuration for CH[7]

High/low limits for event monitoring of a channel Resolution configuration OVERSAMPLE a higher RESOLUTION should be used. Controls normal or continuous sample rate Data pointer Maximum number of 16-bit samples to be written to output RAM buffer Number of 16-bit samples written to output RAM buffer since the previous START task Oversampling configuration. The RESOLUTION is applied before averaging, thus for high 6.21.9.1 TASKS_START Address offset: 0x000 Starts the SAADC and prepares the result buffer in RAM Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_START Starts the SAADC and prepares the result buffer in RAM Trigger 1 Trigger task 6.21.9.2 TASKS_SAMPLE Address offset: 0x004 Takes one SAADC sample Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_SAMPLE Takes one SAADC sample Trigger 1 Trigger task 6.21.9.3 TASKS_STOP Address offset: 0x008 Stops the SAADC and terminates all on-going conversions Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Stops the SAADC and terminates all on-going conversions Trigger 1 Trigger task ID ID A ID ID A ID ID A A A A 6.21.9.4 TASKS_CALIBRATEOFFSET Address offset: 0x00C 4452_021 v1.3 366

ID ID A ID ID A ID ID A ID ID A Peripherals Starts offset auto-calibration Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_CALIBRATEOFFSET Starts offset auto-calibration Trigger 1 Trigger task 6.21.9.5 EVENTS_STARTED Address offset: 0x100 The SAADC has started 0 1 0 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_STARTED NotGenerated Generated The SAADC has started Event not generated Event generated 6.21.9.6 EVENTS_END Address offset: 0x104 The SAADC has filled up the result buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_END The SAADC has filled up the result buffer NotGenerated Generated Event not generated Event generated 6.21.9.7 EVENTS_DONE Address offset: 0x108 A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_DONE A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a NotGenerated Generated 0 1 result to be transferred to RAM. Event not generated Event generated 4452_021 v1.3 367 A A A A Peripherals A A A 6.21.9.8 EVENTS_RESULTDONE Address offset: 0x10C Result ready for transfer to RAM ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RESULTDONE Result ready for transfer to RAM NotGenerated Generated Event not generated Event generated 6.21.9.9 EVENTS_CALIBRATEDONE Address offset: 0x110 Calibration is complete Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CALIBRATEDONE NotGenerated Generated Calibration is complete Event not generated Event generated 6.21.9.10 EVENTS_STOPPED Address offset: 0x114 The SAADC has stopped Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_STOPPED NotGenerated Generated The SAADC has stopped Event not generated Event generated 6.21.9.11 EVENTS_CH[n].LIMITH (n=0..7) Address offset: 0x118 + (n 0x8) Last result is equal or above CH[n].LIMIT.HIGH 0 1 0 1 0 1 4452_021 v1.3 368 Peripherals A A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Last result is equal or above CH[n].LIMIT.HIGH NotGenerated Generated Event not generated Event generated 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Last result is equal or below CH[n].LIMIT.LOW NotGenerated Generated Event not generated Event generated 6.21.9.12 EVENTS_CH[n].LIMITL (n=0..7) Address offset: 0x11C + (n 0x8) Last result is equal or below CH[n].LIMIT.LOW Bit number ID ID A Reset 0x00000000 AccessField RW LIMITH Bit number ID ID A Reset 0x00000000 AccessField RW LIMITL 6.21.9.13 INTEN Address offset: 0x300 Enable or disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW STARTED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event STARTED B RW END Enable or disable interrupt for event END C RW DONE Enable or disable interrupt for event DONE D RW RESULTDONE Enable or disable interrupt for event RESULTDONE E RW CALIBRATEDONE Enable or disable interrupt for event CALIBRATEDONE F RW STOPPED Enable or disable interrupt for event STOPPED G RW CH0LIMITH Enable or disable interrupt for event CH0LIMITH H RW CH0LIMITL Enable or disable interrupt for event CH0LIMITL Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable 4452_021 v1.3 369 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Enable Bit number ID Reset 0x00000000 ID AccessField I J RW CH1LIMITH Enable or disable interrupt for event CH1LIMITH RW CH1LIMITL Enable or disable interrupt for event CH1LIMITL K RW CH2LIMITH Enable or disable interrupt for event CH2LIMITH L RW CH2LIMITL Enable or disable interrupt for event CH2LIMITL M RW CH3LIMITH Enable or disable interrupt for event CH3LIMITH N RW CH3LIMITL Enable or disable interrupt for event CH3LIMITL O RW CH4LIMITH Enable or disable interrupt for event CH4LIMITH P RW CH4LIMITL Enable or disable interrupt for event CH4LIMITL Q RW CH5LIMITH Enable or disable interrupt for event CH5LIMITH R RW CH5LIMITL Enable or disable interrupt for event CH5LIMITL S RW CH6LIMITH Enable or disable interrupt for event CH6LIMITH T RW CH6LIMITL Enable or disable interrupt for event CH6LIMITL U RW CH7LIMITH Enable or disable interrupt for event CH7LIMITH V RW CH7LIMITL Enable or disable interrupt for event CH7LIMITL Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Value ID Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6.21.9.14 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.3 370 Bit number ID ID A Reset 0x00000000 AccessField RW STARTED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event STARTED Peripherals Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set B RW END Write '1' to enable interrupt for event END C RW DONE Write '1' to enable interrupt for event DONE D RW RESULTDONE Write '1' to enable interrupt for event RESULTDONE E RW CALIBRATEDONE Write '1' to enable interrupt for event CALIBRATEDONE F RW STOPPED Write '1' to enable interrupt for event STOPPED G RW CH0LIMITH Write '1' to enable interrupt for event CH0LIMITH H RW CH0LIMITL Write '1' to enable interrupt for event CH0LIMITL I J RW CH1LIMITH Write '1' to enable interrupt for event CH1LIMITH RW CH1LIMITL Write '1' to enable interrupt for event CH1LIMITL K RW CH2LIMITH Write '1' to enable interrupt for event CH2LIMITH L RW CH2LIMITL Write '1' to enable interrupt for event CH2LIMITL M RW CH3LIMITH Write '1' to enable interrupt for event CH3LIMITH 4452_021 v1.3 371 Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 Peripherals Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value N RW CH3LIMITL Write '1' to enable interrupt for event CH3LIMITL Value ID Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 O RW CH4LIMITH Write '1' to enable interrupt for event CH4LIMITH P RW CH4LIMITL Write '1' to enable interrupt for event CH4LIMITL Q RW CH5LIMITH Write '1' to enable interrupt for event CH5LIMITH R RW CH5LIMITL Write '1' to enable interrupt for event CH5LIMITL S RW CH6LIMITH Write '1' to enable interrupt for event CH6LIMITH T RW CH6LIMITL Write '1' to enable interrupt for event CH6LIMITL U RW CH7LIMITH Write '1' to enable interrupt for event CH7LIMITH V RW CH7LIMITL Write '1' to enable interrupt for event CH7LIMITL Description Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled 6.21.9.15 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW STARTED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event STARTED 4452_021 v1.3 372 Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Peripherals B RW END Write '1' to disable interrupt for event END C RW DONE Write '1' to disable interrupt for event DONE D RW RESULTDONE Write '1' to disable interrupt for event RESULTDONE E RW CALIBRATEDONE Write '1' to disable interrupt for event CALIBRATEDONE F RW STOPPED Write '1' to disable interrupt for event STOPPED G RW CH0LIMITH Write '1' to disable interrupt for event CH0LIMITH H RW CH0LIMITL Write '1' to disable interrupt for event CH0LIMITL I J RW CH1LIMITH Write '1' to disable interrupt for event CH1LIMITH RW CH1LIMITL Write '1' to disable interrupt for event CH1LIMITL K RW CH2LIMITH Write '1' to disable interrupt for event CH2LIMITH L RW CH2LIMITL Write '1' to disable interrupt for event CH2LIMITL M RW CH3LIMITH Write '1' to disable interrupt for event CH3LIMITH Description Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Value ID Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 4452_021 v1.3 373 Peripherals Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value N RW CH3LIMITL Write '1' to disable interrupt for event CH3LIMITL Value ID Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 O RW CH4LIMITH Write '1' to disable interrupt for event CH4LIMITH P RW CH4LIMITL Write '1' to disable interrupt for event CH4LIMITL Q RW CH5LIMITH Write '1' to disable interrupt for event CH5LIMITH R RW CH5LIMITL Write '1' to disable interrupt for event CH5LIMITL S RW CH6LIMITH Write '1' to disable interrupt for event CH6LIMITH T RW CH6LIMITL Write '1' to disable interrupt for event CH6LIMITL U RW CH7LIMITH Write '1' to disable interrupt for event CH7LIMITH V RW CH7LIMITL Write '1' to disable interrupt for event CH7LIMITL Description Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled 6.21.9.16 STATUS Address offset: 0x400 Status 4452_021 v1.3 374 Bit number ID ID A Reset 0x00000000 AccessField R STATUS 6.21.9.17 ENABLE Address offset: 0x500 Enable or disable SAADC Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Status Ready Busy SAADC is ready. No on-going conversions. SAADC is busy. Conversion in progress. Peripherals A A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled Enabled Enable or disable SAADC Disable SAADC Enable SAADC When enabled, the SAADC will acquire access to analog input pins specified in registers CH[n].PSELP and CH[n].PSELN 6.21.9.18 CH[n].PSELP (n=0..7) Address offset: 0x510 + (n 0x10) Input positive pin selection for CH[n]

Bit number ID ID A Reset 0x00000000 AccessField RW PSELP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Analog positive input channel Not connected NC AnalogInput0 AnalogInput1 AnalogInput2 AnalogInput3 AnalogInput4 AnalogInput5 AnalogInput6 AnalogInput7 VDD AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDD VDDHDIV5 0x0D VDDH/5 6.21.9.19 CH[n].PSELN (n=0..7) Address offset: 0x514 + (n 0x10) Input negative pin selection for CH[n]

4452_021 v1.3 375 0 1 0 1 0 1 2 3 4 5 6 7 8 9 Bit number ID ID A Reset 0x00000000 AccessField RW PSELN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Analog negative input, enables differential channel Not connected Peripherals A A A A A VDDHDIV5 0x0D VDDH/5 6.21.9.20 CH[n].CONFIG (n=0..7) Address offset: 0x518 + (n 0x10) Input configuration for CH[n]

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G F E E E D C C C B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Positive channel resistor control B RW RESN Negative channel resistor control NC AnalogInput0 AnalogInput1 AnalogInput2 AnalogInput3 AnalogInput4 AnalogInput5 AnalogInput6 AnalogInput7 VDD Bypass Pulldown Pullup VDD1_2 Bypass Pulldown Pullup VDD1_2 Gain1_6 Gain1_5 Gain1_4 Gain1_3 Gain1_2 Gain1 Gain2 Gain4 Internal VDD1_4 3us 5us 10us 0 1 2 3 4 5 6 7 8 9 0 1 2 3 0 1 2 3 0 1 2 3 4 5 6 7 0 1 0 1 2 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDD 1/6 1/5 1/4 1/3 1/2 1 2 4 Bypass resistor ladder Pull-down to GND Pull-up to VDD Set input at VDD/2 Bypass resistor ladder Pull-down to GND Pull-up to VDD Set input at VDD/2 Gain control Reference control Internal reference (0.6 V) VDD/4 as reference input voltage 3 s 5 s 10 s E RW TACQ Acquisition time, the time the SAADC uses to sample the 4452_021 v1.3 376 Bit number ID ID A Reset 0x00020000 AccessField RW RESP C RW GAIN D RW REFSEL Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G F E E E D C C C B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description F RW MODE Enable differential mode Single-ended, PSELN will be ignored, negative input to 15 s 20 s 40 s SAADC shorted to GND Differential Enable burst mode Burst mode is disabled (normal operation) Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. 6.21.9.21 CH[n].LIMIT (n=0..7) Address offset: 0x51C + (n 0x10) High/low limits for event monitoring of a channel Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A Reset 0x7FFF8000 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField RW LOW RW HIGH Value ID Value Description

[-32768 to +32767]

Low level limit

[-32768 to +32767]

High level limit Bit number ID Reset 0x00020000 ID AccessField G RW BURST 15us 20us 40us SE Diff Disabled Enabled ID ID A B ID ID A 6.21.9.22 RESOLUTION Address offset: 0x5F0 Resolution configuration 8bit 10bit 12bit 14bit 6.21.9.23 OVERSAMPLE Address offset: 0x5F4 3 4 5 0 1 0 1 0 1 2 3 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A A A Value ID Value Description Reset 0x00000001 AccessField RW VAL Set the resolution 8 bits 10 bits 12 bits 14 bits Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. 4452_021 v1.3 377 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW OVERSAMPLE Peripherals A A A A Bypass Over2x Over4x Over8x Over16x Over32x Over64x Over128x Over256x Oversample control Bypass oversampling Oversample 2x Oversample 4x Oversample 8x Oversample 16x Oversample 32x Oversample 64x Oversample 128x Oversample 256x 6.21.9.24 SAMPLERATE Address offset: 0x5F8 Controls normal or continuous sample rate Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description

[80..2047]

Capture and compare value. Sample rate is 16 MHz/CC Select mode for sample rate control Rate is controlled from SAMPLE task Rate is controlled from local timer (use CC to control the rate) ID ID A ID ID A B 0 1 2 3 4 5 6 7 8 0 1 AccessField RW CC RW MODE Task Timers 6.21.9.25 RESULT.PTR Address offset: 0x62C Data pointer Bit number ID ID A Reset 0x00000000 AccessField RW PTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Data pointer Note: See Memory on page 19 for details about memories available to EasyDMA. 6.21.9.26 RESULT.MAXCNT Address offset: 0x630 Maximum number of 16-bit samples to be written to output RAM buffer 4452_021 v1.3 378 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW MAXCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A Value ID Value Description Maximum number of 16-bit samples to be written to output RAM buffer 6.21.9.27 RESULT.AMOUNT Address offset: 0x634 Number of 16-bit samples written to output RAM buffer since the previous START task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A Value ID Value Description Reset 0x00000000 AccessField R AMOUNT Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. Symbol Description Typ. Max. Units ID ID A ID ID A DNL10 INL10 DNL12 INL12 VOS CEG fSAMPLE tACQ,10k tACQ,40k tACQ,100k tACQ,200k tACQ,400k tACQ,800k tCONV EG1/6 EG1/4 EG1/2 EG1 CSAMPLE RINPUT 6.21.10 Electrical specification 6.21.10.1 SAADC electrical specification Differential non-linearity, 10-bit resolution Integral non-linearity, 10-bit resolution Differential non-linearity, 12-bit resolution Integral non-linearity, 12-bit resolution Differential offset error (calibrated), 10-bit resolution 25 EVDDHDIV5 Error on VDDHDIV5 input Gain error temperature coefficient Maximum sampling rate Acquisition time (configurable), source resistance <= 10 k Acquisition time (configurable), source resistance <= 40 k Acquisition time (configurable), source resistance <= 100 k Acquisition time (configurable), source resistance <= 200 k Acquisition time (configurable), source resistance <= 400 k Acquisition time (configurable), source resistance <= 800 k Conversion time Error26 for gain = 1/6 Error26 for gain = 1/4 Error26 for gain = 1/2 Error26 for gain = 1 Input resistance Sample and hold capacitance at maximum gain27 25 Digital output code at zero volt differential input. 26 Does not include temperature drift 27 Maximum gain corresponds to highest capacitance. 4452_021 v1.3 379 Min.

-0.95

-0.95

-3

-3

-3

-3

<1 1 1.3 4.7 2 1 0.02 3 5 10 15 20 40

<2 2.5

>1 200 3 3 4 4 LSB10b LSB10b LSB12b LSB12b LSB10b

%/C kHz s s s s s s s

pF M Symbol ENOB SNDR SFDR Description 200 ksps Effective number of bits, differential mode, 12-bit resolution, 1/1 gain, 3 s acquisition time, crystal HFCLK, Peak signal to noise and distortion ratio, differential mode, 12-bit resolution, 1/1 gain, 3 s acquisition time, crystal HFCLK, 200 ksps Spurious free dynamic range, differential mode, 12-bit resolution, 1/1 gain, 3 s acquisition time, crystal HFCLK, 200 ksps RLADDER Ladder resistance Peripherals Min. Typ. Max. Units 9 56 70 Bit dB dBc 160 k 6.22 SPI Serial peripheral interface master The SPI master provides a simple CPU interface which includes a TXD register for sending data and an RXD register for receiving data. This section is added for legacy support for now. RXD-1 and TXD+1 illustrate the double buffered version of RXD and TXD respectively. 6.22.1 Functional description The TXD and RXD registers are double-buffered to enable some degree of uninterrupted data flow in and out of the SPI master. The SPI master does not implement support for chip select directly. Therefore, the CPU must use available GPIOs to select the correct slave and control this independently of the SPI master. The SPI master supports SPI modes 0 through 3. 4452_021 v1.3 380

F

G

3

5

5

3

3

3

5

F

F

F

J

3

3

1

4

3

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Peripherals Mode SPI_MODE0 SPI_MODE1 SPI_MODE2 SPI_MODE3 Clock polarity CPOL 0 (Leading) 0 (Leading) 1 (Trailing) 1 (Trailing) Clock phase CPHA 0 (Active high) 1 (Active low) 0 (Active high) 1 (Active low) 6.22.1.1 SPI master mode pin configuration The different signals SCK, MOSI, and MISO associated with the SPI master are mapped to physical pins. This mapping is according to the configuration specified in the PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers respectively. If the CONNECT field of a PSEL.xxx register is set to Disconnected, the associated SPI master signal is not connected to any physical pin. The PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used as long as the SPI master is enabled, and retained only as long as the device is in ON mode. PSEL.SCK, PSEL.MOSI, and PSEL.MISO must only be configured when the SPI master is disabled. To secure correct behavior in the SPI, the pins used by the SPI must be configured in the GPIO peripheral as described in GPIO configuration on page 381 prior to enabling the SPI. The SCK must always be connected to a pin, and that pin's input buffer must always be connected for the SPI to work. This configuration must be retained in the GPIO for the selected IOs as long as the SPI is enabled. Only one peripheral can be assigned to drive a particular GPIO pin at a time, failing to do so may result in unpredictable behavior. SPI master signal SPI master pin As specified in PSEL.SCK As specified in PSEL.MOSI As specified in PSEL.MISO Direction Output Output Input Output value Same as CONFIG.CPOL 0 Not applicable SCK MOSI MISO 6.22.1.2 Shared resources The SPI shares registers and other resources with other peripherals that have the same ID as the SPI. Therefore, the user must disable all peripherals that have the same ID as the SPI before the SPI can be configured and used. Disabling a peripheral that has the same ID as the SPI will not reset any of the registers that are shared with the SPI. It is therefore important to configure all relevant SPI registers explicitly to secure that it operates correctly. See the Instantiation table in Instantiation on page 22 for details on peripherals and their IDs. 6.22.1.3 SPI master transaction sequence An SPI master transaction is started by writing the first byte, which is to be transmitted by the SPI master, to the TXD register. Since the transmitter is double buffered, the second byte can be written to the TXD register immediately after the first one. The SPI master will then send these bytes in the order they are written to the TXD register. The SPI master is a synchronous interface, and for every byte that is sent, a different byte will be received at the same time; this is illustrated in SPI master transaction on page 382. Bytes that are received will be moved to the RXD register where the CPU can extract them by reading the register. The RXD register is double buffered in the same way as the TXD register, and a second byte can therefore be received at the 4452_021 v1.3 381

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same time as the first byte is being extracted from RXD by the CPU. The SPI master will generate a READY event every time a new byte is moved to the RXD register. The double buffered byte will be moved from RXD-1 to RXD as soon as the first byte is extracted from RXD. The SPI master will stop when there are no more bytes to send in TXD and TXD+1. Peripherals The READY event of the third byte transaction is delayed until B is extracted from RXD in occurrence number 3 on the horizontal lifeline. The reason for this is that the third event is generated first when C is moved from RXD-1 to RXD after B is read. The SPI master will move the incoming byte to the RXD register after a short delay following the SCK clock period of the last bit in the byte. This also means that the READY event will be delayed accordingly, see SPI master transaction on page 383. Therefore, it is important that you always clear the READY event, even if the RXD register and the data that is being received is not used. 4452_021 v1.3 382

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Peripherals 6.22.2 Registers Base address Peripheral Instance Configuration 0x40003000 0x40004000 0x40023000 SPI SPI SPI SPI0 SPI1 SPI2 Description SPI master 0 SPI master 1 SPI master 2 Deprecated Deprecated Deprecated Register EVENTS_READY INTENSET INTENCLR ENABLE PSEL.SCK PSEL.MOSI PSEL.MISO RXD TXD FREQUENCY CONFIG TXD byte sent and RXD byte received Offset 0x108 0x304 0x308 0x500 0x508 0x50C 0x510 0x518 0x51C 0x524 0x554 Description Enable interrupt Disable interrupt Enable SPI Pin select for SCK Pin select for MOSI signal Pin select for MISO signal RXD register TXD register Configuration register SPI frequency. Accuracy depends on the HFCLK source selected. 6.22.2.1 EVENTS_READY Address offset: 0x108 TXD byte sent and RXD byte received 4452_021 v1.3 383

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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_READY TXD byte sent and RXD byte received NotGenerated Generated Event not generated Event generated Peripherals A 0 1 1 0 1 1 0 1 0 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event READY Set Disabled Enabled Enable Read: Disabled Read: Enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event READY Clear Disabled Enabled Disable Read: Disabled Read: Enabled A A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled Enabled Enable or disable SPI Disable SPI Enable SPI 6.22.2.2 INTENSET Address offset: 0x304 Enable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW READY 6.22.2.3 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW READY 6.22.2.4 ENABLE Address offset: 0x500 Enable SPI Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 6.22.2.5 PSEL.SCK Address offset: 0x508 4452_021 v1.3 384 Peripherals B A A A A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect ID A B C ID A B C ID A B C Pin select for SCK Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.22.2.6 PSEL.MOSI Address offset: 0x50C Pin select for MOSI signal Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.22.2.7 PSEL.MISO Address offset: 0x510 Pin select for MISO signal Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.22.2.8 RXD Address offset: 0x518 RXD register C 1 0 C 1 0 C 1 0 4452_021 v1.3 385 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RX data received. Double buffered Peripherals A A A A A A A A Reset 0x00000000 AccessField R RXD 6.22.2.9 TXD Address offset: 0x51C TXD register Reset 0x00000000 AccessField RW TXD 6.22.2.10 FREQUENCY Address offset: 0x524 ID ID A ID ID A ID ID A 6.22.2.11 CONFIG Address offset: 0x554 Configuration register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A Value ID Value Description TX data to send. Double buffered SPI frequency. Accuracy depends on the HFCLK source selected. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x04000000 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW FREQUENCY SPI master data rate K125 K250 K500 M1 M2 M4 M8 0x02000000 0x04000000 0x08000000 0x10000000 0x20000000 0x40000000 0x80000000 125 kbps 250 kbps 500 kbps 1 Mbps 2 Mbps 4 Mbps 8 Mbps 4452_021 v1.3 386 Bit number ID ID A Reset 0x00000000 AccessField RW ORDER B RW CPHA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Peripherals C B A MsbFirst LsbFirst Leading Trailing ActiveHigh ActiveLow 0 1 0 1 0 1 Most significant bit shifted out first Least significant bit shifted out first Serial clock (SCK) phase Sample on leading edge of clock, shift serial data on trailing Sample on trailing edge of clock, shift serial data on leading Description Bit order edge edge Active high Active low C RW CPOL Serial clock (SCK) polarity 6.22.3 Electrical specification 6.22.3.1 SPI master interface electrical specifications Description Bit rates for SPI28 Time from writing TXD register to transmission started Min. Typ. Max. Units 829 Mbps s 1 6.22.3.2 Serial Peripheral Interface (SPI) Master timing specifications Symbol fSPI tSPI,START Symbol tSPI,CSCK tSPI,RSCK,LD tSPI,RSCK,HD tSPI,FSCK,LD tSPI,FSCK,HD tSPI,WHSCK tSPI,SUMI tSPI,HMI tSPI,VMO tSPI,HMO Description SCK period SCK rise time, standard drivea SCK rise time, high drivea SCK fall time, standard drivea SCK fall time, high drivea SCK high timea MISO to CLK edge setup time CLK edge to MISO hold time CLK edge to MOSI valid MOSI hold time after CLK edge tSPI,WLSCK SCK low timea Typ. Max. Units Min. 125 tRF,25pF tHRF,25pF tRF,25pF tHRF,25pF 59 ns ns ns ns ns

(tCSCK/2) tRSCK

(tCSCK/2) tFSCK 19 18 20 28 High bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details. 29 The actual maximum data rate depends on the slave's CLK to MISO and MOSI setup and hold timings. a At 25pF load, including GPIO capacitance, see GPIO spec. 4452_021 v1.3 387 Peripherals 6.23 SPIM Serial peripheral interface master with EasyDMA The SPI master can communicate with multiple SPI slaves using individual chip select signals for each slave. Listed here are the main features for the SPIM EasyDMA direct transfer to/from RAM SPI mode 0-3 Individual selection of I/O pins Optional D/CX output line for distinguishing between command and data bytes 4452_021 v1.3 388

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Peripherals TXD buffer RXD buffer TASKS_ S T A R T S T O P S U S P E N D R E S U M E GPIO SPIM PSEL.MOSI TXD.PTR EasyDMA RAM buffer[0]

buffer[1]

buffer[TXD.MAXCNT-1]

MOSI Pin SCK Pin CSN Pin DCX Pin MISO Pin PSEL.SCK PSEL.CSN PSELDCX EasyDMA buffer[0]

buffer[1]

PSEL.MISO RXD.PTR buffer[RXD.MAXCNT-1]

EVENTS_ S T O P P E D E N D R X E N D E N D T X S T A R T E D 6.23.1 SPI master transaction sequence An SPI master transaction is started by triggering the START task. When started, a number of bytes will be transmitted/received on MOSI/MISO. The following figure illustrates an SPI master transaction:

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A B A B 0 0 1 1 2 2 n ORC ORC m-2 m-1 m MOSI MISO SCK CSN S T A R T Peripherals E N D T X E N D E N D R X The ENDTX is generated when all bytes in buffer TXD.PTR on page 401 are transmitted. The number of bytes in the transmit buffer is specified in register TXD.MAXCNT on page 401. The ENDRX event will be generated when buffer RXD.PTR on page 400 is full, that is when the number of bytes specified in register RXD.MAXCNT on page 400 have been received. The transaction stops automatically after all bytes have been transmitted/received. When the maximum number of bytes in receive buffer is larger than the number of bytes in the transmit buffer, the contents of register ORC on page 404 will be transmitted after the last byte in the transmit buffer has been transmitted. The END event will be generated after both the ENDRX and ENDTX events have been generated. The SPI master can be stopped in the middle of a transaction by triggering the STOP task. When triggering the STOP task the SPIM will complete the transmission/reception of the current byte before stopping. A STOPPED event is generated when the SPI master has stopped. If the ENDTX event has not already been generated when the SPI master has come to a stop, the ENDTX event will be generated even if all bytes in the buffer TXD.PTR on page 401 have not been transmitted. If the ENDRX event has not already been generated when the SPI master has come to a stop, the ENDRX event will be generated even if the buffer RXD.PTR on page 400 is not full. A transaction can be suspended and resumed using the SUSPEND and RESUME tasks, receptively. When the SUSPEND task is triggered the SPI master will complete transmitting and receiving the current ongoing byte before it is suspended. 6.23.2 D/CX functionality Some SPI slaves, for example display drivers, require an additional signal from the SPI master to distinguish between command and data bytes. For display drivers this line is often called D/CX. The SPIM provides support for such a D/CX output line. The D/CX line is set low during transmission of command bytes and high during transmission of data bytes. The D/CX pin number is selected using PSELDCX on page 403 and the number of command bytes preceding the data bytes is configured using DCXCNT on page 403. It is not allowed to write to the DCXCNT on page 403 during an ongoing transmission. 4452_021 v1.3 390

Peripherals 6.23.3 Pin configuration The SCK, CSN, DCX, MOSI, and MISO signals associated with the SPIM are mapped to physical pins according to the configuration specified in the PSEL.n registers. The contents of registers PSEL.SCK on page 398, PSEL.CSN on page 399, PSELDCX on page 403, PSEL.MOSI on page 399 and PSEL.MISO on page 399 are only used when the SPIM is enabled and retained only as long as the device is in System ON mode. The PSEL.n registers can only be configured when the SPIM is disabled. Enabling/disabling is done using register ENABLE on page 398. To ensure correct behavior, the pins used by the SPIM must be configured in the GPIO peripheral as described in GPIO configuration on page 391 before the SPIM is enabled. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. SPI master signal SPI master pin Direction Output value Comments As specified in PSEL.SCK Output Same as CONFIG.CPOL SCK CSN DCX MOSI MISO As specified in PSEL.CSN Output Same as CONFIG.CPOL As specified in PSELDCX Output As specified in PSEL.MOSI Output 1 0 As specified in PSEL.MISO Input Not applicable on page 398 on page 399 on page 403 on page 399 on page 399 Some SPIM instances do not support automatic control of CSN, and for those the available GPIO pins need to be used to control CSN directly. See Instances on page 393 for information about what features are supported in the various SPIM instances. The SPIM supports SPI modes 0 through 3. The clock polarity (CPOL) and the clock phase (CPHA) are configured in register CONFIG on page 402. Mode Clock polarity Clock phase CPOL SPI_MODE0 0 (Active High) SPI_MODE1 0 (Active High) SPI_MODE2 1 (Active Low) SPI_MODE3 1 (Active Low) CPHA 0 (Leading) 1 (Trailing) 0 (Leading) 1 (Trailing) 6.23.4 EasyDMA The SPIM implements EasyDMA for accessing RAM without CPU involvement. 4452_021 v1.3 391

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Peripherals The SPIM peripheral implements the following EasyDMA channels:

Channel TXD RXD Type READER WRITER Register Cluster TXD RXD For detailed information regarding the use of EasyDMA, see EasyDMA on page 44. The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next transmission immediately after having received the STARTED event. The SPI master will automatically stop transmitting after TXD.MAXCNT bytes have been transmitted and RXD.MAXCNT bytes have been received. If RXD.MAXCNT is larger than TXD.MAXCNT, the remaining transmitted bytes will contain the value defined in the ORC register. If TXD.MAXCNT is larger than RXD.MAXCNT, the superfluous received bytes will be discarded. The ENDRX/ENDTX event indicate that EasyDMA has finished accessing respectively the RX/TX buffer in RAM. The END event gets generated when both RX and TX are finished accessing the buffers in RAM. In the case of bus congestion as described in AHB multilayer on page 46, the behaviour of the EasyDMA channel will depend on the SPIM instance. Refer to Instances on page 393 for information about what behaviour is supported in the various instances. 6.23.5 Low power When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral. The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent, software shall wait until the STOPPED event was received as a response before disabling the peripheral through the ENABLE register. 4452_021 v1.3 392

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Peripherals Configuration Not supported: > 8 Mbps data rate, CSNPOL register, DCX functionality, IFTIMING.x registers, hardware CSN control (PSEL.CSN), stalling mechanism during AHB bus contention. Recommended GPIOs for SCK signal for 8 Mbps data rate, see Pin assignments section for your package. CSNPOL register, DCX functionality, IFTIMING.x registers, hardware CSN control (PSEL.CSN), stalling mechanism during AHB bus contention. Recommended GPIOs for SCK signal for 8 Mbps data rate, see Pin assignments section for your package. CSNPOL register, DCX functionality, IFTIMING.x registers, hardware CSN control (PSEL.CSN), stalling mechanism during AHB bus contention. Recommended GPIOs for SCK signal for 8 Mbps data rate, see Pin assignments section for your package. 6.23.6 Registers Base address Peripheral 0x40003000 SPIM Instance SPIM0 Description SPI master 0 0x40004000 SPIM SPIM1 SPI master 1 Not supported: > 8 Mbps data rate, 0x40023000 SPIM SPIM2 SPI master 2 Not supported: > 8 Mbps data rate, 0x4002F000 SPIM SPIM3 SPI master 3 Register TASKS_START TASKS_STOP TASKS_SUSPEND TASKS_RESUME EVENTS_STOPPED EVENTS_ENDRX EVENTS_END EVENTS_ENDTX EVENTS_STARTED SHORTS INTENSET INTENCLR STALLSTAT ENABLE PSEL.SCK PSEL.MOSI PSEL.MISO PSEL.CSN FREQUENCY RXD.PTR Offset 0x010 0x014 0x01C 0x020 0x104 0x110 0x118 0x120 0x14C 0x200 0x304 0x308 0x400 0x500 0x508 0x50C 0x510 0x514 0x524 0x534 Description Start SPI transaction Stop SPI transaction Suspend SPI transaction Resume SPI transaction SPI transaction has stopped End of RXD buffer reached End of RXD buffer and TXD buffer reached End of TXD buffer reached Transaction started Shortcuts between local events and tasks Enable interrupt Disable interrupt Enable SPIM Pin select for SCK Pin select for MOSI signal Pin select for MISO signal Pin select for CSN Data pointer 4452_021 v1.3 393 Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. SPI frequency. Accuracy depends on the HFCLK source selected.

Peripherals A A Register RXD.MAXCNT RXD.AMOUNT RXD.LIST TXD.PTR TXD.MAXCNT TXD.AMOUNT TXD.LIST CONFIG IFTIMING.RXDELAY IFTIMING.CSNDUR CSNPOL PSELDCX DCXCNT ORC Offset 0x538 0x53C 0x540 0x544 0x548 0x54C 0x550 0x554 0x560 0x564 0x568 0x56C 0x570 0x5C0 Description Maximum number of bytes in receive buffer Number of bytes transferred in the last transaction EasyDMA list type Data pointer Number of bytes in transmit buffer Number of bytes transferred in the last transaction EasyDMA list type Configuration register Sample delay for input serial data on MISO stay high between transactions Polarity of CSN output Pin select for DCX signal DCX configuration Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT 6.23.6.1 TASKS_START Address offset: 0x010 Start SPI transaction 6.23.6.2 TASKS_STOP Address offset: 0x014 Stop SPI transaction ID ID A ID ID A 6.23.6.3 TASKS_SUSPEND Address offset: 0x01C Suspend SPI transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_START Start SPI transaction Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Stop SPI transaction Trigger 1 Trigger task 4452_021 v1.3 394

A A A A Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_SUSPEND Suspend SPI transaction Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_RESUME Resume SPI transaction Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description SPI transaction has stopped Event not generated Event generated 6.23.6.4 TASKS_RESUME Address offset: 0x020 Resume SPI transaction 6.23.6.5 EVENTS_STOPPED Address offset: 0x104 SPI transaction has stopped RW EVENTS_STOPPED NotGenerated Generated 6.23.6.6 EVENTS_ENDRX Address offset: 0x110 End of RXD buffer reached ID ID A ID ID A ID ID A ID ID A 0 1 0 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ENDRX NotGenerated Generated End of RXD buffer reached Event not generated Event generated 6.23.6.7 EVENTS_END Address offset: 0x118 End of RXD buffer and TXD buffer reached 4452_021 v1.3 395 A A A ID ID A ID ID A ID ID A ID ID A Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_END End of RXD buffer and TXD buffer reached NotGenerated Generated Event not generated Event generated 6.23.6.8 EVENTS_ENDTX Address offset: 0x120 End of TXD buffer reached RW EVENTS_ENDTX NotGenerated Generated 6.23.6.9 EVENTS_STARTED Address offset: 0x14C Transaction started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description End of TXD buffer reached Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_STARTED NotGenerated Generated Transaction started Event not generated Event generated 6.23.6.10 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW END_START Shortcut between event END and task START Disabled Enabled Disable shortcut Enable shortcut 6.23.6.11 INTENSET Address offset: 0x304 Enable interrupt 4452_021 v1.3 396 0 1 0 1 0 1 0 1 Bit number ID ID A Reset 0x00000000 AccessField RW STOPPED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event STOPPED Peripherals B RW ENDRX Write '1' to enable interrupt for event ENDRX C RW END Write '1' to enable interrupt for event END D RW ENDTX Write '1' to enable interrupt for event ENDTX E RW STARTED Write '1' to enable interrupt for event STARTED 6.23.6.12 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW STOPPED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event STOPPED B RW ENDRX Write '1' to disable interrupt for event ENDRX C RW END Write '1' to disable interrupt for event END D RW ENDTX Write '1' to disable interrupt for event ENDTX E RW STARTED Write '1' to disable interrupt for event STARTED 4452_021 v1.3 397 Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Peripherals 31 30 29 28 27 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Description Stall status for EasyDMA RAM reads B RW RX

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Stall status for EasyDMA RAM writes No stall A stall has occurred No stall A stall has occurred Enable or disable SPIM Disable SPIM Enable SPIM 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Bit number ID Reset 0x00000000 ID AccessField 6.23.6.13 STALLSTAT Address offset: 0x400 Value ID NOSTALL STALL NOSTALL STALL Disabled Enabled 6.23.6.14 ENABLE Address offset: 0x500 Enable SPIM Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 6.23.6.15 PSEL.SCK Address offset: 0x508 Pin select for SCK ID A B C Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 0 1 0 1 0 7 C 1 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 4452_021 v1.3 398 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 6.23.6.16 PSEL.MOSI Address offset: 0x50C Pin select for MOSI signal 6.23.6.17 PSEL.MISO Address offset: 0x510 Pin select for MISO signal Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.23.6.18 PSEL.CSN Address offset: 0x514 Pin select for CSN ID A B C ID A B C ID A B C C 1 0 C 1 0 C 1 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 6.23.6.19 FREQUENCY Address offset: 0x524 SPI frequency. Accuracy depends on the HFCLK source selected. 4452_021 v1.3 399 ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x04000000 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW FREQUENCY SPI master data rate Peripherals K125 K250 K500 M1 M2 M4 M8 M16 M32 0x02000000 0x04000000 0x08000000 0x10000000 0x20000000 0x40000000 0x80000000 0x0A000000 0x14000000 125 kbps 250 kbps 500 kbps 1 Mbps 2 Mbps 4 Mbps 8 Mbps 16 Mbps 32 Mbps 6.23.6.20 RXD.PTR Address offset: 0x534 Data pointer Bit number ID ID A Reset 0x00000000 AccessField RW PTR 6.23.6.21 RXD.MAXCNT Address offset: 0x538 Maximum number of bytes in receive buffer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Data pointer Note: See the memory chapter for details about which memories are available for EasyDMA. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW MAXCNT Value ID Value Description

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Maximum number of bytes in receive buffer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A 6.23.6.22 RXD.AMOUNT Address offset: 0x53C Number of bytes transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R AMOUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description

[0..0xFFFF]

Number of bytes transferred in the last transaction 4452_021 v1.3 400 Peripherals 6.23.6.23 RXD.LIST Address offset: 0x540 EasyDMA list type Reset 0x00000000 AccessField RW LIST 6.23.6.24 TXD.PTR Address offset: 0x544 Data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A Value ID Value Disabled ArrayList 0 1 Description List type Disable EasyDMA list Use array list Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW PTR Value ID Value Description Data pointer A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note: See the memory chapter for details about which memories are available for EasyDMA. 6.23.6.25 TXD.MAXCNT Address offset: 0x548 Number of bytes in transmit buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW MAXCNT Value ID Value Description

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Maximum number of bytes in transmit buffer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A 6.23.6.26 TXD.AMOUNT Address offset: 0x54C Number of bytes transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R AMOUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description

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Number of bytes transferred in the last transaction 4452_021 v1.3 401 ID ID A ID ID A ID ID A ID ID A Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Disabled ArrayList Description List type Disable EasyDMA list Use array list 6.23.6.27 TXD.LIST Address offset: 0x550 EasyDMA list type Bit number ID ID A Reset 0x00000000 AccessField RW LIST 6.23.6.28 CONFIG Address offset: 0x554 Configuration register Bit number ID ID A Reset 0x00000000 AccessField RW ORDER B RW CPHA 0 1 0 1 0 1 0 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value MsbFirst LsbFirst Leading Trailing ActiveHigh ActiveLow Most significant bit shifted out first Least significant bit shifted out first Serial clock (SCK) phase Sample on leading edge of clock, shift serial data on trailing Sample on trailing edge of clock, shift serial data on leading Description Bit order edge edge Active high Active low C RW CPOL Serial clock (SCK) polarity 6.23.6.29 IFTIMING.RXDELAY Address offset: 0x560 Sample delay for input serial data on MISO Bit number ID ID A Reset 0x00000002 AccessField RW RXDELAY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value ID Description Value

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Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY

= 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. 4452_021 v1.3 402 Peripherals 6.23.6.30 IFTIMING.CSNDUR Address offset: 0x564 Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions Bit number ID ID A Reset 0x00000002 AccessField RW CSNDUR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value ID Description Value

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Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description LOW HIGH Polarity of CSN output Active low (idle state high) Active high (idle state low) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A 6.23.6.31 CSNPOL Address offset: 0x568 Polarity of CSN output Bit number ID ID A Reset 0x00000000 AccessField RW CSNPOL 6.23.6.32 PSELDCX Address offset: 0x56C Pin select for DCX signal ID A B C Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value ID Disconnected Connected 6.23.6.33 DCXCNT Address offset: 0x570 DCX configuration 0 1 C 1 0 Value

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Description Pin number Port number Connection Disconnect Connect 4452_021 v1.3 403 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Peripherals A A A A Value ID Description Value 0x0..0xF This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. Bit number ID ID A Reset 0x00000000 AccessField RW DCXCNT 6.23.6.34 ORC Address offset: 0x5C0 Bit number ID ID A Reset 0x00000000 AccessField RW ORC 6.23.7 Electrical specification 6.23.7.1 Timing specifications Symbol fSPIM tSPIM,START tSPIM,CSCK tSPIM,RSCK,LD tSPIM,RSCK,HD tSPIM,FSCK,LD tSPIM,FSCK,HD tSPIM,WHSCK tSPIM,SUMI tSPIM,HMI tSPIM,VMO tSPIM,VMO,HS tSPIM,HMO Time from START task to transmission started Description Bit rates for SPIM30 SCK period SCK rise time, standard drive31 SCK rise time, high drive31 SCK fall time, standard drive31 SCK fall time, high drive31 SCK high time31 MISO to CLK edge setup time CLK edge to MISO hold time CLK edge to MOSI valid, SCK frequency <= 8 MHz CLK edge to MOSI valid, SCK frequency > 8 MHz MOSI hold time after CLK edge tSPIM,WLSCK SCK low time31 Min. Typ. Max. Units 32 Mbps 1 31.25 s ns ns ns ns ns ns tRF,25pF tHRF,25pF tRF,25pF tHRF,25pF 59 8

(tCSCK/2) tRSCK

(tCSCK/2) tFSCK 19 18 20 30 High bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details. 31 At 25pF load, including GPIO pin capacitance, see GPIO spec. 4452_021 v1.3 404 Peripherals I 6.24 SPIS Serial peripheral interface slave with EasyDMA SPI slave (SPIS) is implemented with EasyDMA support for ultra low power serial communication from an external SPI master. EasyDMA in conjunction with hardware-based semaphore mechanisms removes all real-time requirements associated with controlling the SPI slave from a low priority CPU execution context. 4452_021 v1.3 405

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The SPIS supports SPI modes 0 through 3. The CONFIG register allows setting CPOL and CPHA appropriately. Peripherals Mode Clock polarity Clock phase SPI_MODE0 SPI_MODE1 SPI_MODE2 SPI_MODE3 CPOL CPHA 0 (Active High) 0 (Trailing Edge) 0 (Active High) 1 (Leading Edge) 1 (Active Low) 0 (Trailing Edge) 1 (Active Low) 1 (Leading Edge) 6.24.1 Shared resources The SPI slave shares registers and other resources with other peripherals that have the same ID as the SPI slave. Therefore, you must disable all peripherals that have the same ID as the SPI slave before the SPI slave can be configured and used. Disabling a peripheral that has the same ID as the SPI slave will not reset any of the registers that are shared with the SPI slave. It is important to configure all relevant SPI slave registers explicitly to secure that it operates correctly. The Instantiation table in Instantiation on page 22 shows which peripherals have the same ID as the SPI slave. 6.24.2 EasyDMA The SPIS implements EasyDMA for accessing RAM without CPU involvement. The SPIS peripheral implements the following EasyDMA channels:

Channel TXD RXD Type READER WRITER Register Cluster TXD RXD For detailed information regarding the use of EasyDMA, see EasyDMA on page 44. If RXD.MAXCNT is larger than TXD.MAXCNT, the remaining transmitted bytes will contain the value defined in the ORC register. The END event indicates that EasyDMA has finished accessing the buffer in RAM. 6.24.3 SPI slave operation SPI slave uses two memory pointers, RXD.PTR and TXD.PTR, that point to the RXD buffer (receive buffer) and TXD buffer (transmit buffer) respectively. Since these buffers are located in RAM, which can be accessed by both the SPI slave and the CPU, a hardware based semaphore mechanism is implemented to enable safe sharing. See SPI transaction when shortcut between END and ACQUIRE is enabled on page 408. Before the CPU can safely update the RXD.PTR and TXD.PTR pointers it must first acquire the SPI semaphore. The CPU can acquire the semaphore by triggering the ACQUIRE task and then receiving the ACQUIRED event. When the CPU has updated the RXD.PTR and TXD.PTR pointers the CPU must release the semaphore before the SPI slave will be able to acquire it. The CPU releases the semaphore by triggering 4452_021 v1.3 406

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Peripherals the RELEASE task. This is illustrated in SPI transaction when shortcut between END and ACQUIRE is enabled on page 408. Triggering the RELEASE task when the semaphore is not granted to the CPU will have no effect. The semaphore mechanism does not, at any time, prevent the CPU from performing read or write access to the RXD.PTR register, the TXD.PTR registers, or the RAM that these pointers are pointing to. The semaphore is only telling when these can be updated by the CPU so that safe sharing is achieved. The semaphore is by default assigned to the CPU after the SPI slave is enabled. No ACQUIRED event will be generated for this initial semaphore handover. An ACQUIRED event will be generated immediately if the ACQUIRE task is triggered while the semaphore is assigned to the CPU. The SPI slave will try to acquire the semaphore when CSN goes low. If the SPI slave does not manage to acquire the semaphore at this point, the transaction will be ignored. This means that all incoming data on MOSI will be discarded, and the DEF (default) character will be clocked out on the MISO line throughout the whole transaction. This will also be the case even if the semaphore is released by the CPU during the transaction. In case of a race condition where the CPU and the SPI slave try to acquire the semaphore at the same time, as illustrated in lifeline item 2 in SPI transaction when shortcut between END and ACQUIRE is enabled on page 408, the semaphore will be granted to the CPU. If the SPI slave acquires the semaphore, the transaction will be granted. The incoming data on MOSI will be stored in the RXD buffer and the data in the TXD buffer will be clocked out on MISO. When a granted transaction is completed and CSN goes high, the SPI slave will automatically release the semaphore and generate the END event. As long as the semaphore is available the SPI slave can be granted multiple transactions one after the other. If the CPU is not able to reconfigure the TXD.PTR and RXD.PTR between granted transactions, the same TX data will be clocked out and the RX buffers will be overwritten. To prevent this from happening, the END_ACQUIRE shortcut can be used. With this shortcut enabled the semaphore will be handed over to the CPU automatically after the granted transaction has completed, giving the CPU the ability to update the TXPTR and RXPTR between every granted transaction. If the CPU tries to acquire the semaphore while it is assigned to the SPI slave, an immediate handover will not be granted. However, the semaphore will be handed over to the CPU as soon as the SPI slave has released the semaphore after the granted transaction is completed. If the END_ACQUIRE shortcut is enabled and the CPU has triggered the ACQUIRE task during a granted transaction, only one ACQUIRE request will be served following the END event. The MAXRX register specifies the maximum number of bytes the SPI slave can receive in one granted transaction. If the SPI slave receives more than MAXRX number of bytes, an OVERFLOW will be indicated in the STATUS register and the incoming bytes will be discarded. The MAXTX parameter specifies the maximum number of bytes the SPI slave can transmit in one granted transaction. If the SPI slave is forced to transmit more than MAXTX number of bytes, an OVERREAD will be indicated in the STATUS register and the ORC character will be clocked out. The RXD.AMOUNT and TXD.AMOUNT registers are updated when a granted transaction is completed. The TXD.AMOUNT register indicates how many bytes were read from the TX buffer in the last transaction, that is, ORC (over-read) characters are not included in this number. Similarly, the RXD.AMOUNT register indicates how many bytes were written into the RX buffer in the last transaction. The ENDRX event is generated when the RX buffer has been filled. 4452_021 v1.3 407 Peripherals 6.24.4 Pin configuration The CSN, SCK, MOSI, and MISO signals associated with the SPI slave are mapped to physical pins according to the configuration specified in the PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers respectively. If the CONNECT field of any of these registers is set to Disconnected, the associated SPI slave signal will not be connected to any physical pins. The PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used as long as the SPI slave is enabled, and retained only as long as the device is in System ON mode, see POWER Power supply on page 58 chapter for more information about power modes. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register. PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO must only be configured when the SPI slave is disabled. To secure correct behavior in the SPI slave, the pins used by the SPI slave must be configured in the GPIO peripheral as described in GPIO configuration before enabling peripheral on page 409 before enabling the SPI slave. This is to secure that the pins used by the SPI slave are driven correctly if the SPI slave itself is temporarily disabled, or if the device temporarily enters System OFF. This configuration must be retained in the GPIO for the selected I/Os as long as the SPI slave is to be recognized by an external SPI master. The MISO line is set in high impedance as long as the SPI slave is not selected with CSN. 4452_021 v1.3 408

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Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. Peripherals SPI signal SPI pin Direction Output value Comment CSN SCK MOSI MISO As specified in PSEL.CSN As specified in PSEL.SCK As specified in PSEL.MOSI As specified in PSEL.MISO Input Input Input Input Not applicable Not applicable Not applicable Not applicable Emulates that the SPI slave is not selected. 6.24.5 Registers Base address Peripheral Instance Description Configuration 0x40003000 0x40004000 0x40023000 SPIS SPIS SPIS SPIS0 SPIS1 SPIS2 SPI slave 0 SPI slave 1 SPI slave 2 Register TASKS_ACQUIRE TASKS_RELEASE EVENTS_END EVENTS_ENDRX EVENTS_ACQUIRED SHORTS INTENSET INTENCLR SEMSTAT STATUS ENABLE PSEL.SCK PSEL.MISO PSEL.MOSI PSEL.CSN PSELSCK PSELMISO PSELMOSI PSELCSN RXDPTR MAXRX AMOUNTRX RXD.PTR RXD.MAXCNT RXD.AMOUNT RXD.LIST TXDPTR MAXTX AMOUNTTX TXD.PTR TXD.MAXCNT TXD.AMOUNT 0x024 0x028 0x104 0x110 0x128 0x200 0x304 0x308 0x400 0x440 0x500 0x508 0x50C 0x510 0x514 0x508 0x50C 0x510 0x514 0x534 0x538 0x53C 0x534 0x538 0x53C 0x540 0x544 0x548 0x54C 0x544 0x548 0x54C Offset Description Acquire SPI semaphore Release SPI semaphore, enabling the SPI slave to acquire it Granted transaction completed End of RXD buffer reached Semaphore acquired Shortcuts between local events and tasks Enable interrupt Disable interrupt Semaphore status register Status from last transaction Enable SPI slave Pin select for SCK Pin select for MISO signal Pin select for MOSI signal Pin select for CSN signal Pin select for SCK Pin select for MISO Pin select for MOSI Pin select for CSN RXD data pointer Maximum number of bytes in receive buffer Number of bytes received in last granted transaction RXD data pointer Maximum number of bytes in receive buffer Number of bytes received in last granted transaction EasyDMA list type TXD data pointer TXD data pointer Maximum number of bytes in transmit buffer Number of bytes transmitted in last granted transaction Maximum number of bytes in transmit buffer Number of bytes transmitted in last granted transaction 4452_021 v1.3 409 Deprecated Deprecated Deprecated Deprecated Deprecated Deprecated Deprecated Deprecated Deprecated Deprecated

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Register TXD.LIST CONFIG DEF ORC Offset 0x550 0x554 0x55C 0x5C0 Description EasyDMA list type Configuration register Over-read character Default character. Character clocked out in case of an ignored transaction. Peripherals 6.24.5.1 TASKS_ACQUIRE Address offset: 0x024 Acquire SPI semaphore Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_ACQUIRE Acquire SPI semaphore Trigger 1 Trigger task 6.24.5.2 TASKS_RELEASE Address offset: 0x028 Release SPI semaphore, enabling the SPI slave to acquire it Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_RELEASE Release SPI semaphore, enabling the SPI slave to acquire it Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_END NotGenerated Generated 0 1 Granted transaction completed Event not generated Event generated ID ID A ID ID A ID ID A 6.24.5.3 EVENTS_END Address offset: 0x104 Granted transaction completed 6.24.5.4 EVENTS_ENDRX Address offset: 0x110 End of RXD buffer reached A A A 4452_021 v1.3 410

ID ID A ID ID A ID ID A ID ID A Peripherals A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ENDRX NotGenerated Generated End of RXD buffer reached Event not generated Event generated 6.24.5.5 EVENTS_ACQUIRED Address offset: 0x128 Semaphore acquired Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ACQUIRED NotGenerated Generated Semaphore acquired Event not generated Event generated 6.24.5.6 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW END_ACQUIRE Shortcut between event END and task ACQUIRE Disabled Enabled Disable shortcut Enable shortcut 6.24.5.7 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW END Value ID Value Description Write '1' to enable interrupt for event END 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C B A B RW ENDRX Write '1' to enable interrupt for event ENDRX Set Disabled Enabled Set Disabled Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled C RW ACQUIRED Write '1' to enable interrupt for event ACQUIRED 4452_021 v1.3 411 0 1 0 1 0 1 1 0 1 1 0 1 Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Set Disabled Enabled Value 1 0 1 Description Enable Read: Disabled Read: Enabled Bit number ID Reset 0x00000000 ID AccessField 6.24.5.8 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW END Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Free CPU SPIS 6.24.5.9 SEMSTAT Address offset: 0x400 Semaphore status register Bit number ID ID A Reset 0x00000001 AccessField R SEMSTAT 6.24.5.10 STATUS Address offset: 0x440 Status from last transaction 1 0 1 1 0 1 1 0 1 0 1 2 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event END B RW ENDRX Write '1' to disable interrupt for event ENDRX C RW ACQUIRED Write '1' to disable interrupt for event ACQUIRED Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description CPUPending Semaphore is assigned to SPI but a handover to the CPU is Semaphore status Semaphore is free Semaphore is assigned to CPU Semaphore is assigned to SPI slave pending Individual bits are cleared by writing a '1' to the bits that shall be cleared 4452_021 v1.3 412 Peripherals B A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW OVERREAD TX buffer over-read detected, and prevented B RW OVERFLOW RX buffer overflow detected, and prevented NotPresent Present Clear NotPresent Present Clear Read: error not present Read: error present Write: clear error on writing '1'

Read: error not present Read: error present Write: clear error on writing '1'

0 1 1 0 1 1 0 2 C 1 0 6.24.5.11 ENABLE Address offset: 0x500 Enable SPI slave Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 6.24.5.12 PSEL.SCK Address offset: 0x508 Pin select for SCK ID A B C Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.24.5.13 PSEL.MISO Address offset: 0x50C Pin select for MISO signal 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled Enabled Enable or disable SPI slave Disable SPI slave Enable SPI slave Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 4452_021 v1.3 413 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Peripherals B A A A A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect ID A B C ID A B C ID A B C 6.24.5.14 PSEL.MOSI Address offset: 0x510 Pin select for MOSI signal Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.24.5.15 PSEL.CSN Address offset: 0x514 Pin select for CSN signal C 1 0 C 1 0 C 1 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

[0..31]

[0..1]

Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 6.24.5.16 PSELSCK ( Deprecated ) Address offset: 0x508 Pin select for SCK Bit number ID ID A Reset 0xFFFFFFFF AccessField RW PSELSCK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Description Value

[0..31]

Pin number configuration for SPI SCK signal Disconnected 0xFFFFFFFF Disconnect 4452_021 v1.3 414 Peripherals 6.24.5.17 PSELMISO ( Deprecated ) Address offset: 0x50C Pin select for MISO ID ID A ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xFFFFFFFF AccessField RW PSELMISO A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Description Value

[0..31]

Disconnected 0xFFFFFFFF Disconnect Pin number configuration for SPI MISO signal 6.24.5.18 PSELMOSI ( Deprecated ) Address offset: 0x510 Pin select for MOSI Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xFFFFFFFF AccessField RW PSELMOSI A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Description Value

[0..31]

Disconnected 0xFFFFFFFF Disconnect Pin number configuration for SPI MOSI signal 6.24.5.19 PSELCSN ( Deprecated ) Address offset: 0x514 Pin select for CSN Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xFFFFFFFF AccessField RW PSELCSN A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Description Value

[0..31]

Pin number configuration for SPI CSN signal Disconnected 0xFFFFFFFF Disconnect 6.24.5.20 RXDPTR ( Deprecated ) Address offset: 0x534 RXD data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW RXDPTR Value ID Value Description RXD data pointer A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note: See the memory chapter for details about which memories are available for EasyDMA. 4452_021 v1.3 415 ID ID A ID ID A ID ID A Peripherals 6.24.5.21 MAXRX ( Deprecated ) Address offset: 0x538 Maximum number of bytes in receive buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW MAXRX Value ID Value Description

[0..0xFFFF]

Maximum number of bytes in receive buffer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A 6.24.5.22 AMOUNTRX ( Deprecated ) Address offset: 0x53C Number of bytes received in last granted transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R AMOUNTRX

[0..0xFFFF]

Number of bytes received in the last granted transaction 6.24.5.23 RXD.PTR Address offset: 0x534 RXD data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW PTR Value ID Value Description RXD data pointer A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note: See the memory chapter for details about which memories are available for EasyDMA. 6.24.5.24 RXD.MAXCNT Address offset: 0x538 Maximum number of bytes in receive buffer Bit number ID ID A Reset 0x00000000 AccessField RW MAXCNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description

[0..0xFFFF]

Maximum number of bytes in receive buffer 6.24.5.25 RXD.AMOUNT Address offset: 0x53C Number of bytes received in last granted transaction 4452_021 v1.3 416 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description

[0..0xFFFF]

Number of bytes received in the last granted transaction Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A Value ID Value Disabled ArrayList 0 1 Description List type Disable EasyDMA list Use array list Reset 0x00000000 AccessField R AMOUNT 6.24.5.26 RXD.LIST Address offset: 0x540 EasyDMA list type ID ID A ID ID A Reset 0x00000000 AccessField RW LIST Bit number ID ID A Reset 0x00000000 AccessField RW TXDPTR 6.24.5.27 TXDPTR ( Deprecated ) Address offset: 0x544 TXD data pointer 6.24.5.28 MAXTX ( Deprecated ) Address offset: 0x548 Maximum number of bytes in transmit buffer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TXD data pointer Note: See the memory chapter for details about which memories are available for EasyDMA. Bit number ID ID A Reset 0x00000000 AccessField RW MAXTX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description

[0..0xFFFF]

Maximum number of bytes in transmit buffer 6.24.5.29 AMOUNTTX ( Deprecated ) Address offset: 0x54C Number of bytes transmitted in last granted transaction 4452_021 v1.3 417 ID ID A ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R AMOUNTTX

[0..0xFFFF]

Number of bytes transmitted in last granted transaction Peripherals 6.24.5.30 TXD.PTR Address offset: 0x544 TXD data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW PTR Value ID Value Description TXD data pointer A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note: See the memory chapter for details about which memories are available for EasyDMA. 6.24.5.31 TXD.MAXCNT Address offset: 0x548 Maximum number of bytes in transmit buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description

[0..0xFFFF]

Maximum number of bytes in transmit buffer Reset 0x00000000 AccessField RW MAXCNT 6.24.5.32 TXD.AMOUNT Address offset: 0x54C Number of bytes transmitted in last granted transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description

[0..0xFFFF]

Number of bytes transmitted in last granted transaction Reset 0x00000000 AccessField R AMOUNT 6.24.5.33 TXD.LIST Address offset: 0x550 EasyDMA list type 4452_021 v1.3 418 0 1 0 1 0 1 0 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Peripherals A A Value ID Value Disabled ArrayList Description List type Disable EasyDMA list Use array list 6.24.5.34 CONFIG Address offset: 0x554 Configuration register Bit number ID ID A Reset 0x00000000 AccessField RW LIST Bit number ID ID A Reset 0x00000000 AccessField RW ORDER B RW CPHA 6.24.5.35 DEF Address offset: 0x55C Reset 0x00000000 AccessField RW DEF 6.24.5.36 ORC Address offset: 0x5C0 Over-read character ID ID A ID ID A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value MsbFirst LsbFirst Leading Trailing ActiveHigh ActiveLow Most significant bit shifted out first Least significant bit shifted out first Serial clock (SCK) phase Sample on leading edge of clock, shift serial data on trailing Sample on trailing edge of clock, shift serial data on leading Description Bit order edge edge Active high Active low C RW CPOL Serial clock (SCK) polarity Default character. Character clocked out in case of an ignored transaction. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A Value ID Value Description Default character. Character clocked out in case of an ignored transaction. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW ORC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A Value ID Value Description Over-read character. Character clocked out after an over-

read of the transmit buffer. 4452_021 v1.3 419 Peripherals 6.24.6 Electrical specification 6.24.6.1 SPIS slave interface electrical specifications Symbol fSPIS tSPIS,START Description Bit rates for SPIS32 Time from RELEASE task to receive/transmit (CSN active) Min. Typ. Max. Units 833 Mbps s 0.125 6.24.6.2 Serial Peripheral Interface Slave (SPIS) timing specifications Symbol Description Typ. Max. Units tSPIS,CSCKIN tSPIS,RFSCKIN tSPIS,WHSCKIN tSPIS,WLSCKIN tSPIS,SUCSN tSPIS,HCSN tSPIS,ASA tSPIS,ASO tSPIS,DISSO tSPIS,CWH tSPIS,VSO tSPIS,HSO tSPIS,SUSI tSPIS,HSI SCK input period SCK input rise/fall time SCK input high time SCK input low time CSN to CLK setup time CLK to CSN hold time CSN to MISO driven CSN to MISO valid34 CSN to MISO disabled34 CSN inactive time CLK edge to MISO valid MISO hold time after CLK edge MOSI to CLK edge setup time CLK edge to MOSI hold time Min. 125 30 30 1000 1000 0 300 1835 59 20 30 1000 68 19 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 32 High bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details. 33 The actual maximum data rate depends on the master's CLK to MISO and MOSI setup and hold timings. 34 At 25pF load, including GPIO capacitance, see GPIO spec. 35 This is to ensure compatibility to SPI masters sampling MISO on the same edge as MOSI is output 4452_021 v1.3 420 Peripherals 4452_021 v1.3 421

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Peripherals 6.25 SWI Software interrupts A set of interrupts have been reserved for use as software interrupts. 6.25.1 Registers Base address Peripheral Instance Description Configuration 0x40014000 0x40015000 0x40016000 0x40017000 0x40018000 0x40019000 SWI SWI SWI SWI SWI SWI SWI0 SWI1 SWI2 SWI3 SWI4 SWI5 Software interrupt 0 Software interrupt 1 Software interrupt 2 Software interrupt 3 Software interrupt 4 Software interrupt 5 6.26 TEMP Temperature sensor The temperature sensor measures die temperature over the temperature range of the device. Linearity compensation can be implemented if required by the application. Listed here are the main features for TEMP:

Temperature range is greater than or equal to operating temperature of the device Resolution is 0.25 degrees TEMP is started by triggering the START task. When the temperature measurement is completed, a DATARDY event will be generated and the result of the measurement can be read from the TEMP register. To achieve the measurement accuracy stated in the electrical specification, the crystal oscillator must be selected as the HFCLK source, see CLOCK Clock control on page 80 for more information. When the temperature measurement is completed, TEMP analog electronics power down to save power. TEMP only supports one-shot operation, meaning that every TEMP measurement has to be explicitly started using the START task. 6.26.1 Registers Base address Peripheral Instance Description Configuration 0x4000C000 TEMP TEMP Temperature sensor EVENTS_DATARDY Temperature measurement complete, data ready Register TASKS_START TASKS_STOP INTENSET INTENCLR TEMP A0 Offset 0x000 0x004 0x100 0x304 0x308 0x508 0x520 Description Start temperature measurement Stop temperature measurement Enable interrupt Disable interrupt Temperature in C (0.25 steps) Slope of first piecewise linear function 4452_021 v1.3 422

A1 A2 A3 A4 A5 B0 B1 B2 B3 B4 B5 T0 T1 T2 T3 T4 ID ID A ID ID A Register Description Peripherals Offset 0x524 0x528 0x52C 0x530 0x534 0x540 0x544 0x548 0x54C 0x550 0x554 0x560 0x564 0x568 0x56C 0x570 Slope of second piecewise linear function Slope of third piecewise linear function Slope of fourth piecewise linear function Slope of fifth piecewise linear function Slope of sixth piecewise linear function y-intercept of first piecewise linear function y-intercept of second piecewise linear function y-intercept of third piecewise linear function y-intercept of fourth piecewise linear function y-intercept of fifth piecewise linear function y-intercept of sixth piecewise linear function End point of first piecewise linear function End point of second piecewise linear function End point of third piecewise linear function End point of fourth piecewise linear function End point of fifth piecewise linear function 6.26.1.1 TASKS_START Address offset: 0x000 Start temperature measurement 6.26.1.2 TASKS_STOP Address offset: 0x004 Stop temperature measurement Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_START Start temperature measurement Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Stop temperature measurement Trigger 1 Trigger task 6.26.1.3 EVENTS_DATARDY Address offset: 0x100 Temperature measurement complete, data ready A A 4452_021 v1.3 423

Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_DATARDY Temperature measurement complete, data ready NotGenerated Generated Event not generated Event generated 0 1 1 0 1 1 0 1 6.26.1.4 INTENSET Address offset: 0x304 Enable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW DATARDY 6.26.1.5 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW DATARDY 6.26.1.6 TEMP Address offset: 0x508 Temperature in C (0.25 steps) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event DATARDY Set Disabled Enabled Enable Read: Disabled Read: Enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event DATARDY Clear Disabled Enabled Disable Read: Disabled Read: Enabled A A A Bit number ID ID A Reset 0x00000000 AccessField R TEMP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Temperature in C (0.25 steps) Result of temperature measurement. Die temperature in C, 2's complement format, 0.25 C steps. Decision point: DATARDY 4452_021 v1.3 424 Peripherals 6.26.1.7 A0 Address offset: 0x520 Slope of first piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 A A A A A A A A A A A A Value ID Value Description Slope of first piecewise linear function ID ID A ID ID A ID ID A ID ID A Reset 0x00000326 AccessField RW A0 6.26.1.8 A1 Address offset: 0x524 Reset 0x00000348 AccessField RW A1 6.26.1.9 A2 Address offset: 0x528 AccessField RW A2 6.26.1.10 A3 Address offset: 0x52C Reset 0x0000040E AccessField RW A3 6.26.1.11 A4 Address offset: 0x530 Slope of second piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 A A A A A A A A A A A A Value ID Value Description Slope of second piecewise linear function Slope of third piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A Reset 0x000003AA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 Value ID Value Description Slope of third piecewise linear function Slope of fourth piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 A A A A A A A A A A A A Value ID Value Description Slope of fourth piecewise linear function Slope of fifth piecewise linear function 4452_021 v1.3 425 ID ID A ID ID A ID ID A ID ID A ID ID A AccessField RW A5 6.26.1.13 B0 Address offset: 0x540 Reset 0x00003FEF AccessField RW B0 6.26.1.14 B1 Address offset: 0x544 Reset 0x00003FBE AccessField RW B1 6.26.1.15 B2 Address offset: 0x548 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000004BD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 1 0 1 Value ID Value Description Slope of fifth piecewise linear function Peripherals A A A A A A A A A A A A AccessField RW A4 6.26.1.12 A5 Address offset: 0x534 Slope of sixth piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A Reset 0x000005A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 1 1 Value ID Value Description Slope of sixth piecewise linear function y-intercept of first piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 A A A A A A A A A A A A A A Value ID Value Description y-intercept of first piecewise linear function y-intercept of second piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 0 A A A A A A A A A A A A A A Value ID Value Description y-intercept of second piecewise linear function y-intercept of third piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00003FBE AccessField RW B2 Value ID Value Description y-intercept of third piecewise linear function 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 0 A A A A A A A A A A A A A A 4452_021 v1.3 426 Peripherals 6.26.1.16 B3 Address offset: 0x54C y-intercept of fourth piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 A A A A A A A A A A A A A A Value ID Value Description y-intercept of fourth piecewise linear function ID ID A ID ID A ID ID A ID ID A Reset 0x00000012 AccessField RW B3 6.26.1.17 B4 Address offset: 0x550 Reset 0x00000124 AccessField RW B4 6.26.1.18 B5 Address offset: 0x554 Reset 0x0000027C AccessField RW B5 6.26.1.19 T0 Address offset: 0x560 Reset 0x000000E2 AccessField RW T0 6.26.1.20 T1 Address offset: 0x564 y-intercept of fifth piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 A A A A A A A A A A A A A A Value ID Value Description y-intercept of fifth piecewise linear function y-intercept of sixth piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 A A A A A A A A A A A A A A Value ID Value Description y-intercept of sixth piecewise linear function End point of first piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 A A A A A A A A Value ID Value Description End point of first piecewise linear function End point of second piecewise linear function 4452_021 v1.3 427 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description End point of second piecewise linear function Peripherals A A A A A A A A Reset 0x00000000 AccessField RW T1 6.26.1.21 T2 Address offset: 0x568 Reset 0x00000019 AccessField RW T2 6.26.1.22 T3 Address offset: 0x56C Reset 0x0000003C AccessField RW T3 6.26.1.23 T4 Address offset: 0x570 ID ID A ID ID A ID ID A ID ID A End point of third piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 A A A A A A A A Value ID Value Description End point of third piecewise linear function End point of fourth piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 A A A A A A A A Value ID Value Description End point of fourth piecewise linear function End point of fifth piecewise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000050 AccessField RW T4 Value ID Value Description End point of fifth piecewise linear function 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 A A A A A A A A 6.26.2 Electrical specification 6.26.2.1 Temperature Sensor Electrical Specification Symbol tTEMP TTEMP,RANGE TTEMP,ACC TTEMP,ACC,EXT TTEMP,RES TTEMP,STB Description Time required for temperature measurement Temperature sensor range Temperature sensor accuracy Temperature sensor accuracy, extended temperature range Temperature sensor resolution Sample to sample stability at constant device temperature 4452_021 v1.3 428 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-7 105 5 7 36 0.25 0.25 s C C C C C C TTEMP,OFFST Sample offset at 25C

-2.5 2.5 6.27 TWI I2C compatible two-wire interface The TWI master is compatible with I2C operating at 100 kHz and 400 kHz. Peripherals 6.27.1 Functional description This TWI master is not compatible with CBUS. The TWI transmitter and receiver are single buffered. See, TWI master's main features on page 429. A TWI setup comprising one master and three slaves is illustrated in A typical TWI setup comprising one master and three slaves on page 429. This TWI master is only able to operate as the only master on the TWI bus. This TWI master supports clock stretching performed by the slaves. The TWI master is started by triggering the STARTTX or STARTRX tasks, and stopped by triggering the STOP task. If a NACK is clocked in from the slave, the TWI master will generate an ERROR event. 6.27.2 Master mode pin configuration The different signals SCL and SDA associated with the TWI master are mapped to physical pins according to the configuration specified in the PSEL.SCL and PSEL.SDA registers respectively. If the CONNECT field of a PSEL.xxx register is set to Disconnected, the associated TWI signal is not connected to any physical pin. The PSEL.SCL and PSEL.SDA registers and their configurations are only used 4452_021 v1.3 429

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Peripherals as long as the TWI master is enabled, and retained only as long as the device is in ON mode. PSEL.SCL and PSEL.SDA must only be configured when the TWI is disabled. To secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and when the TWI master is disabled, these pins must be configured in the GPIO peripheral as described in GPIO configuration on page 430. Only one peripheral can be assigned to drive a particular GPIO pin at a time, failing to do so may result in unpredictable behavior. TWI master signal TWI master pin Direction Drive strength SCL SDA As specified in PSEL.SCL As specified in PSEL.SDA Input Input S0D1 S0D1 Output value Not applicable Not applicable 6.27.3 Shared resources The TWI shares registers and other resources with other peripherals that have the same ID as the TWI. Therefore, you must disable all peripherals that have the same ID as the TWI before the TWI can be configured and used. Disabling a peripheral that has the same ID as the TWI will not reset any of the registers that are shared with the TWI. It is therefore important to configure all relevant TWI registers explicitly to secure that it operates correctly. The Instantiation table in Instantiation on page 22 shows which peripherals have the same ID as the TWI. 6.27.4 Master write sequence A TWI master write sequence is started by triggering the STARTTX task. After the STARTTX task has been triggered, the TWI master will generate a start condition on the TWI bus, followed by clocking out the address and the READ/WRITE bit set to 0 (WRITE=0, READ=1). The address must match the address of the slave device that the master wants to write to. The READ/

WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) generated by the slave. After receiving the ACK bit, the TWI master will clock out the data bytes that are written to the TXD register. Each byte clocked out from the master will be followed by an ACK/NACK bit clocked in from the slave. A TXDSENT event will be generated each time the TWI master has clocked out a TXD byte, and the associated ACK/NACK bit has been clocked in from the slave. The TWI master transmitter is single buffered, and a second byte can only be written to the TXD register after the previous byte has been clocked out and the ACK/NACK bit clocked in, that is, after the TXDSENT event has been generated. If the CPU is prevented from writing to TXD when the TWI master is ready to clock out a byte, the TWI master will stretch the clock until the CPU has written a byte to the TXD register. A typical TWI master write sequence is illustrated in The TWI master writing data to a slave on page 431. Occurrence 3 in the figure illustrates delayed processing of the TXDSENT event associated with TXD byte 1. In this scenario the TWI master will stretch the clock to prevent writing erroneous data to the slave. 4452_021 v1.3 430

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Peripherals The TWI master write sequence is stopped when the STOP task is triggered whereupon the TWI master will generate a stop condition on the TWI bus. 6.27.5 Master read sequence A TWI master read sequence is started by triggering the STARTRX task. After the STARTRX task has been triggered the TWI master will generate a start condition on the TWI bus, followed by clocking out the address and the READ/WRITE bit set to 1 (WRITE = 0, READ = 1). The address must match the address of the slave device that the master wants to read from. The READ/

WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK = 1) generated by the slave. After having sent the ACK bit the TWI slave will send data to the master using the clock generated by the master. The TWI master will generate a RXDRDY event every time a new byte is received in the RXD register. After receiving a byte, the TWI master will delay sending the ACK/NACK bit by stretching the clock until the CPU has extracted the received byte, that is, by reading the RXD register. The TWI master read sequence is stopped by triggering the STOP task. This task must be triggered before the last byte is extracted from RXD to ensure that the TWI master sends a NACK back to the slave before generating the stop condition. A typical TWI master read sequence is illustrated in The TWI master reading data from a slave on page 432. Occurrence 3 in this figure illustrates delayed processing of the RXDRDY event associated with RXD byte B. In this scenario the TWI master will stretch the clock to prevent the slave from overwriting the contents of the RXD register. 4452_021 v1.3 431

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Peripherals 6.27.6 Master repeated start sequence A typical repeated start sequence is one in which the TWI master writes one byte to the slave followed by reading M bytes from the slave. Any combination and number of transmit and receive sequences can be combined in this fashion. Only one shortcut to STOP can be enabled at any given time. The figure below illustrates a repeated start sequence where the TWI master writes one byte, followed by reading M bytes from the slave without performing a stop in-between. 4452_021 v1.3 432

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Peripherals To generate a repeated start after a read sequence, a second start task must be triggered instead of the STOP task, that is, STARTRX or STARTTX. This start task must be triggered before the last byte is extracted from RXD to ensure that the TWI master sends a NACK back to the slave before generating the repeated start condition. 6.27.7 Low power When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral. The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent, software shall wait until the STOPPED event was received as a response before disabling the peripheral through the ENABLE register. 6.27.8 Registers Base address Peripheral Instance Description Configuration 0x40003000 0x40004000 TWI TWI TWI0 TWI1 Two-wire interface master 0 Two-wire interface master 1 Deprecated Deprecated EVENTS_SUSPENDED TWI entered the suspended state Shortcuts between local events and tasks TWI byte boundary, generated before each byte that is sent or received Register Offset Description TASKS_STARTRX TASKS_STARTTX TASKS_STOP TASKS_SUSPEND TASKS_RESUME EVENTS_STOPPED EVENTS_RXDREADY EVENTS_TXDSENT EVENTS_ERROR EVENTS_BB SHORTS INTENSET INTENCLR ERRORSRC ENABLE PSEL.SCL PSEL.SDA RXD TXD FREQUENCY ADDRESS 0x000 0x008 0x014 0x01C 0x020 0x104 0x108 0x11C 0x124 0x138 0x148 0x200 0x304 0x308 0x4C4 0x500 0x508 0x50C 0x518 0x51C 0x524 0x588 Start TWI receive sequence Start TWI transmit sequence Stop TWI transaction Suspend TWI transaction Resume TWI transaction TWI stopped TWI RXD byte received TWI TXD byte sent TWI error Enable interrupt Disable interrupt Error source Enable TWI Pin select for SCL Pin select for SDA RXD register TXD register 6.27.8.1 TASKS_STARTRX Address offset: 0x000 Start TWI receive sequence 4452_021 v1.3 433 TWI frequency. Accuracy depends on the HFCLK source selected. Address used in the TWI transfer

Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTRX Start TWI receive sequence Trigger 1 Trigger task ID ID A ID ID A ID ID A ID ID A 6.27.8.2 TASKS_STARTTX Address offset: 0x008 Start TWI transmit sequence 6.27.8.3 TASKS_STOP Address offset: 0x014 Stop TWI transaction 6.27.8.4 TASKS_SUSPEND Address offset: 0x01C Suspend TWI transaction 6.27.8.5 TASKS_RESUME Address offset: 0x020 Resume TWI transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTTX Start TWI transmit sequence Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Stop TWI transaction Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_SUSPEND Suspend TWI transaction Trigger 1 Trigger task A A A A 4452_021 v1.3 434 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_RESUME Resume TWI transaction Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value RW EVENTS_STOPPED NotGenerated Generated Description TWI stopped Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description ID ID A ID ID A ID ID A ID ID A 6.27.8.6 EVENTS_STOPPED Address offset: 0x104 TWI stopped 0 1 0 1 0 1 6.27.8.7 EVENTS_RXDREADY Address offset: 0x108 TWI RXD byte received RW EVENTS_RXDREADY NotGenerated Generated 6.27.8.8 EVENTS_TXDSENT Address offset: 0x11C TWI TXD byte sent RW EVENTS_TXDSENT NotGenerated Generated 6.27.8.9 EVENTS_ERROR Address offset: 0x124 TWI error Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description TWI RXD byte received Event not generated Event generated TWI TXD byte sent Event not generated Event generated A A A A 4452_021 v1.3 435 0 1 0 1 ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Peripherals AccessField Value ID Value RW EVENTS_ERROR NotGenerated Generated Description TWI error Event not generated Event generated 6.27.8.10 EVENTS_BB Address offset: 0x138 TWI byte boundary, generated before each byte that is sent or received Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_BB TWI byte boundary, generated before each byte that is sent NotGenerated Generated or received Event not generated Event generated 6.27.8.11 EVENTS_SUSPENDED Address offset: 0x148 TWI entered the suspended state Generated just after ACK bit has been transferred in a read transaction, and only if SUSPEND has been requested earlier. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_SUSPENDED TWI entered the suspended state Generated just after ACK bit has been transferred in a read transaction, and only if SUSPEND has been requested NotGenerated Generated 0 1 earlier. Event not generated Event generated A A A 6.27.8.12 SHORTS Address offset: 0x200 Shortcuts between local events and tasks 4452_021 v1.3 436 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW BB_SUSPEND Shortcut between event BB and task SUSPEND Peripherals B A B RW BB_STOP Shortcut between event BB and task STOP 6.27.8.13 INTENSET Address offset: 0x304 Enable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW STOPPED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event STOPPED B RW RXDREADY Write '1' to enable interrupt for event RXDREADY C RW TXDSENT Write '1' to enable interrupt for event TXDSENT D RW ERROR Write '1' to enable interrupt for event ERROR E RW BB Write '1' to enable interrupt for event BB F RW SUSPENDED Write '1' to enable interrupt for event SUSPENDED Generated just after ACK bit has been transferred in a read transaction, and only if SUSPEND has been requested Disabled Enabled Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Disable shortcut Enable shortcut Disable shortcut Enable shortcut Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled earlier. Enable Read: Disabled Read: Enabled 6.27.8.14 INTENCLR Address offset: 0x308 Disable interrupt 4452_021 v1.3 437 Bit number ID ID A Reset 0x00000000 AccessField RW STOPPED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event STOPPED Peripherals B RW RXDREADY Write '1' to disable interrupt for event RXDREADY C RW TXDSENT Write '1' to disable interrupt for event TXDSENT D RW ERROR Write '1' to disable interrupt for event ERROR E RW BB Write '1' to disable interrupt for event BB F RW SUSPENDED Write '1' to disable interrupt for event SUSPENDED Generated just after ACK bit has been transferred in a read transaction, and only if SUSPEND has been requested Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled earlier. Disable Read: Disabled Read: Enabled 6.27.8.15 ERRORSRC Address offset: 0x4C4 Error source Bit number ID ID A Reset 0x00000000 AccessField RW OVERRUN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Overrun error A new byte was received before previous byte got read by software from the RXD register. (Previous data is lost) B RW ANACK NACK received after sending the address (write '1' to clear) C RW DNACK NACK received after sending a data byte (write '1' to clear) Read: no overrun occured Read: overrun occured Read: error not present Read: error present Read: error not present Read: error present 4452_021 v1.3 438 Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled NotPresent Present NotPresent Present NotPresent Present 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled Enabled Enable or disable TWI Disable TWI Enable TWI 6.27.8.16 ENABLE Address offset: 0x500 Enable TWI Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 6.27.8.17 PSEL.SCL Address offset: 0x508 Pin select for SCL Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.27.8.18 PSEL.SDA Address offset: 0x50C Pin select for SDA Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.27.8.19 RXD Address offset: 0x518 RXD register ID A B C ID A B C 0 5 C 1 0 C 1 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

[0..31]

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 4452_021 v1.3 439 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RXD register Peripherals A A A A A A A A Reset 0x00000000 AccessField R RXD 6.27.8.20 TXD Address offset: 0x51C TXD register ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW TXD Value ID Value Description TXD register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A 6.27.8.21 FREQUENCY Address offset: 0x524 TWI frequency. Accuracy depends on the HFCLK source selected. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x04000000 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW FREQUENCY TWI master clock frequency K100 K250 K400 0x01980000 0x04000000 0x06680000 100 kbps 250 kbps 400 kbps (actual rate 410.256 kbps) 6.27.8.22 ADDRESS Address offset: 0x588 Address used in the TWI transfer Bit number ID ID A Reset 0x00000000 AccessField RW ADDRESS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Address used in the TWI transfer 4452_021 v1.3 440 Peripherals 6.27.9 Electrical specification 6.27.9.1 TWI interface electrical specifications Description Bit rates for TWI36 Min. 100 Typ. Max. Units 400 kbps Time from STARTRX/STARTTX task to transmission started 1.5 s 6.27.9.2 Two Wire Interface (TWI) timing specifications Description Min. Typ. Max. Units Symbol fTWI,SCL tTWI,START Symbol tTWI,SU_DAT tTWI,HD_DAT Data setup time before positive edge on SCL all modes Data hold time after negative edge on SCL all modes tTWI,HD_STA,100kbps TWI master hold time for START and repeated START tTWI,HD_STA,250kbps TWI master hold time for START and repeated START tTWI,HD_STA,400kbps TWI master hold time for START and repeated START tTWI,SU_STO,100kbps TWI master setup time from SCL high to STOP condition, 100 tTWI,SU_STO,250kbps TWI master setup time from SCL high to STOP condition, 250 tTWI,SU_STO,400kbps TWI master setup time from SCL high to STOP condition, 400 tTWI,BUF,100kbps TWI master bus free time between STOP and START tTWI,BUF,250kbps TWI master bus free time between STOP and START tTWI,BUF,400kbps TWI master bus free time between STOP and START condition, 100 kbps condition, 250kbps condition, 400 kbps kbps kbps kbps conditions, 100 kbps conditions, 250 kbps conditions, 400 kbps 300 500 10000 4000 2500 5000 2000 1250 5800 2700 2100 ns ns ns ns ns ns ns ns ns ns ns 6.28 TIMER Timer/counter The TIMER can operate in two modes: timer and counter. 36 High bit rates or stronger pull-ups may require GPIOs to be set as High Drive, see GPIO chapter for more details. 4452_021 v1.3 441

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Peripherals The timer/counter runs on the high-frequency clock source (HFCLK) and includes a four-bit (1/2X) prescaler that can divide the timer input clock from the HFCLK controller. Clock source selection between PCLK16M and PCLK1M is automatic according to TIMER base frequency set by the prescaler. The TIMER base frequency is always given as 16 MHz divided by the prescaler value. The PPI system allows a TIMER event to trigger a task of any other system peripheral of the device. The PPI system also enables the TIMER task/event features to generate periodic output and PWM signals to any GPIO. The number of input/outputs used at the same time is limited by the number of GPIOTE channels. The TIMER can operate in two modes, Timer mode and Counter mode. In both modes, the TIMER is started by triggering the START task, and stopped by triggering the STOP task. After the timer is stopped the timer can resume timing/counting by triggering the START task again. When timing/counting is resumed, the timer will continue from the value it had prior to being stopped. In Timer mode, the TIMER's internal Counter register is incremented by one for every tick of the timer frequency fTIMER as illustrated in Block schematic for timer/counter on page 442. The timer frequency is derived from PCLK16M as shown below, using the values specified in the PRESCALER register:

When fTIMER <= 1 MHz the TIMER will use PCLK1M instead of PCLK16M for reduced power consumption. In counter mode, the TIMER's internal Counter register is incremented by one each time the COUNT task is triggered, that is, the timer frequency and the prescaler are not utilized in counter mode. Similarly, the COUNT task has no effect in Timer mode. The TIMER's maximum value is configured by changing the bit-width of the timer in the BITMODE on page 447 register. PRESCALER on page 447 and the BITMODE on page 447 must only be updated when the timer is stopped. If these registers are updated while the TIMER is started then this may result in unpredictable behavior. When the timer is incremented beyond its maximum value the Counter register will overflow and the TIMER will automatically start over from zero. 4452_021 v1.3 442

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Peripherals The Counter register can be cleared, that is, its internal value set to zero explicitly, by triggering the CLEAR task. The TIMER implements multiple capture/compare registers. Independent of prescaler setting the accuracy of the TIMER is equivalent to one tick of the timer frequency fTIMER as illustrated in Block schematic for timer/counter on page 442. 6.28.1 Capture The TIMER implements one capture task for every available capture/compare register. Every time the CAPTURE[n] task is triggered, the Counter value is copied to the CC[n] register. 6.28.2 Compare The TIMER implements one COMPARE event for every available capture/compare register. A COMPARE event is generated when the Counter is incremented and then becomes equal to the value specified in one of the capture compare registers. When the Counter value becomes equal to the value specified in a capture compare register CC[n], the corresponding compare event COMPARE[n] is generated. BITMODE on page 447 specifies how many bits of the Counter register and the capture/compare register that are used when the comparison is performed. Other bits will be ignored. 6.28.3 Task delays After the TIMER is started, the CLEAR task, COUNT task and the STOP task will guarantee to take effect within one clock cycle of the PCLK16M. 6.28.4 Task priority If the START task and the STOP task are triggered at the same time, that is, within the same period of PCLK16M, the STOP task will be prioritized. 6.28.5 Registers Base address Peripheral 0x40008000 TIMER Instance TIMER0 Description Timer 0 Configuration This timer instance has 4 CC registers 0x40009000 TIMER TIMER1 Timer 1 This timer instance has 4 CC registers 0x4000A000 TIMER TIMER2 Timer 2 This timer instance has 4 CC registers 0x4001A000 TIMER TIMER3 Timer 3 This timer instance has 6 CC registers 0x4001B000 TIMER TIMER4 Timer 4 This timer instance has 6 CC registers

(CC[0..3])

(CC[0..3])

(CC[0..3])

(CC[0..5])

(CC[0..5]) Register TASKS_START TASKS_STOP TASKS_COUNT TASKS_CLEAR Offset 0x000 0x004 0x008 0x00C Description Start Timer Stop Timer Clear time Increment Timer (Counter mode only) 4452_021 v1.3 443

Peripherals Deprecated A A Register Offset Description TASKS_SHUTDOWN TASKS_CAPTURE[0]

TASKS_CAPTURE[1]

TASKS_CAPTURE[2]

TASKS_CAPTURE[3]

TASKS_CAPTURE[4]

TASKS_CAPTURE[5]

EVENTS_COMPARE[0]

EVENTS_COMPARE[1]

EVENTS_COMPARE[2]

EVENTS_COMPARE[3]

EVENTS_COMPARE[4]

EVENTS_COMPARE[5]

SHORTS INTENSET INTENCLR MODE BITMODE PRESCALER CC[0]

CC[1]

CC[2]

CC[3]

CC[4]

CC[5]

0x010 0x040 0x044 0x048 0x04C 0x050 0x054 0x140 0x144 0x148 0x14C 0x150 0x154 0x200 0x304 0x308 0x504 0x508 0x510 0x540 0x544 0x548 0x54C 0x550 0x554 Shut down timer Capture Timer value to CC[0] register Capture Timer value to CC[1] register Capture Timer value to CC[2] register Capture Timer value to CC[3] register Capture Timer value to CC[4] register Capture Timer value to CC[5] register Compare event on CC[0] match Compare event on CC[1] match Compare event on CC[2] match Compare event on CC[3] match Compare event on CC[4] match Compare event on CC[5] match Shortcuts between local events and tasks Enable interrupt Disable interrupt Timer mode selection Timer prescaler register Capture/Compare register 0 Capture/Compare register 1 Capture/Compare register 2 Capture/Compare register 3 Capture/Compare register 4 Capture/Compare register 5 Configure the number of bits used by the TIMER 6.28.5.1 TASKS_START Address offset: 0x000 Start Timer 6.28.5.2 TASKS_STOP Address offset: 0x004 Stop Timer ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value W TASKS_START Trigger 1 Description Start Timer Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value W TASKS_STOP Trigger 1 Description Stop Timer Trigger task 4452_021 v1.3 444

Peripherals A A A A 6.28.5.3 TASKS_COUNT Address offset: 0x008 Increment Timer (Counter mode only) 6.28.5.4 TASKS_CLEAR Address offset: 0x00C Clear time Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_COUNT Increment Timer (Counter mode only) Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value W TASKS_CLEAR Trigger 1 Description Clear time Trigger task 6.28.5.5 TASKS_SHUTDOWN ( Deprecated ) Address offset: 0x010 Shut down timer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_SHUTDOWN Trigger 1 Shut down timer Trigger task Deprecated 6.28.5.6 TASKS_CAPTURE[n] (n=0..5) Address offset: 0x040 + (n 0x4) Capture Timer value to CC[n] register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_CAPTURE Capture Timer value to CC[n] register Trigger 1 Trigger task 6.28.5.7 EVENTS_COMPARE[n] (n=0..5) Address offset: 0x140 + (n 0x4) 4452_021 v1.3 445 ID ID A ID ID A ID ID A ID ID A Compare event on CC[n] match Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_COMPARE Compare event on CC[n] match NotGenerated Generated Event not generated Event generated Peripherals A 6.28.5.8 SHORTS Address offset: 0x200 Shortcuts between local events and tasks 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-F RW COMPARE[i]_CLEAR Shortcut between event COMPARE[i] and task CLEAR Value ID Value Description G-L RW COMPARE[i]_STOP Shortcut between event COMPARE[i] and task STOP Disabled Enabled Disabled Enabled Disable shortcut Enable shortcut Disable shortcut Enable shortcut ID ID A Bit number ID Reset 0x00000000 ID AccessField

(i=0..5)

(i=0..5) 6.28.5.9 INTENSET Address offset: 0x304 Enable interrupt Bit number ID Reset 0x00000000 ID AccessField 6.28.5.10 INTENCLR Address offset: 0x308 Disable interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-F RW COMPARE[i] (i=0..5) Write '1' to enable interrupt for event COMPARE[i]

Value ID Value Description Set Disabled Enabled Enable Read: Disabled Read: Enabled 0 1 0 1 0 1 1 0 1 4452_021 v1.3 446 1 0 1 0 1 2 0 1 2 3 Bit number ID Reset 0x00000000 ID AccessField 6.28.5.11 MODE Address offset: 0x504 Timer mode selection Bit number ID ID A Reset 0x00000000 AccessField RW MODE Peripherals 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-F RW COMPARE[i] (i=0..5) Write '1' to disable interrupt for event COMPARE[i]

Value ID Value Description Clear Disabled Enabled Disable Read: Disabled Read: Enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Timer Counter Description Timer mode Select Timer mode Select Counter mode LowPowerCounter Select Low Power Counter mode A A Deprecated 6.28.5.12 BITMODE Address offset: 0x508 Configure the number of bits used by the TIMER Bit number ID ID A Reset 0x00000000 AccessField RW BITMODE 6.28.5.13 PRESCALER Address offset: 0x510 Timer prescaler register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value 16Bit 08Bit 24Bit 32Bit Description Timer bit width 16 bit timer bit width 8 bit timer bit width 24 bit timer bit width 32 bit timer bit width Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A Reset 0x00000004 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 AccessField Value ID RW PRESCALER Value

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Description Prescaler value ID ID A 6.28.5.14 CC[n] (n=0..5) Address offset: 0x540 + (n 0x4) 4452_021 v1.3 447 Peripherals Capture/Compare register n Bit number ID ID A Reset 0x00000000 AccessField RW CC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Capture/Compare value by the TIMER. Only the number of bits indicated by BITMODE will be used 6.29 TWIM I2C compatible two-wire interface master with EasyDMA TWI master with EasyDMA (TWIM) is a two-wire half-duplex master which can communicate with multiple slave devices connected to the same bus Listed here are the main features for TWIM:

I2C compatible Supported baud rates: 100, 250, 400 kbps Support for clock stretching (non I2C compliant) EasyDMA The two-wire interface can communicate with a bi-directional wired-AND bus with two lines (SCL, SDA). The protocol makes it possible to interconnect up to 127 individually addressable devices. TWIM is not compatible with CBUS. The GPIOs used for each two-wire interface line can be chosen from any GPIO on the device and are independently configurable. This enables great flexibility in device pinout and efficient use of board space and signal routing. 4452_021 v1.3 448 Peripherals A typical TWI setup consists of one master and one or more slaves. For an example, see A typical TWI setup comprising one master and three slaves on page 449. This TWIM is only able to operate as a single master on the TWI bus. Multi-master bus configuration is not supported. This TWI master supports clock stretching performed by the slaves. Note that the SCK pulse following a stretched clock cycle may be shorter than specified by the I2C specification. The TWI master is started by triggering the STARTTX or STARTRX tasks, and stopped by triggering the STOP task. The TWI master will generate a STOPPED event when it has stopped following a STOP task. The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI master has been resumed. After the TWI master is started, the STARTTX task or the STARTRX task should not be triggered again before the TWI master has stopped, i.e. following a LASTRX, LASTTX or STOPPED event. If a NACK is clocked in from the slave, the TWI master will generate an ERROR event. 6.29.1 EasyDMA The TWIM implements EasyDMA for accessing RAM without CPU involvement. The TWIM peripheral implements the following EasyDMA channels:

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Channel TXD RXD Type READER WRITER Register Cluster TXD RXD Peripherals For detailed information regarding the use of EasyDMA, see EasyDMA on page 44. The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/

TX transmission immediately after having received the RXSTARTED/TXSTARTED event. The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM. 6.29.2 Master write sequence A TWI master write sequence is started by triggering the STARTTX task. After the STARTTX task has been triggered, the TWI master will generate a start condition on the TWI bus, followed by clocking out the address and the READ/WRITE bit set to 0 (WRITE=0, READ=1). The address must match the address of the slave device that the master wants to write to. The READ/

WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) generated by the slave. After receiving the ACK bit, the TWI master will clock out the data bytes found in the transmit buffer located in RAM at the address specified in the TXD.PTR register. Each byte clocked out from the master will be followed by an ACK/NACK bit clocked in from the slave. A typical TWI master write sequence is illustrated in TWI master writing data to a slave on page 450. Occurrence 2 in the figure illustrates clock stretching performed by the TWI master following a SUSPEND task. A SUSPENDED event indicates that the SUSPEND task has taken effect; this event can be used to synchronize the software. The TWI master will generate a LASTTX event when it starts to transmit the last byte, this is illustrated in TWI master writing data to a slave on page 450 The TWI master is stopped by triggering the STOP task, this task should be triggered during the transmission of the last byte to secure that the TWI will stop as fast as possible after sending the last byte. It is safe to use the shortcut between LASTTX and STOP to accomplish this. 4452_021 v1.3 450

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Peripherals Note that the TWI master does not stop by itself when the whole RAM buffer has been sent, or when an error occurs. The STOP task must be issued, through the use of a local or PPI shortcut, or in software as part of the error handler. The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI master has been resumed. 6.29.3 Master read sequence A TWI master read sequence is started by triggering the STARTRX task. After the STARTRX task has been triggered the TWI master will generate a start condition on the TWI bus, followed by clocking out the address and the READ/WRITE bit set to 1 (WRITE = 0, READ = 1). The address must match the address of the slave device that the master wants to read from. The READ/WRITE bit is followed by an ACK/NACK bit

(ACK=0 or NACK = 1) generated by the slave. After having sent the ACK bit the TWI slave will send data to the master using the clock generated by the master. Data received will be stored in RAM at the address specified in the RXD.PTR register. The TWI master will generate an ACK after all but the last byte received from the slave. The TWI master will generate a NACK after the last byte received to indicate that the read sequence shall stop. A typical TWI master read sequence is illustrated in The TWI master reading data from a slave on page 452. Occurrence 2 in the figure illustrates clock stretching performed by the TWI master following a SUSPEND task. A SUSPENDED event indicates that the SUSPEND task has taken effect; this event can be used to synchronize the software. The TWI master will generate a LASTRX event when it is ready to receive the last byte, this is illustrated in The TWI master reading data from a slave on page 452. If RXD.MAXCNT > 1 the LASTRX event is generated after sending the ACK of the previously received byte. If RXD.MAXCNT = 1 the LASTRX event is generated after receiving the ACK following the address and READ bit. The TWI master is stopped by triggering the STOP task, this task must be triggered before the NACK bit is supposed to be transmitted. The STOP task can be triggered at any time during the reception of the last byte. It is safe to use the shortcut between LASTRX and STOP to accomplish this. Note that the TWI master does not stop by itself when the RAM buffer is full, or when an error occurs. The STOP task must be issued, through the use of a local or PPI shortcut, or in software as part of the error handler. The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI master has been resumed. 4452_021 v1.3 451 Peripherals 6.29.4 Master repeated start sequence A typical repeated start sequence is one in which the TWI master writes two bytes to the slave followed by reading four bytes from the slave. This example uses shortcuts to perform the simplest type of repeated start sequence, i.e. one write followed by one read. The same approach can be used to perform a repeated start sequence where the sequence is read followed by write. The figure A repeated start sequence, where the TWI master writes two bytes followed by reading 4 bytes from the slave on page 452 illustrates this:

If a more complex repeated start sequence is needed and the TWI firmware drive is serviced in a low priority interrupt it may be necessary to use the SUSPEND task and SUSPENDED event to guarantee that the correct tasks are generated at the correct time. This is illustrated in A double repeated start sequence using the SUSPEND task to secure safe operation in low priority interrupts on page 453. 4452_021 v1.3 452

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Peripherals 6.29.5 Low power When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral. The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent, software shall wait until the STOPPED event was received as a response before disabling the peripheral through the ENABLE register. 6.29.6 Master mode pin configuration The SCL and SDA signals associated with the TWI master are mapped to physical pins according to the configuration specified in the PSEL.SCL and PSEL.SDA registers respectively. The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI master is enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n]

register. PSEL.SCL, PSEL.SDA must only be configured when the TWI master is disabled. To secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and when the TWI master is disabled, these pins must be configured in the GPIO peripheral as described in GPIO configuration before enabling peripheral on page 453. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. TWI master signal TWI master pin Direction SCL SDA As specified in PSEL.SCL As specified in PSEL.SDA Input Input Output value Not applicable Not applicable Drive strength S0D1 S0D1 6.29.7 Registers Base address Peripheral Instance Description Configuration 0x40003000 0x40004000 TWIM TWIM TWIM0 TWIM1 Two-wire interface master 0 Two-wire interface master 1 4452_021 v1.3 453

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Peripherals Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now Stop TWI transaction. Must be issued while the TWI master is not suspended. Register TASKS_STARTRX TASKS_STARTTX TASKS_STOP TASKS_SUSPEND TASKS_RESUME EVENTS_STOPPED EVENTS_ERROR EVENTS_SUSPENDED EVENTS_RXSTARTED EVENTS_TXSTARTED EVENTS_LASTRX EVENTS_LASTTX SHORTS INTEN INTENSET INTENCLR ERRORSRC ENABLE PSEL.SCL PSEL.SDA FREQUENCY RXD.PTR RXD.MAXCNT RXD.AMOUNT RXD.LIST TXD.PTR TXD.MAXCNT TXD.AMOUNT TXD.LIST ADDRESS Offset 0x000 0x008 0x014 0x01C 0x020 0x104 0x124 0x148 0x14C 0x150 0x15C 0x160 0x200 0x300 0x304 0x308 0x4C4 0x500 0x508 0x50C 0x524 0x534 0x538 0x53C 0x540 0x544 0x548 0x54C 0x550 0x588 Description Start TWI receive sequence Start TWI transmit sequence Suspend TWI transaction Resume TWI transaction TWI stopped TWI error suspended. Receive sequence started Transmit sequence started Byte boundary, starting to receive the last byte Byte boundary, starting to transmit the last byte Shortcuts between local events and tasks Enable or disable interrupt Enable interrupt Disable interrupt Error source Enable TWIM Pin select for SCL signal Pin select for SDA signal Data pointer EasyDMA list type Data pointer TWI frequency. Accuracy depends on the HFCLK source selected. Maximum number of bytes in receive buffer Number of bytes transferred in the last transaction Maximum number of bytes in transmit buffer Number of bytes transferred in the last transaction EasyDMA list type Address used in the TWI transfer 6.29.7.1 TASKS_STARTRX Address offset: 0x000 Start TWI receive sequence 6.29.7.2 TASKS_STARTTX Address offset: 0x008 Start TWI transmit sequence Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTRX Start TWI receive sequence Trigger 1 Trigger task ID ID A 4452_021 v1.3 454

Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTTX Start TWI transmit sequence Trigger 1 Trigger task 6.29.7.3 TASKS_STOP Address offset: 0x014 Stop TWI transaction. Must be issued while the TWI master is not suspended. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Stop TWI transaction. Must be issued while the TWI master Trigger 1 is not suspended. Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_SUSPEND Suspend TWI transaction Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_RESUME Resume TWI transaction Trigger 1 Trigger task ID ID A ID ID A ID ID A ID ID A 6.29.7.4 TASKS_SUSPEND Address offset: 0x01C Suspend TWI transaction 6.29.7.5 TASKS_RESUME Address offset: 0x020 Resume TWI transaction 6.29.7.6 EVENTS_STOPPED Address offset: 0x104 TWI stopped A A A A 4452_021 v1.3 455 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value RW EVENTS_STOPPED NotGenerated Generated Description TWI stopped Event not generated Event generated 6.29.7.7 EVENTS_ERROR Address offset: 0x124 TWI error Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value RW EVENTS_ERROR NotGenerated Generated Description TWI error Event not generated Event generated 6.29.7.8 EVENTS_SUSPENDED Address offset: 0x148 Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_SUSPENDED Last byte has been sent out after the SUSPEND task has NotGenerated Generated been issued, TWI traffic is now suspended. Event not generated Event generated 6.29.7.9 EVENTS_RXSTARTED Address offset: 0x14C Receive sequence started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RXSTARTED NotGenerated Generated Receive sequence started Event not generated Event generated ID ID A ID ID A ID ID A ID ID A A A A A 0 1 0 1 0 1 0 1 6.29.7.10 EVENTS_TXSTARTED Address offset: 0x150 Transmit sequence started 4452_021 v1.3 456 ID ID A ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description Peripherals RW EVENTS_TXSTARTED NotGenerated Generated 6.29.7.11 EVENTS_LASTRX Address offset: 0x15C Byte boundary, starting to receive the last byte Transmit sequence started Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_LASTRX Byte boundary, starting to receive the last byte NotGenerated Generated Event not generated Event generated 6.29.7.12 EVENTS_LASTTX Address offset: 0x160 Byte boundary, starting to transmit the last byte Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_LASTTX Byte boundary, starting to transmit the last byte NotGenerated Generated Event not generated Event generated A A A 6.29.7.13 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW LASTTX_STARTRX Shortcut between event LASTTX and task STARTRX B RW LASTTX_SUSPEND Shortcut between event LASTTX and task SUSPEND C RW LASTTX_STOP Shortcut between event LASTTX and task STOP Disabled Enabled Disabled Enabled Disabled Enabled Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut 4452_021 v1.3 457 0 1 0 1 0 1 0 1 0 1 0 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID D Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW LASTRX_STARTTX Shortcut between event LASTRX and task STARTTX Peripherals F E D C B A E RW LASTRX_SUSPEND Shortcut between event LASTRX and task SUSPEND F RW LASTRX_STOP Shortcut between event LASTRX and task STOP 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled 6.29.7.14 INTEN Address offset: 0x300 Enable or disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW STOPPED I J RW LASTRX RW LASTTX 6.29.7.15 INTENSET Address offset: 0x304 Enable interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 J I H G F D A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event STOPPED D RW ERROR Enable or disable interrupt for event ERROR F RW SUSPENDED Enable or disable interrupt for event SUSPENDED G RW RXSTARTED Enable or disable interrupt for event RXSTARTED H RW TXSTARTED Enable or disable interrupt for event TXSTARTED Enable or disable interrupt for event LASTRX Enable or disable interrupt for event LASTTX Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable 4452_021 v1.3 458 Bit number ID ID A Reset 0x00000000 AccessField RW STOPPED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 J I H G F D A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event STOPPED Peripherals D RW ERROR Write '1' to enable interrupt for event ERROR F RW SUSPENDED Write '1' to enable interrupt for event SUSPENDED G RW RXSTARTED Write '1' to enable interrupt for event RXSTARTED H RW TXSTARTED Write '1' to enable interrupt for event TXSTARTED RW LASTRX Write '1' to enable interrupt for event LASTRX RW LASTTX Write '1' to enable interrupt for event LASTTX Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 I J 6.29.7.16 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW STOPPED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 J I H G F D A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event STOPPED D RW ERROR Write '1' to disable interrupt for event ERROR F RW SUSPENDED Write '1' to disable interrupt for event SUSPENDED 4452_021 v1.3 459 Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Peripherals Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 J I H G F D A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value G RW RXSTARTED Write '1' to disable interrupt for event RXSTARTED H RW TXSTARTED Write '1' to disable interrupt for event TXSTARTED RW LASTRX Write '1' to disable interrupt for event LASTRX RW LASTTX Write '1' to disable interrupt for event LASTTX Value ID Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled NotReceived Received NotReceived Received NotReceived Received I J 6.29.7.17 ERRORSRC Address offset: 0x4C4 Error source Bit number ID ID A Reset 0x00000000 AccessField RW OVERRUN 6.29.7.18 ENABLE Address offset: 0x500 Enable TWIM 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 Description Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Description Overrun error Error did not occur Error occurred Error did not occur Error occurred Error did not occur Error occurred 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value A new byte was received before previous byte got transferred into RXD buffer. (Previous data is lost) B RW ANACK NACK received after sending the address (write '1' to clear) C RW DNACK NACK received after sending a data byte (write '1' to clear) 4452_021 v1.3 460 0 6 C 1 0 C 1 0 Peripherals A A A A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled Enabled Enable or disable TWIM Disable TWIM Enable TWIM Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 6.29.7.19 PSEL.SCL Address offset: 0x508 Pin select for SCL signal Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.29.7.20 PSEL.SDA Address offset: 0x50C Pin select for SDA signal ID A B C ID A B C ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 6.29.7.21 FREQUENCY Address offset: 0x524 TWI frequency. Accuracy depends on the HFCLK source selected. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x04000000 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW FREQUENCY TWI master clock frequency K100 K250 K400 0x01980000 0x04000000 0x06400000 100 kbps 250 kbps 400 kbps 4452_021 v1.3 461 Peripherals 6.29.7.22 RXD.PTR Address offset: 0x534 Data pointer Bit number ID ID A Reset 0x00000000 AccessField RW PTR 6.29.7.23 RXD.MAXCNT Address offset: 0x538 Maximum number of bytes in receive buffer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Data pointer Note: See the memory chapter for details about which memories are available for EasyDMA. ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW MAXCNT Value ID Value Description

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Maximum number of bytes in receive buffer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A 6.29.7.24 RXD.AMOUNT Address offset: 0x53C Number of bytes transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description

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Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. Reset 0x00000000 AccessField R AMOUNT 6.29.7.25 RXD.LIST Address offset: 0x540 EasyDMA list type Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A Reset 0x00000000 AccessField RW LIST Value ID Value Disabled ArrayList 0 1 Description List type Disable EasyDMA list Use array list 4452_021 v1.3 462 Peripherals 6.29.7.26 TXD.PTR Address offset: 0x544 Data pointer Bit number ID ID A Reset 0x00000000 AccessField RW PTR 6.29.7.27 TXD.MAXCNT Address offset: 0x548 Maximum number of bytes in transmit buffer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Data pointer Note: See the memory chapter for details about which memories are available for EasyDMA. ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW MAXCNT Value ID Value Description

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Maximum number of bytes in transmit buffer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A 6.29.7.28 TXD.AMOUNT Address offset: 0x54C Number of bytes transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description

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Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. Reset 0x00000000 AccessField R AMOUNT 6.29.7.29 TXD.LIST Address offset: 0x550 EasyDMA list type Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A Reset 0x00000000 AccessField RW LIST Value ID Value Disabled ArrayList 0 1 Description List type Disable EasyDMA list Use array list 4452_021 v1.3 463 Peripherals 6.29.7.30 ADDRESS Address offset: 0x588 Address used in the TWI transfer Bit number ID ID A Reset 0x00000000 AccessField RW ADDRESS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Address used in the TWI transfer 6.29.8 Electrical specification 6.29.8.1 TWIM interface electrical specifications Symbol fTWIM,SCL Description Bit rates for TWIM37 Min. 100 Typ. Max. Units 400 kbps tTWIM,START Time from STARTRX/STARTTX task to transmission started 1.5 s 6.29.8.2 Two Wire Interface Master (TWIM) timing specifications Symbol Description Min. Typ. Max. Units tTWIM,SU_DAT tTWIM,HD_DAT Data setup time before positive edge on SCL all modes Data hold time after negative edge on SCL all modes tTWIM,HD_STA,100kbps TWIM master hold time for START and repeated START tTWIM,HD_STA,250kbps TWIM master hold time for START and repeated START tTWIM,HD_STA,400kbps TWIM master hold time for START and repeated START tTWIM,SU_STO,100kbps TWIM master setup time from SCL high to STOP condition, tTWIM,SU_STO,250kbps TWIM master setup time from SCL high to STOP condition, tTWIM,SU_STO,400kbps TWIM master setup time from SCL high to STOP condition, tTWIM,BUF,100kbps TWIM master bus free time between STOP and START tTWIM,BUF,250kbps TWIM master bus free time between STOP and START tTWIM,BUF,400kbps TWIM master bus free time between STOP and START condition, 100 kbps condition, 250kbps condition, 400 kbps 100 kbps 250 kbps 400 kbps conditions, 100 kbps conditions, 250 kbps conditions, 400 kbps 300 500 9937.5 3937.5 2437.5 5000 2000 1250 5800 2700 2100 ns ns ns ns ns ns ns ns ns ns ns 37 High bit rates or stronger pull-ups may require GPIOs to be set as High Drive, see GPIO chapter for more details. 4452_021 v1.3 464 Peripherals 6.29.9 Pullup resistor Max 700 px 100 kbps 400 kbps 0 100 200 300 400 500 cap [pF]

R [k]

30 25 20 15 10 5 0 M a x 7 5 0 p x The I2C specification allows a line capacitance of 400 pF at most. The value of internal pullup resistor (RPU) for nRF52833 can be found in GPIO General purpose input/output on page 138. 6.30 TWIS I2C compatible two-wire interface slave with EasyDMA TWI slave with EasyDMA (TWIS) is compatible with I2C operating at 100 kHz and 400 kHz. The TWI transmitter and receiver implement EasyDMA. 4452_021 v1.3 465

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Peripherals A typical TWI setup consists of one master and one or more slaves. For an example, see the following figure. TWIS is only able to operate with a single master on the TWI bus. The following figure shows the TWI slave state machine. 4452_021 v1.3 466

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Peripherals Unprepare TX Unprepare RX TX prepared) RX prepared)

! Unprepare TX

nprepare RX The following table contains descriptions of the symbols used in the state machine. Symbol ENABLE PREPARETX STOP PREPARERX STOPPED RXSTARTED TXSTARTED Type Register Task Task Task Event Event Event Description The TWI slave has been enabled via the ENABLE register. The TASKS_PREPARETX task has been triggered. The TASKS_STOP task has been triggered. The TASKS_PREPARERX task has been triggered. The EVENTS_STOPPED event was generated. The EVENTS_RXSTARTED event was generated. The EVENTS_TXSTARTED event was generated. TX prepared Internal Internal flag indicating that a TASKS_PREPARETX task has been triggered. This flag is not visible to the RX prepared Internal Internal flag indicating that a TASKS_PREPARERX task has been triggered. This flag is not visible to the user. user. Unprepare TX Unprepare RX Internal Internal Clears the internal 'TX prepared' flag until next TASKS_PREPARETX task. Clears the internal 'RX prepared' flag until next TASKS_PREPARERX task. Stop condition TWI protocol A TWI stop condition was detected. Restart condition TWI protocol A TWI restart condition was detected. The TWI slave can perform clock stretching, with the premise that the master is able to support it. 4452_021 v1.3 467

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Peripherals The TWI slave operates in a low power mode while waiting for a TWI master to initiate a transfer. As long as the TWI slave is not addressed, it will remain in this low power mode. To secure correct behavior of the TWI slave, PSEL.SCL, PSEL.SDA, CONFIG, and the ADDRESS[n] registers must be configured prior to enabling the TWI slave through the ENABLE register. Similarly, changing these settings must be performed while the TWI slave is disabled. Failing to do so may result in unpredictable behavior. 6.30.1 EasyDMA The TWIS implements EasyDMA for accessing RAM without CPU involvement. The following table shows the Easy DMA channels that the TWIS peripheral implements. Channel TXD RXD Type READER WRITER Register Cluster TXD RXD For detailed information regarding the use of EasyDMA, see EasyDMA on page 44. The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM. 6.30.2 TWI slave responding to a read command Before the TWI slave can respond to a read command, the TWI slave must be configured correctly and enabled via the ENABLE register. When enabled, the TWI slave will be in its IDLE state. A read command is started when the TWI master generates a start condition on the TWI bus, followed by clocking out the address and the READ/WRITE bit set to 1 (WRITE=0, READ=1). The READ/WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the TWI slave. The TWI slave is able to listen for up to two addresses at the same time. This is configured in the ADDRESS registers and the CONFIG register. The TWI slave will only acknowledge (ACK) the read command if the address presented by the master matches one of the addresses the slave is configured to listen for. The TWI slave will generate a READ event when it acknowledges the read command. The TWI slave is only able to detect a read command from the IDLE state. The TWI slave will set an internal 'TX prepared' flag when the PREPARETX task is triggered. When the read command is received, the TWI slave will enter the TX state if the internal 'TX prepared' flag is set. If the internal 'TX prepared' flag is not set when the read command is received, the TWI slave will stretch the master's clock until the PREPARETX task is triggered and the internal 'TX prepared' flag is set. The TWI slave will generate the TXSTARTED event and clear the 'TX prepared' flag ('unprepare TX') when it enters the TX state. In this state the TWI slave will send the data bytes found in the transmit buffer to the master using the master's clock. The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the TX state. The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event will be generated when the transaction has stopped. The TWI slave will clear the 'TX prepared' flag

('unprepare TX') and go back to the IDLE state when it has stopped. 4452_021 v1.3 468

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Peripherals The transmit buffer is located in RAM at the address specified in the TXD.PTR register. The TWI slave will only be able to send TXD.MAXCNT bytes from the transmit buffer for each transaction. If the TWI master forces the slave to send more than TXD.MAXCNT bytes, the slave will send the byte specified in the ORC register to the master instead. If this happens, an ERROR event will be generated. The EasyDMA configuration registers, see TXD.PTR etc., are latched when the TXSTARTED event is generated. The TWI slave can be forced to stop by triggering the STOP task. A STOPPED event will be generated when the TWI slave has stopped. The TWI slave will clear the 'TX prepared' flag and go back to the IDLE state when it has stopped, see also Terminating an ongoing TWI transaction on page 471. Each byte sent from the slave will be followed by an ACK/NACK bit sent from the master. The TWI master will generate a NACK following the last byte that it wants to receive to tell the slave to release the bus so that the TWI master can generate the stop condition. The TXD.AMOUNT register can be queried after a transaction to see how many bytes were sent. A typical TWI slave read command response is shown in the following figure. Occurrence 2 in the figure illustrates clock stretching performed by the TWI slave following a SUSPEND task. 4 6.30.3 TWI slave responding to a write command Before the TWI slave can respond to a write command, the TWI slave must be configured correctly and enabled via the ENABLE register. When enabled, the TWI slave will be in its IDLE state. A write command is started when the TWI master generates a start condition on the TWI bus, followed by clocking out the address and the READ/WRITE bit set to 0 (WRITE=0, READ=1). The READ/WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the slave. The TWI slave is able to listen for up to two addresses at the same time. This is configured in the ADDRESS registers and the CONFIG register. The TWI slave will only acknowledge (ACK) the write command if the address presented by the master matches one of the addresses the slave is configured to listen for. The TWI slave will generate a WRITE event if it acknowledges the write command. The TWI slave is only able to detect a write command from the IDLE state. The TWI slave will set an internal 'RX prepared' flag when the PREPARERX task is triggered. When the write command is received, the TWI slave will enter the RX state if the internal 'RX prepared'

flag is set. 4452_021 v1.3 469

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Peripherals If the internal 'RX prepared' flag is not set when the write command is received, the TWI slave will stretch the master's clock until the PREPARERX task is triggered and the internal 'RX prepared' flag is set. The TWI slave will generate the RXSTARTED event and clear the internal 'RX prepared' flag ('unprepare RX') when it enters the RX state. In this state, the TWI slave will be able to receive the bytes sent by the TWI master. The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the RX state. The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event will be generated when the transaction has stopped. The TWI slave will clear the internal 'RX prepared' flag

('unprepare RX') and go back to the IDLE state when it has stopped. The receive buffer is located in RAM at the address specified in the RXD.PTR register. The TWI slave will only be able to receive as many bytes as specified in the RXD.MAXCNT register. If the TWI master tries to send more bytes to the slave than it can receive, the extra bytes are discarded and NACKed by the slave. If this happens, an ERROR event will be generated. The EasyDMA configuration registers, see RXD.PTR etc., are latched when the RXSTARTED event is generated. The TWI slave can be forced to stop by triggering the STOP task. A STOPPED event will be generated when the TWI slave has stopped. The TWI slave will clear the internal 'RX prepared' flag and go back to the IDLE state when it has stopped, see also Terminating an ongoing TWI transaction on page 471. The TWI slave will generate an ACK after every byte received from the master. The RXD.AMOUNT register can be queried after a transaction to see how many bytes were received. A typical TWI slave write command response is show in the following figure. Occurrence 2 in the figure illustrates clock stretching performed by the TWI slave following a SUSPEND task. 6.30.4 Master repeated start sequence An example of a repeated start sequence is one in which the TWI master writes two bytes to the slave followed by reading four bytes from the slave. This is illustrated in the following figure. In this example, the receiver does not know what the master wants to read in advance. This information is in the first two received bytes of the write in the repeated start sequence. To guarantee that the CPU is able to process the received data before the TWI slave starts to reply to the read command, the SUSPEND task is triggered via a shortcut from the READ event generated when the read command is received. When 4452_021 v1.3 470

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the CPU has processed the incoming data and prepared the correct data response, the CPU will resume the transaction by triggering the RESUME task. Peripherals 6.30.5 Terminating an ongoing TWI transaction In some situations, e.g. if the external TWI master is not responding correctly, it may be required to terminate an ongoing transaction. This can be achieved by triggering the STOP task. In this situation, a STOPPED event will be generated when the TWI has stopped independent of whether or not a STOP condition has been generated on the TWI bus. The TWI slave will release the bus when it has stopped and go back to its IDLE state. 6.30.6 Low power When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral. The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent, software shall wait until the STOPPED event was received as a response before disabling the peripheral through the ENABLE register. 6.30.7 Slave mode pin configuration The SCL and SDA signals associated with the TWI slave are mapped to physical pins according to the configuration specified in the PSEL.SCL and PSEL.SDA registers respectively. The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI slave is enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n]

register. PSEL.SCL and PSEL.SDA must only be configured when the TWI slave is disabled. To secure correct signal levels on the pins used by the TWI slave when the system is in OFF mode, and when the TWI slave is disabled, these pins must be configured in the GPIO peripheral as described in the following table. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. TWI slave signal TWI slave pin Direction SCL SDA As specified in PSEL.SCL As specified in PSEL.SDA Input Input Output value Not applicable Not applicable Drive strength S0D1 S0D1 4452_021 v1.3 471

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6.30.8 Registers Base address Peripheral Instance Description Configuration 0x40003000 0x40004000 TWIS TWIS TWIS0 TWIS1 Two-wire interface slave 0 Two-wire interface slave 1 Peripherals Prepare the TWI slave to respond to a write command Prepare the TWI slave to respond to a read command Description Stop TWI transaction Suspend TWI transaction Resume TWI transaction TWI stopped TWI error Receive sequence started Transmit sequence started Write command received Read command received Enable interrupt Disable interrupt Error source Enable TWIS Pin select for SCL signal Pin select for SDA signal RXD Data pointer EasyDMA list type TXD Data pointer EasyDMA list type TWI slave address 0 TWI slave address 1 Shortcuts between local events and tasks Enable or disable interrupt Status register indicating which address had a match Maximum number of bytes in RXD buffer Number of bytes transferred in the last RXD transaction Maximum number of bytes in TXD buffer Number of bytes transferred in the last TXD transaction Register TASKS_STOP TASKS_SUSPEND TASKS_RESUME TASKS_PREPARERX TASKS_PREPARETX EVENTS_STOPPED EVENTS_ERROR EVENTS_RXSTARTED EVENTS_TXSTARTED EVENTS_WRITE EVENTS_READ SHORTS INTEN INTENSET INTENCLR ERRORSRC MATCH ENABLE PSEL.SCL PSEL.SDA RXD.PTR RXD.MAXCNT RXD.AMOUNT RXD.LIST TXD.PTR TXD.MAXCNT TXD.AMOUNT TXD.LIST ADDRESS[0]

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CONFIG ORC Offset 0x014 0x01C 0x020 0x030 0x034 0x104 0x124 0x14C 0x150 0x164 0x168 0x200 0x300 0x304 0x308 0x4D0 0x4D4 0x500 0x508 0x50C 0x534 0x538 0x53C 0x540 0x544 0x548 0x54C 0x550 0x588 0x58C 0x594 0x5C0 6.30.8.1 TASKS_STOP Address offset: 0x014 Stop TWI transaction 4452_021 v1.3 472 Configuration register for the address match mechanism Over-read character. Character sent out in case of an over-read of the transmit buffer.

ID ID A ID ID A ID ID A ID ID A Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOP Stop TWI transaction Trigger 1 Trigger task 6.30.8.2 TASKS_SUSPEND Address offset: 0x01C Suspend TWI transaction 6.30.8.3 TASKS_RESUME Address offset: 0x020 Resume TWI transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_SUSPEND Suspend TWI transaction Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_RESUME Resume TWI transaction Trigger 1 Trigger task 6.30.8.4 TASKS_PREPARERX Address offset: 0x030 Prepare the TWI slave to respond to a write command Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_PREPARERX Prepare the TWI slave to respond to a write command Trigger 1 Trigger task 6.30.8.5 TASKS_PREPARETX Address offset: 0x034 Prepare the TWI slave to respond to a read command A A A A 4452_021 v1.3 473 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_PREPARETX Prepare the TWI slave to respond to a read command Trigger 1 Trigger task 6.30.8.6 EVENTS_STOPPED Address offset: 0x104 TWI stopped 6.30.8.7 EVENTS_ERROR Address offset: 0x124 TWI error Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value RW EVENTS_STOPPED NotGenerated Generated Description TWI stopped Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value RW EVENTS_ERROR NotGenerated Generated Description TWI error Event not generated Event generated 6.30.8.8 EVENTS_RXSTARTED Address offset: 0x14C Receive sequence started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RXSTARTED NotGenerated Generated Receive sequence started Event not generated Event generated ID ID A ID ID A ID ID A ID ID A A A A A 0 1 0 1 0 1 6.30.8.9 EVENTS_TXSTARTED Address offset: 0x150 Transmit sequence started 4452_021 v1.3 474 A A A ID ID A ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description Peripherals RW EVENTS_TXSTARTED NotGenerated Generated 6.30.8.10 EVENTS_WRITE Address offset: 0x164 Write command received RW EVENTS_WRITE NotGenerated Generated 6.30.8.11 EVENTS_READ Address offset: 0x168 Read command received Transmit sequence started Event not generated Event generated Write command received Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_READ NotGenerated Generated Read command received Event not generated Event generated 6.30.8.12 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW WRITE_SUSPEND Shortcut between event WRITE and task SUSPEND B RW READ_SUSPEND Shortcut between event READ and task SUSPEND Disabled Enabled Disabled Enabled Disable shortcut Enable shortcut Disable shortcut Enable shortcut 4452_021 v1.3 475 0 1 0 1 0 1 0 1 0 1 Peripherals 6.30.8.13 INTEN Address offset: 0x300 Enable or disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW STOPPED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H G F E B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event STOPPED B RW ERROR Enable or disable interrupt for event ERROR E RW RXSTARTED Enable or disable interrupt for event RXSTARTED F RW TXSTARTED Enable or disable interrupt for event TXSTARTED G RW WRITE Enable or disable interrupt for event WRITE H RW READ Enable or disable interrupt for event READ 6.30.8.14 INTENSET Address offset: 0x304 Enable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW STOPPED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H G F E B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event STOPPED B RW ERROR Write '1' to enable interrupt for event ERROR E RW RXSTARTED Write '1' to enable interrupt for event RXSTARTED F RW TXSTARTED Write '1' to enable interrupt for event TXSTARTED 4452_021 v1.3 476 Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Bit number ID ID G Reset 0x00000000 AccessField RW WRITE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H G F E B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event WRITE Peripherals H RW READ Write '1' to enable interrupt for event READ 6.30.8.15 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW STOPPED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H G F E B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event STOPPED B RW ERROR Write '1' to disable interrupt for event ERROR E RW RXSTARTED Write '1' to disable interrupt for event RXSTARTED F RW TXSTARTED Write '1' to disable interrupt for event TXSTARTED G RW WRITE Write '1' to disable interrupt for event WRITE H RW READ Write '1' to disable interrupt for event READ Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled 6.30.8.16 ERRORSRC Address offset: 0x4D0 Error source 4452_021 v1.3 477 Peripherals C B A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW OVERFLOW RX buffer overflow detected, and prevented B RW DNACK NACK sent after receiving a data byte C RW OVERREAD TX buffer over-read detected, and prevented NotDetected Detected NotReceived Received NotDetected Detected 0 1 0 1 0 1 Error did not occur Error occurred Error did not occur Error occurred Error did not occur Error occurred 6.30.8.17 MATCH Address offset: 0x4D4 Status register indicating which address had a match Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A Value ID Description Value

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Indication of which address in {ADDRESS} that matched the incoming address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A Value ID Value Description Disabled Enabled 0 9 Enable or disable TWIS Disable TWIS Enable TWIS ID ID A ID ID A ID ID A Reset 0x00000000 AccessField R MATCH 6.30.8.18 ENABLE Address offset: 0x500 Enable TWIS Reset 0x00000000 AccessField RW ENABLE 6.30.8.19 PSEL.SCL Address offset: 0x508 Pin select for SCL signal 4452_021 v1.3 478 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Peripherals B A A A A A Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect C 1 0 C 1 0 Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.30.8.20 PSEL.SDA Address offset: 0x50C Pin select for SDA signal Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.30.8.21 RXD.PTR Address offset: 0x534 RXD Data pointer ID A B C ID A B C ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW PTR Value ID Value Description RXD Data pointer A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 See the memory chapter for details about which memories are available for EasyDMA. 6.30.8.22 RXD.MAXCNT Address offset: 0x538 Maximum number of bytes in RXD buffer Bit number ID ID A Reset 0x00000000 AccessField RW MAXCNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description

[0..0xFFFF]

Maximum number of bytes in RXD buffer 6.30.8.23 RXD.AMOUNT Address offset: 0x53C 4452_021 v1.3 479 Peripherals Number of bytes transferred in the last RXD transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description

[0..0xFFFF]

Number of bytes transferred in the last RXD transaction Reset 0x00000000 AccessField R AMOUNT 6.30.8.24 RXD.LIST Address offset: 0x540 EasyDMA list type Reset 0x00000000 AccessField RW LIST 6.30.8.25 TXD.PTR Address offset: 0x544 TXD Data pointer ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A Value ID Value Disabled ArrayList 0 1 Description List type Disable EasyDMA list Use array list Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW PTR Value ID Value Description TXD Data pointer A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 See the memory chapter for details about which memories are available for EasyDMA. 6.30.8.26 TXD.MAXCNT Address offset: 0x548 Maximum number of bytes in TXD buffer Bit number ID ID A Reset 0x00000000 AccessField RW MAXCNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description

[0..0xFFFF]

Maximum number of bytes in TXD buffer 6.30.8.27 TXD.AMOUNT Address offset: 0x54C Number of bytes transferred in the last TXD transaction 4452_021 v1.3 480 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description

[0..0xFFFF]

Number of bytes transferred in the last TXD transaction Peripherals Reset 0x00000000 AccessField R AMOUNT 6.30.8.28 TXD.LIST Address offset: 0x550 EasyDMA list type ID ID A ID ID A Bit number ID ID A Reset 0x00000000 AccessField RW ADDRESS 6.30.8.30 CONFIG Address offset: 0x594 Bit number ID Reset 0x00000001 ID AccessField 6.30.8.31 ORC Address offset: 0x5C0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A Reset 0x00000000 AccessField RW LIST Value ID Value Disabled ArrayList 0 1 Description List type Disable EasyDMA list Use array list 6.30.8.29 ADDRESS[n] (n=0..1) Address offset: 0x588 + (n 0x4) TWI slave address n 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description TWI slave address Configuration register for the address match mechanism 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A-B RW ADDRESS[i] (i=0..1) Enable or disable address matching on ADDRESS[i]

Value ID Value Description Disabled Enabled 0 1 Disabled Enabled Over-read character. Character sent out in case of an over-read of the transmit buffer. 4452_021 v1.3 481 Bit number ID ID A Reset 0x00000000 AccessField RW ORC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Over-read character. Character sent out in case of an over-

read of the transmit buffer. Peripherals A A A A A A A A Time from PREPARERX/PREPARETX task to ready to receive/

1.5 Typ. Max. Units 400 kbps 6.30.9 Electrical specification 6.30.9.1 TWIS slave timing specifications Symbol fTWIS,SCL tTWIS,START tTWIS,SU_DAT tTWIS,HD_DAT Description Bit rates for TWIS38 transmit SCL low), 100 kbps SCL low), 400 kbps kbps kbps conditions, 100 kbps conditions, 400 kbps Data setup time before positive edge on SCL all modes Data hold time after negative edge on SCL all modes tTWIS,HD_STA,100kbps TWI slave hold time from for START condition (SDA low to tTWIS,HD_STA,400kbps TWI slave hold time from for START condition (SDA low to tTWIS,SU_STO,100kbps TWI slave setup time from SCL high to STOP condition, 100 tTWIS,SU_STO,400kbps TWI slave setup time from SCL high to STOP condition, 400 tTWIS,BUF,100kbps TWI slave bus free time between STOP and START tTWIS,BUF,400kbps TWI slave bus free time between STOP and START Min. 100 300 500 5200 1300 5200 1300 4700 1300 s ns ns ns ns ns ns ns ns 6.31 UART Universal asynchronous receiver/

transmitter 38 High bit rates or stronger pull-ups may require GPIOs to be set as High Drive, see GPIO chapter for more details. 4452_021 v1.3 482

C

Peripherals 6.31.1 Functional description Listed here are the main features of UART. The UART implements support for the following features:

Full-duplex operation Automatic flow control Parity checking and generation for the 9th data bit As illustrated in UART configuration on page 483, the UART uses the TXD and RXD registers directly to transmit and receive data. The UART uses one stop bit. Note: The external crystal oscillator must be enabled to obtain sufficient clock accuracy for stable communication. See CLOCK Clock control on page 80 for more information. 6.31.2 Pin configuration The different signals RXD, CTS (Clear To Send, active low), RTS (Request To Send, active low), and TXD associated with the UART are mapped to physical pins according to the configuration specified in the PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers respectively. If the CONNECT field of a PSEL.xxx register is set to Disconnected, the associated UART signal will not be connected to any physical pin. The PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers and their configurations are only used as long as the UART is enabled, and retained only for the duration the device is in ON mode. PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD must only be configured when the UART is disabled. To secure correct signal levels on the pins by the UART when the system is in OFF mode, the pins must be configured in the GPIO peripheral as described in Pin configuration on page 483. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. UART pin RXD CTS RTS TXD Direction Input Input Output Output Output value Not applicable Not applicable 1 1 4452_021 v1.3 483

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Peripherals 6.31.3 Shared resources The UART shares registers and resources with other peripherals that have the same ID as the UART. All peripherals with the same ID as the UART must be disabled before configuring and using the UART. Disabling a peripheral that has the same ID as the UART will not reset any of the registers that are shared with the UART. It is therefore important to configure all relevant UART registers explicitly to ensure that it operates correctly. See Instantiation on page 22 for details on peripherals and their IDs. 6.31.4 Transmission A UART transmission sequence is started by triggering the STARTTX task. Bytes are transmitted by writing to the TXD register. When a byte has been successfully transmitted, the UART will generate a TXDRDY event after which a new byte can be written to the TXD register. A UART transmission sequence is stopped immediately by triggering the STOPTX task. If flow control is enabled, a transmission will be automatically suspended when CTS is deactivated, and resumed when CTS is activated again, as shown in the following figure. A byte that is in transmission when CTS is deactivated will be fully transmitted before the transmission is suspended. For more information, see Suspending the UART on page 485. 6.31.5 Reception A UART reception sequence is started by triggering the STARTRX task. The UART receiver chain implements a FIFO capable of storing six incoming RXD bytes before data is overwritten. Bytes are extracted from this FIFO by reading the RXD register. When a byte is extracted from the FIFO, a new byte pending in the FIFO will be moved to the RXD register. The UART will generate an RXDRDY event every time a new byte is moved to the RXD register. When flow control is enabled, the UART will deactivate the RTS signal when there is only space for four more bytes in the receiver FIFO. The counterpart transmitter is therefore able to send up to four bytes after the RTS signal is deactivated before data is being overwritten. To prevent overwriting data in the FIFO, the counterpart UART transmitter must therefore make sure to stop transmitting data within four bytes after the RTS line is deactivated. The RTS signal will first be activated again when the FIFO has been emptied, that is, when all bytes in the FIFO have been read by the CPU, see UART reception on page 485. 4452_021 v1.3 484

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Peripherals The RTS signal will also be deactivated when the receiver is stopped through the STOPRX task as illustrated in UART reception on page 485. The UART is able to receive four to five additional bytes if they are sent in succession immediately after the RTS signal has been deactivated. This is possible because the UART is, even after the STOPRX task is triggered, able to receive bytes for an extended period of time dependent on the configured baud rate. The UART will generate a receiver timeout event (RXTO) when this period has elapsed. To prevent loss of incoming data, the RXD register must only be read one time following every RXDRDY event. To secure that the CPU can detect all incoming RXDRDY events through the RXDRDY event register, the RXDRDY event register must be cleared before the RXD register is read. The reason for this is that the UART is allowed to write a new byte to the RXD register, and can generate a new event immediately after the RXD register is read (emptied) by the CPU. As indicated in occurrence 2 in the figure, the RXDRDY event associated with byte B is generated first after byte A has been extracted from RXD. 6.31.6 Suspending the UART The UART can be suspended by triggering the SUSPEND task. SUSPEND will affect both the UART receiver and the UART transmitter, i.e. the transmitter will stop transmitting and the receiver will stop receiving. UART transmission and reception can be resumed, after being suspended, by triggering STARTTX and STARTRX respectively. Following a SUSPEND task, an ongoing TXD byte transmission will be completed before the UART is suspended. When the SUSPEND task is triggered, the UART receiver will behave in the same way as it does when the STOPRX task is triggered. 6.31.7 Error conditions An ERROR event, in the form of a framing error, will be generated if a valid stop bit is not detected in a frame. Another ERROR event, in the form of a break condition, will be generated if the RXD line is held active low for longer than the length of a data frame. Effectively, a framing error is always generated before a break condition occurs. 6.31.8 Using the UART without flow control If flow control is not enabled, the interface will behave as if the CTS and RTS lines are kept active all the time. 4452_021 v1.3 485

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Peripherals 6.31.9 Parity and stop bit configuration Automatic even parity generation for both transmission and reception can be configured using the register CONFIG on page 494. If odd parity is desired, it can be configured using the register CONFIG on page 494. See the register description for details. The amount of stop bits can also be configured through the register CONFIG on page 494. 6.31.10 Registers Base address Peripheral Description Configuration 0x40002000 UART Universal asynchronous receiver/

Deprecated Instance UART0 transmitter Register Offset Description TASKS_STARTRX TASKS_STOPRX TASKS_STARTTX TASKS_STOPTX TASKS_SUSPEND EVENTS_CTS EVENTS_NCTS EVENTS_RXDRDY EVENTS_TXDRDY EVENTS_ERROR EVENTS_RXTO SHORTS INTENSET INTENCLR ERRORSRC ENABLE PSEL.RTS PSEL.TXD PSEL.CTS PSEL.RXD RXD TXD BAUDRATE CONFIG 0x000 0x004 0x008 0x00C 0x01C 0x100 0x104 0x108 0x11C 0x124 0x144 0x200 0x304 0x308 0x480 0x500 0x508 0x50C 0x510 0x514 0x518 0x51C 0x524 0x56C CTS is activated (set low). Clear To Send. CTS is deactivated (set high). Not Clear To Send. Shortcuts between local events and tasks Start UART receiver Stop UART receiver Start UART transmitter Stop UART transmitter Suspend UART Data received in RXD Data sent from TXD Error detected Receiver timeout Enable interrupt Disable interrupt Error source Enable UART Pin select for RTS Pin select for TXD Pin select for CTS Pin select for RXD RXD register TXD register Baud rate. Accuracy depends on the HFCLK source selected. Configuration of parity and hardware flow control 6.31.10.1 TASKS_STARTRX Address offset: 0x000 Start UART receiver 4452_021 v1.3 486

Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTRX Start UART receiver Trigger 1 Trigger task ID ID A ID ID A ID ID A ID ID A 6.31.10.2 TASKS_STOPRX Address offset: 0x004 Stop UART receiver 6.31.10.3 TASKS_STARTTX Address offset: 0x008 Start UART transmitter 6.31.10.4 TASKS_STOPTX Address offset: 0x00C Stop UART transmitter 6.31.10.5 TASKS_SUSPEND Address offset: 0x01C Suspend UART Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOPRX Stop UART receiver Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTTX Start UART transmitter Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOPTX Stop UART transmitter Trigger 1 Trigger task A A A A 4452_021 v1.3 487 ID ID A ID ID A ID ID A ID ID A Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value W TASKS_SUSPEND Trigger 1 Description Suspend UART Trigger task 6.31.10.6 EVENTS_CTS Address offset: 0x100 CTS is activated (set low). Clear To Send. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CTS CTS is activated (set low). Clear To Send. NotGenerated Generated Event not generated Event generated 6.31.10.7 EVENTS_NCTS Address offset: 0x104 CTS is deactivated (set high). Not Clear To Send. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. NotGenerated Generated Event not generated Event generated 6.31.10.8 EVENTS_RXDRDY Address offset: 0x108 Data received in RXD RW EVENTS_RXDRDY NotGenerated Generated 6.31.10.9 EVENTS_TXDRDY Address offset: 0x11C Data sent from TXD Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description Data received in RXD Event not generated Event generated A A A A 0 1 0 1 0 1 4452_021 v1.3 488 A A A ID ID A ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description Peripherals RW EVENTS_TXDRDY NotGenerated Generated 6.31.10.10 EVENTS_ERROR Address offset: 0x124 Error detected Data sent from TXD Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value RW EVENTS_ERROR NotGenerated Generated Description Error detected Event not generated Event generated 6.31.10.11 EVENTS_RXTO Address offset: 0x144 Receiver timeout Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RXTO NotGenerated Generated Receiver timeout Event not generated Event generated 6.31.10.12 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW CTS_STARTRX Shortcut between event CTS and task STARTRX B RW NCTS_STOPRX Shortcut between event NCTS and task STOPRX Disabled Enabled Disabled Enabled Disable shortcut Enable shortcut Disable shortcut Enable shortcut 0 1 0 1 0 1 0 1 0 1 4452_021 v1.3 489 Peripherals 6.31.10.13 INTENSET Address offset: 0x304 Enable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW CTS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event CTS B RW NCTS Write '1' to enable interrupt for event NCTS C RW RXDRDY Write '1' to enable interrupt for event RXDRDY D RW TXDRDY Write '1' to enable interrupt for event TXDRDY E RW ERROR Write '1' to enable interrupt for event ERROR F RW RXTO Write '1' to enable interrupt for event RXTO 6.31.10.14 INTENCLR Address offset: 0x308 Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW CTS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event CTS B RW NCTS Write '1' to disable interrupt for event NCTS C RW RXDRDY Write '1' to disable interrupt for event RXDRDY 4452_021 v1.3 490 Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Peripherals Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value D RW TXDRDY Write '1' to disable interrupt for event TXDRDY E RW ERROR Write '1' to disable interrupt for event ERROR F RW RXTO Write '1' to disable interrupt for event RXTO Description Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Value ID Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled NotPresent Present NotPresent Present NotPresent Present NotPresent Present 6.31.10.15 ERRORSRC Address offset: 0x480 Error source Bit number ID ID A Reset 0x00000000 AccessField RW OVERRUN B RW PARITY C RW FRAMING D RW BREAK 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 6.31.10.16 ENABLE Address offset: 0x500 4452_021 v1.3 491 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Overrun error A start bit is received while the previous data still lies in A character with bad parity is received, if HW parity check is RXD. (Previous data is lost.) Read: error not present Read: error present Parity error enabled. Read: error not present Read: error present Framing error occurred Read: error not present Read: error present Break condition A valid stop bit is not detected on the serial data input after all bits in a character have been received. The serial data input is '0' for longer than the length of a data frame. (The data frame length is 10 bits without parity bit, and 11 bits with parity bit.). Read: error not present Read: error present Peripherals A A A A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled Enabled Enable or disable UART Disable UART Enable UART Enable UART Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 6.31.10.17 PSEL.RTS Address offset: 0x508 Pin select for RTS ID A B C ID A B C 6.31.10.18 PSEL.TXD Address offset: 0x50C Pin select for TXD 6.31.10.19 PSEL.CTS Address offset: 0x510 Pin select for CTS 0 4 C 1 0 C 1 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 4452_021 v1.3 492 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Peripherals B A A A A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A Value ID Value Description RX data received in previous transfers, double buffered C 1 0 C 1 0 ID A B C ID A B C ID ID A ID ID A 6.31.10.20 PSEL.RXD Address offset: 0x514 Pin select for RXD Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.31.10.21 RXD Address offset: 0x518 RXD register Reset 0x00000000 AccessField R RXD 6.31.10.22 TXD Address offset: 0x51C TXD register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A Value ID Value Description TX data to be transferred Reset 0x00000000 AccessField W TXD 6.31.10.23 BAUDRATE Address offset: 0x524 Baud rate. Accuracy depends on the HFCLK source selected. 4452_021 v1.3 493 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x04000000 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID ID A AccessField Value ID Value RW BAUDRATE Peripherals Baud1200 Baud2400 Baud4800 Baud9600 Baud14400 Baud19200 Baud28800 Baud31250 Baud38400 Baud56000 Baud57600 Baud76800 Baud115200 Baud230400 Baud250000 Baud460800 Baud921600 Baud1M 0x0004F000 0x0009D000 0x0013B000 0x00275000 0x003B0000 0x004EA000 0x0075F000 0x00800000 0x009D5000 0x00E50000 0x00EBF000 0x013A9000 0x01D7E000 0x03AFB000 0x04000000 0x075F7000 0x0EBED000 0x10000000 Description Baud rate 1200 baud (actual rate: 1205) 2400 baud (actual rate: 2396) 4800 baud (actual rate: 4808) 9600 baud (actual rate: 9598) 14400 baud (actual rate: 14414) 19200 baud (actual rate: 19208) 28800 baud (actual rate: 28829) 31250 baud 38400 baud (actual rate: 38462) 56000 baud (actual rate: 55944) 57600 baud (actual rate: 57762) 76800 baud (actual rate: 76923) 115200 baud (actual rate: 115942) 230400 baud (actual rate: 231884) 250000 baud 460800 baud (actual rate: 470588) 921600 baud (actual rate: 941176) 1Mega baud 6.31.10.24 CONFIG Address offset: 0x56C Configuration of parity and hardware flow control 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D C B B B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Bit number ID ID A Reset 0x00000000 AccessField RW HWFC B RW PARITY C RW STOP D RW PARITYTYPE Disabled Enabled Excluded Included One Two Even Odd 0x0 0x7 0 1 0 1 0 1 Hardware flow control Disabled Enabled Parity Exclude parity bit Include parity bit Stop bits One stop bit Two stop bits Even or odd parity type Even parity Odd parity 4452_021 v1.3 494 Peripherals 6.31.11 Electrical specification 6.31.11.1 UART electrical specification Symbol fUART tUART,CTSH tUART,START Description Baud rate for UART39. CTS high time Time from STARTRX/STARTTX task to transmission started Min. Typ. Max. 1000 1 1 Units kbps s s 6.32 UARTE Universal asynchronous receiver/

transmitter with EasyDMA The Universal asynchronous receiver/transmitter with EasyDMA (UARTE) offers fast, full-duplex, asynchronous serial communication with built-in flow control (CTS, RTS) support in hardware at a rate up to 1 Mbps, and EasyDMA data transfer from/to RAM. Listed here are the main features for UARTE:

Full-duplex operation Automatic hardware flow control Optional even parity bit checking and generation EasyDMA Up to 1 Mbps baudrate Return to IDLE between transactions supported (when using HW flow control) One or two stop bit Least significant bit (LSB) first The GPIOs used for each UART interface can be chosen from any GPIO on the device and are independently configurable. This enables great flexibility in device pinout and efficient use of board space and signal routing. Note: The external crystal oscillator must be enabled to obtain sufficient clock accuracy for stable communication. See CLOCK Clock control on page 80 for more information. 39 High baud rates may require GPIOs to be set as High Drive, see GPIO for more details. 4452_021 v1.3 495

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Peripherals 6.32.1 EasyDMA The UARTE implements EasyDMA for reading and writing to and from the RAM. If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 19 for more information about the different memory regions. The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/

TX transmission immediately after having received the RXSTARTED/TXSTARTED event. The ENDRX and ENDTX events indicate that the EasyDMA is finished accessing the RX or TX buffer in RAM. 6.32.2 Transmission The first step of a DMA transmission is storing bytes in the transmit buffer and configuring EasyDMA. This is achieved by writing the initial address pointer to TXD.PTR, and the number of bytes in the RAM buffer to TXD.MAXCNT. The UARTE transmission is started by triggering the STARTTX task. After each byte has been sent over the TXD line, a TXDRDY event will be generated. When all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have been transmitted, the UARTE transmission will end automatically and an ENDTX event will be generated. A UARTE transmission sequence is stopped by triggering the STOPTX task. A TXSTOPPED event will be generated when the UARTE transmitter has stopped. If the ENDTX event has not already been generated when the UARTE transmitter has come to a stop, the UARTE will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have not been transmitted. If flow control is enabled through the HWFC field in the CONFIG register, a transmission will be automatically suspended when CTS is deactivated and resumed when CTS is activated again, as shown in the following figure. A byte that is in transmission when CTS is deactivated will be fully transmitted before the transmission is suspended. The UARTE transmitter will be in its lowest activity level, and consume the least amount of energy, when it is stopped, i.e. before it is started via STARTTX or after it has been stopped via STOPTX and the TXSTOPPED 4452_021 v1.3 496

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Peripherals event has been generated. See POWER Power supply on page 58 for more information about power modes. 6.32.3 Reception The UARTE receiver is started by triggering the STARTRX task. The UARTE receiver is using EasyDMA to store incoming data in an RX buffer in RAM. The RX buffer is located at the address specified in the RXD.PTR register. The RXD.PTR register is double-

buffered and it can be updated and prepared for the next STARTRX task immediately after the RXSTARTED event is generated. The size of the RX buffer is specified in the RXD.MAXCNT register. The UARTE generates an ENDRX event when it has filled up the RX buffer, as seen in the following figure. For each byte received over the RXD line, an RXDRDY event will be generated. This event is likely to occur before the corresponding data has been transferred to Data RAM. The RXD.AMOUNT register can be queried following an ENDRX event to see how many new bytes have been transferred to the RX buffer in RAM since the previous ENDRX event. The UARTE receiver is stopped by triggering the STOPRX task. An RXTO event is generated when the UARTE has stopped. The UARTE will make sure that an impending ENDRX event will be generated before the RXTO event is generated. This means that the UARTE will guarantee that no ENDRX event will be generated after RXTO, unless the UARTE is restarted or a FLUSHRX command is issued after the RXTO event is generated. Note: If the ENDRX event has not been generated when the UARTE receiver stops, indicating that all pending content in the RX FIFO has been moved to the RX buffer, the UARTE will generate the ENDRX event explicitly even though the RX buffer is not full. In this scenario the ENDRX event will be generated before the RXTO event is generated. To determine the amount of bytes the RX buffer has received, the CPU can read the RXD.AMOUNT register following the ENDRX event or the RXTO event. 4452_021 v1.3 497

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Peripherals The UARTE is able to receive up to four bytes after the STOPRX task has been triggered, as long as these are sent in succession immediately after the RTS signal is deactivated. After the RTS is deactivated, the UART is able to receive bytes for a period of time equal to the time needed to send four bytes on the configured baud rate. After the RXTO event is generated the internal RX FIFO may still contain data, and to move this data to RAM the FLUSHRX task must be triggered. To make sure that this data does not overwrite data in the RX buffer, the RX buffer should be emptied or the RXD.PTR should be updated before the FLUSHRX task is triggered. To make sure that all data in the RX FIFO is moved to the RX buffer, the RXD.MAXCNT register must be set to RXD.MAXCNT > 4, as seen in the following figure. The UARTE will generate the ENDRX event after completing the FLUSHRX task even if the RX FIFO was empty or if the RX buffer does not get filled up. To be able to know how many bytes have actually been received into the RX buffer in this case, the CPU can read the RXD.AMOUNT register following the ENDRX event. If HW flow control is enabled through the HWFC field in the CONFIG register, the RTS signal will be deactivated when the receiver is stopped via the STOPRX task or when the UARTE is only able to receive four more bytes in its internal RX FIFO. With flow control disabled, the UARTE will function in the same way as when the flow control is enabled except that the RTS line will not be used. This means that no signal will be generated when the UARTE has reached the point where it is only able to receive four more bytes in its internal RX FIFO. Data received when the internal RX FIFO is filled up, will be lost. The UARTE receiver will be in its lowest activity level, and consume the least amount of energy, when it is stopped, i.e. before it is started via STARTRX or after it has been stopped via STOPRX and the RXTO event has been generated. See POWER Power supply on page 58 for more information about power modes. 6.32.4 Error conditions An ERROR event, in the form of a framing error, will be generated if a valid stop bit is not detected in a frame. Another ERROR event, in the form of a break condition, will be generated if the RXD line is held active low for longer than the length of a data frame. Effectively, a framing error is always generated before a break condition occurs. An ERROR event will not stop reception. If the error was a parity error, the received byte will still be transferred into Data RAM, and so will following incoming bytes. If there was a framing error (wrong stop bit), that specific byte will NOT be stored into Data RAM, but following incoming bytes will. 6.32.5 Using the UARTE without flow control If flow control is not enabled, the interface will behave as if the CTS and RTS lines are kept active all the time. 4452_021 v1.3 498

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7 Peripherals 6.32.6 Parity and stop bit configuration Automatic even parity generation for both transmission and reception can be configured using the register CONFIG on page 512. If odd parity is desired, it can be configured using the register CONFIG on page 512. See the register description for details. The amount of stop bits can also be configured through the register CONFIG on page 512. 6.32.7 Low power When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral. The STOPTX and STOPRX tasks may not be always needed (the peripheral might already be stopped), but if STOPTX and/or STOPRX is sent, software shall wait until the TXSTOPPED and/or RXTO event is received in response, before disabling the peripheral through the ENABLE register. 6.32.8 Pin configuration The different signals RXD, CTS (Clear To Send, active low), RTS (Request To Send, active low), and TXD associated with the UARTE are mapped to physical pins according to the configuration specified in the PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers respectively. The PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers and their configurations are only used as long as the UARTE is enabled, and retained only for the duration the device is in ON mode. PSEL.RXD, PSEL.RTS, PSEL.RTS, and PSEL.TXD must only be configured when the UARTE is disabled. To secure correct signal levels on the pins by the UARTE when the system is in OFF mode, the pins must be configured in the GPIO peripheral as described in the following table. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. UARTE signal UARTE pin As specified in PSEL.RXD As specified in PSEL.CTS As specified in PSEL.RTS As specified in PSEL.TXD Direction Input Input Output Output Output value Not applicable Not applicable 1 1 RXD CTS RTS TXD 6.32.9 Registers Base address Peripheral Description Configuration 0x40002000 UARTE Instance UARTE0 0x40028000 UARTE UARTE1 Universal asynchronous receiver/

Universal asynchronous receiver/

transmitter with EasyDMA, unit 0 transmitter with EasyDMA, unit 1 Register TASKS_STARTRX TASKS_STOPRX TASKS_STARTTX TASKS_STOPTX TASKS_FLUSHRX 4452_021 v1.3 Offset 0x000 0x004 0x008 0x00C 0x02C Description Start UART receiver Stop UART receiver Start UART transmitter Stop UART transmitter Flush RX FIFO into RX buffer 499

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Peripherals Register EVENTS_CTS EVENTS_NCTS EVENTS_RXDRDY EVENTS_ENDRX EVENTS_TXDRDY EVENTS_ENDTX EVENTS_ERROR EVENTS_RXTO EVENTS_RXSTARTED EVENTS_TXSTARTED EVENTS_TXSTOPPED SHORTS INTEN INTENSET INTENCLR ERRORSRC ENABLE PSEL.RTS PSEL.TXD PSEL.CTS PSEL.RXD BAUDRATE RXD.PTR RXD.MAXCNT RXD.AMOUNT TXD.PTR TXD.MAXCNT TXD.AMOUNT CONFIG Offset 0x100 0x104 0x108 0x110 0x11C 0x120 0x124 0x144 0x14C 0x150 0x158 0x200 0x300 0x304 0x308 0x480 0x500 0x508 0x50C 0x510 0x514 0x524 0x534 0x538 0x53C 0x544 0x548 0x54C 0x56C Description CTS is activated (set low). Clear To Send. CTS is deactivated (set high). Not Clear To Send. Data received in RXD (but potentially not yet transferred to Data RAM) Receive buffer is filled up Data sent from TXD Last TX byte transmitted Error detected Receiver timeout UART receiver has started UART transmitter has started Transmitter stopped Shortcuts between local events and tasks Enable or disable interrupt This register is read/write one to clear. Enable interrupt Disable interrupt Error source Enable UART Pin select for RTS signal Pin select for TXD signal Pin select for CTS signal Pin select for RXD signal Baud rate. Accuracy depends on the HFCLK source selected. Data pointer Data pointer Maximum number of bytes in receive buffer Number of bytes transferred in the last transaction Maximum number of bytes in transmit buffer Number of bytes transferred in the last transaction Configuration of parity and hardware flow control 6.32.9.1 TASKS_STARTRX Address offset: 0x000 Start UART receiver 6.32.9.2 TASKS_STOPRX Address offset: 0x004 Stop UART receiver Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTRX Start UART receiver Trigger 1 Trigger task ID ID A 4452_021 v1.3 500

Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOPRX Stop UART receiver Trigger 1 Trigger task 6.32.9.3 TASKS_STARTTX Address offset: 0x008 Start UART transmitter 6.32.9.4 TASKS_STOPTX Address offset: 0x00C Stop UART transmitter 6.32.9.5 TASKS_FLUSHRX Address offset: 0x02C Flush RX FIFO into RX buffer ID ID A ID ID A ID ID A ID ID A 6.32.9.6 EVENTS_CTS Address offset: 0x100 CTS is activated (set low). Clear To Send. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTTX Start UART transmitter Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STOPTX Stop UART transmitter Trigger 1 Trigger task Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_FLUSHRX Flush RX FIFO into RX buffer Trigger 1 Trigger task A A A A 4452_021 v1.3 501 ID ID A ID ID A ID ID A ID ID A Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_CTS CTS is activated (set low). Clear To Send. NotGenerated Generated Event not generated Event generated 6.32.9.7 EVENTS_NCTS Address offset: 0x104 CTS is deactivated (set high). Not Clear To Send. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. NotGenerated Generated Event not generated Event generated 6.32.9.8 EVENTS_RXDRDY Address offset: 0x108 Data received in RXD (but potentially not yet transferred to Data RAM) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RXDRDY Data received in RXD (but potentially not yet transferred to NotGenerated Generated Data RAM) Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description Receive buffer is filled up Event not generated Event generated 6.32.9.9 EVENTS_ENDRX Address offset: 0x110 Receive buffer is filled up RW EVENTS_ENDRX NotGenerated Generated 6.32.9.10 EVENTS_TXDRDY Address offset: 0x11C Data sent from TXD 4452_021 v1.3 502 A A A A 0 1 0 1 0 1 0 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description Peripherals Data sent from TXD Event not generated Event generated Last TX byte transmitted Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_TXDRDY NotGenerated Generated 6.32.9.11 EVENTS_ENDTX Address offset: 0x120 Last TX byte transmitted RW EVENTS_ENDTX NotGenerated Generated 6.32.9.12 EVENTS_ERROR Address offset: 0x124 Error detected 6.32.9.13 EVENTS_RXTO Address offset: 0x144 Receiver timeout ID ID A ID ID A ID ID A ID ID A 0 1 0 1 0 1 0 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value RW EVENTS_ERROR NotGenerated Generated Description Error detected Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RXTO NotGenerated Generated Receiver timeout Event not generated Event generated 6.32.9.14 EVENTS_RXSTARTED Address offset: 0x14C UART receiver has started 4452_021 v1.3 503 A A A A A A A ID ID A ID ID A ID ID A ID ID C Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_RXSTARTED NotGenerated Generated UART receiver has started Event not generated Event generated 6.32.9.15 EVENTS_TXSTARTED Address offset: 0x150 UART transmitter has started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_TXSTARTED NotGenerated Generated UART transmitter has started Event not generated Event generated 6.32.9.16 EVENTS_TXSTOPPED Address offset: 0x158 Transmitter stopped Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_TXSTOPPED NotGenerated Generated Transmitter stopped Event not generated Event generated 6.32.9.17 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D C Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW ENDRX_STARTRX Shortcut between event ENDRX and task STARTRX D RW ENDRX_STOPRX Shortcut between event ENDRX and task STOPRX Disabled Enabled Disabled Enabled Disable shortcut Enable shortcut Disable shortcut Enable shortcut 0 1 0 1 0 1 0 1 0 1 4452_021 v1.3 504 Peripherals 6.32.9.18 INTEN Address offset: 0x300 Enable or disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW CTS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event CTS B RW NCTS Enable or disable interrupt for event NCTS C RW RXDRDY Enable or disable interrupt for event RXDRDY D RW ENDRX Enable or disable interrupt for event ENDRX E RW TXDRDY Enable or disable interrupt for event TXDRDY F RW ENDTX Enable or disable interrupt for event ENDTX G RW ERROR Enable or disable interrupt for event ERROR H RW RXTO Enable or disable interrupt for event RXTO I J RW RXSTARTED Enable or disable interrupt for event RXSTARTED RW TXSTARTED Enable or disable interrupt for event TXSTARTED L RW TXSTOPPED Enable or disable interrupt for event TXSTOPPED Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6.32.9.19 INTENSET Address offset: 0x304 Enable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW CTS 4452_021 v1.3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event CTS 505 Bit number ID Reset 0x00000000 ID AccessField 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Peripherals B RW NCTS Write '1' to enable interrupt for event NCTS C RW RXDRDY Write '1' to enable interrupt for event RXDRDY D RW ENDRX Write '1' to enable interrupt for event ENDRX E RW TXDRDY Write '1' to enable interrupt for event TXDRDY F RW ENDTX Write '1' to enable interrupt for event ENDTX G RW ERROR Write '1' to enable interrupt for event ERROR H RW RXTO Write '1' to enable interrupt for event RXTO I J RW RXSTARTED Write '1' to enable interrupt for event RXSTARTED RW TXSTARTED Write '1' to enable interrupt for event TXSTARTED L RW TXSTOPPED Write '1' to enable interrupt for event TXSTOPPED Description Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Value ID Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 6.32.9.20 INTENCLR Address offset: 0x308 Disable interrupt 4452_021 v1.3 506 Bit number ID ID A Reset 0x00000000 AccessField RW CTS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event CTS Peripherals B RW NCTS Write '1' to disable interrupt for event NCTS C RW RXDRDY Write '1' to disable interrupt for event RXDRDY D RW ENDRX Write '1' to disable interrupt for event ENDRX E RW TXDRDY Write '1' to disable interrupt for event TXDRDY F RW ENDTX Write '1' to disable interrupt for event ENDTX G RW ERROR Write '1' to disable interrupt for event ERROR H RW RXTO Write '1' to disable interrupt for event RXTO I J RW RXSTARTED Write '1' to disable interrupt for event RXSTARTED RW TXSTARTED Write '1' to disable interrupt for event TXSTARTED L RW TXSTOPPED Write '1' to disable interrupt for event TXSTOPPED Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 6.32.9.21 ERRORSRC Address offset: 0x480 Error source This register is read/write one to clear. 4452_021 v1.3 507 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Overrun error A start bit is received while the previous data still lies in Peripherals D C B A A character with bad parity is received, if HW parity check is RXD. (Previous data is lost.) Read: error not present Read: error present Parity error enabled. Read: error not present Read: error present Framing error occurred Read: error not present Read: error present Break condition A valid stop bit is not detected on the serial data input after all bits in a character have been received. The serial data input is '0' for longer than the length of a data frame. (The data frame length is 10 bits without parity bit, and 11 bits with parity bit). Read: error not present Read: error present 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled Enabled Enable or disable UARTE Disable UARTE Enable UARTE NotPresent Present NotPresent Present NotPresent Present NotPresent Present Bit number ID ID A Reset 0x00000000 AccessField RW OVERRUN B RW PARITY C RW FRAMING D RW BREAK 6.32.9.22 ENABLE Address offset: 0x500 Enable UART Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE 6.32.9.23 PSEL.RTS Address offset: 0x508 Pin select for RTS signal 0 1 0 1 0 1 0 1 0 8 4452_021 v1.3 508 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Peripherals B A A A A A Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect C 1 0 C 1 0 C 1 0 ID A B C ID A B C ID A B C Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.32.9.24 PSEL.TXD Address offset: 0x50C Pin select for TXD signal Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.32.9.25 PSEL.CTS Address offset: 0x510 Pin select for CTS signal Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT 6.32.9.26 PSEL.RXD Address offset: 0x514 Pin select for RXD signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B A A A A A Value

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Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 4452_021 v1.3 509 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Peripherals B A A A A A Reset 0xFFFFFFFF ID AccessField RW PIN RW PORT RW CONNECT Value

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C 1 0 Value ID Disconnected Connected Description Pin number Port number Connection Disconnect Connect 6.32.9.27 BAUDRATE Address offset: 0x524 Baud rate. Accuracy depends on the HFCLK source selected. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x04000000 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value RW BAUDRATE ID A B C ID ID A Baud1200 Baud2400 Baud4800 Baud9600 Baud14400 Baud19200 Baud28800 Baud31250 Baud38400 Baud56000 Baud57600 Baud76800 Baud115200 Baud230400 Baud250000 Baud460800 Baud921600 Baud1M 0x0004F000 0x0009D000 0x0013B000 0x00275000 0x003AF000 0x004EA000 0x0075C000 0x00800000 0x009D0000 0x00E50000 0x00EB0000 0x013A9000 0x01D60000 0x03B00000 0x04000000 0x07400000 0x0F000000 0x10000000 Description Baud rate 1200 baud (actual rate: 1205) 2400 baud (actual rate: 2396) 4800 baud (actual rate: 4808) 9600 baud (actual rate: 9598) 14400 baud (actual rate: 14401) 19200 baud (actual rate: 19208) 28800 baud (actual rate: 28777) 31250 baud 38400 baud (actual rate: 38369) 56000 baud (actual rate: 55944) 57600 baud (actual rate: 57554) 76800 baud (actual rate: 76923) 115200 baud (actual rate: 115108) 230400 baud (actual rate: 231884) 250000 baud 460800 baud (actual rate: 457143) 921600 baud (actual rate: 941176) 1 megabaud 6.32.9.28 RXD.PTR Address offset: 0x534 Data pointer Bit number ID ID A Reset 0x00000000 AccessField RW PTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Data pointer See the memory chapter for details about which memories are available for EasyDMA. 4452_021 v1.3 510 Peripherals 6.32.9.29 RXD.MAXCNT Address offset: 0x538 Maximum number of bytes in receive buffer ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW MAXCNT Value ID Value Description

[0..0xFFFF]

Maximum number of bytes in receive buffer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A 6.32.9.30 RXD.AMOUNT Address offset: 0x53C Number of bytes transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description

[0..0xFFFF]

Number of bytes transferred in the last transaction Reset 0x00000000 AccessField R AMOUNT 6.32.9.31 TXD.PTR Address offset: 0x544 Data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW PTR Value ID Value Description Data pointer A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 See the memory chapter for details about which memories are available for EasyDMA. 6.32.9.32 TXD.MAXCNT Address offset: 0x548 Maximum number of bytes in transmit buffer Bit number ID ID A Reset 0x00000000 AccessField RW MAXCNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description

[0..0xFFFF]

Maximum number of bytes in transmit buffer 6.32.9.33 TXD.AMOUNT Address offset: 0x54C Number of bytes transferred in the last transaction 4452_021 v1.3 511 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Value ID Value Description

[0..0xFFFF]

Number of bytes transferred in the last transaction Peripherals Configuration of parity and hardware flow control Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D C B B B A Value ID Value Description Reset 0x00000000 AccessField R AMOUNT 6.32.9.34 CONFIG Address offset: 0x56C ID ID A ID ID A Reset 0x00000000 AccessField RW HWFC B RW PARITY C RW STOP Disabled Enabled Excluded Included One Two Even Odd 0x0 0x7 0 1 0 1 0 1 Hardware flow control Exclude parity bit Include even parity bit Disabled Enabled Parity Stop bits One stop bit Two stop bits Even parity Odd parity D RW PARITYTYPE Even or odd parity type 6.32.10 Electrical specification 6.32.10.1 UARTE electrical specification Symbol fUARTE tUARTE,CTSH tUARTE,START Description Baud rate for UARTE40. CTS high time Time from STARTRX/STARTTX task to transmission started Min. Typ. Max. 1000 1 1 Units kbps s s 6.33 USBD Universal serial bus device The USB device (USBD) controller implements a full speed USB device function that meets 2.0 revision of the USB specification. 40 High baud rates may require GPIOs to be set as High Drive, see GPIO chapter for more details. 4452_021 v1.3 512 Peripherals Listed here are the main features for USBD:

Implements full-speed (12 Mbps) device fully compliant to Universal Serial Bus Specification Revision 2.0, including following engineering change notices (ECNs) issued by USB Implementers Forum:

USB device stack available in the Nordic SDK Integrated (on-chip) USB transceiver (PHY) Software controlled on-chip pull-up on D+

Endpoints:

2 control (1 IN, 1 OUT) 14 bulk/interrupt (7 IN, 7 OUT) 2 isochronous (1 IN, 1 OUT) Supports double buffering for isochronous (ISO) endpoints (IN/OUT) Supports USB suspend, resume, and remote wake-up 64 bytes buffer size for each bulk/interrupt endpoint Up to 1023 bytes buffer size for ISO endpoints EasyDMA for all data transfers 6.33.1 USB device states The behavior of a USB device can be modelled through a state diagram. The USB specification revision 2.0 (see USB device, as illustrated below.

) defines a number of states for a 4452_021 v1.3 513

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Peripherals The device must change state according to host-initiated traffic and USB bus states. It is up to the software to implement a state machine that matches the above definition. To detect the presence or absence of USB supply (VBUS), the POWER chapter defines two events, USBDETECTED and USBREMOVED, which can be used to implement the state machine. As a general rule when implementing the software, the host behavior shall never be assumed to be predictable. In particular the sequence of commands received during an enumeration. The software shall always react to the current bus conditions or commands sent by the host. 6.33.2 USB terminology The USB specification defines bus states, rather than logic levels on the D+ and D- lines. For a full speed device, the bus state where the D+ line is high and the D- line is low is defined as the J state. The bus state where D+ is low and D- high is called the K state. An idle bus, where D+ and D- lines are only polarized through the pull-up on D+ and pull-downs on the host side, will be in J state. Both lines low are called SE0 (single-ended 0), and both lines high SE1 (single-ended 1). 4452_021 v1.3 514

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Peripherals 6.33.3 USB pins The USBD peripheral features a number of dedicated pins. The dedicated USB pins can be grouped in two categories, signal and power. The signal pins consist of the D+ and D- pins, which are to be connected to the USB host. They are dedicated pins, and not available as standard GPIOs. The USBD implements the meaning that these two pins are not 5 V tolerant. The signal pins and the pull-up will operate only while VBUS is in its valid voltage range, and USBD is enabled through the ENABLE register. For details on the USB power supply and VBUS detection, see POWER. See Pin assignments on page 557 for more information about the pinout. 6.33.4 USBD power-up sequence The physical layer interface (PHY)/USB transceiver is powered separately from the rest of the device (VBUS pin), which has some implications on the USBD power-up sequence. The device is not able to properly signal its presence to the USB host and handle traffic from the host, unless the PHY's power supply is enabled and stable. Turning the PHY's power supply on/off is directly linked to register ENABLE. The device provides events that help synchronizing software to the various steps during the power-up sequence. To make sure that all resources in USBD are available and the dedicated USB voltage regulator stabilized, the following is recommended:

Enable USBD after VBUS has been detected only Turn the USB pull-up on after:

USBPWRRDY event has occurred USBEVENT has occurred, with the READY condition flagged in EVENTCAUSE The following sequence chart illustrates a typical handling of VBUS power-up:

Upon VBUS removal detection, signalled by the USBREMOVED event described in POWER, it is recommended to let on-going EasyDMA transfers finish (wait for the relevant ENDEPIN[n], ENDISOIN, ENDEPOUT[n] or ENDISOOUT event, see EasyDMA on page 518), before disabling USBD (by writing ENABLE=Disabled). Reading the ENABLE register will return Enabled until USBD is completely disabled. 4452_021 v1.3 515

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1 V B U S P O W E R C L O C K S o f t w a r e U S B D V B U S i n v a l i d r a n g e U S B D E T E C T E D E N A B L E

E n a b l e d H F C L K S T A R T U S B E V E N T E V E N T C A U S E

R E A D Y U S B P W R R D Y H F C L K S T A R T E D U S B P U L L U P

E n a b l e d H F C L K C r y s t a l o s c i l l a t o r n o w s t a r t i n g U S B D h a s b e e n i n i t i a l i z e d

, b u t P H Y h a s n o t p o w e r e d u p P H Y i s n o w p o w e r e d E n u m e r a t i o n s t a r t s

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Peripherals 6.33.5 USB pull-up The USB pull-up serves two purposes - it indicates to the host that the device is connected to the USB bus, and it indicates the device's speed capability. When no pull-up is connected to the USB bus, the host sees both D+ and D- lines low, as they are pulled down on the host side by 15 k resistors. The device is not seen by the host and hence in detached state, even though it could be physically connected to the host. USB specification does not allow to draw any current on VBUS in that situation. When a full-speed device connects its 1.5 k pull-up to D+, the host sees the corresponding line high. The device is then in the attached state. During the enumeration process, the host attempts to determine if the full-speed device also supports higher speeds and initiates communication with the device to further identify it. The USBD peripheral implemented in this device supports only full-speed (12 Mbps), and thus ignores the negotiation for higher speeds in accordance with the USB specification revision 2.0. Register USBPULLUP provides means to connect or disconnect the pull-up on D+ under software control. This allows the software to control when USB enumeration takes place. It also allows to emulate a physical disconnect from the USB bus, for instance when re-enumeration is required. USBPULLUP has to be enabled to allow the USBD to handle USB traffic and generate appropriate events. This forbids the use of an external pull-up. Note that disconnecting the pull-up through register USBPULLUP while connected to a host, will result in both D+ and D- lines to be pulled low by the host's pull-down resistors. However, as mentioned above, this will also inhibit the generation of the USBRESET event. The pull-up is disabled by default after a chip reset. The pull-up shall only get connected after USBD has been enabled through register ENABLE. The USB pull-up value is automatically changed depending on the bus activity, as specified in amends the original USB specification version 2.0. The user does not have access to this function, it is handled in hardware. which While they should never be used in normal traffic activity, lines D+ and D- may at any time be forced into state specified in register DPDMVALUE by the task DPDMDRIVE. The DPDMNODRIVE task stops driving them, and PHY returns to normal operation. 6.33.6 USB reset The USB specification defines a USB reset, which is not be confused with a chip reset. The USB reset is a normal USB bus condition, and is used as part of the enumeration sequence, it does not reset the chip. The USB reset results from a single-ended low state (SE0) on lines D+/D- for a tUSB,DETRST amount of time. Only the host is allowed to drive a USB reset condition on the bus. The UBSD peripheral automatically interprets a SE0 longer than tUSB,DETRST as a USB reset. When the device detects a USB reset and generates a USBRESET event, the device USB stack and related parts of the application shall re-initialize themselves, and go back to the default state. Some of the registers in the USBD peripheral get automatically reset to a known state, in particular all data endpoints are disabled and the USBADDR reset to 0. After the device has connected to the USB bus (i.e. after VBUS is applied), the device shall not respond to any traffic from the time the pull-up is enabled until it has seen a USB reset condition. This is automatically ensured by the USBD. After a USB reset, the device shall be fully responsive after at most TRSTRCY (according to chapter 7 in the USB specification). Software shall take into account this time that takes the hardware to recover from a USB reset condition. 4452_021 v1.3 516

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1 Peripherals 6.33.7 USB suspend and resume Normally, the host will maintain activity on the USB at least every millisecond according to USB specification. A USB device will enter suspend when there is no activity on the bus (idle) for a given time. The device will resume operation when it receives any non idle signalling. To signal that the device shall go into low power mode (suspend), the host stops activity on the USB bus, which becomes idle. Only the device pull-up and host pull-downs act on D+ and D-, and the bus is thus kept at a constant J state. It is up to the device to detect this lack of activity, and enter the low power mode (suspend) within a specified time. The USB host can decide to suspend or resume USB activity at any time. If remote wake-up is enabled, the device may signal to the host to resume from suspend. 6.33.7.1 Entering suspend The USBD peripheral automatically detects lack of activity for more than a defined amount of time, and performs steps needed to enter suspend. When no activity has been detected for longer than tUSB,SUSPEND, the USBD generates the USBEVENT event with SUSPEND bit set in register EVENTCAUSE. The software shall ensure that the current drawn from the USB supply line VBUS is within the specified limits before T2SUSP, as defined in chapter 7 of the USB specification. In order to reduce idle current of USBD, the software must explicitly place the USBD in low power mode through writing to register LOWPOWER. In order to save power, and provided that no other peripheral needs it, the crystal oscillator (HFXO) in CLOCK may be disabled by software during the USB suspend, while the USB pull-up is disconnected, or when VBUS is not present. Software must explicitly enable it at any other time. The USBD will not be able to respond to USB traffic unless HFXO is enabled and stable. 6.33.7.2 Host-initiated resume Once the host resumes the bus activity, it has to be responsive to incoming requests on the USB bus within the time TRSMRCY (as defined in chapter 7 of the USB specification) and revert to normal power consumption mode. If the host resumes bus activity with or without a RESUME condition (in other words: bus activity is defined as any non-J state), the USBD peripheral will generate a USBEVENT event, with RESUME bit set in register EVENTCAUSE. If the host resumes bus activity simply by restarting sending frames, the USBD peripheral will generate SOF events. 6.33.7.3 Device-initiated remote wake-up Assuming the remote wake-up is supported by the device and enabled by the host, the device can request the host to resume from suspend if wake-up condition is met. To do so, the HFXO needs to be enabled first. After waking up the HFXO, the software must bring USBD out of the low power mode and into the normal power consumption mode through writing in register LOWPOWER. It can then instruct the USBD peripheral to drive a RESUME condition (K state) on the USB bus by triggering the DPDMDRIVE task, and hence attempt to wake up the host. By choosing in DPDMVALUE, the duration of the RESUME state is under hardware control (tUSB,DRIVEK). By or

, the duration of that state is under software control (the J or K state is maintained until a choosing DPDMNODRIVE task is triggered) and has to meet TDRSMUP as specified in USB specification chapter 7. Upon writing the USBWUALLOWED bit set in register EVENTCAUSE. in register LOWPOWER, a USBEVENT event is generated with the The value in register DPDMVALUE on page 546 will only be captured and used when the DPDMDRIVE task is triggered. This value defines the state the bus will be forced into after the DPDMDRIVE task. Note that the device shall ensure that it does not initiate a remote wake-up request before TWTRSM

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Peripherals resume value in DPDMVALUE (rather than K) takes care of this, and postpones the RESUME state accordingly. 6.33.8 EasyDMA The USBD peripheral implements EasyDMA for accessing memory without CPU involvement. Each endpoint has an associated set of registers, tasks and events. EasyDMA and traffic on USB are tightly related. A number of events provide insight of what is happening on the USB bus, and a number of tasks allow to somewhat automate response to the traffic. Note: Endpoint 0 (IN and OUT) are implemented as control endpoint. For more information, see Control transfers on page 519. Enabling endpoints is controlled through the EPINEN and EPOUTEN registers. The following registers define the memory address of the buffer for a specific IN or OUT endpoint:

Registers EPIN[n].PTR, (n=0..7) EPOUT[n].PTR, (n=0..7) ISOIN.PTR ISOOUT.PTR EPIN[n].MAXCNT, (n=0..7) ISOIN.MAXCNT EPOUT[n].MAXCNT, (n=1..7) ISOOUT.MAXCNT The following registers define the amount of bytes to be sent on USB for next transaction:

The following registers define the length of the buffer (in bytes) for next transfer of incoming data:

Since the host decides how many bytes are sent over USB, the MAXCNT value can be copied from register SIZE.EPOUT[n] (n=1..7) or register SIZE.ISOOUT. Register EPOUT[0].MAXCNT defines the length of the OUT buffer (in bytes) for the control endpoint 0. If the USB host does not misbehave, register SIZE.EPOUT[0] will indicate the same value as from the device descriptor or from the SETUP command, whichever the smallest. The .AMOUNT registers indicate how many bytes actually have been transferred over EasyDMA during the last transfer. Stalling bulk/interrupt endpoints is controlled through the EPSTALL register. Note: Due to USB specification requirements, the effect of the stalling control endpoint 0 may be overridden by hardware, in particular when a new SETUP token is received. EasyDMA will not copy the SETUP data to memory (it will only transfer data from the data stage). Setup data is available as separate registers in the USBD peripheral:

BMREQUESTTYPE BREQUEST WVALUEL WVALUEH WINDEXL WINDEXH 4452_021 v1.3 518

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) Peripherals WLENGTHL WLENGTHH Tasks Events EVENTCAUSE register provides details on what caused a given USBEVENT event, for instance if a CRC error is detected during a transaction, or if bus activity stops or resumes. Tasks STARTEPIN[n], STARTEPOUT[n] (n=0..7), STARTISOIN and STARTISOOUT capture the values for .PTR and .MAXCNT registers. For IN endpoints, a transaction over USB gets automatically triggered when the EasyDMA transfer is complete. For OUT endpoints, it is up to software to allow the next transaction over USB. See the examples in Control transfers on page 519, Bulk and interrupt transactions on page 522 and Isochronous transactions on page 525. For the control endpoint 0, OUT transactions are allowed through the EP0RCVOUT task. The EP0STATUS task allows a status stage to be initiated, and the EP0STALL task allows stalling further traffic (data or status stage) on the control endpoint. The STARTED event confirms that the values of the .PTR and .MAXCNT registers of the endpoints flagged in register EPSTATUS have been captured. Those can then be modified by software for the next transfer. Events ENDEPIN[n], ENDEPOUT[n] (n=0..7), ENDISOIN and ENDISOOUT events indicate that the whole buffer has been consumed. The buffer can be accessed safely by the software. Only a single EasyDMA transfer can take place in USBD at any time. Software must ensure that tasks STARTEPIN[n] (n=0..7), STARTISOIN , STARTEPOUT[n] (n=0..7) or STARTISOOUT are not triggered before events ENDEPIN[n] (n=0..7), ENDISOIN, ENDEPOUT[n] (n=0..7) or ENDISOOUT are received from an on-

going transfer. The EPDATA event indicates that a successful (acknowledged) data transaction has occurred on the data endpoint(s) flagged in register EPDATASTATUS. A successful (acknowledged) data transaction on endpoint 0 is signalled by the EP0DATADONE event. At any time a USBEVENT event may be sent, with details provided in EVENTCAUSE register. EP0SETUP event indicates that a SETUP token has been received on the control endpoint 0, and that the setup data is available in registers. 6.33.9 Control transfers The USB specification mandates every USB device to implement endpoint 0 IN and OUT as control endpoints. A control transfer consists of two or three stages:

Each control transfer can be one of following types:

Setup stage Data stage (optional) Status stage Control read Control read no data Control write Control write no data An EP0SETUP event indicates that the data in the setup stage (following the SETUP token) is available in registers. 4452_021 v1.3 519 Peripherals The data in the data stage (following the IN or OUT token) is transferred from or to the desired location using EasyDMA. The control endpoint buffer can be of any size. After receiving the SETUP token, the USB controller will not accept (NAK) any incoming IN or OUT tokens until the software has finished decoding the command, determining the type of transfer, and preparing for the next stage (data or status) appropriately. The software can choose to stall a command (in both data and status stages) through the EP0STALL task, for instance if the command is not supported, or its wValue, wIndex or wLength parameters are wrong. A stalled control read transfer is illustrated below, but the same mechanism (same tasks) applies to stalling a control write transfer (not illustrated):

Setup stage Data stage USB host SETUP 8 bytes IN IN USB device STALL Events & tasks Software ACK E P 0 S E T U P D e c o d e s e t u p NAK E P 0 S T A L L E P 0 S T A L L

1

C o m m a n d n o t s u p p o r t e d

) See chapter 9 of the USB specification and relevant class specifications for rules on when to stall a command. Note: The USBD peripheral handles the SetAddress transfer by itself. As a consequence, the software shall not process this command other than updating its state machine (see Device state diagram), nor initiate a status stage. If necessary, the address assigned by the host can be read out from the USBADDR register after the command has been processed. 6.33.9.1 Control read transfer This section describes how the software behaves to respond to a control read transfer. As mentioned earlier, the USB controller will not accept (NAK) any incoming IN tokens until software has finished decoding the command, determining the type of transfer, and preparing for the next stage (data or status) appropriately. For a control read, transferring the data from memory into USBD will trigger a valid, acknowledged (ACK) IN transaction on USB. The software has to prepare EasyDMA by pointing to the buffer containing the data to be transferred. If no other EasyDMA transfers are on-going with USBD, the software can send the STARTEPIN0 task, which will initiate the data transfer and transaction on USB. 4452_021 v1.3 520

4

Peripherals A STARTED event (with EPIN0 bit set in the EPSTATUS register) will be generated as soon as the EPIN[0].PTR and .MAXCNT registers have been captured. Software may then prepare them for the next data transaction. An ENDEPIN[0] event will be generated when the data has been transferred from memory to the USBD peripheral. Finally, an EP0DATADONE event will be generated when the data has been transmitted over USB and acknowledged by the host. The software can then either prepare and transmit the next data transaction by repeating the above sequence, or initiate the status stage through the EP0STATUS task. Setup stage Data stage Status stage USB host SETUP 8 bytes IN IN ACK IN IN IN ACK OUT DATA (0) USB device ACK NAK NAK DATA (n) NAK NAK DATA (n+1) ACK Events & tasks Software S T A R T E D E N D E P N

0

I S T A R T E D E N D E P N

0

I E P 0 D A T A D O N E I

E P N

0

. P T R

0 x n n n n n n n n

6 4

) S T A R T E P N

0

1 I I E P N

0

. M A X C N T

M a x P a c k e t S i z e S T A R T E P N

0

I l

e n a b e E P 0 D A T A D O N E t o E P 0 S T A T U S

) E P 0 D A T A D O N E E P 0 S T A T U S E P 0 S T A T U S

1 A l l o w s t a t u s s t a g e Note the possibility to enable a shortcut from the EP0DATADONE event to the EP0STATUS task, typically if the data stage is expected to take a single transfer. If there is no data stage, the software can initiate the status stage through the EP0STATUS task right away, as illustrated below:

Setup stage Status stage USB host SETUP 8 bytes OUT DATA (0) OUT DATA (0) USB device ACK NAK ACK IN S T A R T E P N

0

I E P 0 S E T U P D e c o d e s e t u p S T A R T E P N

0

1 I I E P N

0

. P T R

0 x n n n n n n n n I E P N

0

. M A X C N T

M a x P a c k e t S i z e Events & tasks Software E P 0 S E T U P D e c o d e s e t u p E P 0 S T A T U S E P 0 S T A T U S

1 P r e p a r e f o r s t a t u s s t a g e 6.33.9.2 Control write transfer This section describes how the software responds to a control write transfer. The software has to prepare EasyDMA by pointing to the buffer in memory that shall contain the incoming data. If no other EasyDMA transfers are on-going with USBD, the software can then send the EP0RCVOUT task, which will make USBD acknowledge (ACK) the first OUT+DATA transaction from the host. An EP0DATADONE event will be generated when a new OUT+DATA has been transmitted over USB, and is about to get acknowledged by the device. 4452_021 v1.3 521

4

4

Peripherals A STARTED event (with EPOUT0 bit set in the EPSTATUS register) will be generated as soon as the EPOUT[0].PTR and .MAXCNT registers have been captured, after receiving the first transaction. Software may then prepare them for the next data transaction. An ENDEPOUT[0] event will be generated when the data has been transferred from the USBD peripheral to memory. The software can then either prepare to receive the next data transaction by repeating the above sequence, or initiate the status stage through the EP0STATUS task. Until then, further incoming OUT

+DATA transactions get a NAK response by the device. Setup stage Data stage Status stage USB host SETUP 8 bytes OUT DATA (m) OUT DATA (n) OUT DATA (n) IN IN IN ACK ACK NAK DATA (0) USB device Events & tasks Software S T A R T E D ACK E P 0 D A T A D O N E S T A R T E P O U T

0

S T A R T E P O U T

0

1 NAK E N D E P O U T

0

E P 0 R C V O U T

E P 0 R C V O U T

1

) NAK E P 0 S T A T U S E N D E P O U T

0

E P 0 S T A T U S

1

) E P 0 D A T A D O N E S T A R T E D S T A R T E P O U T

0

l

d i s a b e E P 0 D A T A D O N E t o S T A R T E P 0 O U T

) l

e n a b e E N D E P O U T

0

t o E P 0 S T A T U S

) l

d i s a b e E N D E P O U T

0

t o E P 0 R C V O U T

) ACK E P 0 S E T U P D e c o d e s e t u p E P 0 R C V O U T

1 E P 0 R C V O U T E P O U T

0

. P T R

0 x n n n n n n n n E P O U T

0

. M A X C N T

M a x P a c k e t S i z e l

e n a b e E N D E P O U T

0

t o E P 0 R C V O U T

) l

e n a b e E P 0 D A T A D O N E t o S T A R T E P 0 O U T

) Events & tasks Software Setup stage Status stage USB host SETUP 8 bytes IN IN ACK USB device ACK NAK DATA (0) E P 0 S E T U P D e c o d e s e t u p E P 0 S T A T U S E P 0 S T A T U S

1 6.33.10 Bulk and interrupt transactions The USBD peripheral implements seven pairs of bulk/interrupt endpoints. The bulk/interrupt endpoints have a fixed USB endpoint number, summarized in the table below. Bulk endpoint #

USB IN endpoint USB OUT endpoint

[1]

[2]

[3]

[4]

[5]

[6]

[7]

0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x01 0x02 0x03 0x04 0x05 0x06 0x07 A bulk/interrupt transaction consists of a single data stage. Two consecutive, successful transactions are distinguished through alternating leading process ID (PID): DATA0 follows DATA1, DATA1 follows DATA0, 4452_021 v1.3 522

4

4

6

Peripherals etc. A repeated transaction is detected by re-using the same PID as previous transaction, i.e DATA0 follows DATA0, or DATA1 follows DATA1. The USBD controller automatically toggles DATA0/DATA1 PIDs for every bulk/interrupt transaction, and in general software does not need to care about it. If an incoming data is corrupted (CRC does not match), the USBD controller automatically prevents DATA0/

DATA1 from toggling, to request the host to resend the data. In some specific cases, the software may want to force a data toggle (usually reset) on a specific IN endpoint, or force the expected toggle on an OUT endpoint, for instance as a consequence of the host issuing of data IN or OUT endpoint n (n=1..7) is done through register DTOGGLE. or selecting an alternate setting. Controlling the data toggle

, The bulk/interrupt transaction in USB full-speed can be of any size up to 64 bytes, and it has to be a multiple of 4 bytes and 32-bit aligned in memory. When the transaction is done over USB, an EPDATA event is generated. The hardware will then automatically respond with NAK to all incoming IN tokens until the software is ready to send more data and has finished configuring the EasyDMA, started it, and the whole buffer content has been moved to USB controller (signalled by the ENDEPIN[n] event). Each IN or OUT data endpoint has to be explicitly enabled by software through register EPINEN or EPOUTEN, according to the configuration declared by the device and selected by the host through the command. A disabled data endpoint will not respond to any traffic from the host. An enabled data endpoint will normally respond NAK or ACK (depending on the readiness of the buffers), or STALL (if configured in register EPSTALL), in which case the endpoint is asked to halt). The halted (or not) state of a given endpoint can be read back from register HALTED.EPIN[n] or HALTED.EPOUT[n]. The format of the returned 16-bit value can be copied as is as response to a request from the host. Note that enabling or disabling an endpoint will not change its halted state. However, a USB reset will disable and clear the halted state of all data endpoints. The control endpoint 0 IN and OUT can also be enabled and/or halted using the same mechanisms, but due to USB specification, receiving a SETUP will override its state. 6.33.10.1 Bulk and interrupt IN transaction The host issues IN tokens to receive bulk/interrupt data. In order to send data, the software has to enable the endpoint and prepare an EasyDMA transfer on the desired endpoint. Bulk/interrupt IN endpoints are enabled or disabled through their respective INn bit (n=1..7) in EPINEN register. It is also possible to stall or un-stall an endpoint through the EPSTALL register. 4452_021 v1.3 523

Peripherals USB host IN IN USB device NAK NAK S T A R T E D S T A R T E P N

1

I ACK DATA (0) E P D A T A IN E N D E P N

1

I Events & tasks Software P r e p a r e o u t g o n g d a t a i S T A R T E P N

1

1 I I

E P N

1

. P T R

0 x n n n n n n n n I E P N

1

. M A X C N T

M a x P a c k e t S i z e It is possible (and in some situations it is required) to respond to an IN token with a zero-length data packet. Note: On many USB hosts, not responding (DATA+ACK or NAK) to three IN tokens on an interrupt endpoint would have the host disable that endpoint as a consequence. Re-enumerating the device (unplug-replug) may be required to restore functionality. Make sure that the relevant data endpoints are enabled for normal operation as soon as the device gets configured through a request. 6.33.10.2 Bulk and interrupt OUT transaction When the host wants to transmit bulk/interrupt data, it issues an OUT token (packet) followed by a DATA packet on a given endpoint n (n=1..7). A NAK is returned until the software writes any value to register SIZE.EPOUT[n], indicating that the content of the local buffer can be overwritten. Upon receiving the next OUT+DATA transaction, an ACK is returned to the host while an EPDATA event is generated (and the EPDATASTATUS register flags are set to indicate on which endpoint this happened). Once the EasyDMA is prepared and enabled, by writing the EPOUT[n]

registers and triggering the STARTEPOUT[n] task, the incoming data will be transferred to memory. Until that transfer is finished, the hardware will automatically NAK any other incoming OUT+DATA packets. Only when the EasyDMA transfer is done (signalled by the ENDEPOUT[n] event), or as soon as any values are written by the software in register SIZE.EPOUT[n], the endpoint n will accept incoming OUT+DATA again. It is allowed for the host to send zero-length data packets. Bulk/interrupt OUT endpoints are enabled or disabled through their respective OUTn bit (n=1..7) in the EPOUTEN register. It is also possible to stall or un-stall an endpoint through the EPSTALL register. 4452_021 v1.3 524

8

1

USB host OUT DATA (n) OUT DATA (n) OUT DATA (n+1) OUT DATA (n+1) USB device NAK ACK NAK ACK Peripherals Events & tasks Software S I Z E

. E P O U T

1

0 E P D A T A E N D E P O U T

1

P r o c e s s d a t a E P D A T A S T A R T E P O U T

1

S T A R T E D S T A R T E P O U T

1

1 E P O U T

1

. P T R

0 x n n n n n n n n E P O U T

1

. M A X C N T

S I Z E

. E P O U T

1

E P D A T A S T A T U S

. E P O U T 1 s e t

S t a r t e d

) 6.33.11 Isochronous transactions The USBD peripheral implements isochronous (ISO) endpoints. The ISO endpoints have a fixed USB endpoint number, summarized in the table below. ISO endpoint #

[0]

USB IN endpoint 0x88 USB OUT endpoint 0x08 An isochronous transaction consists of a single, non-acknowledged data stage. The host sends out a start of frame at a regular interval (1 ms), and data follows IN or OUT tokens within each frame. EasyDMA allows transferring ISO data directly from and to memory. EasyDMA transfers must be initiated by the software, which can synchronize with the SOF (start of frame) events. Because the timing of the start of frame is very accurate, the SOF event can be used for instance to synchronize a local timer through the SOF event and PPI. The SOF event gets synchronized to the 16 MHz clock prior to being made available to the PPI. Every start of frame increments a free-running counter, which can be read by software through the FRAMECNTR register. Each IN or OUT ISO data endpoint has to be explicitly enabled by software through register EPINEN or EPOUTEN, according to the configuration declared by the device and selected by the host through the command. A disabled ISO IN data endpoint will not respond to any traffic from the host. A disabled ISO OUT data endpoint will ignore any incoming traffic from the host. The USBD peripheral has an internal 1 kB buffer associated with ISO endpoints. The user can either allocate the full amount to the IN or the OUT endpoint, or split the buffer allocation between the two using register ISOSPLIT. The internal buffer also sets the maximum size of the ISO OUT and ISO IN transfers: 1023 bytes when the full buffer is dedicated to either ISO OUT or ISO IN, and half when the buffer is split between the two. 6.33.11.1 Isochronous IN transaction When the host wants to receive isochronous (ISO) data, it issues an IN token on the isochronous endpoint. After the data has been transferred using the EasyDMA, the USB controller on the isochronous IN endpoint responds to the IN token with the transferred data using the ISOIN.MAXCNT for the size of the packet. 4452_021 v1.3 525

8

Peripherals The ISO IN data endpoint has to be explicitly enabled by software through the ISOIN0 bit in register EPINEN. When an ISO IN endpoint is enabled and no data transferred with EasyDMA, the response of the USBD depends on the setting of the RESPONSE field in register ISOINCONFIG - it can either provide no response to an IN token or respond with a zero-length data. If the EasyDMA transfer on the isochronous endpoint is not completed before the next SOF event, the result of the transfer is undefined. The maximum size of an ISO IN transfer in USB full-speed is 1023 bytes, and the data buffer has to be a multiple of 4 bytes 32-bit aligned in memory. However, the amount of bytes transferred on the USB data endpoint can be of any size (up to 1023 bytes, if not shared with an OUT ISO endpoint). Start of frame Start of frame USB host IN response depends on the RESPONSE field in the ISOINCONFIG register IN USB device DATA(0) S O F S T A R T I S O N I S T A R T E D E N D I S O N I Events & tasks Software DATA n S T A R T I S O N I S T A R T I S O N

1 I I

. I S O N M A X C N T

y y I

. I S O N P T R

0 x n n n n n n n n S O F i P r e p a r e o u t g o n g I S O d a t a n

1 S T A R T I S O N

1 I I

. I S O N M A X C N T

y y I

. I S O N P T R

0 x n n n n n n n n P r e p a r e o u t g o n g I S O d a t a n i 6.33.11.2 Isochronous OUT transaction When the host wants to send isochronous (ISO) data, it issues an OUT token on the isochronous endpoint, followed by data. The ISO OUT data endpoint has to be explicitly enabled by software through the ISOOUT0 bit in register EPOUTEN. The amount of last received ISO OUT data is provided in the SIZE.ISOOUT register. Software shall interpret the ZERO and SIZE fields as follows:

ZERO Normal Normal ZeroData SIZE 0 1..1023

(not of interest) Last received data size No data received at all 1..1023 bytes of data received Zero-length data packet received When EasyDMA is prepared and started, triggering a STARTISOOUT task initiates an EasyDMA transfer to memory. Software shall synchronize ISO OUT transfers with the SOF events. EasyDMA uses the address in ISOOUT.PTR and size in ISOOUT.MAXCNT for every new transfer. If the EasyDMA transfer on the isochronous endpoint is not completed before the next SOF event, the result of the transfer is undefined. The maximum size of an isochronous OUT transfer in USB full-speed is 1023 bytes, and the data buffer has to be a multiple of 4 bytes and 32-bit aligned in Data RAM. However, the amount of bytes transferred on the USB data endpoint can be of any size (up to 1023 bytes if not shared with an IN ISO endpoint). 4452_021 v1.3 526

1

5

9

9

C

D

Peripherals If the last received ISO data packet is corrupted (wrong CRC), the USB controller generates an USBEVENT event (at the same time as SOF) and indicates a CRC error on ISOOUTCRC in register EVENTCAUSE. EasyDMA will transfer the data anyway if it has been set up properly. Start of frame Start of frame Start of frame USB host OUT DATA n OUT DATA n+1 OUT DATA n+2 USB device S O F Events & tasks Software I S O O U T

. P T R

0 x n n n n n n n n P r e p a r e f o r r e c e i v i n g I S O d a t a n

I S O O U T

. M A X C N T

S I Z E

. I S O O U T

) l

e n a b e S O F t o S T A R T I S O O U T

) S O F S T A R T I S O O U T

S T A R T I S O O U T

1

) I S O O U T

. M A X C N T

S I Z E

. I S O O U T S T A R T E D I S O O U T

. M A X C N T

S I Z E

. I S O O U T I S O O U T

. P T R

0 x n n n n n n n n

s i z e S T A R T I S O O U T S O F E N D I S O O U T P r o c e s s d a t a 6.33.12 USB register access limitations Some of the registers in USBD cannot be accessed in specific conditions. This may be the case when USBD is not enabled (using the ENABLE register) and ready (signalled by the READY bit in EVENTCAUSE after a USBEVENT event), or when USBD is in low power mode while the USB bus is suspended. Triggering any tasks, including the tasks triggered through the PPI, is affected by this behavior. In addition, the following registers are affected:

HALTED.EPIN[0..7]

HALTED.EPOUT[0..7]

USBADDR BMREQUESTTYPE BREQUEST WVALUEL WVALUEH WINDEXL WINDEXH WLENGTHL WLENGTHH SIZE.EPOUT[0..7]

SIZE.ISOOUT USBPULLUP DTOGGLE 4452_021 v1.3 527

0

Peripherals EPINEN EPOUTEN EPSTALL ISOSPLIT FRAMECNTR 6.33.13 Registers Base address Peripheral Instance Description Configuration 0x40027000 USBD USBD Universal serial bus device Register Description Offset 0x004 TASKS_STARTEPIN[0]

Captures the EPIN[0].PTR and EPIN[0].MAXCNT registers values, and enables endpoint IN 0 to TASKS_STARTEPIN[1]

0x008 Captures the EPIN[1].PTR and EPIN[1].MAXCNT registers values, and enables endpoint IN 1 to TASKS_STARTEPIN[2]

0x00C Captures the EPIN[2].PTR and EPIN[2].MAXCNT registers values, and enables endpoint IN 2 to TASKS_STARTEPIN[3]

0x010 Captures the EPIN[3].PTR and EPIN[3].MAXCNT registers values, and enables endpoint IN 3 to TASKS_STARTEPIN[4]

0x014 Captures the EPIN[4].PTR and EPIN[4].MAXCNT registers values, and enables endpoint IN 4 to TASKS_STARTEPIN[5]

0x018 Captures the EPIN[5].PTR and EPIN[5].MAXCNT registers values, and enables endpoint IN 5 to TASKS_STARTEPIN[6]

0x01C Captures the EPIN[6].PTR and EPIN[6].MAXCNT registers values, and enables endpoint IN 6 to TASKS_STARTEPIN[7]

0x020 Captures the EPIN[7].PTR and EPIN[7].MAXCNT registers values, and enables endpoint IN 7 to TASKS_STARTISOIN 0x024 Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO TASKS_STARTEPOUT[0]

0x028 Captures the EPOUT[0].PTR and EPOUT[0].MAXCNT registers values, and enables endpoint 0 to TASKS_STARTEPOUT[1]

0x02C Captures the EPOUT[1].PTR and EPOUT[1].MAXCNT registers values, and enables endpoint 1 to TASKS_STARTEPOUT[2]

0x030 Captures the EPOUT[2].PTR and EPOUT[2].MAXCNT registers values, and enables endpoint 2 to TASKS_STARTEPOUT[3]

0x034 Captures the EPOUT[3].PTR and EPOUT[3].MAXCNT registers values, and enables endpoint 3 to TASKS_STARTEPOUT[4]

0x038 Captures the EPOUT[4].PTR and EPOUT[4].MAXCNT registers values, and enables endpoint 4 to TASKS_STARTEPOUT[5]

0x03C Captures the EPOUT[5].PTR and EPOUT[5].MAXCNT registers values, and enables endpoint 5 to TASKS_STARTEPOUT[6]

0x040 Captures the EPOUT[6].PTR and EPOUT[6].MAXCNT registers values, and enables endpoint 6 to TASKS_STARTEPOUT[7]

0x044 Captures the EPOUT[7].PTR and EPOUT[7].MAXCNT registers values, and enables endpoint 7 to TASKS_STARTISOOUT 0x048 Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data respond to traffic from host respond to traffic from host respond to traffic from host respond to traffic from host respond to traffic from host respond to traffic from host respond to traffic from host respond to traffic from host endpoint respond to traffic from host respond to traffic from host respond to traffic from host respond to traffic from host respond to traffic from host respond to traffic from host respond to traffic from host respond to traffic from host on ISO endpoint TASKS_EP0RCVOUT TASKS_EP0STATUS TASKS_EP0STALL 0x04C 0x050 0x054 Allows OUT data stage on control endpoint 0 Allows status stage on control endpoint 0 Stalls data and status stage on control endpoint 0 4452_021 v1.3 528

Peripherals Register TASKS_DPDMDRIVE TASKS_DPDMNODRIVE EVENTS_USBRESET EVENTS_STARTED EVENTS_ENDEPIN[0]

EVENTS_ENDEPIN[1]

EVENTS_ENDEPIN[2]

EVENTS_ENDEPIN[3]

EVENTS_ENDEPIN[4]

EVENTS_ENDEPIN[5]

EVENTS_ENDEPIN[6]

EVENTS_ENDEPIN[7]

EVENTS_EP0DATADONE EVENTS_ENDISOIN EVENTS_ENDEPOUT[0]

Description Forces D+ and D- lines into the state defined in the DPDMVALUE register Stops forcing D+ and D- lines into any state (USB engine takes control) Signals that a USB reset condition has been detected on USB lines Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register The whole EPIN[0] buffer has been consumed. The buffer can be accessed safely by software. The whole EPIN[1] buffer has been consumed. The buffer can be accessed safely by software. The whole EPIN[2] buffer has been consumed. The buffer can be accessed safely by software. The whole EPIN[3] buffer has been consumed. The buffer can be accessed safely by software. The whole EPIN[4] buffer has been consumed. The buffer can be accessed safely by software. The whole EPIN[5] buffer has been consumed. The buffer can be accessed safely by software. The whole EPIN[6] buffer has been consumed. The buffer can be accessed safely by software. The whole EPIN[7] buffer has been consumed. The buffer can be accessed safely by software. An acknowledged data transfer has taken place on the control endpoint The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. The whole EPOUT[0] buffer has been consumed. The buffer can be accessed safely by EVENTS_ENDEPOUT[1]

0x134 The whole EPOUT[1] buffer has been consumed. The buffer can be accessed safely by EVENTS_ENDEPOUT[2]

0x138 The whole EPOUT[2] buffer has been consumed. The buffer can be accessed safely by EVENTS_ENDEPOUT[3]

0x13C The whole EPOUT[3] buffer has been consumed. The buffer can be accessed safely by EVENTS_ENDEPOUT[4]

0x140 The whole EPOUT[4] buffer has been consumed. The buffer can be accessed safely by EVENTS_ENDEPOUT[5]

0x144 The whole EPOUT[5] buffer has been consumed. The buffer can be accessed safely by EVENTS_ENDEPOUT[6]

0x148 The whole EPOUT[6] buffer has been consumed. The buffer can be accessed safely by EVENTS_ENDEPOUT[7]

0x14C The whole EPOUT[7] buffer has been consumed. The buffer can be accessed safely by software. software. software. software. software. software. software. software. EVENTS_ENDISOOUT EVENTS_SOF EVENTS_USBEVENT EVENTS_EP0SETUP EVENTS_EPDATA SHORTS INTEN INTENSET INTENCLR EVENTCAUSE HALTED.EPIN[0]

HALTED.EPIN[1]

HALTED.EPIN[2]

HALTED.EPIN[3]

HALTED.EPIN[4]

HALTED.EPIN[5]

HALTED.EPIN[6]

HALTED.EPIN[7]

The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. Signals that a SOF (start of frame) condition has been detected on USB lines An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. A valid SETUP token has been received (and acknowledged) on the control endpoint A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register Shortcuts between local events and tasks Enable or disable interrupt Enable interrupt Disable interrupt Details on what caused the USBEVENT event IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. Offset 0x058 0x05C 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x150 0x154 0x158 0x15C 0x160 0x200 0x300 0x304 0x308 0x400 0x420 0x424 0x428 0x42C 0x430 0x434 0x438 0x43C 0x444 HALTED.EPOUT[0]

OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. 4452_021 v1.3 529 Peripherals Register HALTED.EPOUT[1]

Offset 0x448 Description OUT endpoint halted status. Can be used as is as response to a GetStatus() request to HALTED.EPOUT[2]

0x44C OUT endpoint halted status. Can be used as is as response to a GetStatus() request to HALTED.EPOUT[3]

0x450 OUT endpoint halted status. Can be used as is as response to a GetStatus() request to HALTED.EPOUT[4]

0x454 OUT endpoint halted status. Can be used as is as response to a GetStatus() request to HALTED.EPOUT[5]

0x458 OUT endpoint halted status. Can be used as is as response to a GetStatus() request to HALTED.EPOUT[6]

0x45C OUT endpoint halted status. Can be used as is as response to a GetStatus() request to HALTED.EPOUT[7]

0x460 OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. endpoint. endpoint. endpoint. endpoint. endpoint. endpoint. Provides information on which endpoint's EasyDMA registers have been captured Provides information on which endpoint(s) an acknowledged data transfer has occurred EPSTATUS EPDATASTATUS USBADDR BMREQUESTTYPE BREQUEST WVALUEL WVALUEH WINDEXL WINDEXH WLENGTHL WLENGTHH SIZE.EPOUT[0]

SIZE.EPOUT[1]

SIZE.EPOUT[2]

SIZE.EPOUT[3]

SIZE.EPOUT[4]

SIZE.EPOUT[5]

SIZE.EPOUT[6]

SIZE.EPOUT[7]

SIZE.ISOOUT ENABLE USBPULLUP DPDMVALUE DTOGGLE EPINEN EPOUTEN EPSTALL ISOSPLIT FRAMECNTR LOWPOWER ISOINCONFIG EPIN[0].PTR EPIN[0].MAXCNT EPIN[0].AMOUNT EPIN[1].PTR EPIN[1].MAXCNT EPIN[1].AMOUNT 0x468 0x46C 0x470 0x480 0x484 0x488 0x48C 0x490 0x494 0x498 0x49C 0x4A0 0x4A4 0x4A8 0x4AC 0x4B0 0x4B4 0x4B8 0x4BC 0x4C0 0x500 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0x520 0x52C 0x530 0x600 0x604 0x608 0x614 0x618 0x61C

(EPDATA event) Device USB address SETUP data, byte 0, bmRequestType SETUP data, byte 1, bRequest SETUP data, byte 2, LSB of wValue SETUP data, byte 3, MSB of wValue SETUP data, byte 4, LSB of wIndex SETUP data, byte 5, MSB of wIndex SETUP data, byte 6, LSB of wLength SETUP data, byte 7, MSB of wLength Number of bytes received last in the data stage of this OUT endpoint Number of bytes received last in the data stage of this OUT endpoint Number of bytes received last in the data stage of this OUT endpoint Number of bytes received last in the data stage of this OUT endpoint Number of bytes received last in the data stage of this OUT endpoint Number of bytes received last in the data stage of this OUT endpoint Number of bytes received last in the data stage of this OUT endpoint Number of bytes received last in the data stage of this OUT endpoint Number of bytes received last on this ISO OUT data endpoint Enable USB Control of the USB pull-up Data toggle control and status Endpoint IN enable Endpoint OUT enable STALL endpoints Controls the split of ISO buffers State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). Returns the current value of the start of frame counter Controls USBD peripheral low power mode during USB suspend Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent Data pointer Data pointer Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction 4452_021 v1.3 530 Peripherals Register EPIN[2].PTR EPIN[2].MAXCNT EPIN[2].AMOUNT EPIN[3].PTR EPIN[3].MAXCNT EPIN[3].AMOUNT EPIN[4].PTR EPIN[4].MAXCNT EPIN[4].AMOUNT EPIN[5].PTR EPIN[5].MAXCNT EPIN[5].AMOUNT EPIN[6].PTR EPIN[6].MAXCNT EPIN[6].AMOUNT EPIN[7].PTR EPIN[7].MAXCNT EPIN[7].AMOUNT ISOIN.PTR ISOIN.MAXCNT ISOIN.AMOUNT EPOUT[0].PTR EPOUT[0].MAXCNT EPOUT[0].AMOUNT EPOUT[1].PTR EPOUT[1].MAXCNT EPOUT[1].AMOUNT EPOUT[2].PTR EPOUT[2].MAXCNT EPOUT[2].AMOUNT EPOUT[3].PTR EPOUT[3].MAXCNT EPOUT[3].AMOUNT EPOUT[4].PTR EPOUT[4].MAXCNT EPOUT[4].AMOUNT EPOUT[5].PTR EPOUT[5].MAXCNT EPOUT[5].AMOUNT EPOUT[6].PTR EPOUT[6].MAXCNT EPOUT[6].AMOUNT EPOUT[7].PTR EPOUT[7].MAXCNT EPOUT[7].AMOUNT ISOOUT.PTR ISOOUT.MAXCNT ISOOUT.AMOUNT Offset 0x628 0x62C 0x630 0x63C 0x640 0x644 0x650 0x654 0x658 0x664 0x668 0x66C 0x678 0x67C 0x680 0x68C 0x690 0x694 0x6A0 0x6A4 0x6A8 0x700 0x704 0x708 0x714 0x718 0x71C 0x728 0x72C 0x730 0x73C 0x740 0x744 0x750 0x754 0x758 0x764 0x768 0x76C 0x778 0x77C 0x780 0x78C 0x790 0x794 0x7A0 0x7A4 0x7A8 Description Data pointer Data pointer Data pointer Data pointer Data pointer Data pointer Data pointer Data pointer Data pointer Data pointer Data pointer Data pointer Data pointer Data pointer Data pointer Data pointer Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction Maximum number of bytes to transfer Number of bytes transferred in the last transaction 6.33.13.1 TASKS_STARTEPIN[n] (n=0..7) Address offset: 0x004 + (n 0x4) 4452_021 v1.3 531

Peripherals Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTEPIN Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from Trigger 1 host Trigger task 6.33.13.2 TASKS_STARTISOIN Address offset: 0x024 Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTISOIN Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, Trigger 1 Trigger task and enables sending data on ISO endpoint 6.33.13.3 TASKS_STARTEPOUT[n] (n=0..7) Address offset: 0x028 + (n 0x4) Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTEPOUT Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to Trigger 1 traffic from host Trigger task 6.33.13.4 TASKS_STARTISOOUT Address offset: 0x048 Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint A A A 4452_021 v1.3 532 ID ID A ID ID A ID ID A ID ID A Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_STARTISOOUT Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint Trigger 1 Trigger task 6.33.13.5 TASKS_EP0RCVOUT Address offset: 0x04C Allows OUT data stage on control endpoint 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_EP0RCVOUT Allows OUT data stage on control endpoint 0 Trigger 1 Trigger task 6.33.13.6 TASKS_EP0STATUS Address offset: 0x050 Allows status stage on control endpoint 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_EP0STATUS Allows status stage on control endpoint 0 Trigger 1 Trigger task 6.33.13.7 TASKS_EP0STALL Address offset: 0x054 Stalls data and status stage on control endpoint 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_EP0STALL Stalls data and status stage on control endpoint 0 Trigger 1 Trigger task 6.33.13.8 TASKS_DPDMDRIVE Address offset: 0x058 Forces D+ and D- lines into the state defined in the DPDMVALUE register A A A A 4452_021 v1.3 533 ID ID A ID ID A ID ID A ID ID A Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_DPDMDRIVE Forces D+ and D- lines into the state defined in the Trigger 1 Trigger task DPDMVALUE register 6.33.13.9 TASKS_DPDMNODRIVE Address offset: 0x05C Stops forcing D+ and D- lines into any state (USB engine takes control) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_DPDMNODRIVE Stops forcing D+ and D- lines into any state (USB engine Trigger 1 takes control) Trigger task 6.33.13.10 EVENTS_USBRESET Address offset: 0x100 Signals that a USB reset condition has been detected on USB lines Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_USBRESET Signals that a USB reset condition has been detected on NotGenerated Generated 0 1 USB lines Event not generated Event generated 6.33.13.11 EVENTS_STARTED Address offset: 0x104 Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_STARTED Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register NotGenerated Generated 0 1 Event not generated Event generated A A A A 4452_021 v1.3 534 Peripherals ID ID A ID ID A ID ID A 6.33.13.12 EVENTS_ENDEPIN[n] (n=0..7) Address offset: 0x108 + (n 0x4) The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ENDEPIN The whole EPIN[n] buffer has been consumed. The buffer NotGenerated Generated can be accessed safely by software. Event not generated Event generated 6.33.13.13 EVENTS_EP0DATADONE Address offset: 0x128 An acknowledged data transfer has taken place on the control endpoint Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_EP0DATADONE An acknowledged data transfer has taken place on the NotGenerated Generated control endpoint Event not generated Event generated 6.33.13.14 EVENTS_ENDISOIN Address offset: 0x12C The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ENDISOIN The whole ISOIN buffer has been consumed. The buffer can NotGenerated Generated be accessed safely by software. Event not generated Event generated 6.33.13.15 EVENTS_ENDEPOUT[n] (n=0..7) Address offset: 0x130 + (n 0x4) The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. 0 1 0 1 0 1 A A A 4452_021 v1.3 535 Peripherals 0 1 0 1 0 1 ID ID A ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ENDEPOUT The whole EPOUT[n] buffer has been consumed. The buffer NotGenerated Generated can be accessed safely by software. Event not generated Event generated 6.33.13.16 EVENTS_ENDISOOUT Address offset: 0x150 The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_ENDISOOUT The whole ISOOUT buffer has been consumed. The buffer NotGenerated Generated can be accessed safely by software. Event not generated Event generated 6.33.13.17 EVENTS_SOF Address offset: 0x154 Signals that a SOF (start of frame) condition has been detected on USB lines Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_SOF Signals that a SOF (start of frame) condition has been NotGenerated Generated detected on USB lines Event not generated Event generated 6.33.13.18 EVENTS_USBEVENT Address offset: 0x158 An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_USBEVENT An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. NotGenerated Generated 0 1 Event not generated Event generated A A A A 4452_021 v1.3 536 ID ID A ID ID A ID ID A Peripherals 6.33.13.19 EVENTS_EP0SETUP Address offset: 0x15C A valid SETUP token has been received (and acknowledged) on the control endpoint Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_EP0SETUP A valid SETUP token has been received (and acknowledged) NotGenerated Generated on the control endpoint Event not generated Event generated 6.33.13.20 EVENTS_EPDATA Address offset: 0x160 A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_EPDATA A data transfer has occurred on a data endpoint, indicated NotGenerated Generated by the EPDATASTATUS register Event not generated Event generated A A 6.33.13.21 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EP0DATADONE_STARTEPIN0 Shortcut between event EP0DATADONE and task Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled B RW EP0DATADONE_STARTEPOUT0 Shortcut between event EP0DATADONE and task C RW EP0DATADONE_EP0STATUS Shortcut between event EP0DATADONE and task EP0STATUS D RW ENDEPOUT0_EP0STATUS Shortcut between event ENDEPOUT[0] and task EP0STATUS E RW ENDEPOUT0_EP0RCVOUT Shortcut between event ENDEPOUT[0] and task EP0RCVOUT 4452_021 v1.3 537 STARTEPIN[0]

Disable shortcut Enable shortcut STARTEPOUT[0]

Disable shortcut Enable shortcut Disable shortcut Enable shortcut Disable shortcut Enable shortcut 0 1 0 1 0 1 0 1 0 1 0 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Peripherals E D C B A Value ID Disabled Enabled Value 0 1 Description Disable shortcut Enable shortcut 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event USBRESET Bit number ID Reset 0x00000000 ID AccessField 6.33.13.22 INTEN Address offset: 0x300 Enable or disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW USBRESET B RW STARTED Enable or disable interrupt for event STARTED C-J RW ENDEPIN[i] (i=0..7) Enable or disable interrupt for event ENDEPIN[i]

K RW EP0DATADONE Enable or disable interrupt for event EP0DATADONE L RW ENDISOIN Enable or disable interrupt for event ENDISOIN M-T RW ENDEPOUT[i] (i=0..7) Enable or disable interrupt for event ENDEPOUT[i]

U RW ENDISOOUT Enable or disable interrupt for event ENDISOOUT V RW SOF Enable or disable interrupt for event SOF W RW USBEVENT Enable or disable interrupt for event USBEVENT X RW EP0SETUP Enable or disable interrupt for event EP0SETUP Y RW EPDATA Enable or disable interrupt for event EPDATA Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6.33.13.23 INTENSET Address offset: 0x304 4452_021 v1.3 538 Peripherals Enable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW USBRESET 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event USBRESET B RW STARTED Write '1' to enable interrupt for event STARTED C-J RW ENDEPIN[i] (i=0..7) Write '1' to enable interrupt for event ENDEPIN[i]

K RW EP0DATADONE Write '1' to enable interrupt for event EP0DATADONE L RW ENDISOIN Write '1' to enable interrupt for event ENDISOIN M-T RW ENDEPOUT[i] (i=0..7) Write '1' to enable interrupt for event ENDEPOUT[i]

U RW ENDISOOUT Write '1' to enable interrupt for event ENDISOOUT V RW SOF Write '1' to enable interrupt for event SOF W RW USBEVENT Write '1' to enable interrupt for event USBEVENT X RW EP0SETUP Write '1' to enable interrupt for event EP0SETUP Y RW EPDATA Write '1' to enable interrupt for event EPDATA Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Enable Read: Disabled Read: Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled Set Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 6.33.13.24 INTENCLR Address offset: 0x308 4452_021 v1.3 539 Peripherals Disable interrupt Bit number ID ID A Reset 0x00000000 AccessField RW USBRESET 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Y X W V U T S R Q P O N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event USBRESET B RW STARTED Write '1' to disable interrupt for event STARTED C-J RW ENDEPIN[i] (i=0..7) Write '1' to disable interrupt for event ENDEPIN[i]

K RW EP0DATADONE Write '1' to disable interrupt for event EP0DATADONE L RW ENDISOIN Write '1' to disable interrupt for event ENDISOIN M-T RW ENDEPOUT[i] (i=0..7) Write '1' to disable interrupt for event ENDEPOUT[i]

U RW ENDISOOUT Write '1' to disable interrupt for event ENDISOOUT V RW SOF Write '1' to disable interrupt for event SOF W RW USBEVENT Write '1' to disable interrupt for event USBEVENT X RW EP0SETUP Write '1' to disable interrupt for event EP0SETUP Y RW EPDATA Write '1' to disable interrupt for event EPDATA Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Disable Read: Disabled Read: Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled Clear Disabled Enabled 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 6.33.13.25 EVENTCAUSE Address offset: 0x400 4452_021 v1.3 540 ID ID A ID ID A Peripherals Details on what caused the USBEVENT event Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW ISOOUTCRC CRC error was detected on isochronous OUT endpoint 8. B RW SUSPEND C RW RESUME E RW READY NotDetected Detected NotDetected Detected NotDetected Detected NotAllowed Allowed NotDetected Ready Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. Write '1' to clear. No error detected Error detected Suspend not detected Suspend detected Resume not detected Resume detected clear. Wake up not allowed Wake up allowed USB device is ready for normal operation. Write '1' to clear. USBEVENT was not issued due to USBD peripheral ready USBD peripheral is ready D RW USBWUALLOWED USB MAC has been woken up and operational. Write '1' to 6.33.13.26 HALTED.EPIN[n] (n=0..7) Address offset: 0x420 + (n 0x4) IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R GETSTATUS IN endpoint halted status. Can be used as is as response to a NotHalted Halted GetStatus() request to endpoint. Endpoint is not halted Endpoint is halted 6.33.13.27 HALTED.EPOUT[n] (n=0..7) Address offset: 0x444 + (n 0x4) OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. 0 1 0 1 0 1 0 1 0 1 0 1 4452_021 v1.3 541 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R GETSTATUS OUT endpoint halted status. Can be used as is as response NotHalted Halted to a GetStatus() request to endpoint. Endpoint is not halted Endpoint is halted 6.33.13.28 EPSTATUS Address offset: 0x468 Provides information on which endpoint's EasyDMA registers have been captured Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Q P O N M L K J I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EPIN[i] (i=0..8) Captured state of endpoint's EasyDMA registers. Write '1' to ID ID A ID ID A-I clear. clear. EasyDMA registers have not been captured for this endpoint EasyDMA registers have been captured for this endpoint Captured state of endpoint's EasyDMA registers. Write '1' to EasyDMA registers have not been captured for this endpoint EasyDMA registers have been captured for this endpoint Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 N M L K J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A-G RW EPIN[i] (i=1..7) Acknowledged data transfer on this IN endpoint. Write '1' to Value ID Value Description No acknowledged data transfer on this endpoint Acknowledged data transfer on this endpoint has occurred Acknowledged data transfer on this OUT endpoint. Write '1'

clear. to clear. No acknowledged data transfer on this endpoint Acknowledged data transfer on this endpoint has occurred NoData DataDone NoData DataDone NotDone DataDone NotStarted Started J-R RW EPOUT[i] (i=0..8) 6.33.13.29 EPDATASTATUS Address offset: 0x46C Bit number ID Reset 0x00000000 ID AccessField H-N RW EPOUT[i] (i=1..7) 6.33.13.30 USBADDR Address offset: 0x470 Device USB address 0 1 0 1 0 1 0 1 0 1 4452_021 v1.3 542 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R ADDR Value ID Value Description Device USB address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Peripherals A A A A A A A 6.33.13.31 BMREQUESTTYPE Address offset: 0x480 SETUP data, byte 0, bmRequestType Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R RECIPIENT Value ID Value Description Data transfer type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C B B A A A A A B R TYPE Data transfer type Device Interface Endpoint Other Standard Class Vendor HostToDevice DeviceToHost 0 1 2 3 0 1 2 0 1 Device Interface Endpoint Other Standard Class Vendor Data transfer direction Host-to-device Device-to-host C R DIRECTION 6.33.13.32 BREQUEST Address offset: 0x484 SETUP data, byte 1, bRequest Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R BREQUEST SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor ID ID A ID ID A ID ID A STD_GET_STATUS STD_CLEAR_FEATURE STD_SET_FEATURE STD_SET_ADDRESS STD_GET_DESCRIPTOR STD_SET_DESCRIPTOR 0 1 3 5 6 7 values. Standard request GET_STATUS Standard request CLEAR_FEATURE Standard request SET_FEATURE Standard request SET_ADDRESS Standard request GET_DESCRIPTOR Standard request SET_DESCRIPTOR STD_GET_CONFIGURATION8 Standard request GET_CONFIGURATION STD_SET_CONFIGURATION9 Standard request SET_CONFIGURATION STD_GET_INTERFACE STD_SET_INTERFACE STD_SYNCH_FRAME 10 11 12 Standard request GET_INTERFACE Standard request SET_INTERFACE Standard request SYNCH_FRAME 4452_021 v1.3 543 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R WVALUEL Value ID Value Description SETUP data, byte 2, LSB of wValue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A 6.33.13.33 WVALUEL Address offset: 0x488 SETUP data, byte 2, LSB of wValue 6.33.13.34 WVALUEH Address offset: 0x48C SETUP data, byte 3, MSB of wValue 6.33.13.35 WINDEXL Address offset: 0x490 SETUP data, byte 4, LSB of wIndex 6.33.13.36 WINDEXH Address offset: 0x494 SETUP data, byte 5, MSB of wIndex 6.33.13.37 WLENGTHL Address offset: 0x498 SETUP data, byte 6, LSB of wLength ID ID A ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R WVALUEH Value ID Value Description SETUP data, byte 3, MSB of wValue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R WINDEXL Value ID Value Description SETUP data, byte 4, LSB of wIndex 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R WINDEXH Value ID Value Description SETUP data, byte 5, MSB of wIndex 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A 4452_021 v1.3 544 ID ID A ID ID A ID ID A ID ID A B Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R WLENGTHL SETUP data, byte 6, LSB of wLength Peripherals A A A A A A A A 6.33.13.38 WLENGTHH Address offset: 0x49C SETUP data, byte 7, MSB of wLength Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R WLENGTHH SETUP data, byte 7, MSB of wLength 6.33.13.39 SIZE.EPOUT[n] (n=0..7) Address offset: 0x4A0 + (n 0x4) Number of bytes received last in the data stage of this OUT endpoint Write to any value to accept further OUT traffic on this endpoint, and overwrite the intermediate buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW SIZE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A Value ID Value Description Number of bytes received last in the data stage of this OUT endpoint 6.33.13.40 SIZE.ISOOUT Address offset: 0x4C0 Number of bytes received last on this ISO OUT data endpoint Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B A A A A A A A A A A Reset 0x00010000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Number of bytes received last on this ISO OUT data endpoint Zero-length data packet received Normal ZeroData 0 1 No zero-length data received, use value in SIZE Zero-length data received, ignore value in SIZE AccessField SIZE R R ZERO 6.33.13.41 ENABLE Address offset: 0x500 Enable USB 4452_021 v1.3 545 Peripherals A A After writing Disabled to this register, reading the register will return Enabled until USBD is completely disabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Disabled Enabled Description Enable USB USB peripheral is disabled USB peripheral is enabled Bit number ID ID A Reset 0x00000000 AccessField RW ENABLE Bit number ID ID A Reset 0x00000000 AccessField RW CONNECT 6.33.13.42 USBPULLUP Address offset: 0x504 Control of the USB pull-up 6.33.13.43 DPDMVALUE Address offset: 0x508 Bit number ID ID A Reset 0x00000000 AccessField RW STATE Resume J K 6.33.13.44 DTOGGLE Address offset: 0x50C Data toggle control and status 0 1 0 1 1 2 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled Enabled Control of the USB pull-up on the D+ line Pull-up is disconnected Pull-up is connected to D+

State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description State D+ and D- lines will be forced into by the DPDMDRIVE task D+ forced low, D- forced high (K state) for a timing preset in hardware (50 s or 5 ms, depending on bus state) D+ forced high, D- forced low (J state) D+ forced low, D- forced high (K state) Write this register first with VALUE=Nop to select the endpoint; then read it to get the status from VALUE, or write it again with VALUE=Data0 or Data1 4452_021 v1.3 546 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Value ID Value Description Peripherals C C B A A A Select bulk endpoint number Selects IN or OUT endpoint Selects OUT endpoint Selects IN endpoint Data toggle value No action on data toggle when writing the register with this value Data toggle is DATA0 on endpoint set by EP and IO Data toggle is DATA1 on endpoint set by EP and IO ID ID A B AccessField RW EP RW IO C RW VALUE Out In Nop Data0 Data1 Disable Enable Disable Enable Disable Enable Disable Enable 6.33.13.45 EPINEN Address offset: 0x510 Endpoint IN enable Bit number ID Reset 0x00000001 ID AccessField A-H RW IN[i] (i=0..7) I RW ISOIN 6.33.13.46 EPOUTEN Address offset: 0x514 Endpoint OUT enable Bit number ID Reset 0x00000001 ID AccessField I RW ISOOUT 6.33.13.47 EPSTALL Address offset: 0x518 STALL endpoints 0 1 0 1 2 0 1 0 1 0 1 0 1 4452_021 v1.3 547 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Enable IN endpoint i Disable endpoint IN i (no response to IN tokens) Enable endpoint IN i (response to IN tokens) Enable ISO IN endpoint Disable ISO IN endpoint 8 Enable ISO IN endpoint 8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A-H RW OUT[i] (i=0..7) Enable OUT endpoint i Value ID Value Description Disable endpoint OUT i (no response to OUT tokens) Enable endpoint OUT i (response to OUT tokens) Enable ISO OUT endpoint 8 Disable ISO OUT endpoint 8 Enable ISO OUT endpoint 8 ID ID A B ID ID A ID ID A Peripherals C B A A A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description AccessField W EP W IO C W STALL Out In UnStall Stall 0 1 0 1 Select endpoint number Selects IN or OUT endpoint Selects OUT endpoint Selects IN endpoint Stall selected endpoint Don't stall selected endpoint Stall selected endpoint 6.33.13.48 ISOSPLIT Address offset: 0x51C Controls the split of ISO buffers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A A A A A A A Reset 0x00000000 AccessField RW SPLIT Value ID Value Description OneDir HalfIN 0x0000 0x0080 Full buffer dedicated to either iso IN or OUT Lower half for IN, upper half for OUT Controls the split of ISO buffers 6.33.13.49 FRAMECNTR Address offset: 0x520 Returns the current value of the start of frame counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R FRAMECNTR Returns the current value of the start of frame counter 6.33.13.50 LOWPOWER Address offset: 0x52C Controls USBD peripheral low power mode during USB suspend 4452_021 v1.3 548 ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW LOWPOWER Controls USBD peripheral low-power mode during USB ForceNormal Software must write this value to exit low power mode and suspend before performing a remote wake-up LowPower Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral 6.33.13.51 ISOINCONFIG Address offset: 0x530 Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW RESPONSE Controls the response of the ISO IN endpoint to an IN token NoResp ZeroData when no data is ready to be sent Endpoint does not respond in that case Endpoint responds with a zero-length data packet in that case 0 1 0 1 Peripherals A A 6.33.13.52 EPIN[n].PTR (n=0..7) Address offset: 0x600 + (n 0x14) Data pointer Bit number ID ID A Reset 0x00000000 AccessField RW PTR 6.33.13.53 EPIN[n].MAXCNT (n=0..7) Address offset: 0x604 + (n 0x14) Maximum number of bytes to transfer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Data pointer See the memory chapter for details about which memories are available for EasyDMA. Bit number ID ID A Reset 0x00000000 AccessField RW MAXCNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Description Value

[64..0]

Maximum number of bytes to transfer 4452_021 v1.3 549 Peripherals 6.33.13.54 EPIN[n].AMOUNT (n=0..7) Address offset: 0x608 + (n 0x14) Number of bytes transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A Value ID Value Description Number of bytes transferred in the last transaction Reset 0x00000000 AccessField R AMOUNT 6.33.13.55 ISOIN.PTR Address offset: 0x6A0 Data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW PTR Value ID Value Description Data pointer A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 See the memory chapter for details about which memories are available for EasyDMA. 6.33.13.56 ISOIN.MAXCNT Address offset: 0x6A4 Maximum number of bytes to transfer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW MAXCNT Value ID Description Value

[1023..1]

Maximum number of bytes to transfer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A 6.33.13.57 ISOIN.AMOUNT Address offset: 0x6A8 Number of bytes transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R AMOUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A Value ID Value Description Number of bytes transferred in the last transaction ID ID A ID ID A ID ID A ID ID A 6.33.13.58 EPOUT[n].PTR (n=0..7) Address offset: 0x700 + (n 0x14) Data pointer 4452_021 v1.3 550 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW PTR Value ID Value Description Data pointer A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 See the memory chapter for details about which memories are available for EasyDMA. 6.33.13.59 EPOUT[n].MAXCNT (n=0..7) Address offset: 0x704 + (n 0x14) Maximum number of bytes to transfer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW MAXCNT Value ID Description Value

[64..0]

Maximum number of bytes to transfer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A 6.33.13.60 EPOUT[n].AMOUNT (n=0..7) Address offset: 0x708 + (n 0x14) Number of bytes transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A Value ID Value Description Number of bytes transferred in the last transaction Reset 0x00000000 AccessField R AMOUNT 6.33.13.61 ISOOUT.PTR Address offset: 0x7A0 Data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW PTR Value ID Value Description Data pointer A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 See the memory chapter for details about which memories are available for EasyDMA. ID ID A ID ID A ID ID A ID ID A 6.33.13.62 ISOOUT.MAXCNT Address offset: 0x7A4 Maximum number of bytes to transfer 4452_021 v1.3 551 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW MAXCNT Value ID Value Description Maximum number of bytes to transfer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A Peripherals 6.33.13.63 ISOOUT.AMOUNT Address offset: 0x7A8 Number of bytes transferred in the last transaction Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField R AMOUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A A A A A A A Value ID Value Description Number of bytes transferred in the last transaction ID ID A ID ID A 6.33.14 Electrical specification 6.33.14.1 USB Electrical Specification Symbol Description RUSB,PU,ACTIVE Value of pull-up on D+, bus active (upstream device Minimum duration of an SE0 state to be detected as a USB RUSB,PU,IDLE tUSB,DETRST fUSB,CLK fUSB,TOL transmitting) Value of pull-up on D+, bus idle reset condition Frequency of local clock, USB active Accuracy of local clock, USB active41 TUSB,JITTER Jitter on USB local clock, USB active Min. 1425 Typ. 2300 Max. 3090 900 1200 1575 Units s 48 MHz 1000 ppm 1 ns 6.34 WDT Watchdog timer A countdown watchdog timer using the low-frequency clock source (LFCLK) offers configurable and robust protection against application lock-up. The watchdog timer is started by triggering the START task. The watchdog can be paused during long CPU sleep periods for low power applications and when the debugger has halted the CPU. The watchdog is implemented as a down-counter that generates a TIMEOUT event when it wraps over after counting down to 0. When the watchdog timer is started through the START task, the watchdog counter is loaded with the value specified in the CRV register. This counter is also reloaded with the value specified in the CRV register when a reload request is granted. The watchdogs timeout period is given by the following equation:

41 The local clock can be stopped during USB suspend 4452_021 v1.3 552

A

5

H

D

U

I

T

Peripherals When started, the watchdog will automatically force the 32.768 kHz RC oscillator on as long as no other 32.768 kHz clock source is running and generating the 32.768 kHz system clock, see chapter CLOCK Clock control on page 80. 6.34.1 Reload criteria The watchdog has eight separate reload request registers, which shall be used to request the watchdog to reload its counter with the value specified in the CRV register. To reload the watchdog counter, the special value 0x6E524635 needs to be written to all enabled reload registers. One or more RR registers can be individually enabled through the RREN register. 6.34.2 Temporarily pausing the watchdog By default, the watchdog will be active counting down the down-counter while the CPU is sleeping and when it is halted by the debugger. It is possible to configure the watchdog to automatically pause while the CPU is sleeping as well as when it is halted by the debugger. 6.34.3 Watchdog reset A TIMEOUT event will automatically lead to a watchdog reset. See Reset on page 67 for more information about reset sources. If the watchdog is configured to generate an interrupt on the TIMEOUT event, the watchdog reset will be postponed with two 32.768 kHz clock cycles after the TIMEOUT event has been generated. Once the TIMEOUT event has been generated, the impending watchdog reset will always be effectuated. The watchdog must be configured before it is started. After it is started, the watchdogs configuration registers, which comprise registers CRV, RREN, and CONFIG, will be blocked for further configuration. The watchdog can be reset from several reset sources, see Reset behavior on page 68. When the device starts running again, after a reset, or waking up from OFF mode, the watchdog configuration registers will be available for configuration again. 6.34.4 Registers Base address Peripheral Instance Description Configuration 0x40010000 WDT WDT Watchdog timer Register TASKS_START EVENTS_TIMEOUT INTENSET INTENCLR RUNSTATUS REQSTATUS CRV RREN CONFIG RR[0]

RR[1]

RR[2]

RR[3]

RR[4]

Offset 0x000 0x100 0x304 0x308 0x400 0x404 0x504 0x508 0x50C 0x600 0x604 0x608 0x60C 0x610 Description Start the watchdog Watchdog timeout Enable interrupt Disable interrupt Run status Request status Counter reload value Reload request 0 Reload request 1 Reload request 2 Reload request 3 Reload request 4 Enable register for reload request registers Configuration register 4452_021 v1.3 553

Peripherals A A A Register RR[5]

RR[6]

RR[7]

Offset 0x614 0x618 0x61C Description Reload request 5 Reload request 6 Reload request 7 6.34.4.1 TASKS_START Address offset: 0x000 Start the watchdog ID ID A ID ID A ID ID A Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description W TASKS_START Start the watchdog Trigger 1 Trigger task 6.34.4.2 EVENTS_TIMEOUT Address offset: 0x100 Watchdog timeout Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description RW EVENTS_TIMEOUT NotGenerated Generated Watchdog timeout Event not generated Event generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 AccessField RW TIMEOUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event TIMEOUT Set Disabled Enabled Enable Read: Disabled Read: Enabled 0 1 1 0 1 6.34.4.3 INTENSET Address offset: 0x304 Enable interrupt 6.34.4.4 INTENCLR Address offset: 0x308 Disable interrupt 4452_021 v1.3 554

Bit number ID ID A Reset 0x00000000 AccessField RW TIMEOUT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event TIMEOUT Clear Disabled Enabled Disable Read: Disabled Read: Enabled Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AccessField Value ID Value Description R RUNSTATUS Indicates whether or not the watchdog is running NotRunning Running Watchdog not running Watchdog is running 1 0 1 0 1 Peripherals A A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description DisabledOrRequested 0 RR[i] register is not enabled, or are already requesting Request status for RR[i] register reload EnabledAndUnrequested 1 RR[i] register is enabled, and are not yet requesting reload 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description

[0xF..0xFFFFFFFF]

Counter reload value in number of cycles of the 32.768 kHz clock 6.34.4.8 RREN Address offset: 0x508 Enable register for reload request registers 4452_021 v1.3 555 6.34.4.5 RUNSTATUS Address offset: 0x400 Run status 6.34.4.6 REQSTATUS Address offset: 0x404 Request status Bit number ID Reset 0x00000001 ID AccessField A-H R RR[i] (i=0..7) 6.34.4.7 CRV Address offset: 0x504 Counter reload value Bit number ID ID A Reset 0xFFFFFFFF AccessField RW CRV Peripherals H G F E D C B A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Disabled Enabled Enable or disable RR[i] register Disable RR[i] register Enable RR[i] register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Configure the watchdog to either be paused, or kept running, while the CPU is sleeping Pause watchdog while the CPU is sleeping Keep the watchdog running while the CPU is sleeping Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger Pause watchdog while the CPU is halted by the debugger Keep the watchdog running while the CPU is halted by the debugger Bit number ID Reset 0x00000001 ID AccessField A-H RW RR[i] (i=0..7) 6.34.4.9 CONFIG Address offset: 0x50C Configuration register Bit number ID ID A Reset 0x00000001 AccessField RW SLEEP C RW HALT Pause Run Pause Run 6.34.4.10 RR[n] (n=0..7) Address offset: 0x600 + (n 0x4) Reload request n 0 1 0 1 0 1 Bit number ID ID A Reset 0x00000000 AccessField W RR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Reload request register Reload 0x6E524635 Value to request a reload of the watchdog timer 6.34.5 Electrical specification 6.34.5.1 Watchdog Timer Electrical Specification Symbol tWDT Description Time out interval Min. Typ. Max. Units 458 s 36 h 4452_021 v1.3 556 7 Hardware and layout 7.1 Pin assignments The pin assignment figures and tables describe the pinouts for the product variants of the chip. The nRF52833 device provides flexibility regarding GPIO pin routing and configuration. However, some pins have limitations or recommendations for pin configurations and uses. 7.1.1 aQFN73 ball assignments The ball assignment figure and table in the following section describe the assignments for this variant of the chip.

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Hardware and layout Recommended usage Standard drive, low frequency I/O Standard drive, low frequency I/O Standard drive, low frequency I/O Standard drive, low frequency I/O Standard drive, low frequency I/O Standard drive, low frequency I/O Standard drive, low frequency I/O Standard drive, low frequency I/O only only only only only only E24) only only only only only B5) P1.05 Digital I/O General purpose I/O Standard drive, low frequency I/O Digital I/O General purpose I/O Standard drive, low frequency I/O Analog input Connection for 32 MHz crystal 1.3 V regulator supply decoupling Must be connected to DEC6 (pin Pin A8 A10 A12 A14 A16 A18 A20 A22 A23 B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B24 C1 D2 D23 E24 F2 F23 G1 H2 H23 J1 J24 Name P0.31 AIN7 P0.29 AIN5 P0.02 AIN0 P0.19 N.C. P0.25 VDD XC2 VDD DCC DEC4 VSS P0.30 AIN6 P0.28 AIN4 P0.03 AIN1 P1.03 N.C. XC1 DEC1 P0.00 XL1 DEC3 DEC6 XL2 VSS_PA P0.26 P0.27 ANT P0.04 AIN2 P0.10 NFC2 Function Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Digital I/O Power Power Power Power Power Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Power Digital I/O Analog input Power Power Power Digital I/O Digital I/O RF Digital I/O Analog input Digital I/O NFC input Description General purpose I/O Analog input General purpose I/O Analog input General purpose I/O Analog input General purpose I/O Power supply Power supply DC/DC converter output Ground General purpose I/O Analog input General purpose I/O Analog input General purpose I/O Analog input General purpose I/O Connection for 32 MHz crystal 1.1 V regulator supply decoupling General purpose I/O Connection for 32.768 kHz crystal Power supply, decoupling Ground (radio supply) General purpose I/O General purpose I/O General purpose I/O Analog input General purpose I/O NFC antenna connection 1.3 V regulator supply decoupling Must be connected to DEC4 (pin P0.01 Digital I/O General purpose I/O Analog input Connection for 32.768 kHz crystal Single-ended radio antenna connection See Reference circuitry on page 567 for guidelines on how to ensure good RF performance Standard drive, low frequency I/O only 4452_021 v1.3 558 P0.23 Digital I/O General purpose I/O Standard drive, low frequency I/O TRACEDATA1 Trace data P1.04 Digital I/O Trace buffer TRACEDATA[1]

General purpose I/O Standard drive, low frequency I/O Hardware and layout Recommended usage Standard drive, low frequency I/O Standard drive, low frequency I/O Standard drive, low frequency I/O Standard drive, low frequency I/O Standard drive, low frequency I/O only only only only only only Analog input Analog input TRACECLK Trace clock Description General purpose I/O General purpose I/O General purpose I/O NFC antenna connection General purpose I/O Trace buffer clock General purpose I/O 1.3 V regulator supply decoupling General purpose I/O General purpose I/O P1.09 Digital I/O General purpose I/O TRACEDATA3 Trace data P1.06 Digital I/O Trace buffer TRACEDATA[3]

General purpose I/O P0.11 Digital I/O General purpose I/O TRACEDATA2 Trace data Trace buffer TRACEDATA[2]

Digital I/O General purpose I/O Pin K2 L1 L24 M2 N1 N24 P2 P23 R1 R24 T2 T23 U1 U24 V23 W1 W24 Y2 Y23 AB2 AC5 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC24 AD2 AD4 AD6 AD8 AD10 AD12 AD14 AD16 Name P0.05 AIN3 P0.06 P0.09 NFC1 P0.07 P0.08 DEC5 P1.08 P1.07 N.C. P0.12 N.C. VDD P1.02 VDDH P1.01 N.C. P0.14 P0.16 P0.18 nRESET N.C. P0.21 N.C. N.C. SWDIO VBUS D-

D+

P0.13 P0.15 P0.17 VDD P0.20 Function Digital I/O Digital I/O Digital I/O NFC input Digital I/O Digital I/O Power Digital I/O Digital I/O Power Digital I/O Power Digital I/O Digital I/O Digital I/O Digital I/O Debug Power USB USB Digital I/O Digital I/O Digital I/O Power Digital I/O AA24 SWDCLK Debug Serial wire debug clock input for debug and DECUSB Power USB 3.3 V regulator supply decoupling Digital I/O General purpose I/O Serial wire debug I/O for debug and programming 5 V input for USB 3.3 V regulator Power supply General purpose I/O High voltage power supply General purpose I/O programming General purpose I/O General purpose I/O General purpose I/O Configurable as pin RESET USB D-

USB D+

General purpose I/O General purpose I/O General purpose I/O Power supply General purpose I/O 4452_021 v1.3 559 Pin AD18 AD20 AD22 Name P0.22 P0.24 P1.00 Function Digital I/O Digital I/O Digital I/O AD23 Die pad VDD VSS Power Power TRACEDATA0 Trace data Trace buffer TRACEDATA[0]

Description General purpose I/O General purpose I/O General purpose I/O Serial wire output (SWO) Power supply Ground pad

Hardware and layout Recommended usage Exposed die pad must be connected to ground (VSS) for proper device operation Note: For more information on standard drive, see GPIO General purpose input/output on page 138. Low frequency I/O is a signal with a frequency up to 10 kHz. Note: If SPIM0, SPIM1, or SPIM2 is used with 8 Mbps data rate, the recommended GPIOs for the clock signal (SCK) are P0.27, P1.08, P0.04, and P1.09. 7.1.2 QFN40 pin assignments The pin assignment figure and table describe the assignments for this variant of the chip.

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Pin Name Function Description Recommended usage Left side of the chip Hardware and layout Bottom side of the chip DECUSB Power USB 3.3 V regulator supply decoupling 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DEC1 P0.00 XL1 P0.01 XL2 P0.04 AIN2 P0.05 AIN3 P1.09 P0.11 VDD VDDH VBUS D-

D+

P0.15 P0.17 P0.18 nRESET P0.20 VDD SWDIO SWDCLK DEC5 P0.09 NFC1 P0.10 NFC2 ANT VSS_PA DEC6 DEC3 XC1 XC2 VDD P0.03 AIN1 P0.02 AIN0 Power Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Digital I/O Digital I/O Power Power Power USB USB Digital I/O Digital I/O Digital I/O Digital I/O Power Debug Debug Power Digital I/O NFC input Digital I/O NFC input RF Power Power Power Analog input Analog input Power Digital I/O Analog input Digital I/O Analog input Right side of the chip Top side of the chip 1.1 V Digital supply decoupling General purpose I/O pin. Connection for 32.768 kHz crystal General purpose I/O pin Connection for 32.768 kHz crystal General purpose I/O pin Analog input General purpose I/O pin Analog input General purpose I/O pin General purpose I/O pin Power supply High voltage power supply 5 V input for USB 3.3 V regulator USB D-

USB D+

General purpose I/O General purpose I/O General purpose I/O Configurable as pin RESET General purpose I/O Power supply NFC antenna connection General purpose I/O NFC antenna connection Power supply, decoupling Connection for 32 MHz crystal Connection for 32 MHz crystal Power supply Analog input Analog input Serial wire debug I/O for debug and programming Serial wire debug clock input for debug and programming 1.3 V regulator supply decoupling General purpose I/O Standard drive, low frequency I/O Standard drive, low frequency I/O 567 for guidelines on how to ensure good RF performance Single-ended radio antenna connection See Reference circuitry on page Ground (radio supply) 1.3 V regulator supply decoupling Must be connected to DEC4 (pin General purpose I/O pin Standard drive, low frequency I/O General purpose I/O pin Standard drive, low frequency I/O only only 38) only only 4452_021 v1.3 561 Pin 33 34 35 36 37 38 39 40 Name P0.28 AIN4 P0.29 AIN5 P0.30 AIN6 P0.31 AIN7 VSS DEC4 DCC VDD Function Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Power Power Power Power Hardware and layout Description Recommended usage General purpose I/O pin Standard drive, low frequency I/O General purpose I/O pin Standard drive, low frequency I/O General purpose I/O pin Standard drive, low frequency I/O Analog input Analog input Analog input General purpose I/O pin Analog input Ground DC/DC converter output Power supply only only only 26) 1.3 V regulator supply decoupling Must be connected to DEC6 (pin Backside of the the chip Die pad VSS Power Ground pad Exposed die pad must be connected to ground (VSS) for proper device operation Note: For more information on standard drive, see GPIO General purpose input/output on page 138. Low frequency I/O is a signal with a frequency up to 10 kHz. Note: If SPIM0, SPIM1, or SPIM2 is used with 8 Mbps data rate, the recommended GPIOs for the clock signal (SCK) are P1.09, P0.04, and P0.31. 7.1.3 WLCSP ball assignments The ball assignment figure and table describe the assignments for this variant of the chip. N52833 WLCSP 4452_021 v1.3 562

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P1.03 Digital I/O General purpose I/O Standard drive, low frequency I/O General purpose I/O pin Standard drive, low frequency I/O General purpose I/O pin Standard drive, low frequency I/O Hardware and layout Description Recommended usage Connection for 32 MHz crystal Connection for 32 MHz crystal General purpose I/O Standard drive, low frequency I/O General purpose I/O pin Standard drive, low frequency I/O General purpose I/O pin Standard drive, low frequency I/O 1.3 V regulator supply decoupling Must be connected to DEC6 (ball only only only C2) only only only A6) only only only only only Analog input Analog input Ground DC/DC converter output Power supply Power supply Analog input Analog input General purpose I/O pin Connection for 32.768 kHz crystal General purpose I/O pin. Connection for 32.768 kHz crystal 1.1 V Digital supply decoupling Ground (radio supply) Analog input Analog input General purpose I/O General purpose I/O Ground Ground Ground Ground General purpose I/O pin Analog input General purpose I/O pin Analog input 1.3 V regulator supply decoupling Must be connected to DEC4 (ball P1.05 Digital I/O General purpose I/O Standard drive, low frequency I/O P0.19 Digital I/O General purpose I/O Standard drive, low frequency I/O General purpose I/O pin Standard drive, low frequency I/O General purpose I/O pin Standard drive, low frequency I/O P0.23 Digital I/O General purpose I/O Standard drive, low frequency I/O Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 B3 B4 B5 B6 B7 B8 B9 C1 C2 C4 C5 C6 C7 C8 C9 D3 D4 D5 D6 D7 D8 D9 Name XC1 XC2 P0.25 P0.03 AIN1 P0.29 AIN5 DEC4 VSS DCC VDD VDD P0.30 AIN6 P0.31 AIN7 P0.01 XL2 P0.00 XL1 DEC1 VSS_PA DEC6 P0.02 AIN0 P0.28 AIN4 P0.27 P0.26 VSS VSS VSS VSS P0.04 AIN2 P0.05 AIN3 Function Analog input Analog input Digital I/O Digital I/O Analog input Digital I/O Analog input Power Power Power Power Power Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Digital I/O Analog input Power Power Power Digital I/O Analog input Digital I/O Analog input Digital I/O Digital I/O Power Power Power Power Digital I/O Analog input Digital I/O Analog input 4452_021 v1.3 563 only only only only only only only Pin E1 Name ANT Function RF Description Recommended usage Single-ended radio antenna connection See Reference circuitry on page General purpose I/O Standard drive, low frequency I/O Hardware and layout 567 for guidelines on how to ensure good RF performance Standard drive, low frequency I/O 1.3 V regulator supply decoupling General purpose I/O Standard drive, low frequency I/O Standard drive, low frequency I/O TRACEDATA3 Trace data Trace buffer TRACEDATA[3]

P1.04 Digital I/O General purpose I/O Standard drive, low frequency I/O P0.24 Digital I/O General purpose I/O Standard drive, low frequency I/O Standard drive, low frequency I/O TRACEDATA2 Trace data Trace buffer TRACEDATA[2]

SWDCLK Debug Serial wire debug clock input for debug and Standard drive, low frequency I/O only TRACECLK Trace clock P0.10 NFC2 P1.06 VSS VSS VSS P0.08 P0.07 P0.06 DEC5 P0.09 NFC1 P1.01 VSS VSS VSS P0.13 P1.09 P1.08 P1.07 P0.21 P0.20 P0.16 P0.11 VDD P1.02 Digital I/O NFC input Digital I/O Power Power Power Digital I/O Digital I/O Digital I/O Power Digital I/O NFC input Digital I/O Power Power Power Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Power Digital I/O E2 E3 E4 E5 E6 E7 E8 E9 F1 F2 F3 F4 F5 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G8 G9 H1 H2 H3 H4 H5 H6 H7 NFC antenna connection General purpose I/O Ground Ground Ground General purpose I/O General purpose I/O Trace buffer clock General purpose I/O NFC antenna connection General purpose I/O Ground Ground Ground General purpose I/O General purpose I/O General purpose I/O General purpose I/O General purpose I/O General purpose I/O General purpose I/O General purpose I/O Power supply General purpose I/O programming General purpose I/O Serial wire output (SWO) Configurable as pin RESET General purpose I/O General purpose I/O P1.00 Digital I/O TRACEDATA0 Trace data Trace buffer TRACEDATA[0]

P0.18 Digital I/O General purpose I/O nRESET P0.15 P0.12 Digital I/O Digital I/O TRACEDATA1 Trace data Trace buffer TRACEDATA[1]

D-

USB USB D-

4452_021 v1.3 564 Hardware and layout Description Recommended usage Pin H8 H9 J1 J2 J3 J4 J5 J6 J7 J8 J9 Name VBUS VDDH VDD SWDIO P0.22 VDD P0.17 P0.14 D+

DECUSB VSS Function Power Power Power Debug Digital I/O Power Digital I/O Digital I/O USB Power Power 5 V input for USB 3.3 V regulator High voltage power supply Power supply Serial wire debug I/O for debug and programming General purpose I/O Power supply General purpose I/O General purpose I/O USB D+

Ground USB 3.3 V regulator supply decoupling Note: For more information on standard drive, see GPIO General purpose input/output on page 138. Low frequency I/O is a signal with a frequency up to 10 kHz. Note: If SPIM0, SPIM1, or SPIM2 is used with 8 Mbps data rate, the recommended GPIOs for the clock signal (SCK) are P0.27, P1.08, P0.04, and P1.09. 7.2 Mechanical specifications The mechanical specifications for the packages show the dimensions in millimeters. 7.2.1 aQFN73 7 x 7 mm package Dimensions in millimeters for the aQFN 73 7 x 7 mm package.

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Hardware and layout A A2 A3 b D2, E2 e e1 e2 Min. Nom. Max. 0.85 A1 0.02 0.05 0.08 D, E 6.90 7.00 7.10 4.75 4.85 4.95 0.20 0.25 0.30

0.675 0.13 0.5 2.75 0.559 7.2.2 QFN40 5 x 5 mm package 40 1 40 1 10 31 30 21 11 20 Min. Nom. Max. A 0.80 0.85 0.90 A1 0.00 0.05 A3 b D2, E2 e D, E 4.90 5.00 5.10 3.50 3.60 3.70 0.15 0.20 0.25 0.035 0.203 0.40 K 0.20 L 0.30 0.35 0.40 7.2.3 WLCSP 3.175 x 3.175 mm package Dimensions in millimeters for the WLCSP 3.175 x 3.175 mm package. 4452_021 v1.3 566

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Hardware and layout i j A A1 A2 A3 b D E D2 E2 e i j Min. Nom. Max. 0.464 0.148 0.281 0.022 0.184 0.514 0.180 0.319 0.028 0.244 0.489 0.300 0.025 0.200 3.175 3.175 2.800 2.800 0.350 0.025 0.025 7.3 Reference circuitry To ensure good RF performance when designing PCBs, it is highly recommended to use the PCB layouts and component values provided by Nordic Semiconductor. Documentation for the different package reference circuits, including Altium Designer files, PCB layout files, and PCB production files can be downloaded from the product page for the nRF52833 on www.nordicsemi.com. In this section there are reference circuits for QIAA aQFN showing the components and component values to support on-chip features in a design. 73, CJAA WLCSP, and QDAA QFN40 packages, Note: This is not a complete list of configurations, but all required circuitry is shown for further configurations. Some general guidance is summarized here:

When supplying power from a USB source only, VBUS must be connected to VDDH if USB is to be used. Components required for DC/DC function are only needed if DC/DC mode is enabled for that regulator. NFC can be used in any configuration. USB can be used in any configuration as long as VBUS is supplied by the USB host. The schematics include an optional series resistor on the USB supply for improved immunity to transient overvoltage during VBUS connection. Using the series resistor is recommended for new designs. 4452_021 v1.3 567

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Hardware and layout Features that can be enabled for each configuration example DCDCEN1 USB NFC Features that can be enabled for each configuration example DCDCEN1 USB NFC No No No Yes Yes No No No No Yes Yes No No No No Yes Yes No Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes No No No No No Yes No No No No No Yes No No No No No Yes No Features that can be enabled for each configuration example DCDCEN1 USB NFC Circuit configurations for QIAA aQFN 73 Config no. Supply configuration VDDH Config. 1 USB (VDDH = VBUS) Config. 2 Battery/Ext. regulator VDD N/A N/A Config. 3 N/A Battery/Ext. regulator Config. 4 Battery/Ext. regulator N/A Config. 5 N/A Config. 6 N/A Battery/Ext. regulator Battery/Ext. regulator Circuit configurations for QDAA QFN40 Config no. Supply configuration VDDH Config. 1 USB (VDDH = VBUS) Config. 2 Battery/Ext. regulator VDD N/A N/A Config. 3 N/A Battery/Ext. regulator Config. 4 Battery/Ext. regulator N/A Config. 5 N/A Config. 6 N/A Battery/Ext. regulator Battery/Ext. regulator Circuit configurations for CJAA WLCSP Config no. Supply configuration VDDH Config. 1 USB (VDDH = VBUS) Config. 2 Battery/Ext. regulator VDD N/A N/A Config. 3 N/A Battery/Ext. regulator Config. 4 Battery/Ext. regulator N/A Config. 5 N/A Config. 6 N/A Battery/Ext. regulator Battery/Ext. regulator 4452_021 v1.3 568

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Hardware and layout 7.3.1 Circuit configuration no. 1 for QIAA aQFN73 Circuit configuration number 1 for QIAA aQFN 73, showing the schematic and the bill of materials table. Config no. Supply configuration VDDH Config. 1 USB (VDDH = VBUS) VDD N/A Enabled features DCDCEN1 USB No Yes NFC No Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 569

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Hardware and layout Footprint 0402 0402 0402 0402 0603 0402 0402 0402 0603 0603 0402 0402 0402 C5, C7, C8, C12 100 nF Capacitor, X7R, 10%

Description Capacitor, NP0, 2%

Capacitor, NP0, 5%

Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, NP0, 5%

Not mounted Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, X7S, 10%

Value 12 pF 1.0 pF 1.2 pF 4.7 F 820 pF N.C. 100 pF 1.0 F 4.7 F 4.7 nH 2.2 nH Designator C1, C2, C16, C17 C6, C19 C13, C14 C3 C4 C9 C10 C11 C18 L1 L2 R1 U1 X1 X2 High frequency chip inductor 5%

High frequency chip inductor 5%

4R7 nRF52833-QIAA Multiprotocol Resistor, 1%, 0.063 W low energy, IEEE AQFN-73 802.15.4, ANT, and 2.4 GHz proprietary System on Chip 32 MHz 32.768 kHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_2016 Crystal SMD 3215, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_3215 7.3.2 Circuit configuration no. 2 for QIAA aQFN73 Circuit configuration number 2 for QIAA aQFN 73, showing the schematic and the bill of materials table. Config no. Supply configuration VDDH Config. 2 Battery/Ext. regulator VDD N/A Enabled features DCDCEN1 USB No Yes NFC No 4452_021 v1.3 570

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 571

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Hardware and layout Footprint 0402 0402 0402 0402 0603 0402 0402 0402 0603 0603 0402 0402 C5, C7, C8, C12 100 nF Capacitor, X7R, 10%

Description Capacitor, NP0, 2%

Capacitor, NP0, 5%

Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, NP0, 5%

Not mounted Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, X7S, 10%

Value 12 pF 1.0 pF 1.2 pF 4.7 F 820 pF N.C. 100 pF 1.0 F 4.7 F 4.7 nH Designator C1, C2, C16, C17 C6, C19 C13, C14 C18, C19 C3 C4 C9 C10 C11 L1 L2 U1 X1 X2 High frequency chip inductor 5%

2.2 nH nRF52833-QIAA Multiprotocol High frequency chip inductor 5%

low energy, IEEE AQFN-73 802.15.4, ANT, and 2.4 GHz proprietary System on Chip 32 MHz 32.768 kHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_2016 Crystal SMD 3215, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_3215 7.3.3 Circuit configuration no. 3 for QIAA aQFN73 Circuit configuration number 3 for QIAA aQFN 73, showing the schematic and the bill of materials table. Config no. Supply configuration VDDH VDD Config. 3 N/A Battery/Ext. regulator No Yes Enabled features DCDCEN1 USB NFC No 4452_021 v1.3 572

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 573

4

Hardware and layout Footprint 0402 0402 0402 0402 0603 0402 0402 0402 0603 0603 0402 0402 C5, C7, C8, C12 100 nF Capacitor, X7R, 10%

Description Capacitor, NP0, 2%

Capacitor, NP0, 5%

Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, NP0, 5%

Not mounted Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, X7S, 10%

Value 12 pF 1.0 pF 1.2 pF 4.7 F 820 pF N.C. 100 pF 1.0 F 4.7 F 4.7 nH Designator C1, C2, C16, C17 C6, C19 C13, C14 C3 C4 C9 C10 C11 C20 L1 L2 U1 X1 X2 High frequency chip inductor 5%

2.2 nH nRF52833-QIAA Multiprotocol High frequency chip inductor 5%

low energy, IEEE AQFN-73 802.15.4, ANT, and 2.4 GHz proprietary System on Chip 32 MHz 32.768 kHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_2016 Crystal SMD 3215, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_3215 7.3.4 Circuit configuration no. 4 for QIAA aQFN73 Circuit configuration number 4 for QIAA aQFN 73, showing the schematic and the bill of materials table. Config no. Supply configuration VDDH Config. 4 Battery/Ext. regulator VDD N/A Enabled features DCDCEN1 USB Yes Yes NFC No 4452_021 v1.3 574

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com.

4452_021 v1.3 575

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Hardware and layout Footprint 0402 0402 0402 0402 0603 0402 0402 0402 0603 0402 0603 0402 0402 0603 0402 C5, C7, C8, C12 100 nF Capacitor, X7R, 10%

Description Capacitor, NP0, 2%

Capacitor, NP0, 5%

Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, NP0, 5%

Not mounted Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

Capacitor, X7S, 10%

Value 12 pF 1.0 pF 1.2 pF 4.7 F 820 pF N.C. 100 pF 1.0 F 47 nF 4.7 F 4.7 nH 2.2 nH 10 H Designator C1, C2, C16, C17 C6, C19 C13, C14 C18, C20 C3 C4 C9 C10 C11 C15 L1 L2 L3 L4 U1 X1 X2 High frequency chip inductor 5%

High frequency chip inductor 5%

Chip inductor, IDC min = 50 mA, 20%

15 nH nRF52833-QIAA Multiprotocol High frequency chip inductor 10%

low energy, IEEE AQFN-73 802.15.4, ANT, and 2.4 GHz proprietary System on Chip 32 MHz 32.768 kHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_2016 Crystal SMD 3215, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_3215 7.3.5 Circuit configuration no. 5 for QIAA aQFN73 Circuit configuration number 5 for QIAA aQFN 73, showing the schematic and the bill of materials table. Config no. Supply configuration VDDH VDD Config. 5 N/A Battery/Ext. regulator Yes Yes Enabled features DCDCEN1 USB NFC Yes 4452_021 v1.3 576

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 577

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Hardware and layout Footprint 0402 0402 0402 0402 0603 0402 0402 0402 0603 0402 0603 0402 0402 0402 0603 0402 C5, C7, C8, C12 100 nF Capacitor, X7R, 10%

Description Capacitor, NP0, 2%

Capacitor, NP0, 5%

Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, NP0, 5%

Not mounted Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, X7S, 10%

Capacitor, X7S, 10%

Capacitor, NP0, 5%

Value 12 pF 1.0 pF 1.2 pF 4.7 F 820 pF N.C. 100 pF 1.0 F 47 nF 4.7 F 4.7 nH 2.2 nH 10 H Designator C1, C2, C16, C17 C6, C19 C13, C14 C3 C4 C9 C10 C11 C15 C20 L1 L2 L3 L4 U1 X1 X2 Ctune1, Ctune2 Antenna dependent High frequency chip inductor 5%

High frequency chip inductor 5%

Chip inductor, IDC min = 50 mA, 20%

15 nH nRF52833-QIAA Multiprotocol High frequency chip inductor 10%

low energy, IEEE AQFN-73 802.15.4, ANT, and 2.4 GHz proprietary System on Chip 32 MHz 32.768 kHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_2016 Crystal SMD 3215, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_3215 7.3.6 Circuit configuration no. 6 for QIAA aQFN73 Circuit configuration number 6 for QIAA aQFN 73, showing the schematic and the bill of materials table. Config no. Supply configuration VDDH VDD Config. 6 N/A Battery/Ext. regulator No No Enabled features DCDCEN1 USB NFC No 4452_021 v1.3 578

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 579

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Hardware and layout Footprint 0402 0402 0402 0402 0603 0402 0402 0402 0603 0402 0402 C5, C7, C8, C12 100 nF Capacitor, X7R, 10%

Description Capacitor, NP0, 2%

Capacitor, NP0, 5%

Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, NP0, 5%

Not mounted Capacitor, NP0, 5%

Capacitor, X7R, 10%

Value 12 pF 1.0 pF 1.2 pF 4.7 F 820 pF N.C. 100 pF 1.0 F 4.7 nH Designator C1, C2, C16, C17 C3 C4 C6 C9 C10 C11 L1 L2 U1 X1 X2 C13, C14 High frequency chip inductor 5%

2.2 nH nRF52833-QIAA Multiprotocol High frequency chip inductor 5%

low energy, IEEE AQFN-73 802.15.4, ANT, and 2.4 GHz proprietary System on Chip 32 MHz 32.768 kHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_2016 Crystal SMD 3215, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_3215 7.3.7 Circuit configuration no. 1 for QDAA QFN40 This section contains a configuration summary, a schematic, and bill of materials table for QDAA QFN40 circuit configuration number 1. Config no. Supply configuration VDDH Config. 1 USB (VDDH = VBUS) VDD N/A Enabled features DCDCEN1 USB No Yes NFC No 4452_021 v1.3 580

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 581

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0 Hardware and layout Footprint 0201 0201 0201 0201 0603 0201 0201 0201 0402 0603 0201 0201 0402 C5, C7, C11 100 nF Capacitor, X7S, 10%

Description Capacitor, NP0, 2%

Capacitor, NP0, 5%

Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

Not mounted Capacitor, NP0, 5%

Capacitor, X7S, 10%

Capacitor, X7S, 10%

Value 12 pF 1.0 pF 1.2 pF 4.7 F 820 pF N.C. 100 pF 1.0 F 4.7 F 4.7 nH 2.2 nH 4R7 Designator C1, C2, C15, C16 C6, C19 C12, C13 C3 C4 C8 C9 C10 C17 L1 L2 R1 U1 X1 X2 High frequency chip inductor, 5%

High frequency chip inductor, 5%

nRF52833-

QDAA 32 MHz 32.768 kHz Resistor, 1%, 0.063 W Multiprotocol 802.15.4, ANT, and 2.4 GHz proprietary System on Chip Low Energy, IEEE QFN-40 Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_1612 Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_2012 7.3.8 Circuit configuration no. 2 for QDAA QFN40 This section contains a configuration summary, a schematic, and bill of materials table for QDAA QFN40 circuit configuration number 2. Config no. Supply configuration VDDH Config. 2 Battery/Ext. regulator VDD N/A Enabled features DCDCEN1 USB No Yes NFC No 4452_021 v1.3 582

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 583

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0 Hardware and layout Footprint 0201 0201 0201 0201 0603 0201 0201 0201 0402 0603 0201 0201 C5, C7, C11 100 nF Capacitor, X7S, 10%

Description Capacitor, NP0, 2%

Capacitor, NP0, 5%

Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

Not mounted Capacitor, NP0, 5%

Capacitor, X7S, 10%

Capacitor, X7S, 10%

Designator C1, C2, C15, C16 C6, C19 C12, C13 C17, C18 C3 C4 C8 C9 C10 L1 L2 U1 X1 X2 Value 12 pF 1.0 pF 1.2 pF 4.7 F 820 pF N.C. 100 pF 1.0 F 4.7 F 4.7 nH 2.2 nH nRF52833-

QDAA 32 MHz 32.768 kHz High frequency chip inductor, 5%

High frequency chip inductor, 5%

Multiprotocol 802.15.4, ANT, and 2.4 GHz proprietary System on Chip Low Energy, IEEE QFN-40 Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_1612 Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_2012 7.3.9 Circuit configuration no. 3 for QDAA QFN40 This section contains a configuration summary, a schematic, and bill of materials table for QDAA QFN40 circuit configuration number 3. Config no. Supply configuration VDDH VDD Config. 3 N/A Battery/Ext. regulator No Yes Enabled features DCDCEN1 USB NFC No 4452_021 v1.3 584

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 585

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0 Hardware and layout Footprint 0201 0201 0201 0201 0603 0201 0201 0201 0402 0603 0201 0201 C5, C7, C11 100 nF Capacitor, X7S, 10%

Description Capacitor, NP0, 2%

Capacitor, NP0, 5%

Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

Not mounted Capacitor, NP0, 5%

Capacitor, X7S, 10%

Capacitor, X7S, 10%

Designator C1, C2, C15, C16 C6, C19 C12, C13 C3 C4 C8 C9 C10 C18 L1 L2 U1 X1 X2 Value 12 pF 1.0 pF 1.2 pF 4.7 F 820 pF N.C. 100 pF 1.0 F 4.7 F 4.7 nH 2.2 nH nRF52833-

QDAA 32 MHz 32.768 kHz High frequency chip inductor, 5%

High frequency chip inductor, 5%

Multiprotocol 802.15.4, ANT, and 2.4 GHz proprietary System on Chip Low Energy, IEEE QFN-40 Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_1612 Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_2012 7.3.10 Circuit configuration no. 4 for QDAA QFN40 This section contains a configuration summary, a schematic, and bill of materials table for QDAA QFN40 circuit configuration number 4. Config no. Supply configuration VDDH Config. 4 Battery/Ext. regulator VDD N/A Enabled features DCDCEN1 USB Yes Yes NFC No 4452_021 v1.3 586

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 587

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0 Hardware and layout Footprint 0201 0201 0201 0201 0603 0201 0201 0201 0402 0201 0603 0201 0201 0603 0402 C5, C7, C11 100 nF Capacitor, X7S, 10%

Description Capacitor, NP0, 2%

Capacitor, NP0, 5%

Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

Not mounted Capacitor, NP0, 5%

Capacitor, X7S, 10%

Capacitor, X7S, 10%

Capacitor, X7S, 10%

Value 12 pF 1.0 pF 1.2 pF 4.7 F 820 pF N.C. 100 pF 1.0 F 47 nF 4.7 F 4.7 nH 2.2 nH 10 H 15 nH Designator C1, C2, C15, C16 C6, C19 C12, C13 C17, C18 C3 C4 C8 C9 C10 C14 L1 L2 L3 L4 U1 X1 X2 High frequency chip inductor, 5%

High frequency chip inductor, 5%

Chip inductor, IDC,min = 50 mA, 20%

nRF52833-

QDAA 32 MHz 32.768 kHz High frequency chip inductor, 10%

Multiprotocol 802.15.4, ANT, and 2.4 GHz proprietary System on Chip Low Energy, IEEE QFN-40 Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_1612 Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_2012 7.3.11 Circuit configuration no. 5 for QDAA QFN40 This section contains a configuration summary, a schematic, and bill of materials table for QDAA QFN40 circuit configuration number 5. Config no. Supply configuration VDDH VDD Config. 5 N/A Battery/Ext. regulator Yes Yes Enabled features DCDCEN1 USB NFC Yes 4452_021 v1.3 588

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 589

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0 Hardware and layout Footprint 0201 0201 0201 0201 0603 0201 0201 0201 0402 0201 0603 0201 0201 0201 0603 0402 C5, C7, C11 100 nF Capacitor, X7S, 10%

Description Capacitor, NP0, 2%

Capacitor, NP0, 5%

Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

Not mounted Capacitor, NP0, 5%

Capacitor, X7S, 10%

Capacitor, X7S, 10%

Capacitor, X7S, 10%

Value 12 pF 1.0 pF 1.2 pF 4.7 F 820 pF N.C. 100 pF 1.0 F 47 nF 4.7 F 4.7 nH 2.2 nH 10 H 15 nH Designator C1, C2, C15, C16 C6, C19 C12, C13 C3 C4 C8 C9 C10 C14 C18 L1 L2 L3 L4 U1 X1 X2 Ctune1, Ctune2 TBD Capacitor, X7R, 10%

High frequency chip inductor, 5%

High frequency chip inductor, 5%

Chip inductor, IDC,min = 50 mA, 20%

nRF52833-

QDAA 32 MHz 32.768 kHz High frequency chip inductor, 10%

Multiprotocol 802.15.4, ANT, and 2.4 GHz proprietary System on Chip Low Energy, IEEE QFN-40 Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_1612 Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_2012 7.3.12 Circuit configuration no. 6 for QDAA QFN40 This section contains a configuration summary, a schematic, and bill of materials table for QDAA QFN40 circuit configuration number 6. Config no. Supply configuration VDDH VDD Config. 6 N/A Battery/Ext. regulator No No Enabled features DCDCEN1 USB NFC No 4452_021 v1.3 590

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 591

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0 Hardware and layout Footprint 0201 0201 0201 0201 0603 0201 0201 0201 0402 0201 0201 C5, C7, C11 100 nF Capacitor, X7S, 10%

Description Capacitor, NP0, 2%

Capacitor, NP0, 5%

Capacitor, NP0, 5%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

Not mounted Capacitor, NP0, 5%

Capacitor, X7S, 10%

Designator C1, C2, C15, C16 C10 C12, C13 C3 C4 C6 C8 C9 L1 L2 U1 X1 X2 Value 12 pF 1.0 pF 1.2 pF 4.7 F 820 pF N.C. 100 pF 1.0 F 4.7 nH 2.2 nH nRF52833-

QDAA 32 MHz 32.768 kHz High frequency chip inductor, 5%

High frequency chip inductor, 5%

Multiprotocol 802.15.4, ANT, and 2.4 GHz proprietary System on Chip Low Energy, IEEE QFN-40 Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_1612 Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_2012 7.3.13 Circuit configuration no. 1 for CJAA WLCSP This section contains a configuration summary, a schematic, and bill of materials table for CJAA WLCSP circuit configuration number 1. Config no. Supply configuration VDDH Config. 1 USB (VDDH = VBUS) VDD N/A Enabled features DCDCEN1 USB No Yes NFC No 4452_021 v1.3 592

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 593

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Hardware and layout Footprint 0201 0201 0201 0603 0201 0603 0603 0201 0201 0201 Designator C1, C2, C13, C14 Value 12 pF Description Capacitor, NP0, 2%

C3 0.8 pF Capacitor, NP0, 5%

C4, C6, C7, C9 100 nF Capacitor, X7S, 10%

4.7 F 820 pF 1.0 F 4.7 F 3.9 nH 5.6 nH Capacitor, X7R, 10%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

Capacitor, X7S, 10%

High frequency chip inductor, 5%

High frequency chip inductor, 5%

C5, C16 C8 C10, C11 C15 L1 L2 R1 U1 X1 X2 4R7 nRF52833-CJAA Multiprotocol Resistor, 1%, 0.05W Low Energy, IEEE WLCSP-75 802.15.4, ANT, and 2.4 GHz proprietary System on Chip 32 MHz 32.768 kHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_1612 Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_2012 7.3.14 Circuit configuration no. 2 for CJAA WLCSP This section contains a configuration summary, a schematic, and bill of materials table for CJAA WLCSP circuit configuration number 2. Config no. Supply configuration VDDH Config. 2 Battery/Ext. regulator VDD N/A Enabled features DCDCEN1 USB No Yes NFC No 4452_021 v1.3 594

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 595

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Hardware and layout Footprint 0201 0201 0201 0603 0201 0603 0603 0201 0201 Designator C1, C2, C13, C14 Value 12 pF Description Capacitor, NP0, 2%

C3 0.8 pF Capacitor, NP0, 5%

C4, C6, C7, C9 100 nF Capacitor, X7S, 10%

4.7 F 820 pF 1.0 F 4.7 F 3.9 nH Capacitor, X7R, 10%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

Capacitor, X7S, 10%

High frequency chip inductor, 5%

C5, C16 C8 C10, C11 C15, C17 L1 L2 U1 X1 X2 5.6 nH nRF52833-CJAA Multiprotocol High frequency chip inductor, 5%

Low Energy, IEEE WLCSP-75 802.15.4, ANT, and 2.4 GHz proprietary System on Chip 32 MHz 32.768 kHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_1612 Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_2012 7.3.15 Circuit configuration no. 3 for CJAA WLCSP This section contains a configuration summary, a schematic, and bill of materials table for CJAA WLCSP circuit configuration number 3. Config no. Supply configuration VDDH VDD Config. 3 N/A Battery/Ext. regulator No Yes Enabled features DCDCEN1 USB NFC No 4452_021 v1.3 596

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 597

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Hardware and layout Footprint 0201 0201 0201 0603 0201 0603 0603 0201 0201 Designator C1, C2, C13, C14 Value 12 pF Description Capacitor, NP0, 2%

C3 0.8 pF Capacitor, NP0, 5%

C4, C6, C7, C9 100 nF Capacitor, X7S, 10%

4.7 F 820 pF 1.0 F 4.7 F 3.9 nH Capacitor, X7R, 10%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

Capacitor, X7S, 10%

High frequency chip inductor, 5%

C5, C16 C8 C10, C11 C17 L1 L2 U1 X1 X2 5.6 nH nRF52833-CJAA Multiprotocol High frequency chip inductor, 5%

Low Energy, IEEE WLCSP-75 802.15.4, ANT, and 2.4 GHz proprietary System on Chip 32 MHz 32.768 kHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_1612 Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_2012 7.3.16 Circuit configuration no. 4 for CJAA WLCSP This section contains a configuration summary, a schematic, and bill of materials table for CJAA WLCSP circuit configuration number 4. Config no. Supply configuration VDDH Config. 4 Battery/Ext. regulator VDD N/A Enabled features DCDCEN1 USB Yes Yes NFC No 4452_021 v1.3 598

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 599

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Hardware and layout Footprint 0201 0201 0201 0603 0201 0603 0201 0603 0201 0201 0603 0402 Designator C1, C2, C13, C14 Value 12 pF Description Capacitor, NP0, 2%

C3 0.8 pF Capacitor, NP0, 5%

C4, C6, C7, C9 100 nF Capacitor, X7S, 10%

C5, C16 C8 C10, C11 C12 C15, C17 L1 L2 L3 L4 U1 X1 X2 4.7 F 820 pF 1.0 F 47 nF 4.7 F 3.9 nH 5.6 nH 10 H Capacitor, X7R, 10%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

Capacitor, X7S, 10%

Capacitor, X7S, 10%

High frequency chip inductor, 5%

High frequency chip inductor, 5%

Chip inductor, IDC,min = 50 mA, 20%

15 nH nRF52833-CJAA Multiprotocol High frequency chip inductor, 10%

Low Energy, IEEE WLCSP-75 802.15.4, ANT, and 2.4 GHz proprietary System on Chip 32 MHz 32.768 kHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_1612 Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_2012 7.3.17 Circuit configuration no. 5 for CJAA WLCSP This section contains a configuration summary, a schematic, and bill of materials table for CJAA WLCSP circuit configuration number 5. Config no. Supply configuration VDDH VDD Config. 5 N/A Battery/Ext. regulator Yes Yes Enabled features DCDCEN1 USB NFC Yes 4452_021 v1.3 600

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 601

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Hardware and layout Footprint 0201 0201 0201 0603 0201 0603 0201 0603 0201 0201 0201 0603 0402 Designator C1, C2, C13, C14 Value 12 pF Description Capacitor, NP0, 2%

C3 0.8 pF Capacitor, NP0, 5%

C4, C6, C7, C9 100 nF Capacitor, X7S, 10%

4.7 F 820 pF 1.0 F 47 nF 4.7 F 3.9 nH 5.6 nH 10 H Capacitor, X7R, 10%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

Capacitor, X7S, 10%

Capacitor, X7S, 10%

Capacitor, X7R, 10 %

High frequency chip inductor, 5%

High frequency chip inductor, 5%

Chip inductor, IDC,min = 50 mA, 20%

CT1, CT2, CT3, CT4 Antenna dependent C5, C16 C8 C10, C11 C12 C17 L1 L2 L3 L4 U1 X1 X2 15 nH nRF52833-CJAA Multiprotocol High frequency chip inductor, 10%

Low Energy, IEEE WLCSP-75 802.15.4, ANT, and 2.4 GHz proprietary System on Chip 32 MHz 32.768 kHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_1612 Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_2012 7.3.18 Circuit configuration no. 6 for CJAA WLCSP This section contains a configuration summary, a schematic, and bill of materials table for CJAA WLCSP circuit configuration number 6. Config no. Supply configuration VDDH VDD Config. 6 N/A Battery/Ext. regulator No No Enabled features DCDCEN1 USB NFC No 4452_021 v1.3 602

Hardware and layout Note: For PCB reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 603

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Hardware and layout Footprint 0201 0201 0201 0603 0201 0603 0201 0201 C3 C5 C8 L1 L2 U1 X1 X2 Designator C1, C2, C13, C14 Value 12 pF Description Capacitor, NP0, 2%

0.8 pF Capacitor, NP0, 5%

C4, C6, C7, C9 100 nF Capacitor, X7S, 10%

C10, C11 4.7 F 820 pF 1.0 F 3.9 nH Capacitor, X7R, 10%

Capacitor, X7R, 10%

Capacitor, X7R, 10%

High frequency chip inductor, 5%

5.6 nH nRF52833-CJAA Multiprotocol High frequency chip inductor, 5%

Low Energy, IEEE WLCSP-75 802.15.4, ANT, and 2.4 GHz proprietary System on Chip 32 MHz 32.768 kHz Crystal SMD 1612, 32 MHz, Cl=8 pF, Total Tol: 40 ppm XTAL_1612 Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol:

50 ppm XTAL_2012 7.3.19 PCB guidelines A well designed PCB is necessary to achieve good RF performance. Poor layout can lead to loss in performance or functionality. A qualified RF layout for the IC and its surrounding components, including matching networks, can be downloaded from www.nordicsemi.com. To ensure optimal performance it is essential that you follow the schematics and layout references closely. Especially in the case of the antenna matching circuitry (components between device pin ANT and the antenna), any changes to the layout can change the behavior, resulting in degradation of RF performance or a need to change component values. All reference circuits are designed for use with a 50 single-

ended antenna. A PCB with a minimum of four layers, including a ground plane, is recommended for optimal performance. On the inner layers, put a keep-out area on the inner layers directly below the antenna matching circuitry

(components between device pin ANT and the antenna) to reduce the stray capacitances that influence RF performance. A matching network is needed between the RF pin ANT and the antenna, to match the antenna impedance (normally 50 ) to the optimum RF load impedance for the chip. For optimum performance, the impedance for the matching network should be set as described in the recommended package reference circuitry in Reference circuitry on page 567. The DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF capacitors. See the schematics for recommended decoupling capacitor values. The supply voltage for the chip should be filtered and routed separately from the supply voltages of any digital circuitry. Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD bypass capacitors must be connected as close as possible to the IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground 4452_021 v1.3 604

Hardware and layout plane, the best technique is to have via holes as close as possible to the VSS pads. A minimum of one via hole should be used for each VSS pin. Fast switching digital signals should not be routed close to the crystal or the power supply lines. Capacitive loading of fast switching digital output lines should be minimized in order to avoid radio interference. 7.3.20 PCB layout example The PCB layout shown in the following figures is a reference layout for the aQFN LDO setup and VBUS supply. package with internal Note: Pay attention to how the capacitor C3 is grounded. It is not directly connected to the ground plane, but grounded via VSS_PA pin F23. This is done to create additional filtering of harmonic components. For all available reference layouts, see the product page for the nRF52833 on www.nordicsemi.com. 4452_021 v1.3 605

Hardware and layout Note: No components in bottom layer. 4452_021 v1.3 606

Hardware and layout 7.4 Package thermal characteristics A summary of the thermal characteristics for the different packages available for the IC can be found below. Symbol JA,aQFN73 JA,QFN40 JA,WLCSP Package aQFN73 QFN40 WLCSP Typ. 74.60 136.59 93.09 Unit C/W C/W C/W Values obtained by simulation following the EIA/JESD51-2 for still air condition. 7.5 Package Variation The following describes the variation between the stated parameters in this specification and the values for the specific device package. 7.5.1 aQFN73 The parameter variation when using the aQFN73 package is as follows:

Min. Max. Symbol PSENS,IEEE 802.15.4 PSENS,IT,SP,1M,BLE PRF Typ.

-99

-95 7.542 Unit dBm dBm dBm 42 Achieved using setting in RADIO.TXPOWER 4452_021 v1.3 607

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A 8 Recommended operating conditions The operating conditions are the physical parameters that the chip can operate within. VDD supply voltage, independent of DCDC enable VDD supply voltage needed during power-on reset Symbol Parameter VDD VDDPOR VDDH VBUS tR_VDD TA TAEXT TJ tR_VDDH Supply rise time (0 V to 3.7 V) VDDH supply voltage VBUS USB supply voltage Supply rise time (0 V to 1.7 V) Operating temperature Extended operating temperature Junction temperature Min. 1.7 1.75 2.5 4.35

-40 85 Nom. 3.0 Max. 3.6 Units 3.7 5.0 25 5.5 5.5 60 100 85 105 110 V V V V ms ms C C C Note: The on-chip power-on reset circuitry may not function properly for rise times longer than the specified maximum. 8.1 Extended Operating Temperature The operating temperature range for the device is defined in Recommended operating conditions on page 608. The range extends from Some electrical parameters are valid only for the case an additional parameter for the extended operating temperature condition is provided. operating temperature conditions. When this is the minimum to maximum. Note: When running the device in the extended operating temperature conditions range, the register LFXODEBOUNCE on page 92 must be set to

. To avoid surpassing the maximum die juntion temperature, see Recommended operating conditions on page 608, it is important to minimize current consumption when operating in the extended operating temperature conditions. It is therefore recommended to use the device in Normal Voltage mode with DC/

DC enabled. See POWER Power supply on page 58 for details about main supply modes. 8.2 WLCSP light sensitivity All WLCSP package variants are sensitive to visible and close-range infrared light. This means that a final product design must shield the chip properly, either by final product encapsulation or by shielding/coating of the WLCSP device. Some WLCSP package variants have a backside coating, where the marking side of the device is covered with a light absorbing film, while the side edges and the ball side of the device are still exposed and need to be protected. Other WLCSP package variants do not have any such protection. The WLCSP package variant CJAA has a backside coating. 4452_021 v1.3 608

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9 Absolute maximum ratings Maximum ratings are the extreme limits to which the chip can be exposed for a limited amount of time without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may affect the reliability of the device.43 Note Max. Unit NFC antenna pin current INFC1/2 Environmental aQFN package Storage temperature Environmental QFN40 package Storage temperature Supply voltages VDD VDDH VBUS VSS I/O pin voltage VI/O, VDD 3.6 V VI/O, VDD >3.6 V MSL ESD HBM ESD HBM Class ESD CDM MSL ESD HBM ESD HBM Class ESD CDM Storage temperature MSL ESD HBM ESD HBM Class ESD CDM Flash memory Endurance Retention at 85 C Retention at 105 C Moisture Sensitivity Level Human Body Model Human Body Model Class Charged Device Model Moisture Sensitivity Level Human Body Model Human Body Model Class Charged Device Model Moisture Sensitivity Level Human Body Model Human Body Model Class Charged Device Model

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+125 VDD + 0.3

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-40 10 000 10 3 6.7 Environmental WLCSP 3.175 x 3.175 mm package

-40

+125 Retention at 105 C-85 C, execution split Limited to 1000 write/erase cycles Limited to 1000 write/erase cycles 75% execution time at 85 C or less write/erase cycles years years years 43 For accellerated life time testing (HTOL, etc) supply voltage should not exceed the recommended operating conditions max value, see Recommended operating conditions on page 608. 4452_021 v1.3 609

5

Absolute maximum ratings 4452_021 v1.3 610 10 Ordering information This chapter contains information on IC marking, ordering codes, and container sizes. 10.1 IC marking The nRF52833 package is marked as shown in the following figure. N

<P

<Y 5 P>

Y>

2 8 3 3

<V V>

<H>

<P>

<W W>

<L L>

10.2 Box labels The following figures show the box labels used for nRF52833. 4452_021 v1.3 611

0

Ordering information 10.3 Order code The following are the order codes and definitions for nRF52833. n R F 5 2 8 3 3

<P P>

<V V>

<C C>

4452_021 v1.3 612

Ordering information P - Production configuration code (production site, etc.) F - Firmware version code (only visible on shipping container label) Abbrevitation Definition and implemented codes N52/nRF52 nRF52 Series product 833

<PP>

<VV>

Part code Package variant code Function variant code

<H><P><F>

Build code H - Hardware version code

<YY><WW><LL>

Tracking code YY - Year code WW - Assembly week number LL - Wafer lot code

<CC>

Container code 10.4 Code ranges and values Defined here are the nRF52833 code ranges and values.

<PP>

QI QD CJ

<VV>

AA Package Size (mm) Pin/Ball count Pitch (mm) aQFN QFN WLCSP 7 x 7 5 x 5 3.175 x 3.175 73 40 75 0.5 0.4 0.35 Flash (kB) 512 RAM (kB) 128

<H>

[A . Z]

Description Hardware version/revision identifier (incremental) 4452_021 v1.3 613

6

3

Ordering information Description Production device identifier (incremental) Engineering device identifier (incremental) Description

[A . N, P . Z]

Version of preprogrammed firmware Delivered without preprogrammed firmware

<P>

[0 . 9]

[A . Z]

<F>

[0]

<YY>

Description

[00 . 99]

Production year: 2000 to 2099

<WW>

[1 . 52]

Description Week of production

<LL>

Description

[AA . ZZ]

Wafer production lot identifier

<CC>

R7 R Description 7" Reel 13" Reel 10.5 Product options Defined here are the nRF52833 product options. 4452_021 v1.3 614

F

6

2

Ordering information Order code nRF52833-QIAA-R7 nRF52833-QIAA-R nRF52833-QDAA-R7 nRF52833-QDAA-R nRF52833-CJAA-R7 nRF52833-CJAA-R MOQ44 800 3000 1500 4000 1500 7000 Order code nRF52833-DK Description nRF52833 Development Kit 44 Minimum Ordering Quantity 4452_021 v1.3 615

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U