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User Manual | Users Manual | 1.47 MiB | November 09 2013 / October 03 2014 | |||
1 2 | Cover Letter(s) | November 09 2013 | ||||||
1 2 | External Photos | November 09 2013 / October 03 2014 | ||||||
1 2 | Internal Photos | November 09 2013 / October 03 2014 | ||||||
1 2 | ID Label/Location Info | November 09 2013 | ||||||
1 2 | Cover Letter(s) | November 09 2013 | ||||||
1 2 | RF Exposure Info | November 09 2013 | ||||||
1 2 | Test Report | November 09 2013 | ||||||
1 2 | Test Setup Photos | November 09 2013 / October 03 2014 | ||||||
1 2 | Test Report | November 09 2013 |
1 2 | User Manual | Users Manual | 1.47 MiB | November 09 2013 / October 03 2014 |
eUniStone BlueMoon Universal Platform Embedded PBA 31309 Version 1.x Intel Public Users Manual Hardware Description Revision 1.2, 1-Feb-2013 legal lines and disclaimers Information in this document related to the Intel product or, if any, related to its use is provided in connection with Intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in agreements concluded individually or Intels terms and conditions of sale for such products, Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Unless otherwise agreed in writing by Intel, the Intel products are not designed nor intended for any application in which the failure of the Intel product could create a situation where personal injury or death may occur. Unless otherwise agreed upon, Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Unless otherwise agreed, the information here is subject to change without notice. Do not finalize a design with this information. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-
4725, or go to: http://www.intel.com/#/en_US_01. Any software source code reprinted in this document is furnished under a software license and may only be used or copied in accordance with the terms of that license. This document may contain information on products in the design phase of development. Intel product numbers are not a measure of performance. Product numbers differentiate features within each product family, not across different product families. Code Names are only for use by Intel to identify products, platforms, programs, services, etc. (products) in development by Intel that have not been made commercially available to the public, i.e., announced, launched or shipped. They are never to be used as commercial names for products. Also, they are not intended to function as trademarks. SMARTI, SMARTi & Device, BlueMoon, Comneon, Comneon & Device, M-GOLD, S-GOLD, E-GOLD, A-GOLD, X-GOLD, XMM, X-PMU, XPOSYS are trademarks of Intel Corporation and related companies. Copyright 2013, Intel Corporation. All rights reserved.
*Other names and brands may be claimed as the property of others. Users Manual Hardware Description Intel Public 2 Revision 1.0, 1-Feb-2013 The template (FrameMaker) of this document has been formally released by DOC department (IMC-DOC@intel.com). Template data: T_TechDoc.fm, Rev. 2.00, 2012-04-01. eUniStone PBA 31309 Revision History Page or Item Subjects (major changes since previous revision) Revision 1.0, 1-Feb-2013
<Revision X.Y>, <yyyy-mm-dd>
Users Manual Hardware Description Intel Public 3 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Contents 3.2 3.1 4.1 4.2 2.1 2.2 2.3 1.1 1.2 1.3 1.4 1.5 1.6 1.0 General Device Overview........................................................................................... 8 Features ............................................................................................................ 8 Block Diagram .................................................................................................... 9 Pin Configuration LGA ........................................................................................ 10 Pin Description ................................................................................................. 11 System Integration ........................................................................................... 13 SW Patch in EEPROM ......................................................................................... 14 2.0 Basic Operating Information ................................................................................... 15 Power Supply ................................................................................................... 15 Clocking........................................................................................................... 15 Low Power Modes.............................................................................................. 15 2.3.1 Low Power Mode .................................................................................... 15 2.3.2 Complete Power Down ............................................................................ 15 2.3.3 ON/OFF ................................................................................................ 15 3.0 eUniStone Interfaces............................................................................................... 16 UART Interface ................................................................................................. 16 3.1.1 UART.................................................................................................... 16 3.1.1.1 Baud Rates .............................................................................. 16 3.1.1.2 Detailed UART Behavior............................................................. 17 3.1.1.3 UARTCTS Response Time........................................................... 18 Low Power Control ............................................................................................ 18 4.0 General Device Capabilities ..................................................................................... 19 RF Test Application............................................................................................ 19 Firmware ROM Patching ..................................................................................... 19 Patch Support........................................................................................ 19 4.2.1 5.0 Bluetooth Capabilities ............................................................................................. 20 Supported Features ........................................................................................... 20 eUniStone Bluetooth Features............................................................................. 20 5.2.1 Secure Simple Paining ............................................................................ 20 5.2.2 Role Switch ........................................................................................... 20 5.2.3 Sniff Mode ............................................................................................ 21 5.2.4 Sniff Subrating ...................................................................................... 21 5.2.5 Enhanced Power Control ......................................................................... 21 Encryption Pause and Resume ................................................................. 21 5.2.6 6.0 Electrical Characteristics ......................................................................................... 22 Absolute Maximum Ratings................................................................................. 22 Operating Conditions ......................................................................................... 22 DC Characteristics............................................................................................. 23 Pad Driver and Input Stages.................................................................... 23 6.3.1 Pull-ups and Pull-downs .......................................................................... 25 6.3.2 6.3.3 Protection Circuits .................................................................................. 25 6.3.4 System Power Consumption .................................................................... 26 RF Part ............................................................................................................ 26 6.4.1 Characteristics RF Part............................................................................ 26 6.4.1.1 Bluetooth Related Specifications ................................................. 26 7.0 Package Information............................................................................................... 29 Package Marking............................................................................................... 29 Production Package ........................................................................................... 30 7.2.1 Pin Mark ............................................................................................... 30 8.0 Bluetooth Qualification and Regulatory Certification ............................................... 31 6.1 6.2 6.3 5.1 5.2 7.1 7.2 6.4 Users Manual Hardware Description Intel Public 4 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 9.1 9.2 9.3 9.4 Reference Design .............................................................................................. 31 8.1 FCC Class B Digital Devices Regulatory Notice....................................................... 32 8.2 FCC Wireless Notice........................................................................................... 32 8.3 FCC Interference Statement ............................................................................... 33 8.4 FCC Identifier ................................................................................................... 33 8.5 European R&TTE Declaration of Conformity........................................................... 34 8.6 Bluetooth Qualified Design ID ............................................................................. 36 8.7 Industry Canada Certification.............................................................................. 36 8.8 8.9 Label Design of the Host Product......................................................................... 36 8.10 Regulatory Test House....................................................................................... 36 9.0 Assembly Guidelines ............................................................................................... 37 General Description of the Module ....................................................................... 37 Printed Circuit Board Design ............................................................................... 38 Solder Paste Printing ......................................................................................... 39 Assembly ......................................................................................................... 39 9.4.1 Component Placement ............................................................................ 39 9.4.2 Pin Mark ............................................................................................... 39 9.4.3 Package................................................................................................ 40 Soldering Profile................................................................................................ 41 Rework........................................................................................................... 42 9.6.1 Removal Procedure ............................................................................... 42 9.6.2 Replacement Procedure .......................................................................... 42 9.6.2.1 Alternative 1: Dispensing Solder ................................................. 42 9.6.2.2 Alternative 2: Printing Solder ..................................................... 43 Inspection........................................................................................................ 43 Component Salvage .......................................................................................... 44 Voids in the Solder Joints ................................................................................... 44 Expected Void Content and Reliability ....................................................... 44 9.9.1 9.9.2 Parameters with an Impact on Voiding ...................................................... 45 9.7 9.8 9.9 9.5 9.6 Users Manual Hardware Description Intel Public 5 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Figures Simplified Block Diagram of eUniStone ......................................................................... 9 1 Pin Configuration for eUniStone in Top View (footprint) ................................................. 10 2 System Architecture Example with eUniStone .............................................................. 13 3 UART Interface ........................................................................................................ 16 4 UARTCTS Response Time .......................................................................................... 18 5 Package Marking...................................................................................................... 29 6 Production Package .................................................................................................. 30 7 Top View and Bottom View........................................................................................ 30 8 9 Reference Design Schematics .................................................................................... 31 10 Cutout Drawing ....................................................................................................... 33 11 Equipment Label...................................................................................................... 34 12 Declaration of Conformity ......................................................................................... 35 13 Pad Layout on the Module (top view).......................................................................... 37 14 Cutout Drawing ....................................................................................................... 38 15 Pin Marking............................................................................................................. 39 16 Tape on Reel........................................................................................................... 40 17 Eutectic Lead-Solder Profile....................................................................................... 41 18 Eutectic Leadfree-Solder Profile ................................................................................. 41 19 Solder Printing ........................................................................................................ 43 20 X-ray Picture Showing Voids Conforming to IPC-A-610D................................................ 44 Users Manual Hardware Description Intel Public 6 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Tables Pin Description ....................................................................................................... 11 1 UART Baud Rates .................................................................................................... 17 2 Default (non-inverted) behavior of UART signals ......................................................... 17 3 Absolute Maximum Ratings ...................................................................................... 22 4 Operating Conditions ............................................................................................... 22 5 Internal1 (1.5 V) Supplied Pins ................................................................................. 23 6 Internal2 (2.5 V) Supplied Pins ................................................................................. 23 7 VDDUART Supplied Pins ........................................................................................... 24 8 9 VDD1 Supplied Pins ................................................................................................. 24 10 ONOFF PIN ............................................................................................................ 24 11 Pull-up and Pull-down Currents ................................................................................. 25 12 Max. Load at the Different Supply Voltages ................................................................ 26 13 BDR - Transmitter Part ............................................................................................ 26 14 BDR -Receiver Part ................................................................................................. 27 15 EDR - Transmitter Part ............................................................................................ 27 16 EDR -Receiver Part .................................................................................................. 28 Users Manual Hardware Description Intel Public 7 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 General Device Overview 1.0 General Device Overview 1.1 Features General Complete Bluetooth 2.1 + EDR solution Implements a single point-to-point data link to other SPP capable Bluetooth devices Ultra low power design in 0.13 m CMOS Temperature range from -40C to +85C Integrates ARM7TDMI, RAM and patchable ROM On-module voltage regulators. External supply 2.9 - 4.1 V On-module EEPROM with configuration data On-module tuned reference clock Module can enter low power mode in idle state and during sniff intervals Interfaces AT command interface over UART with HW flow control Default UART baudrate 115200 bit/s Module configuration reprogrammable for 9600 bit/s up to 3.25 Mbit/s UART baudrate JTAG for boundary scan in production test RF Class 2 device up to +4 dBm Receiver sensitivity typ. -86 dBm Integrated antenna, balun and ISM band filter Integrated LNA with excellent blocking and intermodulation performance Digital demodulation for optimum sensitivity and co-/adjacent channel performance Users Manual Hardware Description Intel Public 8 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 General Device Overview Bluetooth Bluetooth V2.1 + EDR compliant Secure Simple Pairing Device A (initiating link) or Device B (accepting link) role supported Single point-to-point data link, role switch supported Packet data mode and stream data mode supported Sniff mode and Sniff Subrating is supported with above capabilities 5 trusted devices stored in EEPROM SW version available to configure specific RF certification tests 1.2 Block Diagram eUniStone VDD1 VDD_UART UART GPIO Vsupply Voltage Regulator EEPROM I2C PMB8754 BlueMoon UniCellular Crystal 26 MHz Balun Filter Figure 1. Simplified Block Diagram of eUniStone eUnistone_ Block_ Diagram.vsd Users Manual Hardware Description Intel Public 9 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 General Device Overview 1.3 Pin Configuration LGA F4 LPMin P0.14 F5 UARTCTS F6 VDDUART F7 UARTTXD F8 UARTRTS F3 P0.11 E3 P1.3 TDO D3 P1.1 TCK E4 LPMout P0.0 D4 P0.3 E5 P0.1 D5 P0.2 C3 JTAG#
C4 TRST#
C5 VDD1 B3 P1.0 TMS B4 P1.4 RTCK B5 ONOFF F1 VSS E1 P0.12 SDA0 D1 P0.10 C1 VREG B1 P1.7 A1 VSS F2 P1.2 TDI E2 P013 SCL0 D2 P0.8 C2 P0.9 B2 P1.8 A2 P1.6 A3 RESET#
A4 VSUPPLY A5 VSUPPLY A6 VSUPPLY E6 UARTRXD D6
(NC) C6
(NC) B6
(NC) E7
(NC) D7 VSS C7
(NC) B7
(NC) A7 VSS E8 VSS D8 VSS C8 VSS B8
(NC) A8 P1.5 F9 VSS E9 VSS D9
(NC) C9 VSS B9 P0.15 A9 VSS F11 VSS F12 VSS Top View A11 VSS A12 VSS PBA31309_Pinout.vsd Figure 2. Pin Configuration for eUniStone in Top View (footprint) Users Manual Hardware Description Intel Public 10 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 General Device Overview 1.4 Table 1. Pin No. Symbol Pin Description The non-shaded cells indicate pins that will be fixed for the product lifetime. Shaded cells indicate that the pin might be removed/changed in future variants. Pins not listed below shall not be connected. Pin Description Input /
Output Supply Voltage During Reset After Reset Function A2 A3 A8 B1 B2 B3 B4 B5 B9 C2 C3 C4 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 E6 F2 F3 F4 F5 F7 F8 A4, A5, A6 C1 F6 C5 P1.6 RESET#
P1.5 P1.7 P1.8 P1.0 /
TMS P1.4 /
RTCK ONOFF P0.15 P0.9 JTAG#
TRST#
P0.10 P0.8 P1.1 /
TCK P0.3 P0.2 P0.12 / SDA0 P0.13 / SCL0 P1.3 /
TDO P0.0 LPMout P0.1 P0.5 /
UARTRXD P1.2 /
TDI P0.11 P0.14 LPMin P0.7 /
UARTCTS P0.4 /
UARTTXD P0.6 /
UARTRTS VSUPPLY VREG VDDUART VDD1 I/O/OD AI I/O/OD I/O/OD I/O/OD I/O/OD Internal1 Internal1 Internal1 Internal1 Internal1 Internal2 I/O/OD Internal2 I I/O I/O/OD I I I/O/OD I/O/OD I/O/OD VDDUART Internal2 Internal2 Internal2 Internal2 Internal2 Internal2 I/O/OD VDD1 I/O/OD I/O/OD I/O/OD I/O/OD VDD1 Internal2 Internal2 Internal2 I/O/OD VDD1 I/O/OD I/O/OD VDD1 VDDUART Z Input Input PD/ Input PD PU1 Z Input Input PD/ Input PD PU1. Z
PD Z PU PD Z PD PU1. Conf. PD def. Z PU PU Z PD PD Z Z
H Z PU PD Z PD PU1. Conf. PD def. Z PU PU Z PD PD Z I/O/OD Internal2 PU1. PU1. I/O/OD I/O Internal2 VDDUART I/O/OD VDDUART I/O/OD VDDUART I/O/OD VDDUART SI SO SI SI Z Z Z PU PU
Z Z Z PU PU
Port 1.6 Hardware Reset Port 1.5 Port 1.7 Port 1.8 Port 1.0 or JTAG interface Port 1.4 or JTAG interface Turns off module completely Port 0.15 Port 0.9 Mode selection Port 1:
0: JTAG 1: Port JTAG interface Port 0.10 Port 0.8 Port 1.1 or JTAG interface Port 0.3 Port 0.2 I2C data signal I2C clock signal Port 1.3 or JTAG interface Port 0.0 LPM wakeup output Port 0.1 Port 0.5 or UART receive data Port 1.2 or JTAG interface Port 0.11 Port 0.14 LPM wakup input Port 0.7 or UART CTS flow control Port 0.4 or UART transmit data Port 0.6 or UART RTS flow control Power supply Regulated Power supply UART interface Power supply Power supply Users Manual Hardware Description Intel Public 11 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 General Device Overview Table 1. Pin No. Symbol Pin Description (Continued) Input /
Output Supply Voltage During Reset VSS NC
A1, A7, A9, A11, A12, C8, C9, D7, D8, E8, E9, F1, F9, F11, F12 B6, B7, B8, C6, C7, D6, D9, E7
After Reset
Function Ground
No connection 1. Fixed pull-up/pull-down if JTAG interface is selected, not affected by any chip reset. If JTAG interface is not selected the port is tristate. Descriptions of acronyms used in the pin list:
Acronym Description I O OD Z PU PD A S Input Output Output with open drain capability Tristate Pull-up Pull-down Analog (e.g. AI means analog input) Supply (e.g. SO means supply output) Users Manual Hardware Description Intel Public 12 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 General Device Overview 1.5 System Integration eUniStone is optimized for a low bill of material (BOM) and a small PCB size. Figure 3 shows a typical application example. Buttons, Leds HOST UART RESET LPM AT command interface GPIO SPP(Serial Port Profile) Oscillator EEPROM Configuration , SW patch I2C Voltage Regulator API RFCOMM BT Stack BT Baseband BT RF BALUN Antenna System_Architecture.vsd VSUPPLY Figure 3. System Architecture Example with eUniStone Users Manual Hardware Description Intel Public 13 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 General Device Overview The UART interface is used for communication between the host and eUniStone. The lines UARTTXD and UARTRXD are used for commands, events and data. The lines UARTRTS and UARTCTS are used for hardware flow control. Low power mode control of eUniStone and the host can be implemented in by using the pins P0.14 and P0.0. P0.14 is used by the host to allow eUniStone to enter low power mode and P0.0 is used by eUniStone to wake-up the host when attention is required. To save current in idle mode, the host could hardware reset the module using the RESET#. Power is supplied to a single VSUPPLY input from which internal regulators can generate all required voltages. The UART and the GPIOs interfaces have separate supply voltages so that they can comply with host signaling. 1.6 SW Patch in EEPROM Bugfixes for the SW in ROM are downloaded from the EEPROM. Intel may include new bugfixes in EEPROM during product lifetime.. Users Manual Hardware Description Intel Public 14 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Basic Operating Information 2.0 Basic Operating Information 2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 Power Supply eUniStone is supplied from a single supply voltage VSUPPLY. This supply voltage must always be present. The Bluetooth chip is supplied from an internally generated 2.5 V supply voltage. This voltage can be accessed from the VREG pin. This voltage shall not be used for supplying other components in the host system but can be used for referencing the host interfaces. The GPIOs and the UART interface are supplied with dedicated, independent, reference levels via the VDD1 and VDDUART pins. All other digital I/O pins are supplied internally by either 2.5 V (Internal2) or 1.5 V (Internal1). Section 1.4 provides a mapping between pins and supply voltages. The I/O power domains (VDD1 and VDDUART) are completely separated from the other power domains and can stay present also in low power modes. Clocking eUniStone contains a crystal from which the internal 26 MHz system clock is generated. Also, the low power mode clock of 32.768 kHz is generated internally, which means that no external clock is needed. Low Power Modes To minimize current consumption, eUniStone automatically switches between different low power modes. The major modes are described below. Low Power Mode In Low Power Mode (LPM) most parts of eUniStone are powered down. This is done automatically in idle mode or if the link is in Sniff mode and the host allows LPM with the pin P0.14. Complete Power Down If Bluetooth functionality is not needed at all, VSUPPLY should be grounded to minimize power consumption. In this state there is no activity in eUniStone and the Bluetooth state (native clock, etc.) is not updated. ON/OFF eUniStone provides an alternative way to power down using the ONOFF logic input. When the ONOFF is low, the internal regulator on the module is turned OFF. The intention with the signal is to have the possibility to turn off the module without having to turn off the supply voltage. In the OFF state, the module will consume less than 1 mA excluding the interface currents that is mainly set by the external load. If this signal isnt used then it should be connected to VSUPPLY on the host PCB. Users Manual Hardware Description Intel Public 15 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 eUniStone Interfaces 3.0 eUniStone Interfaces 3.1 UART Interface The UART interface is the main communication interface between the host and eUniStone. AT commands are described in detail in the AT Commands specification [1]. The interface consists of four UART signals and two LPM control signals as shown in Figure 4. Host UARTTXD UARTRXD UARTRTS UARTCTS WAKEUP_BT WAKEUP_HOST Figure 4. UART Interface eUniStone UARTTXD UARTRXD UARTRTS UARTCTS P0.14 input P0.0 output eUnistone_UART_Interface.vsd 3.1.1 UART The lines UARTTXD and UARTRXD are used for commands, responses and data. The lines UARTRTS and UARTCTS are used for hardware flow control. A separate supply voltage, VDDUART, defines the UART reference levels to fit any system requirements. 3.1.1.1 Baud Rates The UART baud rate can be configured with the BD_DATA parameter UART_Baudrate. The module is programmed for a default baudrate of 115200 baud. Reprogramming of the EEPROM configuration is possible by AT commands at manufacturing time of the end product. The baudrate written to EEPROM will be used each time eUniStone starts or, HW or SW reset is done. The host is also able to change the baudrate temporarily with an AT command. This baudrate is used by eUniStone until a HW or SW reset is done, when it will change back to the baudrate stored in the EEPROM. Users Manual Hardware Description Intel Public 16 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 eUniStone Interfaces Table 2. Standard Baud Rate 9600 19200 38400 57600 115200 230400 460800 921600 1843200 3250000 Table 2 shows the UART baudrates supported. UART Baud Rates Module Baud Rate Deviation in %
9615 19230 38461 57522 115044 230088 464285 928571 1857142 3250000 0.16 0.16 0.16
-0.14
-0.14
-0.14 0.76 0.76 0.76 0 3.1.1.2 Detailed UART Behavior After reset the UART interface is configured with one start bit, eight data bits, no parity bit and one stop bit. The least significant bit is transmitted first. The polarity of the UART signals can be changed with the BD_DATA parameter UART_Invert. The default (non-inverted) behavior is shown in Table 3 Default (non-inverted) behavior of UART signals Level Meaning Table 3. Signal UARTTXD / UARTRXD UARTRTS / UARTCTS 0 1 0 1 Start bit, 0 bit in character. Idle level, stop bit Flow on Flow stopped Users Manual Hardware Description Intel Public 17 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 eUniStone Interfaces 3.1.1.3 UARTCTS Response Time Figure 5 shows the UARTCTS response time. Assuming non-inverted UART signals, the data flow stops within the flow off response time after UARTCTS has been set to high. If UARTCTS goes high during the transmission of a byte (phase 1 in the figure) this byte will be completely transmitted. While UARTCTS is high, no data will be transmitted
(phase 2). When UARTCTS goes low again, data transmission will continue (phase 3). The maximum flow off response time is 10 UART bits (including start and stop bits). As an example, if the UART baud rate is 115200 Baud, the maximum flow off response time is 10 x 1/115200 s = 87 s. UARTCTS max. flow off response time flow off response time UARTTXD t r a t s 0 t i b 1 t i b 2 t i b 3 t i b 4 t i b 5 t i b 6 t i b 7 t i b p o t s t r a t s 0 t i b
... phase 1 phase 2 phase 3 HCI_UARTCTS_Response_Time.vsd Figure 5. UARTCTS Response Time 3.2 Low Power Control Pin P0.14 and P0.0 are optional, but strongly recommended to be used. P0.14 is used to allow eUniStone to enter Low Power Mode (LPM). P0.0 is used by eUniStone when in LPM to wake up the host. Users Manual Hardware Description Intel Public 18 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 General Device Capabilities 4.0 General Device Capabilities 4.1 4.2 4.2.1 This chapter describes features available in the eUniStone (PBA 31309). Actual feature set and how to access the features can be found in the AT Command document [1]. Release specific performance characteristics, data throughput and current consumption are listed in the SW Release Notes [2]. RF Test Application The eUniStone module can be programmed over UART with a specific application for RF test purposes, e.g. TX continuous or TX burst mode. This test application is controlled over the UART through Intel specific HCI commands. The commands supported by this test application are described in the document T8753-2-Intel_Specific_HCI_Commands-7600.pdf. Firmware ROM Patching In any chip with complex firmware in ROM it is wise to support patching. The risk of project delay is significantly reduced when problems can be solved without hardware changes. Enhancements, adaptations and bug fixes can be handled very late during design-in, even after the chip has been soldered in the final product. The well-proven patch concept used in BlueMoon UniCellular is described below. Patch Support The Bluetooth chip contains dedicated hardware that makes it possible to apply patches to the code and data in the firmware ROM. The hardware is capable of replacing up to 32 blocks of 16 bytes each with new content. This area can be filled with any combination of code and data. The firmware patch is stored in EEPROM and automatically loaded after startup. This provides a flexible bugfix solution for the software in ROM. Users Manual Hardware Description Intel Public 19 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Bluetooth Capabilities 5.0 Bluetooth Capabilities 5.1 Supported Features Bluetooth V2.1 + EDR compliant Enhanced Data Rate 2 and 3 Mbit/s symbol rate on the air Secure Simple Pairing Device A (initiating link) or Device B (accepting link) role supported Single point-to-point data link, role switch supported Packet data mode and stream data mode supported Link in sniff mode supported. Device enters Low Power Mode in sniff intervals if permitted by the host. Sniff Subrating 5 trusted devices stored in EEPROM Connection to a Bluetooth Tester 5.2 eUniStone Bluetooth Features 5.2.1 Secure Simple Paining The device implements Secure Simple Pairing with the following association models according to BT2.1 core specification:
Numeric Comparisoon Just Works Passkey Entry Also pairing with legacy (BT2.0 and older) devices is supported. 5.2.2 Role Switch The initiating device (devA) starts as Bluetooth master of the link, the accepting device starts as Bluetooth slave of the link. The remote device can request a role change to accomodate with other Bluetooth links. If that happens, the module will send an event to the host. Also if the eUniStone start as slave, (Device B), the other device can change it's own role making eUniStone master. The host controlling eUniStone will be notified with the same event. Users Manual Hardware Description Intel Public 20 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Bluetooth Capabilities 5.2.3 5.2.4 5.2.5 5.2.6 Sniff Mode The local host or the remote device can request sniff mode for the link. During sniff mode, the devices synchronize on sniff instants only. The module will enter low power mode in the sniff intervals, if allowed by the host LPM control signals. Data packets can be exchanged at the sniff instants only, so the data rate is reduced in sniff mode. The module will wake up the host when data is received or other responses need to be transmitted. Sniff Subrating The local host or the remote device can request Sniff Subrating for the link. When in sniff mode, the device will automatically switch between Sniff Mode and Sniff Subrating Mode making it possible to stay longer in Low Power Mode when there is no data transmitted or received. Enhanced Power Control eUniStone support Enhanced Power Control according to Bluetooth specification 3.0. The Enhanced Power Control is handled automatically to make different modulations modes transmit on optimal levels. Encryption Pause and Resume Encryption Pause Resume is supported making it possible to change connection link key on an encrypted link, pause the encryption and resume it with the new link key. This is handled automatically by eUniStone to make the link more secure. Users Manual Hardware Description Intel Public 21 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Electrical Characteristics 6.0 Electrical Characteristics 6.1 Absolute Maximum Ratings Table 4. Parameter Absolute Maximum Ratings Symbol Values Unit Note / Test Condition Storage temperature VSUPPLY supply voltage VDDUART supply voltage VDD1 supply voltage VREG VREG ONOFF Input voltage range Output voltage range ESD Min. Typ. Max.
-40
-0.3
-0.9
-0.9
-0.3
-0.3
-0.3
-0.9
-0.9 125 6.0 4.0 4.0 4.0 VSUPPLY VSUPPLY+0.3 4.0 4.0 1.0 C V V V V V V V V kV VSUPPLY > 4 V VSUPPLY < 4 V
-9 According to MIL-STD883D method 3015.7 Note:
Stresses above those listed here are likely to cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Maximum ratings are not operating conditions. 6.2 Operating Conditions Table 5. Parameter Operating Conditions Symbol Values Unit Note / Test Condition Min. Typ. Max. Operating temperature Main supply voltage (Vsupply) VDDUART VDD1 1. At ambient temperatures above 65oC the maximum allowed power dissipation in the module is limited to 200 mW
-40 2.9 1.35 1.35 85 4.11 3.6 3.6 C V V V Users Manual Hardware Description Intel Public 22 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Electrical Characteristics 6.3 DC Characteristics 6.3.1 Table 6. Parameter Pad Driver and Input Stages For more information, see Chapter 1.4. Internal1 (1.5 V) Supplied Pins Input low voltage Input high voltage Output low voltage Output high voltage Continuous Load1 Pin Capacitance Magnitude Pin Leakage Symbol Values Unit Note / Test Condition Min.
-0.3 1.15 1.1 Typ. Max. 0.01 0.27 3.6 0.25 1 10 1 V V V V mA pF A IOL = 1 mA IOH = -1 mA Input and output drivers disabled 1. The total continuous load for all Internal1 supplied pins shall not exceed 2 mA at the same time Table 7. Parameter Internal2 (2.5 V) Supplied Pins Symbol Values Unit Note / Test Condition Input low voltage Input high voltage Input high voltage Output low voltage Output low voltage Output high voltage Output high voltage Continuous Load1 Pin Capacitance Magnitude Pin Leakage Min. Typ. Max.
-0.3 1.93 1.93 2.0 2.1 0.01 0.45 2.8 3.6 0.25 0.15 5 10 1 V V V V V V V mA pF A P0.10 Other pins IOL = 5 mA IOL = 2 mA IOH = -5 mA IOH = -2 mA Input and output drivers disabled 1. The total continuous load for all Internal2 supplied pins shall not exceed 35 mA at the same time Users Manual Hardware Description Intel Public 23 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Electrical Characteristics Table 8. Parameter VDDUART Supplied Pins Symbol Values Unit Note / Test Condition Input low voltage Input high voltage Input high voltage Output low voltage Output low voltage Output high voltage Output high voltage Continuous Load1 Pin Capacitance Magnitude Pin Leakage Min. Typ. Max.
-0.3 0.7*VDDUART 0.7*VDDUART VDDUART
-0.25 VDDUART
-0.15 0.01 0.2*VDDUART VDDUART+0.3 3.6 0.25 0.15 5 10 1 V V V V V V V mA pF A P0.5/UARTRXD Other pins IOL = 5 mA VDDUART = 2.5 V IOL = 2 mA VDDUART = 2.5 V IOH = -5 mA VDDUART = 2.5 V IOH = -2 mA VDDUART = 2.5 V Input and output drivers disabled 1. The total continuous load for all VDDUART supplied pins shall not exceed 35 mA at the same time Table 9. Parameter VDD1 Supplied Pins Symbol Input low voltage Input high voltage Output low voltage Output low voltage Output high voltage Output high voltage Continuous Load1 Pin Capacitance Magnitude Pin Leakage Min.
-0.3 0.7*VDD1 VDD1
-0.25 VDD1
-0.15 Values Typ. Max. 0.01 0.2*VDD1 3.6 0.25 0.15 5 10 1 Unit Note / Test Condition V V V V V V mA pF A IOL = 5 mA VDD1 = 2.5 V IOL = 2 mA VDD1 = 2.5 V IOH = -5 mA VDD1 = 2.5 V IOH = -2 mA VDD1 = 2.5 V Input and output drivers disabled 1. The total continuous load for all VDD1 supplied pins shall not exceed 35 mA at the same time Table 10. Parameter ONOFF PIN Symbol Input low voltage Input high voltage Input current Values Unit Note / Test Condition Min. 1.7
-1 Typ. 0.01 Max. 0.7 VSUPPLY 1 V V A ONOFF = 0 V Users Manual Hardware Description Intel Public 24 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Electrical Characteristics 6.3.2 Pull-ups and Pull-downs Table 11. Pin P0.12 P0.13 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.10 P0.8 P0.9 P0.11 P0.14 P0.15 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 6.3.3 Pull-up and Pull-down Currents Pull Up Current Pull Down Current Unit Conditions Min. 260 Typ. 740 Max. 1300 Min. N/A 22 130 350 23 Typ. N/A 150 Max. N/A 380 4.2 24 68 3.0 20 55 A A A Pull-up current measured with pin voltage = 0 V Pull-down current measured with pin voltage =
supply voltage Min measured at 125C with supply = 1.35 V Typ. measured at 27C with supply = 2.5V Max measured at -40C with supply = 3.63 V 1.1 6.0 17 0.75 5.0 14 A Protection Circuits All pins have an inverse protection diode against VSS. P0.10 has an inverse diode against Internal2. P0.5/UARTRXD has an inverse diode against VDDUART. All other pins have no diode against their supply. Users Manual Hardware Description Intel Public 25 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Electrical Characteristics 6.3.4 System Power Consumption Table 12. Parameter Vsupply Note:
Max. Load at the Different Supply Voltages Symbol Values Unit Note / Test Condition Min. Typ. Max. 100 mA Peak current I/O currents are not included since they depend mainly on external loads. For more details see [2]. 6.4 RF Part 6.4.1 Characteristics RF Part The characteristics involve the spread of values to be within the specific temperature range. Typical characteristics are the median of the production. All values refers to Intel reference design. 6.4.1.1 Bluetooth Related Specifications Table 13. Parameter BDR - Transmitter Part Symbol Values Unit Note / Test Condition Output power (high gain) Output power (highest gain) Power control step size Frequency range fL Frequency range fH 20 dB bandwidth 2nd adjacent channel power 3rd adjacent channel power
>3rd adjacent channel power Average modulation deviation for 00001111 sequence Minimum modulation deviation for 01010101 sequence Ratio Deviation 01010101 /
Deviation 00001111 Initial carrier frequency tolerance
|foffset|
Carrier frequency drift
(one slot) |fdrift|
Carrier frequency drift
(three slots) |fdrift|
Carrier frequency drift
(five slots) |fdrift|
Carrier frequency driftrate
(one slot) |fdriftrate|
Min. 0.5 4 2400 140 115 0.8 Typ. 2.5 4.5 6 2401.3 2480.7 0.930
-40
-60
-64 156 145 1 10 10 10 5 Max. 4.5 8 2483.5 1
-20
-40
-40 175 75 25 40 40 20 dBm dBm dB MHz MHz MHz dBm dBm dBm kHz kHz kHz kHz kHz kHz kHz/50 ms Default settings Maximum settings Max. 2 of 3 exceptions @ 52 MHz offset might be used Users Manual Hardware Description Intel Public 26 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Electrical Characteristics Table 13. Parameter BDR - Transmitter Part (Continued) Values Symbol Unit Note / Test Condition Carrier frequency driftrate (three slots) |fdriftrate|
Carrier frequency driftrate
(five slots) |fdriftrate|
Table 14. Parameter BDR -Receiver Part Symbol Min. Typ. Max. 5 5 20 20 kHz/50 ms kHz/50 ms Values Unit Note / Test Condition Min. Typ. Max. Sensitivity C/I-performance:
-4th adjacent channel C/I-performance:
-3rd adjacent channel
(1st adj. of image) C/I-performance:
-2nd adjacent channel (image) C/I-performance:
-1st adjacent channel C/I-performance: co. channel C/I-performance:
+1st adjacent channel C/I-performance:
+2nd adjacent channel C/I-performance:
+3rd adjacent channel Blocking performance 30 MHz - 2 GHz Blocking performance 2 GHz - 2.4 GHz Blocking performance 2.5 GHz - 3 GHz Blocking performance 3 GHz - 12.75 GHz Intermodulation performance Maximum input level 10
-27
-27 10
-39
-20
-86
-51
-46
-35
-4 9
-4
-40
-50
-34
-81
-40
-20
-9 0 11 0
-30
-40 dBm dB Ideal wanted signal dB dB dB dB dB dB dB dBm dBm dBm dBm dBm dBm Some spurious responses, but according to BT-specification Some spurious responses, but according to BT-specification Valid for all intermodulation tests Table 15. Parameter EDR - Transmitter Part Symbol Values Unit Note / Test Condition Output power (high gain) Relative transmit power:
PxPSK - PGFSK Carrier frequency stability |i|
Carrier frequency stability |i+0|
Carrier frequency stability |0|
DPSK - RMS DEVM 8DPSK - RMS DEVM DPSK - Peak DEVM 8DPSK - Peak DEVM DPSK - 99% DEVM 8DPSK - 99% DEVM Differential phase encoding Min.
-2.5
-4 99 Typ. Max.
-0.6 2 10 10 20 20 100 2 1 75 75 10 20 13 35 25 30 20 dBm dB kHz kHz kHz
Users Manual Hardware Description Intel Public 27 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Electrical Characteristics Table 15. Parameter EDR - Transmitter Part (Continued) Values Symbol Unit Note / Test Condition 1st adjacent channel power 2nd adjacent channel power 3rd adjacent channel power Table 16. Parameter EDR -Receiver Part DQPSK-Sensitivity 8DPSK-Sensitivityl DQPSK - BER Floor Sensitivity 8DPSK - BER Floor Sensitivity DQPSK - C/I-performance:
-4th adjacent channel DQPSK - C/I-performance:
-3rd adjacent channel (1st adj. of image) DQPSK - C/I-performance:
-2nd adjacent channel (image) DQPSK - C/I-performance:
-1st adjacent channel DQPSK - C/I-performance:
co. channel DQPSK - C/I-performance:
+1st adjacent channel DQPSK - C/I-performance:
+2nd adjacent channel DQPSK - C/I-performance:
+3rd adjacent channel 8DPSK - C/I-performance:
-4th adjacent channel 8DPSK - C/I-performance:
-3rd adjacent channel (1st adj. of image) 8DPSK - C/I-performance:
-2nd adjacent channel (image) 8DPSK - C/I-performance:
-1st adjacent channel 8DPSK - C/I-performance:
co. channel 8DPSK - C/I-performance:
+1st adjacent channel 8DPSK - C/I-performance:
+2nd adjacent channel 8DPSK - C/I-performance:
+3rd adjacent channel Maximum input level Min. Typ. Max.
-40
-26
-20
-40 dBc dBm dBm Carrier power measured at basic rate Carrier power measured at basic rate Symbol Values Unit Note / Test Condition Min. Typ. Max.
-88
-83
-84
-79
-53
-47
-31
-7 11
-9
-44
-50
-48
-44
-25
-5 17
-5
-36
-46
-20
-83
-77
-60
-60
-40
-20
-7 0 13 0
-30
-40
-33
-13 0 5 21 5
-25
-33 dBm dBm dBm dBm dB Ideal wanted signal Ideal wanted signal dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBm Users Manual Hardware Description Intel Public 28 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Package Information 7.0 Package Information 7.1 Package Marking Product ID Date code FCC ID i intelC PBA31309 V1.00 GYYWW /D FYWW9EXX PD9PBA313309 Case PCB Example of marking P B A 3 1 3 0 9 G Y Y W W
/ D F C C I D : Q 2 3 3 1 3 0 8 V 1 . 0 0 F Y W W 9 E X X Marking definition YYWW F Y WW 9E XX
- calendar Year (2digits) + calendar week (2digits) of production
- lot code starts with F
- last digit of assembly year (201 3)
- assembly week = calendar week + 1
- final test ID + assembly site ID
- unique lot sequential number 00-09,0A-0Z,10, , ZZ Figure 6. Package Marking Version Machine readable 2D bar code Intel usage only , could be changed without any notice Package_Marking.vsd Users Manual Hardware Description Intel Public 29 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Package Information 7.2 Production Package 6 5 1
, 0 6 0
, 15,60 0 8 1
, 0 7 8
, Tolerances: +-0.2mm Figure 7. Production Package All dimensions are in mm. 121011_ PAN1322_V1.0.vsd Tolerances on all outer dimensions, height, width and length, are +/- 0.2 mm. 7.2.1 Pin Mark Pin 1 (A1) is marked on bottom footprint and on the top of the shield on the module according to Figure 8. Diameter of pin 1 mark on the shield is 0.40 mm. i intel PBA31309 V1.00 GYYWW /D FYWW9EXX PD9PBA31309 F12 F11 A12 A11 F9 E 9 D9 C9 B 9 A 9 F8 E8 D8 C8 B8 A8 F7 E7 D7 C7 B7 A7 F6 E 6 D6 C6 B 6 A 6 F5 E5 D5 C5 B5 A5 F4 E4 D4 C4 B4 A4 F3 E 3 D3 C3 B 3 A 3 F2 E2 D2 C2 B2 A2 F1 E1 D1 C1 B1 A1 Pin 1 marking top side Pin 1 marking bottom side Top_and_Bottom_Views.vsd Figure 8. Top View and Bottom View Users Manual Hardware Description Intel Public 30 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Bluetooth Qualification and Regulatory Certification 8.0 Bluetooth Qualification and Regulatory Certification 8.1 Reference Design
Figure 9. Reference Design Schematics Users Manual Hardware Description Intel Public 31 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Bluetooth Qualification and Regulatory Certification 8.2 8.3 PBA 31309 is intended to be installed inside end user equipment. PBA 31309 is Bluetoooth-qualified and also FCC-certified, and conforms to R&TTE (European) requirements and directives with the reference design described in Figure 9. Manufacturers of mobile, fixed or portable devices incorporating this device are advised to clarify any regulatory questions and to have their complete product tested and approved for compliance (FCC or other when applicable). There are no parts in PBA 31309 that can be modified by the user except modifications of the device BD data and loading of SW patches. Any changes or modifications made to this device that are not expressly approved by Intel, may void the users authority to operate the equipment. FCC Class B Digital Devices Regulatory Notice This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by 1 or more of the following measures:
Reorient or relocate the antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio or television technician for help FCC Wireless Notice This product emits radio frequency energy, but the radiated output power of this device is far below the FCC radio frequency exposure limits. Nevertheless, the device should be used in such a manner that the potential for human contact with the antenna during normal operation is minimized. To meet the FCC's RF exposure rules and regulations:
The system antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. The on-board antenna used must not be altered. Users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance. See Figure 10. Users Manual Hardware Description Intel Public 32 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Bluetooth Qualification and Regulatory Certification If possible place PBA31309in the center of the main PCB. Min. 15mm 8.7 5.00 0 0
. 3 Restricted Area No copper in any layer Top View 6
. 5 1 m m 0 4
. i n M Min. 15mm e h t t a
. B C P n 9 0 3 1 3 A B P e c a P l i a m e h t f o e g d e Use a Ground plane in the area surrounding the PBA31309 module wherever possible. Dimensions are in mm. Visio-Source-PAN1322.vsd Figure 10. Cutout Drawing Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and to have their complete product tested and approved for FCC compliance. FCC Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
1. This device may not cause harmful interference 2. This device must accept any interference received, including interference that may cause undesired operation. FCC Identifier FCC ID: PD9PBA31309 8.4 8.5 Users Manual Hardware Description Intel Public 33 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Bluetooth Qualification and Regulatory Certification 8.6 European R&TTE Declaration of Conformity Hereby, Intel declares that the Bluetooth module PBA 31309 is in compliance with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labelled as follows:
Figure 11. Equipment Label eUniStone in the specified reference design can be used in the following countries:
Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. Users Manual Hardware Description Intel Public 34 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Bluetooth Qualification and Regulatory Certification Figure 12. Declaration of Conformity The product will be compliant to R&TTE Directive 1999/5/EC: EN 60950-1 2006, EN 50371: 2002 Health and Safety of the User EN301 489-1, v1.8.1, EN301 489-17 v2.1.1 Electromagnetic Compatibility EN300 328 v1.8.1 Effective use of spectrum allocated. Users Manual Hardware Description Intel Public 35 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Bluetooth Qualification and Regulatory Certification 8.7 8.9 8.10 Bluetooth Qualified Design ID Intel has submitted End Product Listings (EPL) for eUniStone and eBMU in the Qualified Product List of the Bluetooth SIG. These EPLs are referencing the Bluetooth qualification of the SPP-AT application running on the eBMU chip under QD ID t.b.d. Manufacturers of Bluetooth devices incorporating eUniStone or eBMU can reference the same QD ID number. Bluetooth QD ID: B021246 Label Design of the Host Product It is recommended to include the following information on the host product label:
Contains transmitter Module FCC ID: PD9PBA31309 Regulatory Test House The test house used by Intel in the Bluetooth and Regulatory approvals for the module PBA 31309:
AT4wireless Parque Tecnologico de Andalucia c/ Severo Ochoa 2 E-29590 - Malaga SPAIN Tel: (34) 95 261 91 00 Fax: (34) 95 261 91 13 www.at4wireless.com Users Manual Hardware Description Intel Public 36 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Assembly Guidelines 9.0 Assembly Guidelines 9.1 The target of this chapter is to provide guidelines for customers to successfully introduce the eUniStone module in production. This includes general description, PCB-
design, solder printing process, assembly, soldering process, rework and inspection. General Description of the Module eUniStone is a Land Grid Array (LGA 6x12) module made for surface mounting. The pad diameter is 0.6 mm and the pitch 1.2 mm. All solder joints on the module will reflow during soldering on the mother board. All components and shield will stay in place due to wetting force. Wave soldering is not possible. Surface treatment on the module pads is Nickel (5-8 m)/Gold (0.04 - 0.10 m). Figure 13 shows the pad layout on the module, seen from the component side. 15.6 mm 1.0 0.6 1.2 2.4 F1 E1 D1 C1 B1 A1 F3 E3 D3 C3 B3 A3 F2 E2 D2 C2 B2 A2 0.6 F4 E4 D4 C4 B4 A4 F5 E5 D5 C5 B5 A5 F6 E6 F7 E7 D6 D7 C6 C7 B6 A6 B7 A7 F8 E8 D8 C8 B8 A8 F9 E9 D9 C9 B9 A9 5 3 1
. 2
. 1 5 3
. 1 Figure 13. Pad Layout on the Module (top view) 5.0 F11 F12 A11 A12 m m 0 7 8
. Users Manual Hardware Description Intel Public 37 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Assembly Guidelines 9.2 Printed Circuit Board Design The land pattern on the PCB shall be according to the land pattern on the module, which means that the diameter of the LGA pads on the PCB shall be 0.6 mm. It is recommended that each pad on the PCB shall be surrounded by a solder mask clearance of about 75 m to avoid overlapping solder mask and pad. If possible place PBA31309in the center of the main PCB. Min. 15mm 8.7 5.00 0 0
. 3 Restricted Area No copper in any layer Top View 6
. 5 1 m m 0 4
. i n M Min. 15mm e h t t a
. B C P n 9 0 3 1 3 A B P e c a P l i a m e h t f o e g d e Use a Ground plane in the area surrounding the PBA31309 module wherever possible. Dimensions are in mm. Visio-Source-PAN1322.vsd Figure 14. Cutout Drawing In order to preserve the characteristics of the embedded antenna, a cutout must be respected under the antenna through all metal layers of the PCB, as shown in drawing Figure 14. Placing the module inside a metal housing or close to metal parts like fasteners, shielding cages, washers, etc. can significantly affect the antenna characteristics. Users Manual Hardware Description Intel Public 38 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Assembly Guidelines 9.3 Solder Paste Printing The solder paste deposited on the PCB by stencil printing has to be of eutectic or near eutectic tin leadfree / lead composition. A no-clean solder paste is preferred, since cleaning of the solder joints is difficult because of the small gap between the module and the PCB. Preferred thickness of the solder paste stencil is 100 - 127 mm (4 - 5 mils). The apertures on the solder paste stencil shall be of the same size as the pads, 0.6 mm. 9.4 Assembly 9.4.1 Component Placement In order to assure a high yield, good placement on the PCB is necessary. As a rule of thumb the tolerable misplacement is 150 mm. This means that the eUniStone module can be assembled with a variety of placement systems. It is recommended to use a vision system capable of package pad recognition and alignment that evaluates the pad locations on the package (in contrast to outline centring). This eliminates the pad to package edge tolerance. The recommendation is to pick and place the module with a nozzle in the centre of the shield. The nozzle diameter shall not be bigger than 4 mm. 9.4.2 Pin Mark Pin 1 (A1) is marked on bottom footprint and on the top of the shield on the module according to Figure 15. Diameter of pin 1 mark on the shield is 0.40 mm. i intel PBA31309 V1.00 GYYWW /D FYWW9EXX FCCID:QG2331308 Pin 1 marking top side Figure 15. Pin Marking F12 F11 A12 A11 F9 E 9 D9 C9 B 9 A 9 F8 E8 D8 C8 B8 A8 F7 E7 D7 C7 B7 A7 F6 E 6 D6 C6 B 6 A 6 F5 E5 D5 C5 B5 A5 F4 E4 D4 C4 B4 A4 F3 E 3 D3 C3 B 3 A 3 F2 E2 D2 C2 B2 A2 F1 E1 D1 C1 B1 A1 Pin 1 marking bottom side Top_and_Bottom_Views.vsd Users Manual Hardware Description Intel Public 39 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Assembly Guidelines 9.4.3 Package eUniStone is packed in tape on reel according to Figure 16. Figure 16. Tape on Reel Users Manual Hardware Description Intel Public 40 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Assembly Guidelines 9.5 Soldering Profile Generally all standard reflow soldering processes (vapour phase, convection, infrared) and typical temperature profiles used for surface mount devices are suitable for the eUniStone module. Wave soldering is not possible. Figure 17 and Figure 18 shows example of a suitable solder reflow profile. One for leaded and one for leadfree solder. 10 1s 30 +20/-10s 90 30s Time [s]
Lead _Solder _Profile .v s d 30 sec max 60 ~ 150 sec 235C max. Temp.[C]
Recommended temp. profile for reflow soldering 150 10C 220 5C 200C Figure 17. Eutectic Lead-Solder Profile Recommended temp. profile for reflow soldering (J-STD-020C) Temp.[C]
260C 255C 217C 200C 150C 25C 60 ~ 120 sec @ 3C/sec max 8 minutes max 6C/sec max Time [s]
LeadF ree _Solder _Profile .v s d Figure 18. Eutectic Leadfree-Solder Profile Users Manual Hardware Description Intel Public 41 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Assembly Guidelines At the reflow process each solder joint has to be exposed to temperatures above solder liquids for a sufficient time to get the optimum solder joint quality, whereas overheating the board with its components has to be avoided. Using infrared ovens without convection special care may be necessary to assure a sufficiently homogeneous temperature profile for all solder joints on the PCB (especially on large, complex boards with different thermal masses of the components). The most recommended types are therefore forced convection or vapour phase reflow. Nitrogen atmosphere can generally improve solder joint quality, but is normally not necessary. The reflow profiles and other reflow parameters are dependent on the used solder paste. The paste manufacturer provides a reflow profile recommendation for this product. Additionally it is important not to overheat the eUniStone module by a too large reflow peak temperature. eUniStone contain several plastic packages and is there by sensitive of the moisture content level at the time of board assembly. Overheating in combination with excessive moisture content could result in package delaminations or cracks (popcorn effect). The heating rate should not exceed 3C/s and max sloping rate should not exceed 4C/s. eUniStone shall be handled according to MSL3, which means a floor life of 168 h in 30C/60% r.h. The eUniStone module can be soldered according to max. J-STD-020C curve, assuming that all other conditions are followed stated in Product Specification, Qualification Report and in Application Note. Restriction is that PBA 31309 can be soldered two times, since one time is already consumed when soldering devices on Module. 9.6 Rework 9.6.1 Removal Procedure 1. Heat the module with an appropriate heating nozzle according to the instruction of the equipment or on a hot plate (about 225C dependent on the board). Hot plate can only be used if the board is single side assembled. The temperature of the module shall be 200-220C. 2. Use grippers or a pair of tweezers to remove the module. The module has to be gripped on two opposite edges of the module (not on the shield). 3. Remove excess solder by using solder sucker, suction soldering irons or solder wick. 9.6.2 Replacement Procedure Replacement can be done in two ways, dependent of how the solder is applied. Solder can be applied either by dispensing on the mother board or by printing the solder paste directly on the module. 9.6.2.1 Alternative 1: Dispensing Solder A dispenser with controlled volume must be used to assure the same volume on every pad. The volume on each pad shall be about 0.04 mm3. 1. Dispense 0.04 mm3 on each LGA pad 2. Pick the module by a nozzle and place in the right position on the board 3. Reflow the solder. Users Manual Hardware Description Intel Public 42 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Assembly Guidelines 9.6.2.2 Alternative 2: Printing Solder To print solder on the module a fixture must be used. The purpose of the fixture is to get a flat surface and fix the stencil and module for printing. An example of how this fixture can be designed is shown in Figure 19. Solder paste stencil C avity of the module Vacuum hol es B ottom Tooling pins Fixture Solder _Printing .v s d Figure 19. Solder Printing 1. Assemble the fixture to the bottom 2. Place the module in the cavity with the LGA pads upwards 3. Place the solder paste stencil on the fixture and make sure it fits to the tooling pins and the module 4. Apply vacuum to fix the solder paste stencil 5. Apply solder paste on the stencil and print by using a blade 6. Turn everything (bottom, fixture and stencil) upside down. 7. Separate carefully the bottom from the fixture 8. Pick the module by a nozzle and place in the right position on the board 9. Reflow the solder. 9.7 Inspection Automatic inspection of the solder paste printing before assembly is highly recommended to ensure high yield and good long term reliability. Users Manual Hardware Description Intel Public 43 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Assembly Guidelines 9.8 Component Salvage If it is intended to send a defect eUniStone module back to the supplier for failure analysis, please note that during the removal of this component no further defects must be introduced to the device, because this may hinder the failure analysis at the supplier. This includes ESD precautions, not to apply high mechanical force for component removal, and to prevent excess moisture content in the package during salvage (risk of pop corning failures). Therefore if the maximum storage time out of the dry pack (see label on packing material) is exceeded after board assembly, the PCB has to be dried 24h at 125C before soldering off the defect component, because otherwise too much moisture may have been accumulated. 9.9 Voids in the Solder Joints 9.9.1 Expected Void Content and Reliability The content of voids is larger on LGA modules than for modules with BGA or leads. At a LGA solder joint the outgassing flux has a longer way to the surface of the solder and it has a relatively small surface to the air. The void content of the eUniStone module conforms to IPC-A-610D (25% or less voiding area/area). Figure 20 shows an example of void-content at a module assembled at production site. Normally you can see the whole spectra of void content variation within the same lot and occasion of assembly. Figure 20. X-ray Picture Showing Voids Conforming to IPC-A-610D Voids _IPC _A_ 610D .v s d Users Manual Hardware Description Intel Public 44 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Assembly Guidelines 9.9.2 Parameters with an Impact on Voiding If the void content has to be reduced following parameters have an impact. Solderability on module and PCB Bad solderability is often connected to oxidation and has therefore a major impact on voiding. Flux will get entrapped on oxidized surfaces. In general, Ni/Au pads show fewer voids than HASL and OSP. Solder paste Higher activity of the flux will remove oxide rapidly and less flux will get entrapped. Voiding increases with increasing solder paste exposure time, since long exposure time will result in more oxidation and moisture pickup. Pad size A large soldering pad means that the outgassing flux has a longer way to the surface of the solder, and will thereby create more voids. Solder paste Smaller powder size and higher metal load means more metal surface to deoxidize and thereby more entrapped flux and voiding. Higher metal load does also mean higher viscosity and more difficult for outgassed flux to remove from the solder. Stencil thickness A thick solder paste stencil means more surface area to the air and thereby easier for the outgassing flux to leave the solder. Temperature soldering profile Too short preheat time means that the flux does not get enough time to react and flux get entrapped in the solder and create voids. Too long reflow time gives larger voids Too short reflow time gives a fraction of voids Users Manual Hardware Description Intel Public 45 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 References
[1] Intel AT Command Specification
(eUniStone_1.00_UM_SD.pdf)
[2] Release Notes for SPP AT application SW version 1.1
(eUniStone_1.00_SW_3.1_RN.pdf) Users Manual Hardware Description Intel Public 46 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 Terminology A ACK ACL AFH AHS ARQ B b B BALUN BD_ADDR BER BMU BOM BT BW C CDCT CMOS COD CODEC CPU CQDDR CRC CTS CVSD D DC DDC DM DMA DH DPSK DQPSK DSP DUT E EDR EEPROM eSCO EV F FEC Acknowledgement Asynchronous Connection-oriented (logical transport) Adaptive Frequency Hopping Adaptive Hop Sequence Automatic Repeat reQuest bit/bits (e.g. kb/s) Byte/Bytes (e.g. kB/s) BALanced UNbalanced Bluetooth Device Address Bit Error Rate BlueMoon Universal Bill Of Material Bluetooth Bandwidth Clock Drift Compensation Task Complementary Metal Oxide Semiconductor Class Of Device COder/DECoder Central Processing Unit Channel Quality Driven Data Rate Cyclic Redundancy Check Clear To Send (UART flow control signal) Continuous Variable Slope Delta (modulation) Direct Current Device Data Control Data Medium-Rate (packet type) Direct Memory Access Data High-Rate (packet type) Differential Phase Shift Keying (modulation) Differential Quaternary Phase Shift Keying (modulation) Digital Signal Processor Device Under Test Enhanced Data Rate Electrically Erasable Programmable Read Only Memory Extended Synchronous Connection-Oriented (logical transport) Extended Voice (packet type) Forward Error Correction Users Manual Hardware Description Intel Public 47 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 FHS FIFO FM FW G GFSK GPIO GSM H HCI HCI+
HEC HV HW I I2C I2S IAC ID IEEE IF ISM J JTAG L LAN LAP LM LMP LNA LO LPM LPO LSB LT_ADDR M MSB MSRS N NC NOP NVM O OCF OGF P PA PCB PCM PDU PER PIN Frequency Hop Synchronization (packet) First In First Out (buffer) Frequency Modulation Firmware Gaussian Frequency Shift Keying (modulation) General Purpose Input/Output Global System for Mobile communication Host Controller Interface Intel Specific HCI command set Header Error Check High quality Voice (packet type) Hardware Inter-IC Control (bus) Inter-IC Sound (bus) Inquiry Access Code IDentifier Institute of Electrical and Electronics Engineers Intermediate Frequency Industrial Scientific & Medical (frequency band) Joint Test Action Group Local Area Network Lower Address Part Link Manager Link Manager Protocol Low Noise Amplifier Local Oscillator Low Power Mode(s) Low Power Oscillator Least Significant Bit/Byte Logical Transport Address Most Significant Bit/Byte Master-Slave Role Switch No Connection No OPeration Non-Volatile Memory Opcode Command Field Opcode Group Field Power Amplifier Printed Circuit Board Pulse Coded Modulation Protocol Data Unit Packet Error Rate Personal Identification Number Users Manual Hardware Description Intel Public 48 Revision 1.0, 1-Feb-2013 eUniStone PBA 31309 PLC PLL PMU POR PTA PTT Q QoS R RAM RF ROM RSSI RTS RX RXD S SCO SIG SW SYRI T TBD TCK TDI TDO TL TMS TX TXD U UART ULPM V VCO W WLAN Packet Loss Concealment Phase Locked Loop Power Management Unit Power-On Reset Packet Traffic Arbitration Packet Type Table Quality Of Service Random Access Memory Radio Frequency Read Only Memory Received Signal Strength Indication Request To Send (UART flow control signal) Receive Receive Data (UART signal) Synchronous Connection-Oriented (logical transport) Special Interest Group (Bluetooth SIG) Software Synthesizer Reference Input To Be Determined Test Clock (JTAG signal) Test Data In (JTAG signal) Test Data Out (JTAG signal) Transport Layer Test Mode Select (JTAG signal) Transmit Transmit Data (UART signal) Universal Asynchronous Receiver & Transmitter Ultra Low Power Mode Voltage Controlled Oscillator Wireless LAN (Local Area Network) Users Manual Hardware Description Intel Public 49 Revision 1.0, 1-Feb-2013 This document has been formally released by DOC department (IMC-DOC@intel.com) on February 16, 2013
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2013-09-11 | 2402 ~ 2480 | DSS - Part 15 Spread Spectrum Transmitter | Original Equipment |
2 | JBP - Part 15 Class B Computing Device Peripheral |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 2 | Effective |
2013-09-11
|
||||
1 2 | Applicant's complete, legal business name |
Intel Corporation
|
||||
1 2 | FCC Registration Number (FRN) |
0008035131
|
||||
1 2 | Physical Address |
100 Center Point Circle
|
||||
1 2 |
Columbia, South Carolina 29210
|
|||||
1 2 |
United States
|
|||||
app s | TCB Information | |||||
1 2 | TCB Application Email Address |
h******@acbcert.com
|
||||
1 2 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
1 2 |
A1: Low Power Transmitters below 1 GHz (except Spread Spectrum), Unintentional Radiators, EAS (Part 11) & Consumer ISM devices
|
|||||
app s | FCC ID | |||||
1 2 | Grantee Code |
PD9
|
||||
1 2 | Equipment Product Code |
PBA31309
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 2 | Name |
S******** C******** H********
|
||||
1 2 | Title |
Product Regulations Engineer
|
||||
1 2 | Telephone Number |
803-3********
|
||||
1 2 | Fax Number |
803-2********
|
||||
1 2 |
s******@intel.com
|
|||||
app s | Technical Contact | |||||
1 2 | Firm Name |
Intel Mobile Communications
|
||||
1 2 | Name |
S****** H****
|
||||
1 2 | Physical Address |
100 Center Point Circle Suit 200
|
||||
1 2 |
Columbia, South Carolina 29210
|
|||||
1 2 |
United States
|
|||||
1 2 | Telephone Number |
80321********
|
||||
1 2 | Fax Number |
80321********
|
||||
1 2 |
s******@intel.com
|
|||||
app s | Non Technical Contact | |||||
n/a | ||||||
app s | Confidentiality (long or short term) | |||||
1 2 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 2 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 2 | If so, specify the short-term confidentiality release date (MM/DD/YYYY format) | 03/10/2014 | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 2 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 2 | Equipment Class | DSS - Part 15 Spread Spectrum Transmitter | ||||
1 2 | JBP - Part 15 Class B Computing Device Peripheral | |||||
1 2 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | Bluetooth Wireless Adapter | ||||
1 2 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 2 | Modular Equipment Type | Single Modular Approval | ||||
1 2 | Purpose / Application is for | Original Equipment | ||||
1 2 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | Yes | ||||
1 2 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 2 | Grant Comments | Power Output listed is conducted. Modular Approval filing, the antenna(s) used for this transmitter must not be co-located with any other transmitters except in accordance with FCC multi-transmitter product procedures. Only those antenna(s) tested with the device or similar antenna(s) with equal or lesser gain may be used with this transmitter. This filing meets the SAR threshold exclusion set forth in KDB447498 and therefore can be used in mobile/portable configurations. End-users and installers must be provided with transmitter operating conditions for satisfying RF exposure compliance. | ||||
1 2 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 2 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 2 | Firm Name |
TUV Rheinland Nederland B.V.
|
||||
1 2 | Name |
R**** v****
|
||||
1 2 | Telephone Number |
31-08********
|
||||
1 2 | Fax Number |
31-59********
|
||||
1 2 |
r******@nl.tuv.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15C | CC | 2402.00000000 | 2480.00000000 | 0.0010000 | |||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
2 | 1 | 15B | CC |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC