FCC ID: 2APJ4-SNM955 Wi-Fi 6E Smart Module with Bluetooth and WiFi

Technical data of meige intelligent products SNM955 Hardware Design Manua l Release DateApril 2022 The Name Of The Controlled File SNM955 Hardware Design Mannual Controlled VersionV1.00 PublisherMEIG SWART TECHNOLOGY CO .LTD SRM955 Hardware Design Manual Page 1 Technical data of meige intelligent products Important Notice Copyright Notice Copyright: Meige Intelligent Technology Co., Ltd. This information and all contents contained therein are owned by Meige Intelligent Technology Co., Ltd. and are protected by relevant copyright laws in Chinese laws and applicable international conventions. Without the written authorization of Meige Intelligent Technology Co., Ltd., no one may copy, disseminate, distribute, modify or otherwise use part or all of this information in any form. Violators will be held accountable according to law. Disclaimer Of Warranty MeiGe Intelligent Technology Co., Ltd. makes no representations or warranties, express or implied, with respect to any content in this document, and shall not be liable for merchantability and fitness for a particular purpose or for any indirect, special or consequential damages. Confidentiality Statement The information contained in this document (including any attachments) is confidential. The recipient understands that this document obtained by him is confidential and shall not be used for any purpose other than the specified purpose, nor shall this document be disclosed to any third party. Disclaimer The company is not responsible for property or personal injury caused by abnormal operation of the customer. Customers are requested to develop corresponding products according to the technical specifications and reference designs in the manual. Before making a statement, the company has the right to change the content of this manual according to the needs of technological development, and the changed version will not be notified. SNM955 Hardware Design Manual Page 2 Technical data of meige intelligent products SNM955 Hardware Design Mannua l V1.00 SNM955 Hardware Design Manual Page 3 Technical data of meige intelligent products Foreword Thanks for using the SNM955 module provided by Meige Smart. This product can provide data communication services. Please read the design manual carefully before use, it will help you fully understand the function of the module. The company is not responsible for property damage or personal injury caused by the user's abnormal operation. Users are requested to develop corresponding products according to the technical specifications and reference designs in the manual. Also pay attention to the general safety precautions you should be aware of when using mobile products

. Before making a statement, the company has the right to modify the contents of this manual according to the needs of technological development. SNM955 Hardware Design Manual Page 4 Technical data of meige intelligent products Content 1. Introduction................................................................................................................................................................8 2.Module Overview....................................................................................................................................................... 9 2.1. Main Features Of The Module..................................................................................................................... 10 2.2. Functional Block Diagram Of The Module................................................................................................. 12 3.Module Packaging.................................................................................................................................................... 12 3.1. Pinout Diagram.............................................................................................................................................12 3.2. Description Of Module Pins.........................................................................................................................13 3.3. Mechanical Dimensions............................................................................................................................... 29 3.4. Recommended Package................................................................................................................................30 4.Interface Application................................................................................................................................................ 31 4.1. Power............................................................................................................................................................ 31 4.1.1. Power Pin...........................................................................................................................................32 4.2. Power On And Off........................................................................................................................................ 33 4.2.1. Power-on Of The Module..................................................................................................................33 4.2.2. Module Shutdown............................................................................................................................. 34 4.2.3. Module Reset.....................................................................................................................................34 4.3. VCOIN Power.............................................................................................................................................. 36 4.4. Power Output................................................................................................................................................ 37 4.5. Serial Port..................................................................................................................................................... 38 4.6. MIPI Interface...............................................................................................................................................40 4.6.1. LCD Interface.................................................................................................................................... 40 4.6.2. MIPI Camera Interface...................................................................................................................... 42 4.7. Resistive Touch Interface............................................................................................................................. 46 4.8. Capacitive Touch Interface........................................................................................................................... 47 4.9. Audio Interface............................................................................................................................................. 48 4.9.1. Receiver Interface Circuit................................................................................................................. 49 4.9.2. Microphone Receiver Circuit............................................................................................................ 49 4.9.3. Headphone Interface Circuit............................................................................................................. 50 4.9.4. Circuit Of The Speaker Interface...................................................................................................... 51 4.9.5. I2S Interface...................................................................................................................................... 51 4.10. USB Interface............................................................................................................................................. 52 4.10.2. DP Screen Interface......................................................................................................................... 53 4.11. UIM Card Interface.....................................................................................................................................55 4.12. SD Card Interface....................................................................................................................................... 56 4.13. I2C Bus Interface........................................................................................................................................57 4.14. Analog To Digital ConverterADC......................................................................................................58 4.15. PWM...........................................................................................................................................................59 4.16. Antenna Interface........................................................................................................................................60 4.16.1 WAN ANT(ANT_0/1 )..................................................................................................................... 60 4.16.2 GPS Antenna.................................................................................................................................... 61 4.16.3 WiFi/BT Antenna..............................................................................................................................61 PCB Layout.......................................................................................................................................................63 5.1. Module PIN Distribution..............................................................................................................................63 5.2. PCB Layout Guidelines................................................................................................................................64 5.2.1. Antenna.............................................................................................................................................. 64 5.2.2. Power.............................................................................................................................................. 64 5.2.3. SIM Card........................................................................................................................................... 64 5.2.4. T Card................................................................................................................................................ 65 5.2.5. MIPI...................................................................................................................................................65 5.2.6. USB....................................................................................................................................................65 5.2.7. Audio..................................................................................................................................................66 5.2.8. Other.................................................................................................................................................. 66 6. Electrical, Reliability.............................................................................................................................................. 67 6.1. Absolute Maximum...................................................................................................................................... 67 6.2. Operating Temperature................................................................................................................................. 68 6.3. Operating Voltage......................................................................................................................................... 69 6.4. Digital Interface Features............................................................................................................................. 70 5. SNM955 Hardware Design Manual Page 5 Technical data of meige intelligent products 6.5. Characteristics Of SIM_VDD...................................................................................................................... 71 6.6. Features Of PWRKEY................................................................................................................................. 72 6.7. Features Of VCOIN......................................................................................................................................73 6.8. Current Consumption (VBAT=3.8V)...........................................................................................................74 6.9. Static Protection............................................................................................................................................75 6.10. Module Working Frequency.......................................................................................................................76 6.11. RF Characteristics.......................................................................................................................................78 6.12. Module Conducted Receive Sensitivity..................................................................................................... 79 6.13. The Main RF Performance Of WIFI.......................................................................................................... 81 6.14. Main RF Performance Of BT..................................................................................................................... 82 6.15. Key RF Performance Of GNSS..................................................................................................................83 Production.......................................................................................................................................................84 7.1. Top And Bottom Views Of The Module...................................................................................................... 84 7.2. Recommended Welding Furnace Temperature Curve..................................................................................85 7.3. Moisture Sensitive Characteristics (MSL)................................................................................................... 86 7.4. Baking Demand............................................................................................................................................ 87 8.Support The List Of Peripheral Devices.................................................................................................................. 88 Appendix.......................................................................................................................................................90 9. 9.1. Related Documentation................................................................................................................................ 90 9.2. Terminology And Explanation..................................................................................................................... 91 9.3. Reuse Function............................................................................................................................................. 93 9.4. Safety Warning............................................................................................................................................. 95 7. SNM955 Hardware Design Manual Page 6 Technical data of meige intelligent products Revision History Time 2022-04 Version 1.00 Revision Rreason Initial establishment Author Hardware Department SNM955 Hardware Design Manual Page 7 Technical data of meige intelligent products 1. Introduction This document describes the hardware application interface of the module, including circuit connections and radio frequency interfaces in related applications. It can help users to quickly understand the detailed information of the module's interface definition, electrical performance and structural dimensions. Combined with this document and other application documents, users can quickly use modules to design mobile communication applications. SNM955 Hardware Design Manual Page 8 Technical data of meige intelligent products 2. Module Overview The main chip used in the SNM955 series core board is Qualcomm Q C S 6 4 9 0

, which adopts 6nm process technology and has a built-in 8-core Kryo CPU 6xx (Kryo Gold plus: 1 high-performance core at 2.7GHz, Kryo Gold: 3 high-performance cores at 2.4GHz Performance cores, Kryo Silver: 4 1.9GHz low-power cores). The physical interface of the module is the 536 PIN LGA pad, whic h provides the following hardware interfaces:

One-way LCD interfaceMIPI-DSI Five-way Camera interfaceMIPI-CSI Four-way flash interface Three-way indicator interface Two-way USB2.0 interface One-way USB3.1 interface Four-way analog MIC input interfaces Three-way digital MIC interface Two sets of I2S interfaces (multiplexing physical interface with digital MIC) Three-way analog audio output interface (headphone, earpiece, AUX) Two-way UIM card interface GPIO interface Three-way 1.8V UART interface, support four-wire or two-wire Ten-way groups of I2C interfaces One set of I3C interface Two sets of SPI interfaces One set of PCIe interface (2-lane Gen3) One SD card interface Support WiFi, Bluetooth 5.1 function SNM955 Hardware Design Manual Page 9 Technical data of meige intelligent products 2.1. Main Features Of The Module Table 2.1Main features of the module Product features Describe Platform Qualcomm QCS6490 CP U GPU 8 nuclear Kryo CPU 6xx Adreno GPU 6XX@812MHz System Memory UMCP128GB UFS3.1+8GB LPDDR5 Operating System Android 11.0 Size 55*45*3.95mm536pin of LGA package America Edition NA Wi-F i Bluetooth F M GNSS Data s Acces 5G NR E LT SIM Displa y Camera Input Device Reset Application WCN6856: 2x2 IEEE 802.11a/b/g/n/ac/ax 2.4G&5G BT 5.2 Not support NA NA NA NA FHD+ 144Hz QCLTM, HDR10+,WCG LCD Size: User defined Interface: LCMMIPI DSI 4-lane;

Interface: Can support five groups of CSI, each group is 4-Lane, supports D-PHY 1.2 (2.5Gbps/lane) or C-PHY 1.2 (10.26Gbps/T) Triple 14-bit image signal processing (ISP) + two lite ISP 22 + 22 + 22MP, 64 MP/30 fps Video decode Video encode Keys (PWR key, Home, RESET, VOL+, VOL-) Capacitive TP Support hardware reset 4K60 for H.264/H.265/P9 Up to 4K30 for H.264/H.265 The name of Description of main functions SNM955 Hardware Design Manual Page 1 0 Technical data of meige intelligent products Interface the interface VBAT SDIO 4pin, module power input, 3.5V4.35V, nominal value 3.8V TF Card, up to 128GB Support OTG USB2.0(3.0) USB_BOOTForce USB boot for emergency download BLSP ports QUP(SE0~SE7)QUP1(SE1~SE6), 4-bits each, multiplexed serial interface functions UART I2C SPI(master only) ADC Charging function Motor GPIO VCOIN Support 3-way UART by defaultExpandable via QUP interface By default, 10 channels of I2C are supported, of which 6 channels are dedicated I2CExpandable via QUP interface Two sets of SPI are supported by default (expandable through the QUP interface Support 8-channel ADC Support QC4.0+USB PD Support ERM 103GPIO Battery backup for real time clock RF interface ANT6:WiFi/BT ANT0 ANT7:Wifi ANT1 4-way analog MIC interface 3-way digital MIC interface 2 groups of I2S interface (multiplexing physical interface Audi o with digital MIC) 1 channel AUX signal (requires external audio PA) 1 way handset 1 channel stereo headphone (including headphone MIC) SNM955 Hardware Design Manual Page 1 1 Technical data of meige intelligent products 2.2. Functional Block Diagram Of The Module The following figure lists the main functional parts of the module:

Q C S 6 4 9 0 baseband chip PM7325, PM7350C, PM7250B, PMK7325 power management chip WCN6856-WIFI/BT combo chip Antenna interface LCD/CAM-MIPI interface UMCP memory chip AUDIO interface USB, SD card, SIM card interface, etc. Figure 2.1: Module function box 3. Module Packaging 3.1. Pinout Diagram SNM955 Hardware Design Manual Page 1 2 Technical data of meige intelligent products Note: The yellow PIN represents the antenna interface, the orange PIN represents the high-speed signal interface, the blue PIN represents the audio, ADC and other analog signal interfaces, the red PIN represents the power supply interface, and the green PIN represents the general signal interface. Figure 3.1: Module Pin Diagram 3.2. Description Of Module Pins Table 3.1: Pin Descriptions The name of the pin Pin number I/O Describe VBAT Power 460461462 463 The module provides 4 VBAT I/O power pins. Voltage range 3.5V to 4.35V. Remark External need to increase VPH_PWR SNM955 Hardware Design Manual 456457458 O System power output, typical capacitance Page 1 3 458 value is 3.8V. Can supply and surge power to peripherals. tube Charging input interface and protection USB_VBUS 466467468 469 OTG power output interface. I/O Support USB plug-in detection, maximum support 12V charging. When the system power VBAT is not in place, the external backup battery VCOIN 471 I/O provides power to the system real-time clock. The backup battery is charged while VBAT is in place. Connect a 3V button battery or a large capacitor the pin. to VCOIN VREG_L2C_1P8(RESERVED) 416 VREG_L3C_3P0(TPVDD) 501 VREG_L4C_1P8_3P0(VSIM1) 338 VREG_L5C_1P8_3P0(VSIM2) 350 VREG_L6C_2P96(SDVIO) 413 VREG_L7C_3P0(SENSOR_VD D) 417 VREG_L8C_1P8(SENSOR_VD DIO) 504 VREG_L9C_2P96(SD_VDD) 414 VREG_L11C_2P8(WCN_VDD) 415 VREG_L12C_1P8(OLED VDDIO) 418 VREG_L13C_3P0(OLED VCI) 427 VREG_L2B_3P072(USBHS_VI O) VREG_L11B_1P776(SDR_VDD

) SNM955 Hardware Design Manual 492 125 O O O O O O O O O O O O O 1.8V power output, DMIC reserved power, default NC 150mA 3.0V power output, can be used for TP VDD power supply 150mA 1.8/3.0V power output, UIM1 power supply pin 1.8/3.0V power output, UIM2 power supply pin 3V power output for SD card signal pull-up 3V power output, it will be turned off during standby, and can be used to power the Sensor. 1.8V power output, it will be turned off during standby, used as IO power supply for Sensor, CAM, TP 3V power output for SD card VCC power supply 2.8V power output for WCN_VDD power supply 1.8V power output, it will be turned off during standby, and can be used for OLED IO power supply. 3V power output, it will be turned off during standby, and can be used for OLED VCI power supply. 3.1V power output for USB_HS, PDPHY, etc. 1.776V power output, can be used for RF SDR, QPM and 150mA 150mA 150mA 300mA 300mA 600mA 300mA 150mA 150mA 150mA 300mA Page 1 4 VREG_L18B_1P8 419 VREG_L19B_1P8(RF_VDDIO) 532 VREG_SYS_1P8 424 other related power supply 1.8V power output, always supply when power on, used for power supply of CPU, Memory, IO pull-up, etc. 1.8V power output, can be used for RFFE loads power supply 1.8V power output, only used for SMB parallel charging chip. O O O 300mA 300mA 50mA GND 8111229303229303236 37383940414951525758 6366687378919899101 103105107108109110111112 113115117118119120121122 123124125127132134137138 140142144145147148152165 168171175176178181184189 192197198201202205206207 209212216221224229230235 236237238243244245246250 254256265267268271275276 277282284289290293294295 296300301302306307308315 325339341342347357360363 368371374378385386389392 395400408431440441448449 454455464465470472477478 479480481482483484485486 487488494496497503510511 512513533534535536 Main Display Interface (MIPI) Ground MIPI_DSI0_CLK_N MIPI_DSI0_CLK_P MIPI_DSI0_LANE0_N MIPI_DSI0_LANE0_P MIPI_DSI0_LANE1_N MIPI_DSI0_LANE1_P MIPI_DSI0_LANE2_N MIPI_DSI0_LANE2_P MIPI_DSI0_LANE3_N MIPI_DSI0_LANE3_P LCD_RST_N/GPIO44*

LCD_TE/GPIO80*

LCD_ID/GPIO46 BL_PWM/PM7350C_GPIO9 SNM955 Hardware Design Manual 406 407 390 391 396 397 398 399 404 405 393 401 394 412 O O O O O O O O O O I/O I/O I/O I/O MIPI_DSI clock line MIPI_DSI data line LCD reset pin LCD frame sync signal LCD_ID signal Backlight chip PWM control Page 1 5 System Debug UART DBG_UART_TX/GPIO22 DBG_UART_RX/GPIO23*

UART2_TX/GPIO26 UART2_RX/GPIO27*

UART1_TX/GPIO18*

UART1_RX/GPIO19*

UIM1_DATA UIM1_CLK UIM1_RESET_N UIM1_PRESENT/GPIO116*

UIM2_DATA UIM2_CLK UIM2_RESET_N UIM2_PRESENT/GPIO112*

MIPI_CSI0_CLK_P MIPI_CSI0_CLK_N MIPI_CSI0_LANE0_P MIPI_CSI0_LANE0_N MIPI_CSI0_LANE1_P MIPI_CSI0_LANE1_N MIPI_CSI0_LANE2_P MIPI_CSI0_LANE2_N MIPI_CSI0_LANE3_P MIPI_CSI0_LANE3_N CCI_I2C0_SCL/GPIO70 CCI_I2C0_SDA/GPIO69 MCAM_PWD_N/GPIO107 CAM_MCLK0/GPIO64 CAM0_RST_N/GPIO20*

MIPI_CSI3_CLK_P MIPI_CSI3_CLK_N MIPI_CSI3_LANE0_P 528 529 507 506 157 158 344 343 337 336 349 348 346 345 232 231 228 227 226 225 220 219 218 217 223 222 215 214 213 86 85 87 signal UART(1.8V) O I O I O I UART data transmission UART data reception UART data transmission UART data reception UART data transmission UART data reception UIM interface I O O UIM1 data signal UIM1 clock signal UIM1 reset signal I/O UIM1 insertion monitoring I O O UIM2 data signal UIM2 clock signal UIM2 reset signal I/O UIM2 insertion monitoring REAR CAM O O I I I I I I I I I/O I/O I/O I/O I/O REAR CAM MIPI clock REAR CAM MIPI data REAR CAM I2C_SCL REAR CAM I2C_SDA REAR CAM sleep signal REAR CAM master clock REAR CAM reset signal FRONT CAM O O I FRONT CAM MIPI clock FRONT CAM MIPI data SNM955 Hardware Design Manual Page 1 6 MIPI_CSI3_LANE0_N MIPI_CSI3_LANE1_P MIPI_CSI3_LANE1_N MIPI_CSI3_LANE2_P MIPI_CSI3_LANE2_N MIPI_CSI3_LANE3_P MIPI_CSI3_LANE3_N CCI_I2C3_SCL/GPIO76 CCI_I2C3_SDA/GPIO75*

SCAM_PWD_N/GPIO43*

CAM_MCLK3/GPIO67 CAM3_RST_N/GPIO78*

MIPI_CSI1_CLK_P MIPI_CSI1_CLK_N MIPI_CSI1_LANE0_P MIPI_CSI1_LANE0_N MIPI_CSI1_LANE1_P MIPI_CSI1_LANE1_N MIPI_CSI1_LANE2_P MIPI_CSI1_LANE2_N MIPI_CSI1_LANE3_P MIPI_CSI1_LANE3_N CCI_I2C1_SCL/GPIO72*

CCI_I2C1_SDA/GPIO71 DCAM_PWD_N/GPIO42 CAM_MCLK1/GPIO65 CAM1_RST_N/GPIO21*

MIPI_CSI2_CLK_P MIPI_CSI2_CLK_N MIPI_CSI2_LANE0_P MIPI_CSI2_LANE0_N MIPI_CSI2_LANE1_P MIPI_CSI2_LANE1_N MIPI_CSI2_LANE2_P MIPI_CSI2_LANE2_N 84 88 83 89 82 90 81 94 93 96 97 95 80 79 72 71 70 69 62 61 60 59 77 76 75 74 67 180 179 186 185 188 187 194 193 I I I I I I I I/O I/O I/O I/O I/O DEPTH CAM O O I I I I I I I I I/O I/O I/O I/O I/O FRONT CAM/RESERVED CAM I2C_SCL FRONT CAM/RESERVED CAM I2C_SDA FRONT CAM sleep signal FRONT CAM master clock FRONT CAM reset signal DEPTH CAM MIPI clock DEPTH CAM MIPI data DEPTH CAM I2C_SCL DEPTH CAM I2C_SDA DEPTH CAM sleep signal DEPTH CAM master clock DEPTH CAM reset signal RESERVED CAM1 RESERVED CAM1 MIPI clock RESERVED CAM1 MIPI data O O I I I I I I SNM955 Hardware Design Manual Page 1 7 MIPI_CSI2_LANE3_P MIPI_CSI2_LANE3_N CCI_I2C2_SCL/GPIO74 CCI_I2C2_SDA/GPIO73 FP_RST/GPIO35*

CAM_MCLK2/GPIO66 CAM2_RST_N/GPIO77*

MIPI_CSI4_CLK_P MIPI_CSI4_CLK_N MIPI_CSI4_LANE0_P MIPI_CSI4_LANE0_N MIPI_CSI4_LANE1_P MIPI_CSI4_LANE1_N MIPI_CSI4_LANE2_P MIPI_CSI4_LANE2_N MIPI_CSI4_LANE3_P MIPI_CSI4_LANE3_N CAM_MCLK4/GPIO68*

GPIO1 MI2S_MCLK/GPIO96 CCI_I2C2_SCL/GPIO74 CCI_I2C2_SDA/GPIO73 MIC1_IN_M MIC1_IN_P HPHMIC_IN2_P HPHMIC_IN2_M MIC3_IN_M MIC3_IN_P MIC_BIAS1 MIC_BIAS2 MIC_BIAS3 MIC4_IN_P MIC4_IN_M SNM955 Hardware Design Manual 196 195 183 182 313 190 191 169 170 163 164 161 162 155 156 153 154 151 172 283 183 182 26 25 21 22 23 24 33 34 35 28 27 I I I/O I/O I/O I/O I/O RESERVED CAM1 I2C_SCL RESERVED CAM1 I2C_SDA RESERVED CAM1 sleep signal RESERVED CAM1 master clock signal RESERVED CAM1 reset signal RESERVED CAM2 O O I I I I I I I I I/O I/O I/O I/O I/O RESERVED CAM2 MIPI CLOCK RESERVED CAM2 MIPI DATA RESERVED CAM2 master clock signal RESERVED CAM2 sleep signal RESERVED CAM2 reset signal RESERVED CAM1 I2C_SCL RESERVED CAM1 I2C_SDA Audio Port I I I I I I O O O I I Main MIC negative Main MIC positive Headphone MIC positive Headphone MIC negative Noise reduction MIC negative Noise reduction MIC positive The BIAS voltage of the main mic and the auxiliary mic, used for silicon microphone design BIAS voltage of headphone MIC BIAS voltage of mic4 for silicon wheat design MIC4 positive MIC4 negative Page 1 8 HSJ_HPH_R HSJ_HPH_L HSJ_HS_DET HSJ_HPH_REF WCD_EAR_OUT_P WCD_EAR_OUT_M WCD_AUX_P WCD_AUX_M I2S1_DATA1/DMIC2_DATA/GP IO153*

I2S1_DATA0/DMIC2_CLK/GPI O152 I2S1_CLK/DMIC1_CLK/GPIO15 0*

I2S1_WS/DMIC1_DATA/GPIO1 51*

I2S2_DATA0/DMIC3_CLK/GPI O156*

I2S2_DATA1/DMIC3_DATA/GP IO157*

SDCARD_DET_N/GPIO91*

SDC2_CLK SDC2_CMD SDC2_DATA_0 SDC2_DATA_1 SDC2_DATA_2 SDC2_DATA_3 SENSOR_I2C_SDA/GPIO161 SENSOR_I2C_SCL/GPIO162 NFC_I2C_SDA/GPIO36*

NFC_I2C_SCL/GPIO37 HDMI_I2C_SDA/GPIO8*

HDMI_I2C_SCL/GPIO9 TS_I2C_SDA/GPIO52*

TS_I2C_SCL/GPIO53 APPS_I2C_SDA/GPIO4*

16 15 13 14 17 18 19 20 56 55 53 54 287 288 498 379 380 381 382 383 384 47 48 524 525 515 514 409 410 252 O O I I O O O O I O O I O I Headphone right channel Headphone left channel Headphone plug-in detection Headphone reference ground earpiece output positive Headphone output negative External amplifier input positive External power amplifier input negative External amplifier input Digital MIC2 data signal Digital MIC2 clock signal Digital MIC1 clock signal Digital MIC1 data signal Digital MIC3 clock signal Digital MIC3 data signal SD INTERFACE I/O I/O I/O I/O I/O I/O I/O I2C I/O I/O I/O I/O I/O I/O I/O I/O SD card insertion and removal detection signal SD card clock signal SD card CMD signal SD card data signal SENSOR_I2C signal Pull high to VREG_L8C_1 P8 Pull high to General purpose I2C signals VREG_L18B_ 1P8 Pull high to General purpose I2C signals VREG_L18B_ TP_I2C signal 1P8 Pull high to VREG_L12C_ 1P8 I/O General purpose I2C signals Pull high to SNM955 Hardware Design Manual Page 1 9 APPS_I2C_SCL/GPIO5 CCI_I2C0_SCL/GPIO70 251 223 CCI_I2C0_SDA/GPIO69 222 CCI_I2C2_SCL/GPIO74 CCI_I2C2_SDA/GPIO73 CCI_I2C1_SCL/GPIO72*

CCI_I2C1_SDA/GPIO71 CCI_I2C3_SCL/GPIO76 CCI_I2C3_SDA/GPIO75*

MAG_I2C_SDA/GPIO163 MAG_I2C_SCL/GPIO164 TS_I2C_SDA/GPIO52*

TS_I2C_SCL/GPIO53 TS_INT_N/GPIO81*

TS_RST_N/GPIO105 USB0_HS_DP USB0_HS_DM USB1_HS_D_P USB1_HS_D_M USB0_SS_TX1_P USB0_SS_TX1_M USB0_SS_RX1_P USB0_SS_RX1_M USB0_SS_TX0_P USB0_SS_TX0_M USB0_SS_RX0_P 183 182 77 76 94 93 476 475 409 410 402 403 375 376 369 370 366 367 372 373 364 365 358 R-CAM I2C signal F-CAM I2C signal D-CAM I2C signal VREG_L18B_ 1P8 Pull high to CAM_IOVD D_1P8

(external LDO) Pull high to CAM_IOVD D_1P8 Pull high to CAM_IOVD D_1P8 Pull high to RESERVED CAM I2C signal CAM_IOVD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O D_1P8 Pull high to VREG_L8C_1 P8 Pull high to VREG_L12C_ 1P8 Only supports host mode MAG sensor I2C signal TP I/O I2C signal I/O I2C signal TP interrupt signal TP reset signal I/O I/O USB I/O I/O I/O I/O O O I I O O I USB 2.0 DP signal USB 2.0 DM signal USB 2.0 DP signal USB 2.0 DM signal USB super-speed 1 transmit plus USB super-speed 1 transmit minus USB super-speed 1 receive plus USB super-speed 1 receive minus USB super-speed 0 transmit plus USB super-speed 0 transmit minus USB super-speed 0 receive plus SNM955 Hardware Design Manual Page 2 0 USB0_SS_RX0_M 359 USB_CC1 USB_CC2 PM7250B_USB_SBU1 PM7250B_USB_SBU2 USB_CONN_THERM USB_ID/GPIO60*

DP_AUX_P DP_AUX_M USB_CC_DIR 5 6 3 4 442 377 361 362 426 USB_OPTION 425 I I/O I/O I O I I I/O I/O O I USB super-speed 0 receive minus CC1 pin for the Type-C CC2 pin for the Type-C Type-C side band signal SBU1; protected to 22 V max Type-C side band signal SBU2; protected to 22 V max USB Type-C connector temperature sensor. USB ID signal DP_AUX_P signal DP_AUX_M signal 1.8V tri-state output indicates CC connection direction Select different PON items according to the pull-down resistor value USB_PHY_PS 518 I/O USB_PHY_PS Type-C: This pin is connected to 518pin Micro-USB:

The pin NC Type-C: The pin NC Micro-USB:

This pin is grounded Type-C: This pin is connected to 426pin Micro-USB:

Connect this pin to the ground with a 1K resistor Antenna interface I/O NA I/O NA I/O NA I/O NA I/O NA I/O WIFI/BT Antenna I/O WIFI/BT Antenna I NA I NA 316 50 31 266 25 5 116 100 130 139 GPIO and default function (* to support interrupt wake-up port) ANT_0 ANT_ 1 ANT_2 ANT_ 3 ANT_4 WIFI_CH 1 WIFI_CH 0 GPS_L1_ANT GPS_L5_AN T GPIO0*

GPIO1 173 172 204 I/O I/O I/O General-purpose GPIO, no default function General-purpose GPIO, no default function General purpose GPIO, default is PCIE1_RESET_N Page 2 1 PCIE1_RESET_N/GPIO2 SNM955 Hardware Design Manual PCIE1_WAKE_N/GPIO3*

APPS_I2C_SDA/GPIO4*

APPS_I2C_SCL/GPIO5 EDP_CABC_EN/GPIO6 GPIO7*

HDMI_I2C_SDA/GPIO8*

HDMI_I2C_SCL/GPIO9 203 252 251 253 257 515 514 GPS_L1_ELNA_CTRL/GPIO10 128 GNSS_L5_ELNA_CTRL/GPIO1 1*

GPIO12*

GPIO13 GPIO14 GPIO15*

GPIO16*

GPIO17 UART1_TX/GPIO18*

UART1_RX/GPIO19*

CAM0_RST_N/GPIO20*

CAM1_RST_N/GPIO21*

DBG_UART_TX/GPIO22 DBG_UART_RX/GPIO23*

HOME_KEY/GPIO24*

VOL_DOWN/GPIO25*

UART2_TX/GPIO26 UART2_RX/GPIO27*

FP_INT/GPIO34*

FP_RST/GPIO35*

NFC_I2C_SDA/GPIO36*

NFC_I2C_SCL/GPIO37 NFC_EN/GPIO38 133 499 261 262 160 502 159 157 158 213 67 528 529 530 531 507 506 314 313 524 525 474 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Generic GPIO, default is PCIE1_WAKE_N General GPIO, default is APPS_I2C_SDA Generic GPIO, default is APPS_I2C_SCL General-purpose GPIO, no default function General-purpose GPIO, no default function Generic GPIO, default is HDMI_I2C_SDA Generic GPIO, default is HDMI_I2C_SCL General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General purpose GPIO, default is UART1_TX General purpose GPIO, default is UART1_RX General purpose GPIO, default is CAM0_RST_N General purpose GPIO, default is CAM1_RST_N Generic GPIO, default is DBG_UART_TX Generic GPIO, default is DBG_UART_RX Generic GPIO, default is HOME_KEY General-purpose GPIO, default is VOL_DOWN General purpose GPIO, default is UART2_TX General purpose GPIO, default is UART2_RX General-purpose GPIO, no default function General-purpose GPIO, no default function Generic GPIO, default is NFC_I2C_SDA Generic GPIO, default is NFC_I2C_SCL General-purpose GPIO, no default function SNM955 Hardware Design Manual Page 2 2 NFC_CLK_REQ/GPIO39*

NFC_DWL_REQ/GPIO40*

NFC_INT/GPIO41*

DCAM_PWD_N/GPIO42 SCAM_PWD_N/GPIO43*

LCD_RST_N/GPIO44*

GPIO45*

LCD_ID/GPIO46 GPIO47*

NFC_SPI_MISO/GPIO48*

NFC_SPI_MOSI/GPIO49 NFC_SPI_SCLK/GPIO50 NFC_SPI_CS/GPIO51*

TS_I2C_SDA/GPIO52*

TS_I2C_SCL/GPIO53 GPIO54*

AUDIO_PA_EN/GPIO55*

SPI1_MISO/GPIO56*

SPI1_MOSI/GPIO57 SPI1_SCK/GPIO58 SPI1_CS/GPIO59*

USB_ID/GPIO60*

FP_WAKE/GPIO61*

WSA0_EN/GPIO63*

CAM_MCLK0/GPIO64 CAM_MCLK1/GPIO65 CAM_MCLK2/GPIO66 CAM_MCLK3/GPIO67 CAM_MCLK4/GPIO68*

CCI_I2C0_SDA/GPIO69 321 323 473 75 96 393 318 394 324 320 319 312 311 409 410 309 310 522 523 521 520 377 322 114 214 74 190 97 151 222 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General purpose GPIO, default is DCAM_PWD_N Generic GPIO, default is SCAM_PWD_N General purpose GPIO, default is LCD_RST_N General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General purpose GPIO, default is TS_I2C_SDA General purpose GPIO, default is TS_I2C_SCL General-purpose GPIO, no default function General-purpose GPIO, default is external audio PA enable General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function Generic GPIO, default is USB_ID General-purpose GPIO, no default function General-purpose GPIO, no default function General purpose GPIO, default is CAM_MCLK0 General purpose GPIO, default is CAM_MCLK1 General purpose GPIO, default is CAM_MCLK2 Generic GPIO, default is CAM_MCLK3 General purpose GPIO, default is CAM_MCLK4 General purpose GPIO, default is CCI_I2C0_SDA SNM955 Hardware Design Manual Page 2 3 CCI_I2C0_SCL/GPIO70 CCI_I2C1_SDA/GPIO71 CCI_I2C1_SCL/GPIO72*

CCI_I2C2_SDA/GPIO73 CCI_I2C2_SCL/GPIO74 CCI_I2C3_SDA/GPIO75*

CCI_I2C3_SCL/GPIO76 CAM2_RST/GPIO77*

CAM3_RST/GPIO78*

223 76 77 182 183 93 94 191 95 PCIE1_CLK_REQ_N/GPIO79*

527 LCD_TE/GPIO80*

TS_INT_N/GPIO81*

SDCARD_DET_N/GPIO91*

CAM_MCLK5/GPIO93*

MI2S_MCLK/GPIO96 GYRO_INT/GPIO102*

ACCL_INT/GPIO103*

PRESSURE_INT/GPIO104*

TS_RST_N/GPIO105 MCAM_PWD_N/GPIO107 UIM2_PRESENT/GPIO112*

UIM1_PRESENT/GPIO116*

QCM_RFFE1_CLK_GRFC_2/G PIO119*

QCM_RFFE1_DATA_GRFC_3/

GPIO120 SAR_INT_N/GPIO141*

ALSP_INT_N/GPIO142*

I2S1_CLK/DMIC1_CLK/GPIO15 0*

I2S1_WS/DMIC1_DATA/GPIO1 51*

I2S1_DATA0/DMIC2_CLK/GPI O152 I2S1_DATA1/DMIC2_DATA/GP IO153*

SNM955 Hardware Design Manual 401 402 498 174 283 508 516 526 403 215 345 336 269 270 146 317 53 54 55 56 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O General purpose GPIO, default is CCI_I2C0_SCL General purpose GPIO, default is CCI_I2C1_SDA General purpose GPIO, default is CCI_I2C1_SCL Generic GPIO, default is CCI_I2C2_SDA General purpose GPIO, default is CCI_I2C2_SCL General purpose GPIO, default is CCI_I2C3_SDA General purpose GPIO, default is CCI_I2C3_SCL General purpose GPIO, default is CAM2_RST General purpose GPIO, default is CAM3_RST General purpose GPIO, default is PCIE1_CLK_REQ_N General purpose GPIO, default is LCD_TE General purpose GPIO, default is TS_INT_N Generic GPIO, default is SDCARD_DET_N General-purpose GPIO, no default function General-purpose GPIO, no default function General purpose GPIO, default is GYRO_INT General purpose GPIO, default is ACCL_INT Generic GPIO, default is PRESSURE_INT General purpose GPIO, default is TS_RST_N Generic GPIO, default is MCAM_PWD_N Dedicated GPIO, can only be used as UIM2_PRESENT Dedicated GPIO, can only be used as UIM1_PRESENT Dedicated GPIO, reserved for radio frequency Dedicated GPIO, reserved for radio frequency General-purpose GPIO, no default function General purpose GPIO, default is ALSP_INT_N General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function Page 2 4 I2S2_CLK/SWR_CLK/GPIO154 285 I2S2_WS/SWR_DATA/GPIO15 5*

I2S2_DATA0/DMIC3_CLK/GPI O156*

I2S2_DATA1/DMIC3_DATA/GP IO157*

SNS_I3C0_SDA/GPIO159 SNS_I3C0_SCL/GPIO160 SENSOR_I2C_SDA/GPIO161 SENSOR_I2C_SCL/GPIO162 MAG_I2C_SDA/GPIO163 MAG_I2C_SCL/GPIO164 286 287 288 490 489 47 48 476 475 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General-purpose GPIO, no default function General purpose GPIO, default is SENSOR_I2C_SDA General purpose GPIO, default is SENSOR_I2C_SCL General-purpose GPIO, no default function General-purpose GPIO, no default function Other Functional Feet FORCED_USB_BOOT 517 PM_MID_CHG 12910 VIB_DRV_P PM7250B_GPIO1/ADC1 PM7250B_GPIO5/ADC2 PM7250B_GPIO8/ADC3 PM7250B_GPIO11/ADC4 PM7250B_GPIO12/ADC5 PM7325_GPIO2/ADC6 PM7325_AMUX4 PM7325_AMUX2 SMB1355_INT/PM7250B_GPIO 6 DISPLAY_BIAS_DRIVER_EN/P M7250B_GPIO2 EDP_PWM/PM7350C_GPIO8 FLASH_LED1 FLASH_LED2 FLASH_LED3 FLASH_LED4 IRIS_RED SNM955 Hardware Design Manual 7 42 43 44 45 46 434 435 436 432 437 411 421 422 423 420 351 Boot up to 1.8V

(VREG_L18B_1P8) to enter emergency download mode Mid point of the charger. Charger buck input. Joint point for DC/charging. Motor output positive, support ERM PM7250B_GPIO, used as ADC by default PM7250B_GPIO, used as ADC by default PM7250B_GPIO, used as ADC by default PM7250B_GPIO, used as ADC by default PM7250B_GPIO, used as ADC by default PM7325_GPIO, used as ADC by default Analog multiplexer (AMUX) input Analog multiplexer (AMUX) input PM7250B_GPIO, used as SMB1355_INT by default PM7250B_GPIO, used as DISPLAY_BIAS_DRIVER_EN by default PM7350C_GPIO, can be used as PWM output Flash positive, 1.5A output Flash positive, 1.5A output Flash positive, 0.8A output Flash positive, 0.8A output RED_LED indicator positive I I O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O O O O O O Page 2 5 IRIS_GREE N IRIS_BLUE SMB_SPMI_CLK SMB_SPMI_DATA SMB_ICHG_FB SMB_EN_CHG SMB_THERM IUSB_OUT DC_IN_PSNS DC_IN_PON DC_IN_EN LN_BB_CLK2 KPD_PWR_N PM_RESIN_N KYPD_VOLP_N CBL_PWR_N WCD_RESET_N AOSS_SLEEP_INDICATOR 352 353 387 388 438 439 444 433 428 429 430 519 509 505 493 491 494 500 Inter-chip communicati on for parallel charging When using SMB1393, pull down the 40.2K resistor reserved port O O O GREEN _LED indicator positive BLUE_LED indicator positive SMB_SPMI_CLK I/O SMB_SPMI_CLK I O Current sense plus from the external parallel charger. Enable/disable control pin for parallel SMB (slave) charger. I Inductor temperature sensor. Buffered voltage signal proportional to USB input current. Output to the charge pump. Needed for regulating the input current limit with the charge pump DC charging power sense input DC charging power-on trigger DC barrel jack charging power source enable/disable pin. KeepsDC charger input disabled during USB charging. LN_BB_CLK219.2MHz clock , for NFC Power Key Hardware reset key Control volume+

Power-on automatic power-on control pin O I I O O I I I I I/O Internal audio chip reset signal I/O AOSS_SLEEP_INDICATOR NC processing CHARGER_SKIN_THERM 443 I Analog multiplexer (AMUX) input, used for charging related temperature detection by default BATT_ID 445 I Battery ID detection input SNM955 Hardware Design Manual To fake presence of battery and have charging enabled, use a 100 k pull-down to GND on BATT_ID. To fake presence of battery and have charging Page 26 disabled, use 2 k to 14 k pull-down to GND on BATT_ID. To fake a good battery temperature, connect a 100 k pull-

down to GND on BATT_THER M. Connect to battery negative ground Connect to battery negative Connect to battery positive Connect to battery positive Connect to battery positive BATT_THERM 446 VBATT_PACK_SNS_M 447 VBATT_CONN_VSENSE_M 450 VBATT_CONN_VSENSE_P 451 VBATT_CONN_ISNS_M VBATT_CONN_ISNS_P PCIE1_TX0_P PCIE1_TX0_M PCIE1_TX1_P PCIE1_TX1_M PCIE1_RX0_P PCIE1_RX0_M PCIE1_RX1_P PCIE1_RX1_M PCIE1_REFCLK_P PCIE1_REFCLK_M RESERVED 452 453 334 327 332 329 333 328 331 330 335 326 646592 102104106 126129131 135136141 143149150 166167177 199200208 210211233 234239240 241242247 248249258 259260263 264272273 I I I I I I O O O O I I I I O O Battery temperature detection input Battery voltage detection input negative pole Battery voltage detection input negative pole Battery voltage detection input positive Reserved Reserved PCIe TX0 PCIe TX1 PCIe RX0 PCIe RX1 PCIe REFCLK RESERVED pin SNM955 Hardware Design Manual Page 2 7 274278279 280281291 292297298 299303304 305340354 355356 GPIO*Indicates an interrupt pin that can wake up the system SNM955 Hardware Design Manual Page 2 8 3.3. Mechanical Dimensions Figure 3.1: TOP View & Side View Figure 3.2: BOTTOM View SNM955 Hardware Design Manual Page 2 9 3.4. Recommended Package Figure 3.3: Recommended Package SNM955 Hardware Design Manual Page 3 0 4. Interface Application 4.1. Power If it is a battery device, the voltage input range of the module VBAT is 3.5V to 4.35V. In the 5G frequency band, when the module transmits at the maximum power, the peak current can reach up to 4A instantaneously, resulting in a large voltage drop on VBAT. It is recommended to use a large capacitor for voltage regulation close to VBAT. It is recommended to use two 47uF ceramic capacitors. Parallel 33PF and 10PF capacitors can effectively remove high frequency interference. At the same time, in order to prevent ESD and surge damage to the chip, it is recommended to use a suitable TVS tube and a 5.1V/500mW Zener diode on the VBAT pin of the module. During PCB layout, capacitors and diodes should be placed as close as possible to the VBAT pin of the module. Users can directly power the module with a 3.8V lithium-ion battery. When using a battery, the impedance between the VBAT pin and the battery should be less than 150m. Figure 4.1: VBAT input reference circuit If it is a DC power supply device, the DC input voltage is 5V-12V, and the recommended circuit that can use DC-DC power supply is shown in the figure below:

SNM955 Hardware Design Manual Page 3 1 Figure 4.2: DC-DC power supply circuit 4.1.1. Power Pin VBAT pins (460, 461, 462, 463) are used for power input. In the user's design, please pay special attention to the design of the power supply part to ensure that even when the module current consumption reaches 4A, the drop of VBAT should not be lower than 3.5 V. If the voltage drops below 3.5V, the module may shut down. The PCB trace from the VBAT pin to the power supply should be wide enough to reduce voltage droop during transmission burst mode. Figure 4.3: Minimum voltage at which VBAT drops SNM955 Hardware Design Manual Page 3 2 4.2. Power On And Off Do not turn on the module when the temperature and voltage limits of the module are exceeded. In extreme cases such operations can lead to permanent damage to the module. 4.2.1. Power-on Of The Module The user can turn on the module by pulling down the KPD_PWR_N pin (509) for at least 5 seconds. This pin has been pulled up to 1.8V inside the module. The recommended circuit is as follows; or pull down the CBL_PWR_N pin (491), CBL_PWR_N can realize the function of automatic power-on after power-on by means of a 1K pull-down resistor to ground, and it is not necessary to release this signal after power-on. Figure 4.4: Using an external signal to drive the module to boot SNM955 Hardware Design Manual Page 3 3 Figure 4.5: Power on using the button circuit 4.2.2. Module Shutdown User can shutdown using KPD_PWR_N pin 4.2.2.1. PWRKEY Shutdown User can shut down by pulling the KPD_PWR_N signal low for at least 3 seconds. The shutdown circuit can refer to the design of the startup circuit. After the module detects the shutdown action, a prompt window will pop up on the screen to confirm whether to perform the shutdown action. Users can implement forced shutdown by pulling KPD_PWR_N low for at least 15 seconds. 4.2.3. Module Reset The SNM955 module supports the hardware reset function, and the user can quickly restart the module by pulling down the PM_RESIN_N pin (505) of the module. The recommended circuit is as follows

SNM955 Hardware Design Manual Page 3 4 Figure 4.6: Reset using key circuit Figure 4.7: Resetting the module using an external signal When the pin is at a high level, the typical voltage is 1.8V, so users with a level of 3V or 3.3V cannot directly use the GPIO of the MCU to drive this pin, and an isolation circuit needs to be added. The hardware parameters of PM_RESIN_N can refer to the following table:

Table 4.1: PM_RESIN_N hardware parameters Pin Describe Minimum PM_RESIN_N Input high level Input low level Valid time of pull low 1.17

500 SNM955 Hardware Design Manual Typical value

Maximu m

0.63

Unit V V ms Page 3 5 4.3. VCOIN Power When VBAT is disconnected, the user needs to save the real-time clock, so the VCOIN pin (471) cannot be left floating, and should be connected to a large capacitor or battery. When a large capacitor is connected, the recommended value is 100uF, which can keep the real-time clock for 20 seconds. When the RTC power supply uses an external large capacitor or battery to supply power to the RTC inside the module, the reference design circuit is as follows:

Figure 4.8: External Capacitor Powering the RTC Non-rechargeable battery powered:

Rechargeable battery powered:

Figure 4.9: Non-rechargeable battery powering the RTC Figure 4.10: Rechargeable battery powers RTC The VCOIN power supply is typically 3.0V. SNM955 Hardware Design Manual Page 36 4.4. Power Output The SNM955 has multiple power outputs. For SD card, SIM card, sensor, touch panel, external LDO, etc. In application, it is recommended to add parallel 33PF and 10PF capacitors to each power supply to effectively remove high-frequency interference. Table 4.2: Power supply description r Powe VREG_L2C_1P8(RESERVED) VREG_L3C_3P0(TPVDD) VREG_L4C_1P8_3P0(VSIM1) VREG_L5C_1P8_3P0(VSIM2) VREG_L6C_2P96(SDVIO) VREG_L7C_3P0(SENSOR_VDD) VREG_L8C_1P8(SENSOR_VDDI O) VREG_L9C_2P96(SD_VDD) VREG_L11C_2P8(WCN_VDD) VREG_L12C_1P8(OLED VDDIO) VREG_L13C_3P0(OLED VCI) VREG_L2B_3P072(USBHS_VIO) VREG_L11B_1P776(SDR_VDD) VREG_L18B_1P8 VREG_L19B_1P8(RF_VDDIO) VREG_SYS_1P8 VPH_PWR Default voltage

(V) 1.8 3.0 1.8/3.0 1.8/3.0 2.96 3.0 1.8 2.96 2.8 1.8 3.0 3.072 1.776 1.8 1.8 1.8 3.8 Drive current (mA) 150mA 150mA 150mA 150mA 150mA 300mA 300mA 600mA 300mA 150mA 150mA 150mA 300mA 300mA 300mA 50mA

>1A SNM955 Hardware Design Manual Page 3 7 4.5. Serial Port SNM955 provides 3 serial ports for communication, of which 2 groups of interfaces support four-wire serial ports

.The number of serial ports can also be expanded through the QUP interface. Table 4.3: UART pin descriptions Nam e GPIO16*

GPIO17 UART1_TX/GPIO18*

UART1_RX/GPIO19*

DBG_UART_TX/GPIO22 DBG_UART_RX/GPIO23*

HOME_KEY/GPIO24*

VOL_DOWN/GPIO25*

UART2_TX/GPIO26 UART2_RX/GPIO27*

Pin 502 159 157 158 528 529 530 531 507 506 Direction Features I O O I O I I O O I UART1_CTS UART1_RTS UART1_TX UART1_RX Debug UART data transmission Debug UART data reception UART2_CTS UART2_RTS UART2_TX UART2_RX You can refer to the connection method below:

Figure 4.11: Serial connection diagram When the level of the serial port used by the user does not match the module, in addition to adding a level conversion IC, the following figure can also be used to achieve level matching. Only the matching circuits on TX and RX are listed here. Other low-speed signals can refer to this two circuits. SNM955 Hardware Design Manual Page 3 8 Figure 4.12: TX Connection Diagram Figure 4.13: RX connection diagram Note: When using Figure 4.12 and 4.13 for level isolation, it is necessary to pay attention to using VREG_L18B_1P8 as the pull-up power supply. VREG_L12C_1P8 or VREG_L8C_1P8 will enter low power consumption mode during sleep, so it is not recommended to use it. Table 4.4: Serial hardware parameters Describe Minimum Maximum Unit Input low level Input high level Output low level Output high level

1.17

1.35 0.63

0.45

V V V V Note: 1. The serial port of the module is a CMOS interface and cannot be directly connected to RS232 signals. If needed, please use RS232 conversion chip. 2. If the 1.8V output of the module cannot meet the high level range of the user, please add a level conversion circuit. SNM955 Hardware Design Manual Page 3 9 4.6. MIPI Interface SNM955 supports MIPI interface for Camera and LCD. MIPI is a high-speed signal line. In the layout stage, please strictly follow the impedance and length requirements, control the equal length of the differential pair within the group and between the groups, and keep the total length as short as possible. 4.6.1. LCD Interfac e SNM955 module supports MIPI interface of 1 group of LCD display screen, and has the identification signal of compatible screen. The screen resolution can support up to FHD+. The signal interface is show n in the table below. When Layout, please strictly control the differential 85 ohm impedance and the equal length of the signal line within and between groups. The MIPI interface of the module is in the 1.2V power domain. When the user needs to be compatible with the LCD_ID pin of the module can be used. The LCD VCC power supply can use the screen design, VREG_L13C_3P0 or an external LDO power supply. The specific solution can be selected according to the current consumption Table 4.5: Screen Interface Definition Screen Interface MIPI_DSI0_CLK_N MIPI_DSI0_CLK_P MIPI_DSI0_LANE0_N MIPI_DSI0_LANE0_P MIPI_DSI0_LANE1_N MIPI_DSI0_LANE1_P MIPI_DSI0_LANE2_N MIPI_DSI0_LANE2_P MIPI_DSI0_LANE3_N MIPI_DSI0_LANE3_P LCD_RST_N/GPIO44*

LCD_TE/GPIO80*

LCD_ID/GPIO46 406 407 390 391 396 397 398 399 404 405 393 401 394 O O O O O O O O O O I/O I/O I/O MIPI_LCD clock line MIPI_LCD data line LCD reset pin LCD frame sync signal LCD_ID signal LCD_ID of the module, this pin is GPIO inside. When used as LCD_ID, please confirm the internal circuit of the LCD. If the resistor divider method is used inside the LCD, please pay attention to the voltage to meet the high level or low level range of GPIO. MIPI is a high-speed signal line. To avoid EMI interference, it is recommended to place a common mode inductor on the side close to the LCD. SNM955 Hardware Design Manual Page 4 0 Figure 4.14: Schematic diagram of LCD interface circuit SNM955 can control the external backlight chip to adjust the backlight brightness through the BL_PWM/PM7350C_GPIO9 signal of the module, and the modulation method is PWM mode. Figure 4.15: Schematic diagram of backlight driving Note: 1. The backlight circuit should choose the chip according to the backlight circuit of the LCD. The user should read the LCD documentation carefully and choose the correct driver chip. The reference circuit provided in this document is a series-type PWM dimming backlight drive circuit; if it is a series-type one-line dimming backlight drive circuit, it needs to be controlled by GPIO. SNM955 Hardware Design Manual Page 4 1 4.6.2. MIPI Camera Interface The SNM955 module supports 5 groups of MIPI interface Camera, each group supports 4 lane data lines, and each lane supports a maximum rate of 2.5Gbps. It can be used for the design of main camera, secondary camera, depth of field camera, etc.; it can also be used for the design of MIPI interface scanning head. The module does not provide the power required by the Camera, including AVDD-2.8V, AFVDD-2.8V (focus motor power supply) and DVDD-1.2V (CAM core voltage), all of which require external LDO generation. n Table 4.6: MIPI Camera Interface Definitio REAR CAM MIPI_CSI0_CLK_P MIPI_CSI0_CLK_N MIPI_CSI0_LANE0_P MIPI_CSI0_LANE0_N MIPI_CSI0_LANE1_P MIPI_CSI0_LANE1_N MIPI_CSI0_LANE2_P MIPI_CSI0_LANE2_N MIPI_CSI0_LANE3_P MIPI_CSI0_LANE3_N CCI_I2C0_SCL/GPIO70 CCI_I2C0_SDA/GPIO69 MCAM_PWD_N/GPIO107 CAM_MCLK0/GPIO64 CAM0_RST_N/GPIO20*

MIPI_CSI3_CLK_P MIPI_CSI3_CLK_N MIPI_CSI3_LANE0_P MIPI_CSI3_LANE0_N MIPI_CSI3_LANE1_P MIPI_CSI3_LANE1_N MIPI_CSI3_LANE2_P MIPI_CSI3_LANE2_N MIPI_CSI3_LANE3_P MIPI_CSI3_LANE3_N CCI_I2C3_SCL/GPIO76 CCI_I2C3_SDA/GPIO75*

SCAM_PWD_N/GPIO43*

232 231 228 227 226 225 220 219 218 217 223 222 215 214 213 86 85 87 84 88 83 89 82 90 81 94 93 96 O O I I I I I I I I I/O I/O I/O I/O I/O REAR CAM MIPI clock REAR CAM MIPI data REAR CAM I2C_SCL REAR CAM I2C_SDA REAR CAM sleep signal REAR CAM master clock REAR CAM reset signal FRONT CAM FRONT CAM MIPI CLOCK FRONT CAM MIPI data O O I I I I I I I I I/O I/O I/O FRONT CAM/RESERVED CAM I2C_SCL FRONT CAM/RESERVED CAM I2C_SDA FRONT CAM sleep signal SNM955 Hardware Design Manual Page 4 2 CAM_MCLK3/GPIO67 CAM3_RST_N/GPIO78*

MIPI_CSI1_CLK_P MIPI_CSI1_CLK_N MIPI_CSI1_LANE0_P MIPI_CSI1_LANE0_N MIPI_CSI1_LANE1_P MIPI_CSI1_LANE1_N MIPI_CSI1_LANE2_P MIPI_CSI1_LANE2_N MIPI_CSI1_LANE3_P MIPI_CSI1_LANE3_N CCI_I2C1_SCL/GPIO72*

CCI_I2C1_SDA/GPIO71 DCAM_PWD_N/GPIO42 CAM_MCLK1/GPIO65 CAM1_RST_N/GPIO21*

MIPI_CSI2_CLK_P MIPI_CSI2_CLK_N MIPI_CSI2_LANE0_P MIPI_CSI2_LANE0_N MIPI_CSI2_LANE1_P MIPI_CSI2_LANE1_N MIPI_CSI2_LANE2_P MIPI_CSI2_LANE2_N MIPI_CSI2_LANE3_P MIPI_CSI2_LANE3_N CCI_I2C2_SCL/GPIO74 CCI_I2C2_SDA/GPIO73 FP_RST/GPIO35*

CAM_MCLK2/GPIO66 CAM2_RST_N/GPIO77*

MIPI_CSI4_CLK_P MIPI_CSI4_CLK_N SNM955 Hardware Design Manual 97 95 80 79 72 71 70 69 62 61 60 59 77 76 75 74 67 180 179 186 185 188 187 194 193 196 195 183 182 313 190 191 169 170 I/O I/O FRONT CAM master clock FRONT CAM reset signal DEPTH CAM O O I I I I I I I I I/O I/O I/O I/O I/O DEPTH CAM MIPI clock DEPTH CAM MIPI data DEPTH CAM I2C_SCL DEPTH CAM I2C_SDA DEPTH CAM sleep signal DEPTH CAM master clock DEPTH CAM reset signal RESERVED CAM1 O O I I I I I I I I I/O I/O I/O I/O I/O RESERVED CAM1 MIPI clock RESERVED CAM1 MIPI data RESERVED CAM1 I2C_SCL RESERVED CAM1 I2C_SDA RESERVED CAM1 sleep signal RESERVED CAM1 master clock signal RESERVED CAM1 reset signal RESERVED CAM2 O O RESERVED CAM2 MIPI Clock Page 4 3 MIPI_CSI4_LANE0_P MIPI_CSI4_LANE0_N MIPI_CSI4_LANE1_P MIPI_CSI4_LANE1_N MIPI_CSI4_LANE2_P MIPI_CSI4_LANE2_N MIPI_CSI4_LANE3_P MIPI_CSI4_LANE3_N CAM_MCLK4/GPIO68*

GPIO1 MI2S_MCLK/GPIO96 CCI_I2C2_SCL/GPIO74 CCI_I2C2_SDA/GPIO73 163 164 161 162 155 156 153 154 151 172 283 183 182 I I I I I I I I I/O I/O I/O I/O I/O RESERVED CAM2 MIPI data RESERVED CAM2 master clock signal RESERVED CAM2 sleep signal RESERVED CAM2 reset signal RESERVED CAM1 I2C_SCL RESERVED CAM1 I2C_SDA If the user designs to use the CAMERA module with auto focus function, please note that the I2C of the module cannot be directly connected to the AF device. The I2C of the AF device should be connected to the CAMERA driver chip. The correct connection is as shown below:

Figure 4.16: Schematic diagram of correct CAMERA connection The MIPI interface rate is relatively high. Users should control the 85 ohm differential impedance during the routing stage. At the same time, please pay attention to the requirements of the routing length. It is not recommended to add small capacitors on the MIPI signal line, which may affect the rising edge time of MIPI data. , resulting in invalid MIPI data. SNM955 Hardware Design Manual Page 4 4 Figure 4.17: MIPI Camera reference circuit Important note: When designing the camera function, you need to pay attention to the placement of the connector. There will be a little man indicating the imaging direction in the camera specification. Make sure that the little man is standing on the long side of the LCD, otherwise the camera image will be flipped At 90, the software cannot adjust. As shown in the two figures below. Figure 4.18: Schematic diagram of camera imaging SNM955 Hardware Design Manual Page 4 5 4.7. Resistive Touch Interface The module does not provide a resistive touch screen interface. If the user needs to use resistive touch, a dedicated chip needs to be added externally. The module can provide an I2C interface. SNM955 Hardware Design Manual Page 4 6 4.8. Capacitive Touch Interface The module provides a set of I2C interfaces that can be used to connect the capacitive touch screen. The default interface pins of the capacitive touch screen are defined in the following table. Table 4.7: Capacitive Touch Interface Definition Name TS_I2C_SDA/GPIO52*

TS_I2C_SCL/GPIO53 TS_INT_N/GPIO81*

TS_RST_N/GPIO105 VREG_L12C_1P8(OLED VDDIO) VREG_L3C_3P0(TPVDD) Pin 409 410 402 403 418 501 Input/Output Description I/O I/O I/O I/O PO PO I2C signal I2C signal TP interrupt signal TP reset signal VDDIO_1.8V power supply VDD_3.0V power supply Note: The interface definition of capacitive touch can be adjusted by software, and users can change GPIO and I2C according to design needs. SNM955 Hardware Design Manual Page 4 7 4.9. Audio Interface The module provides 4 channels of analog audio input, MIC1_IN_P/M is used to connect the main microphone;

HPHMIC_IN2_P/M can be used to connect the headphone microphone, MIC3_IN_P/M is used to connect the noise reduction microphone, and MIC4_IN_P/M is reserved. The module also provides three analog audio outputs

(HSJ_HPH_L/R, WCD_EAR_OUT_P/M, WCD_AUX_P/M). The audio pins are defined in the following table:

Table 4.8: Audio pin definition MIC1_IN_M MIC1_IN_P HPHMIC_IN2_P HPHMIC_IN2_M MIC3_IN_M MIC3_IN_P MIC_BIAS1 MIC_BIAS2 MIC_BIAS3 MIC4_IN_P MIC4_IN_M HSJ_HPH_R HSJ_HPH_L HSJ_HS_DET HSJ_HPH_REF WCD_EAR_OUT_P WCD_EAR_OUT_M WCD_AUX_P WCD_AUX_M I2S1_DATA1/DMIC2_DATA/GP IO153*

I2S1_DATA0/DMIC2_CLK/GPI O152 I2S1_CLK/DMIC1_CLK/GPIO15 0*

I2S1_WS/DMIC1_DATA/GPIO1 51*

I2S2_DATA0/DMIC3_CLK/GPI O156*

I2S2_DATA1/DMIC3_DATA/GP IO157*

26 25 21 22 23 24 33 34 35 28 27 16 15 13 14 17 18 19 20 56 55 53 54 287 288 I I I I I I O O O I I O O I I O O O O I O O I O I Main MIC negative Main MIC positive Headphone MIC positive Headphone MIC negative Noise reduction MIC negative Noise reduction MIC positive The BIAS voltage of the main mic and the auxiliary mic, used for silicon microphone design BIAS voltage of headphone MIC BIAS voltage of mic4 for silicon wheat design MIC4 positive MIC4 negative Headphone right channel Headphone left channel Headphone plug-in detection Headphone Audio Reference Ground earpiece output positive Headphone output negative External amplifier input positive External power amplifier input negative Digital MIC2 data signal Digital MIC2 clock signal Digital MIC1 clock signal Digital MIC1 data signal Digital MIC3 clock signal Digital MIC3 data signal External amplifier input It is recommended that the user choose the following circuit according to the actual application to get better sound SNM955 Hardware Design Manual Page 4 8 effect. 4.9.1. Receiver Interface Circuit The receiver interface circuit places the following devices near the REC end, B302 and B303 can be changed to magnetic beads according to the actual effect. Figure 4.19: Receiver Interface Circuit 4.9.2. Microphone Receiver Circuit The figure below shows the interface circuit of electret microphone and MEMS microphone Please refer to the circuit design in strict accordance with the following figure according to the different selection of the user's microphone. SNM955 Hardware Design Manual Page 4 9 Figure 4.20: Electret microphone, analog silicon microphone interface circuit 4.9.3. Headphone Interface Circuit The module integrates a stereo headphone jack. It is recommended that users reserve ESD devices in the design stage to prevent ESD damage. The HSJ_HS_DET pin of the module can be set as an interrupt. The software defaults to this pin as an earphone interrupt. Users can use this pin to detect the plugging and unplugging of the earphone. SNM955 Hardware Design Manual Page 5 0 Figure 4.21: Headphone Interface Circuit Notice:

1. The headset seat in Figure 4.24 is a normal -closed method. If the user uses a commonly opened method, please modify the detection circuit according to the actual pin and modify the software accordingly. 2. We recommend the headset detection foot HSJ_HS_DET and HSJ_HPH_L to form a detection circuit (the connection method in the figure above), because the HSJ_HPH_L inside the chip has a drop -down resistance, which can ensure that the HSJ_HS_DETT and HSJ_HPH_L are low. Connect, please reserve the position of a 1K drop -down resistance on the HSJ_HPH_R. 3 The standard of the headset interface is the European standard OMPT. If you need to design the US -standard CTIA interface, you need to change the GND and MIC signals on the network. If you want to be compatible with two headphones, you need to connect special chips, such as Ti-TS3A226AE. 4.9.4. Circuit Of The Speaker Interface There is no internal audio amplifier inside the module. The audio amplifier needs to be added to the outside. WCD_AUX_P, WCD_AUX_M is used as a differential input signal. The reference circuit is shown in the figure below. Figure 4.22: Recommended circuit with external audio amplifiers 4.9.5. I2S Interface There are two groups of I2S interfaces compatible with GPIO in the module. The pins used for this function are as follows:

Table 4.9: I2S interface PIN foot definition Name Pin Input/Output I2S1_CLK/DMIC1_CLK/GPIO150*

I2S1_WS/DMIC1_DATA/GPIO151*

I2S1_DATA0/DMIC2_CLK/GPIO152 I2S1_DATA1/DMIC2_DATA/GPIO15 3*

I2S2_CLK/SWR_CLK/GPIO154 I2S2_WS/SWR_DATA/GPIO155*

53 54 55 56 285 286 I2S2_DATA0/DMIC3_CLK/GPIO156*

287 O O I/O I/O O O I/O Description I2S1_ SLK I2S1_ WS I2S1 DATA0 I2S1_ DATA1 I2S2_ SLK I2S2_WS I2S2_ DATA0 SNM955 Hardware Design Manual Page 5 1 I2S2_DATA1/DMIC3_DATA/GPIO15

7 288 4.10. USB Interface I/O I2S2_ DATA1 SNM955 supports 2 USB 2.0 interface, 1 USB 3.1 interface. When layout, you must control the 90 ohm differential impedance, follow the differential long line according to the differential pair, and control the length of the external wiring. n Table 4.10: definition of USB interface switching pi USB0_HS_DP USB0_HS_DM USB1_HS_D_P USB1_HS_D_M USB0_SS_TX1_P USB0_SS_TX1_M USB0_SS_RX1_P USB0_SS_RX1_M USB0_SS_TX0_P USB0_SS_TX0_M USB0_SS_RX0_P USB0_SS_RX0_M USB_CC1 USB_CC2 PM7250B_USB_SBU1 PM7250B_USB_SBU2 USB_CONN_THERM USB_ID/GPIO60*

DP_AUX_P DP_AUX_M USB_CC_DIR USB_OPTION USB_PHY_PS 375 376 369 370 366 367 372 373 364 365 358 359 5 6 3 4 442 377 361 362 426 425 518 SNM955 Hardware Design Manual I/O I/O I/O I/O USB 2.0 DP signal USB 2.0 DM signal USB 2.0 DP signal USB 2.0 DM signal O O I I O O I I I/O I/O I O I I I/O I/O O I USB super-speed 1 transmit plus USB super-speed 1 transmit minus USB super-speed 1 receive plus USB super-speed 1 receive minus USB super-speed 0 transmit plus USB super-speed 0 transmit minus USB super-speed 0 receive plus USB super-speed 0 receive minus CC1 pin for the Type-C CC2 pin for the Type-C Type-C side band signal SBU1; protected to 22 V max Type-C side band signal SBU2; protected to 22 V max USB Type-C connector temperature sensor. USB ID signal DP_AUX_P signal DP_AUX_M signal 1.8V tri-state output indicates CC connection direction Select different PON items according to the pull-down resistor value I/O USB_PHY_PS Only support Host mode Type-C: This pin is connected to 518pin Micro-USB: The pin NC Type-C: The pin NC Micro-USB: This pin is grounded Type-C: This pin is connected to 426pin Micro-USB:

Page 52 Connect this pin to the ground with a 1K resistor The module also supports OTG function. The USB insertion detection of the module is realized by VBUS and DP/DM data line. When the USB line is inserted, the VBUS voltage is detected first, and then the up-down state of the DM/DP is detected to determine whether the USB data line or the charger is inserted. Therefore, if the user needs to use the USB function, please be sure to connect VBUS to the 5V power supply on the data line. USB is in high-speed mode. It is recommended to connect a common mode inductor in series near the USB connector, which can effectively suppress EMI interference. At the same time, the USB interface is an external interface, and the DM/DP must add a TVS tube to prevent electrostatic damage caused by plugging and unplugging the data cable. When selecting TVS, users should pay attention to the load capacitance should be less than 1pf. VBUS also needs to increase the TVS tube, if there is a need for anti-surge, but also add a surge-proof tube. The connection diagram is as follows:

Figure 4.23: USB Connection Diagram 4.10.2. DP Screen Interface The USB3.0 interface and the DP screen interface share the relevant PIN pins, and the multiplexing combination relationship is as follows:

SNM955 Hardware Design Manual Page 5 3 Figure 4.24: The multiplexing relationship between the USB3.1 interface and the DP screen interface SNM955 Hardware Design Manual Page 5 4 4.11. UIM Card Interface SNM955 can support two SIM card interfaces at the same time to realize dual card dual standby. Support SIM card hot swap, can automatically identify 1.8V and 3.0V cards. The following figure is the SIM recommended interface circuit. In order to protect the SIM card, it is recommended to use a TVS device for electrostatic protection. Devices of the peripheral circuit of the SIM card should be close to the SIM card holder.

The reference circuit is as follows Figure 4.25: UIM card interface circuit SNM955 Hardware Design Manual Page 5 5 4.12. SD Card Interface SNM955 supports SD card interface, up to 128GB The reference circuit is as follows:

Figure 4.26: SD Card Interface Circuit SNM955 Hardware Design Manual Page 5 6 4.13. I2C Bus Interface The SNM955 module supports 10-channel hardware I2C bus interface and 5-channel camera dedicated CCI interface. The pin definitions and default functions are as follows:

Table 4.11: I2C interface pin description SENSOR_I2C_SDA/GPIO16 1 SENSOR_I2C_SCL/GPIO162 NFC_I2C_SDA/GPIO36*

NFC_I2C_SCL/GPIO37 HDMI_I2C_SDA/GPIO8*

HDMI_I2C_SCL/GPIO9 TS_I2C_SDA/GPIO52*

TS_I2C_SCL/GPIO53 APPS_I2C_SDA/GPIO4*

APPS_I2C_SCL/GPIO5 CCI_I2C0_SCL/GPIO70 CCI_I2C0_SDA/GPIO69 CCI_I2C2_SCL/GPIO74 CCI_I2C2_SDA/GPIO73 CCI_I2C1_SCL/GPIO72*

CCI_I2C1_SDA/GPIO71 CCI_I2C3_SCL/GPIO76 CCI_I2C3_SDA/GPIO75*

MAG_I2C_SDA/GPIO163 MAG_I2C_SCL/GPIO164 47 48 524 525 515 514 409 410 252 251 223 222 183 182 77 76 94 93 476 475 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SENSOR_I2C signal General purpose I2C signals General purpose I2C signals TP_I2C signal General purpose I2C signals Pull high to VREG_L8C_1P8 Pull high to VREG_L18B_1P8 Pull high to VREG_L18B_1P8 Pull high to VREG_L12C_1P8 Pull high to VREG_L18B_1P8 Pull high to R-CAM I2C signal CAM_IOVDD_1P8 F-CAM I2C signal D-CAM I2C signal RESERVED CAM I2C signal MAG sensor I2C signal

(external LDO) Pull high to CAM_IOVDD_1P8 Pull high to CAM_IOVDD_1P8 Pull high to CAM_IOVDD_1P8 Pull high to VREG_L8C_1P8 Note: When using as an I2C bus interface, connect a 2.2K pull-up resistor to 1.8V. SNM955 Hardware Design Manual Page 5 7 4.14. Analog To Digital ConverterADC The SNM955 module provides multiple ADCs by the internal power management chip, supports 1.8V input, and has an accuracy of 15bit. See table below. e Table 4.12: The pin description of ADC interfac Pin Name PIN number PM7250B_GPIO1/ADC1 PM7250B_GPIO5/ADC2 PM7250B_GPIO8/ADC3 PM7250B_GPIO11/ADC4 PM7250B_GPIO12/ADC5 PM7325_GPIO2/ADC6 PM7325_AMUX4 PM7325_AMUX2 42 43 44 45 46 434 435 436 I/O I/O I/O I/O I/O I/O I/O I I Description Remark PM7250B_GPIO, used as ADC by default PM7250B_GPIO, used as ADC by default PM7250B_GPIO, used as ADC by default PM7250B_GPIO, used as ADC by default PM7250B_GPIO, used as ADC by default PM7325_GPIO, used as ADC by default Analog multiplexer (AMUX) input Analog multiplexer (AMUX) input SNM955 Hardware Design Manual Page 5 8 4.15. PWM BL_PWM/PM7350C_GPIO9 (412PIN), EDP_PWM/PM7350C_GPIO8 (411PIN) can be used for LCD backlight adjustment, and the backlight brightness can be adjusted by adjusting the duty cycle. SNM955 Hardware Design Manual Page 5 9 4.16. Antenna Interface The module provides 8 antenna interfaces such as ANT_0, ANT_1, ANT_2, ANT_3, ANT_4, WIFI_ANT0, WIFI_ANT1, GNSS_ANT, etc. In order to ensure that the user's product has good wireless performance, the antenna selected by the user should meet the requirements of an input impedance of 50 ohms and a standing wave coefficient of less than 2 in the working frequency band. 4.16.1 WAN ANT(ANT_0/1 ) The module provides ANT_0/1 antenna interface, the antenna on the user's motherboard should be connected to the antenna pin of the module using a microstrip line or stripline with a characteristic impedance of 50 ohms. In order to facilitate antenna debugging and certification testing, an RF connector and antenna matching network should be added. The recommended circuit diagram is as follows:

Figure 4.27: ANT_0/1/2/3 antenna interface connection circuit In the figure, R101, C101, and C102 are antenna matching devices, and the specific component values can be determined after the antenna factory has debugged the antenna. Among them, R101 defaults to 0R, and C101 and C102 default to not. If there are fewer components that can be placed between the antenna and the module output, or when the RF test head is not required in the design, the antenna matching circuit can be simplified as shown in the following figure:

Figure 4.28: ANT_0/1/2/3 antenna interface simplified connection circuit SNM955 Hardware Design Manual Page 6 0 Figure 4.30: WiFI_BT antenna interface connection circuit In the figure, R301, C301, and C302 are antenna matching devices, and the specific component values can be determined after the antenna factory has debugged the antenna. Among them, R301 defaults to 0R, C301 and C302 do not default. If there are fewer components that can be placed between the antenna and the module output, or when the RF test head is not required in the design, the antenna matching circuit can be simplified as shown in the following figure:

Figure 4.31: WIFI_BT antenna interface simplified connection circuit In the above picture, R301 is pasted 0R by default, and C301 and C302 are not pasted by default. SNM955 Hardware Design Manual Page 6 2 5. PCB Layout The quality of a product's performance largely depends on the PCB traces. As mentioned earlier, if the PCB layout is unreasonable, it may cause interference problems such as card dropping. The way to solve these interferences is often to redesign the PCB. If a good PCB layout can be planned in the early stage, so that the PCB routing is smooth, it can save a lot of time. , Of course, it can also save a lot of costs. This chapter mainly introduces some matters that users should pay attention to in the PCB layout stage to minimize interference problems and shorten the user's research and development cycle. The SNM955 module is an intelligent module with its own Android operating system. It includes sensitive e data lines such as high-speed USB and MIPI. It also has strict requirements on the length and impedance of th signal lines. If the high-speed signal processing is not good, it will cause serious EMI. If the problem is more serious, it will also affect the identification of USB and the display of LCD. Therefore, when using the SNM955 module, the PCB design requirements are much higher than that of the previous 4G module. Please read this

. chapter carefully to reduce the subsequent hardware debugging cycle When using the SNM955 module, users are required to use at least a 6-layer first-order design on the PCB, which is convenient for impedance control and signal line shielding. 5.1. Module PIN Distributio n Before PCB layout, you must first understand the pin distribution of the module, and rationally arrange the related devices and interfaces according to the distribution defined by the pins. Please refer to Figure 3.1 to determine the distribution of the module's functional pins. SNM955 Hardware Design Manual Page 6 3 5.2. PCB Layout Guideline s There are several aspects to pay attention to in the PCB layout stage:

5.2.1. Antenna Antenna part design, SNM955 module has a total of 2 antenna interfaces, they are WIFI_ANT0, WIFI_ANT1 Attention should be paid to the components and RF wiring:

placement o f The RF test head is used to test the conducted RF performance and should be placed as close a s possible to the antenna pins of the module;

The antenna matching circuit needs to be placed close to the antenna end;

The connection between the antenna pin of the module and the antenna matching circuit must be controlled by 50 ohm impedance;

The components and connections between the antenna pins of the module and the antenna connector must be kept away from high-speed signal lines and strong interference sources, and avoid crossing or parallel with any signal lines on adjacent layers. The length of the RF line between the antenna pin of the module and the antenna connector should be as short as possible, and it should absolutely avoid the situation of crossing the entire PCB board. If the antenna is connected by a coaxial radio frequency line, care should be taken to avoid making the coaxial radio frequency line straddle the SIM card, power supply circuit, and high-speed digital circuit to minimize mutual influence. 5.2.2. Power The power trace should not only consider VBAT, but also the return GND of the power supply. The trace of the positive pole of VBAT must be short and thick, and the trace must first pass through a large capacitor, a Zener diode, and then to the power PIN of the module. There are multiple PAD exposed coppers at the bottom of the module. It is necessary to ensure that the GND path from these exposed copper areas to the power supply is the shortest and most unobstructed. In this way, the current path of the entire power supply can be guaranteed to be the shortest and the interference can be minimized. 5.2.3. SIM Card The SIM card has a large area and has no anti-EMI interference devices, so it is more susceptible to interference. Therefore, when laying out, first ensure that the SIM card is far away from the antenna and the antenna extension cable inside the product, and is placed as close to the module as possible. When routing the PCB, pay attention to To protect the SIM_CLK signal, the SIM_DATA, SIM_RST and SIM_VDD signals of the SIM card should be kept away from the power supply and high-speed signal lines. If it is not handled properly, it will easily cause the card not to recognize or drop the card, so please follow the following principles when designing:

The SIM card wiring should be kept as far away as possible from RF lines, VBAT and high-speed signal

lines, and the SIM card wiring should not be too long The GND of the SIM card holder should maintain good connectivity with the GND of the module, so that SNM955 Hardware Design Manual Page 63 the two GNDs are equipotential;

To prevent SIM_CLK from interfering with other signals, it is recommended to protect SIM_CLK;

It is recommended to place a 100nF capacitor on the SIM_VDD signal line close to the SIM card holder;

Place a TVS near the SIM card holder, the parasitic capacitance of the TVS should not be greater than 50pF

, and a 51 resistor in series with the module can enhance ESD protection;

The SIM card signal line can reserve 22pf capacitance to ground to prevent radio frequency interference. The return path of VBAT has a large current passing through, so the SIM card wiring should avoid the return path of VBAT as much as possible. 5.2.4. T Card The CLK signal (SDC2_CLK) of the T card should be grounded separately, and the ground wire of the grounding path should be appropriately increased with ground holes; the rest of the data lines should be combined to three-dimensionally cover the ground; the total load capacitance of each signal line is less than 5pF (including the TVS capacitance value and filter capacitor). 5.2.5. MIPI MIPI is a high-speed signal line. The user must pay attention to protection during the layout stage to keep it away from the signal line that is easily disturbed. It must be processed with GND on the top, bottom, left, and right. To ensure the consistency of impedance, try not to bridge different GND planes. When choosing an ESD device for the MIPI interface, please choose a TVS with a small capacitance value. It is recommended that the parasitic capacitance be less than 1pF. MIPI routing requirements are as follows:

The total length of the wiring should not exceed 130mm It is required to control 85 ohm differential impedance with an error of 10%. The length error of the differential line within the group is controlled within 0.7mm. The length error between groups is controlled within 1.4mm. 5.2.6. USB The module supports high-speed USB interface with a rate of 480Mbps. Users are recommended to add a common mode inductor in the schematic design stage, which can effectively suppress EMI interference. If users need to increase electrostatic protection, please choose a TVS tube with parasitic capacitance less than 1pF. Please refer to the following precautions when Layout:

The common mode inductor should be close to the side of the USB connector. It is required to control 90 ohm differential impedance with an error of 10%. The length error of USB2.0 differential line is controlled within 2mm, and the length error of USB3.1 differential line is controlled within 0.7mm. If the Type-C over DP function is available, the length error between different differential line pairs of USB3.1 is required to be controlled within 10mm, and the length error of the DP_AUX differential line is controlled within 7mm. If the USB has a charging function, please pay attention to the VBUS trace as wide as possible. If there are test points, try to avoid bifurcation of the traces, and place the test points on the path of the SNM955 Hardware Design Manual Page 64 6. y Electrical, Reliabilit 6.1. Absolute Maximum The table below shows the absolute maximum values that the module can withstand, exceeding these limits may result in permanent damage to the module. Table 6.1: Absolute Maximum Values Parameter Minimum Typical Value Maximum Unit VBAT VBUS Peak Current

--0.3

--0.3

6 28 4 V V A SNM955 Hardware Design Manual Page 65 6.2. Operating Temperatur e The following table shows the operating temperature range of the module:

Table 6.2: Module operating temperature Parameter Minimum Typical Value Maximum Operating Temperature Storage Temperature

-25

-40

75 90 Unit SNM955 Hardware Design Manual Page 66 6.3. Operating Voltag e Table 6.3: Module operating voltage Parameter Minimum Typical Value Maximum Unit VBAT VBUS 3.5 3.7 3.8 5 4.35 12.6 V V SNM955 Hardware Design Manual Page 67 6.4. Digital Interface Feature s Table 6.4: Digital Interface Characteristics (1.8V) Parameter Description Minimum Typical Value Maximum Unit VIH VIL VOH VOL Input high level voltage Input low level voltage Output high level voltage Output low level voltage 1.17

-0.3 1.35 0 1.8 0

2.1 0.63 1.8 0.45 V V V V SNM955 Hardware Design Manual Page 68 6.5. Characteristics Of SIM_VD D Table 6.5: SIM_VDD characteristics Parameter Description Minimum VO IO The output voltage The output current 1.65

Typical Value 1.8 2.95

Maximum Unit 1.95

150 V mA SNM955 Hardware Design Manual Page 69 6.6. Features Of PWRKE Y Table 6.6: Features of PWRKEY Parameter Description Minimum PWRKEY High level Low level 1.4

Effective time 2000 Typical Value

Maximum Unit

0.6 V V ms SNM955 Hardware Design Manual Page 70 6.7. Features Of VCOI N Table 6.7: VCOIN Characteristics Parameter Description Minimum VCOIN-IN VCOIN-OUT VCOIN input voltage VCOIN output voltage 2.1

Typical Value 3.0 3.0 Maximum Unit 3.25

V V SNM955 Hardware Design Manual Page 71 6.9. Static Protectio n The modules are not specifically protected against electrostatic discharge. Therefore, users must pay attention to electrostatic protection when producing, assembling and operating the module. SNM955 Hardware Design Manual Page 72 6.13. The Main RF Performance Of WIF I The following table lists the main RF performance under WIFI conduction. Table 6.13: Main RF performance parameters under WIFI conduction 2.4G transmission performance 802.11B 802.11G 802.11N 802.11AX Transmit power (minimum rate) Transmit Power (Max Rate) EVM (maximum rate) 2.4G reception performance Receive sensitivity 802.11B 802.11G 802.11N 802.11AX Minimum speed Maximum speed 5G launch performance 802.11A 802.11N 802.11AC 802.11AX Transmit power (minimum rate) Transmit Power (Max Rate) 15 14 12 11 EVM (Maximum rate) 5G reception performance Receive sensitivity 802.11A 802.11N 802.11AC 802.11AX Minimum speed Maximum speed Transmit power (minimum rate) Transmit Power (Max Rate) EVM (Maximum rate) 6G launch performance 802.11A 802.11AX dBm dBm dB dBm dBm dBm dBm dB dBm dBm 6G reception performance Receive sensitivity 802.11A 802.11AX Minimum speed Maximum speed SNM955 Hardware Design Manual dBm dBm Page 73 6.14. Main RF Performance Of B T The following table lists the main RF performance under BT conduction. Table 6.14: Main RF performance parameters under BT conduction Transmit power Receive sensitivity Launch performance DH5 2DH5 3DH5 Receiving performance DH5 2DH5 3DH5 dBm dBm SNM955 Hardware Design Manual Page 74 7. Productio n 7.1. Top And Bottom Views Of The Module Figure 7.1: Module top and bottom views (not yet available) SNM955 Hardware Design Manual Page 75 7.2. Recommended Welding Furnace Temperature Curv e Figure 7.2: Recommended soldering furnace temperature curve for modules SNM955 Hardware Design Manual Page 7 6

) 7.3. Moisture Sensitive Characteristics (MSL The SNM955 module complies with humidity sensitivity class 3. Under the environmental conditions of temperature <30 degrees and relative humidity <60%, dry packaging executes J-STD-

020C specificationaccording to IPC/JEDEC standard. Shelf life is at least 6 months in the unopened condition under ambientconditions of temperature <

40 degrees and relative humidity <90%. After unpacking, Table 22 lists the shelf life of the modules corresponding to different moisture sensitivity levels. Table 7.1: Humidity sensitivity level distinctio n Grade Factory environment++30 /60%RH 1 2 2a 3 4 5 5a 6 Under the condition of environmental 3+30 /85% RH 1 year 4 weeks 168 hours 72 hours 48 hours 24 hours Forced baking before use. After baking, the module must be picked within the time limit specified on the label. After sealing, under the environmental conditions of the temperature <30 degrees and relative humidity

<60%, SMT patch is performed within 168 hours. If the above conditions are not met, it is necessary to bake. Note:

Oxidation risk: Baking SMD packaging may cause metal oxidation, if excessive causes welding problems during the circuit board assembly process. The temperature and time of baking SMD packaging are limited to weldable considerations. The accumulation of baking time should not exceed 96 hours at the temperature greater than 90 C and up to 125 C. SNM955 Hardware Design Manual Page 7 7 7.4. Baking Deman d Due to the wet sensitivity characteristics of the module, the SNM955 should be baked sufficiently before the reflow welding, otherwise the module may cause permanent damage during the return welding process. SNM955 should be baked 192 hours in a low-temperature container with a temperature of 40 C +5 C /-0 C and a relative humidity of less than 5%, or 72 in high temperature containers of the module for 80 C 5 C. Calf -hour baking. The user should notice that the tray is not high to resist, and the user should take the module out of the tray to bake, otherwise the tray may be damaged by high temperature. Table 7.2: Baking requirements

Baking temperature Humidity Baking time 40C5C 120C5C

<5%

<5%

192 hours 4 hours SNM955 Hardware Design Manual Page 7 8 s 8. Support The List Of Peripheral Device SNM955 peripheral devices can support devices contained in the platform QVL. The following is a software default adaptering device. s Table 8.1: Support the list of display screen model Manufacturer ZONEWAY/

Driver IC ILI9881P Specification 1280x720 Table 8.2: List of supporting Camera model Manufacturer YDOPTICS/

YDOPTICS/

SUNNYOPTICAL/

Table 8.3: Support touch screen model list Manufacturer ZONEWAY/

Table 8.4: Support GSENSOR model list Manufacturer Bosch/

Driver IC s5k3m2xx s5k4h7 S5K5E8 Driver IC GT5688 Driver IC BMI120 Specification 13M 8M 5M Specification 5"

Specification 9-Axis,16-bit Table 8.5: Support the ECOMPASS model list Manufacturer ACEINNA /

Driver IC GM303 Specification 3-Axis,14-bit Table 8.6: Support PS/ALS Sensor model list Manufacturer LITEON/

Driver IC LTR-553ALS-01 Specification ALS+PS Table 8.7: Support Gyro Sensor model list SNM955 Hardware Design Manual Page 7 9 Manufacturer Bosch/

Driver IC BMI120 Specification 9-axis,16bit/16bit SNM955 Hardware Design Manual Page 8 0 9.3. Reuse Functio n Table 9.3: Reuse function SNM955 Hardware Design Manual Page 8 1 The GPIO32 and GPIO33 are only used inside the module. The reuse function of the same QUP/SE can only be used at the same time. SNM955 Hardware Design Manual Page 8 2 Doc Products with CE Marking comply with the radio Equipment Directive2014/53/EUand UK Radio Equipment Regulations (SI 2017/1206) The full text of the EU declaration of conformity is available at the following internet address: http://www.meigsmart.com RF exposure statement RF exposure information: The Maximum Permissible Exposure (MPE) level has been calculated based on a distance of d=20 cm between the device and the human body. To maintain compliance with RF exposure requirement, use product that maintain a 20cm distance between the device and human body. Temperature: -40C ~ +75C Bands:

The Radio equipment operation with following frequecy bands Maximum tune-up power(dBm) BT3.0: 10dBm(eirp) Ble: 5dBm(eirp) 2.4GWIFI:19dBm(eirp) 5GWIFI: 16dBm(eirp) 5.8GWIFI:13dBm(eirp) 6G WIFI:13dBm(eirp) 5G WIFI restricetion info:

restricetion info:

This device may be operated in all members states of the EU and UK.Observe national and local regulation where the device is used. This device maybe restricted for use,depending on local network. The restriction 1 2 3 applies in EU and 4 applies in UK.More details as below 1.The 5150-5250MHz frequency band: Indoor, including installations inside road vehicles, trains and aircraft, and limited outdoor use. If used outdoors, equipment shall not be attached to a fixed installation or to the external body of road vehicles, a fixed infrastructure or a fixed outdoor antenna. 2.The 5250-5350MHz frequency band: Indoor use: inside buildings only.Installations in road vehicles, trains and aircraft are not permitted (note 2).Outdoor use is not permitted. 3. The 5470-5725MHz Indoor and outdoor use. Installations in road vehicles, trains and aircraft and use for UAS are not permitted(note3). 4.In accordance with the relevant statutory requirements in UK, the 5150-5350MHz frequency range is restricted to indoor use only in UK. 5.5945 GHz 6.425 GHz isrestricted to indoor only in EU and UK. Note1:If used outdoors, equipment shall not be attached to a fixed installation or to the external body of road vehicles, a fixed infrastructure or a fixed outdoor antenna

. Note2Operation of WAS/RLAN installations in large aircraft () (excluding multi-engined helicopters) is permitted until 31 December 2028 with a maximum mean e.i.r.p. for in-band emissions of 100 mW. Note3: Operation of WAS/RLAN installations in large aircraft (excluding multi-engined helicopters), except in the frequency band 5 600 5 650 MHz, is permitted until 31 December 2028 with a maximum mean e.i.r.p. for in-band emissions of 100 mW. 15.19 Labeling requirements. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. 15.21 Changes or modification warning. Any Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. 15.105 Information to the user. Note: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

-Reorient or relocate the receiving antenna.

-Increase the separation between the equipment and receiver.

-Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

-Consult the dealer or an experienced radio/TV technician for help RF warning for Mobile device:

This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body. This module is intended for OEM integrators only. Per FCC KDB 996369 D03 OEM Manual v01 guidance, the following conditions must be strictly followed when using this certified module:

KDB 996369 D03 OEM Manual v01 rule sections:

2.2 List of applicable FCC rules This module has been tested for compliance to FCC Part 15 2.3 Summarize the specific operational use conditions The module is tested for standalone mobile RF exposure use condition. Any other usage conditions such as co-location with other transmitter(s) or being used in a portable condition will need a separate reassessment through a class II permissive change application or new certification. 2.4 Limited module procedures Not application 2.5 Trace antenna designs Not application 2.6 RF exposure considerations This equipment complies with FCC mobile radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with a minimum distance of 20cm between the radiator & your body. If the module is installed in a portable host, a separate SAR evaluation is required to confirm compliance with relevant FCC portable RF exposure rules. 2.7 Antennas The following antennas have been certified for use with this module; antennas of the same type with equal or lower gain may also be used with this module. The antenna must be installed such that 20 cm can be maintained between the antenna and users. Antenna Type(Dipole) Antenna connector BT/2.4Gwifi 3.95 dBi;

1.46dBi;

U-NII-1 1.52dBi;

U-NII-2A 1.29dBi;

U-NII-2C 1.48dBi;

U-NII-3 0.96dBi;

U-NII-5 0.75dBi;

U-NII-6 0.77dBi;

U-NII-7 U-NII-8 1.56dBi;

SMA 2.8 Label and compliance information The final end product must be labeled in a visible area with the following: Contains FCC ID: 2APJ4-SNM955. The grantee's FCC ID can be used only when all FCC compliance requirements are met. 2.9 Information on test modes and additional testing requirements This transmitter is tested in a standalone mobile RF exposure condition and any co-located or simultaneous transmission with other transmitter(s) or portable use will require a separate class II permissive change re-evaluation or new certification. 2.10 Additional testing, Part 15 Subpart B disclaimer This transmitter module is tested as a subsystem and its certification does not cover the FCC Part 15 Subpart B (unintentional radiator) rule requirement applicable to the final host. The final host will still need to be reassessed for compliance to this portion of rule requirements if applicable. As long as all conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. IMPORTANT NOTE:

In the event that these conditions can not be met (for example certain laptop configurations or co-location with another transmitter), then the FCC authorization is no longer considered valid and the FCC ID can not be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC authorization. Manual Information To the End User:

The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual OEM/Host manufacturer responsibilities OEM/Host manufacturers are ultimately responsible for the compliance of the Host and Module. The final product must be reassessed against all the essential requirements of the FCC rule such as FCC Part 15 Subpart B before it can be placed on the US market. This includes reassessing the transmitter module for compliance with the Radio and EMF essential requirements of the FCC rules. This module must not be incorporated into any other device or system without retesting for compliance as multi-radio and combined equipment Industry Canada statement This complies with ISEDs licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Le prsent appareil est conforme aux CNR d ISED applicables aux appareils radio exempts de licence. Lexploitation est autorise aux deux conditions suivantes : (1) le dispositif ne doit pas produire de brouillage prjudiciable, et (2) ce dispositif doit accepter tout brouillage reu, y compris un brouillage susceptible de provoquer un fonctionnement indsirable. 5GWIFI statement The device is restricted to indoor use when operated in 5150MHz~5350MHz to reduce the potential for interference and 5600-5650 MHz frequency band cannot use in Canada. Radiation Exposure Statement:

This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with greater than 20cm between the radiator & your body. Dclaration d'exposition aux radiations:

Cet quipement est conforme aux limites d'exposition aux rayonnements ISED tablies pour un environnement non contrl. Cet quipement doit tre install et utilis plus de 20 cm entre le radiateur et votre corps. IC statement The final end product must be labeled in a visible area with the following Contains IC:

23860-SNM955 The Host Marketing Name (HMN) must be indicated at any location on the exterior of the host product or product packaging or product literature, which shall be available with the host produc t or online. This radio transmitter [ lC: 23860-SNM955] has been approved by Innovation, Science and Economic Development Canada to operate with the antenna types listed below, with the maximum permissible gain indicated. Antenna types not included in this list that have a gain greater than the maximum gain indicated for any type listed are strictly prohibited for use with this device. Frequency range Manufacturer Peak gain Impedance Antenna type 2400-2483.5Mhz TOXU TECHNOLOGY CO., LTD. 3.95 dBi 50ohm Dipole U-NII-1 TOXU TECHNOLOGY CO., LTD. 1.46dBi 50ohm Dipole U-NII-2A TOXU TECHNOLOGY CO., LTD. 1.52dBi 50ohm Dipole U-NII-2C TOXU TECHNOLOGY CO., LTD. 1.29dBi 50ohm Dipole U-NII-3 U-NII-5 U-NII-6 U-NII-7 U-NII-8 TOXU TECHNOLOGY CO., LTD. 1.48dBi 50ohm Dipole TOXU TECHNOLOGY CO., LTD. 0.96dBi 50ohm Dipole TOXU TECHNOLOGY CO., LTD. 0.75dBi 50ohm Dipole TOXU TECHNOLOGY CO., LTD. 0.77dBi 50ohm Dipole TOXU TECHNOLOGY CO., LTD. 1.56dBi 50ohm Dipole 1.The OEM integrator must be aware not to provide information to the end user regarding how to install or remove this RF module in the user manual of the end product. The user manual which is provided by OEM integrators for end users must include the following information in a prominent location. L'intgrateur OEM doit tre conscient de ne pas fournir d'informations l'utilisateur final sur la manire d'installer ou de retirer ce module RF dans le manuel d'utilisation du produit final. Le manuel d'utilisation fourni par les intgrateurs OEM pour les utilisateurs finaux doit inclure les informations suivantes dans un emplacement visible. 2.To comply with IC RF exposure compliance requirements, the antenna used for this transmitter must not be colocated or operating in conjunction with any other antenna or transmitter, except in accordance with IC multitransmitter product procedures. Pour se conformer aux exigences de conformit de l'exposition RF IC, l'antenne utilise pour cet metteur ne doit pas tre co-localise ou fonctionner en conjonction avec une autre antenne ou un autre metteur, sauf conformment aux procdures du produit multi-metteur IC. 3.The final system integrator must ensure there is no instruction provided in the user manual or customer documentation indicating how to install or remove the transmitter module except such device has implemented twoways authentication between module and the host system. L'intgrateur systme final doit s'assurer qu'aucune instruction n'est fournie dans le manuel de l'utilisateur ou dans la documentation du client indiquant comment installer ou retirer le module transmetteur, sauf qu'un tel dispositif a mis en place une authentification bidirectionnelle entre le module et le systme hte. 4. The host device shall be properly labelled to identify the module within the host device. The end product must be labeled in a visible area with the following: Contains IC: 23860-

SNM955 Any similar wording that expresses the same meaning may be used. Le priphrique hte doit tre correctement tiquet pour identifier le module dans le priphrique hte. Le produit final doit tre tiquet dans une zone visible avec: Contains IC:

23860-SNM955 Toute formulation similaire exprimant la mme signification peut tre utilise. The IC Statement below should also be included on the label. When not possible, the IC Statement should be included in the User Manual of the host device. This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Le prsent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le onctionnement. RLAN devices shall include the following text in the user manual:

Devices shall not be used for control of or communications with unmanned aircraft systems Le dispositif rlan doit inclure le texte suivant dans le manuel de l'utilisateur:

L'quipement ne doit pas tre utilis pour le contrle ou la communication des systmes d'

aronefs sans pilote Comply with RSS-247 and Serves as the general condition,are instruction to OEM if integrator install the module, and use the external antenna that are able to be detached. the following notice . 1the device for operation in the band 51505250 MHz is only for indoor use to reduce the potential for harmful interference to co-channel mobile satellite systems;

2for devices with detachable antenna(s), the maximum antenna gain permitted for devices in the bands 5250-5350 MHz and 5470-5725 MHz shall be such that the equipment still complies with the e.i.r.p. limit;

3for devices with detachable antenna(s), the maximum antenna gain permitted for devices in the band 5725-5850 MHz shall be such that the equipment still complies with the e.i.r.p. limits as appropriate 4where applicable, antenna type(s), antenna models(s), and worst-case tilt angle(s) necessary to remain compliant with the e.i.r.p. elevation mask requirement set forth in section 6.2.2.3 shall be clearly indicated. 5les dispositifs fonctionnant dans la bande de 5 150 5 250 MHz sont rservs uniquement pour une utilisation lintrieur afin de rduire les risques de brouillage prjudiciable aux systmes de satellites mobiles utilisant les mmes canaux;

6pour les dispositifs munis dantennes amovibles, le gain maximal dantenne permis pour les dispositifs utilisant les bandes de 5 250 5 350 MHz et de 5 470 5 725 MHz doit tre conforme la limite de la p.i.r.e;

7pour les dispositifs munis dantennes amovibles, le gain maximal dantenne permis (pour les dispositifs utilisant la bande de 5 725 5 850 MHz) doit tre conforme la limite de la p.i.r.e. spcifie, selon le cas;

8lorsquil y a lieu, les types dantennes (sil y en a plusieurs), les numros de modle de lantenne et les pires angles dinclinaison ncessaires pour rester conforme lexigence de la p.i.r.e. applicable au masque dlvation, nonce la section 6.2.2.3, doivent tre clairement indiqus. Indoor Client 6XD a. Contention-Based Protocol, as demonstrated in the test report, is permanently embedded in the module and is not host-dependent. b. The device will only associate and connect with a low-power indoor access point or subordinate device and never directly connect to other client devices. c. This device will always initiate transmission under the control of a low-power indoor AP or subordinate except for brief transmissions before joining a network. These short messages will only occur if the client has detected an indoor AP or subordinate operating on a channel. These brief messages will have a time-out mechanism such that if it does not receive a response from an AP it will not continually repeat the request. d. Transmissions will be lower or equal to the power advertised by the indoor low-power access point or subordinate and never above the maximum output power allowed by the FCC grant for equipment class 6XD.