FCC ID: XMR2022AG568NNA 5G Module

 

AG568N Series QuecOpen Hardware Design Automotive Module Series Version: 1.0.6 Date: 2023-01-19 Status: Preliminary Automotive Module Series At Quectel, our aim is to provide timely and comprehensive services to our customers. If you require any assistance, please contact our headquarters:

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http://www.quectel.com/support/technical.htm. Or email us at: support@quectel.com. Legal Notices We offer information as a service to you. The provided information is based on your requirements and we make every effort to ensure its quality. You agree that you are responsible for using independent analysis and evaluation in designing intended products, and we provide reference designs for illustrative purposes only. Before using any hardware, software or service guided by this document, please read this notice carefully. Even though we employ commercially reasonable efforts to provide the best possible experience, you hereby acknowledge and agree that this document and related services hereunder are provided to you on an as available basis. We may revise or restate this document from time to time at our sole discretion without any prior notice to you. Use and Disclosure Restrictions License Agreements Documents and information provided by us shall be kept confidential, unless specific permission is granted. They shall not be accessed or used for any purpose except as expressly provided herein. Copyright Our and third-party products hereunder may contain copyrighted material. Such copyrighted material shall not be copied, reproduced, distributed, merged, published, translated, or modified without prior written consent. We and the third party have exclusive rights over copyrighted material. No license shall be granted or conveyed under any patents, copyrights, trademarks, or service mark rights. To avoid ambiguities, purchasing in any form cannot be deemed as granting a license other than the normal non-

exclusive, royalty-free license to use the material. We reserve the right to take legal action for noncompliance with abovementioned requirements, unauthorized use, or other illegal or malicious use of the material. AG568N_Series_QuecOpen_Hardware_Design 1 / 135 Automotive Module Series Trademarks Except as otherwise set forth herein, nothing in this document shall be construed as conferring any rights to use any trademark, trade name or name, abbreviation, or counterfeit product thereof owned by Quectel or any third party in advertising, publicity, or other aspects. Third-Party Rights This document may refer to hardware, software and/or documentation owned by one or more third parties (third-party materials). Use of such third-party materials shall be governed by all restrictions and obligations applicable thereto. We make no warranty or representation, either express or implied, regarding the third-party materials, including but not limited to any implied or statutory, warranties of merchantability or fitness for a particular purpose, quiet enjoyment, system integration, information accuracy, and non-infringement of any third-

party intellectual property rights with regard to the licensed technology or use thereof. Nothing herein constitutes a representation or warranty by us to either develop, enhance, modify, distribute, market, sell, offer for sale, or otherwise maintain production of any our products or any other hardware, software, device, tool, information, or product. We moreover disclaim any and all warranties arising from the course of dealing or usage of trade. Privacy Policy To implement module functionality, certain device data are uploaded to Quectels or third-partys servers, including carriers, chipset suppliers or customer-designated servers. Quectel, strictly abiding by the relevant laws and regulations, shall retain, use, disclose or otherwise process relevant data for the purpose of performing the service only or as permitted by applicable laws. Before data interaction with third parties, please be informed of their privacy and data security policy. Disclaimer a) We acknowledge no liability for any injury or damage arising from the reliance upon the information. b) We shall bear no liability resulting from any inaccuracies or omissions, or from the use of the information contained herein. c) While we have made every effort to ensure that the functions and features under development are free from errors, it is possible that they could contain errors, inaccuracies, and omissions. Unless otherwise provided by valid agreement, we make no warranties of any kind, either implied or express, and exclude all liability for any loss or damage suffered in connection with the use of features and functions under development, to the maximum extent permitted by law, regardless of whether such loss or damage may have been foreseeable. d) We are not responsible for the accessibility, safety, accuracy, availability, legality, or completeness of information, advertising, commercial offers, products, services, and materials on third-party websites and third-party resources. Copyright Quectel Wireless Solutions Co., Ltd. 2023. All rights reserved. AG568N_Series_QuecOpen_Hardware_Design 2 / 135 Automotive Module Series Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be paid to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions, such as when the mobile bill is unpaid or the (U)SIM card is invalid. When emergency help is needed in such conditions, use emergency call if the device supports it. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. In an emergency, the device with emergency call function cannot be used as the only contact method considering network connection cannot be guaranteed under all circumstances. The cellular terminal or mobile contains a transceiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV sets, radios, computers or other electric equipment. In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or metal powders. AG568N_Series_QuecOpen_Hardware_Design 3 / 135 Automotive Module Series About the Document Revision History Version Date Author Description

2021-08-31 1.0.0 2021-08-31 Cathy CHEN/

Jason FAN Cathy CHEN/

Jason FAN Creation of the document Preliminary 1.0.1 2021-10-19 Cathy CHEN/

Jason FAN 1. Updated the pin 60, pin 163 and pin 166 from RESERVED to ADC3, ADC4, ADC5. 2. Updated the pin 132, pin 136 and pin 428 from RESERVED to GPIO 22, GPIO23, GPIO24. 3. Updated the pin 411 and pin 412 from RESERVED to UART3_RXD, UART3_TXD. 4. Updated the pin 275, pin 276, pin 277 and pin 278 from RESERVED to SPI_MISO, SPI3_CLK, SPI3_MOSI, SPI_CS. 5. Updated the package information of the module

(Chapter 8.3). 1.0.2 2021-12-03 Spencer YANG/

Jason FAN Added the related information of AG568N-EU. 1. Modified the pin name of pin 96 and pin 99 (Figure 2). 2. Updated the power domain and DC characteristic 1.0.3 2021-02-18 Cathy CHEN/

Jason FAN of USB_BOOT (Table 6). 3. Updated the description of thermal dissipation 1.0.4 2022-05-23 Cathy CHEN/

Jason FAN/

Pepe HU

(Chapter 6.6). 4. Updated the max slope of manufacturing and soldering (Figure 45&Table 52). 1. Added the sub-models of AG568N-NA and AG568N-ROW. 2. Added the information of module weight (Table 2). 3. Updated the maximum clock frequency rate from AG568N_Series_QuecOpen_Hardware_Design 4 / 135 Automotive Module Series up to 52 MHz to 50 MHz of SPI interface at master mode (Table 4). 4. Updated the information of USB serial driver (Table 4). 5. Modified the information of transmitting power

(Table 4). 6. Updated the DL/UL transmitting rate of LTE-FDD and LTE-TDD on AG568N-CN and AG568N-EU

(Table 4). 7. Updated the way of firmware grade from DFOTA to FOTA (Table 4). 8. Added the max. output current of VDD_EXT (Table 6). 9. Updated the description and comment of USB_VBUS. (Table 6) 10. Updated the chapter USB Application with USB Remote Wakeup Function to USB Application without USB Suspend Function (Chapter 3.2.1.1). 11. Updated the turn-off time by driving PWRKEY low

(Chapter 3.6.1) 12. Updated the reset time by driving RESET_N low

(Chapter 3.7). 13. Updated the R3 in the reference circuit of USB application from NM_0R to 0R (Tabel 15). 14. Deleted the simple block diagram for Ethernet application (Chapter 4.12&4.13) 15. Updated the information of Tx power (Chapter 5.1.2). 16. Updated the information of Rx sensitivity (Chapter 5.1.3). 17. Added the conditions and typical value of power consumption on AG568N-CN and added the conditions of power consumption on AG568N-EU

(Table 51&52). 1. Updated the information of USB serial driver

(Table 4). 2. Updated the information of receiving sensitivity

(Chapter 5.1.3). 3. Deleted the consumption. information of GNSS power 1. Updated the frequency bands of AG568N-NA and AG568N-ROW. 2. Updated the baud rates of Debug UART (Table 4

& Table 12). 1.0.5 2022-08-30 Cathy CHEN/

Kiasher WANG/

Pepe HU 1.0.6 2023-01-19 Cathy CHEN/

Jason FAN AG568N_Series_QuecOpen_Hardware_Design 5 / 135 Automotive Module Series 3. Updated the data rates (Table 4). 4. Updated the LTE features (Table 4). 5. Updated the description of for VDD_EXT, RESET_N, USB_VBUS, USB_DP/DM, DBG_RXD/TXD, USB_BOOT (Table 6 & Table 10

& Table 11 & Table 13 & Table 28). tests points 6. Updated the PWRKEY (Chapter 3.5.1). information of turning on with 7. Updated the data of powering-down timing

(Figure 11). 8. Updated the timing and parameters of SPI interfaces in master mode (Figure 26 & Table 27). 9. Updated the pin definition of cellular network interface (Chapter 5.1.1.1). 10. Updated the

(Chapter 5.1.1.2). operating frequency 11. Updated Rx sensitivity (Chapter 5.1.3). 12. Updated GNSS performance (Chapter 5.2.2). 13. Updated the antenna design requirements

(Table 48). 14. Updated the power supply ratings (Table 50). 15. Updated the data of power consumption

(Chapter 6.3). 16. Updated the information of manufacturing and soldering (Chapter 8.2). 17. Added the mounting direction (Chapter 8.3.3). AG568N_Series_QuecOpen_Hardware_Design 6 / 135 Automotive Module Series Contents Safety Information ....................................................................................................................................... 3 About the Document ................................................................................................................................... 4 Contents ....................................................................................................................................................... 7 Table Index ................................................................................................................................................. 10 Figure Index ............................................................................................................................................... 12 1 Introduction ........................................................................................................................................ 14 Special Marks .......................................................................................................................... 17 1.1. 2 Product Overview .............................................................................................................................. 18 Frequency Bands and Functions ............................................................................................ 19 Key Features ........................................................................................................................... 20 Functional Diagram ................................................................................................................. 24 Pin Assignment ........................................................................................................................ 25 Pin Description ........................................................................................................................ 26 EVB Kit .................................................................................................................................... 39 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 3.3. 3.4. 3 Operating Characteristics ................................................................................................................. 40 3.1. Operating Modes ..................................................................................................................... 40 Sleep Mode ............................................................................................................................. 41 3.2. 3.2.1.1. USB Application Scenario (without USB Suspend Function) ......................... 41 Airplane Mode ......................................................................................................................... 42 Power Supply .......................................................................................................................... 43 3.4.1. Power Supply Pins ......................................................................................................... 43 3.4.2. Reference Design for Power Supply .............................................................................. 43 3.4.3. Voltage Stability Requirements ...................................................................................... 44 Turn On ................................................................................................................................... 45 3.5.1. Turn On with PWRKEY .................................................................................................. 45 Turn Off .................................................................................................................................... 47 3.6.1. Turn Off with PWRKEY .................................................................................................. 47 3.6.2. Turn Off with Linux Commands ...................................................................................... 48 Reset ....................................................................................................................................... 48 3.7. 3.5. 3.6. 4 Application Interfaces ....................................................................................................................... 51 USB Interface .......................................................................................................................... 51 4.1. UART Interfaces ...................................................................................................................... 53 4.2.

(U)SIM Interfaces .................................................................................................................... 56 4.3. I2C Interfaces .......................................................................................................................... 59 4.4. I2S Interface ............................................................................................................................ 59 4.5. 4.6. PCM Interface ......................................................................................................................... 60 4.7. WLAN and Bluetooth Application Interfaces ........................................................................... 61 4.8. Analog Audio Interfaces (Optional) ......................................................................................... 62 4.9. GPIOs ...................................................................................................................................... 63 AG568N_Series_QuecOpen_Hardware_Design 7 / 135 Automotive Module Series 4.10.1. 4.10. SDIO Interface ......................................................................................................................... 64 Reference Design for eMMC Application ............................................................... 66 4.11. ADC Interfaces ........................................................................................................................ 67 4.12. SGMII Interface ....................................................................................................................... 68 4.13. RGMII Interface ....................................................................................................................... 69 4.14. RTC ......................................................................................................................................... 72 4.15. SPI Interfaces .......................................................................................................................... 72 4.16. USB_BOOT ............................................................................................................................. 74 4.17. PCIe Interface ......................................................................................................................... 75 4.18. Control Signals ........................................................................................................................ 78 WAKEUP_IN ........................................................................................................... 78 WAKEUP_OUT ....................................................................................................... 78 4.18.1. 4.18.2. 5.1. 5.1.1.1. 5.1.1.2. 5 RF Specifications ............................................................................................................................... 79 Cellular Network ...................................................................................................................... 79 5.1.1. Antenna Interfaces & Frequency Bands ........................................................................ 79 Pin Definition of Cellular Network Interface.................................................... 79 Operating Frequency ...................................................................................... 81 5.1.2. Tx Power ........................................................................................................................ 84 5.1.3. Rx Sensitivity .................................................................................................................. 85 5.1.4. Reference Design .......................................................................................................... 89 5.2. GNSS ...................................................................................................................................... 90 5.2.1. Antenna Interfaces & Frequency Bands ........................................................................ 90 5.2.2. GNSS Performance ....................................................................................................... 91 5.2.3. Reference Design .......................................................................................................... 91 RF Routing Guidelines ............................................................................................................ 92 Antenna Design Requirements ............................................................................................... 94 RF Connector Recommendation ............................................................................................ 95 5.3. 5.4. 5.5. 6.1. 6.2. 6.3. 6 Electrical Characteristics and Reliability ........................................................................................ 96 Absolute Maximum Ratings .................................................................................................... 96 Power Supply Ratings ............................................................................................................. 97 Power Consumption ................................................................................................................ 97 6.3.1. AG568N-CN Power Consumption ................................................................................. 97 6.3.2. AG568N-EU Power Consumption................................................................................ 104 6.3.3. AG568N-NA Power Consumption ................................................................................ 113 6.3.4. AG568N-ROW Power Consumption ............................................................................ 116 6.4. ESD Protection ...................................................................................................................... 120 6.5. Operating and Storage Temperatures ................................................................................... 121 Thermal Dissipation............................................................................................................... 121 6.6. 7 Mechanical Information ................................................................................................................... 123 7.1. Mechanical Dimensions ........................................................................................................ 123 Recommended Footprint ....................................................................................................... 125 7.2. Top and Bottom Views........................................................................................................... 126 7.3. AG568N_Series_QuecOpen_Hardware_Design 8 / 135 Automotive Module Series 8 Storage, Manufacturing & Packaging ............................................................................................ 127 8.1. Storage Conditions ................................................................................................................ 127 8.2. Manufacturing and Soldering ................................................................................................ 128 Packaging Specifications ...................................................................................................... 129 8.3. 8.3.1. Carrier Tape .................................................................................................................. 130 8.3.2. Plastic Reel .................................................................................................................. 130 8.3.3. Mounting Direction ....................................................................................................... 131 8.3.4. Packaging Process ...................................................................................................... 131 9 Appendix References ...................................................................................................................... 133 AG568N_Series_QuecOpen_Hardware_Design 9 / 135 Automotive Module Series Table Index Table 1: Special Marks ............................................................................................................................... 17 Table 2: Brief Introduction of the Module ................................................................................................... 18 Table 3: Frequency Bands and Functions of AG568N Series ................................................................... 19 Table 4: Key Features ................................................................................................................................ 20 Table 5: I/O Parameters Definition ............................................................................................................. 26 Table 6: Pin Description ............................................................................................................................. 26 Table 7: Overview of Operating Modes ...................................................................................................... 40 Table 8: Pin Definition of Power Supply ..................................................................................................... 43 Table 9: Pin Definition of PWRKEY ............................................................................................................ 45 Table 10: Pin Definition of RESET_N ......................................................................................................... 49 Table 11: Pin Definition of USB Interface ................................................................................................... 51 Table 12: Features of UART Interfaces ...................................................................................................... 53 Table 13: Pin Definition of UART Interfaces ............................................................................................... 54 Table 14: Pin Definition of (U)SIM Interface ............................................................................................... 56 Table 15: Pin Definition of I2C Interfaces ................................................................................................... 59 Table 16: Pin Definition of I2S Interface ..................................................................................................... 59 Table 17: Pin Definition of PCM Interface .................................................................................................. 60 Table 18: Pin Definition of Coexistence Control Interface ......................................................................... 61 Table 19: Pin Definition of Analog Audio Interfaces ................................................................................... 63 Table 20: Pin Description of GPIO Interfaces ............................................................................................ 63 Table 21: Pin Definition of SDIO Interface ................................................................................................. 65 Table 22: Pin Definition of ADC Interfaces ................................................................................................. 67 Table 23: Characteristics of ADC Interfaces .............................................................................................. 67 Table 24: Pin Definition of SGMII Interface ................................................................................................ 68 Table 25: Pin Definition of RGMII Interface ................................................................................................ 70 Table 26: Pin Definition of SPI Interface .................................................................................................... 72 Table 27: Parameters of SPI Interfaces Timing in Master Mode ............................................................... 73 Table 28: Pin Definition of USB_BOOT...................................................................................................... 74 Table 29: Pin Definition of PCIe Interface .................................................................................................. 76 Table 30: Pin Definition of WAKEUP_IN .................................................................................................... 78 Table 31: Pin Definition of WAKEUP_OUT ................................................................................................ 78 Table 32: Pin Definition of AG568N-CN Cellular Network Interface .......................................................... 79 Table 33: Pin Definition of AG568N-EU Cellular Network Interface .......................................................... 80 Table 34: Pin Definition of AG568N-NA Cellular Network Interface ........................................................... 80 Table 35: Pin Definition of AG568N-ROW Cellular Network Interface....................................................... 81 Table 36: AG568N-CN Operating Frequency ............................................................................................ 81 Table 37: AG568N-EU Operating Frequency ............................................................................................. 82 Table 38: AG568N-NA Operating Frequency ............................................................................................. 83 Table 39: AG568N-ROW Operating Frequency ......................................................................................... 84 Table 40: Tx Power (25 C, 3.8 V Power Supply) ...................................................................................... 84 Table 41: AG568N-CN Conducted RF Receiving Sensitivity (Unit: dBm) ................................................. 85 AG568N_Series_QuecOpen_Hardware_Design 10 / 135 Automotive Module Series Table 42: AG568N-EU Conducted RF Receiving Sensitivity (Unit: dBm) ................................................. 86 Table 43: AG568N-NA Conducted RF Receiving Sensitivity (Unit: dBm) .................................................. 87 Table 44: AG568N-ROW Conducted RF Receiving Sensitivity (Unit: dBm) .............................................. 88 Table 45: Pin Definition of GNSS Antenna Interface ................................................................................. 90 Table 46: GNSS Frequency (Unit: MHz) .................................................................................................... 90 Table 47: GNSS Performance .................................................................................................................... 91 Table 48: Antenna Design Requirements .................................................................................................. 94 Table 49: Absolute Maximum Ratings ........................................................................................................ 96 Table 50: Power Supply Ratings ................................................................................................................ 97 Table 51: AG568N-CN Power Consumption (25 C, 3.8 V Power Supply) ............................................... 97 Table 52: AG568N-EU Power Consumption (25 C, 3.8 V Power Supply) ............................................. 104 Table 53: AG568N-NA Power Consumption (25 C, 3.8 V Power Supply) .............................................. 113 Table 54: AG568N-ROW Power Consumption (25 C, 3.8 V Power Supply).......................................... 116 Table 55: ESD Characteristics (Temperature: 2530 C, Humidity: 40 5 %) ......................................... 121 Table 56: Operating and Storage Temperatures ...................................................................................... 121 Table 57: Recommended Thermal Profile Parameters ............................................................................ 129 Table 58: Carrier Tape Dimension Table (Unit: mm) ................................................................................ 130 Table 59: Plastic Reel Dimension Table (Unit: mm) ................................................................................. 131 Table 60: Related Documents .................................................................................................................. 133 Table 61: Terms and Abbreviations .......................................................................................................... 133 AG568N_Series_QuecOpen_Hardware_Design 11 / 135 Automotive Module Series Figure Index Figure 1: Functional Diagram ..................................................................................................................... 24 Figure 2: Pin Assignment (Top View) ......................................................................................................... 25 Figure 3: Sleep Mode Power Consumption Diagram ................................................................................ 41 Figure 4: Sleep-Mode Application without Suspend Function ................................................................... 42 Figure 5: Reference Design of Power Supply ............................................................................................ 44 Figure 6: Power Supply Limits During Burst Transmission ........................................................................ 44 Figure 7: Star Structure of the Power Supply ............................................................................................ 45 Figure 8: Turn On the Module Using Driving Circuit .................................................................................. 46 Figure 9: Turn On the Module Using a Button ........................................................................................... 46 Figure 10: Power-up Timing ....................................................................................................................... 47 Figure 11: Power-down Timing ................................................................................................................... 48 Figure 12: Reference Circuit of RESET_N with Driving Circuit ................................................................. 49 Figure 13: Reference Circuit of RESET_N with Button ............................................................................. 49 Figure 14: Reset Timing ............................................................................................................................. 50 Figure 15: Reference Circuit of USB Application ....................................................................................... 52 Figure 16: Reference Circuit with Translator Chip ..................................................................................... 55 Figure 17: Reference Circuit with Transistor Circuit (UART1) ................................................................... 55 Figure 18: UART Interface Connection (UART2) ....................................................................................... 56 Figure 19: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector ......................... 57 Figure 20: Reference Circuit of a 6-Pin (U)SIM Card Connector .............................................................. 58 Figure 21: I2S and I2C1 Application with External Audio Codec ............................................................... 60 Figure 22: WLAN & Bluetooth Application Interfaces Connection Block Diagram .................................... 62 Figure 23: Reference Design for eMMC Application.................................................................................. 66 Figure 24: Reference Circuit of SGMII Interface with PHY Application ..................................................... 69 Figure 25: Reference Circuit of RGMII Interface with PHY Application ..................................................... 71 Figure 26: SPI Interfaces Timing in Master Mode...................................................................................... 73 Figure 27: Reference Circuit of SPI Interfaces with a Voltage-level Translator......................................... 74 Figure 28: Reference Circuit of USB_BOOT ............................................................................................. 74 Figure 29: Timing Sequence for Entering Emergency Download Mode ................................................... 75 Figure 30: PCIe Interface Connection ........................................................................................................ 77 Figure 31: Reference Circuit for RF Antenna Interfaces ............................................................................ 89 Figure 32: Reference Circuit of GNSS Antenna ........................................................................................ 92 Figure 33: Microstrip Design on a 2-layer PCB ......................................................................................... 93 Figure 34: Coplanar Waveguide Design on a 2-layer PCB ....................................................................... 93 Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 93 Figure 36: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 94 Figure 37: Description of the HFM Connector ........................................................................................... 95 Figure 38: Placement and Fixing of the Heatsink .................................................................................... 122 Figure 39: Module Top and Side Dimensions (Unit: mm) ........................................................................ 123 Figure 40: Module Bottom Dimensions (Bottom View, Unit: mm) ........................................................... 124 Figure 41: Recommended Footprint (Top View, Unit: mm) ...................................................................... 125 AG568N_Series_QuecOpen_Hardware_Design 12 / 135 Automotive Module Series Figure 42: Top and Bottom Views of the Module ..................................................................................... 126 Figure 43: Recommended Reflow Soldering Thermal Profile ................................................................. 128 Figure 44: Carrier Tape Dimension Drawing ............................................................................................ 130 Figure 45: Plastic Reel Dimension Drawing ............................................................................................ 130 Figure 46: Mounting Direction .................................................................................................................. 131 Figure 47: Packaging Process ................................................................................................................. 132 AG568N_Series_QuecOpen_Hardware_Design 13 / 135 Automotive Module Series 1 Introduction QuecOpen is a solution where the module acts as the main processor. Constant transition and evolution of both the communication technology and the market highlight its merits. It can help you to:

Realize embedded applications quick development and shorten product R&D cycle Simplify circuit and hardware structure design to reduce engineering costs Miniaturize products Reduce product power consumption Apply OTA technology Enhance product competitiveness and price-performance ratio This document defines the AG568N series in QuecOpen solution and describes its air interface and hardware interfaces which are connected with your applications. It can help you quickly understand interface specifications, electrical and mechanical details, as well as other related information of the module. Associated with application notes and user guides, you can use this module to design and to set up automotive industry mobile applications easily. FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met:

1. This Modular Approval is limited to OEM installation for mobile and fixed applications only. The antenna installation and operating configurations of this transmitter, including any applicable source-

based timeaveraging duty factor, antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements of 2.1091. 2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the users body and must not transmit simultaneously with any other antenna or transmitter. 3. A label with the following statements must be attached to the host end product: This device contains FCC ID: XMR2022AG568NNA 4. To comply with FCC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed:

radiation, maximum antenna gain (including cable loss) must not exceed: Operating Band LTE BAND 2 LTE BAND 4 FCC Max Antenna Gain IC Max Antenna Gain

(dBi) 8.00 5.00

(dBi) 8.00 5.00 AG568N_Series_QuecOpen_Hardware_Design 14 / 135 Automotive Module Series LTE BAND 5 LTE BAND 12 LTE BAND 66 NR BAND 2 NR BAND 5 NR BAND 12 NR BAND 66 NR BAND 77 NR BAND 78 9.41 8.70 5.00 8.00 9.42 8.71 5.00 3.00 3.00 6.12 5.64 5.00 8.00 6.13 5.64 5.00

5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093 If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations. For this device, OEM integrators must be provided with labeling instructions of finished products. Please refer to KDB784748 D01 v07, section 8. Page 6/7 last two paragraphs:

A certified modular has the option to use a permanently affixed label, or an electronic label. For a permanently affixed label, the module must be labeled with an FCC ID - Section 2.926 (see 2.2 Certification (labeling requirements) above). The OEM manual must provide clear instructions explaining to the OEM the labeling requirements, options and OEM user manual instructions that are required (see next paragraph). For a host using a certified modular with a standard fixed label, if (1) the modules FCC ID is not visible when installed in the host, or (2) if the host is marketed so that end users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible;

then an additional permanent label referring to the enclosed module: Contains Transmitter Module FCC ID: XMR2022AG568NNA or Contains FCC ID: XMR2022AG568NNA must be used. The host OEM user manual must also contain clear instructions on how end users can find and/or access the module and the FCC ID. The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The users manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. In cases where the manual is provided only in a form other than paper, such as on a computer disk or over the Internet, the information required by this section may be included in the manual in that alternative form, provided the user can reasonably be expected to have the capability to access information in that form. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the manufacturer could void the users authority to operate the equipment. AG568N_Series_QuecOpen_Hardware_Design 15 / 135 Automotive Module Series To ensure compliance with all non-transmitter functions the host manufacturer is responsible for ensuring compliance with the module(s) installed and fully operational. For example, if a host was previously authorized as an unintentional radiator under the Suppliers Declaration of Conformity procedure without a transmitter certified module and a module is added, the host manufacturer is responsible for ensuring that the after the module is installed and operational the host continues to be compliant with the Part 15B unintentional radiator requirements. Manual Information To the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. Product Marketing Name: Quectel AG568N-NA IC Statement IRSS-GEN

"This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device." or "Le prsent appareil est conforme aux CNR dIndustrie Canada applicables aux appareils radio exempts de licence. Lexploitation est autorise aux deux conditions suivantes :

1) lappareil ne doit pas produire de brouillage; 2) lutilisateur de lappareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible den compromettre le fonctionnement."

Dclaration sur l'exposition aux rayonnements RF L'autre utilis pour l'metteur doit tre install pour fournir une distance de sparation d'au moins 20 cm de toutes les personnes et ne doit pas tre colocalis ou fonctionner conjointement avec une autre antenne ou un autre metteur. The host product shall be properly labeled to identify the modules within the host product. The Innovation, Science and Economic Development Canada certification label of a module shall be clearly visible at all times when installed in the host product; otherwise, the host product must be labeled to display the Innovation, Science and Economic Development Canada certification number for the module, preceded by the word Contains or similar wording expressing the same meaning, as follows:

Contains IC: 10224A-022AG568NNA or where: 10224A-022AG568NNAis the modules certification number. Le produit hte doit tre correctement tiquet pour identifier les modules dans le produit hte. L'tiquette de certification d'Innovation, Sciences et Dveloppement conomique Canada d'un module doit tre clairement visible en tout temps lorsqu'il est installdans le produit hte; sinon, le produit hte doit porter une tiquette indiquant le numro de certification d'Innovation, Sciences et Dveloppement conomique Canada pour le module, prcd du mot Contient ou d'un libell semblable exprimant la mme signification, comme suit:

"Contient IC: 10224A-022AG568NNA" ou "o: 10224A-022AG568NNA est le numro de certification du module". AG568N_Series_QuecOpen_Hardware_Design 16 / 135 Automotive Module Series 1.1. Special Marks Table 1: Special Marks Mark Definition

Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin, AT command, or argument is under development and currently not supported; and the asterisk

(*) after a model indicates that the sample of the model is currently unavailable. Brackets ([]) used after a pin enclosing a range of numbers indicate all pins of the same four SDIO pins: SDIO_DATA0, type. For example, SDIO_DATA[0:3] refers SDIO_DATA1, SDIO_DATA2, and SDIO_DATA3. to all AG568N_Series_QuecOpen_Hardware_Design 17 / 135 Automotive Module Series 2 Product Overview AG568N series module is an SMD type module which is engineered to meet the demanding requirements in automotive applications and other harsh operating conditions. More specifically, the module will be commonly found in telematics boxes (T-Box), telematics control units (TCU), advanced driver-assistance systems (ADAS), on-board units (OBU), roadside units (RSU), and other automotive/traffic systems. Related information and details are listed in the table below:

Table 2: Brief Introduction of the Module Basic Information Pin number and package 426 LGA pins Dimensions

(45.0 0.2) mm (46.9 0.2) mm (3.25 0.2) mm. Weight Approx. 16 g Wireless technologies 5G NR, LTE, WCDMA, GSM Single-frequency GNSS/dual-frequency GNSS Variants AG568N-CN AG568N-EU AG568N-NA AG568N-ROW AG568N_Series_QuecOpen_Hardware_Design 18 / 135 Automotive Module Series 2.1. Frequency Bands and Functions Table 3: Frequency Bands and Functions of AG568N Series Mode AG568N-CN AG568N-EU AG568N-NA AG568N-ROW SA n1/n3/n28A 1/n41/n78 n1/n3/n7/n8/n20/n28/n77/n78 n2/n5/n12/n66/n77/n78 n28/n77/n78/n79 NSA n41/n78 n77/n78 n2/n5/n66/n77 n77/n78/n79 FDD B1/B3/B5/B7/B8 B1/B3/B5/B7/B8/B20/B28/B32 2 B2/B4/B5/B12/B29 2/B66 B1/B3/B19/B21 3/B28 5G NR LTE TDD B34/B38/B39/B40/B41 B38/B40 WCDMA B1/B8 B1/B3/B5/B8 GSM EGSM900/DCS1800 EGSM900/DCS1800

GNSS 4 Single-frequency GNSS (GPS, GLONASS, BDS, Galileo): L1 Dual-frequency GNSS (GPS, GLONASS, BDS, Galileo): L1 + L5

B1/B3

1 5G FDD n28A supports Tx at 703733 MHz (UL) and Rx at 758788 MHz (DL). 2 LTE B29 and B32 support Rx only. 3 LTE B21 only supports 2 2 MIMO. 4 AG568N series only supports dual-frequency GNSS (L1 + L5) by default, but the module is designed to be compatible with single-frequency GNSS (L1). For more details, please contact Quectel Technical Support. AG568N_Series_QuecOpen_Hardware_Design 19 / 135 Automotive Module Series 2.2. Key Features Table 4: Key Features Features Details Power Supply SMS VBAT_BB/VBAT_RF:

Supply voltage: 3.34.3 V Typical supply voltage: 3.8 V Text and PDU mode Point-to-point MO and MT SMS cell broadcast SMS storage: ME by default

(U)SIM Interfaces Supports (U)SIM card: 1.8/3.0 V Supports Dual SIM Dual Standby (DSDS) 5 Audio Features Digital Audio Interfaces SPI Interfaces I2C Interfaces Support two digital audio interfaces: I2S interface and PCM interface GSM: HR/FR/EFR/AMR/AMR-WB WCDMA: AMR/AMR-WB LTE: AMR/AMR-WB Support echo cancellation and noise suppression PCM:

Used for Bluetooth audio transmission by default Supports 16-bit and 24-bit precision in PCM data path Supports long frame synchronization and short frame synchronization Supports master and slave modes I2S:

Supports 8192 kHz sampling rate Used for audio function with external codec IC by default Three SPI interfaces: SPI1 and SPI2 only support master mode, SPI3 supports both master and slave modes. Maximum clock frequency rate:

- Master mode: 50 MHz

- Slave mode: 26 MHz Two I2C interfaces Compliant with UM10204 I2C-bus specification and user manual Multi-master mode is not supported SGMII Interface Supports 10/100/1000/2500 Mbps in full duplex mode Supports 10/100 Mbps in half duplex mode 5 DSDS function is optional. AG568N_Series_QuecOpen_Hardware_Design 20 / 135 Automotive Module Series RGMII Interface Supports 10/100/1000 Mbps in half/full duplex mode WLAN and Bluetooth Application Interfaces Supports PCIe interface for WLAN function Supports Bluetooth UART and PCM interfaces for Bluetooth function USB Interface Compliant with USB 3.1 and 2.0 specifications, with transmission rates up to 480 Mbps on USB 2.0 and 5 Gbps on USB 3.1 Used for AT command communication, data transmission, software debugging, firmware upgrade and GNSS NMEA sentences output USB 3.1 and USB 2.0 support data communication with external AP, and cannot be used simultaneously since they share the same controller USB serial driver: supports USB serial driver for Windows 7/8/8.1/10/11, Linux 2.65.18 and Android 4.x12.x systems SDIO Interface Supports eMMC version 5.1 and HS400 mode UART Interfaces UART1 (Main UART):

Used for AT command communication and data transmission Baud rate: 115200 bps by default Supports RTS and CTS hardware flow control UART2 (Bluetooth UART):

Used for Bluetooth function Baud rate: 9600 bps by default Supports RTS and CTS hardware flow control UART3 (V2X):

Used for external V2X function Baud rate: 9600 bps by default Debug UART:

Used for Linux console and log output Baud rate: 115200 bps by default PCIe Interface Compliant with PCIe Gen 3, supports 2-lane, 8 Gbps/lane Compliant with PCI Express Base Specification Revision 3.0 Supports RC and EP mode in hardware design, but only supports RC mode in the software design Can be used to connect with an external WLAN IC and used for Wi-Fi communication by default AT Commands Compliant with 3GPP TS 27.007 and 3GPP TS 27.005 Quectel enhanced AT commands Rx-diversity 5G NR/LTE/WCDMA Antenna Interface One main antenna interface (ANT_MAIN) One diversity antenna interface (ANT_DRX) Two MIMO antenna interfaces (ANT_MIMO3, ANT_MIMO4) One GNSS antenna interface (ANT_GNSS) 50 impedance Tx Power 5G NR TDD bands: Class 2 (26 dBm +1/-2 dB) AG568N_Series_QuecOpen_Hardware_Design 21 / 135 Automotive Module Series 5G NR FDD bands: Class 3 (23 dBm 2 dB) LTE bands: Class 3 (23 dBm 2 dB) WCDMA bands: Class 3 (23 dBm 2 dB) EGSM900: Class 4 (33 dBm 2 dB) DCS1800: Class 1 (30 dBm 2 dB) EGSM900 8-PSK: Class E2 (27 dBm 3 dB) DCS1800 8-PSK: Class E2 (26 dBm 3 dB) Support 3GPP Rel-15 Support uplink 256QAM and downlink 256QAM Support 4 4 MIMO for MHB bands in DL direction Support SCS 15 kHz @ FDD and 30 kHz @ TDD Support SA and NSA operation modes

- NSA: supports option 3x, 3a, and option 3

- SA: supports option 3 Max. data rates:

AG568N-CN/-EU

- NSA: Max. 2.4 Gbps (DL)/550 Mbps (UL)

- SA: Max. 3.8 Gbps (DL 2CA)/480 Mbps (UL) AG568N-NA

- NSA: Max. 3.5 Gbps (DL)/550 Mbps (UL)

- SA: Max. 3.8 Gbps (DL 2CA)/480 Mbps (UL) AG568N-ROW

- NSA: Max. 2.7 Gbps (DL)/550 Mbps (UL)

- SA: Max. 3.8 Gbps (DL 2CA)/480 Mbps (UL) AG568N-CN:

Support up to DL CA Cat 15 LTE-FDD and TDD Support 1.4/3/5/10/15/20 MHz RF bandwidth Support 4 4 MIMO for MHB bands in DL direction Supports QPSK, 16QAM and 64QAM and 256QAM modulation in UL/DL direction FDD: Max. 750 Mbps (DL)/80 Mbps (UL) TDD: Max. 650 Mbps (DL)/50 Mbps (UL) AG568N-EU:

Support up to DL CA Cat 19 LTE-FDD and TDD Support 1.4/3/5/10/15/20 MHz RF bandwidth Support 4 4 MIMO for MHB bands in DL direction Supports QPSK, 16QAM and 64QAM and 256QAM modulation in UL/DL direction FDD: Max 1.6 Gbps (DL)/150 Mbps (UL) TDD: Max 1.0 Gbps (DL)/100 Mbps (UL) AG568N-NA:

Support up to DL CA Cat 18 LTE-FDD Support 1.4/3/5/10/15/20 MHz RF bandwidth Support 4 4 MIMO for MHB bands in DL direction 5G NR Features LTE Features AG568N_Series_QuecOpen_Hardware_Design 22 / 135 Automotive Module Series Supports QPSK, 16QAM and 64QAM and 256QAM modulation in UL/DL direction FDD: Max 1.5 Gbps (DL)/150 Mbps (UL) AG568N-ROW:

Support up to DL CA Cat 16 LTE-FDD Support 1.4/3/5/10/15/20 MHz RF bandwidth Support 4 4 MIMO for MHB 6 bands in DL direction Supports QPSK, 16QAM and 64QAM and 256QAM modulation in UL/DL direction FDD: Max 1.1 Gbps (DL)/150 Mbps (UL) Support 3GPP Rel-8 DC-HSDPA, HSPA+, HSDPA, HSUPA, WCDMA Support QPSK, 16QAM and 64QAM modulation DC-HSDPA: Max. 42 Mbps (DL) DC-HSUPA: Max. 11 Mbps (UL) WCDMA: Max. 384 kbps (DL)/384 kbps (UL) GPRS:

Support GPRS multi-slot class 33 (by default) Coding scheme: CS 14 Max. 107 kbps (DL)/85.6 kbps (UL) EDGE:

Support EDGE multi-slot class 33 (by default) Supports GMSK and 8-PSK for different MCS (Modulation and Coding Scheme) Downlink coding schemes: MCS 19 Uplink coding schemes: MCS 19 Max. 296 kbps (DL)/236.8 kbps (UL) Supports GPS, GLONASS, BDS, Galileo Support single-frequency GNSS: L1 Support dual-frequency GNSS L1 + L5 Protocol: NMEA 0183 Update rate: 1 Hz by default, up to 10 Hz UMTS Features 7 GSM Features 8 GNSS Features Temperature Range Operating temperature range 9: -35 C to +75 C Extended operating temperature range 10: -40 C to +85 C eCall temperature range 11: -40 C to +95 C Storage temperature range: -40 C to +95 C 6 LTE B21 only support to 2 2 MIMO. 7 AG568N-NA does not support UMTS function. 8 AG568N-NA and AG568N-ROW do not support GSM function. 9 Within the operating temperature range, the module meets 3GPP specifications. 10 Within the extended temperature range, the module remains the ability to establish and maintain functions such as voice, SMS, data transmission, eCall*, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may exceed the specified tolerances of 3GPP. When the temperature returns to the operating temperature range, the module meets 3GPP specifications again. 11 Within eCall temperature range, the eCall function must be functional until the module is broken. When the ambient temperature is between 75 C and 95 C and the module temperature has reached the threshold value, the module will trigger protective measures (such as reduce power, decrease throughput, unregister the device, etc.) to ensure the full function of eCall. AG568N_Series_QuecOpen_Hardware_Design 23 / 135 Automotive Module Series Firmware Upgrade USB 2.0 interface FOTA RoHS All hardware components are fully compliant with EU RoHS directive 2.3. Functional Diagram The following figure shows a block diagram of the module and illustrates the major functional parts. Power management Baseband LPDDR4X+ NAND flash Radio frequency Peripheral interfaces Figure 1: Functional Diagram AG568N_Series_QuecOpen_Hardware_Design 24 / 135 ANT_DRXANT_MIMO3ANT_GNSSVBAT_BBVBAT_RFPWRKEYADCsRESET_NDRFControlTxPRxDRxSPIsANT_MAINANT_MIMO4VDD_EXTUSB 2.0/3.1(U)SIMsUARTsI2CsPCIeSDIORGMIII2SMIPI&GRFC26 MHzXOControlTx/Rx BlocksPMURF TransceiverLPDDR4X NAND flashBasebandGNSSTransceiverIQSGMIIGPIOsPCMADCs26 MHzTCXO Automotive Module Series 2.4. Pin Assignment The following figure illustrates the pin assignment of the module. Figure 2: Pin Assignment (Top View) NOTE 1. Keep all RESERVED pins and unused pins unconnected. 2. GND pins should be connected to ground. AG568N_Series_QuecOpen_Hardware_Design 25 / 135 Power PinsGND PinsRESERVED PinsPCIe PinsPCM Pins(U)SIM PinsUSB PinsI2C PinsUART PinsSPI PinsAntenna PinsSDIO PinsRGMII PinsSignal PinsI2S PinsADC Pins1MIC1_N2MIC1_P3MICBIAS4MIC2_N5MIC2_P6AGND7PWRKEY8RESET_N9GPIO 910RGMII_MD_IO11RGMII_MD_CLK12GND13RGMII_RX_014RGMII_RX_115RGMII_CTL_RX16RGMII_RX_217RGMII_RX_318GND19RGMII_CK_RX20RGMII_TX_021RGMII_CTL_TX22RGMII_TX_123RGMII_TX_224RGMII_CK_TX25RGMII_TX_326GND27GPIO1928RESERVED29RGMII_INT30PCIE_WAKE_N31RGMII_RST32PCIE_RX0_M33GND34PCIE_RX0_P35PCIE_RX1_M36PCIE_CLKREQ_N37PCIE_RX1_P38PCIE_REFCLK_M39PCIE_RST_N40PCIE_REFCLK_P41PCIE_TX1_M42GND43PCIE_TX1_P44PCIE_TX0_M45RESERVED46PCIE_TX0_P47SDIO_CLK48SDIO_CMD49SDIO_DATA050SDIO_DATA151SDIO_DATA252SDIO_DATA353SDIO_DATA454EMMC_RST55SDIO_DATA556SDIO_DATA657SDIO_DSL58SDIO_DATA759UART2_TXD60ADC361UART2_RTS62UART2_CTS63UART2_RXD64GPIO2065RESERVED66GPIO1467COEX_RXD68VDD_EXT69COEX_TXD70UART1_TXD71UART1_CTS72UART1_RXD73PCM_SYNC74UART1_RTS75PCM_CLK76PCM_DIN77CDC_RESET_N78PCM_DOUT79I2C1_SCL80I2C1_SDA81MCLK82RESERVED83USB_BOOT84USB_VBUS85USB_DP86GND87USB_DM88USB_SS_RX_M89RESERVED90USB_SS_RX_P91USB_SS_TX_M92GND93USB_SS_TX_P94SGMII_TX_P95DR_SYNC96SGMII_TX_M97SGMII_RX_P98GND99SGMII_RX_M100WAKEUP_IN101GPIO18102WAKEUP_OUT103SPI2_CLK104GPIO21105SPI2_CS106SPI2_MISO107DBG_TXD108SPI2_MOSI109VBAT_RF110DBG_RXD111VBAT_RF112VBAT_RF113ADC2114VBAT_RF115GND116GPIO5117GND118GND119RESERVED120GND121GND122RESERVED123RESERVED124GND125GND126GND127GND128GND129GND130GND131GND132GPIO22133GND134GND135GND136GPIO23137GND138GND139RESERVED140GND141GND142RESERVED143RESERVED144GND145GND146GND147GND148GND149GND150GND151GND152RESERVED153GND154RESERVED155GND156GND157RESERVED158GND159GND160GND161RESERVED162GND163ADC4164GND165GND166ADC5167GND168GND169IMU_INT1170RESERVED171GND172GND173GND174GND175RESERVED176GND177GND178RESERVED179RESERVED180GND181IMU_PWR_EN182GND183GND184RESERVED185GND186GND187IMU_INT2188RESERVED189GND190RESERVED191GND192GND193RESERVED194GND195GND196RESERVED197RESERVED198GND199GND200RESERVED201GND202GND203GND204RESERVED205RESERVED206GND207RESERVED208GND209GND210SPI1_MOSI211GND212GND213SPI1_CS214RESERVED215GND216SPI1_CLK217GND218GND219SPI1_MISO220GND221GND222GPIO15223SGMII_INT224SGMII_RST225GPIO16226RESERVED227RESERVED228GPIO17229RESERVED230GND231RESERVED232GND233GND234GND235VBAT_RF236VBAT_RF237GND238VBAT_RF239VBAT_RF240GND241VBAT_BB242VBAT_BB243GPIO6244VBAT_BB245ADC1246GPIO7247ADC0248RESERVED249GPIO8250USIM1_RST251USIM1_VDD252RESERVED253USIM1_CLK254USIM1_DATA255USIM1_DET256USIM2_VDD257USIM2_DATA258USIM2_DET259USIM2_CLK260USIM2_RST261I2S_DOUT262I2S_CLK263I2S_DIN264I2C2_SDA265I2S_WS266SPK1_N267I2C2_SCL268SPK1_P269SPK2_P270SPK2_N271SGMII_MDIO_DATA272SGMII_MDIO_CLK307GND308GND309GND310GND311GND312GND313GND314GND315GND316GND317GND318GND319GND320GND321GND322GND323GND324GND325GND326GND327GND328GND329GND330GND331GND332GND333GND334GND335GND336GND337GND338GND339GND340GND341GND342GND343GND344GND345GND346GND347GND348GND349GND350GND351GND352GND353GND354GND355GND356GND357GND358GND359GND360GND361GND362GND363GND364GND365GND366GND367GND368GND369GND370GND371GND372GND373GND374GND375GND376GND377GND378GND379GND380GND381GND382GND383GND384GND385GND386GND387GND388GND389GND390GND391GND392GND393GND394GND395GND396GND273RESERVED274RESERVED275SPI3_MISO276SPI3_CLK277SPI3_MOSI278SPI3_CS279RESERVED280GPIO11281RESERVED282RESERVED283GPIO10284GPIO12285RESERVED286RESERVED287RESERVED288RESERVED289GPIO13290RESERVED291RESERVED292RESERVED293RESERVED294RESERVED295GPIO1296GPIO2297GPIO3298GPIO4299RESERVED300RESERVED301RESERVED302RESERVED303RESERVED304RESERVED305RESERVED306RESERVED397GND398GND399GND400GND401GND402GND403RESERVED404GND407GND408GND409GND410GND411UART3_RXD412UART3_TXD413GND414ANT_MAIN415GND416ANT_DRX417GND418ANT_MIMO3419GND420ANT_MIMO4421GND422RESERVED423GND424RESERVED425GND426ANT_GNSS427GND428GPIO24Audio PinsSGMII Pins Automotive Module Series 2.5. Pin Description The following table shows the DC characteristics and pin descriptions. DC characteristics include power domain, rate current, etc. Table 5: I/O Parameters Definition Type AI AO AIO DI DO DIO OD PI PO Description Analog Input Analog Output Analog Input/Output Digital Input Digital Output Digital Input/Output Open Drain Power Input Power Output Table 6: Pin Description Power Supply Pin Name VBAT_BB VBAT_RF Pin No. 241, 242, 244 109, 111, 112, 114, 235, 236, 238, 239 I/O Description DC Characteristics Comment PI Power supply for the modules BB part PI Power supply for the modules RF part Vmax = 4.3 V Vmin = 3.3 V Vnom = 3.8 V It must be provided with sufficient current up to 1.5 A. It must be provided with sufficient current up to 2.0 A. AG568N_Series_QuecOpen_Hardware_Design 26 / 135 Automotive Module Series VDD_EXT 68 PO Provide 1.8 V for external circuits Vnom = 1.8 V Iomax = 50 mA Power supply only for external pull up circuits. It is recommended to reserve test points. GND 12, 18, 26, 33, 42, 86, 92, 98, 115, 117, 118, 120, 121, 124131, 133135, 137, 138, 140, 141, 144151, 153, 155, 156, 158, 159, 160, 162, 164, 165, 167, 168, 171174, 176, 177, 180, 182, 183, 185, 186, 189, 191, 192, 194, 195, 198, 199, 201, 202, 203, 206, 208, 209, 211, 212, 215, 217, 218, 220, 221, 230, 232, 233, 234, 237, 240, 307 402, 404, 407410, 413, 415, 417, 419, 421, 423, 425, 427 Turn On/Off Pin Name Pin No. I/O Description DC Characteristics Comment PWRKEY 7 DI Turn on/off the module RESET_N 8 DI Reset the module VIHmax = 1.98 V VIHmin = 1.45 V VILmax = 0.3 V Internally pulled up to 1.8 V. Active low. Internally pulled up to 1.8 V. Active low. It is recommended to reserve test points. USB Interface Pin Name Pin No. I/O Description DC Characteristics Comment USB_VBUS 84 DI Turn-on/

USB connection detect Vmax = 21 V Vmin = 4.2 V Vnom = 5.0 V USB_DP 85 AIO USB_DM 87 AIO USB_SS_ TX_P USB_SS_ TX_M USB_SS_ RX_P 93 AO 91 AO 90 AI USB 2.0 differential data

(+) USB 2.0 differential data

(-) USB 3.1 SuperSpeed transmit (+) USB 3.1 SuperSpeed transmit (-) USB 3.1 SuperSpeed receive (+) USB_SS_ 88 AI USB 3.1 SuperSpeed It is recommended to keep it open before the module is powered on. Test points must be reserved. Require differential impedance of 90 . Test points must be reserved. Require differential impedance of 90 . If these pins are unused, connect Rx pairs with GND directly and keep other pins open. AG568N_Series_QuecOpen_Hardware_Design 27 / 135 Automotive Module Series RX_M receive (-)

(U)SIM Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment USIM1_VDD 251 PO

(U)SIM1 card power supply Either 1.8/3.0 V is supported by the module automatically. USIM1_ DATA 254 DIO

(U)SIM1 card data For 1.8 V (U)SIM:

VILmax = 0.27 V VIHmin = 1.4 V VOLmax = 0.27 V VOHmin = 1.4 V For 3.0 V (U)SIM:

VILmax = 0.4 V VIHmin = 2.6 V VOLmax = 0.4 V VOHmin = 2.6 V For 1.8 V (U)SIM:

VOLmax = 0.22 V VOHmin = 1.62 V If unused, keep it open. USIM1_CLK 253 DO

(U)SIM1 card clock For 3.0 V (U)SIM:

VOLmax = 0.4 V VOHmin = 2.7 V For 1.8 V (U)SIM:

VOLmax = 0.36 V VOHmin = 1.62 V USIM1_RST 250 DO

(U)SIM1 card reset USIM1_DET 255 DI

(U)SIM1 card hot-plug detect USIM2_VDD 256 PO

(U)SIM2 card power supply For 3.0 V (U)SIM:

VOLmax = 0.36 V VOHmin = 2.7 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V 1.8 V power domain. If unused, keep it open. Either 1.8/3.0 V is supported by the module automatically. USIM2_ DATA 257 DIO

(U)SIM2 card data For 1.8 V (U)SIM:

VILmax = 0.27 V VIHmin = 1.4 V If unused, keep these pins open. AG568N_Series_QuecOpen_Hardware_Design 28 / 135 Automotive Module Series VOLmax = 0.27 V VOHmin = 1.4 V For 3.0 V (U)SIM:

VILmax = 0.4 V VIHmin = 2.6 V VOLmax = 0.4 V VOHmin = 2.6 V For 1.8 V (U)SIM:

VOLmax = 0.22 V VOHmin = 1.62 V USIM2_CLK 259 DO

(U)SIM2 card clock For 3.0 V (U)SIM:

VOLmax = 0.4 V VOHmin = 2.7 V For 1.8 V (U)SIM:

VOLmax = 0.36 V VOHmin = 1.62 V USIM2_RST 260 DO

(U)SIM2 card reset USIM2_DET 258 DI

(U)SIM2 card hot-plug detect For 3.0 V (U)SIM:

VOLmax = 0.36 V VOHmin = 2.7 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V 1.8 V power domain. If unused, keep it open. UART1 (Main UART) Pin Name Pin No. I/O Description DC Characteristics Comment UART1_CTS 71 DO DTE clear to send signal from DCE VOLmax = 0.45 V VOHmin = 1.35 V UART1_RTS 74 DI DTE request to send signal to DCE UART1_RXD 72 DI UART1 receive UART1_TXD 70 DO UART1 transmit VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V Connect to DTEs CTS. 1.8 V power domain. If unused, keep these pins open. Connect to DTE's RTS. 1.8 V power domain. If unused, keep these pins open. 1.8 V power domain. If unused, keep these pins open. AG568N_Series_QuecOpen_Hardware_Design 29 / 135 Automotive Module Series UART2 (Bluetooth UART) Pin Name Pin No. I/O Description UART2_TXD 59 DO UART2 transmit UART2_RXD 63 DI UART2 receive UART2_RTS 61 DI DTE request to send signal from DCE DC Characteristics VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V UART2_CTS 62 DO DTE clear to send signal to DCE VOLmax = 0.45 V VOHmin = 1.35 V Comment 1.8 V power domain. If unused, keep these pins open. Connect to DTEs CTS. 1.8 V power domain. If unused, keep these pins open. Connect to DTEs CTS. 1.8 V power domain. If unused, keep these pins open. UART3 (V2X) UART3_RXD 411 DI UART3 receive UART3_TXD 412 DO UART3 transmit Debug UART Interface Pin Name Pin No. I/O Description DBG_RXD 110 DI Debug UART receive DBG_TXD 107 DO Debug UART transmit VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V Used for external V2X function by default. 1.8 V power domain. If unused, keep them open. DC Characteristics VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V Comment 1.8 V power domain. Test points must be reserved. I2C Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment I2C1_SCL 79 DO I2C serial clock VILmax = 0.63 V VIHmin = 1.17 V VOLmax = 0.36 V 1.8 V power domain. If unused, keep them open. Used for external AG568N_Series_QuecOpen_Hardware_Design 30 / 135 Automotive Module Series I2C1_SDA 80 DIO I2C serial data I2C2_SCL 267 DO I2C serial clock I2C2_SDA 264 DIO I2C serial data I2S Interface Pin Name Pin No. I/O Description I2S_WS 265 DIO I2S word select I2S_CLK 262 DIO I2S clock I2S_DIN 263 DI I2S data input audio codec IC. Reserve pull-up resistors and not mount by default. 1.8 V power domain. If unused, keep them open. Used for external IMU sensor. Reserve pull-up resistors and not mount by default. Comment 1.8 V power domain. If unused, keep these pins open. DC Characteristics VOLmax = 0.45 V VOHmin = 1.35V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V I2S_DOUT 261 DO I2S data output MCLK 81 DO Master clock output for codec VOLmax = 0.45 V VOHmin = 1.35 V CDC_ RESET_N PCM Interface 77 DO External codec reset Pin Name Pin No. I/O Description PCM_SYNC 73 DIO PCM data frame sync PCM_CLK 75 DIO PCM clock PCM_DIN 76 DI PCM data input Comment 1.8 V power domain. If unused, keep them open. DC Characteristics VOLmax = 0.45 V VOHmin = 1.35V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V AG568N_Series_QuecOpen_Hardware_Design 31 / 135 Automotive Module Series PCM_DOUT 78 DO PCM data output VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V PCIe Interface Pin Name PCIE_ REFCLK_P PCIE_ REFCLK_M Pin No. I/O Description DC Characteristics Comment 40 AIO PCIe reference clock (+) 38 AIO PCIe reference clock (-) PCIE_TX0_P 46 AO PCIe transmit 0 (+) PCIE_TX0_M 44 AO PCIe transmit 0 (-) PCIE_RX0_P 34 PCIE_RX0_M 32 AI AI PCIe receive 0 (+) PCIe receive 0 (-) PCIE_TX1_P 43 AO PCIe transmit 1 (+) PCIE_TX1_M 41 AO PCIe transmit 1 (-) PCIE_RX1_P 37 PCIE_RX1_M 35 AI AI PCIe receive 1 (+) PCIe receive 1 (-) PCIE_ CLKREQ_N 36 DIO PCIe clock request PCIE_RST_N 39 DO PCIe reset PCIE_ WAKE_N 30 DI PCIe wake up Compliant with PCIe revision 3.0 specification. Requires differential impedance of 85 . If unused, connect Rx pairs with GND directly and keep others open. 1.8 V power domain. If unused, keep these pins open. VOLmax = 0.45 V VOHmin = 1.35V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V SGMIl Interface Pin Name Pin No. I/O Description DC Characteristics Comment SGMII_RX_P 97 AI SGMII receive (+) Requires differential AG568N_Series_QuecOpen_Hardware_Design 32 / 135 Automotive Module Series SGMII_RX_M 99 AI SGMII receive (-) SGMII_TX_P 94 AO SGMII transmit (+) SGMII_TX_M 96 AO SGMII transmit (-) SGMII_INT 223 DI PHY interrupt output SGMII_RST 224 DO SGMII reset external PHY SGMII_ MDIO_DATA 271 DIO SGMII management data SGMII_ MDIO_CLK 272 DO SGMII management data clock RGMII Interface VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V VOLmax = 0.45 V VOHmin = 1.35V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V impedance of 100 . If unused, connect Rx pairs with GND directly and keep others open. 1.8 V power domain. If unused, keep them open. Pin Name RGMII_MD_ IO RGMII_MD_ CLK Pin No. I/O Description DC Characteristics Comment 10 DIO 11 DO RGMII management data RGMII management data clock RGMII_RX_0 13 DI RGMII receive data bit 0 RGMII_RX_1 14 DI RGMII receive data bit 1 RGMII_RX_2 16 DI RGMII receive data bit 2 RGMII_RX_3 17 DI RGMII receive data bit 3 RGMII_CTL_ RX RGMII_CK_ RX 15 DI RGMII receive control 19 DI RGMII receive clock RGMII_TX_0 20 DO RGMII transmit data bit 0 RGMII_TX_1 22 DO RGMII transmit data bit 1 RGMII_TX_2 23 DO RGMII transmit data bit 2 Single-ended impedance of 50 . 1.8 V power domain. If unused, keep these pins open. AG568N_Series_QuecOpen_Hardware_Design 33 / 135 Automotive Module Series RGMII_TX_3 25 DO RGMII transmit data bit 3 RGMII_CTL_ TX RGMII_CK_ TX 21 DO RGMII transmit control 24 DO RGMII transmit clock RGMII_INT 29 DI PHY interrupt output RGMII_RST 31 DO RGMII reset external PHY SDIO Interface Pin Name Pin No. I/O Description EMMC_RST 54 DO eMMC reset SDIO_DATA0 49 DIO SDIO data bit 0 SDIO_DATA1 50 DIO SDIO data bit 1 SDIO_DATA2 51 DIO SDIO data bit 2 SDIO_DATA3 52 DIO SDIO data bit 3 SDIO_DATA4 53 DIO SDIO data bit 4 SDIO_DATA5 55 DIO SDIO data bit 5 SDIO_DATA6 56 DIO SDIO data bit 6 SDIO_DATA7 58 DIO SDIO data bit 7 SDIO_CMD 48 DIO SDIO command SDIO_CLK 47 DO SDIO clock SDIO_DSL 57 DI SDIO data strobe VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V DC Characteristics VOLmax = 0.45 V VOHmin = 1.4 V VOLmax = 0.45 V VOHmin = 1.4V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.4 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V 1.8 V power domain. If unused, keep them open. Comment 1.8 V power domain. If unused, keep these pins open. RF Antenna Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment AG568N_Series_QuecOpen_Hardware_Design 34 / 135 Automotive Module Series ANT_GNSS 426 AI GNSS antenna interface ANT_MAIN 414 AIO Main antenna interface ANT_DRX 416 AIO ANT_MIMO3 418 AIO 12 ANT_MIMO4 420 AI Diversity antenna interface 4 4 MIMO antenna interface 4 4 MIMO antenna interface Single-ended impedance of 50 . Supports active antenna only. Single-ended impedance of 50 . SPI Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment SPI1_CS 213 DO SPI1 chip select SPI1_CLK 216 DO SPI1 clock SPI1_MOSI 210 DO SPI1 master-out slave-in SPI1_MISO 219 DI SPI1 master-in slave-out SPI2_CS 105 DO SPI2 chip select SPI2_CLK 103 DO SPI2 clock SPI2_MOSI 108 DO SPI2 master-out slave-in SPI2_MISO 106 DI SPI2 master-in slave-out SPI3_CS 278 DO SPI3 chip select SPI3_CLK 276 DO SPI3 clock SPI3_MOSI 277 DO SPI3 master-out slave-in SPI3_MISO 275 DI SPI3 master-in slave-out VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V 12 The I/O is AI on AG568N-EU/-ROW/-NA. Master mode only. 1.8 V power domain. If unused, keep them open. Master and slave mode. 1.8 V power domain. Used for external V2X function by default. If unused, keep them open. AG568N_Series_QuecOpen_Hardware_Design 35 / 135 Automotive Module Series VIHmax = 2.1 V ADC Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment ADC0 247 AI ADC1 245 AI ADC2 113 AI ADC3 60 AI ADC4 163 AI ADC5 166 AI General-purpose ADC interface General-purpose ADC interface General-purpose ADC interface General-purpose ADC interface General-purpose ADC interface General-purpose ADC interface Voltage range:

0.041.78 V Voltage range:

0.051.45 V If unused, connect them with ground. GPIO Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment GPIO1 295 DIO GPIO2 296 DIO GPIO3 297 DIO GPIO4 298 DIO GPIO5 116 DIO GPIO6 243 DIO GPIO7 246 DIO GPIO8 249 DIO GPIO9 9 DIO GPIO10 283 DIO General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output VOLmax = 0.45 V VOHmin = 1.4 V VILmin = -0.3 V VILmax = 0.58 V VIHmin = 1.27 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V 1.8 V power domain. If unused, keep these pins open. AG568N_Series_QuecOpen_Hardware_Design 36 / 135 Automotive Module Series GPIO11 280 DIO GPIO12 284 DIO GPIO13 289 DIO GPIO14 66 DIO General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output GPIO15 222 DIO General-purpose input/output GPIO16 225 DIO GPIO17 228 DIO GPIO18 101 DIO GPIO19 27 DIO GPIO20 64 DIO GPIO21 104 DIO GPIO22 132 DIO GPIO23 136 DIO GPIO24 428 DIO General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output Do not pull down this pin before powering on if the module does not need to enter Fast Meta mode. 1.8 V power domain. If unused, keep it open. 1.8 V power domain. If unused, keep these pins open. Used for external V2X function by default. 1.8 V power domain. If unused, keep these pins open. Coexistence Control Interface Pin Name Pin No. I/O Description COEX_RXD 67 DI LTE & WLAN/

Bluetooth coexistence receive DC Characteristics VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V Comment 1.8 V power domain. If unused, keep them open. AG568N_Series_QuecOpen_Hardware_Design 37 / 135 Automotive Module Series COEX_TXD 69 DO Analog Audio Interfaces LTE & WLAN/

Bluetooth coexistence transmit VOLmax = 0.45 V VOHmin = 1.35 V Pin Name Pin No. I/O Description DC Characteristics Comment MIC1_P MIC1_N MIC2_P MIC2_N MICBIAS 2 1 5 4 3 AI AI AI AI Microphone analog input 1 (+) Microphone analog input 1 (-) Microphone analog input 2 (+) Microphone analog input 2 (-) PO Bias voltage output for microphone SPK1_P 268 AO SPK1_N 266 AO SPK2_P 269 AO SPK2_N 270 AO Analog audio differential output 1 (+) Analog audio differential output 1 (-) Analog audio differential output 2 (+) Analog audio differential output 2 (-) AGND 6

Analog ground Other Interfaces Pin Name Pin No. I/O Description USB_BOOT 83 DI Force the module into emergency download mode DR_SYNC 95 DO Dead reckoning sync WAKEUP_ OUT WAKEUP_ IN 102 DO 100 DI Wakeup signal from the module External wakeup signal to the module IMU_INT1 169 DI IMU interrupt 1 The analog audio function is optional. It is not configured by default. DC Characteristics VILmin = -0.3 V VILmax = 0.3 V VIHmin = 1.2 V VIHmax = 3.5 V VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V Comment 1.8/3.3 V power domain. It is recommended to reserve test points. 1.8 V power domain. If unused, keep these pins open. AG568N_Series_QuecOpen_Hardware_Design 38 / 135 Automotive Module Series IMU_INT2 187 DI IMU interrupt 2 VIHmax = 2.1 V IMU_PWR_ EN 181 DO IMU power enable control VOLmax = 0.45 V VOHmin = 1.35 V RESERVED Pins Pin Name Pin No. Comment RESERVED 28, 45, 65, 82, 89, 119, 122, 123, 139, 142, 143, 152, 154, 157, 161, 170, 175, 178, 179, 184, 188, 190, 193, 196, 197, 200, 204, 205, 207, 214, 226, 227, 229, 231, 248, 252, 273, 274, 279, 281, 282, 285288, 290294, 299306, 403, 422, 424 2.6. EVB Kit To help you develop applications with the module, Quectel supplies an evaluation board (V2X&5G EVB) with accessories to control or test the module. For more details, see document [1]. AG568N_Series_QuecOpen_Hardware_Design 39 / 135 Automotive Module Series 3 Operating Characteristics 3.1. Operating Modes The table below outlines operating modes of the module. Table 7: Overview of Operating Modes Mode Details Full Functionality Mode Idle The module remains registered on the network, and is ready to send and receive data. In this mode, the software is active. Voice/Data The module is connected to network. Its power consumption varies with the network setting and data transfer rate. Airplane Mode AT+CFUN=4 or device management related API function can set the module to airplane mode where the RF function is invalid. Minimum Functionality Mode AT+CFUN=0 or device management related API function can set the module to a minimum functionality mode without removing the power supply. In this mode, both RF function and (U)SIM card are invalid. Sleep Mode Power Down Mode The module retains the ability to receive paging message, SMS, voice call and TCP/UDP data from the network normally. In this mode, the power consumption of the module is reduced to a very low level. The modules power supply is cut off by its power management unit. In this mode, the software is inactive, the serial interfaces are inaccessible, while the operating voltage (connected to VBAT_RF and VBAT_BB) remains applied. NOTE See document [2] for details of device management API functions, and document [3] for details of AT+CFUN. AG568N_Series_QuecOpen_Hardware_Design 40 / 135 Automotive Module Series 3.2. Sleep Mode The module is able to reduce the power consumption to a minimum value during the sleep mode. This chapter mainly introduces the way to enter or exit from sleep mode. The diagram below illustrates the power consumption of the module during the sleep mode. See document [4] for more details about the low power mode of the module. Figure 3: Sleep Mode Power Consumption Diagram NOTE The DRX cycle values are broadcasted by the wireless network. 3.2.1.1. USB Application Scenario (without USB Suspend Function) If the host does not support USB suspend function, USB_VBUS should be connected with an external control circuit to set the module to sleep mode. In this case, the following three preconditions can make the module enter the sleep mode:

Use sleep and wakeup related API functions to enable the sleep mode. Ensure that all pins configured to interrupt the wake-up function are in the non-wakeup state. Disconnect USB_VBUS. The following figure shows the connection between the module and the host. AG568N_Series_QuecOpen_Hardware_Design 41 / 135 CurrentRun TimeDRX OFF ON OFF ON ON OFF OFFON OFF Automotive Module Series Figure 4: Sleep-Mode Application without Suspend Function NOTE 1. Pay attention to the level match of the connection signals between the module and the external MCU. 2. USB_VBUS pin can turn on the module when it is turned off. 3.3. Airplane Mode When the module enters airplane mode, the RF function does not work, and all AT commands and API functions correlative with RF function will be inaccessible. AT command:

The mode can be set via AT+CFUN=<fun>. For more details about this command, see document [3]. The parameter <fun> of AT+CFUN indicates the modules functionality levels, as shown below. AT+CFUN=0: Minimum functionality mode. (Both (U)SIM and RF functions are disabled.) AT+CFUN=1: Full functionality mode (by default). AT+CFUN=4: Airplane mode. (RF function is disabled.) API functions:

The mode can be set via device management related API functions. For more details about device management API functions, see document [2]. AG568N_Series_QuecOpen_Hardware_Design 42 / 135 USB InterfaceVDDUSB InterfaceModuleHostGNDGNDUSB_VBUSGPIOEINTPower SwitchGPIO Automotive Module Series NOTE The execution of AT+CFUN or related API functions will not affect GNSS function. 3.4. Power Supply 3.4.1. Power Supply Pins The module provides eleven VBAT pins dedicated to the connection with the external power supply. There are two separate voltage domains for VBAT. Eight VBAT_RF pins for RF part. Three VBAT_BB pins for BB part. Table 8: Pin Definition of Power Supply Pin Name Pin No. I/O Description Comment VBAT_BB 241, 242, 244 PI Power supply for the modules BB part It must be provided with sufficient current up to 1.5 A. VBAT_RF 109, 111, 112, 114, 235, 236, 238, 239 PI Power supply for the modules RF part It must be provided with sufficient current up to 2.0 A. GND 12, 18, 26, 33, 42, 86, 92, 98, 115, 117, 118, 120, 121, 124131, 133135, 137, 138, 140, 141, 144151, 153, 155, 156, 158, 159, 160, 162, 164, 165, 167, 168, 171174, 176, 177, 180, 182, 183, 185, 186, 189, 191, 192, 194, 195, 198, 199, 201, 202, 203, 206, 208, 209, 211, 212, 215, 217, 218, 220, 221, 230, 232, 233, 234, 237, 240, 307 402, 404, 407410, 413, 415, 417, 419, 421, 423, 425, 427 3.4.2. Reference Design for Power Supply The performance of the module largely depends on the power source. The power supply of the module should be able to provide sufficient current of 3.5 A at least. VBAT_BB needs at least 1.5 A and VBAT_RF needs at least 2 A. If the voltage drop between the input and output is not too high, it is applicable to use an LDO to supply power for the module. If there is a big voltage difference between the input source and the desired output

(VBAT), a buck converter is preferred to be used as the power supply. If the input power supply is not within the power supply range of the module, it is necessary to add a power conversion circuit. AG568N_Series_QuecOpen_Hardware_Design 43 / 135 Automotive Module Series The following figure shows a reference design for DC +12 V/+24 V input power source. The designed output for the power supply is 3.8 V, and the maximum rated current is 5 A. Figure 5: Reference Design of Power Supply NOTE To avoid corrupting the data in the internal flash, do not switch off the power supply when the module works normally. Only after shutting down the module with PWRKEY or AT command can you cut off the power supply. 3.4.3. Voltage Stability Requirements The power supply range of the module is from 3.3 V to 4.3 V. Please make sure the input voltage will never drop below 3.3 V. Figure 6: Power Supply Limits During Burst Transmission AG568N_Series_QuecOpen_Hardware_Design 44 / 135 2413678243KNM100K10 pF100 pF100 nF10 F3V8_EN100 nFBOOTVINENRT/CLKSWGNDCOMPFBGNDTPS54560B-Q17.2H9547 F47 F18.7K7.5 nF6.8 pF75K20KVCC_3V847 F+12V_INPower Supply (V)Burst TransmissionRippleDropBurst TransmissionLoad (A) Automotive Module Series To decrease the voltage drop, bypass capacitors of about 100 F with low ESR should be used for VBAT_BB and VBAT_RF respectively, and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to their ultra-low ESR. It is recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC array, and place these capacitors close to VBAT pins. The main power supply from an external application must be a single voltage source and can be expanded to two sub paths with the star structure. The width of VBAT_BB trace should be not less than 1.5 mm. The width of VBAT_RF trace should be not less than 2 mm. In principle, the longer the VBAT trace is, the wider it should be. In addition, to get a stable power source, it is necessary to add two high-power TVS components at the front end of the power supply. Also, the TVS should be placed as close to the VBAT pins as possible. Figure 7: Star Structure of the Power Supply 3.5. Turn On 3.5.1. Turn On with PWRKEY Table 9: Pin Definition of PWRKEY Pin Name Pin No. I/O Description Comment PWRKEY 7 DI Turn on/off the module Internally pulled up to 1.8 V. Active low. When the module is in turn-off mode, it can be turned on by driving the PWRKEY low for at least 500 ms. It is recommended to use an open drain/collector driver to control the PWRKEY. AG568N_Series_QuecOpen_Hardware_Design 45 / 135 ModuleVBAT_RFVBAT_BBVBAT_RFC1C6C7C810 pF++C2C6C3C4D1100 nF33 pF10 pF33 pF100 nFFB1FB2100 F100 FBLM21PG600SH1DBLM21PG600SH1DVBAT_BBD2 Automotive Module Series Figure 8: Turn On the Module Using Driving Circuit Another way to control the PWRKEY is by using a button directly. When pressing the button, an electrostatic strike may generate from finger. Therefore, a TVS component shall be placed near the button for ESD protection. Figure 9: Turn On the Module Using a Button The power-up timing is illustrated in the following figure. AG568N_Series_QuecOpen_Hardware_Design 46 / 135 PWRKEY 500 msMCUGPIOModuleTurn on pulse4.7K47KQ1PWRKEYModuleS1Close to S1TVS1KTurn-on pulseR1 Automotive Module Series Figure 10: Power-up Timing

. NOTE 1. Ensure that VBAT is stable for at least 30 ms before pulling down the PWRKEY. 2. 3. Do not connect PWRKEY to GND all the time. Pull up PWRKEY to a high level after the module is If USB_VBUS is connected, the module will start automatically after power-on. turned on. It is recommended to use an external OD/OC circuit to control the PWRKEY. 4. 3.6. Turn Off The following procedures can be used to turn off the module normally. 3.6.1. Turn Off with PWRKEY Driving PWRKEY low for at least 2 s, the module will execute power-down procedure after the PWRKEY is released. AG568N_Series_QuecOpen_Hardware_Design 47 / 135 VIL 0.3 VVIH 1.45 VVBATPWRKEYRESET_NNOTE 1InactiveActiveUSBVDD_EXT 60 ms 500 msNOTE 2 35 s Automotive Module Series Figure 11: Power-down Timing 3.6.2. Turn Off with Linux Commands The module can be turned off safely with Linux commands, such as shutdown and poweroff, which are similar to turning off the module via the PWRKEY pin. NOTE 1. To avoid corrupting the data in the internal flash, do not switch off the power supply when the module works normally. Only after the module is turned off by PWRKEY or Linux commands, the power supply can be cut off. 2. When turning off the module with Linux commands, keep PWRKEY at a high level after the execution of the commands. Otherwise, the module will be turned on again after successfully turn-

off. 3. Ensure that there is no large capacitance on PWRKEY pin. 4. Do not pull down PWRKEY to GND all the time ( 8 s). Driving PWRKEY high after the module executes power-down procedure. 3.7. Reset The module can be reset by driving the RESET_N low for 250550 ms and then releasing it. As the RESET_N pin is sensitive to interference, the routing trace is recommended to be as short as possible and totally ground surrounded. AG568N_Series_QuecOpen_Hardware_Design 48 / 135 VBATPWRKEY 15 s 2 sRunningPower-down procedureOFFModuleStatusVDD_EXT Automotive Module Series Table 10: Pin Definition of RESET_N Pin Name Pin No. I/O Description Comment RESET_N 8 DI Reset the module Internally pulled up to 1.8 V. Active low. It is recommended to reserve test points. The recommended circuit is equal to the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET_N. Figure 12: Reference Circuit of RESET_N with Driving Circuit Figure 13: Reference Circuit of RESET_N with Button AG568N_Series_QuecOpen_Hardware_Design 49 / 135 RESET_N250550 msMCUGPIOModuleReset pulse4.7K47KQ1RESET_NModuleS2Close to S2TVS1KReset pulseR1 Automotive Module Series Figure 14: Reset Timing NOTE 1. RESET_N should only be used when turning off the module by Linux commands and PWRKEY pin all failed. 2. Ensure that there is no large capacitance on RESET_N pin. AG568N_Series_QuecOpen_Hardware_Design 50 / 135 VIL 0.3 VVIH 1.45 VVBATRESET_N250550 msResettingModule StatusRunningRestart 250 ms Automotive Module Series 4 Application Interfaces 4.1. USB Interface The module provides one integrated Universal Serial Bus (USB) interface. The USB interface complies with the USB 3.1 and USB 2.0 specifications. USB 3.1 and USB 2.0 support data communication with external AP, and cannot be used simultaneously since they share the same controller. The USB interface supports SuperSpeed (5 Gbps) for USB 3.1, high-speed (480 Mbps), full-speed (12 Mbps) and low-speed (1.5 Mbps) for USB 2.0. It can be used for AT command communication, data transmission, software debugging, firmware upgrade, GNSS NMEA sentences output. Pin definition of the USB interface is here as follows. Table 11: Pin Definition of USB Interface Pin Name Pin No. I/O Description Comment USB_VBUS 84 DI Turn-on/USB connection detect USB_DP USB_DM 85 87 AIO USB 2.0 differential data (+) AIO USB 2.0 differential data (-) USB_SS_TX_P 93 AO USB 3.1 SuperSpeed transmit (+) USB_SS_TX_M 91 AO USB 3.1 SuperSpeed transmit (-) USB_SS_RX_P 90 AI USB 3.1 SuperSpeed receive (+) USB_SS_RX_M 88 AI USB 3.1 SuperSpeed receive (-) It is recommended to keep it open before the module is powered on. Test points must be reserved. Require differential impedance of 90 . Test points must be reserved. Require differential impedance of 90 . If these pins are unused, connect Rx pairs with GND directly and keep other pins open. AG568N_Series_QuecOpen_Hardware_Design 51 / 135 Automotive Module Series Test points of USB 2.0 interface must be reserved, which can be used for debugging and firmware upgrading in your designs. The following figure shows a reference circuit of USB interface. Figure 15: Reference Circuit of USB Application For USB 2.0 application, a common mode choke L1 is recommended to be added in series between the module and your MCU to suppress EMI spurious transmission. Meanwhile, the 0 resistors (R1 and R2) should be added in series between the module and the test points to facilitate debugging, and the resistors are not mounted by default. To ensure the integrity of USB data trace signal, L1, R1 and R2 components must be placed close to the module, and also resistors R1 and R2 should be placed close to each other. The extra trace stubs must be as short as possible. For USB 3.1 application, place C1 and C2 near the module, and place C3 and C4 near the other device. The extra stubs of trace must be as short as possible. As USB_VBUS is an input signal for turn-on condition, it is suggested to keep it open before the module is turned on. To meet USB 2.0 and USB 3.1 specifications, the following principles of USB interface should be complied with. It is important to route the USB signal traces as differential pairs with ground surrounded. The impedance of USB differential trace is 90 . For USB 2.0 signal traces, length matching of each differential data pair (Tx/Rx) should be less than 60 mil. For USB 3.1 signal traces, length matching of each differential data pair (Tx/Rx) should be less than 5 mil. AG568N_Series_QuecOpen_Hardware_Design 52 / 135 USB_DPUSB_DMGNDUSB_DPUSB_DMGNDClose to ModuleR1R2Test PointsESD ArrayNM_0RNM_0RMinimize these stubsModuleUSB_VBUSUSB_VBUSUSB_SS_TX_PUSB_SS_TX_MUSB_SS_RX_PUSB_SS_RX_MC1C3C4100 nF100 nF100 nF100 nFUSB_SS_RX_PUSB_SS_RX_MUSB_SS_TX_PUSB_SS_TX_MC20RL1R3USB Connector Automotive Module Series Do not route signal traces under crystals, oscillators, magnetic devices, PCIe and RF signal traces. It is important to route the USB differential traces in PCB inner-layer, and surround the traces with ground on that layer and ground planes above and below. Junction capacitance of the ESD protection device might cause influences on USB data traces, so pay attention to the selection of the device. Typically, the stray capacitance should be less than 3.0 pF for USB 2.0, and less than 0.5 pF for USB 3.1. If possible, reserve a 0 resistor on USB_DP and USB_DM traces respectively. For more details about the USB specifications, visit http://www.usb.org/home. NOTE 1. The module supports USB host mode and slave mode, but works in slave mode only by default. 2. The high-speed PHY and SuperSpeed PHY share the same controller inside baseband chipset, so USB 2.0 and USB 3.1 cannot be used simultaneously. 4.2. UART Interfaces The module provides four UART interfaces: UART1, UART2, UART3 and Debug UART. The module serves as DCE (Data Communication Equipment), which is connected in the traditional DCE-DTE (Data Terminal Equipment) mode. The features of UART interfaces are shown in the following table. Table 12: Features of UART Interfaces UART Types Supported Baud Rates

(bps) Default Baud Rates (bps) Functions UART1

(Main UART interface) UART2

(Bluetooth UART Interface) UART3

(V2X Interface) Data transmission AT command 115200 communication 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 9600 RTS and CTS hardware flow control Data transmission for Bluetooth function RTS and CTS hardware flow control 9600 External V2X function Debug UART Interface 115200 115200 Linux console Log output AG568N_Series_QuecOpen_Hardware_Design 53 / 135 Automotive Module Series Pin definition of the UART interface is here as follows:

Table 13: Pin Definition of UART Interfaces Pin Name Pin No. I/O Description Comment UART1_CTS 71 DO DTE clear to send signal from DCE UART1_RTS 74 DI DTE request to send signal to DCE UART1_RXD 72 DI UART1 receive UART1_TXD 70 DO UART1 transmit UART2_TXD 59 DO UART2 transmit UART2_RXD 63 DI UART2 receive UART2_RTS 61 DI DTE request to send signal from DCE UART2_CTS 62 DO DTE clear to send signal to DCE UART3_RXD 411 DI UART3 receive UART3_TXD 412 DO UART3 transmit DBG_RXD 110 DI Debug UART receive DBG_TXD 107 DO Debug UART transmit Connect to DTEs CTS. 1.8 V power domain. If unused, keep these pins open. Connect to DTE's RTS. 1.8 V power domain. If unused, keep these pins open. 1.8 V power domain. If unused, keep these pins open. Connect to DTE's RTS. 1.8 V power domain. If unused, keep these pins open. Connect to DTEs CTS. 1.8 V power domain. If unused, keep these pins open. Used for external V2X function by default. 1.8 V power domain. If unused, keep them open. 1.8 V power domain. Test points must be reserved. The module provides 1.8 V UART interfaces. A voltage-level translator should be used if the application is equipped with a 3.3 V UART interface. The following figure shows a reference design. AG568N_Series_QuecOpen_Hardware_Design 54 / 135 Automotive Module Series Figure 16: Reference Circuit with Translator Chip Another example with transistor circuit is shown as below. For the design of circuits shown in dotted lines, see that shown in solid lines, but pay attention to the direction of connection. Figure 17: Reference Circuit with Transistor Circuit (UART1) The following figure illustrates the reference design for UART2 interface connection between different modules. AG568N_Series_QuecOpen_Hardware_Design 55 / 135 VCCAVCCBOEA1A2A3A4NCGNDB1B2B3B4NCVDD_1V8CTSRTSRXDTXD0.1 F0.1 FCTS_MCURTS_MCURXD_MCUTXD_MCUVDD_MCUTranslatorMCU/ARMTXDRXDVDD_1V810KVCC_MCU4.7K10KVDD_1V8UART1_TXDUART1_RXDUART1_RTSUART1_CTSRTSCTSGNDModuleVDD_1V84.7KGND1 nF1 nF Automotive Module Series Figure 18: UART Interface Connection (UART2) NOTE 1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps. 2. If hardware flow control function is intended to be used, then CTS and RTS should also be designed with the level-shifting circuit. 3. Please note that the modules CTS is connected to the hosts CTS, and the modules RTS is connected to the hosts RTS. 4.3. (U)SIM Interfaces The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Either 1.8 V or 3.0 V (U)SIM card is supported, and Dual SIM Dual Standby (DSDS) 13 function is supported. Table 14: Pin Definition of (U)SIM Interface Pin Name Pin No. I/O Description Comment USIM1_VDD 251 PO

(U)SIM1 card power supply Either 1.8/3.0 V is supported by the module automatically. USIM1_DATA 254 DIO

(U)SIM1 card data USIM1_CLK 253 DO

(U)SIM1 card clock USIM1_RST 250 DO

(U)SIM1 card reset USIM1_DET 255 DI

(U)SIM1 card hot-plug detect If unused, keep these pins open. 1.8 V power domain. If unused, keep it open. 13 DSDS function is optional. AG568N_Series_QuecOpen_Hardware_Design 56 / 135 Wi-Fi/Bluetooth ModuleAG568N SeriesBT_TXDBT_RXDBT_RTSBT_CTSUART2_RXDUART2_TXDUART2_RTSUART2_CTS Automotive Module Series USIM2_VDD 256 PO

(U)SIM2 card power supply Either 1.8/3.0 V is supported by the module automatically. USIM2_DATA 257 DIO

(U)SIM2 card data USIM2_CLK 259 DO

(U)SIM2 card clock USIM2_RST 260 DO

(U)SIM2 card reset USIM2_DET 258 DI

(U)SIM2 card hot-plug detect If unused, keep these pins open. 1.8 V power domain. If unused, keep it open. The module supports (U)SIM card hot-plug via the USIM_DET pin, and both high and low level detection are supported. The function is enabled by default. The following figure illustrates a reference design for (U)SIM card interface with an 8-pin (U)SIM card connector. Figure 19: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, keep USIM_DET pin unconnected. A reference circuit for

(U)SIM card interface with a 6-pin (U)SIM card connector is illustrated in the following figure. AG568N_Series_QuecOpen_Hardware_Design 57 / 135 ModuleUSIM_VDDUSIM_RSTUSIM_CLKUSIM_DATAUSIM_DET0R0R0RVDD_EXT470K1 F(U)SIM Card ConnectorGNDGNDVCCRSTCLKIOVPPGNDUSIM_VDDNM33 pF33 pF33 pFCD1CD2TVS array Automotive Module Series Figure 20: Reference Circuit of a 6-Pin (U)SIM Card Connector To enhance the reliability and availability of the (U)SIM card in applications, follow the criteria below in

(U)SIM circuit design. Place the (U)SIM card connector as close to the module as possible. Keep the trace length as short as possible, at most 200 mm. Keep (U)SIM card signal traces away from RF and power supply traces. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with ground surrounded. For better ESD protection, it is recommended to add a TVS array with a parasitic capacitance not exceeding 10 pF. The 0 resistors should be added in series between the module and the (U)SIM card connector to suppress EMI spurious transmission and enhance ESD protection. The 33 pF capacitors are used for filtering out RF interference. Please note that the (U)SIM peripheral circuit should be close to the (U)SIM card connector. The pull-up resistor on USIM_DATA trace improves anti-jamming capability when long layout trace and sensitive occasions are applied, and should be placed close to the (U)SIM card connector. It should be not mounted by default. Reserve 1 F capacitor on the power rails of (U)SIM interface with shunt connection and the capacitor should be placed close to (U)SIM connector. NOTE The load capacitance of (U)SIM interfaces will affect the rising and falling time of the data exchange. AG568N_Series_QuecOpen_Hardware_Design 58 / 135 ModuleUSIM_VDDUSIM_GNDUSIM_RSTUSIM_CLKUSIM_DATA0R0R0R1 F(U)SIM Card ConnectorGND33 pF33 pF33 pFVCCRSTCLKIOVPPGNDGNDNMUSIM_VDDTVS array Automotive Module Series 4.4. I2C Interfaces The module provides two I2C interfaces. The I2C interfaces have been pulled to 1.8 V inside. It is recommended to reserve pull-up resistors and not mount by default. Table 15: Pin Definition of I2C Interfaces Pin Name Pin No. I/O Description Comment I2C1_SCL 79 DO I2C serial clock I2C1_SDA 80 DIO I2C serial data I2C2_SCL 267 DO I2C serial clock I2C2_SDA 264 DIO I2C serial data 1.8 V power domain. If unused, keep them open. Used for external audio codec IC. Reserve pull-up resistors and not mount by default. 1.8 V power domain. If unused, keep them open. Used for external IMU sensor. Reserve pull-up resistors and not mount by default. 4.5. I2S Interface The module provides one I2S interface, supports 8192 kHz sampling rates. Table 16: Pin Definition of I2S Interface Pin Name Pin No. I/O Description Comment I2S_WS I2S_DIN I2S_DOUT I2S_CLK 265 263 261 262 DIO I2S word select DI I2S data input DO I2S data output DIO I2S clock MCLK 81 DO Master clock output for codec CDC_RESET_N 77 DO External codec reset 1.8 V power domain. If unused, keep these pins open. AG568N_Series_QuecOpen_Hardware_Design 59 / 135 Automotive Module Series The following figure shows a reference design of I2S interface with an external codec IC. Figure 21: I2S and I2C1 Application with External Audio Codec NOTE The module works as a master device pertaining to I2C interface. 4.6. PCM Interface The module provides one Pulse Code Modulation (PCM) digital interface for Bluetooth audio transmission by default. The interface supports master and slave modes. Table 17: Pin Definition of PCM Interface Pin Name Pin No. I/O Description Comment PCM_SYNC 73 DIO PCM data frame sync PCM_CLK PCM_DIN 75 76 DIO PCM clock DI PCM data input 1.8 V power domain. If unused, keep these pins open. PCM_DOUT 78 DO PCM data output AG568N_Series_QuecOpen_Hardware_Design 60 / 135 I2S_DINI2S_DOUTI2S_CLKI2S_WSI2C1_SCLI2C1_SDAModule1.8 VNMNMWCLKBCLKDINDOUTSCLSDABIASMICBIASINPINNLOUTPLOUTNCodecMCLKMCLKCDC_RESET_NRESET Automotive Module Series 4.7. WLAN and Bluetooth Application Interfaces The module provides one PCIe interface for WLAN function (see Chapter 4.17 for more details), and one Bluetooth UART and one PCM interface for Bluetooth function (see Chapter 4.2 and Chapter 4.6 for more details). The following table shows the pin definition of coexistence control interface. Table 18: Pin Definition of Coexistence Control Interface Pin Name Pin No. I/O Description Comment COEX_RXD 67 DI COEX_TXD 69 DO LTE & WLAN/Bluetooth coexistence receive LTE & WLAN/Bluetooth coexistence transmit 1.8 V power domain. If unused, keep them open. The following figure shows a reference design of interfaces for WLAN and Bluetooth applications. AG568N_Series_QuecOpen_Hardware_Design 61 / 135 Automotive Module Series Figure 22: WLAN & Bluetooth Application Interfaces Connection Block Diagram 4.8. Analog Audio Interfaces (Optional) The module is designed with a built-in audio codec to enable analog audio function. The analog audio interfaces are optional. If you need this function, please contact Quectel Technical Support. AG568N_Series_QuecOpen_Hardware_Design 62 / 135 PCIE_TX0_MPCIE_TX0_PPCIE_RST_NPCIE_RX0_PCOEX_ RXD UART2_TXDUART2_CTSPCM_SYNCModulePCIE_REFCLK_MPCIE_REFCLK_PPCIE_WAKE_NPCIE_CLKREQ_NPCM_CLKPCIE_RX0_MCOEX_ TXD UART2_RXDUART2_RTSPCM_DINPCM_DOUTGPIOGPIOPCIE_CLKREQ_NWLAN & Bluetooth PHYPCIE_WAKEPCIE_RSTPCIE_REFCLK_PPCIE_REFCLK_MPCIE_RX_MPCIE_RX_PPCIE_TX_PPCIE_TX_MCOEX_UART_ RXD COEX_UART_ TXD BT_UART_TXDBT_UART_RXDBT_UART_CTSBT_UART_RTSPCM_CLKPCM_SYNCPCM_INPCM_OUTWLAN_ENBT_ENR1100KR2100KVDD_EXTC1220 nFC2220 nFC3220 nFC4220 nFR449.9 RR5 49.9 RR3NM Automotive Module Series Table 19: Pin Definition of Analog Audio Interfaces Pin Name Pin No. I/O Description Comment MIC1_P MIC1_N MIC2_P MIC2_N MICBIAS SPK1_P SPK1_N SPK2_P SPK2_N AGND 2 1 5 4 3 268 266 269 270 6 AI AI AI AI Microphone analog input 1 (+) Microphone analog input 1 (-) Microphone analog input 2 (+) Microphone analog input 2 (-) PO Bias voltage output for microphone AO Analog audio differential output 1 (+) AO Analog audio differential output 1 (-) AO Analog audio differential output 2 (+) AO Analog audio differential output 2 (-)

Analog ground The analog audio function is optional. It is not configured by default. 4.9. GPIOs The module provides 24 GPIOs for your design, which all support wake-up interrupt. Table 20: Pin Description of GPIO Interfaces Pin Name Pin No. I/O Description Comment GPIO1 295 DIO General-purpose input/output GPIO2 296 DIO General-purpose input/output GPIO3 297 DIO General-purpose input/output GPIO4 298 DIO General-purpose input/output GPIO5 116 DIO General-purpose input/output GPIO6 243 DIO General-purpose input/output 1.8 V power domain. If unused, keep these pins open. AG568N_Series_QuecOpen_Hardware_Design 63 / 135 Automotive Module Series GPIO7 246 DIO General-purpose input/output GPIO8 249 DIO General-purpose input/output GPIO9 9 DIO General-purpose input/output GPIO10 283 DIO General-purpose input/output GPIO11 280 DIO General-purpose input/output GPIO12 284 DIO General-purpose input/output GPIO13 289 DIO General-purpose input/output GPIO14 66 DIO General-purpose input/output GPIO15 222 DIO General-purpose input/output GPIO16 225 DIO General-purpose input/output GPIO17 228 DIO General-purpose input/output GPIO18 101 DIO General-purpose input/output GPIO19 27 DIO General-purpose input/output GPIO20 64 DIO General-purpose input/output GPIO21 104 DIO General-purpose input/output GPIO22 132 DIO General-purpose input/output GPIO23 136 DIO General-purpose input/output GPIO24 428 DIO General-purpose input/output 4.10. SDIO Interface Do not pull down this pin before powering on if the module does not need to enter Fast Meta mode. 1.8 V power domain. If unused, keep it open. 1.8 V power domain. If unused, keep these pins open. Used for external V2X function by default. 1.8 V power domain. If unused, keep these pins open. The module provides one SDIO interface only for eMMC application, which supports eMMC 5.1 protocol and HS400 mode. AG568N_Series_QuecOpen_Hardware_Design 64 / 135 Automotive Module Series Table 21: Pin Definition of SDIO Interface Pin Name Pin No. I/O Description Comment EMMC_RST 54 DO eMMc reset SDIO_DATA0 49 DIO SDIO data bit 0 SDIO_DATA1 50 DIO SDIO data bit 1 SDIO_DATA2 51 DIO SDIO data bit 2 SDIO_DATA3 52 DIO SDIO data bit 3 SDIO_DATA4 53 DIO SDIO data bit 4 SDIO_DATA5 55 DIO SDIO data bit 5 SDIO_DATA6 56 DIO SDIO data bit 6 SDIO_DATA7 58 DIO SDIO data bit 7 SDIO_CMD SDIO_CLK SDIO_DSL 48 47 57 DIO SDIO command DO SDIO clock DI SDIO data strobe 1.8 V power domain. If unused, keep these pins open. AG568N_Series_QuecOpen_Hardware_Design 65 / 135 Automotive Module Series 4.10.1. Reference Design for eMMC Application Figure 23: Reference Design for eMMC Application Follow the principles below in eMMC circuit design:

To avoid jitter of bus, it is recommended to reserve resistors R12R19 (10100 k) to pull up SDIO traces to VDD_1V8. R12R19 are not mounted by default. To improve signal quality, it is recommended to add 0 R1R9, R11 and R22 in series between the module and eMMC. The resistance of R10 depends on your specific device. R23 and bypass capacitors C1C11 are reserved and not mounted by default. All resistors and bypass capacitors should be placed close to the module. SDIO signal traces should comply with the following principles:

1) It is important to route the SDIO signal traces with ground surrounded. The impedance of SDIO data trace should be 50 10 %. 2) Keep the spacing between adjacent SDIO_DATA traces and spacing between SDIO_DATA and SDIO_CLK traces two times the trace width. 3) Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog 4) is recommended signals, etc., as well as noisy signals such as clock signals, DC-DC signals, etc. length difference between SDIO_CLK and It SDIO_DATA[0:7]/SDIO_CMD less than 1 mm and the total routing length less than 50 mm. The total trace length inside the module is 10 mm, so the exterior total trace length should be less than 40 mm. to keep trace the 5) Keep the spacing between SDIO and other signal traces at least two times the trace width and the load capacitance of SDIO bus less than 3 pF. AG568N_Series_QuecOpen_Hardware_Design 66 / 135 R12NMR13NMR14NMR15NMR16NMR17NMR18NMR19NMR2010KR2147KVDD_1V8C1NMC2NMC3NMC4NMC5NMC6NMC7NMC8NMC9NMC10NMC11NMVDD_3VC14100 nFC152.2 FVDD_1.8VC12100 nFC131 FDAT0DAT1DAT2DAT3DAT4DAT5DAT6DAT7CMDCLKRSTNVCCQVCCVSSeMMCSDIO_DATA0SDIO_DATA1SDIO_DATA2SDIO_DATA3SDIO_DATA4SDIO_DATA5SDIO_DATA6SDIO_DATA7SDIO_CMDSDIO_CLKEMMC_RSTModuleR1 0RR2 0RR3 0RR4 0RR5 0RR6 0RR7 0RR8 0RR9 0RR10R11 0RSDIO_DSLDSLR22 0RR23NM Automotive Module Series 4.11. ADC Interfaces The module provides six Analog-to-Digital Converter (ADC) interfaces. In order to improve the accuracy of ADC, the trace of ADC interfaces should be surrounded by ground. Table 22: Pin Definition of ADC Interfaces Pin Name Pin No. I/O Description Comment ADC0 247 ADC1 245 ADC2 113 ADC3 60 ADC4 163 ADC5 166 AI AI AI AI AI AI General-purpose ADC interface General-purpose ADC interface General-purpose ADC interface General-purpose ADC interface General-purpose ADC interface General-purpose ADC interface If unused, connect them with ground. The resolution of ADC0 and ADC1 is 15-bit, ADC2ADC5 is 12-bit. The following table describes the characteristics of the ADC interfaces. Table 23: Characteristics of ADC Interfaces Parameter Min. Typ. ADC0 Voltage Range ADC1 Voltage Range ADC2 Voltage Range ADC3 Voltage Range ADC4 Voltage Range ADC5 Voltage Range ADC Resolution ADC Sample Rate 0.04 V 0.05 V

ADC0 & ADC1: 15 bit ADC2ADC5: 12 bit ADC0 & ADC1: 100 kHz ADC2ADC5: 3.25 MHz

Max. 1.78 V 1.45 V AG568N_Series_QuecOpen_Hardware_Design 67 / 135 Automotive Module Series NOTE 1. The input voltage of ADC should not exceed its corresponding voltage range. It is prohibited to supply any voltage to ADC pin when VBAT is removed. 2. It is recommended to use resistor divider circuit for ADC application. 3. 4.12. SGMII Interface The module includes an integrated Ethernet MAC with an SGMII interface and one MDIO management interface. Key features of the SGMII interface are shown below:

IEEE 802.3 compliance Supports 10/100/1000/2500 Mbps in full duplex mode and 10/100 Mbps in half duplex mode Can be connected to an external Ethernet PHY or an external switch The power domain of management interface: 1.8 V Table 24: Pin Definition of SGMII Interface Pin Name Pin No. I/O Description Comment SGMII_RX_P SGMII_RX_M SGMII_TX_P SGMII_TX_M SGMII_INT SGMII_RST 97 99 94 96 223 224 AI AI SGMII receive (+) SGMII receive (-) AO SGMII transmit (+) AO SGMII transmit (-) DI PHY interrupt output DO SGMII reset external PHY SGMII_MDIO_DATA 271 DIO SGMII management data Requires differential impedance of 100 . If unused, connect Rx pairs with GND directly and keep other pins open. 1.8 V power domain. If unused, keep these pins open. SGMII_MDIO_CLK 272 DO SGMII management data clock AG568N_Series_QuecOpen_Hardware_Design 68 / 135 Automotive Module Series Figure 24: Reference Circuit of SGMII Interface with PHY Application To enhance the reliability and availability of your application, follow the criteria below in the SGMII circuit design:

Keep SGMII data and control signals away from RF and power supply traces. Keep the maximum trace length less than 12.7 cm and keep skew on the differential pairs less than 5 mils. The differential impedance of SGMII data trace should be 100 10 %. To minimize crosstalk, the distance between separate adjacent pairs that are on the same layer must be equal to or larger than 40 mils. It is recommended to be less than 2 total vias in the differential pair. It is recommended to insert GND between SGMII_MDIO_CLK and SGMII_MDIO_DATA to prevent crosstalk. Both SGMII_TX_P and SGMII_TX_N should be connected to 100 nF AC coupling capacitance. 4.13. RGMII Interface The module provides one RGMII interface, which can be connected with a PHY IC. Supports IEEE 15882008, IEEE 802.1AS-2011 and IEEE 802.1-Qav-2009 Supports half/full duplex for 10/100/1000 Mbps Supports connection to an external Ethernet PHY or an external switch AG568N_Series_QuecOpen_Hardware_Design 69 / 135 SGMII_MDIO_DATASGMII_RSTMDIOINTMDCR1R2NMModule PHYETH_VDDIOSGMII_INTRSTNSGMII_MDIO_CLK100 nFSGMII_TX_MSGMII_TX_PSGMII_RX_PSGMII_RX_MRX_PRX_MTX_PTX_MClose to PHYControlSGMII Data100 nF100 nF100 nFNMR3R4NMNM Automotive Module Series Table 25: Pin Definition of RGMII Interface Pin Name Pin No. I/O Description Comment RGMII_MD_IO RGMII_MD_CLK RGMII_RX_0 RGMII_RX_1 RGMII_RX_2 RGMII_RX_3 RGMII_CK_RX RGMII_CTL_RX RGMII_TX_0 RGMII_TX_1 RGMII_TX_2 RGMII_TX_3 RGMII_CK_TX RGMII_CTL_TX RGMII_INT RGMII_RST 10 11 13 14 16 17 19 15 20 22 23 25 24 21 29 31 DIO RGMII management data DO RGMII management data clock DI DI DI DI DI DI DO DO DO DO DO DO DI RGMII receive data bit 0 RGMII receive data bit 1 RGMII receive data bit 2 RGMII receive data bit 3 RGMII receive clock RGMII receive control RGMII transmit data bit 0 RGMII transmit data bit 1 RGMII transmit data bit 2 RGMII transmit data bit 3 RGMII transmit clock RGMII transmit control PHY interrupt output DO RGMII reset external PHY Single-ended impedance of 50 . 1.8 V power domain. If unused, keep them open. 1.8 V power domain. If unused, keep them open. The following figure shows a reference design of RGMII interface with PHY application. For more details, see document [5]. AG568N_Series_QuecOpen_Hardware_Design 70 / 135 Automotive Module Series Figure 25: Reference Circuit of RGMII Interface with PHY Application To enhance the reliability and availability of your application design, follow the criteria below in the Ethernet PHY circuit design:

Keep RGMII data and control signals away from other sensitive circuits/signals such as RF circuits, analog signals, etc., as well as noisy signals such as clock signals, DC-DC signals, etc. The single-ended impedance of RGMII data traces should be 50 20 %. The length match within Tx signal traces (RGMII_CK_TX, RGMII_CTL_TX and RGMII_TX_[0:3]) and Rx signal traces (RGMII_CK_RX, RGMII_CTL_RX and RGMII_RX_[0:3]) should be less than 2 mm. Keep the spacing between Tx bus and Rx bus traces at least 2.5 times trace width. Keep the spacing between Tx bus traces (RGMII_CK_TX, RGMII_CTL_TX, RGMII_TX_[0:3]) or that between Rx bus traces (RGMII_CK_RX, RGMII_CTL_RX, RGMII_RX_[0:3]) at least twice the trace width. Keep the spacing between of RGMII and other signal traces at least 3 times trace width. The resistors R7R12 should be placed near the module. The resistors R1R6 should be placed near the Ethernet PHY. The value of R1R12 may be varied with the selection of PHY. AG568N_Series_QuecOpen_Hardware_Design 71 / 135 R13R14R15R16RGMII_VDDOR1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 RGMII_RX_0RGMII_RX_1RGMII_RX_2RGMII_RX_3RGMII_CTL_RXRGMII_CK_RXRGMII_TX_0RGMII_TX_1RGMII_TX_2RGMII_TX_3RGMII_CTL_TXRGMII_CK_TXModuleRGMII_RSTRGMII_INTRGMII_MD_CLKRGMII_MD_IOMDIOINTNRESETNEthernet PHYMDCRXD0RXD1RXD2RXD3RXCRCLKTXD0TXD1TXD2TXD3TCLKTXC Automotive Module Series 4.14. RTC The module has a real time clock within the PMIC, but has no dedicated RTC power supply pin. The RTC is powered by VBAT_BB. If VBAT_BB is removed, the RTC will not be maintained. Therefore, VBAT_BB must be powered continuously in actual applications if you need to maintain the RTC function. 4.15. SPI Interfaces The module provides three SPI interfaces. SPI1 and SPI2 only support master mode. SPI3 supports both master and slave modes. The maximum clock frequency is up to 50 MHz at master mode and 26 MHz at slave mode. Table 26: Pin Definition of SPI Interface Pin Name Pin No. I/O Description Comment SPI1_CS 213 DO SPI1 chip select SPI1_CLK 216 DO SPI1 clock SPI1_MOSI 210 DO SPI1 master-out slave-in SPI1_MISO 219 DI SPI1 master-in slave-out SPI2_CS 105 DO SPI2 chip select SPI2_CLK 103 DO SPI2 clock SPI2_MOSI 108 DO SPI2 master-out slave-in SPI2_MISO 106 DI SPI2 master-in slave-out SPI3_CS 278 DO SPI3 chip select SPI3_CLK 276 DO SPI3 clock SPI3_MOSI 277 DO SPI3 master-out slave-in SPI3_MISO 275 DI SPI3 master-in slave-out Master mode only. 1.8 V power domain. If unused, keep them open. Master and slave mode. 1.8 V power domain. Used for external V2X function by default. If unused, keep them open. AG568N_Series_QuecOpen_Hardware_Design 72 / 135 Automotive Module Series Figure 26: SPI Interfaces Timing in Master Mode The related parameters of SPI timing in master mode are listed in the following table. Table 27: Parameters of SPI Interfaces Timing in Master Mode Parameter Description Min. Typ. Max. Unit T SPI clock cycle t (ch) SPI clock high-level period t (cl) SPI clock low-level period t (mos) SPI master data output setup time t (moh) SPI master data output hold time t (mis) SPI master data input setup time t (mih) SPI master data input hold time

7.2 7.2 7.1 7.1 0 0

50 MHz

ns ns ns ns ns ns The module provides three 1.8 V SPI interfaces. A voltage-level translator between the module and the host should be used if the application is equipped with a 3.3 V processor or device interface. AG568N_Series_QuecOpen_Hardware_Design 73 / 135 SPI_CSSPI_CLKSPI_MOSI12SPI_MISO3T4t (mis)t (ch)t (cl)t (mos)t (moh)t (mih) Automotive Module Series Figure 27: Reference Circuit of SPI Interfaces with a Voltage-level Translator 4.16. USB_BOOT The module provides a USB_BOOT pin. Pull up USB_BOOT to VDD_EXT or external MCU controlling pin before powering on the module, thus the module will enter emergency download mode when powered on. In this mode, the module supports firmware upgrade over USB 2.0 interface. Table 28: Pin Definition of USB_BOOT Pin Name Pin No. I/O Description Comment USB_BOOT 83 DI Force the module into emergency download mode 1.8/3.3 V power domain. It is recommended to reserve test points. Figure 28: Reference Circuit of USB_BOOT AG568N_Series_QuecOpen_Hardware_Design 74 / 135 VCCAVCCBOEA1A2A3A4NCGNDB1B2B3B4NCVDD_EXTSPI_CSSPI_CLKSPI_MISOSPI_MOSI0.1 F0.1 FSPI_CS_N_MCUSPI_CLK_MCUSPI_MISO_MCUSPI_MOSI_MCUVDD_MCUTranslatorModuleUSB_BOOTVDD_EXT4.7KTest pointTVSClose to test point Automotive Module Series Figure 29: Timing Sequence for Entering Emergency Download Mode NOTE 1. Ensure VBAT is stable before driving PWRKEY low. The time period between powering VBAT up and driving PWRKEY low shall be not less than 30 ms. 2. Follow the above timing sequence when using MCU to control the module to enter the emergency download mode. Do not pull up USB_BOOT to VDD_EXT or external MCU controlling pin before powering up VBAT. Directly connect the test points as shown in Figure 28 can manually force the module to enter emergency download mode. 4.17. PCIe Interface The module provides an integrated PCIe (Peripheral Component Interconnect Express) interface which follows PCI Express Base Specification Revision 3.0. The key features of the PCIe interface are mentioned below:

PCI Express Base Specification Revision 3.0 compliant Supports 2-lane and maximum data rate at 8 Gbps/lane. Dedicated to connect to an external WLAN IC and used for Wi-Fi communication by default. The module supports RC and EP mode in hardware design, but only supports RC mode in the software design. AG568N_Series_QuecOpen_Hardware_Design 75 / 135 VIL 0.3VVIH=1.45VVBATPWRKEY 500msRESET_NVDD_EXT 100 msUSB_BOOTUSB_BOOT can be pulled up to 1.8 V before VDD_EXT is powered up, and the module will enter emergency download mode when it is turned on.NOTE 1 Automotive Module Series Table 29: Pin Definition of PCIe Interface Pin Name Pin No. I/O Description Comment PCIE_REFCLK_P 40 AIO PCIe reference clock (+) PCIE_REFCLK_M 38 AIO PCIe reference clock (-) PCIE_TX0_P PCIE_TX0_M PCIE_RX0_P PCIE_RX0_M PCIE_TX1_P PCIE_TX1_M PCIE_RX1_P PCIE_RX1_M 46 44 34 32 43 41 37 35 AO AO AI AI AO AO AI AI PCIe transmit 0 (+) PCIe transmit 0 (-) PCIe receive 0 (+) PCIe receive 0 (-) PCIe transmit 1 (+) PCIe transmit 1 (-) PCIe receive 1 (+) PCIe receive 1 (-) Compliant with PCIe revision 3.0 specification. Requires differential impedance of 85 . If unused, connect Rx pairs with GND directly and keep others open. PCIE_CLKREQ_N 36 DIO PCIe clock request PCIE_RST_N PCIE_WAKE_N 39 30 DO PCIe reset DI PCIe wake up 1.8 V power domain. If unused, keep these pins open. The following figure illustrates the PCIe interface connection. AG568N_Series_QuecOpen_Hardware_Design 76 / 135 Automotive Module Series Figure 30: PCIe Interface Connection The following principles of PCIe interface design should be complied with to meet PCIe specifications. It is important to route the PCIe signal and PCIE_REFCLK traces as differential pairs with ground surrounded. The differential impedance of 85 10% is recommended. PCIe signals must be protected from noisy signals (clocks, DC-DC, RF and so forth). All other sensitive/high-speed signals and circuits must be routed far away from PCIe traces. For each differential pair, intra-lane length match should be less than 5 mil. Inter-lane length match, that is, the trace length matching between the reference clock, TX, and RX pairs is not required. The space between TX and RX, and the spacing between PCIe lanes and all other signals, should be at least 4 times the trace width. It is better to place PCIe TX AC coupling capacitors close to source or connector side to keep good signal integrity of main route on PCB. Do not stagger the capacitors, as this can affect the differential integrity of the design and can generate EMI. TX AC coupling capacitors should be 220 nF for PCIe Gen 3, and 100 nF is recommended for PCIe Gen 2 application. Use a serpentine to keep the differential pairs equal in the break out region as much as possible, to ensure that the traces stay differential thereafter. To reduce the probability for layer-to-layer manufacturing variation, minimize layer transitions on the main route (In other words, apply layer transitions only at module breakouts and connectors to ensure minimum layer transitions on the main route). AG568N_Series_QuecOpen_Hardware_Design 77 / 135 PCIE_TX0_MPCIE_TX0_PPCIE_RST_NPCIE_RX0_PAG568N SeriesPCIE_REFCLK_MPCIE_REFCLK_PPCIE_WAKE_NPCIE_CLKREQ_NPCIE_RX0_MPCIE_CLKREQ_NWi-Fi ModulePCIE_WAKE_NPCIE_RST_NPCIE_REFCLK_PPCIE_REFCLK_MPCIE_RX_MPCIE_RX_PPCIE_TX_PPCIE_TX_MR1100KR2100KVDD_EXTC1220 nFC2220 nFC3220 nFC4220 nFR3NMR449.9RR549.9RPlace close to EP side Automotive Module Series The PCIE_REFCLK pair must add resistors near the slot (EP) side. The recommended resistor value is 49.9 +/-1%. 4.18. Control Signals 4.18.1. WAKEUP_IN The module can be woken up by other devices. Table 30: Pin Definition of WAKEUP_IN Pin Name Pin No. I/O Description Comment WAKEUP_IN 100 DI External wakeup signal to the module 1.8 V power domain. If unused, keep it open. 4.18.2. WAKEUP_OUT The module can wake up other devices. Table 31: Pin Definition of WAKEUP_OUT Pin Name Pin No. I/O Description Comment WAKEUP_OUT 102 DO Wakeup signal from the module 1.8 V power domain. If unused, keep it open. NOTE GPIOs can also be configured as wake-up interrupt pins. For more details, see Chapter 4.9. AG568N_Series_QuecOpen_Hardware_Design 78 / 135 Automotive Module Series 5 RF Specifications The module includes one main antenna interface, one Rx-diversity antenna interface 14, two MIMO antenna interfaces, and one GNSS antenna interface. The impedance of antenna port is 50 . 5.1. Cellular Network 5.1.1. Antenna Interfaces & Frequency Bands 5.1.1.1. Pin Definition of Cellular Network Interface The pin definition is shown as below:

Table 32: Pin Definition of AG568N-CN Cellular Network Interface Pin Name Pin No. I/O Description ANT_MAIN 414 AIO ANT_DRX 416 AIO ANT_MIMO3 418 AIO ANT_MIMO4 420 AI 2G/3G/4G LMHB TRx0 5G NR n1/n3/n28A/n41 TRx0 SA 5G NR n41 Rx1 NSA 5G NR n78 DRx0 SA/NSA 2G/3G/4G LMHB DRx0 5G NR n1/n3/n28A/n41 DRx0 SA 5G NR n41 DRx1 NSA 5G NR n78 TRx0 SA/NSA 4G MHB Rx1 5G NR n1/n3/n41 Rx1 SA 5G NR n41 TRx0 NSA 5G NR n78 DRx1 SA/NSA 4G MHB DRx1 5G NR n1/n3/n41 DRx1 SA 5G NR n41 DRx0 NSA 5G NR n78 Rx1 SA/NSA 14 Rx-diversity antenna interface is used to resist the fall of signals caused by high-speed movement and multipath effect. AG568N_Series_QuecOpen_Hardware_Design 79 / 135 Automotive Module Series Table 33: Pin Definition of AG568N-EU Cellular Network Interface Pin Name Pin No. I/O Description ANT_MAIN 414 AIO ANT_DRX 416 AIO ANT_MIMO3 418 AI ANT_MIMO4 420 AI 2G/3G/4G LMHB TRx0 5G NR n1/n3/n7/n8/n20/n28 TRx0 SA 5G NR n77/n78 DRx0 SA/NSA 2G/3G/4G LMHB DRx0 5G NR n1/n3/n7/n8/n20/n28 DRx0 SA 5G NR n77/n78 TRx0 SA/NSA 4G MHB Rx1 5G NR n1/n3/n7 Rx1 SA 5G NR n77/n78 DRx1 SA/NSA 4G MHB DRx1 5G NR n1/n3/n7 DRx1 SA 5G NR n77/n78 Rx1 SA/NSA Table 34: Pin Definition of AG568N-NA Cellular Network Interface Pin Name Pin No. I/O Description ANT_MAIN 414 AIO ANT_DRX 416 AIO ANT_MIMO3 418 AI ANT_MIMO4 420 AI 4G MHB TRx0 4G LB DRx0 5G NR n5 DRx0 SA/NSA 5G NR n12 DRx0 SA 5G NR n2/n66 TRx0 SA/NSA 5G NR n77 DRx0 SA/NSA @ MHB LTE 5G NR n77 Tx0/DRx0 NSA @ LB LTE 5G NR n78 DRx0 SA 4G MHB DRx0 4G LB TRx0 5G NR n5 TRx0 SA/NSA 5G NR n12 TRx0 SA 5G NR n2/n66 DRx0 SA/NSA 5G NR n77 TRx0 SA/NSA @ MHB LTE 5G NR n77 Rx0 NSA @ LB LTE 5G NR n78 TRx0 SA 4G MHB Rx1 5G NR n2/n66 Rx1 SA/NSA 5G NR n77 DRx1 SA/NSA @ LMHB LTE 5G NR n78 DRx1 SA 4G MHB DRx1 5G NR n2/n66 DRx1 SA/NSA 5G NR n77 Rx1 SA/NSA @ LMHB LTE AG568N_Series_QuecOpen_Hardware_Design 80 / 135 Automotive Module Series 5G NR n78 Rx1 SA Table 35: Pin Definition of AG568N-ROW Cellular Network Interface Pin Name Pin No. I/O Description ANT_MAIN 414 AIO ANT_DRX 416 AIO 3G/4G LMHB TRx0 5G NR n28 TRx0 SA 5G NR n77/n78/n79 DRx0 3G/4G LMHB DRx0 5G NR n28 DRx0 SA 5G NR n77/n78/n79 TRx0 SA/NSA ANT_MIMO3 418 ANT_MIMO4 420 AI AI 4G MHB Rx1 5G NR n77/n78/n79 DRx1 4G MHB DRx1 5G NR n77/n78/n79 Rx1 NOTE 1. Only passive antennas are supported. 2. LTE B21 only supports TRx0 and DRx0 on AG568N-ROW. 3. 5G n78 only supports SA on AG568N-NA. 5.1.1.2. Operating Frequency Table 36: AG568N-CN Operating Frequency Operating Frequency Transmit (MHz) Receive (MHz) EGSM900 DCS1800 WCDMA B1 WCDMA B8 LTE-FDD B1 LTE-FDD B3 LTE-FDD B5 880915 17101785 19201980 880915 19201980 17101785 824849 925960 18051880 21102170 925960 21102170 18051880 869894 AG568N_Series_QuecOpen_Hardware_Design 81 / 135 Automotive Module Series LTE-FDD B7 LTE-FDD B8 LTE-TDD B34 LTE-TDD B38 LTE-TDD B39 LTE-TDD B40 LTE-TDD B41 5G NR FDD n1 5G NR FDD n3 25002570 880915 20102025 25702620 18801920 23002400 24962690 19201980 17101785 5G NR FDD n28A 703733 5G NR TDD n41 5G NR TDD n78 24962690 33003800 Table 37: AG568N-EU Operating Frequency 26202690 925960 20102025 25702620 18801920 23002400 24962690 21102170 18051880 758788 24962690 33003800 Operating Frequency Transmit (MHz) Receive (MHz) EGSM900 DCS1800 WCDMA B1 WCDMA B3 WCDMA B5 WCDMA B8 LTE-FDD B1 LTE-FDD B3 LTE-FDD B5 LTE-FDD B7 880915 17101785 19201980 17101785 824849 880915 19201980 17101785 824849 25002570 925960 18051880 21102170 18051880 869894 925960 21102170 18051880 869894 26202690 AG568N_Series_QuecOpen_Hardware_Design 82 / 135 Automotive Module Series LTE-FDD B8 LTE-FDD B20 LTE-FDD B28 LTE-FDD B32 LTE-TDD B38 LTE-TDD B40 5G NR FDD n1 5G NR FDD n3 5G NR FDD n7 5G NR FDD n8 5G NR FDD n20 5G NR FDD n28 5G NR TDD n77 5G NR TDD n78 880915 832862 703748

25702620 23002400 19201980 17101785 25002570 880915 832862 703748 33004200 33003800 925960 791821 758803 14521496 25702620 23002400 21102170 18051880 26202690 925960 791821 758803 33004200 33003800 Table 38: AG568N-NA Operating Frequency Operating Frequency Transmit (MHz) Receive (MHz) LTE-FDD B2 LTE-FDD B4 LTE-FDD B5 LTE-FDD B12 LTE-FDD B29 LTE-FDD B66 5G NR FDD n2 5G NR FDD n5 18501910 17101755 824849 699716

17101780 18501910 824849 19301990 21102155 869894 729746 717728 21102200 19301990 869894 AG568N_Series_QuecOpen_Hardware_Design 83 / 135 Automotive Module Series 5G NR FDD n12 5G NR FDD n66 5G NR TDD n77 5G NR TDD n78 699716 17101780 33004200 33003800 729746 21102200 33004200 33003800 Table 39: AG568N-ROW Operating Frequency Operating Frequency Transmit (MHz) Receive (MHz) WCDMA B1 WCDMA B3 LTE-FDD B1 LTE-FDD B3 LTE-FDD B19 LTE-FDD B21 LTE-FDD B28 5G NR FDD n28 5G NR TDD n77 5G NR TDD n78 5G NR TDD n79 19201980 17101785 19201980 17101785 830845 21102170 18051880 21102170 18051880 875890 1447.91462.8 1495.91510.8 703748 703748 33004200 33003800 44005000 758803 758803 33004200 33003800 44005000 5.1.2. Tx Power The following table shows the Tx power of the module. Table 40: Tx Power (25 C, 3.8 V Power Supply) Frequency EGSM900 Max. Tx Power Min. Tx Power 33 dBm 2 dB 5 dBm 5 dB AG568N_Series_QuecOpen_Hardware_Design 84 / 135 Automotive Module Series DCS1800 30 dBm 2 dB 0 dBm 5 dB EGSM900 8-PSK 27 dBm 3 dB 5 dBm 5 dB DCS1800 8-PSK 26 dBm 3 dB 0 dBm 5 dB WCDMA bands LTE bands 5G NR TDD 5G NR FDD

. NOTE 23 dBm 2 dB 23 dBm 2 dB 26 dBm+1/-2 dB 23 dBm 2 dB

< -49 dBm

< -49 dBm

< -39 dBm

< -39 dBm 1. In GPRS 4 slots Tx mode, the maximum output power is reduced by 4 dB. The design conforms to the GSM specification as described in Chapter 13.16 of 3GPP TS 51.010-1. 2. For 5G NR FDD/TDD bands, refer to the specifications as described in Clause 6.2 of TS 38.101-1-

g80. 3. WCDMA specified power tolerance conforms to 3GPP TS 34.121-1 requirements. 4. The specified typical power tolerance of LTE conforms to 3GPP TS 36.521-1 requirements and the module is tested @ BW = 10 MHz,1 RB. 5.1.3. Rx Sensitivity The following table shows conducted RF receiving sensitivity of the module. Table 41: AG568N-CN Conducted RF Receiving Sensitivity (Unit: dBm) Frequency Band EGSM900 DCS1800 WCDMA B1 WCDMA B8 SIMO 15 Typ.

-108

-108

-109

-109 Max.

-110

-110

-111.7

-111.6 3GPP SIMO

-102

-102

-106

-103 Min.

-104

-104

-108

-105 15 Test conditions for the receiving sensitivity of AG568N-CN:

1) GSM/WCDMA: tested with 1 antenna (1Rx);

2) 3) LTE B5/B8: tested with 2 antennas (2Rx). Other 4G bands: tested with 4 antennas (4Rx);

5G NR SA n28A: tested with 2 antennas (2Rx). Other 5G NR SA bands: tested with 4 antennas (4Rx). AG568N_Series_QuecOpen_Hardware_Design 85 / 135 Automotive Module Series LTE-FDD B1 (10 MHz) LTE-FDD B3 (10 MHz) LTE-FDD B5 (10 MHz) LTE-FDD B7 (10 MHz) LTE-FDD B8 (10 MHz) LTE-TDD B34 (10 MHz) LTE-TDD B38 (10 MHz) LTE-TDD B39 (10 MHz) LTE-TDD B40 (10 MHz) LTE-TDD B41 (10 MHz) 5G NR FDD n1 (20 MHz) 5G NR FDD n3 (20 MHz) 5G NR FDD n28A (20 MHz) 5G NR TDD n41 (100 MHz) 5G NR TDD n78 (100 MHz)

-101

-98

-96.3

-99

-95.3

-101

-101

-101

-101

-99

-95.8

-92.8

-90.1

-86.7

-86.8

-103

-100

-98.3

-101

-97.3

-102

-102

-102

-102

-100

-97.3

-94.3

-91.6

-88.2

-88.3

-105.3

-104.8

-99

-96

-103.6

-94.3

-103.8

-97

-103.1

-93.3

-105.9

-104.9

-106.1

-104.9

-104.5

-99

-99

-99

-99

-97

-101.7

-95.8

-100.6

-92.8

-100.6

-90.1

-93.4

-93.2

-86.7

-86.8 Table 42: AG568N-EU Conducted RF Receiving Sensitivity (Unit: dBm) Frequency Bands 3GPP SIMO SIMO 16 EGSM900 DCS1800 WCDMA B1 WCDMA B3 WCDMA B5 Min. TBD TBD TBD TBD TBD Typ. TBD TBD TBD TBD TBD Max. TBD TBD TBD TBD TBD

-102

-102

-106

-103

-104 16 Test conditions for the receiving sensitivity of AG568N-EU:

1) GSM/WCDMA: tested with 1 antenna (1Rx);

2) 3) 4) LTE B5/B8/B20/B28: tested with 2 antennas (2Rx). Other 4G bands: tested with 4 antennas (4Rx);

LTE B32 supports Rx only and cannot be tested under single-band conditions;

5G NR SA n8/n20/n28: tested with 2 antennas (2Rx). Other 5G NR SA bands: tested with 4 antennas (4Rx);

AG568N_Series_QuecOpen_Hardware_Design 86 / 135 Automotive Module Series WCDMA B8 LTE-FDD B1 (10 MHz) LTE-FDD B3 (10 MHz) LTE-FDD B5 (10 MHz) LTE-FDD B7 (10 MHz) LTE-FDD B8 (10 MHz) LTE-FDD B20 (10 MHz) LTE-FDD B28 (10 MHz) LTE-FDD B32 (10 MHz) LTE-TDD B38 (10 MHz) LTE-TDD B40 (10 MHz) 5G NR FDD n1 (20 MHz) 5G NR FDD n3 (20 MHz) 5G NR FDD n7 (20 MHz) 5G NR FDD n8 (20 MHz) 5G NR FDD n20 (20 MHz) 5G NR FDD n28 (20 MHz) 5G NR TDD n77 (100 MHz) 5G NR TDD n78 (100 MHz) TBD TBD TBD TBD TBD TBD TBD TBD

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

-103

-99

-96

-94.3

-97

-93.3

-93.3

-94.8

-99

-99

-95.8

-92.8

-93.8

-89.3

-89.1

-90.1

-86.8

-86.8 Table 43: AG568N-NA Conducted RF Receiving Sensitivity (Unit: dBm) Frequency Bands LTE-FDD B2 (10 MHz) SIMO 17 Typ.

-101 3GPP SIMO Max.

-104.6

-97 Min.

-99 17 Test conditions for the receiving sensitivity of AG568N-NA:

1) 2) 3) LTE B5/B12: tested with 2 antennas (2Rx). Other 4G bands: tested with 4 antennas (4Rx);

LTE B29 supports Rx only and cannot be tested under single-band conditions;

5G NR SA n5/n12: tested with 2 antennas (2Rx). Other 5G NR SA bands: tested with 4 antennas (4Rx);

AG568N_Series_QuecOpen_Hardware_Design 87 / 135 Automotive Module Series LTE-FDD B4 (10 MHz) LTE-FDD B5 (10 MHz) LTE-FDD B12 (10 MHz) LTE-FDD B29 (10 MHz)

-101

-96.3

-95.3

-103

-98.3

-97.3

-105.1

-99

-102.7

-94.3

-103.6

-93.3

LTE-FDD B66 (10 MHz)

-100.5

-102.5

-104.2

-98.5 5G NR FDD n2 (20 MHz) 5G NR FDD n5 (20 MHz) 5G NR FDD n12 (15 MHz) 5G NR FDD n66 (20 MHz) 5G NR TDD n77 (100 MHz) 5G NR TDD n78 (100 MHz)

-93.8

-90.1

-83.3

-95.3

-86.8

-86.8

-95.3

-91.6

-84.8

-96.8

-88.3

-88.3

-102.5

-93.8

-100.7

-90.1

-99.2

-83.3

-102.5

-95.3

-93.7

-93.9

-86.8

-86.8 Table 44: AG568N-ROW Conducted RF Receiving Sensitivity (Unit: dBm) Frequency Bands 3GPP SIMO SIMO 18 WCDMA B1 WCDMA B3 LTE-FDD B1 (10 MHz) LTE-FDD B3 (10 MHz) LTE-FDD B19 (10 MHz) LTE-FDD B21 (10 MHz) LTE-FDD B28 (10 MHz) 5G NR FDD n28 (20 MHz) 5G NR TDD n77 (100 MHz) Min.

-108

-105

-101

-98

-98.3

-98.3

-96.8

-90.1

-86.8 Typ.

-109

-109

-103

-100 Max.

-111.1

-111.6

-104.4

-104.0

-106

-103

-99

-96

-100.3

-103.1

-96.3

-99

-98.8

-91.6

-88.3

-101.4

-96.3

-102.9

-94.8

-100.4

-90.1

-93.9

-86.8 18 Test conditions for the receiving sensitivity of AG568N-ROW:

1) WCDMA: tested with 1 antenna (1Rx);

2) 3) LTE B19/B21/B28: tested with 2 antennas (2Rx). Other 4G bands: tested with 4 antennas (4Rx);

5G NR SA n28: tested with 2 antennas (2Rx). Other 5G NR SA bands: tested with 4 antennas (4Rx). AG568N_Series_QuecOpen_Hardware_Design 88 / 135 Automotive Module Series 5G NR TDD n78 (100 MHz) 5G NR TDD n79 (100 MHz)

-86.8

-86.8

-88.3

-88.3

-94.0

-92.4

-86.8

-86.8 NOTE 1. 5G NR FDD n1, n3, n7, n8, n12, n20, n28A and n28 support SA only. 2. 5G NR FDD n2, n5 and n66 support SA and NSA ;5G NR TDD n41, n77, n78 and n79 support SA and NSA. 3. GSM specified sensitivity values conforms to 3GPP TS 51.010-1 requirements. 4. WCDMA specified sensitivity values conforms to 3GPP TS 34.121-1 requirements. 5. LTE specified sensitivity values conforms to 3GPP TS 36.521-1 requirements. 6. 5G NR specified sensitivity values conforms to 3GPP TS 38.521-1 requirements, FDD test @ SCS 15 kHz, TDD test @ SCS 30 kHz. 5.1.4. Reference Design The module provides the main and Rx-diversity RF antenna interfaces for antenna connection. It is recommended to reserve a -type matching circuit for better RF performance, and the -type matching components (R1/C1/C2 and R2/C3/C4) should be placed as close to the antenna as possible. The capacitors are not mounted by default. Figure 31: Reference Circuit for RF Antenna Interfaces AG568N_Series_QuecOpen_Hardware_Design 89 / 135 ANT_MAINR1 0 RC1ModuleMainantennaNMC2NMR2 0 RC3Diversity antennaNMC4NMANT_DRX Automotive Module Series

. NOTE 1. The reference design of MIMO antenna interfaces is the same as that of main antenna interface. 2. Keep a proper distance between each antenna to improve receiving sensitivity. 5.2. GNSS The module includes a fully integrated global navigation satellite system solution that supports GPS, GLONASS, BDS, Galileo, and supports L1 + L5 dual-frequency positioning 19. The module supports standard NMEA 0183 protocol, and outputs NMEA sentences via USB interface

(data update rate: 110 Hz, 1 Hz by default). 5.2.1. Antenna Interfaces & Frequency Bands The following table shows the pin definition, frequency, and performance of GNSS antenna interface. Table 45: Pin Definition of GNSS Antenna Interface Pin Name Pin No. I/O Description Comment ANT_GNSS 426 AI GNSS antenna interface Single-ended impedance of 50 . Supports active antenna only. Table 46: GNSS Frequency (Unit: MHz) Type GPS Frequency 1575.42 1.023 (L1) 1176.45 10.23 (L5) GLONASS 1597.51605.8 Galileo BDS 1575.42 2.046 (E1) 1176.45 10.23 (E5a) 1561.098 2.046 19 AG568N series only supports dual-frequency GNSS (L1 + L5) by default, but the module is designed to be compatible with single-frequency GNSS (L1). For more details, please contact Quectel Technical Support. AG568N_Series_QuecOpen_Hardware_Design 90 / 135 Automotive Module Series 5.2.2. GNSS Performance Table 47: GNSS Performance Parameter Description Conditions Typ. Acquisition Autonomous

-149 Sensitivity Reacquisition Autonomous

-162 Tracking Autonomous

-168 Cold start @ open sky TTFF Warm start @ open sky Hot start @ open sky Accuracy CEP-50

. NOTE Autonomous EPO Enabled Autonomous EPO Enabled Autonomous EPO Enabled Autonomous @

open sky 30 15 25 5 1 1 2 Unit dBm s M 1. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (the module lost lock 3 times in 5 minutes for 10 seconds each time). 2. Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock within 5 minutes after loss of lock. 3. Acquisition sensitivity: the minimum GNSS signal power at which the module can fix position successfully within 3 minutes after executing cold start command. 4. The above GNSS performance test data is measured under dual-frequency L1 + L5. 5. For more details about GNSS performance, please consult Quectel Technical Support for GNSS performance test report. 5.2.3. Reference Design The reference circuit of GNSS antenna is shown as below. AG568N_Series_QuecOpen_Hardware_Design 91 / 135 Automotive Module Series Figure 32: Reference Circuit of GNSS Antenna

. NOTE 1. An external LDO can be selected to supply power according to the active antenna requirement. 2. 3. Junction capacitance of ESD protection components on the antenna interface should not exceed If the module is designed with a passive antenna, then the VDD circuit is not needed. 0.05 pF. The following layout guidelines should be considered in application design:

Maximize the distance among GNSS antenna, main antenna, Rx-diversity antenna and MIMO antennas. Digital circuits such as (U)SIM card, USB interface, camera module, SDIO interface and display connector should be kept away from antennas. Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar isolation and protection. Keep the characteristic impedance for ANT_GNSS trace as 50 . Select an external active antenna, since there is no LNA inside the module. The optimal value of the gain of the external active antenna minus the loss of RF cable is 1824 dB, otherwise the performance of GNSS positioning will be affected. 5.3. RF Routing Guidelines For users PCB, the characteristic impedance of all RF traces should be controlled to 50 . The impedance of the RF traces is usually determined by the trace width (W), the materials dielectric constant, the height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control AG568N_Series_QuecOpen_Hardware_Design 92 / 135 GNSS AntennaVDDModuleANT_GNSS47 nH10 R0.1 F0 RNMNM100 pF Automotive Module Series characteristic impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB structures. Figure 33: Microstrip Design on a 2-layer PCB Figure 34: Coplanar Waveguide Design on a 2-layer PCB Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) AG568N_Series_QuecOpen_Hardware_Design 93 / 135 Automotive Module Series Figure 36: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, follow the principles below in RF layout design:

Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 . The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground. The distance between the RF pins and the RF connector should be as short as possible and all the right-angle traces should be changed to curved ones. The recommended trace angle is 135. There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be not less than twice the width of RF signal traces

(2 W). Keep RF traces away from interference sources, and avoid intersection and paralleling between traces on adjacent layers. For more details about RF layout, see document [6]. 5.4. Antenna Design Requirements Table 48: Antenna Design Requirements Antenna Type Requirements GNSS Frequency range:

L1: 15591609 MHz L5: 11661187 MHz Polarization: RHCP or linear VSWR: 2 (Typ.) AG568N_Series_QuecOpen_Hardware_Design 94 / 135 Automotive Module Series Passive antenna gain: > 0 dBi Active antenna noise figure: < 1.5 dB Active antenna gain: > 0 dBi Active antenna embedded LNA gain: < 24 dB VSWR: 2 Efficiency: > 30 %

Gain:1dBi Max input power: 50 W Input impedance: 50 Vertical polarization Cable insertion loss:

< 1 dB: LB (< 1 GHz)

< 1.5 dB: MB (12.3 GHz)

< 2 dB: HB (> 2.3 GHz) 5G NR/LTE/UMTS/GSM 5.5. RF Connector Recommendation If RF connector is used for antenna connection, it is recommended to use the HFM connector provided by Rosenberger. Figure 37: Description of the HFM Connector For more details, visit https://www.rosenbergerap.com. AG568N_Series_QuecOpen_Hardware_Design 95 / 135 Automotive Module Series 6 Electrical Characteristics and Reliability 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 49: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_RF/VBAT_BB USB_VBUS Peak current of VBAT_BB Peak current of VBAT_RF 0 0

Voltage on Digital Pins

-0.3 Voltage at ADC0 Voltage at ADC1 Voltage at ADC2 Voltage at ADC3 Voltage at ADC4 Voltage at ADC5 0 0 0 0 0 0 5 21 1.5 2 1.98 1.98 1.98 1.98 1.98 1.98 1.98 V V A A V V V V V V V AG568N_Series_QuecOpen_Hardware_Design 96 / 135 Automotive Module Series 6.2. Power Supply Ratings Table 50: Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT VBAT_BB and VBAT_RF The actual input voltages must be kept between the minimum and maximum values. USB_VBUS Turn-on/

USB connection detect

3.3 3.8 4.3 V 4.2 5.0 21 V 6.3. Power Consumption 6.3.1. AG568N-CN Power Consumption Table 51: AG568N-CN Power Consumption (25 C, 3.8 V Power Supply) Description Conditions OFF state Power down AT+CFUN=0 AT+CFUN=4 EGSM900 DRX = 2 EGSM900 DRX = 5 EGSM900 DRX = 9 Sleep state DCS1800 DRX = 2 DCS1800 DRX = 5 DCS1800 DRX = 9 WCDMA @ DRX = 0.64 s WCDMA @ DRX = 1.28 s WCDMA @ DRX = 2.56 s Typ. 53 2.840 2.936 4.4 3.6 3.3 4.5 3.6 3.3 4.2 3.5 3.2 Unit A mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 97 / 135 Automotive Module Series WCDMA @ DRX = 5.12s LTE-FDD @ DRX = 0.32 s LTE-FDD @ DRX = 0.64 s LTE-FDD @ DRX = 1.28 s LTE-FDD @ DRX = 2.56 s LTE-TDD @ DRX = 0.32 s LTE-TDD @ DRX = 0.64 s LTE-TDD @ DRX = 1.28 s LTE-TDD @ DRX = 2.56 s 5G NR FDD @ DRX = 0.32 s 5G NR FDD @ DRX = 0.64 s 5G NR FDD @ DRX = 1.28 s 5G NR FDD @ DRX = 2.56 s 5G NR TDD @ DRX = 0.32 s 5G NR TDD @ DRX = 0.64 s 5G NR TDD @ DRX = 1.28 s 5G NR TDD @ DRX = 2.56 s 3.0 6.1 4.4 3.9 3.4 6.0 4.6 3.6 3.1 12.7 7.8 5.3 4.4 10.9 7.1 5.3 5.1 Idle state EGSM900 CH62 @ DRX = 5 139.0 EGSM900 CH62 @ DRX = 5 (USB active) 147.2 WCDMA @ Paging Frame= 64 138.7 WCDMA @ Paging Frame = 64 (USB active) 146.7 LTE-FDD @ DRX = 0.64 s LTE-FDD @ DRX = 0.64 s (USB active) LTE-TDD @ DRX = 0.64 s LTE-TDD @ DRX = 0.64 s (USB active) 140.4 149.0 139.4 147.3 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 98 / 135 Automotive Module Series 5G NR FDD @ DRX = 0.64 s 143.8 5G NR FDD @ DRX = 0.64 s (USB active) 149.6 5G NR TDD @ DRX = 0.64 s 143.2 5G NR TDD @ DRX = 0.64 s (USB active) 149.3 EGSM900 CH1 PCL = 5 @ 32.55 dBm EGSM900 CH62 PCL = 5 @ 32.54 dBm 454.9 456.3 EGSM900 CH62 PCL = 12 @ 18.87 dBm 258.4 EGSM900 CH62 PCL = 19 @ 5.15 dBm 214.3 EGSM900 CH124 PCL = 5 @ 32.57 dBm 458.9 DCS1800 CH512 PCL = 0 @ 28.75 dBm DCS1800 CH698 PCL = 0 @ 28.80 dBm DCS1800 CH698 PCL = 7 @ 15.80 dBm DCS1800 CH698 PCL = 15 @ 0.43 dBm DCS1800 CH885 PCL = 0 @ 28.77 dBm EGSM900 CH1 1DL/4UL @ 29.05 dBm EGSM900 CH62 4DL/1UL @ 32.58 dBm EGSM900 CH62 3DL/2UL @ 31.84 dBm EGSM900 CH62 2DL/3UL @ 30.39 dBm EGSM900 CH62 1DL/4UL @ 28.91 dBm 347.3 345.0 242.4 212.3 343.7 899.1 450.8 666.0 804.2 900.6 EGSM900 CH124 1DL/4UL @ 28.92 dBm 912.8 DCS1800 CH512 1DL/4UL @ 25.76 dBm 654.3 DCS1800 CH698 4DL/1UL @ 28.74 dBm 350.3 DCS1800 CH698 3DL/2UL @ 28.18 dBm 478.2 DCS1800 CH698 2DL/3UL @ 26.67 dBm 573.2 DCS1800 CH698 1DL/4UL @ 25.77 dBm 646.9 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA GSM voice call GPRS data transfer

(GNSS OFF) AG568N_Series_QuecOpen_Hardware_Design 99 / 135 Automotive Module Series DCS1800 CH885 1DL/4UL @ 25.76 dBm 650.2 EGSM900 CH1 1DL/4UL @ 23.68 dBm EGSM900 CH62 4DL/1UL @ 28.05 dBm EGSM900 CH62 3DL/2UL @ 27.39 dBm EGSM900 CH62 2DL/3UL @ 25.14 dBm EGSM900 CH62 1DL/4UL @ 23.68 dBm 711.3 379.8 517.5 613.5 709.2 EDGE data transfer

(GNSS OFF) EGSM900 CH124 1DL/4UL @ 23.45 dBm 708.3 DCS1800 CH512 1DL/4UL @ 22.30 dBm 683.9 DCS1800 CH698 4DL/1UL @ 26.78 dBm 348.9 DCS1800 CH698 3DL/2UL @ 25.50 dBm 474.6 DCS1800 CH698 2DL/3UL @ 24.16 dBm 575.8 DCS1800 CH698 1DL/4UL @ 22.85 dBm 683.0 DCS1800 CH885 1DL/4UL @ 22.57 dBm 681.1 WCDMA B1 CH10562 @ 23.14 dBm WCDMA B1 CH10700 @ 23.12 dBm WCDMA B1 CH10838 @ 23.11 dBm WCDMA B8 CH2937 @ 23.26 dBm WCDMA B8 CH3012 @ 23.18 dBm WCDMA B8 CH3088 @ 23.18 dBm 689.7 716.7 735.5 752.2 722.2 770.2 WCDMA B1 HSDPA CH10562 @ 22.67 dBm 679.5 WCDMA B1 HSDPA CH10700 @ 22.11 dBm 674.3 WCDMA voice call WCDMA data transfer (GNSS OFF) WCDMA B1 HSDPA CH10838 @ 22.11 dBm 687.6 WCDMA B8 HSDPA CH2937 @ 22.26 dBm 695.1 WCDMA B8 HSDPA CH3012 @ 22.22 dBm 670.5 WCDMA B8 HSDPA CH3088 @ 22.16 dBm 712.2 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 100 / 135 Automotive Module Series WCDMA B1 HSUPA CH10562 @ 23.19 dBm 710.4 WCDMA B1 HSUPA CH10700 @ 22.16 dBm 685.2 WCDMA B1 HSUPA CH10838 @ 22.12 dBm 699.1 WCDMA B8 HSUPA CH2937 @ 22.28 dBm 707.1 WCDMA B8 HSUPA CH3012 @ 22.24 dBm 681.1 WCDMA B8 HSUPA CH3088 @ 22.19 dBm 72764 LTE-FDD B1 CH100 @ 23.15 dBm LTE-FDD B1 CH300 @ 23.29 dBm LTE-FDD B1 CH500 @ 23.22 dBm LTE-FDD B3 CH1300 @ 22.84 dBm LTE-FDD B3 CH1575 @ 22.79 dBm LTE-FDD B3 CH1850 @ 22.80 dBm LTE-FDD B5 CH2450 @ 22.94 dBm LTE-FDD B5 CH2525 @ 22.97 dBm LTE-FDD B5 CH2600 @ 23.01 dBm LTE-FDD B7 CH2850 @ 22.99 dBm LTE-FDD B7 CH3100 @ 22.97 dBm LTE-FDD B7 CH3350 @ 23.43 dBm LTE-FDD B8 CH3500 @ 23.08 dBm LTE-FDD B8 CH3625 @ 23.07 dBm LTE-FDD B8 CH3750 @ 23.08 dBm LTE-TDD B34 CH36275 @ 23.05 dBm 718.5 748.2 839.9 750.9 738.4 785.6 696.3 674.9 690.7 927.6. 910.6 1024.1 741.8 720.1 754.9 460.1 LTE-TDD B38 CH37850 @ 23.01 dBm 521.76 LTE-TDD B38 CH38000 @ 22.98 dBm LTE-TDD B38 CH38150 @ 22.99 dBm 520.2 520.1 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA LTE data transfer

(GNSS OFF) AG568N_Series_QuecOpen_Hardware_Design 101 / 135 Automotive Module Series LTE-TDD B39 CH38350 @ 22.76 dBm LTE-TDD B39 CH38450 @ 22.83 dBm LTE-TDD B39 CH38550 @ 22.80 dBm LTE-TDD B40 CH38750 @ 22.75 dBm LTE-TDD B40 CH39150 @ 22.74 dBm LTE-TDD B40 CH39550 @ 22.79 dBm LTE-TDD B41 CH39750 @ 22.56 dBm LTE-TDD B41 CH40620 @ 23.00 dBm LTE-TDD B41 CH41490 @ 22.83 dBm n1A CH427000 @ 23.13 dBm n1A CH428000 @ 23.02 dBm n1A CH429000 @ 23.12 dBm n3A CH365000 @ 21.99 dBm n3A CH368500 @ 21.82 dBm n3A CH372000 @ 21.81 dBm n28A CH154600 @ 22.78 dBm n41A CH509202 @ 26.36 dBm n41A CH518598 @ 26.37 dBm n41A CH528000 @ 25.82 dBm n78A CH623334 @ 26.79 dBm n78A CH636666 @ 26.97 dBm n78A CH650000 @ 26.89 dBm 5G NR SA data transfer (GNSS OFF) 5G NR NSA data transfer (GNSS OFF) 3A_n41A CH509202 @ 23.79 dBm 3A_n41A CH518598 @ 25.79 dBm 3A_n41A CH5280008 @ 25.73 dBm 410.1 414.7 418.2 483.8 470.7 478.2 584.2 517.9 555.1 784.5 792.7 807.2 691.2 672.4 701.8 778.0 585.3 573.0 584.1 570.6 614.0 626.2 979.0 1031.0 1043.0 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 102 / 135 Automotive Module Series 5A_n41A CH509202 @ 22.64 dBm 5A_n41A CH518598 @ 22.88 dBm 5A_n41A CH5280008 @ 22.43 dBm 8A_n41A CH509202 @ 22.70 dBm 8A_n41A CH518598 @ 23.13 dBm 8A_n41A CH5280008 @ 22.89 dBm 39A_n41A CH509202 @ 22.85 dBm 39A_n41A CH518598 @ 22.85 dBm 39A_n41A CH5280008 @ 22.85 dBm 40A_n41A CH509202 @ 22.85 dBm 40A_n41A CH518598 @ 22.85 dBm 40A_n41A CH5280008 @ 22.85 dBm 1A_n78A CH623334 @ 22.51 dBm 1A_n78A CH636666 @ 22.72 dBm 1A_n78A CH650000 @ 22.88 dBm 3A_n78A CH623334 @ 25.42 dBm 3A_n78A CH636666 @ 25.45 dBm 3A_n78A CH650000 @ 25.45 dBm 5A_n78A CH623334 @ 22.95 dBm 5A_n78A CH636666 @ 23.09 dBm 5A_n78A CH650000 @ 23.16 dBm 7A_n78A CH623334 @ 22.88 dBm 7A_n78A CH636666 @ 23.04 dBm 7A_n78A CH650000 @ 23.18 dBm 8A_n78A CH623334 @ 22.99 dBm 750.0 749.0 769.0 787.0 785.0 805.0 652.0 736.0 858.0 590.0 591.0 581.0 781.0 805.0 854.0 1069.0 1069.0 1093.0 761.0 745.0 732.0 893.0 872.0 921.0 786.0 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 103 / 135 Automotive Module Series 8A_n78A CH636666 @ 23.13 dBm 8A_n78A CH650000 @ 23.21 dBm 38A_n78A CH623334 @ 23.04 dBm 38A_n78A CH636666 @ 23.16 dBm 38A_n78A CH650000 @ 23.25 dBm 40A_n78A CH623334 @ 22.80 dBm 40A_n78A CH636666 @ 22.97 dBm 40A_n78A CH650000 @ 23.09 dBm 41A_n78A CH623334 @ 23.00 dBm 41A_n78A CH636666 @ 23.16 dBm 41A_n78A CH650000 @ 23.28 dBm 782.0 829.0 629.0 604.0 651.0 612.0 595.0 652.0 623.0 605.0 652.0 6.3.2. AG568N-EU Power Consumption Table 52: AG568N-EU Power Consumption (25 C, 3.8 V Power Supply) Description Conditions OFF state Power down AT+CFUN=0 AT+CFUN=4 EGSM900 DRX = 2 EGSM900 DRX = 5 Sleep state EGSM900 DRX = 9 DCS1800 DRX = 2 DCS1800 DRX = 5 DCS1800 DRX = 9 WCDMA @ DRX = 0.64 s Typ. 53 TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA Unit A mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 104 / 135 Automotive Module Series WCDMA @ DRX = 1.28 s WCDMA @ DRX = 2.56 s WCDMA @ DRX = 5.12 s LTE-FDD @ DRX = 0.32 s LTE-FDD @ DRX = 0.64 s LTE-FDD @ DRX = 1.28 s LTE-FDD @ DRX = 2.56 s LTE-TDD @ DRX = 0.32 s LTE-TDD @ DRX = 0.64 s LTE-TDD @ DRX = 1.28 s LTE-TDD @ DRX = 2.56 s 5G NR FDD @ DRX = 0.32 s 5G NR FDD @ DRX = 0.64 s 5G NR FDD @ DRX = 1.28 s 5G NR FDD @ DRX = 2.56 s 5G NR TDD @ DRX = 0.32 s 5G NR TDD @ DRX = 0.64 s 5G NR TDD @ DRX = 1.28 s 5G NR TDD @ DRX = 2.56 s EGSM900 CH62 @ DRX = 5 EGSM900 CH62 @ DRX = 5 (USB active) WCDMA @ Paging Frame = 64 Idle state TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD WCDMA @ Paging Frame = 64 (USB active) TBD LTE-FDD @ DRX = 0. 64 s LTE-FDD @ DRX = 0. 64 s (USB active) TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 105 / 135 Automotive Module Series LTE-TDD @ DRX = 0. 64 s LTE-TDD @ DRX = 0. 64s (USB active) 5G NR FDD @ DRX = 0.64 s 5G NR FDD @ DRX = 0.64 s (USB active) 5G NR TDD @ DRX = 0.64 s 5G NR TDD @ DRX = 0.64 s (USB active) EGSM900 CH1 PCL = 5 @ TBD dBm EGSM900 CH62 PCL = 5 @ TBD dBm EGSM900 CH62 PCL = 12 @ TBD dBm EGSM900 CH62 PCL = 19 @ TBD dBm EGSM900 CH124 PCL = 5 @ TBD dBm DCS1800 CH512 PCL = 0 @ TBD dBm DCS1800 CH698 PCL = 0 @ TBD dBm DCS1800 CH698 PCL = 7 @ TBD dBm DCS1800 CH698 PCL = 15 @ TBD dBm DCS1800 CH885 PCL = 0 @ TBD dBm EGSM900 CH1 1DL/4UL @ TBD dBm EGSM900 CH62 4DL/1UL @ TBD dBm EGSM900 CH62 3DL/2UL @ TBD dBm EGSM900 CH62 2DL/3UL @ TBD dBm EGSM900 CH62 1DL/4UL @ TBD dBm EGSM900 CH124 1DL/4UL @ TBD dBm DCS1800 CH512 1DL/4UL @ TBD dBm DCS1800 CH698 4DL/1UL @ TBD dBm DCS1800 CH698 3DL/2UL @ TBD dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD GSM voice call GPRS data transfer

(GNSS OFF) mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 106 / 135 Automotive Module Series DCS1800 CH698 2DL/3UL @ TBD dBm DCS1800 CH698 1DL/4UL @ TBD dBm DCS1800 CH885 1DL/4UL @ TBD dBm EGSM900 CH1 1DL/4UL @ TBD dBm EGSM900 CH62 4DL/1UL @ TBD dBm EGSM900 CH62 3DL/2UL @ TBD dBm EGSM900 CH62 2DL/3UL @ TBD dBm EGSM900 CH62 1DL/4UL @ TBD dBm EGSM900 CH124 1DL/4UL @ TBD dBm DCS1800 CH512 1DL/4UL @ TBD dBm DCS1800 CH698 4DL/1UL @ TBD dBm DCS1800 CH698 3DL/2UL @ TBD dBm DCS1800 CH698 2DL/3UL @ TBD dBm DCS1800 CH698 1DL/4UL @ TBD dBm DCS1800 CH885 1DL/4UL @ TBD dBm WCDMA B1 CH10562 @ TBD dBm WCDMA B1 CH10700 @ TBD dBm WCDMA B1 CH10838 @ TBD dBm WCDMA B3 CH1162 @ TBD dBm WCDMA B3 CH1338 @ TBD dBm WCDMA B3 CH1513 @ TBD dBm WCDMA B5 CH4357 @ TBD dBm WCDMA B5 CH4408 @ TBD dBm WCDMA B5 CH4458 @ TBD dBm WCDMA B8 CH2937 @ TBD dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD EDGE data transfer

(GNSS OFF) WCDMA voice call mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 107 / 135 Automotive Module Series WCDMA B8 CH3012 @ TBD dBm WCDMA B8 CH3088 @ TBD dBm TBD TBD WCDMA B1 HSDPA CH10562 @ TBD dBm TBD WCDMA B1 HSDPA CH10700 @ TBD dBm TBD WCDMA B1 HSDPA CH10838 @ TBD dBm TBD WCDMA B3 HSDPA CH1162 @ TBD dBm WCDMA B3 HSDPA CH1338 @ TBD dBm WCDMA B3 HSDPA CH1513 @ TBD dBm WCDMA B5 HSDPA CH4357 @ TBD dBm WCDMA B5 HSDPA CH4408 @ TBD dBm WCDMA B5 HSDPA CH4458 @ TBD dBm WCDMA B8 HSDPA CH2937 @ TBD dBm WCDMA B8 HSDPA CH3012 @ TBD dBm WCDMA B8 HSDPA CH3088 @ TBD dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD WCDMA B1 HSUPA CH10562 @ TBD dBm TBD WCDMA B1 HSUPA CH10700 @ TBD dBm TBD WCDMA B1 HSUPA CH10838 @ TBD dBm TBD WCDMA B3 HSUPA CH1162 @ TBD dBm WCDMA B3 HSUPA CH1338 @ TBD dBm WCDMA B3 HSUPA CH1513 @ TBD dBm WCDMA B5 HSUPA CH4357 @ TBD dBm WCDMA B5 HSUPA CH4408 @ TBD dBm WCDMA B5 HSUPA CH4458 @ TBD dBm WCDMA B8 HSUPA CH2937 @ TBD dBm WCDMA B8 HSUPA CH3012 @ TBD dBm TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA WCDMA data transfer (GNSS OFF) AG568N_Series_QuecOpen_Hardware_Design 108 / 135 Automotive Module Series WCDMA B8 HSUPA CH3088 @ TBD dBm LTE-FDD B1 CH100 @ TBD dBm LTE-FDD B1 CH300 @ TBD dBm LTE-FDD B1 CH500 @ TBD dBm LTE-FDD B3 CH1300 @ TBD dBm LTE-FDD B3 CH1575 @ TBD dBm LTE-FDD B3 CH1850 @ TBD dBm LTE-FDD B5 CH2450 @ TBD dBm LTE-FDD B5 CH2525 @ TBD dBm LTE-FDD B5 CH2600 @ TBD dBm LTE-FDD B7 CH2850 @ TBD dBm LTE-FDD B7 CH3100 @ TBD dBm LTE-FDD B7 CH3350 @ TBD dBm LTE-FDD B8 CH3500 @ TBD dBm LTE-FDD B8 CH3625 @ TBD dBm LTE-FDD B8 CH3750 @ TBD dBm LTE-TDD B20 CH6250 @ TBD dBm LTE-TDD B20 CH6300 @ TBD dBm LTE-TDD B20 CH6350 @ TBD dBm LTE-TDD B28 CH9310 @ TBD dBm LTE-TDD B28 CH9435 @ TBD dBm LTE-TDD B28 CH9560 @ TBD dBm LTE-TDD B38 CH37850 @ TBD dBm LTE-TDD B38 CH38000 @ TBD dBm LTE-TDD B38 CH38150 @ TBD dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA LTE data transfer

(GNSS OFF) AG568N_Series_QuecOpen_Hardware_Design 109 / 135 Automotive Module Series LTE-TDD B40 CH38750 @ TBD dBm LTE-TDD B40 CH39150 @ TBD dBm LTE-TDD B40 CH39550 @ TBD dBm n1A CH426000 @ TBD dBm n1A CH428000 @ TBD dBm n1A CH430000 @ TBD dBm n3A CH364000 @ TBD dBm n3A CH368500 @ TBD dBm n3A CH373000 @ TBD dBm n7A CH526000 @ TBD dBm n7A CH531000 @ TBD dBm n7A CH536000 @ TBD dBm n8A CH187000 @ TBD dBm 5G NR SA data transfer (GNSS OFF) n8A CH188500 @ TBD dBm n8A CH190000 @ TBD dBm n20A CH160200 @ TBD dBm n20A CH161200 @ TBD dBm n20A CH162200 @ TBD dBm n28A CH154600 @ TBD dBm n28A CH156100 @ TBD dBm n28A CH157600 @ TBD dBm n77A CH623334 @ TBD dBm n77A CH650000 @ TBD dBm n77A CH676666 @ TBD dBm n78A CH623334 @ TBD dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 110 / 135 Automotive Module Series n78A CH636666 @ TBD dBm n78A CH650000 @ TBD dBm 1A_n77A CH623334 @ TBD dBm 1A_n77A CH650000 @ TBD dBm 1A_n77A CH676666 @ TBD dBm 3A_n77A CH623334 @ TBD dBm 3A_n77A CH650000 @ TBD dBm 3A_n77A CH676666 @ TBD dBm 5A_n77A CH623334 @ TBD dBm 5A_n77A CH650000 @ TBD dBm 5A_n77A CH676666 @ TBD dBm 8A_n77A CH623334 @ TBD dBm 8A_n77A CH650000 @ TBD dBm 8A_n77A CH676666 @ TBD dBm 20A_n77A CH623334 @ TBD dBm 20A_n77A CH650000 @ TBD dBm 20A_n77A CH676666 @ TBD dBm 28A_n77A CH623334 @ TBD dBm 28A_n77A CH650000 @ TBD dBm 28A_n77A CH676666 @ TBD dBm 40A_n77A CH623334 @ TBD dBm 40A_n77A CH650000 @ TBD dBm 40A_n77A CH676666 @ TBD dBm 1A_n78A CH623334 @ TBD dBm 1A_n78A CH636666 @ TBD dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 5G NR NSA data transfer (GNSS OFF) AG568N_Series_QuecOpen_Hardware_Design 111 / 135 Automotive Module Series 1A_n78A CH650000 @ TBD dBm 3A_n78A CH623334 @ TBD dBm 3A_n78A CH636666 @ TBD dBm 3A_n78A CH650000 @ TBD dBm 5A_n78A CH623334 @ TBD dBm 5A_n78A CH636666 @ TBD dBm 5A_n78A CH650000 @ TBD dBm 7A_n78A CH623334 @ TBD dBm 7A_n78A CH636666 @ TBD dBm 7A_n78A CH650000 @ TBD dBm 8A_n78A CH623334 @ TBD dBm 8A_n78A CH636666 @ TBD dBm 8A_n78A CH650000 @ TBD dBm 20A_n78A CH623334 @ TBD dBm 20A_n78A CH636666 @ TBD dBm 20A_n78A CH650000 @ TBD dBm 28A_n78A CH623334 @ TBD dBm 28A_n78A CH636666 @ TBD dBm 28A_n78A CH650000 @ TBD dBm 38A_n78A CH623334 @ TBD dBm 38A_n78A CH636666 @ TBD dBm 38A_n78A CH650000 @ TBD dBm 40A_n78A CH623334 @ TBD dBm 40A_n78A CH636666 @ TBD dBm 40A_n78A CH650000 @ TBD dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 112 / 135 Automotive Module Series 6.3.3. AG568N-NA Power Consumption Table 53: AG568N-NA Power Consumption (25 C, 3.8 V Power Supply) Description Conditions OFF state Power down Sleep state AT+CFUN=0 AT+CFUN=4 LTE-FDD @ DRX = 0.32 s LTE-FDD @ DRX = 0.64 s LTE-FDD @ DRX = 1.28 s LTE-FDD @ DRX = 2.56 s 5G NR FDD @ DRX = 0.32 s 5G NR FDD @ DRX = 0.64 s 5G NR FDD @ DRX = 1.28 s 5G NR FDD @ DRX = 2.56 s 5G NR TDD @ DRX = 0.32 s 5G NR TDD @ DRX = 0.64 s 5G NR TDD @ DRX = 1.28 s 5G NR TDD @ DRX = 2.56 s LTE-FDD @ DRX = 0. 64 s Typ. 52 2.865 2.955 5.843 4.378 3.695 3.360 10.079 6.515 4.850 4.546 11.080 7.083 5.156 4.797 143.49 Idle state LTE-FDD @ DRX = 0. 64 s (USB active) 152.00 5G NR FDD @ DRX = 0.64 s 144.95 5G NR FDD @ DRX = 0.64 s (USB active) 153.47 5G NR TDD @ DRX = 0.64 s 142.74 5G NR TDD @ DRX = 0.64 s (USB active) 151.00 LTE data transfer LTE-FDD B2 CH700 @ 22.35 dBm 935 Unit A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 113 / 135 Automotive Module Series

(GNSS OFF) LTE-FDD B2 CH900 @ 22.42 dBm LTE-FDD B2 CH1100 @ 22.44 dBm LTE-FDD B4 CH2000 @ 22.36 dBm LTE-FDD B4 CH2175 @ 22.43 dBm LTE-FDD B4 CH2350 @ 22.40 dBm LTE-FDD B5 CH2450 @ 22.47 dBm LTE-FDD B5 CH2525 @ 22.50 dBm LTE-FDD B5 CH2600 @ 22.52 dBm LTE-FDD B12 CH5060 @ TBD dBm LTE-FDD B12 CH5095 @ TBD dBm LTE-FDD B12 CH5130 @ TBD dBm LTE-FDD B66 CH66536 @ 22.37 dBm LTE-FDD B66 CH66886 @ 22.43 dBm LTE-FDD B66 CH67036 @ 22.44 dBm n2A CH388000 @ 23.15 dBm n2A CH392000 @ 23.14 dBm n2A CH396000 @ 23.18 dBm n5A CH175800 @ 22.85 dBm n5A CH176300 @ 22.87 dBm n5A CH176800 @ 22.85 dBm n12A CH147300 @ 22.86 dBm n12A CH147500 @ 22.84 dBm n12A CH147700 @ 22.84 dBm n66A CH426000 @ 23.32 dBm n66A CH429000 @ 23.31 dBm 5G NR SA data transfer (GNSS OFF) 804 920 901 836 830 724 832 837 747 758 742 894 855 828 980 925 969 1013 1058 1065 905 897 895 912 900 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 114 / 135 Automotive Module Series n66A CH432000 @ 23.30 dBm n77A CH623334@ 25.63 dBm n77A CH650000@ 25.86 dBm n77A CH676666@ 25.88 dBm n78A CH623334 @ 26.03 dBm n78A CH636666 @ 26.18 dBm n78A CH650000 @ 26.03 dBm 5A_n2A CH388000 @ 22.66 dBm 5A_n2A CH392000 @ 23.03 dBm 5A_n2A CH396000 @ 22.95 dBm 2A_n77A CH623334 @ 22.56 dBm 2A_n77A CH650000 @ 22.76 dBm 2A_n77A CH6766666 @ 22.86 dBm 5A_n77A CH623334 @ 22.62 dBm 5A_n77A CH650000 @ 22.88 dBm 5G NR NSA data transfer (GNSS OFF) 5A_n77A CH6766666 @ 22.98 dBm 12A_n77A CH623334 @ 22.87 dBm 12A_n77A CH650000 @ 22.96 dBm 12A_n77A CH6766666 @ 23.08 dBm 66A_n77A CH623334 @ 22.63 dBm 66A_n77A CH650000 @ 22.72 dBm 66A_n77A CH6766666 @ 22.90 dBm 12A_n2A CH388000 @ 23.08 dBm 12A_n2A CH392000 @ 22.70 dBm 12A_n2A CH396000 @ 22.99 dBm 922 552 601 625 568 597 618 1095 1074 1090 815 810 815 865 851 845 816 795 788 820 808 812 1056 1027 1037 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 115 / 135 Automotive Module Series 2A_n5A CH175800 @ 22.52 dBm 2A_n5A CH176300 @ 22.70 dBm 2A_n5A CH176800 @ 22.62 dBm 66A_n5A CH175800 @22.65 dBm 66A_n5A CH176300 @ 22.64 dBm 66A_n5A CH176800 @ 22.60 dBm 5A_n66A CH426000 @ 22.67 dBm 5A_n66A CH429000 @ 22.85 dBm 5A_n66A CH432000 @ 22.94 dBm 12A_n66A CH426000 @ 23.08dBm 12A_n66A CH429000 @ 22.61 dBm 12A_n66A CH432000 @ 22.64 dBm 1023 1048 1053 1046 1062 1067 1074 1080 1076 1020 1029 1024 mA mA mA mA mA mA mA mA mA mA mA mA 6.3.4. AG568N-ROW Power Consumption Table 54: AG568N-ROW Power Consumption (25 C, 3.8 V Power Supply) Description Conditions Typ. Unit OFF state Power down Sleep state AT+CFUN=0 AT+CFUN=4 WCDMA @ DRX = 0.64 s WCDMA @ DRX = 1.28 s WCDMA @ DRX = 2.56 s WCDMA @ DRX = 5.12s LTE-FDD @ DRX = 0.32 s LTE-FDD @ DRX = 0.64 s 46 3.877 3.890 5.391 4.638 4.238 4.099 6.941 5.504 A mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 116 / 135 Automotive Module Series LTE-FDD @ DRX = 1.28 s LTE-FDD @ DRX = 2.56 s 5G NR FDD @ DRX = 0.32 s 5G NR FDD @ DRX = 0.64 s 5G NR FDD @ DRX = 1.28 s 5G NR FDD @ DRX = 2.56 s 4.828 4.530 TBD TBD TBD TBD mA mA mA mA mA mA 5G NR TDD @ DRX = 0.32 s 11.735 mA 5G NR TDD @ DRX = 0.64 s 5G NR TDD @ DRX = 1.28 s 5G NR TDD @ DRX = 2.56 s 8.143 5.706 5.448 mA mA mA WCDMA @ Paging Frame = 64 148.65 mA WCDMA @ Paging Frame = 64 (USB active) 157.66 mA LTE-FDD @ DRX = 0.64 s 148.15 mA LTE-FDD @ DRX = 0.64 s (USB active) 159.57 mA 5G NR FDD @ DRX = 0.64 s 5G NR FDD @ DRX = 0.64 s (USB active) TBD TBD mA mA 5G NR TDD @ DRX = 0.64 s 153.07 mA 5G NR TDD @ DRX = 0.64 s (USB active) 156.68 mA Idle state WCDMA voice call WCDMA B1 CH10562 @ 23.17dBm WCDMA B1 CH10700 @ 23.09 dBm WCDMA B1 CH10838 @ 23.05 dBm WCDMA B3 CH1162 @ 22.69 dBm WCDMA B3 CH1338 @ 22.61 dBm WCDMA B3 CH1513 @ 22.71 dBm WCDMA data WCDMA B1 HSDPA CH10562 @ 22.04 dBm 756 774 802 752 677 790 696 mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 117 / 135 Automotive Module Series transfer (GNSS OFF) WCDMA B1 HSDPA CH10700 @ 21.96 dBm WCDMA B1 HSDPA CH10838 @ 21.92 dBm WCDMA B3 HSDPA CH1162 @ 21.82 dBm WCDMA B3 HSDPA CH1338 @ 21.83 dBm WCDMA B3 HSDPA CH1513 @ 21.94 dBm WCDMA B1 HSUPA CH10562 @ 21.62 dBm WCDMA B1 HSUPA CH10700 @ 21.56 dBm WCDMA B1 HSUPA CH10838 @ 21.47 dBm WCDMA B3 HSUPA CH1162 @ 21.16 dBm WCDMA B3 HSUPA CH1338 @ 21.05 dBm WCDMA B3 HSUPA CH1513 @ 21.19 dBm LTE-FDD B1 CH100 @ 22.79 dBm LTE-FDD B1 CH300 @ 22.75 dBm LTE-FDD B1 CH500 @ 22.74 dBm LTE-FDD B3 CH1300 @ 22.49 dBm LTE-FDD B3 CH1575 @ 22.40 dBm LTE-FDD B3 CH1850 @ 22.46 dBm LTE-FDD B19 CH6075@ 22.60 dBm LTE-FDD B21 CH6525 @ 22.17 dBm LTE-FDD B28 CH9310 @ 22.52 dBm LTE-FDD B28 CH9435 @ 22.47 dBm LTE-FDD B28 CH9560 @ 22.52 dBm LTE data transfer

(GNSS OFF) 5G NR SA data transfer (GNSS OFF) n28A CH154600 @ 22.59 dBm n28A CH157600 @ 22.42 dBm n77A CH623334 @ 25.87 dBm 715 725 696 681 677 640 659 673 653 620 684 760 786 791 804 812 866 751 740 754 801 730 730 804 576 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA AG568N_Series_QuecOpen_Hardware_Design 118 / 135 Automotive Module Series n77A CH650000 @ 25.93 dBm n77A CH676666 @ 25.65 dBm n78A CH623334 @ 26.35 dBm n78A CH636666 @ 26.42 dBm n78A CH650000 @ 26.43 dBm n79A CH697094 @ 22.56 dBm n79A CH713990 @ 22.58 dBm n79A CH729468 @ 26.74 dBm 19A_n77A CH623334 @ 22.82 dBm 19A_n77A CH650000 @ 22.92 dBm 19A_n77A CH676666 @ 22.70 dBm 21A_n77A CH623334 @ 22.64 dBm 21A_n77A CH650000 @ 22.68 dBm 21A_n77A CH676666 @ 22.66 dBm 1A_n78A CH623334 @ 23.04 dBm 1A_n78A CH636666 @ 23.03 dBm 1A_n78A CH650000 @ 23.06 dBm 3A_n78A CH623334 @ 25.88 dBm 3A_n78A CH636666 @ 25.95 dBm 3A_n78A CH650000 @ 25.95 dBm 19A_n78A CH623334 @ 23.04 dBm 19A_n78A CH636666 @ 23.10 dBm 19A_n78A CH650000 @ 23.12 dBm 21A_n78A CH623334 @ 22.87 dBm 21A_n78A CH636666 @ 22.94 dBm 596 563 596 578 618 587 587 632 798 788 778 739 724 711 867 844 854 1137 1119 1140 814 783 793 743 717 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 5G NR NSA data transfer (GNSS OFF) AG568N_Series_QuecOpen_Hardware_Design 119 / 135 Automotive Module Series 21A_n78A CH650000 @ 22.93 dBm 28A_n78A CH623334 @ 22.93 dBm 28A_n78A CH636666 @ 22.91dBm 28A_n78A CH650000 @ 23.00 dBm 1A_n79A CH697094 @ 23.40 dBm 1A_n79A CH713990 @ 23.38 dBm 1A_n79A CH729468 @ 23.48 dBm 3A_n79A CH697094 @ 23.28 dBm 3A_n79A CH713990 @ 23.27 dBm 3A_n79A CH729468 @ 23.27 dBm 19A_n79A CH697094 @ 23.50 dBm 19A_n79A CH713990 @ 23.51 dBm 19A_n79A CH729468 @ 23.56 dBm 21A_n79A CH697094 @ 23.28 dBm 21A_n79A CH713990 @ 23.24 dBm 21A_n79A CH729468 @ 23.32 dBm 28A_n79A CH697094 @ 23.43 dBm 28A_n79A CH713990 @ 23.39 dBm 28A_n79A CH729468 @ 23.42 dBm 727 808 782 794 883 880 888 835 836 843 819 819 826 756 753 760 818 818 825 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 6.4. ESD Protection Static electricity occurs naturally and it may damage the module. Therefore, applying proper ESD countermeasures and handling methods is imperative. For example, wear anti-static gloves during the development, production, assembly and testing of the module; add ESD protection components to the ESD sensitive interfaces and points in the product design. AG568N_Series_QuecOpen_Hardware_Design 120 / 135 Automotive Module Series Table 55: ESD Characteristics (Temperature: 2530 C, Humidity: 40 5 %) Tested Interfaces Contact Discharge Air Discharge Unit VBAT, GND Antenna Interfaces Other Interfaces 6 5 0.5 10 10 1 kV kV kV 6.5. Operating and Storage Temperatures Table 56: Operating and Storage Temperatures Parameter Operating temperature range 20 Min.

-35 Extended operating temperature range 21

-40 eCall temperature range 22 Storage temperature range

-40

-40 Typ.

+25

Max. Unit

+75

+85

+95

+95 C C C C 6.6. Thermal Dissipation The module offers the best performance when all internal IC chips are working within their operating temperatures. When the IC chip reaches or exceeds the maximum junction temperature, the module may still work but the performance and function (such as RF output power, data rate, etc.) will be affected to a certain extent. Therefore, the thermal design should be maximally optimized to ensure all internal IC chips always work within the recommended operating temperature range. The following principles for thermal consideration are provided for reference:

20 Within the operating temperature range, the module meets 3GPP specifications. 21 Within the extended temperature range, the module remains the ability to establish and maintain functions such as voice, SMS, data transmission, eCall*, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may exceed the specified tolerances of 3GPP. When the temperature returns to the operating temperature range, the module meets 3GPP specifications again. 22 Within eCall temperature range, the eCall function must be functional until the module is broken. When the ambient temperature is between 75 C and 95 C and the module temperature has reached the threshold value, the module will trigger protective measures (such as reduce power, decrease throughput, unregister the device, etc.) to ensure the full function of eCall. AG568N_Series_QuecOpen_Hardware_Design 121 / 135 Automotive Module Series Keep the module away from heat sources on your PCB, especially high-power components such as processor, power amplifier, and power supply. Maintain the integrity of the PCB copper layer and drill as many thermal vias as possible. Follow the principles below when the heatsink is necessary:

- Do not place large size components in the area where the module is mounted on your PCB to reserve enough place for heatsink installation.

- Attach the heatsink to the shielding cover of the module; In general, the base plate area of the heatsink should be larger than the module area to cover the module completely;

- Choose the heatsink with adequate fins to dissipate heat;

- Choose a TIM (Thermal Interface Material) with high thermal conductivity, good softness and good wettability and place it between the heatsink and the module;

- Fasten the heatsink with four screws to ensure that it is in close contact with the module to prevent the heatsink from falling off during the drop, vibration test, or transportation. Figure 38: Placement and Fixing of the Heatsink NOTE 1. The module offers the best performance when the internal BB chip stays below 105C. When the maximum temperature of the BB chip reaches or exceeds 105C, the module works normal but provides reduced performance (such as RF output power, data rate, etc.). When the maximum BB chip temperature reaches or exceeds 115C, the module will disconnect from the network, and it will recover to network connected state after the maximum temperature falls below 115C. Therefore, the thermal design should be maximally optimized to make sure the maximum BB chip temperature always maintains below 105C. Customers can execute related software command to get the maximum BB chip temperature. 2. For more detailed guidelines on thermal design, see document [7]. AG568N_Series_QuecOpen_Hardware_Design 122 / 135 PCBHeatsinkTIMModuleScrewTIMModuleHeatsinkPCB Automotive Module Series 7 Mechanical Information This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are 0.2 mm unless otherwise specified. 7.1. Mechanical Dimensions Pin 1 Figure 39: Module Top and Side Dimensions (Unit: mm) AG568N_Series_QuecOpen_Hardware_Design 123 / 135 Automotive Module Series Figure 40: Module Bottom Dimensions (Bottom View, Unit: mm) Pin 1 NOTE The package warpage level of the module conforms to JEITA ED-7306 standard. AG568N_Series_QuecOpen_Hardware_Design 124 / 135 Automotive Module Series 7.2. Recommended Footprint Pin 1 Figure 41: Recommended Footprint (Top View, Unit: mm) NOTE Keep at least 3 mm between the module and other components on the motherboard to improve soldering quality and maintenance convenience. AG568N_Series_QuecOpen_Hardware_Design 125 / 135 Automotive Module Series 7.3. Top and Bottom Views Figure 42: Top and Bottom Views of the Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. AG568N_Series_QuecOpen_Hardware_Design 126 / 135 Automotive Module Series 8 Storage, Manufacturing & Packaging 8.1. Storage Conditions The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: the temperature should be 23 5 C and the relative humidity should be 3560 %. 2. Shelf life (in a vacuum-sealed packaging): 12 months in Recommended Storage Condition. 3. Floor life: 168 hours 23 in a factory where the temperature is 23 5 C and relative humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g., a dry cabinet). 4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under the following circumstances:

The module is not stored in Recommended Storage Condition;

Violation of the third requirement mentioned above;

Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;

Before module repairing. 5. If needed, the pre-baking should follow the requirements below:

The module should be baked for 8 hours at 120 5 C;

The module must be soldered to PCB within 24 hours after the baking, otherwise it should be put in a dry environment such as in a dry cabinet. 23 This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to, or are not sure to conform to IPC/JEDEC J-STD-033. And do not remove the packages of tremendous modules if they are not ready for soldering. AG568N_Series_QuecOpen_Hardware_Design 127 / 135 Automotive Module Series NOTE 1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to the air is forbidden. 2. Take out the module from the package and put it on high-temperature-resistant fixtures before baking. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure. 3. Pay attention to ESD protection, such as wearing anti-static gloves, when touching the modules. 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. Apply proper force on the squeegee to produce a clean stencil surface on a single pass. To guarantee module soldering quality, the thickness of stencil for the module is recommended to be 0.150.18 mm. For more details, see document [8]. The recommended peak reflow temperature should be 235246 C, with 246 C as the absolute maximum reflow temperature. To avoid damage to the module caused by repeated heating, it is recommended that the module should be mounted only after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below:

Figure 43: Recommended Reflow Soldering Thermal Profile AG568N_Series_QuecOpen_Hardware_Design 128 / 135 Temp. (C)Reflow ZoneSoak Zone246200217235CDBA150100 Ramp-to-soak slope: 03 C/s Cool-down slope: -30 C/s Ramp-up slope: 03 C/s Automotive Module Series Table 57: Recommended Thermal Profile Parameters Factor Soak Zone Recommended Value Ramp-to-soak slope 03 C/s Soak time (between A and B: 150 C and 200 C) 70120 s Reflow Zone Ramp-up slope Reflow time (D: over 217C) Max temperature Cool-down slope Reflow Cycle Max reflow cycle NOTE 03 C/s 4070 s 235246 C

-30 C/s 1 1. The above profile parameter requirements are for the measured temperature of the solder joints. Both the hottest and coldest spots of solder joints on the PCB should meet the above requirements. If a conformal coating is necessary for the module, do not use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module. 2. 3. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the module. 4. Due to the complexity of the SMT process, please contact Quectel Technical Supports in advance for any situation that you are not sure about, or any process (e.g. selective soldering, ultrasonic soldering) that is not mentioned in document [8]. 8.3. Packaging Specifications This chapter describes only the key parameters and process of packaging. All figures below are for reference only. The appearance and structure of the packaging materials are subject to the actual delivery. The module adopts carrier tape packaging and details are as follow:

AG568N_Series_QuecOpen_Hardware_Design 129 / 135 Automotive Module Series 8.3.1. Carrier Tape Dimension details are as follow:

Figure 44: Carrier Tape Dimension Drawing Table 58: Carrier Tape Dimension Table (Unit: mm) W 72 P 64 T A0 B0 K0 0.4 47.5 45.6 4.55 K1 6 F E 34.2 1.75 8.3.2. Plastic Reel Figure 45: Plastic Reel Dimension Drawing AG568N_Series_QuecOpen_Hardware_Design 130 / 135 Automotive Module Series Table 59: Plastic Reel Dimension Table (Unit: mm) D1 380 D2 180 W 72.5 8.3.3. Mounting Direction Figure 46: Mounting Direction 8.3.4. Packaging Process Place the module into the carrier tape and use the cover tape to cover it; then wind the heat-sealed carrier tape to the plastic reel and use for protection. 1 plastic 150 modules. the protective reel can tape load AG568N_Series_QuecOpen_Hardware_Design 131 / 135 Automotive Module Series Place the packaged plastic reel, 1 humidity indicator card and 1 desiccant bag into a vacuum bag, vacuumize it. Place the vacuum-packed plastic reel into the pizza box. Put 4 packaged pizza boxes into 1 carton box and seal it. 1 carton box can pack 600 modules. Figure 47: Packaging Process AG568N_Series_QuecOpen_Hardware_Design 132 / 135 Automotive Module Series 9 Appendix References Table 60: Related Documents Document Name

[1] Quectel_V2X&5G_EVB_User_Guide

[2] Quectel_AG56xN_Series_QuecOpen_Device_Management_API_Reference_Manual

[3] Quectel_AG56xN_Series_QuecOpen_AT_Commands_Manual

[4] Quectel_AG56xN_Series_QuecOpen_Low_Power_Mode_Application_Note

[5] Quectel_AG568N_Series_QuecOpen_Reference_Design

[6] Quectel_RF_Layout_Application_Note

[7] Quectel_Module_Thermal_Design_Guide

[8] Quectel_Module_SMT_Application_Note Table 61: Terms and Abbreviations Abbreviation Description 3GPP 5G NR ADC AMR 3rd Generation Partnership Project 5G New Radio Analog-to-Digital Converter Adaptive Multi-rate AMR-WB Adaptive Multi-Rate Wideband AP API Application Processor Application Program Interface AG568N_Series_QuecOpen_Hardware_Design 133 / 135 Automotive Module Series ASRC bps CA CHAP CS CTS Asynchronous Sampling Rate Converter Bits Per Second Carrier Aggregation Challenge Handshake Authentication Protocol Coding Scheme Clear To Send DC-HSDPA Dual-carrier High Speed Downlink Packet Access DL DRX DSDS DTE EDGE EFR EGSM EMI eMMC ESD EVB FDD FR Downlink Discontinuous Reception Dual SIM Dual Standby Data Terminal Equipment Enhanced Data Rates for GSM Evolution Enhanced Full Rate Extended GSM900 Band (including standard GSM900 band) Electromagnetic Interference Embedded Multimedia Card Electrostatic Discharge Evaluation Board Frequency Division Duplex Full Rate GLONASS Global Navigation Satellite System (Russia) GMSK GNSS GPIOs GPRS Gaussian Minimum Shift Keying Global Navigation Satellite System General-purpose Input/Output General Packet Radio Service AG568N_Series_QuecOpen_Hardware_Design 134 / 135 Automotive Module Series GPS GSM HB HPUE HR HSDPA HSPA HSUPA IC I2C I2S I/O Inom LB LDO LED LGA LMHB LNA LTE MAC MB MCU MDIO ME Global Positioning System Global System for Mobile Communications High Band High Power User Equipment Half Rate High Speed Downlink Packet Access High Speed Packet Access High Speed Uplink Packet Access Integrated Circuit Inter-Integrated Circuit Inter-IC Sound Input/Output Nominal Current Low Band Low-dropout Regulator Light Emitting Diode Land Grid Array Low/Middle/High Band Low Noise Amplifier Long Term Evolution Media Access Control Middle Band Microcontroller Unit Management Data Input/Output Mobile Equipment AG568N_Series_QuecOpen_Hardware_Design 135 / 135 Automotive Module Series Middle/High Band Multiple Input Multiple Output Mobile Originated Mobile Terminated Multi-layer Ceramic Chip Capacitor NMEA (National Marine Electronics Association) 0183 Interface Standard Non-Stand Alone Printed Circuit Board Peripheral Component Interconnect Express Pulse Code Modulation Protocol Data Unit Physical Layer Power Management Integrated Circuit Phase Shift Keying Quadrature Amplitude Modulation Quadrature Phase Shift Keying Radio Frequency Reduced Gigabit Media Independent Interface Right Hand Circularly Polarized Receive Stand Alone Sub-Carrier Space Secure Digital Input/Output Single Input Multiple Output Surface Mount Device MHB MIMO MO MT MLCC NMEA NSA PCB PCIe PCM PDU PHY PMIC PSK QAM QPSK RF RGMII RHCP Rx SA SCS SDIO SIMO SMD AG568N_Series_QuecOpen_Hardware_Design 136 / 135 Automotive Module Series SMS SPI TDD Short Message Service Serial Peripheral Interface Time Division Duplexing TD-SCDMA Time Division-Synchronous Code Division Multiple Access TRX Tx UART UL UMTS USB Transmit & Receive Transmit Universal Asynchronous Receiver/Transmitter Uplink Universal Mobile Telecommunications System Universal Serial Bus

(U)SIM Universal Subscriber Identity Module V2I V2P V2V V2X VBAT Vmax Vnom Vmin VIHmax VIHmin VILmax VILmin VImax VImin Vehicle-to-Infrastructure Vehicle to Pedestrian Vehicle-to-Vehicle Vehicle-to-Everything Voltage at Battery (Pin) Maximum Voltage Value Nominal Voltage Value Minimum Voltage Value Maximum High-level Input Voltage Minimum High-level Input Voltage Maximum Low-level Input Voltage Minimum Low-level Input Voltage Absolute Maximum Input Voltage Absolute Minimum Input Voltage AG568N_Series_QuecOpen_Hardware_Design 137 / 135 Automotive Module Series VOHmax VOHmin VOLmax VOLmin VSWR Maximum High-level Output Voltage Minimum High-level Output Voltage Maximum Low-level Output Voltage Minimum Low-level Output Voltage Voltage Standing Wave Ratio WCDMA Wideband Code Division Multiple Access Wi-Fi WLAN Wireless Fidelity Wireless Local Area Network AG568N_Series_QuecOpen_Hardware_Design 138 / 135

 

 

 

 

 

 

 

 

 

 

DQUWEcrTrere AG568N-NA Q2-AXXXX AB AG568NNAAB-M28-C GADQ FCC ID:XMR2022AG568NNA IC:10224A-022AG568NNA SN: XXXXXXXXXXXXKXX IMEI:

Label Location

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Federal Communications Commission Authorization and Evaluation Division 7435 Oakland Mills Road Columbia, MD 21046 USA Date: 06-01-2023 Ref: Attestation Statements Part 2.911(d)(5)(i) Filing FCC ID: XMR2022AG568NNA

[Quectel Wireless Solutions Co., Ltd.] (the applicant) certifies that the equipment for which authorization is sought is not covered equipment prohibited from receiving an equipment authorization pursuant to section 2.903 of the FCC rules. Sincerely, Jean Hu Rev 1/26/2023 Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Federal Communications Commission Authorization and Evaluation Division 7435 Oakland Mills Road Columbia, MD 21046 USA Date: 06-01-2023 Ref: Attestation Statements Part 2.911(d)(5)(ii) Filing FCC ID: XMR2022AG568NNA

[Quectel Wireless Solutions Co., Ltd.] (the applicant) certifies that, as of the date of the filing of the application, the applicant is not identified on the Covered List as an entity producing covered equipment. Sincerely, Jean Hu Rev 1/26/2023

 

 

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Federal Communications Commission Authorization and Evaluation Division Confidentiality Request regarding application for certification of FCC ID:XMR2022AG568NNA. Pursuant to Sections 0.457 and 0.459 of the Commissions Rules, we hereby request confidential treatment of information accompanying this application as outlined below:

Exhibit Type

(1. Block Diagram; 2.SCH; 3.Operational description; 4.BOM.;5.Tune-up Procedure) File Name

(Block Diagram, SCH, Operational description, BOM, FCC Tune Up) The above materials contain trade secrets and proprietary information not customarily released to the public. The public disclosure of these materials may be harmful to the applicant and provide unjustified benefits to its competitors. The applicant understands that pursuant to Section 0.457 of the Rules, disclosure of this application and all accompanying documentation will not be made before the date of the Grant for this application. We are requesting the commission to grant short-term confidentiality request on the following attachment(s) for 180 days after the grant as outlined in Public Notice DA 04-1705. Exhibit Type

(External Photos, Internal Photos, Setup Photos, Manual) File Name

(Appendix A.1-External Photos.pdf; Appendix A.2-Internal Photos.pdf; Appendix A.2 PCB Setup Photos; Manual;) Sincerely, Name: Jean Hu Title: Certification Manager Rev 11/20/07

 

 

WARNING:pdfminer.pdfpage:The PDF <_io.BufferedReader name='/Volumes/Scratch/Incoming/eg-scratch/6586546.pdf'> contains a metadata field indicating that it should not allow text extraction. Ignoring this field and proceeding. Use the check_extractable if you want to raise an error in this case RF_734_02 04 April 16 Modular Approval Request FCC (KDB 996369 D01 & Part 15.212) FCC ID: XMR2022AG568NNA Items to be covered by Single modular transmitters. 1. The modular transmitter must have its own RF shielding. 2. 3. 4. 5. The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with Part 15 requirements under conditions of excessive data rates or over-modulation. The modular transmitter must have its own power supply regulation. The modular transmitter must comply with the antenna requirements of Section 15.203 and 15.204(b)(c). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing. This is intended to demonstrate that the module is capable of complying with Part 15 emission limits regardless of the device into which it is eventually installed. 6. The modular transmitter must be equipped with either a permanently affixed label or must be capable of electronically displaying its FCC identification number in accordance with 15.212 (a)(1)(vi)(A) / (B). 7. The modular transmitter must comply with any specific rule or operating requirements applicable to the transmitter and the manufacturer must provide adequate instructions along with the module to explain any such requirements. A copy of these instructions must be included in the application for equipment authorization. For example, timing requirements that must be met before a transmitter is authorized for operation under Section 15.231. For instance, data transmission is prohibited, except for operation under Section 15.231(e), in which case there are separate field strength level and timing requirements. Compliance with these requirements must be assured. there are very strict operational and 8. The modular transmitter must comply with any applicable RF exposure requirements. For example, FCC Rules in Sections 1.1310, 2.1091, 2.1093, and specific Sections of Part 15, including 15.319(i), 15.407(f), 15.253(f) and 15.255(g), require that Unlicensed PCS, UNII and millimeter wave devices perform routine environmental evaluation for RF Exposure to demonstrate compliance. In addition, spread spectrum transmitters operating under Section 15.247 are required to address RF Exposure compliance. Modular transmitters approved under other Sections of Part 15, when necessary, may also need to address certain RF Exposure concerns, typically by providing specific installation and operating instructions for users, installers and other interested parties to ensure compliance. Answer from applicant Yes, please see exhibition external photos Yes, the modular has buffer modulation /data inputs Yes, please see the SCH.pdf Yes, the requirements of antenna connector and spurious emission have been fulfilled. Please refer to the test report exhibition. Yes, please refer to the setup photo exhibition for the stand-alone configuration Yes, the module will be label with its own FCC ID, and the instruction on the labelling rule of the end product has been stated in the user manual of this module. Please refer to the label and user manual exhibition. Yes, the required FCC rule has been fulfilled and all the instruction for maintaining compliance have been clearly stated in the user manual. Yes, please refer exhibition RF exposure for the compliance of MPE RF exposure rule. Note: A limited modular approval (LMA) may be granted for single modular transmitters that comply partially with the requirements above. RF_734_02 04 April 16 Name and surname of applicant (or authorized representative):

Signature:

Date:

2023/06/01.. City:

Name:

Email:

Shanghai .. Jean Hu .. jean.hu@quectel.com. Signature:

 

 

RF_160, Issue 04 Quectel Wireless Solutions Co., Ltd. Declaration of Authorization We Name:

Address:

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 City:

Country:

Shanghai China Declare that:

Name Representative of agent: Well Wei Agent Company name:

Address:

Park, Suzhou Area, China (Jiangsu) Pilot Free Trade Zone City:

Country Suzhou China SGS-CSTC Standards Technical Services (Suzhou) Co., Ltd South of No. 6 Plant, No. 1, Runsheng Road, Suzhou Industrial is authorized to apply for Certification of the following product(s):

Product description: 5G Module Type designation: AG568N-NA Trademark:

Quectel on our behalf. Date:

City:

Name:

Email:

Signature:

2023/06/01.. Shanghai .. Jean Hu .. (2) jean.hu@quectel.com. Notes:

(1): Required for FCC application

(2): For FCC it must be the Grantee Code owner or the authorized agent.

 

 

 

 

 

 

FCC FEDERAL COMMUNICATIONS COMMISSION Suppliers Declaration of Conformity (SDoC) Trademark(s) and Model(s): Quectel / AG568N-NA Equipment: 5G Module Manufacturer: Quectel Wireless Solutions Co., Ltd. FCC ID in case other parts of this equipment are subject to certification:

XMR2022AG568NNA This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1)

(2) this device may not cause harmful interference, and this device must accept any interference received, including interference that may cause undesired operation. The following test reports are subject to this declaration:

Test report number:

SEWA2210000069RG03 Issue date:

2023-03-29 The following manufacturer/importer/entity (located in the USA) is responsible for this declaration:

Date:

City:

Name:

Email:

Signature:

2023/06/01.. Shanghai .. Jean Hu .. jean.hu@quectel.com.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Date: 2023/3/29 Federal Communications Commission Authorization and Evaluation Division 7435 Oakland Mills Road Columbia, MD 21046 FCC ID: XMR2022AG568NNA US Agent Attestation Statement / Part 2.911(d)(7) Quectel Wireless Solutions Co., Ltd. certifies, that as of 2023/3/29, we have designated FCC US Agent, LLC to accept service of process on our behalf for FCC ID: XMR2022AG568NNA. Quectel Wireless Solutions Co., Ltd. accepts to maintain an agent of service of process in the United States for no less than one year after either the grantee has permanently terminated all marketing and importation of the applicable equipment within the U.S., or the conclusion of any Commission-related administrative or judicial proceeding involving the equipment, whichever is later. FCC US Agent, LLC, accepts as of the date of the filing of this application, the obligation of being the designated agent for the purpose of accepting service of process on behalf of Quectel Wireless Solutions Co., Ltd. for FCC ID: XMR2022AG568NNA The service term is covering product lifetime for one FCC ID. Designated Agent Information:

Company Name: FCC US Agent, LLC FRN: 0033402884 Address: 3722 Illinois Avenue, Saint Charles, IL, 60174, USA Contact Person: Tim Payne Phone: 708-571-3148 Email: Support@FCCUSAgent.com Sincerely, Company: Quectel Wireless Solutions Co., Ltd. Designated Agent: FCC US Agent, LLC Company Representative: Jean Hu Designated Agent Representative: Tim Payne Signature:

Signature: