FCC ID: XMR2022RG520NNA 5G Sub-6 GHz LGA Module

 

RG520F&RG520N Series Hardware Design 5G Module Series Version: 1.0.1 Date: 2022-01-21 Status: Preliminary 5G Module Series At Quectel, our aim is to provide timely and comprehensive services to our customers. If you require any assistance, please contact our headquarters:

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http://www.quectel.com/support/technical.htm. Or email us at: support@quectel.com. Legal Notices We offer information as a service to you. The provided information is based on your requirements and we make every effort to ensure its quality. You agree that you are responsible for using independent analysis and evaluation in designing intended products, and we provide reference designs for illustrative purposes only. Before using any hardware, software or service guided by this document, please read this notice carefully. Even though we employ commercially reasonable efforts to provide the best possible experience, you hereby acknowledge and agree that this document and related services hereunder are provided to you on an as available basis. We may revise or restate this document from time to time at our sole discretion without any prior notice to you. Use and Disclosure Restrictions License Agreements Documents and information provided by us shall be kept confidential, unless specific permission is granted. They shall not be accessed or used for any purpose except as expressly provided herein. Copyright Our and third-party products hereunder may contain copyrighted material. Such copyrighted material shall not be copied, reproduced, distributed, merged, published, translated, or modified without prior written consent. We and the third party have exclusive rights over copyrighted material. No license shall be granted or conveyed under any patents, copyrights, trademarks, or service mark rights. To avoid ambiguities, purchasing in any form cannot be deemed as granting a license other than the normal non-exclusive, royalty-free license to use the material. We reserve the right to take legal action for noncompliance with abovementioned requirements, unauthorized use, or other illegal or malicious use of the material. RG520F&RG520N_Series_Hardware_Design 1 / 116 5G Module Series Trademarks Except as otherwise set forth herein, nothing in this document shall be construed as conferring any rights to use any trademark, trade name or name, abbreviation, or counterfeit product thereof owned by Quectel or any third party in advertising, publicity, or other aspects. Third-Party Rights This document may refer to hardware, software and/or documentation owned by one or more third parties

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Unless otherwise provided by valid agreement, we make no warranties of any kind, either implied or express, and exclude all liability for any loss or damage suffered in connection with the use of features and functions under development, to the maximum extent permitted by law, regardless of whether such loss or damage may have been foreseeable. d) We are not responsible for the accessibility, safety, accuracy, availability, legality, or completeness of information, advertising, commercial offers, products, services, and materials on third-party websites and third-party resources. Copyright Quectel Wireless Solutions Co., Ltd. 2022. All rights reserved. RG520F&RG520N_Series_Hardware_Design 2 / 116 5G Module Series Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be paid to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions, such as when the mobile bill is unpaid or the (U)SIM card is invalid. When emergency help is needed in such conditions, use emergency call if the device supports it. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. In an emergency, the device with emergency call function cannot be used as the only contact method considering network connection cannot be guaranteed under all circumstances. The cellular terminal or mobile contains a transceiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV sets, radios, computers or other electric equipment. In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or metal powders. RG520F&RG520N_Series_Hardware_Design 3 / 116 5G Module Series About the Document Revision History Revision Date Author Description

2021-12-22 1.0.0 2021-12-22 Frank PENG/

Six ZHANG Frank PENG/

Six ZHANG Creation of the document Preliminary Preliminary:

1. Updated the dimensions (Table 2). 2. Added n38 HPUE for Class 2 transmitting power;

Changed the Max. transmission data rates of NSA and SA TDD in 5G NR features (Table 4). 3. Updated the functional diagram (Figure 2). 4. Added the note about optional ANT4 and ANT5 for 1.0.1 2022-01-21 Frank PENG/

Six ZHANG pin assignment (Chapter 2.4). 5. Changed pin 135 from RESERVED to HST_LAA_TX_EN (Figure 2 & Table 6). 6. Simplified DC characteristics and added Digital I/O Characteristic chapter (Table 6 & Chapter 6.4). 7. Updated Power-up, Power-down and Reset Timing

(Figure 13 & 14 & 17). 8. Updated the pull-up resistor value of USB_BOOT interface from 4.7 k to 10 k (Figure 19). 9. Added UART interfaces description (Chapter 4.7). RG520F&RG520N_Series_Hardware_Design 4 / 116 5G Module Series Contents Safety Information ...................................................................................................................................... 3 About the Document .................................................................................................................................. 4 Contents ...................................................................................................................................................... 5 Table Index .................................................................................................................................................. 8 Figure Index .............................................................................................................................................. 10 1 Introduction ....................................................................................................................................... 12 Special Marks ....................................................................................................................... 12 1.1. 2 Product Overview ............................................................................................................................. 13 Frequency Bands and Functions ......................................................................................... 14 Key Features ........................................................................................................................ 14 Functional Diagram .............................................................................................................. 18 Pin Assignment ..................................................................................................................... 19 Pin Description ..................................................................................................................... 20 EVB ....................................................................................................................................... 31 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 3.3. 3.1. 3.2. 3 Operating Characteristics ................................................................................................................ 32 Operating Modes .................................................................................................................. 32 Sleep Mode .......................................................................................................................... 33 3.2.1. UART Application Scenario ........................................................................................... 33 3.2.2. USB Application Scenario ............................................................................................. 34 3.2.2.1. USB Application with USB Remote Wakeup Function ................................... 34 3.2.2.2. USB Application with USB Suspend/Resume and MAIN_RI Function .......... 34 USB Application without USB Suspend Function .......................................... 35 3.2.2.3. Airplane Mode ...................................................................................................................... 36 3.3.1. Hardware ....................................................................................................................... 36 3.3.2. Software ........................................................................................................................ 36 Power Supply ....................................................................................................................... 37 3.4.1. Power Supply Pins ........................................................................................................ 37 3.4.2. Reference Design for Power Supply ............................................................................. 38 3.4.3. Power Supply ................................................................................................................ 38 3.4.4. Voltage Stability Requirements ..................................................................................... 39 Turn On ................................................................................................................................. 41 3.5.1. Turn on the Module with PWRKEY ............................................................................... 41 Turn Off ................................................................................................................................. 43 3.6.1. Turn off the Module with PWRKEY ............................................................................... 43 3.6.2. Turn off the Module with AT Command ......................................................................... 43 Reset .................................................................................................................................... 44 3.7. 3.4. 3.5. 3.6. 4 Application Interfaces ...................................................................................................................... 46 USB Interface ....................................................................................................................... 46 USB_BOOT Interface ........................................................................................................... 48 4.1. 4.2. RG520F&RG520N_Series_Hardware_Design 5 / 116 5G Module Series 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. 4.9. 4.10. 4.11. 4.12.

(U)SIM Interfaces ................................................................................................................. 49 I2C Interface* ........................................................................................................................ 51 I2S Interface* ........................................................................................................................ 52 PCM Interface* ..................................................................................................................... 53 UART Interfaces ................................................................................................................... 55 SDIO Interface ...................................................................................................................... 58 ADC Interface ....................................................................................................................... 60 SPI Interface ......................................................................................................................... 61 PCIe Interface ....................................................................................................................... 62 Control Signal ....................................................................................................................... 65 W_DISABLE# ........................................................................................................ 65 Indication Signal ................................................................................................................... 66 Network Status Indication ...................................................................................... 66 STATUS ................................................................................................................. 67 4.14. IPQ Status and Err Fatal Interface* ...................................................................................... 68 4.15. MAIN_RI* .............................................................................................................................. 69 Time Service and Repeater Interface* ................................................................................. 70 4.16. 4.17. GRFC Interfaces* ................................................................................................................. 70 4.13.1. 4.13.2. 4.12.1. 4.13. 5.1. 5.2. 5 RF Specifications .............................................................................................................................. 72 Cellular Network ................................................................................................................... 72 5.1.1. Antenna Interface & Frequency Bands ......................................................................... 72 5.1.2. Tx Power ....................................................................................................................... 76 5.1.3. Rx Sensitivity ................................................................................................................. 76 5.1.4. Reference Design ......................................................................................................... 80 GNSS .................................................................................................................................... 81 5.2.1. Antenna Interface & Frequency Bands ......................................................................... 81 5.2.2. GNSS Performance ...................................................................................................... 82 5.2.3. Reference Design ......................................................................................................... 83 Reference Design of RF Routing ......................................................................................... 83 Antenna Requirements ......................................................................................................... 86 RF Connector Recommendation .......................................................................................... 87 5.5.1. Recommended RF Connector for Installation .............................................................. 88 Assemble Coaxial Cable Plug Manually ........................................................ 88 Assemble Coaxial Cable Plug with Fixture .................................................... 89 5.5.2. Recommended Manufacturers of RF Connector and Cable ........................................ 90 5.5.1.1. 5.5.1.2. 5.3. 5.4. 5.5. 6 Electrical Characteristics & Reliability ........................................................................................... 91 Absolute Maximum Ratings.................................................................................................. 91 Power Supply Ratings .......................................................................................................... 92 Power Consumption ............................................................................................................. 92 Digital I/O Characteristic ....................................................................................................... 93 ESD Protection ..................................................................................................................... 94 Operating and Storage Temperatures .................................................................................. 95 Thermal Consideration ......................................................................................................... 95 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. RG520F&RG520N_Series_Hardware_Design 6 / 116 5G Module Series 7 Mechanical Information .................................................................................................................... 97 Mechanical Dimensions ....................................................................................................... 97 Recommended Footprint ...................................................................................................... 99 Top and Bottom Views ........................................................................................................ 100 7.1. 7.2. 7.3. 8.1. 8.2. 8.3. 8 Storage, Manufacturing & Packaging ........................................................................................... 101 Storage Conditions ............................................................................................................. 101 Manufacturing and Soldering ............................................................................................. 102 Packaging Specifications ................................................................................................... 103 8.3.1. Carrier Tape ................................................................................................................. 103 8.3.2. Plastic Reel ................................................................................................................. 104 8.3.3. Packaging Process ..................................................................................................... 105 9 Appendix A References .................................................................................................................. 106 10 Appendix B Operating Frequency.................................................................................................. 111 RG520F&RG520N_Series_Hardware_Design 7 / 116 5G Module Series Table Index Table 1: Special Marks ............................................................................................................................... 12 Table 2: Brief Introduction of the Module ................................................................................................... 13 Table 3: Wireless Network Type ................................................................................................................. 14 Table 4: Key Features ................................................................................................................................ 14 Table 5: I/O Parameters Definition ............................................................................................................. 20 Table 6: Pin Description ............................................................................................................................. 20 Table 7: Overview of Operating Modes ...................................................................................................... 32 Table 8: Pin Definition of Power Supply ..................................................................................................... 37 Table 9: Pin Definition of PWRKEY ............................................................................................................ 41 Table 10: Pin Definition of RESET ............................................................................................................. 44 Table 11: Functions of the USB Interface ................................................................................................... 46 Table 12: Pin Definition of USB Interface ................................................................................................... 46 Table 13: USB Trace Length in the Module ............................................................................................... 48 Table 14: Pin Definition of (U)SIM Interfaces ............................................................................................. 49 Table 15: Pin Definition of I2C Interface..................................................................................................... 52 Table 16: Pin Definition of I2S Interface ..................................................................................................... 52 Table 17: Pin Definition of PCM Interface .................................................................................................. 53 Table 18: Pin Definition of UART Interfaces ............................................................................................... 56 Table 19: Pin Definition of SD Card Interface ............................................................................................ 58 Table 20: SDC Trace Length in the Module ............................................................................................... 60 Table 21: Pin Definition of ADC Interface ................................................................................................... 61 Table 22: Characteristics of ADC Interface ................................................................................................ 61 Table 23: Pin Definition of SPI Interface .................................................................................................... 61 Table 24: Pin Definition of PCIe Interface .................................................................................................. 62 Table 25: PCIe Trace Length in the Module ............................................................................................... 65 Table 26: Pin Definition of Control Signal .................................................................................................. 65 Table 27: RF Function Status ..................................................................................................................... 66 Table 28: Pin Definition of Indication Signal ............................................................................................... 66 Table 29: Working State of the Network Connection Status/Activity Indication ......................................... 67 Table 30: Pin Definition of IPQ Status and Err Fatal Interface .................................................................. 68 Table 31: Behaviors of the RI ..................................................................................................................... 69 Table 32: Pin Definition of Time Service and Repeater Function .............................................................. 70 Table 33: Pin Definition of GRFC Interfaces .............................................................................................. 71 Table 34: Logic Levels of GRFC Interfaces ............................................................................................... 71 Table 35: Truth Table of GRFC Interfaces .................................................................................................. 71 Table 36: Pin Definition of Cellular Network Interface for RG520F-NA*/RG520N-NA .............................. 72 Table 37: Pin Definition of Cellular Network Interface for RG520F-EU*/RG520N-EU .............................. 73 Table 38: Cellular Network Antenna Mapping for RG520F-NA*/RG520N-NA ........................................... 74 Table 39: Cellular Network Antenna Mapping for RG520F-EU*/RG520N-EU ........................................... 75 Table 40: Tx Power ..................................................................................................................................... 76 Table 41: Conducted RF Receiving Sensitivity of RG520F-NA*/RG520N-NA .......................................... 76 RG520F&RG520N_Series_Hardware_Design 8 / 116 5G Module Series Table 42: Conducted RF Receiving Sensitivity of RG520F-EU*/RG520N-EU .......................................... 78 Table 43: Pin Definition of GNSS Antenna Interface ................................................................................. 81 Table 44: GNSS Frequency ....................................................................................................................... 81 Table 45: GNSS Performance .................................................................................................................... 82 Table 46: Antenna Requirements ............................................................................................................... 86 Table 47: Absolute Maximum Ratings ........................................................................................................ 91 Table 48: Module Power Supply Ratings ................................................................................................... 92 Table 49: Averaged Power Consumption for the Module .......................................................................... 92 Table 50: 1.8 V I/O Requirements .............................................................................................................. 93 Table 51: (U)SIM 1.8 V I/O Requirements ................................................................................................. 94 Table 52: (U)SIM 2.95 V I/O Requirements ............................................................................................... 94 Table 53: Electrostatics Discharge Characteristics (25 C, 45 % Relative Humidity) ............................... 94 Table 54: Operating and Storage Temperatures ........................................................................................ 95 Table 55: Recommended Thermal Profile Parameters ............................................................................ 103 Table 56: Carrier Tape Dimension Table (Unit: mm) ................................................................................ 104 Table 57: Plastic Reel Dimension Table (Unit: mm) ................................................................................. 104 Table 58: Related Documents .................................................................................................................. 106 Table 59: Terms and Abbreviations .......................................................................................................... 106 Table 60: Operating Frequencies (5G) ...................................................................................................... 111 Table 61: Operating Frequencies (2G + 3G + 4G)................................................................................... 113 RG520F&RG520N_Series_Hardware_Design 9 / 116 5G Module Series Figure Index Figure 1: Functional Diagram ..................................................................................................................... 18 Figure 2: Pin Assignment (Top View) ......................................................................................................... 19 Figure 3: DRX Run Time and Current Consumption in Sleep Mode ......................................................... 33 Figure 4: Sleep Mode Application via UART .............................................................................................. 33 Figure 5: Sleep Mode Application with USB Remote Wakeup .................................................................. 34 Figure 6: Sleep Mode Application with RI .................................................................................................. 35 Figure 7: Sleep Mode Application without Suspend Function ................................................................... 36 Figure 8: Reference Design of Power Supply ............................................................................................ 38 Figure 9: Power Supply Limits during Burst Transmission ........................................................................ 39 Figure 10: Star Structure of the Power Supply .......................................................................................... 40 Figure 11: Reference Circuit of Turning on the Module with Driving Circuit .............................................. 41 Figure 12: Reference Circuit of Turning on the Module with a Button ....................................................... 42 Figure 13: Power-up Timing ....................................................................................................................... 42 Figure 14: Power-down Timing .................................................................................................................. 43 Figure 15: Reference Circuit of RESET_N with Driving Circuit ................................................................. 44 Figure 16: Reference Circuit of RESET_N with Button ............................................................................. 45 Figure 17: Reset Timing ............................................................................................................................. 45 Figure 18: Reference Circuit of USB Application ....................................................................................... 47 Figure 19: Reference Circuit of USB_BOOT Interface .............................................................................. 49 Figure 20: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector ......................... 50 Figure 21: Reference Circuit of a 6-Pin (U)SIM Card Connector .............................................................. 51 Figure 22: Reference Circuit of I2S Application with Audio Codec ............................................................ 53 Figure 23: Primary Mode Timing ................................................................................................................ 54 Figure 24: Auxiliary Mode Timing ............................................................................................................... 54 Figure 25: Reference Circuit of PCM Interface .......................................................................................... 55 Figure 26: UART Interface Connection ...................................................................................................... 57 Figure 27: Reference Circuit with Translator Chip ..................................................................................... 57 Figure 28: Reference Circuit with Transistor Circuit .................................................................................. 58 Figure 29: Reference Circuit of SD Card Interface .................................................................................... 59 Figure 30: Reference Circuit of SPI Interface with a Level Translator....................................................... 62 Figure 31: PCIe Interface Connection ........................................................................................................ 64 Figure 32: Reference Circuit of the Network Status Indication .................................................................. 67 Figure 33: Reference Circuits of STATUS ................................................................................................. 68 Figure 34: Module with IPQ GPIO Application ........................................................................................... 69 Figure 35: Reference Circuit for RF Antenna Interfaces ............................................................................ 80 Figure 36: Reference Circuit of GNSS Antenna ........................................................................................ 83 Figure 37: Microstrip Design on a 2-layer PCB ......................................................................................... 84 Figure 38: Coplanar Waveguide Design on a 2-layer PCB ....................................................................... 84 Figure 39: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 84 Figure 40: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 85 Figure 41: Dimensions of the Receptacles (Unit: mm) .............................................................................. 87 RG520F&RG520N_Series_Hardware_Design 10 / 116 5G Module Series Figure 42: Specifications of Mating Plugs Using 0.81 mm Coaxial Cables (Unit: mm) .......................... 88 Figure 43: Plug in a Coaxial Cable Plug .................................................................................................... 89 Figure 44: Pull out a Coaxial Cable Plug ................................................................................................... 89 Figure 45: Install the Coaxial Cable Plug with Fixture ............................................................................... 90 Figure 46: Heatsink Placement .................................................................................................................. 96 Figure 47: Heatsink Fixing ......................................................................................................................... 96 Figure 48: Module Top and Side Dimensions (Unit: mm) .......................................................................... 97 Figure 49: Module Bottom Dimensions (Bottom View, Unit: mm) ............................................................. 98 Figure 50: Recommended Footprint .......................................................................................................... 99 Figure 51: Top & Bottom Views of RG520N Series ................................................................................. 100 Figure 52: Top & Bottom Views of RG520F Series .................................................................................. 100 Figure 53: Recommended Reflow Soldering Thermal Profile ................................................................. 102 Figure 54: Carrier Tape Dimension Drawing ............................................................................................ 104 Figure 55: Plastic Reel Dimension Drawing ............................................................................................ 104 Figure 56: Packaging Process ................................................................................................................. 105 RG520F&RG520N_Series_Hardware_Design 11 / 116 5G Module Series 1 Introduction This document defines RG520F and RG520N series modules and describes their air interfaces and hardware interfaces which relate to customers applications. It can help customers quickly understand interface specifications, electrical and mechanical details, as well as other related information of the module. Associated with application notes and user guides, customers can use this module to design and to set up mobile applications easily. 1.1. Special Marks Table 1: Special Marks Mark Definition

Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin, AT command, or argument is under development and currently not supported; and the asterisk (*) after a model indicates that the sample of such model is currently unavailable. Brackets ([]) used after a pin enclosing a range of numbers indicate all pins of the same type. For example, SDIO_DATA[0:3] refers to all four SDIO pins: SDIO_DATA0, SDIO_DATA1, SDIO_DATA2, and SDIO_DATA3. RG520F&RG520N_Series_Hardware_Design 12 / 116 5G Module Series 2 Product Overview RG520F and RG520N series are 5G NR/LTE-FDD/LTE-TDD/WCDMA 1 wireless communication modules, which provides data connectivity on 5G NR SA and NSA, LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA, and WCDMA networks. It also provides GNSS to meet your specific application demands. RG520F and RG520N series are industrial-grade modules for industrial and commercial applications only. The following tables show the brief introduction and supported frequency bands of the module. For CA and EN-DC configurations, refer to document [1], [2], [3] and [4]. Table 2: Brief Introduction of the Module Categories Packaging and pin counts LGA: 392 Dimensions Weight

(44.0 0.2) mm (41.0 0.2) mm (2.75 0.2) mm Approx. 11 g Wireless network functions 5G NR/LTE/WCDMA 1 Variants RG520F-NA*, RG520F-EU*, RG520N-NA, RG520N-EU 1 WCDMA is only supported by RG520F-EU* and RG520N-EU. RG520F&RG520N_Series_Hardware_Design 13 / 116 5G Module Series 2.1. Frequency Bands and Functions Table 3: Wireless Network Type Wireless Network Type 5G NR LTE-FDD RG520F-NA*

RG520N-NA n2/n5/n7/n12/n13/n14/n25/n26/n29/n30/

n38/n41/n48/n66/n70/n71/n77/n78 RG520F-EU*

RG520N-EU n1/n3/n5/n7/n8/n20/n28/n38/n40/n41/

n75/n76/n77/n78 B2/B4/B5/B7/B12/B13/B14/B17/B25/B26/

B29/B30/B66/B71 B1/B3/B5/B7/B8/B20/B28/B32 LTE-TDD B38/B41/B42/B43/B46 (LAA) /B48 B38/B40/B41/B42/B43 WCDMA

B1/B5/B8 GNSS GPS/GLONASS/BDS/Galileo/QZSS GPS/GLONASS/BDS/Galileo/QZSS 2.2. Key Features Table 4: Key Features Features Details Power Supply SMS Supply voltage: 3.34.4 V Typical supply voltage: 3.8 V Text and PDU mode Point-to-point MO and MT SMS cell broadcast SMS storage: ME by default

(U)SIM Interfaces Supports USIM/SIM card: 1.8 V, 2.95 V Audio Features*

PCM Interface*

SPI Interface Supports two digital audio interfaces: PCM and I2S WCDMA: AMR/AMR-WB LTE: AMR/AMR-WB Supports echo cancellation and noise suppression Supports 16-bit linear data format Supports long frame synchronization and short frame synchronization Supports master and slave modes, but must be in master mode for long frame synchronization Provides a duplex, synchronous and serial communication link with the peripheral devices RG520F&RG520N_Series_Hardware_Design 14 / 116 5G Module Series One SPI interface, only supports master mode 1.8 V operation voltage with clock rates up to 50 MHz One I2C interface Comply with I2C Specification, Version 3.0 Multi-master mode is not supported Supports 16-bit linear data format I2S is a common 4-wire DAI (MCLK is not used in the design normally) used in Hi-Fi, STB and portable devices The Tx and Rx lines are used for audio transmission, whilst the bit clock and left/right clock synchronize the link I2S in either controller or codec state is able to drive (master) the bit clock and left/right clock lines Can be multiplexed into PCM function Compliant with USB 3.1 and 2.0 specifications, with transmission rates up to 10 Gbps on USB 3.1 and 480 Mbps on USB 2.0 Used for AT command communication, data transmission, GNSS NMEA sentence output, software debugging and firmware upgrade USB Serial Driver: supports USB serial driver for Windows 7/8/8.1/10, Linux 2.65.14, Android 4.x11.x systems I2C Interface*

I2S Interface*

USB Interface SDIO Interface Supports SD 3.0 protocol Main UART:

Used for AT command communication Baud rate: 115200 bps by default Debug UART:

Used for Linux console and log output Baud rate: 115200 bps Bluetooth UART*:

Used for Bluetooth communication Baud rate: 115200 bps Supports RTS and CTS hardware flow control COEX UART*:

Used for WWAN/WLAN coexistence mechanism only for Qualcomn platform Complaint with PCIe Gen 3, supports two lanes, 8 Gbps per lane Complaint with PCIe Gen 4, supports one lane, 16 Gbps per lane Supports RC (Root Complex) mode and EP (End Point) mode Can be used to connect an external Wi-Fi IC and used for Wi-Fi communication by default UART Interfaces PCIe Interface eSIM*

A space was reserved for eSIM inside the module Network Indication NET_MODE and NET_STATUS to indicate network connectivity status AT Commands Compliant with 3GPP TS 27.007, 27.005 and Quectel enhanced AT commands RG520F&RG520N_Series_Hardware_Design 15 / 116 5G Module Series Rx-diversity 5G NR/LTE/WCDMA 1 Cellular antenna interfaces:

- RG520F-NA*/RG520N-NA:

4 cellular antenna interfaces

- RG520F-EU*/RG520N-EU:

Antenna Interfaces Transmitting Power 5G NR Features 4 + 2 (optional) cellular antenna interfaces One GNSS antenna interface 50 impedance WCDMA 1: Class 3 (24 dBm + 1/-3 dB) LTE-FDD: Class 3 (23 dBm 2 dB) LTE-TDD: Class 3 (23 dBm 2 dB) LTE B38/B41/B42 HPUE: Class 2 (26 dBm 2 dB) 2 5G NR: Class 3 (23 dBm 2 dB) 5G NR n38/n41/n77/n78 HPUE: Class 2 (26 dBm +2/-3 dB) 2 Supports 3GPP Rel-16 Supports UL 256QAM and DL 256QAM modulations Supports DL 4 4 MIMO 3

- RG520F-NA*/RG520N-NA:

n2/n5/n7/n12/n13/n14/n25/n26/n29/n30/n38/n41/n48/n66/n70/

n71/n77/n78

- RG520F-EU*/RG520N-EU:

n1/n3/n5/n7/n8/n20/n28/n38/n40/n41/n75/n76/n77/n78 Supports UL 2 2 MIMO 4

- RG520F-NA*/RG520N-NA: n38/n41/n77/n78

- RG520F-EU*/RG520N-EU: n38/n41/n77/n78 Supports SCS 15 kHz 5 and 30 kHz 5 Supports SA and NSA operation modes 6 Supports Option 3x, 3a, 3 and Option 2 Max. transmission data rates 7:

NSA TDD:

- RG520N-NA/RG520N-EU:

Max. 3.2 Gbps (DL)/550 Mbps (UL)

- RG520F-NA*/RG520F-EU*:

Max. 4.0 Gbps (DL)/550 Mbps (UL) SA TDD:

- RG520N-NA/RG520N-EU:

Max. 2.4 Gbps (DL)/900 Mbps (UL)

- RG520F-NA*/RG520F-EU*:

2 HPUE only supports single carrier. 3 LB 4 4 MIMO is optional. Even if it is not required, to support LB + LB CA or EN-DC combinations, ANT0ANT3 must support low bands. 4 UL 2 2 MIMO is only supported in 5G SA mode. 5 5G NR FDD bands only support 15 kHz SCS, and NR TDD bands only support 30 kHz SCS. 6 See document [1], [2], [3] and [4] for bandwidth supported by each frequency band in the NSA and SA modes. 7 The maximum rates are theoretical and the actual values refer to the network configuration. RG520F&RG520N_Series_Hardware_Design 16 / 116 5G Module Series Max. 4.0 Gbps (DL)/900 Mbps (UL) Supports FDD and TDD Supports 1.4/3/5/10/15/20 MHz RF bandwidth Supports UL QPSK, 16QAM, 64QAM and 256QAM* modulations Supports DL QPSK, 16QAM, 64QAM and 256QAM modulations Supports DL 4 4 MIMO 3

- RG520F-NA*/RG520N-NA:

B2/B4/B5/B7/B12/B13/B14/B17/B25/B26/B29/B30/B38/B41/B42/

B43/B48/B66/B71

- RG520F-EU*/RG520N-EU:

LTE Features B1/B3/B5/B7/B8/B20/B28/B32/B38/B40/B41/B42/B43 Max. transmission data rates 7:

- RG520N-NA:

LTE: 1.6 Gbps (DL)/200 Mbps (UL)

- RG520F-NA*:

LTE: 2.0 Gbps (DL)/200 Mbps (UL)

- RG520N-EU:

LTE: 1.6 Gbps (DL)/200 Mbps (UL)

- RG520F-EU*:

LTE: 2.0 Gbps (DL)/200 Mbps (UL) Supports 3GPP R9 DC-HSDPA, HSPA+, HSDPA, HSUPA and UMTS Features Internet Protocol Features GNSS Features Temperature Range WCDMA Supports QPSK, 16QAM, 64QAM modulations Max. transmission data rates 7:

- DC-HSDPA: 42 Mbps (DL)

- DC-HSUPA: 5.76 Mbps (UL)

- WCDMA: 384 kbps (DL)/384 kbps (UL) Supports NITZ, PING, QMI protocols Support PAP and CHAP for PPP connections Support Dual-band GNSS: L1 and L5 Supports GPS, GLONASS, BDS, Galileo, QZSS Protocol: NMEA-0183 Data update rate: 1 Hz Operating temperature range 8: -30 to +75 C Extended temperature range 9: -40 to +85 C Storage temperature range: -40 to +90 C Firmware Upgrade Use USB interface or FOTA to upgrade 8 To meet this operating temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module can meet 3GPP specifications. 9 To meet this extended temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module remains the ability to establish and maintain functions such as voice, SMS, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may undergo a reduction in value, exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again. RG520F&RG520N_Series_Hardware_Design 17 / 116 5G Module Series RoHS All hardware components are fully compliant with EU RoHS directive 2.3. Functional Diagram The following figure shows a block diagram of the module and illustrates the major functional parts. Power management Baseband DDR + NAND flash Radio frequency Peripheral interface 0 T N A 1 T N A 2 T N A 3 T N A 4 T N A 5 T N A S S N G _ T N A VBAT_RF QET Tx/Rx Blocks x T x R P x R D S S N G C F R G

P M I I VBAT_BB PWRKEY RESET_N ADC STATUS RFCLK 76.8MHz Transceiver NAND LPDDR4X SDRAM QLINK Control PMIC BBCLK(19.2 MHz) SleepCLK(32.768KHz) PMU 76.8 MHz XO SPMI eSIM Baseband I2S SPI VDD_WIFI_VL VDD_WIFI_VM VDD_WIFI_VH VDD_EXT

(U)SIM2

(U)SIM1 USB 2.0

/3.1 PCM PCIe 3.0/4.0 I2C UART SDIO Figure 1: Functional Diagram RG520F&RG520N_Series_Hardware_Design 18 / 116 5G Module Series NOTE 1. RG520F-NA* and RG520N-NA have 5 antenna interfaces. 2. RG520F-EU* and RG520N-EU have 7 antenna interfaces. ANT4 and ANT5 are used for CA combinations related to 1A-32A or 3A-32A. If there is no need for these CA combinations, ANT4 and ANT5 can be removed. 2.4. Pin Assignment The following figure illustrates the pin assignment of the module. 2 9 3 D N G 5 9 1 D N G 3 9 1 S S N G _ T N A 0 9 1 D N G 7 8 1 D N G 4 8 1 3 T N A 1 8 1 D N G 8 7 1 D N G 5 7 1 5 T N A 2 7 1 D N G 9 6 1 D N G 6 6 1 2 T N A 3 6 1 D N G 0 6 1 D N G 7 5 1 1 T N A 4 5 1 D N G 1 5 1 D N G 8 4 1 D E V R E S E R 5 4 1 D N G 2 4 1 D N G 9 3 1 D E V R E S E R 6 3 1 D N G 3 3 1 D N G 1 9 3 D N G 4 9 1 D N G 1 9 1 D N G 8 8 1 D N G 5 8 1 D N G 2 8 1 D N G 9 7 1 D N G 6 7 1 D N G 3 7 1 D N G 0 7 1 D N G 7 6 1 D N G 4 6 1 D N G 1 6 1 D N G 8 5 1 D N G 5 5 1 D N G 2 5 1 D N G 9 4 1 D N G 6 4 1 D N G 3 4 1 D N G 0 4 1 D N G 7 3 1 D N G 4 3 1 D N G 196 GND 199 RESERVED 202 GND 205 GND 208 RESERVED 211 GND 214 GND 217 RESERVED 220 ETH1_PWR_EN 223 ETH2_PWR_EN 226 GND 229 VBAT_RF1 232 VBAT_RF1 235 VBAT_BB 238 VBAT_BB 241 ADC0 244 USIM1_RST 247 USIM1_CLK 250 USIM2_VDD 253 USIM2_CLK 256 I2S_SCK 259 I2S_WS 262 RESERVED 264 RESERVED 2 9 1 D E V R E S E R 9 8 1 D E V R E S E R 6 8 1 D E V R E S E R 3 8 1 D E V R E S E R 0 8 1 L R T C _ W S _ L W 7 7 1 D E V R E S E R 4 7 1 1 C F R G _ R D S 1 7 1 0 C F R G _ R D S 8 6 1 D N G 5 6 1 D E V R E S E R 2 6 1 I G N T U M _ A P _ N A L W 9 5 1 N E _ S A _ A A L _ L W 6 5 1 D N G 3 5 1 D E V R E S E R 0 5 1 D E V R E S E R 7 4 1 D N G 4 4 1 D N G 1 4 1 D N G 8 3 1 N E _ X T _ L W _ T S H 5 3 1 _ X T _ A A L _ T S H N E 8 9 2 D E V R E S E R 7 9 2 D E V R E S E R 6 9 2 D E V R E S E R 5 9 2 D E V R E S E R 4 9 2 D E V R E S E R 3 9 2 D E V R E S E R 2 9 2 D E V R E S E R 1 9 2 D E V R E S E R 0 9 2 D E V R E S E R 9 8 2 D E V R E S E R 8 8 2 D E V R E S E R 7 8 2 D E V R E S E R 6 8 2 D E V R E S E R 5 8 2 D E V R E S E R 4 8 2 D E V R E S E R 3 8 2 D E V R E S E R 2 8 2 D E V R E S E R 299 GND 300 GND 301 GND 302 GND 303 GND 304 GND 305 GND 306 GND 307 GND 308 GND 309 GND 310 GND 311 GND 312 GND 313 GND 314 GND 315 GND 316 GND 317 GND 318 GND 319 GND 320 GND 321 GND 322 GND 323 GND 324 GND 325 GND 326 GND 327 GND 328 GND 329 GND 330 GND 331 GND 332 GND 333 GND 334 GND 335 GND 336 GND 337 GND 338 GND 339 GND 340 GND 341 GND 342 GND 343 GND 344 GND 345 GND 346 GND 347 GND 348 GND 349 GND 350 GND 351 GND 352 GND 353 GND 354 GND 355 GND 356 GND 357 GND 358 GND 359 GND 360 GND 361 GND 362 GND 363 GND 364 GND 365 GND 366 GND 367 GND 368 GND 369 GND 370 GND 371 GND 372 GND 373 GND 374 GND 375 GND 376 GND 377 GND 378 GND 379 GND 380 GND 381 GND 382 GND 383 GND 384 GND 385 GND 386 GND 387 GND 388 GND 5 6 2 D E V R E S E R 6 6 2 I I L V _ F W _ D D V 7 6 2 I I L V _ F W _ D D V 8 6 2 I I M V _ F W _ D D V 9 6 2 I I H V _ F W _ D D V 0 7 2 D E V R E S E R 1 7 2 D E V R E S E R 2 7 2 D E V R E S E R 3 7 2 D E V R E S E R 4 7 2 D E V R E S E R 5 7 2 I T C _ X D S _ O T _ L W 6 7 2 I T C _ L W _ O T _ X D S 7 7 2 D E V R E S E R 8 7 2 D E V R E S E R 9 7 2 D E V R E S E R 0 8 2 D E V R E S E R 1 8 2 I T N _ T X E 129 GND 126 GND 123 GND 120 RESERVED 117 RESERVED 114 W_DISABLE#

111 RESERVED 108 DBG_RXD 105 DBG_TXD 102 SLEEP_IND 99 RESERVED 96 GND 93 RESERVED 90 GND 87 RESERVED 84 GND 81 USB_BOOT 78 I2C_SDA 75 EXT_RST 72 RESERVED 69 RESERVED 66 VDD_EXT 197 GND 200 GND 203 GND 206 GND 209 GND 212 GND 215 GND 218 RESERVED 221 ETH1_INT_N 224 GND 227 GND 230 VBAT_RF1 233 VBAT_RF1 236 VBAT_BB 239 RESERVED 242 RESERVED 245 USIM1_VDD 248 USIM1_DATA 251 USIM2_DATA 254 USIM2_RST 257 I2S_DIN 260 RESERVED 263 RESERVED 198 RESERVED 201 WL_LAA_RX 204 SPI_MOSI 207 SPI_CS 210 SPI_CLK 213 SPI_MISO 216 WLAN_PWR_EN1 219 WLAN_PWR_EN2 222 WLAN_EN 225 WLAN_SLP_CLK 228 GND 231 GND 234 GND 237 STATUS 240 NET_MODE 243 NET_STATUS 246 RF_CLK3_WL 249 USIM1_DET 252 USIM2_DET 255 I2S_DOUT 258 MAIN_DTR 261 MAIN_DCD 3 D E V R E S E R 6 D E V R E S E R 9 D E V R E S E R 2 1 D N G 5 1 D E V R E S E R 8 1 D N G 1 2 D E V R E S E R 4 2 D E V R E S E R 7 2 D E V R E S E R 0 3 _ E K A W _ E C P I N 3 3 D N G 6 3 Q E R K L C _ E C P I N _ 9 3 N _ T S R _ E C P I 2 4 D N G 5 4 D E V R E S E R 8 4 D M C _ O D S I 1 5 2 A T A D _ O D S I 4 5 D E V R E S E R 7 5 D E V R E S E R 0 6 D D V _ O D S I 2 D E V R E S E R 5 D E V R E S E R 8 N _ T E S E R 1 1 D E V R E S E R 4 1 D E V R E S E R 7 1 D E V R E S E R 0 2 D E V R E S E R 3 2 D E V R E S E R 6 2 D N G 9 2 D E V R E S E R 2 3 M _ 0 X R _ E C P I 5 3 M _ 1 X R _ E C P I 8 3 M _ K L C F E R _ E C P I 1 4 M _ 1 X T _ E C P I 4 4 M _ 0 X T _ E C P I 7 4 K L C _ O D S I 0 5 1 A T A D _ O D S I 3 5 N E _ R W P _ O D S I 6 5 T E S V _ R W P _ O D S I 9 5 D X T _ T B 2 6 S T C _ T B 131 GND 128 GND 125 GND 122 GND 119 GND 116 GND 113 GND 110 VBAT_RF2 107 VBAT_RF2 104 ETH2_INT_N 101 RESERVED 98 GPIO_32 95 RESERVED 92 RESERVED 89 USB_SS_TX_M 86 USB_SS_RX_M 83 USB_DP 80 RESERVED 77 I2C_SCL 74 PCM_DIN 71 PCM_SYNC 68 MAIN_TXD 65 COEX_RXD 132 GND 130 ANT0 127 GND 124 GND 121 ANT4 118 GND 115 GND 112 VBAT_RF2 109 VBAT_RF2 106 RESERVED 103 RESERVED 100 MAIN_RI 97 RESERVED 94 RESERVED 91 USB_SS_TX_P 88 USB_SS_RX_P 85 USB_DM 82 USB_VBUS 79 MCLK 76 PCM_DOUT 73 PCM_CLK 70 MAIN_RXD 67 COEX_TXD 64 BT_EN 389 GND 1 D E V R E S E R 4 D E V R E S E R 7 Y E K R W P 0 1 D E V R E S E R 3 1 D E V R E S E R 6 1 D E V R E S E R 9 1 D E V R E S E R 2 2 D E V R E S E R 5 2 D E V R E S E R 8 2 D E V R E S E R 1 3 D E V R E S E R 4 3 P _ 0 X R _ E C P I 7 3 P _ 1 X R _ E C P I 0 4 P _ K L C F E R _ E C P I 3 4 P _ 1 X T _ E C P I 6 4 P _ 0 X T _ E C P I 9 4 0 A T A D _ O D S I 2 5 3 A T A D _ O D S I 5 5 T E D _ O D S I 8 5 D E V R E S E R 1 6 S T R _ T B 3 6 D X R _ T B 0 9 3 D N G Power Pins PCIe Pins ADC Pins CTL Pins GND Pins PCM Pins UART Pins Peripherals Control GPIO Pins

(U)SIM Pins SPI Pins I2S Pins RESERVED Pins I2C Pins USB Pins ANT Pins GRFC&RFFE SDIO Pins Wi-Fi Pins Figure 2: Pin Assignment (Top View) RG520F&RG520N_Series_Hardware_Design 19 / 116 5G Module Series NOTE 1. Keep all RESERVED or unused pins unconnected. 2. All GND pins should be connected to ground. 3. For RG520F-NA* and RG520N-NA, pins 121 and 175 are RESERVED. For RG520F-EU* and RG520N-EU, pins 121 and 175 are optional for ANT4 and ANT5 separately, which is related to CA configuration. 2.5. Pin Description The following table shows the DC characteristics and pin descriptions. Table 5: I/O Parameters Definition Type AI AO AIO DI DO DIO OD PI PO Description Analog Input Analog Output Analog Input/Output Digital Input Digital Output Digital Input/Output Open Drain Power Input Power Output Table 6: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment VBAT_BB 235, 236, 238 PI Power supply for the modules baseband part Vmax = 4.4 V Vmin = 3.3 V Vnom = 3.8 V RG520F&RG520N_Series_Hardware_Design 20 / 116 5G Module Series VBAT_RF1 VBAT_RF2 10 229, 230, 232, 233 PI 107, 109, 110, 112 PI VDD_WIFI_VL 266, 267 PO Power supply for the modules RF part Power supply for the modules RF part Provides 0.95 V for Wi-Fi/Bluetooth modules Vmax = 4.4 V Vmin = 3.3 V Vnom = 3.8 V Vmax = 4.4 V Vmin = 3.3 V Vnom = 3.8 V Vnom = 0.95 V IOmax = 1.7 A VDD_WIFI_VM 268 PO Provides 1.28 V for Wi-Fi/Bluetooth modules Vmax = 1.35 V Vnom = 1.28 V IOmax = 400 mA Power supply for Wi-Fi/Bluetooth modules. VDD_WIFI_VH 269 PO Provides 1.88 V for Wi-Fi/Bluetooth modules Vnom = 1.88 V IOmax = 400 mA VDD_EXT 66 PO Provides 1.8 V for external circuits Vnom = 1.8 V IOmax = 50 mA Power supply for external GPIOs pull-up circuits. 12, 18, 26, 33, 42, 84, 90, 96, 113, 115, 116, 118, 119, 122129, 131134, 136, 137, 140147, 149, 151, 152, 154156, 158, 160, 161, 163, 164, 167170, 172, 173, 176, 178, 179, 181, 182, 185, 187, 188, 190, 191, 194197, 200, 202, 203, 205, 206, 209, 211, 212, 214, 215, 224, 226, 227, 228, 231, 234, 299392 GND Turn on/off Pin Name Pin No. I/O Description DC Characteristics 1.8 V high level DI Turns on/off the module DI Resets the module 1.8 V Comment Internally pulled up to 1.8 V. Internally pulled up to 1.8 V with a 40 k resistor. PWRKEY RESET_N 7 8 Status Indication Pin Name Pin No. I/O Description DC Characteristics Comment STATUS 237 DO NET_MODE 240 DO Indicates the modules operation status Indicates whether the module has registered on 5G 1.8 V 10 VBAT_RF2 should be connected to an external VBAT power supply while PC 1.5 (which is optional for customers) is designed; otherwise, it is only used to connect decoupling capacitors. RG520F&RG520N_Series_Hardware_Design 21 / 116 5G Module Series network Indicates the modules network activity status Indicates the modules sleep mode NET_STATUS 243 DO SLEEP_IND 102 DO USB Interface Pin Name Pin No. I/O Description USB_VBUS 82 AI USB connection detect USB_DP USB_DM 83 85 AIO AIO USB differential data (+) USB differential data (-) USB_SS_TX_P 91 AO USB_SS_TX_M 89 AO USB_SS_RX_P 88 AI USB_SS_RX_M 86 AI

(U)SIM Interfaces USB 3.1 super-speed transmit (+) USB 3.1 super-speed transmit (-) USB 3.1 super-speed receive (+) USB 3.1 super-speed receive (-) DC Characteristics Vmax = 5.25 V Vmin = 3.3 V Vnom = 5.0 V Comment For USB connection detection only, not power supply. Requires differential impedance of 90 . USB 2.0 compliant. Requires differential impedance of 85 . USB 3.1 Gen2 compliant. Pin Name Pin No. I/O Description DC Characteristics Comment USIM1_VDD 245 PO

(U)SIM1 card power supply 1.8/2.95 V USIM1_DATA 248 DIO

(U)SIM1 card data USIM1_CLK 247 DO

(U)SIM1 card clock USIM1_VDD 1.8/2.95 V USIM1_RST 244 DO

(U)SIM1 card reset RG520F&RG520N_Series_Hardware_Design 22 / 116 5G Module Series USIM1_DET 249 DI USIM2_VDD 250 PO

(U)SIM1 card hot-plug detect

(U)SIM2 card power supply 1.8 V 1.8/2.95 V USIM2_DATA 251 DIO

(U)SIM2 card data USIM2_CLK 253 DO

(U)SIM2 card clock USIM2_VDD 1.8/2.95 V USIM2_RST 254 DO

(U)SIM2 card reset If unused, keep it open. USIM2_DET 252 DI

(U)SIM2 card hot-plug detect 1.8 V If unused, keep it open. Main UART Interface Pin Name Pin No. I/O Description MAIN_TXD MAIN_RXD 68 70 DO DI Main UART transmit Main UART receive DC Characteristics Comment MAIN_RI*

100 DO MAIN_DTR 258 DI MAIN_DCD*

261 DO Bluetooth UART Interface*

1.8 V Main UART ring indication Main UART data terminal ready Main UART data carrier detect Pin Name Pin No. I/O Description DC Characteristics Comment BT_TXD BT_RXD BT_RTS BT_CTS 59 63 61 62 DO DI DI DO Bluetooth UART transmit Bluetooth UART receive DTE request to send signal to DCE DTE clear to send signal from DCE 1.8 V Debug UART Interface Connect to DTEs RTS. Connect to DTEs CTS. Pin Name Pin No. I/O Description DC Characteristics Comment RG520F&RG520N_Series_Hardware_Design 23 / 116 5G Module Series DBG_RXD 108 DI DBG_TXD 105 DO Debug UART receive Debug UART transmit 1.8 V I2C Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment I2C_SCL 77 OD I2C serial clock I2C_SDA 78 OD I2C serial data 1.8 V Pull each of them up to VDD_EXT with an external 4.7 k resistor. If unused, keep them open. I2S Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment I2S_WS 259 DIO I2S word select I2S_SCK 256 DIO I2S clock 1.8 V I2S_DIN 257 DI I2S data in I2S_DOUT 255 DO I2S data out MCLK 79 DO Clock output for codec PCM Interface*

In master mode, it is an output signal. In slave mode, it is an input signal. Can be multiplexed into PCM_SYNC. In master mode, it is an output signal. In slave mode, it is an input signal. Can be multiplexed into PCM_CLK. Can be multiplexed into PCM_DIN. Can be multiplexed into PCM_DOUT. If unused, keep it open. Pin Name Pin No. I/O Description DC Characteristics Comment PCM_SYNC PCM_CLK 71 73 DIO PCM data frame sync DIO PCM clock 1.8 V In master mode, it is an output signal. In slave mode, it is an input signal. RG520F&RG520N_Series_Hardware_Design 24 / 116 5G Module Series PCM_DIN PCM_DOUT 74 76 DI PCM data input DO PCM data output If unused, keep it open. DC Characteristics Comment PCIe Interface Pin Name Pin No. I/O Description PCIE_REFCLK_P 40 AIO PCIE_REFCLK_M 38 AIO PCIe reference clock (+) PCIe reference clock (-) PCIE_TX0_M PCIE_TX0_P PCIE_TX1_M PCIE_TX1_P PCIE_RX0_M PCIE_RX0_P PCIE_RX1_M PCIE_RX1_P 44 46 41 43 32 34 35 37 AO PCIe transmit 0 (-) AO PCIe transmit 0 (+) AO PCIe transmit 1 (-) AO PCIe transmit 1 (+) AI AI AI AI PCIe receive 0 (-) PCIe receive 0 (+) PCIe receive 1 (-) PCIe receive 1 (+) PCIE_CLKREQ_N 36 OD PCIe clock request PCIE_RST_N 39 DIO PCIe reset 1.8 V PCIE_WAKE_N 30 OD PCIe wake up Requires differential impedance of 85 . One PCIe port is supported. It can be either Gen 3 2-lane or Gen 4 1-lane. In root complex mode, it is an input signal. In endpoint mode, it is an output signal. In root complex mode, it is an output signal. In endpoint mode, it is an input signal. In root complex mode, it is an input signal. In endpoint mode, it is an output signal. WWAN/WLAN Application Interface*

Pin Name Pin No. I/O Description DC Comment RG520F&RG520N_Series_Hardware_Design 25 / 116 5G Module Series Characteristics Only for Qualcomn platform. Signal interface used for WWAN/WLAN coexistence mechanism. Pin 65 can be multiplexed into SDX2AP_E911 function. Pin 67 can be multiplexed into SDX2AP_STATUS function. For details, please contact Quectel Technical Supports. This pin is used for the coexistence of n79 and Wi-Fi 5G. If n79 is needed in customer future project with Quectel modules, then this pin shall be pulled out and reserved;

otherwise, the pin can be NC. COEX_RXD 65 DI Coexistence UART receive COEX_TXD 67 DO Coexistence UART transmit HST_LAA_TX_EN 135 DO HST_WL_TX_EN 138 DI WLAN_PWR_ EN1 WLAN_PWR_ EN2 216 DO 219 DO 1.8 V Notifies LAA/n79 transmission from SDR transceiver to WLAN Notifies WLAN transmission from WLAN to SDR transceiver Controls WLAN PA power Controls WLAN other power BT_EN 64 DO Bluetooth enable WLAN_EN 222 DO WLAN enable RG520F&RG520N_Series_Hardware_Design 26 / 116 5G Module Series WL_SW_CTRL 180 DI WLAN_SLP_CLK 225 AO RF_CLK3_WL 246 AO 76.8 MHz system clock request 32.768 kHz sleep clock output 76.8 MHz system clock output SDX_TO_WL_CTI 276 DO

Vmax = 1.08 V Vnom = 1.05 V Vmin = 1.02 V Not used by default. Keep it open. WLAN_PA_ MUTING 162 DO WL_LAA_AS_EN 159 DO WL_LAA_RX 201 DO GPIO from SDX to disable WLAN PA GPIO to allow WWAN to power on WLAN 0.8 V AON domain, when WLAN is sleeping or disabled. Additionally, the control logic in WLAN AON domain allows SDR to control 5G WLAN xLNA (LNA in FEMs) SoC signal to set 5G xLNA to high gains or high isolation when both chains (LAA and 5G WLAN) are active simultaneously. No individual control for each chain 1.8 V WL_TO_SDX_CTI 275 DI

SDIO Interface Not used by default. Keep it open. Pin Name Pin No. I/O Description DC Characteristics Comment RG520F&RG520N_Series_Hardware_Design 27 / 116 5G Module Series SDIO_VDD 60 PI SDIO power supply SDIO_DATA0 SDIO_DATA1 SDIO_DATA2 SDIO_DATA3 SDIO_CMD SDIO_CLK 49 50 51 52 48 47 SDIO_PWR_EN 53 SDIO_PWR_ VSET 56 DIO SDIO data bit 0 DIO SDIO data bit 1 DIO SDIO data bit 2 DIO SDIO data bit 3 DIO SDIO command DO SDIO clock DO DO SDIO power supply enable SDIO power domain set SDIO_DET 55 DI SD hot-plug detect 1.8/2.85 V configurable input. If unused, connect it to VDD_EXT. The power domain of SD I/O pins depends on SDIO_VDD. If unused, keep them open. 1.8 V Pull it up to VDD_EXT with a 470 k resistor. If unused, keep it open. Antenna Interfaces for RG520F-NA*/RG520N-NA Pin Name Pin No. I/O Description Comment ANT0 130 AIO Antenna 0 interface:

5G NR: n41 TRX1 & n77/n78 TRX0 LTE: LMB_TRX0 & HB_TRX1 &

UHB_TRX0 ANT1 157 AIO

Antenna 1 interface:

5G NR: n41 DRX MIMO & n77/n78 DRX MIMO LTE: LMB_PRX MIMO & HB_DRX MIMO & UHB_DRX MIMO &

LAA_PRX 50 impedance. ANT2 166 AIO

Antenna 2 interface:

5G NR: n41 PRX MIMO & n77/n78 PRX MIMO LTE: LMB_DRX MIMO & HB_PRX MIMO & UHB_PRX MIMO &

LAA_DRX RG520F&RG520N_Series_Hardware_Design 28 / 116 5G Module Series ANT3 184 AIO ANT_GNSS 193 AI Antenna 3 interface:

5G NR: n41 TRX0 & n77/n78 TRX1 LTE: LMB_TRX1 & HB_TRX0 &

UHB_TRX1 GNSS antenna interface:

L1/L5 Antenna Interfaces for RG520F-EU*/RG520N-EU Pin Name Pin No. I/O Description Comment ANT0 130 AIO Antenna 0 interface:

5G NR: n41 TRX1 & n77/n78 TRX0 LTE: LMB_TRX0 & HB_TRX1 &

UHB_TRX0

- WCDMA: LMB_TRX ANT1 157 AIO

Antenna 1 interface:

5G NR: n41 DRX MIMO & n77/n78 DRX MIMO LTE: LMB_PRX MIMO & HB_DRX MIMO & UHB_DRX MIMO ANT2 166 AIO

Antenna 2 interface:

5G NR: n41 PRX MIMO & n77/n78 PRX MIMO LTE: LMB_DRX MIMO & HB_PRX MIMO & UHB_PRX MIMO 50 impedance. ANT3 184 AIO Antenna 3 interface:

5G NR: n41 TRX0 & n77/n78 TRX1 LTE: LMB_TRX1 & HB_TRX0 &

UHB_TRX1 ANT4 ANT5 121 175 ANT_GNSS 193

- WCDMA: LMB_DRX Antenna 4 interface:

LTE: B32_PRX (optional) Antenna 5 interface:

LTE: B32_DRX (optional) GNSS antenna interface:

L1/L5 AI AI AI Antenna Tuner Control Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment SDR_GRFC0 171 SDR_GRFC1 174 DO DO GRFC interface dedicated for external antenna tuner control 1.8 V If unused, keep them open. RG520F&RG520N_Series_Hardware_Design 29 / 116 5G Module Series SPI Interface Pin Name Pin No. I/O Description DC Characteristics Comment SPI_CLK SPI_CS 210 207 DO SPI clock DO SPI chip select SPI_MISO 213 DI SPI_MOSI 204 DO SPI master-in slave-out SPI master-out slave-in ADC Interface 1.8 V Only master mode is supported. Pin Name Pin No. I/O Description DC Characteristics Comment ADC0 241 AI General-purpose ADC interface Voltage range:

01.875 V Time Service and Repeater Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment GPIO_32 98 DO Supports time service and repeater functions;

supports 1PPS pulse output and frame synchronization 1.8 V Can be multiplexed into AP2SDX_ STATUS function. For details, please contact Quectel Technical Supports. Other Interface Pins Pin Name Pin No. I/O Description DC Characteristics Comment USB_BOOT 81 DI EXT_RST 75 DO EXT_INT 281 W_DISABLE#

114 DI DI Forces the module to enter emergency download mode External audio reset External audio interrupt Airplane mode control 1.8 V ETH1_PWR_EN*

220 DO Ethernet PHY 1 These pins are the RG520F&RG520N_Series_Hardware_Design 30 / 116 5G Module Series power enable Ethernet PHY 2 power enable Interrupts input from Ethernet PHY 1 Interrupts input from Ethernet PHY 2 ETH2_PWR_EN*

223 DO ETH1_INT_N*

221 DI ETH2_INT_N*

104 DI RESERVED Pins Pin Name Pin No. 16, 9, 10, 11, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29, 31, 45, 54, 57, 58, 69, 72, 80, 87, 9295, 97, 99, 101, 103, 106, 111, 117, 120, 139, 148, 150, 153, 165, 177, 183, 186, 189, 192, 198, 199, 208, 217, 218, 239, 242, 260, 262265, 270, 271273, 274, 277280, 282298 RESERVED NOTE control pins of PHY chip recommended by the platform. Comment Keep these pins unconnected. 1. RG520F-NA* and RG520N-NA: 4 antenna interfaces + 1 GNSS antenna interface (ANT0/1/2/3 +

ANT_GNSS). 2. RG520F-EU* and RG520N-EU: 4 + 2 (optional) cellular antenna interfaces + 1 GNSS antenna interface (ANT0/1/2/3 + ANT4/5 (optional) + ANT_GNSS). 2.6. EVB In order to help customers to develop applications with the module conveniently, Quectel supplies an evaluation board (5G EVB), USB data cable, earphone, antenna, and other peripherals to control or to test the module. For more details, please refer to document [5]. RG520F&RG520N_Series_Hardware_Design 31 / 116 5G Module Series 3 Operating Characteristics 3.1. Operating Modes The table below outlines operating modes of the module. Table 7: Overview of Operating Modes Mode Details Normal Operation Idle Talk/Data Software is active. The module is registered on the network and ready to send and receive data. Network connection is ongoing. In this mode, the power consumption is decided by network setting and data transfer rate. Minimum Functionality Mode Airplane Mode AT+CFUN=0 command can set the module to a minimum functionality mode. In this case, both RF function and (U)SIM card will be invalid. AT+CFUN=4 command or driving W_DISABLE# LOW will set the module to airplane mode. In this case, RF function will be invalid. Sleep Mode In this mode, current consumption of the module will be reduced to the minimal level. In this mode, the module can still receive paging, SMS, voice call and TCP/UDP data from network. Power Down Mode In this mode, the VBAT power supply is constantly turned on and the software stops working. NOTE For more details about AT command, see document [6]. RG520F&RG520N_Series_Hardware_Design 32 / 116 5G Module Series 3.2. Sleep Mode DRX of the module is able to reduce the current consumption to a minimum value during sleep mode. The diagram below illustrates the relationship between the DRX run time and the current consumption of the module in this mode. t n e r r u C DRX OFF ON OFF ON OFF ON OFF ON OFF Run Time Figure 3: DRX Run Time and Current Consumption in Sleep Mode 3.2.1. UART Application Scenario If the host communicates with the module via UART interface, the following two preconditions should be met to set the module enter sleep mode:

Execute AT+QSCLK=1 command to enable sleep mode. Drive MAIN_DTR high. The figure illustrates the connection between the module and the host. Module MAIN_RXD MAIN_TXD MAIN_RI MAIN_DTR GND Host TXD RXD EINT GPIO GND Figure 4: Sleep Mode Application via UART RG520F&RG520N_Series_Hardware_Design 33 / 116 5G Module Series Driving MAIN_DTR low with the host will wake up the module. When the module has a URC to report, MAIN_RI signal will wake up the host. Please refer to Chapter 4.15 for details about RI behavior. 3.2.2. USB Application Scenario 3.2.2.1. USB Application with USB Remote Wakeup Function If the host supports USB suspend/resume and remote wakeup function, the following three preconditions can make the module enter the sleep mode. Execute AT+QSCLK=1 to enable sleep mode. Ensure the MAIN_DTR is held at high level or keep it open. Ensure the hosts USB bus, which is connected with the modules USB interface, enters suspend state. Module USB_VBUS USB_DP USB_DM GND Host VDD USB_DP USB_DM GND Figure 5: Sleep Mode Application with USB Remote Wakeup Sending data to the module through USB will wake up the module. When the module has a URC to report, the module will send remote wake-up signals to USB Bus to wake up the host. 3.2.2.2. USB Application with USB Suspend/Resume and MAIN_RI Function If the host supports USB Suspend/Resume, but does not support remote wakeup function, the MAIN_RI signal is needed to wake up the host. RG520F&RG520N_Series_Hardware_Design 34 / 116 5G Module Series In this case, the following three preconditions can make the module enter the sleep mode. Execute AT+QSCLK=1 command to enable sleep mode. Ensure MAIN_DTR is held at a high level or keep it open. The hosts USB Bus, which is connected with the modules USB interface, enters suspend state. The following figure illustrates the connection between the module and the host. Module USB_VBUS USB_DP USB_DM MAIN_RI GND Host VDD USB_DP USB_DM EINT GND Figure 6: Sleep Mode Application with RI Sending data to the module through USB will wake up the module. When the module has a URC to report, the MAIN_RI signal will wake up the host. 3.2.2.3. USB Application without USB Suspend Function If the host does not support USB suspend function, disconnect USB_VBUS with an external control circuit to make the module enter sleep mode. Execute AT+QSCLK=1 command to enable sleep mode. Ensure the MAIN_DTR is held at a high level or keep it open. Disconnect USB_VBUS. The figure illustrates the connection between the module and the host. RG520F&RG520N_Series_Hardware_Design 35 / 116 5G Module Series Module Host USB_VBUS Power Switch USB_DP USB_DM MAIN_RI GND GPIO VDD USB_DP USB_DM EINT GND Figure 7: Sleep Mode Application without Suspend Function Turn on the power switch and supply power to USB_VBUS will wake up the module. NOTE Please pay attention to the level match shown in dotted line between the module and the host. 3.3. Airplane Mode When the module enters airplane mode, the RF function will be disabled, and all AT commands related to it will be inaccessible. This mode can be set via the following ways. 3.3.1. Hardware The W_DISABLE# pin is pulled up by default. Its control function for airplane mode is disabled by default and AT+QCFG= airplanecontrol, 1 can be used to enable the function. Driving it low will set the module enter airplane mode. 3.3.2. Software AT+CFUN=<fun> command provides choices of the functionality level through setting <fun> into 0, 1 or 4. AT+CFUN=0: Minimum functionality (disable RF function and (U)SIM function). RG520F&RG520N_Series_Hardware_Design 36 / 116 5G Module Series AT+CFUN=1: Full functionality (default). AT+CFUN=4: Airplane mode (disable RF function). NOTE The execution of AT+CFUN command will not affect GNSS function. 3.4. Power Supply 3.4.1. Power Supply Pins The module provides 11 VBAT pins dedicated to the connection with the external power supply. There are three separate voltage domains for VBAT. Four VBAT_RF1 pins and four VBAT_RF2 pins for RF part. Three VBAT_BB pins for baseband part. Table 8: Pin Definition of Power Supply Pin Name Pin No. I/O Description Min. Typ. Max. Unit VBAT_BB VBAT_RF1 VBAT_RF2 11 235, 236, 238 229, 230, 232, 233 107, 109, 110, 112 PI PI PI Power supply for the modules baseband part 3.3 3.8 4.4 V Power supply for the modules RF part Power supply for the modules RF part 3.3 3.8 4.4 V 3.3 3.8 4.4 V GND 12, 18, 26, 33, 42, 84, 90, 96, 113, 115, 116, 118, 119, 122129, 131134, 136, 137, 140147, 149, 151, 152, 154156, 158, 160, 161, 163, 164, 167170, 172, 173, 176, 178, 179, 181, 182, 185, 187, 188, 190, 191, 194197, 200, 202, 203, 205, 206, 209, 211, 212, 214, 215, 224, 226, 227, 228, 231, 234, 299392

0

V 11 VBAT_RF2 should be connected to an external VBAT power supply while PC 1.5 (which is optional for customers) is designed; otherwise, it is only used to connect decoupling capacitors. RG520F&RG520N_Series_Hardware_Design 37 / 116 5G Module Series 3.4.2. Reference Design for Power Supply The performance of the module largely depends on the power source. The power supply of the module should be able to provide sufficient current of 3 A at least. If the voltage drops between input and output is not too high, it is suggested that an LDO should be used to supply power to the module. If there is a big voltage difference between input and the desired output VBAT, a buck converter is preferred as the power supply. The following figure shows a reference design for +5 V input power source. The designed output of the power supply is about 3.8 V and the maximum rated current is 3 A. GND TPS62130

+5 V TV S C1 C2 R1 C3 L1 R2 R3 R4 C5 C6 3V8_EN C4 GND GND GND GND Figure 8: Reference Design of Power Supply NOTE To avoid damaging internal flash, do not switch off the power supply when the module works normally. Only after shutting down the module with PWRKEY or AT command can you cut off the power supply. 3.4.3. Power Supply AT+CBC command can monitor the VBAT_BB voltage value. For more details, please refer to document

[6]. RG520F&RG520N_Series_Hardware_Design 38 / 116 5G Module Series 3.4.4. Voltage Stability Requirements The power supply range of the module is from 3.3 V to 4.4 V. Please make sure the input voltage will never drop below 3.3 V. Burst Transmission Burst Transmission VBAT Drop Figure 9: Power Supply Limits during Burst Transmission To decrease voltage s drop, a bypass capacitor of about 100 F with low ESR should be used, and a same bypass capacitor of about 100 F need to be reserved. On the other hand, a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low ESR. It is recommended to use 22 ceramic capacitors for composing the MLCC array, and place these capacitors close to VBAT pins. The main power supply from an external application must be a single voltage source and can be expanded to two sub paths with the star structure. The width of VBAT_BB trace should be no less than 1.2 mm. The width of VBAT_RF1 and VBAT_RF2 trace should be no less than 2 mm. In principle, the longer the VBAT trace is, the wider it will be. In addition, in order to ensure the stability of the power supply, it is necessary to add a high-power TVS at the front end of the power supply. Reference circuit is shown as below:

RG520F&RG520N_Series_Hardware_Design 39 / 116 5G Module Series VBAT F 0 0 1 _ M N C1 C2 C3 C4 C5 C6 100 F 100 nF 6.8 nF 220 pF 68 pF R1 0R R2 0R 0R F 0 0 1 _ M N R3 NM-0R D1 F 0 0 1 _ M N 100 F 100 nF 220 pF 68 pF 15 pF 9.1 pF 4.7 pF C7 C8 C9 C10 C11 C12 C13 C14 VBAT_BB VBAT_RF1 VBAT_RF2 100 F 100 nF 220 pF 68 pF 15 pF 9.1 pF 4.7 pF C15 C16 C17 C18 C19 C20 C21 C22 Module Figure 10: Star Structure of the Power Supply NOTE 1. MLCC array for VBAT_BB includes 100 F, 100 nF, 6.8 nF, 220 pF, 68 pF and a 100 F is reserved. 2. MLCC array for VBAT_RF1 and VBAT_RF2 includes 100 F, 100 nF, 220 pF, 68 pF, 15 pF, 9.1 pF, 4.7 pF and a 100 F is reserved. 3. R3 needs to be reserved since VBAT_RF2 should be connected to an external VBAT power supply while PC 1.5 (which is optional for customers) is designed. RG520F&RG520N_Series_Hardware_Design 40 / 116 5G Module Series 3.5. Turn On 3.5.1. Turn on the Module with PWRKEY Table 9: Pin Definition of PWRKEY Pin Name Pin No. PWRKEY 7 I/O DI Description Comment Turns on/off the module Internally pulled up. When the module is in power off mode, it can be turned on and enter normal operation mode by driving PWRKEY low for at least 500 ms. It is recommended to use an open drain/collector driver to control PWRKEY. After STATUS pin outputs a high level, PWRKEY can be released. 500 ms Turn on pulse 4.7K 47K Q1 G P IO M C U PWRKEY M odule Figure 11: Reference Circuit of Turning on the Module with Driving Circuit Another way to control the PWRKEY is by using a button directly. When pressing the button, an electrostatic strike may generate from finger. Therefore, a TVS component shall be placed near the button for ESD protection. RG520F&RG520N_Series_Hardware_Design 41 / 116 5G Module Series S1 R1 1K PWRKEY TVS Turn-on pulse Close to S1 M odule Figure 12: Reference Circuit of Turning on the Module with a Button The turn on scenario is illustrated in the following figure. N O TE V B AT P W R K E Y R ES E T_N S TA TU S U AR T U SB V D D _E X T 69 m s 500 m s V IH = 1.8 V 3 m s V IL 0.5 V TB D TB D Inactive TB D A ctive Inactive A ctive 10 m s Figure 13: Power-up Timing RG520F&RG520N_Series_Hardware_Design 42 / 116 5G Module Series

. NOTE Please ensure that VBAT is stable for at least 30 ms before pulling down the PWRKEY. 3.6. Turn Off 3.6.1. Turn off the Module with PWRKEY Driving PWRKEY low for at least 800 ms, then the module will execute power-down procedure after the PWRKEY is released. 800 m s T B D V B A T P W R K E Y S T A TU S M od ule S tatus R unning P ow er-dow n procedure O F F V D D _E X T 17 m s Figure 14: Power-down Timing 3.6.2. Turn off the Module with AT Command It is safe to use AT+QPOWD command to turn off the module, which is similar to turn off the module via PWRKEY pin. Please refer to document [6] for details about AT+QPOWD command. RG520F&RG520N_Series_Hardware_Design 43 / 116 5G Module Series

. NOTE 1. In order to avoid damaging the internal flash, please do not switch off the power supply when the module works normally. Only after the module is power off by PWRKEY or AT command, the power supply can be cut off. 2. When turning off module with AT command, please keep PWRKEY at a high level after the execution of power-off command. Otherwise, the module will be turned on again after turned off. 3.7. Reset The module can be reset by driving RESET_N low for at least 500 ms and then releasing it. The RESET_N signal is sensitive to interference, so it is recommended to route the trace as short as possible and surround it with ground. Table 10: Pin Definition of RESET Pin Name Pin No. RESET_N 8 I/O DI Description Comment Resets the module Internally pulled up to 1.8 V. The recommended circuit is the same as the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET_N. 500 ms Reset pulse 4.7K 47K Q1 G P IO M C U RESET_N M odule Figure 15: Reference Circuit of RESET_N with Driving Circuit RG520F&RG520N_Series_Hardware_Design 44 / 116 5G Module Series S2 TVS RESET_N R1 1K Reset pulse Close to S2 Module Figure 16: Reference Circuit of RESET_N with Button V B A T R E S E T_N S T A TU S M od ule S tatus NOTE T 500 m s 200 m s T B D R unning R esetting R estart Figure 17: Reset Timing 1. Use RESET_N only when you fail to turn off the module with the AT+QPOWD and PWRKEY. 2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins. RG520F&RG520N_Series_Hardware_Design 45 / 116 5G Module Series 4 Application Interfaces 4.1. USB Interface The module provides one USB interface. The USB interface complies with the USB 3.1 and USB 2.0 specifications, and supports Super-Speed (10 Gbps) for USB 3.1, High-Speed (480 Mbps) and Full-Speed (12 Mbps) for USB 2.0. Table 11: Functions of the USB Interface Functions AT command communication Data transmission GNSS NMEA sentence output Software debugging Firmware upgrade Voice over USB*

Pin definition of the USB interface is here as follows:

Table 12: Pin Definition of USB Interface Pin Name Pin No. I/O Description Comment USB_VBUS USB_DP USB_DM 82 83 85 AI USB connection detect AIO USB differential data (+) AIO USB differential data (-) For USB connection detection only, not power supply. Requires differential impedance of 90 . USB 2.0 compliant. RG520F&RG520N_Series_Hardware_Design 46 / 116 5G Module Series USB_SS_TX_P 91 USB_SS_TX_M 89 USB_SS_RX_P 88 USB_SS_RX_M 86 AO AO AI AI USB 3.1 super-speed transmit (+) USB 3.1 super-speed transmit (-) USB 3.1 super-speed receive (+) USB 3.1 super-speed receive (-) Requires differential impedance of 85 . USB 3.1 Gen2 compliant. It is recommended to reserve test points for debugging and firmware upgrading in your designs. Minimize these stubs Test Points Module VDD USB_VBUS USB_DM USB_DP R3 R4 R1 R2 NM_0R NM_0R 0R 0R Close to Module TVS Array USB_SS_TX_P C1 220 nF USB_SS_TX_M C2 220 nF USB_SS_RX_P USB_SS_RX_M GND 220 nF C3 220 nF C4 Host USB_DM USB_DP USB_SS_RX_P USB_SS_RX_M USB_SS_TX_P USB_SS_TX_M GND Figure 18: Reference Circuit of USB Application To ensure the signal integrity of USB data lines, you must place R1, R2, R3, R4, C1 and C2 close to the module, C3 and C4 close to the host, and keep these resistors close to each other. Keep the extra stubs of trace as short as possible. The following principles should be complied with when designing the USB interface, to meet USB specifications. It is important to route the USB signal traces as differential pairs with ground surrounded. The impedance of USB 2.0 differential trace is 90 . The impedance of USB 3.1 differential trace is 85 . For USB 2.0 signal traces, the trace as length should be less than 250 mm, length matching of each differential data pair (DP/DM) should be less than 2 mm (14 ps). For USB 3.1 signal traces, length RG520F&RG520N_Series_Hardware_Design 47 / 116 5G Module Series matching of each differential data pair (Tx/Rx) should be less than 0.7 mm (5 ps), while the matching between Tx and Rx should be less than 10 mm. Do not route signal traces under crystals, oscillators, magnetic devices, PCIe and RF signal traces. It is important to route the USB differential traces in inner-layer of the PCB, and surround the traces with ground on that layer and ground planes above and below. Junction capacitance of the ESD protection components might cause influences on USB data lines, so please pay attention to the selection of the components. Typically, the stray capacitance should be less than 1.0 pF for USB 2.0, and less than 0.15 pF for USB 3.1. Keep the ESD protection components as close to the USB connector as possible If possible, reserve a 0 resistor on USB_DP and USB_DM lines respectively. For more details about the USB specifications, please visit http://www.usb.org/home. Table 13: USB Trace Length in the Module Pin No. Pin Name Length (mm) Length difference (P-M) (mm) USB_DP USB_DM USB_SS_TX_P USB_SS_TX_M USB_SS_RX_P USB_SS_RX_M 31.10 31.15 32.90 33.02 30.90 30.73 83 85 91 89 88 86 NOTE

-0.05

-0.12

-0.17 1. Only USB 2.0 interface supports firmware upgrade. 2. Both USB 3.1 interface and PCIe Gen 3 interface support data transmission, and USB 3.1 interface is used by default. If you want to use PCIe interface for data communication, set it with AT+QCFG via USB 2.0. For more details about AT command, see document [6]. 4.2. USB_BOOT Interface The module provides a USB_BOOT pin. You can pull up USB_BOOT to VDD_EXT before powering on the module, thus the module will enter emergency download mode when powered on. In this mode, the module supports firmware upgrade over USB 2.0 interface. RG520F&RG520N_Series_Hardware_Design 48 / 116 5G Module Series Module USB_BOOT Test point 10K VDD_EXT TVS TVS Close to test point Figure 19: Reference Circuit of USB_BOOT Interface 4.3. (U)SIM Interfaces

(U)SIM interfaces circuitry meet ETSI and IMT-2000 requirements. Both Class B (2.95 V) and Class C

(1.8 V) (U)SIM cards are supported, and Dual SIM Single Standby* function is supported. Table 14: Pin Definition of (U)SIM Interfaces Pin Name Pin No. I/O Description Comment USIM1_VDD 245 PO

(U)SIM1 card power supply Either 1.8 V or 2.95 V is supported by the module automatically. DIO

(U)SIM1 card data USIM1_DATA USIM1_CLK USIM1_RST USIM1_DET 248 247 244 249 DO DO DI USIM2_VDD 250 PO

(U)SIM1 card clock

(U)SIM1 card reset

(U)SIM1 card hot-plug detect 1.8 V power domain. If unused, keep it open.

(U)SIM2 card power supply Either 1.8 V or 2.95 V is supported by the module automatically. USIM2_DATA USIM2_CLK 251 253 DIO DO

(U)SIM2 card data

(U)SIM2 card clock RG520F&RG520N_Series_Hardware_Design 49 / 116 5G Module Series USIM2_RST USIM2_DET 254 252 DO DI

(U)SIM2 card reset

(U)SIM2 card hot-plug detect 1.8 V power domain. If unused, keep it open. The module supports (U)SIM card hot-plug via the USIM_DET pin. The function supports low level and high level detections. It is disabled by default and you can configure it via AT+QSIMDET. See document

[6] for more details about the command. The following figure illustrates a reference design for (U)SIM card interface with an 8-pin (U)SIM card connector. VDD_EXT USIM_VDD 100 K 20K Module USIM_GND USIM_VDD USIM_RST USIM_CLK USIM_DET USIM_DATA 0R 0R 0R F p 0 1 F n 0 0 1

(U)SIM Card Connector VCC RST CLK GND VPP IO 10 pF 10 pF 10 pF GND TVS Array GND GND Figure 20: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_DET unconnected. A reference circuit for (U)SIM card interface with a 6-pin (U)SIM card connector is illustrated in the following figure. RG520F&RG520N_Series_Hardware_Design 50 / 116 5G Module Series Module USIM_VDD F p 0 1 F n 0 0 1 USIM_VDD USIM_RST USIM_CLK USIM_DET USIM_DATA GND 20k 0R 0R 0R F p 0 1 F p 0 1 F p 0 1 TVS Array

(U)SIM Card Connector VPP VCC RST CLK IO GND Figure 21: Reference Circuit of a 6-Pin (U)SIM Card Connector In order to enhance the reliability and availability of the (U)SIM card in applications, please follow the criteria below in (U)SIM circuit design. Keep (U)SIM card connector as close as possible to the module. Keep the trace length as less than 200 mm as possible. Keep (U)SIM card signal traces away from RF and VBAT traces. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with ground surrounded. In order to offer better ESD protection, it is recommended to add a TVS array with a parasitic capacitance not exceeding 10 pF. The 0 resistors should be added in series between the module and the (U)SIM card connector so as to suppress EMI spurious transmission and enhance ESD protection. The 10 pF capacitors are used to filter out RF interference. The 20 k pull-up resistor on USIM_DATA trace improves anti-jamming capability and should be placed close to the (U)SIM card connector.

(U)SIM card hot plug function is not supported by default. A space was reserved for eSIM inside the module on the (U)SIM2 interface. All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout. 4.4. I2C Interface*

The module provides one I2C interface. As an open drain output, it should be pulled up to 1.8 V. Pin definition is here as follows:

RG520F&RG520N_Series_Hardware_Design 51 / 116 5G Module Series Table 15: Pin Definition of I2C Interface Pin Name Pin No. I2C_SCL I2C_SDA 77 78 Description Comment I/O OD I2C serial clock OD I2C serial data Pull each of them up to VDD_EXT with an external 4.7 k resistor. If unused, keep them open. 4.5. I2S Interface*

The module provides one I2S interface. Pin definition is here as follows:

Table 16: Pin Definition of I2S Interface Pin Name Pin No. I/O Description Comment In master mode, it is an output signal. In slave mode, it is an input signal. Can be multiplexed into PCM_SYNC. In master mode, it is an output signal. In slave mode, it is an input signal. Can be multiplexed into PCM_CLK. Can be multiplexed into PCM_DIN. Can be multiplexed into PCM_DOUT. I2S_WS 259 DIO I2S word select I2S_SCK 256 DIO I2S clock I2S_DIN I2S_DOUT MCLK 257 255 79 DI I2S data in DO I2S data out DO Clock output for codec If unused, keep it open. The following figure shows a reference design of I2S interface with an external codec IC. RG520F&RG520N_Series_Hardware_Design 52 / 116 5G Module Series MCLK I2S_SCK I2S_WS I2S_DOUT I2S_DIN I2C_SCL I2C_SDA Module K 7

. 4 K 7

. 4 1.8 V MCLK MICBIAS I2S_SCK I2S_WS I2S_DIN I2S_DOUT SCL SDA Codec INP INN S A B I LOUTP LOUTN Figure 22: Reference Circuit of I2S Application with Audio Codec 4.6. PCM Interface*

The module provides one Pulse Code Modulation (PCM) digital interface and one I2S interface. The PCM interface supports the following modes:

Primary mode (short frame synchronization, works as both master and slave) Auxiliary mode (long frame synchronization, works as master only) In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC falling edge represents the MSB. In this mode, the PCM interface supports 256 kHz, 512 kHz, 1024 kHz or 2048 kHz PCM_CLK at 8 kHz PCM_SYNC, and also supports 4096 kHz PCM_CLK at 16 kHz PCM_SYNC. In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC rising edge represents the MSB. In this mode, PCM interface operates with a 256 kHz, 512 kHz, 1024 kHz or 2048 kHz PCM_CLK and an 8 kHz, 50 % duty cycle PCM_SYNC only. Table 17: Pin Definition of PCM Interface Pin Name Pin No. I/O Description Comment PCM_SYNC PCM_CLK 71 73 DIO PCM data frame sync DIO PCM clock In master mode, it is an output signal. In slave mode, it is an RG520F&RG520N_Series_Hardware_Design 53 / 116 5G Module Series PCM_DIN PCM_DOUT 74 76 DI PCM data input DO PCM data output input signal. If unused, keep it open. The module supports 16-bit linear data format. The following figures show the primary modes timing relationship with 8 kHz PCM_SYNC and 2048 kHz PCM_CLK, as well as the auxiliary modes timing relationship with 8 kHz PCM_SYNC and 256 kHz PCM_CLK. 125 s P CM _CLK 1 2 2 5 5 2 5 6 P CM _S YNC P CM _DOUT P CM _DIN MS B LS B MS B MS B LS B MS B Figure 23: Primary Mode Timing 125 s P CM _CLK 1 2 31 32 P CM _S YNC P CM _DOUT P CM _DIN MS B MS B LS B LS B Figure 24: Auxiliary Mode Timing RG520F&RG520N_Series_Hardware_Design 54 / 116 5G Module Series Clock and mode can be configured by AT command, and the default configuration is master mode using short frame sync format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. Please refer to document [6]

about AT+QDAI command for details. The reference design is illustrated as follows:

PCM_CLK PCM_SYNC PCM_DOUT PCM_DIN I2C_SCL I2C_SDA S A B I MICBIAS INP INN LOUTP LOUTN BCLK LRCK DAC ADC SCL SDA Module K 7

. 4 K 7

. 4 1.8 V Codec Figure 25: Reference Circuit of PCM Interface 4.7. UART Interfaces The module provides four UART interfaces: one main UART interface, one debug UART interface, one Bluetooth UART interface*, and one COEX UART interface*. The following shows their features:

Main UART interface supports 115200 bps baud rate by default. This interface is used for AT command communication. Debug UART interface supports 115200 bps baud rate. It is used for Linux console and log output. Bluetooth UART interface supports 115200 bps baud rate. It is used for Bluetooth communication. It supports RTS and CTS hardware flow control. COEX UART interface is used for WWAN/WLAN coexistence mechanism only for Qualcomn platform. Pin definition of the UART interfaces is here as follows:

RG520F&RG520N_Series_Hardware_Design 55 / 116 5G Module Series Table 18: Pin Definition of UART Interfaces Pin Name Pin No. MAIN_TXD MAIN_RXD MAIN_RI*

MAIN_DTR 68 70 100 258 MAIN_DCD*

261 BT_TXD*

BT_RXD*

BT_RTS*

BT_CTS*

DBG_RXD DBG_TXD 59 63 61 62 108 105 I/O DO DI Description Comment Main UART transmit Main UART receive DO Main UART ring indication DI DO Main UART data terminal ready Main UART data carrier detect DO Bluetooth UART transmit 1.8 V power domain. DI DI DO Bluetooth UART receive DTE request to send signal to DCE Connect to DTEs RTS. 1.8 V power domain. DTE clear to send signal from DCE Connect to DTEs CTS. 1.8 V power domain. DI Debug UART receive DO Debug UART transmit 1.8 V power domain. COEX_RXD*

65 DI Coexistence UART receive Only for Qualcomn COEX_TXD*

67 DO Coexistence UART transmit platform. Signal interface used for WWAN/WLAN coexistence mechanism. Pin 65 can be multiplexed into SDX2AP_E911 function. Pin 67 can be multiplexed into SDX2AP_STATUS function. For details, please contact Quectel Technical Supports. The following figure illustrates the reference design for UART interface connection between different modules. RG520F&RG520N_Series_Hardware_Design 56 / 116 5G Module Series BT_TXD BT_UART_RXD Module BT_RXD BT_CTS BT_RTS FC60E BT_UART_TXD BT_UART_CTS BT_UART_RTS Figure 26: UART Interface Connection The module provides 1.8 V UART interfaces. A level translator should be used if the application is equipped with a 3.3 V UART interface. A level translator is recommended. VDD_1V8 VCCA 0.1 F MAIN_RI MAIN_DCD MAIN_DTR MAIN_TXD MAIN_RXD 51 K OE A1 A2 A3 A4 A5 A6 VCCB GND B1 B2 B3 B4 B5 B6 0.1 F VDD_MCU RI_MCU DCD_MCU DTR_MCU TXD_MCU RXD_MCU 51 K Translator Figure 27: Reference Circuit with Translator Chip Another example with transistor circuit is shown as below. For the design of circuits shown in dotted lines, please refer to that shown in solid lines, but pay attention to the direction of connection. RG520F&RG520N_Series_Hardware_Design 57 / 116 5G Module Series Module MAIN_RXD MAIN_TXD MAIN_DTR MAIN_RI MAIN_DCD GND 4.7 K 1 nF VDD_1V8 VDD_1V8 10 K MCU/ARM VDD_1V8 1 nF 10 K 4.7 K VDD_MCU TXD RXD GPIO EINT GPIO GND Figure 28: Reference Circuit with Transistor Circuit NOTE 1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps. 2. Other baud rates of the main UART are under development. 3. Please note that the module BT_CTS is connected to the host CTS, and the module BT_RTS is connected to the host RTS. 4.8. SDIO Interface The module provides one SDIO interface which support SD 3.0 protocol. SDIO interface is used for SD card interface. Table 19: Pin Definition of SD Card Interface Pin Name Pin No. I/O Description Comment SDIO_VDD 60 PI SDIO power supply 1.8/2.85 V configurable input. If unused, connect it to VDD_EXT. SDIO_DATA0 49 DIO SDIO data bit 0 If unused, keep them RG520F&RG520N_Series_Hardware_Design 58 / 116 SDIO_DATA1 SDIO_DATA2 SDIO_DATA3 SDIO_CMD SDIO_CLK 50 51 52 48 47 SDIO_PWR_EN 53 SDIO_PWR_ VSET SDIO_DET 56 55 5G Module Series DIO SDIO data bit 1 open. DIO SDIO data bit 2 DIO SDIO data bit 3 DIO SDIO command DO DO SDIO clock SDIO power supply enable DO SDIO power domain set DI SD hot-plug detect Pull it up to VDD_EXT with a 470 k resistor. If unused, keep it open. The following figure illustrates a reference design of SD card interface with the module. SDIO_VDD_DUAL VDD_2V95 LDO SDIO_PWR_EN LDO VDD_EXT R13 470 K C9 1 F C8 33 pF R12 NM-100 K SDIO_PWR_EN SDIO_PWR_VSET Module SDIO_VDD R7 100 K R8 100 K R9 100 K R10 100 K R11 100 K R1 0R R2 0R R3 0R R4 0R R5 0R R6 0R SDIO_DATA3 SDIO_DATA2 SDIO_DATA1 SDIO_DATA0 SDIO_CLK SDIO_CMD SDIO_DET C1 NM 27pF C2 NM 27pF C3 NM 27pF C4 NM 27pF C5 NM 27pF C6 NM 27pF TVS Array Figure 29: Reference Circuit of SD Card Interface SD Card Connector VDD CD/DAT3 DAT2 DAT1 DAT0 CLK CMD DETECTIVE VSS In SD card interface design, in order to ensure good communication performance with SD card, the following design principles should be complied with:

The voltage range of SD power supply VDD_2V95 is 2.73.6 V and a sufficient current of up to 0.8 A should be provided. SDIO_VDD_DUAL is an SDIO Bus power domain, which can be used for SD card IO signal pull-up. Note that SDIO_VDD is an input pin for the module. To avoid jitter of Bus, resistors from R7 to R11 are needed to be pulled up to SDIO_VDD_DUAL. Value of these resistors are from 10 to 100 k and the recommended value is 100 k. RG520F&RG520N_Series_Hardware_Design 59 / 116 5G Module Series In order to improve signal quality, it is recommended to add 0 resistors R1 to R6 in series between the module and the SD card connector. The bypass capacitors C1 to C6 are reserved and not mounted by default. All resistors and bypass capacitors should be placed close to the SD card connector. For good ESD protection, it is recommended to add a ESD protection components with capacitance value less than 1.2 pF on each SD card pin. It is important to route the SDIO signal traces with ground surrounded. The impedance of SDIO data trace is 50 (10 %). Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals, etc., as well as noisy signals such as clock signals, DC-DC signals, etc. Keep the trace length difference between SDIO_CLK and SDIO_DATA[0:3]/SDIO_CMD less than 2 mm and the total routing length less than 50 mm for SDR104 mode. For other speed modes, the trace length difference between SDIO_CLK and SDIO_DATA[0:3]/SDIO_CMD should be less than 6 mm and the total trace routing length less than 150 mm. Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of SDIO Bus should be less than 5.0 pF. The DETECT pin of SD card connector must be connected to the module when the SD card function is being used. Table 20: SDC Trace Length in the Module Pin No. Pin Name Length (mm) 49 50 51 52 48 47 SDIO_DATA0 SDIO_DATA1 SDIO_DATA2 SDIO_DATA3 SDIO_CMD SDIO_CLK 33.46 33.50 33.15 33.51 34.38 33.57 4.9. ADC Interface The module provides one Analog-to-Digital Converter (ADC) interface. In order to improve the accuracy of ADC, the trace of ADC interface should be surrounded by ground. RG520F&RG520N_Series_Hardware_Design 60 / 116 5G Module Series Table 21: Pin Definition of ADC Interface Pin Name ADC0 Pin No. 241 I/O AI Description General-purpose ADC interface The voltage value on ADC pin can be read via AT+QADC=<port> command:

AT+QADC=0: read the voltage value on ADC0 For more details about the AT command, please refer to document [6]. Table 22: Characteristics of ADC Interface Name Min. ADC0 Voltage Range 0 ADC Input Resistance 398 ADC Resolution ADC Sample Rate

NOTE Typ.

400 64.879 4.8 Max. 1.875 402

Unit V k V MHz 1. The input voltage of ADC should not exceed its corresponding voltage range. It is prohibited to supply any voltage to ADC pin when VBAT is removed. 2. It is recommended to use resistor divider circuit for ADC application. 3. 4.10. SPI Interface The module provides one SPI interface which only supports master mode with a maximum clock frequency of up to 50 MHz. Table 23: Pin Definition of SPI Interface Pin Name Pin No. SPI_CLK 210 I/O DO Description Comment SPI clock 1.8 V power domain. RG520F&RG520N_Series_Hardware_Design 61 / 116 5G Module Series SPI_CS SPI_MISO SPI_MOSI 207 213 204 DO SPI chip select DI SPI master-in slave-out DO SPI master-out slave-in Only master mode is supported. The module provides a 1.8 V SPI interface. Use a level shifter between the module and the host if the application is equipped with a 3.3 V processor or device interface. The following figure shows a reference design. VDD_EXT VCCA 0.1 F SPI_CS SPI_CLK SPI_MOSI SPI_MISO Translator OE A1 A2 A3 A4 NC VCCB GND B1 B2 B3 B4 NC 0.1 F VDD_MCU SPI_CS_N_MCU SPI_CLK_MCU SPI_MOSI_MCU SPI_MISO_MCU Figure 30: Reference Circuit of SPI Interface with a Level Translator 4.11. PCIe Interface The module provides one integrated PCIe (Peripheral Component Interconnect Express) interface, which follows PCI Express Specification Revision 3.0/4.0. The key features of the PCIe interface are mentioned below:

PCI Express Specification Revision 3.0/4.0 Compliance. Data rate at 8 Gbps per lane for PCIe 3.0 and only lane 0 can be 16 Gbps for PCIe 4.0. Can be used to connect to an external Ethernet IC (MAC and PHY) or Wi-Fi IC. Table 24: Pin Definition of PCIe Interface Pin Name Pin No. I/O Description Comment PCIE_REFCLK_P 40 AIO PCIe reference clock (+) PCIE_REFCLK_M 38 AIO PCIe reference clock (-) Requires differential impedance of 85 . One PCIe port is RG520F&RG520N_Series_Hardware_Design 62 / 116 5G Module Series PCIE_TX0_M PCIE_TX0_P PCIE_TX1_M PCIE_TX1_P PCIE_RX0_M PCIE_RX0_P PCIE_RX1_M PCIE_RX1_P 44 46 41 43 32 34 35 37 AO AO AO AO AI AI AI AI PCIe transmit 0 (-) PCIe transmit 0 (+) PCIe transmit 1 (-) PCIe transmit 1 (+) PCIe receive 0 (-) PCIe receive 0 (+) PCIe receive 1 (-) PCIe receive 1 (+) PCIE_CLKREQ_N 36 OD PCIe clock request PCIE_RST_N 39 DIO PCIe reset PCIE_WAKE_N 30 OD PCIe wake up The following figure illustrates the PCIe interface connection. supported. It can be either Gen 3 2-lane or Gen 4 1-lane. 1.8 V power domain. In root complex mode, it is an input signal. In endpoint mode, it is an output signal. 1.8 V power domain. In root complex mode, it is an output signal. In endpoint mode, it is an input signal. 1.8 V power domain. In root complex mode, it is an input signal. In endpoint mode, it is an output signal. RG520F&RG520N_Series_Hardware_Design 63 / 116 5G Module Series VDD_EXT R1 100K R2 100K R3 NM_100K PCIE_CLKREQ_N PCIE_WAKE_N PCIE_RST_N Module PCIE_REFCLK_P PCIE_REFCLK_M PCIE_TX0_M PCIE_TX0_P PCIE_RX0_M PCIE_RX0_P R4 0R R5 0R C1 220 nF C2 220 nF PCIE_CLKREQ_N PCIE_WAKE_N PCIE_RST_N PCIE_REFCLK_P PCIE_REFCLK_M Other PCIE_RX_M PCIE_RX_P PCIE_TX_M PCIE_TX_P C3 220 nF C4 220 nF Figure 31: PCIe Interface Connection The following principles of PCIe interface design should be complied with to meet PCIe specifications. It is important to route the PCIe signal traces as differential pairs with ground surrounded. The differential impedance is 72.597.5 and 85 is recommended. PCIe signals must be protected from noisy signals (clocks, DC-DC, RF and so forth). All other sensitive/high-speed signals and circuits must be routed far away from PCIe traces. For each differential pair, intra-lane length match should be less than 0.7 mm. Inter-lane length match, that is, the trace length matching between the reference clock, Tx, and Rx pairs) is not required. The space between Tx and Rx, and the spacing between PCIe lanes and all other signals, should be larger than 4 times of the trace width. PCIe Tx AC coupling capacitors can be anywhere along the line, but better to be placed close to source or connector side to keep good signal integrity of main route on PCB. Ensure not to stagger the capacitors. This can affect the differential integrity of the design and can create EMI. PCIe Tx AC coupling capacitors should be 220 nF for Gen 3/Gen 4, and 100 nF is recommended for Gen 2/Gen 1 application. In the case of trace serpentines, one line of a differential pair must be routed to make up a length delta, then it must be routed at the source (breakout) this ensures that lines stay differential thereafter. To reduce the probability for layer-to-layer manufacturing variation, minimize layer transitions on the main route (in other words, apply layer transitions only at module breakouts and connectors to ensure minimum layer transitions on the main route). RG520F&RG520N_Series_Hardware_Design 64 / 116 5G Module Series Table 25: PCIe Trace Length in the Module Pin No. Pin Name Length (mm) Length Difference (P-M) (mm)

-0.06

-0.03

-0.01

-0.17 0.03 40 38 46 44 43 41 34 32 37 35 PCIE_REFCLK_P PCIE_REFCLK_M PCIE_TX0_P PCIE_TX0_M PCIE_TX1_P PCIE_TX1_M PCIE_RX0_P PCIE_RX0_M PCIE_RX1_P PCIE_RX1_M 7.52 7.58 12.87 12.90 10.36 10.37 3.92 4.09 4.88 4.85 4.12. Control Signal Relative interfaces pin descriptions are here as follows:

Table 26: Pin Definition of Control Signal Pin Name Pin No. W_DISABLE#

WL_SW_CTRL 114 180 I/O DI DI Description Airplane mode control 76.8 MHz system clock request 4.12.1. W_DISABLE#

The module provides a W_DISABLE# pin to enable or disable airplane mode through hardware operation. W_DISABLE# is pulled up by default, and driving it low will set the module to airplane mode. The RF function can also be enabled or disabled through software AT commands. RG520F&RG520N_Series_Hardware_Design 65 / 116 5G Module Series Table 27: RF Function Status W_DISABLE# Level AT Commands RF Function Status High Level High Level Low Level AT+CFUN=1 AT+CFUN=0 AT+CFUN=4 AT+CFUN=0 AT+CFUN=1 AT+CFUN=4 Enabled Disabled Disabled 4.13. Indication Signal Relative interfaces pin descriptions are here as follows:

Table 28: Pin Definition of Indication Signal Pin Name Pin No. I/O Description Comment NET_MODE 240 STATUS 237 NET_STATUS 243 SLEEP_IND 102 DO DO DO DO Indicates whether the module has registered on 5G network Indicates the modules operation status Indicates the modules network activity status Indicates the modules sleep mode 1.8 V power domain. 4.13.1. Network Status Indication The network indication pins can be used to drive network status indication LEDs. The module provides two network indication pins: NET_MODE and NET_STATUS. The following tables describe pin definition and logic level changes in different network status. RG520F&RG520N_Series_Hardware_Design 66 / 116 5G Module Series Table 29: Working State of the Network Connection Status/Activity Indication Pin Name Status Description NET_MODE Always High Always Low Registered on 5G network Others Flicker slowly (200 ms High/1800 ms Low) Network searching Flicker slowly (1800 ms High/200 ms Low) Idle NET_STATUS Flicker quickly (125 ms High/125 ms Low) Data transfer is ongoing Always High Voice calling Module VBAT Network Indicator 4.7K 2.2K 47K Figure 32: Reference Circuit of the Network Status Indication 4.13.2. STATUS The STATUS pin is an open drain output for indicating the modules operation status. It will output high level when module is powered ON successfully. A reference circuit is shown as below. RG520F&RG520N_Series_Hardware_Design 67 / 116 5G Module Series Module STATUS 4.7K VBAT 2.2K 47K Figure 33: Reference Circuits of STATUS 4.14. IPQ Status and Err Fatal Interface*

The module provides one IPQ status interface and one Err Fatal interface for connection between the module and IPQ. The following tables show the pin definition. Table 30: Pin Definition of IPQ Status and Err Fatal Interface Pin Name Pin No. I/O Description Comment COEX_RXD 65 DI Coexistence UART receive COEX_TXD 67 DO Coexistence UART transmit Only for Qualcomn platform. Signal interface used for WWAN/WLAN coexistence mechanism. Pin 65 can be multiplexed into SDX2AP_E911 function. Pin 67 can be multiplexed into SDX2AP_STATUS function. For details, please contact Quectel Technical Supports. GPIO_32 98 DO Supports time service and repeater functions;

supports 1PPS pulse output and frame synchronization Can be multiplexed into AP2SDX_STATUS function. For details, please contact Quectel Technical Supports. RG520F&RG520N_Series_Hardware_Design 68 / 116 5G Module Series The following figure shows a reference design of the module with IPQ GPIOs. Module COEX_RXD COEX_TXD GPIO_32 IPQ 5018 SDX2AP_E911 SDX2AP_STATUS AP2SDX_STATUS Figure 34: Module with IPQ GPIO Application NOTE IPQ5018 is used by default here. 4.15. MAIN_RI*

AT+QCFG= risignaltype, physical command can be used to configure MAIN_RI behavior. No matter on which port a URC is presented, the URC will trigger the behavior of MAIN_RI pin. NOTE The URC can be outputted via UART port, USB AT port and USB modem port, which can be set by AT+QURCCFG command. The default port is USB AT port. In addition, MAIN_RI behaviors can be configured flexibly. The default behavior of the MAIN_RI is shown as below. Table 31: Behaviors of the RI State Idle Response MAIN_RI keeps at high level. RG520F&RG520N_Series_Hardware_Design 69 / 116 5G Module Series URC MAIN_RI outputs 120 ms low pulse when a new URC return. The MAIN_RI behavior can be changed via AT+QCFG="urc/ri/ring"*. Please refer to document [6] for details. 4.16. Time Service and Repeater Interface*

Time service provides time information for other devices or systems through standard or customized interfaces and protocols. Its basic channels are shortwave, TV signals, cables, networks, satellites, base stations, etc. Repeater is a kind of wireless signal relay device, which amplifies the base station signal and then transmits it to areas with weak signal coverage, expanding the network coverage. Repeater is a kind of wireless signal relay device, which amplifies the base station signal and then transmits it to areas with weak signal coverage, expanding the network coverage. With GNSS time service and repeater functions, the module can provide 1PPS pulse output, and can execute time service through AT commands based on baseline SIB9 system messages. Table 32: Pin Definition of Time Service and Repeater Function Pin Name Pin No. I/O Description Comment GPIO_32 98 DO Supports time service and repeater functions;

supports 1PPS pulse output and frame synchronization 1.8 V power domain. Can be multiplexed into AP2SDX_STATUS function. For details, please contact Quectel Technical Supports. NOTE If GPIO_32 is needed for other purposes, its default function should be disabled in the relevant software configuration. 4.17. GRFC Interfaces*

The module provides two generic RF control interfaces for the control of external antenna tuners. RG520F&RG520N_Series_Hardware_Design 70 / 116 5G Module Series Table 33: Pin Definition of GRFC Interfaces Pin Name Pin No. I/O Default Status Description Comment SDR_GRFC0 171 SDR_GRFC1 174 DO DO PD PD GRFC interface dedicated for external antenna tuner control If unused, keep them open. Table 34: Logic Levels of GRFC Interfaces Parameter VOL VOH Min. 0 1.35 Max. 0.45 1.8 Unit V V Table 35: Truth Table of GRFC Interfaces GRFC1 Level GRFC2 Level Frequency Range (MHz) Band Low Low High High Low High Low High TBD TBD TBD TBD TBD TBD TBD TBD RG520F&RG520N_Series_Hardware_Design 71 / 116 5G Module Series 5 RF Specifications 5.1. Cellular Network 5.1.1. Antenna Interface & Frequency Bands The pin definition is shown below:

Table 36: Pin Definition of Cellular Network Interface for RG520F-NA*/RG520N-NA Pin Name Pin No. I/O Description Comment ANT0 130 AIO Antenna 0 interface:

5G NR: n41 TRX1 & n77/n78 TRX0 LTE: LMB_TRX0 & HB_TRX1 & UHB_TRX0 ANT1 157 AIO

Antenna 1 interface:

5G NR: n41 DRX MIMO & n77/n78 DRX MIMO LTE: LMB_PRX MIMO & HB_DRX MIMO &

UHB_DRX MIMO & LAA_PRX ANT2 166 AIO

Antenna 2 interface:

5G NR: n41 PRX MIMO & n77/n78 PRX MIMO LTE: LMB_DRX MIMO & HB_PRX MIMO &

UHB_PRX MIMO & LAA_DRX 50 impedance ANT3 184 AIO Antenna 3 interface:

5G NR: n41 TRX0 & n77/n78 TRX1 LTE: LMB_TRX1 & HB_TRX0 & UHB_TRX1 RG520F&RG520N_Series_Hardware_Design 72 / 116 5G Module Series Table 37: Pin Definition of Cellular Network Interface for RG520F-EU*/RG520N-EU Pin Name Pin No. I/O Description Comment ANT0 130 AIO Antenna 0 interface:

5G NR: n41 TRX1 & n77/n78 TRX0 LTE: LMB_TRX0 & HB_TRX1 &

UHB_TRX0

- WCDMA: LMB_TRX ANT1 157 AIO

Antenna 1 interface:

5G NR: n41 DRX MIMO & n77/n78 DRX MIMO LTE: LMB_PRX MIMO & HB_DRX MIMO & UHB_DRX MIMO ANT2 166 AIO

Antenna 2 interface:

5G NR: n41 PRX MIMO & n77/n78 PRX MIMO LTE: LMB_DRX MIMO & HB_PRX MIMO & UHB_PRX MIMO 50 impedance ANT3 184 AIO ANT4 ANT5 121 175 AI AI Antenna 3 interface:

5G NR: n41 TRX0 & n77/n78 TRX1 LTE: LMB_TRX1 & HB_TRX0 &

UHB_TRX1

- WCDMA: LMB_DRX Antenna 4 interface:

LTE: B32_PRX (optional) Antenna 5 interface:

LTE: B32_DRX (optional) RG520F&RG520N_Series_Hardware_Design 73 / 116 5G Module Series Table 38: Cellular Network Antenna Mapping for RG520F-NA*/RG520N-NA Antenna WCDMA LTE 5G NR Refarmed n41 n77/n78 LB (MHz) MHB (MHz) n77/n78

(MHz) Pin No. ANT0 ANT1 ANT2 ANT3

LMB_TRX0, HB_TRX1, UHB_TRX0 LMB_PRX MIMO, HB_DRX MIMO, UHB_DRX MIMO, LAA_PRX LMB_DRX MIMO, HB_PRX MIMO, UHB_PRX MIMO, LAA_DRX LMB_TRX1, HB_TRX0, UHB_TRX1 LMB_TRX0, HB_TRX1 LMB_PRX MIMO, HB_DRX MIMO LMB_DRX MIMO, HB_PRX MIMO LMB_TRX1, HB_TRX0 TRX1 TRX0 617960 17102690 33004200 130 DRX MIMO DRX MIMO 617960 17102690 33004200 157 PRX MIMO PRX MIMO 617960 17102690 33004200 166 TRX0 TRX1 617960 17102690 33004200 184 RG520F&RG520N_Series_Hardware_Design 74 / 116 5G Module Series Table 39: Cellular Network Antenna Mapping for RG520F-EU*/RG520N-EU Antenna WCDMA LTE 5G NR Refarmed n41 n77/n78 LB (MHz) MHB (MHz) n77/n78

(MHz) Pin No. ANT0 LMB_TRX ANT1 ANT2

ANT3 LMB_DRX LMB_TRX0, HB_TRX1, UHB_TRX0 LMB_PRX MIMO, HB_DRX MIMO, UHB_DRX MIMO LMB_DRX MIMO, HB_PRX MIMO, UHB_PRX MIMO LMB_TRX1, HB_TRX0, UHB_TRX1 LMB_TRX0, HB_TRX1 LMB_PRX MIMO, HB_DRX MIMO LMB_DRX MIMO, HB_PRX MIMO LMB_TRX1, HB_TRX0 TRX1 TRX0 617960 14272690 33004200 130 DRX MIMO DRX MIMO 617960 14272690 33004200 157 PRX MIMO PRX MIMO 617960 14272690 33004200 166 TRX0 TRX1 617960 14272690 33004200 184 ANT4 ANT5

B32_PRX (Optional) B32_DRX (Optional)

14271496 14271496

121 175 NOTE 1. LTE L/M/H/UHB_TRX1 is activated when 5G NR FDD L/M/H/UHB bands are supported in NSA mode. 2. LTE UHB frequency range: 34003800 MHz. 3. TRX0/1 = TX0/1 + PRX/DRX. 4. LTE LB 4 4 MIMO is optional. Even if it is not required, to support LB + LB CA or EN-DC combinations, ANT0ANT3 must support low bands. RG520F&RG520N_Series_Hardware_Design 75 / 116 5G Module Series 5.1.2. Tx Power The following table shows the RF output power of the module. Table 40: Tx Power Mode Frequency Max. Min. WCDMA WCDMA bands 24 dBm +1/-3 dB (Class 3)

<-50 dBm LTE bands 23 dBm 2 dB (Class 3)

<-40 dBm LTE HPUE bands (B38/B41/B42) 26 dBm 2 dB (Class 2)

<-40 dBm 5G NR bands 23 dBm 2 dB (Class 3)

<-40 dBm 5G NR HPUE bands

(n38/n41/n77/n78) 26 dBm +2/-3 dB (Class 2)

<-40 dBm LTE 5G NR

. NOTE For 5G NR bands, they have different standards for different channel bandwidth, please refer to the specifications as described in Clause 6.3.1 of TS 38.101-1 [2]. 5.1.3. Rx Sensitivity The following table shows conducted RF receiving sensitivity of the module. Table 41: Conducted RF Receiving Sensitivity of RG520F-NA*/RG520N-NA Frequency LTE-FDD B2

(10 MHz) LTE-FDD B4

(10 MHz) LTE-FDD B5

(10 MHz) Receiving Sensitivity (Typ.) Primary Diversity SIMO TBD TBD TBD TBD TBD TBD TBD TBD TBD 3GPP Requirement

(SIMO)

-95.0 dBm

-97.0 dBm

-95.0 dBm RG520F&RG520N_Series_Hardware_Design 76 / 116 5G Module Series LTE-FDD B7

(10 MHz) LTE-FDD B12

(10 MHz) LTE-FDD B13

(10 MHz) LTE-FDD B14

(10 MHz) LTE-FDD B17

(10 MHz) LTE-FDD B25

(10 MHz) LTE-FDD B26

(10 MHz) LTE-FDD B29

(10 MHz) LTE-FDD B30

(10 MHz) LTE-TDD B38

(10 MHz) LTE-TDD B41

(10 MHz) LTE-TDD B42

(10 MHz) LTE-TDD B43

(10 MHz) LTE-TDD B46

(10 MHz) LTE-TDD B48

(10 MHz) LTE-FDD B66

(10 MHz) LTE-FDD B71

(10 MHz) 5G NR FDD n2

(20 MHz) 5G NR FDD n5

(20 MHz) 5G NR FDD n7

(20 MHz) 5G NR FDD n12

(10 MHz) 5G NR FDD n13

(10 MHz) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

-95.0 dBm

-94.0 dBm

-94.0 dBm

-94.0 dBm

-94.0 dBm

-93.5 dBm

-94.5 dBm TBD

-96.0 dBm

-97.0 dBm

-95.0 dBm

-96.0 dBm

-96.0 dBm TBD

-96.0 dBm

-96.5 dBm

-94.2 dBm

-91.8 dBm

-90.8 dBm

-91.8 dBm

-93.8 dBm TBD RG520F&RG520N_Series_Hardware_Design 77 / 116 5G Module Series 5G NR FDD n14

(10 MHz) 5G NR FDD n25

(20 MHz) 5G NR TDD n26

(20 MHz) 5G NR FDD n29

(10 MHz) 5G NR FDD n30

(10 MHz) 5G NR TDD n38

(20 MHz) 5G NR TDD n41

(100 MHz) 5G NR TDD n48

(20 MHz) 5G NR FDD n66

(20 MHz) 5G NR FDD n70

(20 MHz) 5G NR FDD n71

(20 MHz) 5G NR TDD n77

(100 MHz) 5G NR TDD n78

(100 MHz) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Table 42: Conducted RF Receiving Sensitivity of RG520F-EU*/RG520N-EU Frequency WCDMA B1 WCDMA B5 WCDMA B8 LTE-FDD B1

(10 MHz) LTE-FDD B3

(10 MHz) LTE-FDD B5

(10 MHz) Receiving Sensitivity (Typ.) Primary Diversity SIMO TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

-93.8 dBm

-90.3 dBm

-87.6 dBm TBD

-95.8 dBm

-93.8 dBm

-84.7 dBm

-92.9 dBm

-93.3 dBm

-93.8 dBm

-86.0 dBm

-85.1 dBm

-85.6 dBm 3GPP Requirement

(SIMO)

-106.7 dBm

-104.7 dBm

-103.7 dBm

-97.0 dBm

-94.0 dBm

-95.0 dBm RG520F&RG520N_Series_Hardware_Design 78 / 116 5G Module Series LTE-FDD B7

(10 MHz) LTE-FDD B8

(10 MHz) LTE-FDD B20

(10 MHz) LTE-FDD B28

(10 MHz) LTE-TDD B32

(10 MHz) LTE-TDD B38

(10 MHz) LTE-TDD B40

(10 MHz) LTE-TDD B41

(10 MHz) LTE-TDD B42

(10 MHz) LTE-TDD B43

(10 MHz) 5G NR FDD n1

(20 MHz) 5G NR FDD n3

(20 MHz) 5G NR FDD n5

(20 MHz) 5G NR FDD n7

(20 MHz) 5G NR FDD n8

(20 MHz) 5G NR FDD n20

(20 MHz) 5G NR FDD n28

(20 MHz) 5G NR TDD n38

(20 MHz) 5G NR TDD n40

(20 MHz) 5G NR TDD n41

(100 MHz) 5G NR TDD n75

(20 MHz) 5G NR TDD n76

(5 MHz) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

-95.0 dBm

-94.0 dBm

-94.0 dBm

-95.5 dBm TBD

-97.0 dBm

-97.0 dBm

-95.0 dBm

-96.0 dBm

-96.0 dBm

-93.8 dBm

-90.8 dBm

-90.8 dBm

-91.8 dBm

-90.0 dBm

-89.8 dBm

-90.8 dBm

-94.0 dBm

-94.0 dBm

-84.7 dBm

-93.8 dBm

-100 dBm RG520F&RG520N_Series_Hardware_Design 79 / 116 5G Module Series 5G NR TDD n77

(100 MHz) 5G NR TDD n78

(100 MHz) TBD TBD TBD TBD TBD TBD

-85.1 dBm

-85.6 dBm 5.1.4. Reference Design RG520F-NA* and RG520N-NA modules provide 4 RF cellular antenna interfaces for antenna connection. RG520F-EU* and RG520N-EU modules provide 6 RF cellular antenna interfaces for antenna connection. It is recommended to reserve a -type matching circuit for better RF performance, and the -type matching components (C1, R1, and C2) should be placed as close to the antenna as possible. The capacitors are not mounted by default. Module ANT0 ANT5 R1 0R R6 0R C1 NM C9 NM C2 NM C10 NM Figure 35: Reference Circuit for RF Antenna Interfaces

. NOTE 1. Use a -type circuit for all the antenna circuits to facilitate future debugging. 2. Keep the impedance of the cellular antennas (ANT0ANT5) traces as 50 when routing. 3. Keep at least 15 dB isolation between RF antennas to improve the receiving sensitivity, and at least 20 dB isolation between 5G NR UL MIMO antennas. 4. Keep 75 dB isolation between each two antenna traces. 5. Keep digital circuits such as switch mode power supply, (U)SIM card, USB interface, camera module, display connector and SD card away from the antenna traces. RG520F&RG520N_Series_Hardware_Design 80 / 116 5G Module Series 5.2. GNSS The module includes a fully integrated global navigation satellite system solution that supports GPS, GLONASS, BDS, Galileo and QZSS. The module supports standard NMEA-0183 protocol, and outputs NMEA sentences via USB interface

(data update rate: 110 Hz, 1 Hz by default). By default, the modules GNSS function is switched off. It must be switched on via AT command. For more details about GNSS functions technology and configurations, please refer to document [7]. 5.2.1. Antenna Interface & Frequency Bands The following table shows the pin definition, frequency, and performance of GNSS antenna interface. Table 43: Pin Definition of GNSS Antenna Interface Pin Name Pin No. ANT_GNSS 193 I/O AI Description Comment GNSS antenna interface 50 impedance Table 44: GNSS Frequency Type GPS Frequency Unit 1575.42 1.023 (GPS L1) 1176.45 10.23 (GPS L5) GLONASS 1597.51605.8 Galileo BDS QZSS 1575.42 2.046 MHz 1561.098 2.046 1575.42 (L1) 1176.45 (L5) RG520F&RG520N_Series_Hardware_Design 81 / 116 5G Module Series 5.2.2. GNSS Performance Table 45: GNSS Performance Parameter Description Conditions Cold start Sensitivity (GNSS) Reacquisition Autonomous Tracking Cold start Typ. TBD TBD TBD TBD TTFF (GNSS)

@ open sky XTRA enabled TBD Warm start Autonomous TBD

@ open sky XTRA enabled TBD Hot start Autonomous TBD

@ open sky XTRA enabled TBD Unit dBm s Accuracy (GNSS) CEP-50 Autonomous

@ open sky TBD m

. NOTE 1. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes. 2. Re-acquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can fix position again within 3 minutes after loss of lock. 3. Cold start sensitivity: the lowest GNSS signal value at the antenna port on which the module fixes position within 3 minutes after executing cold start commands. RG520F&RG520N_Series_Hardware_Design 82 / 116 5G Module Series 5.2.3. Reference Design The following is the reference circuit of GNSS antenna. VDD 0.1 F 10 R GNSS Antenna 47 nH 100 pF 0 R NM NM Module ANT_GNSS Figure 36: Reference Circuit of GNSS Antenna

. NOTE If the module is designed with a passive antenna, then the VDD circuit is not needed. 1. An external LDO can be selected to supply power according to the active antenna requirement. 2. 3. Keep the characteristic impedance for ANT_GNSS trace as 50 . 4. Place the -type matching components as close to the antenna as possible. 5. Keep Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card away from the antenna traces. 6. Keep 75 dB isolation between GNSS and cellular antenna traces. 7. Keep 15 dB isolation between GNSS and cellular antennas to improve the receiving sensitivity. 5.3. Reference Design of RF Routing For users PCB, the characteristic impedance of all RF traces should be controlled to 50 . The impedance of the RF traces is usually determined by the trace width (W), the materials dielectric constant, height from the reference ground to the signal layer (H), and the space between RF traces and grounds

(S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB structures. RG520F&RG520N_Series_Hardware_Design 83 / 116 5G Module Series Figure 37: Microstrip Design on a 2-layer PCB Figure 38: Coplanar Waveguide Design on a 2-layer PCB Figure 39: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) RG520F&RG520N_Series_Hardware_Design 84 / 116 5G Module Series Figure 40: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:

Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 . The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground. The distance between the RF pins and the RF connector should be as short as possible, and all the right-angle traces should be changed to curved ones. There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, ground vias around RF traces and the reference ground improves RF performance. The distance between the ground vias and RF traces should be more than two times the width of RF signal traces (2 W). For more details about RF layout, please refer to document [8]. RG520F&RG520N_Series_Hardware_Design 85 / 116 5G Module Series 5.4. Antenna Requirements Table 46: Antenna Requirements Antenna Type Requirements GNSS 5G NR/LTE/WCDMA Frequency range 1: 15591606 MHz Frequency range 2: 11661187 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0 dBi Active antenna noise figure: < 1.5 dB Active antenna gain: > -2 dBi Active antenna embedded LNA gain: 17 dB VSWR: 2 Efficiency: > 30 %

Gain: 1 dBi Max input power: 50 W Input impedance: 50 Polarization: Vertical Cable insertion loss:

< 1 dB: LB (<1 GHz)

< 1.5 dB: MB (12.3 GHz)

< 2 dB: HB (> 2.3 GHz)

RG520F&RG520N_Series_Hardware_Design 86 / 116 5G Module Series 5.5. RF Connector Recommendation The receptacle dimensions are illustrated as below. Figure 41: Dimensions of the Receptacles (Unit: mm) RG520F&RG520N_Series_Hardware_Design 87 / 116 5G Module Series The following figure shows the specifications of mating plugs using 0.81 mm coaxial cables. Figure 42: Specifications of Mating Plugs Using 0.81 mm Coaxial Cables (Unit: mm) 5.5.1. Recommended RF Connector for Installation 5.5.1.1. Assemble Coaxial Cable Plug Manually The illustration for plugging in a coaxial cable plug is shown below, = 90 is acceptable, while 90 is not. RG520F&RG520N_Series_Hardware_Design 88 / 116 5G Module Series Figure 43: Plug in a Coaxial Cable Plug The illustration of pulling out the coaxial cable plug is shown below, = 90 is acceptable, while 90 is not. Figure 44: Pull out a Coaxial Cable Plug 5.5.1.2. Assemble Coaxial Cable Plug with Fixture The pictures of installing the coaxial cable plug with a fixture is shown below, = 90 is acceptable, while 90 is not. RG520F&RG520N_Series_Hardware_Design 89 / 116 5G Module Series Figure 45: Install the Coaxial Cable Plug with Fixture 5.5.2. Recommended Manufacturers of RF Connector and Cable For more details, visit https://www.i-pex.com. RG520F&RG520N_Series_Hardware_Design 90 / 116 5G Module Series 6 Electrical Characteristics &

Reliability 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 47: Absolute Maximum Ratings Parameter VBAT_RF/VBAT_BB USB_VBUS Peak Current of VBAT_BB Peak Current of VBAT_RF Voltage on Digital Pins Voltage at ADC0 Min.

-0.5

-0.3

-0.5

-0.5 Max. 6.0 5.5 TBD TBD 2.2 2.2 Unit V V A A V V RG520F&RG520N_Series_Hardware_Design 91 / 116 5G Module Series 6.2. Power Supply Ratings Table 48: Module Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT VBAT_BB and VBAT_RF USB_VBUS USB connection detection The actual input voltages must stay between the minimum and maximum values 3.3 3.8 4.4 V 3.3 5.0 5.25 V 6.3. Power Consumption Table 49: Averaged Power Consumption for the Module Mode Conditions Band/Combinations Current Unit Power-off Power off RF Disabled AT+CFUN=0 (USB 3.0 suspend) AT+CFUN=4 (USB 3.0 suspend) Sleep State Idle State SA FDD PF = 64 (USB 3.0 suspend) SA TDD PF = 64 (USB 3.0 suspend) SA PF = 64 (USB 2.0 active) SA PF = 64 (USB 3.0 active) LTE LB @ 23 dBm LTE LTE MB @ 23 dBm LTE CA LTE HB @ 23 dBm DL 3CA, 256QAM UL 1CA, 256QAM

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A mA mA mA mA mA mA mA mA mA TBD mA RG520F&RG520N_Series_Hardware_Design 92 / 116 5G Module Series Tx power @ 23 dBm 5G NR LB @ 23 dBm 5G NR MB @ 23 dBm 5G NR HB @ 23 dBm 5G NR UHB @ 26 dBm TBD TBD TBD TBD 5G NR UL 2 2 MIMO @ 26 dBm TBD DL 2CA, 256QAM 5G SA

(1 Tx) 5G SA

(2 Tx) TBD TBD TBD TBD TBD mA mA mA mA mA 5G SA CA UL 1CA, 256QAM TBD TBD mA LTE + 5G EN-DC Tx power @ 26 dBm LTE DL, 256QAM LTE UL QPSK NR DL, 256QAM NR UL QPSK LTE Tx Power @ 23 dBm NR Tx Power @ 23 dBm 6.4. Digital I/O Characteristic Table 50: 1.8 V I/O Requirements Parameter Description VIH VIL VOH VOL Min. 1.26

-0.3 Input high voltage Input low voltage Output high voltage 1.35 Output low voltage 0 TBD TBD mA Max. 2.1 0.54 1.8 0.45 Unit V V V V RG520F&RG520N_Series_Hardware_Design 93 / 116 5G Module Series Table 51: (U)SIM 1.8 V I/O Requirements Parameter Description USIM_VDD Power supply Input high voltage Input low voltage Output high voltage 1.44 Output low voltage 0.0 Table 52: (U)SIM 2.95 V I/O Requirements Parameter Description USIM_VDD Power supply Input high voltage Input low voltage Output high voltage 2.36 Output low voltage 0.0 Min. 1.65 1.26

-0.3 Min. 2.7 2.06

-0.3 VIH VIL VOH VOL VIH VIL VOH VOL Max. Unit 1.95 2.1 0.36 1.8 0.4 V V V V V Max. Unit 3.05 3.25 0.59 2.95 0.4 V V V V V 6.5. ESD Protection If the static electricity generated by various ways discharges to the module, the module maybe damaged to a certain extent. Thus, please take proper ESD countermeasures and handling methods. For example, wearing anti-static gloves during the development, production, assembly and testing of the module;

adding ESD protective components to the ESD sensitive interfaces and points in the product design. Table 53: Electrostatics Discharge Characteristics (25 C, 45 % Relative Humidity) Tested Interfaces Contact Discharge Air Discharge Unit VBAT, GND All Antenna Interfaces 5 4 10 8 kV kV RG520F&RG520N_Series_Hardware_Design 94 / 116 5G Module Series Other Interfaces 0.5 1 kV 6.6. Operating and Storage Temperatures Table 54: Operating and Storage Temperatures Parameter Operating Temperature Range 12 Min.

-30 Extended Operating Temperature Range 13

-40 Storage temperature range

-40 Typ.

+25

Max. Unit

+75

+85

+90 C C C 6.7. Thermal Consideration In order to achieve better performance of the module, it is recommended to comply with the following principles for thermal consideration:

On customers PCB design, keep the module away from heat sources, especially high-power components such as processor, power amplifier, and power supply. Do not place large size components in the area where the module is located on the PCB, in order to facilitate the installation of heatsink. Maintain the integrity of the PCB copper layer and place as many thermal vias as possible. Considering the heat dissipation characteristics of the module, the heatsink should be attached on the top of the module. The heatsink should be designed with adequate fins to dissipate heat, and TIM (Thermal Interface Material) in contact between the heat sink and the module should have high thermal conductivity, good softness and good wettability. The heatsink should be fastened with four screws to ensure that it is in close contact with the module, so as to prevent the heatsink from falling off during the drop, vibration test, and transportation. The following figures show the placement and fixing of the heat sink for reference. 12 To meet this operating temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module can meet 3GPP specifications. 13 To meet this extended temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module remains the ability to establish and maintain functions such as voice, SMS, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may undergo a reduction in value, exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again. RG520F&RG520N_Series_Hardware_Design 95 / 116 5G Module Series Figure 46: Heatsink Placement Figure 47: Heatsink Fixing The module offers the best performance when the internal IC chips stay below its maximum junction temperature, When IC reaches or exceeds this temperature, the module may still work but the performance and function (such as RF output power, data rate, etc.) will be affected to a certain extent. Therefore, the thermal design should be maximally optimized to make sure all internal ICs temperature always maintains below the maximum junction temperature with enough margin. RG520F&RG520N_Series_Hardware_Design 96 / 116 5G Module Series 7 Mechanical Information This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are 0.2 mm unless otherwise specified. 7.1. Mechanical Dimensions Pin 1 Figure 48: Module Top and Side Dimensions (Unit: mm) RG520F&RG520N_Series_Hardware_Design 97 / 116 5G Module Series Figure 49: Module Bottom Dimensions (Bottom View, Unit: mm) NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard. RG520F&RG520N_Series_Hardware_Design 98 / 116 5G Module Series 7.2. Recommended Footprint Pin 1 Figure 50: Recommended Footprint

. NOTE 1. Keep at least 3 mm between the module and other components on the motherboard to improve soldering quality and maintenance convenience. 2. To keep the reliability of the mounting and soldering, keep the motherboard thickness as at least 1.2 mm. RG520F&RG520N_Series_Hardware_Design 99 / 116 5G Module Series 7.3. Top and Bottom Views Figure 51: Top & Bottom Views of RG520N Series Figure 52: Top & Bottom Views of RG520F Series NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. RG520F&RG520N_Series_Hardware_Design 100 / 116 5G Module Series 8 Storage, Manufacturing & Packaging 8.1. Storage Conditions The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 5 C and the relative humidity should be 3560 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in recommended storage condition. 3. The floor life of the module is 168 hours 14 in a plant where the temperature is 23 5 C and relative humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g. a drying cabinet). 4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under the following circumstances:

The module is not stored in recommended storage condition;

Violation of the third requirement above occurs;

Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;

Before module repairing. 5. If needed, the pre-baking should follow the requirements below:

The module should be baked for 8 hours at 120 5 C;

All modules must be soldered to PCB within 24 hours after the baking, otherwise they should be put in a dry environment such as in a drying oven. 14 This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to, or are not sure to conform to IPC/JEDEC J-STD-033. And do not remove the packages of tremendous modules if they are not ready for soldering. RG520F&RG520N_Series_Hardware_Design 101 / 116 5G Module Series NOTE 1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to the air is forbidden. 2. Take out the module from the package and put it on high-temperature-resistant fixtures before baking. All modules must be soldered to PCB within 24 hours after the baking, otherwise put them in the drying oven. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure. 3. Pay attention to ESD protection, such as wearing anti-static gloves, when touching the modules. 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. Apply proper force on the squeegee to produce a clean stencil surface on a single pass. To guarantee module soldering quality, the thickness of stencil for the module is recommended to be 0.150.18 mm. For more details, please refer to document [9]. The peak reflow temperature should be 235246 C, with 246 C as the absolute maximum reflow temperature. To avoid damage to the module caused by repeated heating, it is strongly recommended that the module should be mounted only after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. T em p. (C ) 246 235 217 200 150 100 S oak Z one A M ax slope: 1~3 C /s R eflow Z one M ax slope:

2~3 C /s C C ooling dow n slope:

-1.5 ~ -3 C /s B D Figure 53: Recommended Reflow Soldering Thermal Profile RG520F&RG520N_Series_Hardware_Design 102 / 116 5G Module Series Table 55: Recommended Thermal Profile Parameters Factor Soak Zone Max slope Recommendation 1 to 3 C/s Soak time (between A and B: 150 C and 200 C) 70 to 120 s Reflow Zone Max slope Reflow time (D: over 217C) Max temperature Cooling down slope Reflow Cycle Max reflow cycle NOTE 2 to 3 C/s 40 to 70 s 235 to 246 C

-1.5 to -3 C/s 1 1. If a conformal coating is necessary for the module, do NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module. 2. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the module. 3. Due to the complexity of the SMT process, please contact Quectel Technical Supports in advance for any situation that you are not sure about, or any process (e.g. selective soldering, ultrasonic soldering) that is not mentioned in document [9]. 8.3. Packaging Specifications The module adopts carrier tape packaging and details are as follow:

8.3.1. Carrier Tape Dimension details are as follow:

RG520F&RG520N_Series_Hardware_Design 103 / 116 5G Module Series Figure 54: Carrier Tape Dimension Drawing Table 56: Carrier Tape Dimension Table (Unit: mm) W 72 P 56 T 0.4 A0 B0 44.7 41.7 K0 4.2 K1 5.2 F E 34.2 1.75 8.3.2. Plastic Reel Figure 55: Plastic Reel Dimension Drawing Table 57: Plastic Reel Dimension Table (Unit: mm) D1 380 D2 180 W 72.5 RG520F&RG520N_Series_Hardware_Design 104 / 116 5G Module Series 8.3.3. Packaging Process Place the packaged plastic reel, humidity indicator card and desiccant bag into a vacuum bag, then vacuumize it. Place the module into the carrier tape and use the cover tape to cover them; then wind the heat-sealed carrier tape to the plastic reel and use the protective tape for protection. One plastic reel can load 200 modules. Place the vacuum-packed plastic reel into a pizza box. Put 4 pizza boxes into 1 carton and seal it. One carton can pack 800 modules. Figure 56: Packaging Process RG520F&RG520N_Series_Hardware_Design 105 / 116 5G Module Series 9 Appendix A References Table 58: Related Documents Document Name

[1] Quectel_RG520N-EU_CA&EN-DC_Features

[2] Quectel_RG520N-NA_CA&EN-DC_Features

[3] Quectel_RG520F-EU_CA&EN-DC_Features

[4] Quectel_RG520F-NA_CA&EN-DC_Features

[5] Quectel_5G_EVB_User_Guide

[6] Quectel_RG520N&RG5x0F&RM5x0N&RM5x0F_Series_AT_Commands_Manual

[7] Quectel_RG520N&RG5x0F&RM5x0N&RM5x0F_Series_GNSS_Application_Note

[8] Quectel_RF_Layout_Application_Note

[9] Quectel_Module_Secondary_SMT_Application_Note

[10] Quectel_RG520F&RG520N_Series_Reference_Design Table 59: Terms and Abbreviations Abbreviation Description 1PPS ADC 1 Pulse Per Second Analog-to-Digital Converter AMR-WB Adaptive Multi-Rate Wideband AON AP bps Active Optical Network Application Processor Bits Per Second RG520F&RG520N_Series_Hardware_Design 106 / 116 5G Module Series BPSK CA CTS DAI DCE Binary Phase Shift Keying Carrier Aggregation Clear To Send Digital Audio Interface Data Communications Equipment DC-HSDPA Dual-carrier High Speed Downlink Packet Access DDR DFOTA DL DRX DRX DTE DTR ESD FDD FEM Double Data Rate Delta Firmware Upgrade Over The Air Downlink Discontinuous Reception Diversity Receive Data Terminal Equipment Data Terminal Ready Electrostatic Discharge Frequency Division Duplex Front-End Module GLONASS Global Navigation Satellite System (Russia) GNSS GPS GRFC HB HPUE HSDPA HSPA HSUPA Global Navigation Satellite System Global Positioning System General RF Control High Band High Power User Equipment High Speed Downlink Packet Access High Speed Packet Access High Speed Uplink Packet Access RG520F&RG520N_Series_Hardware_Design 107 / 116 5G Module Series IC I2C I2S I/O LAA LB LED LGA LMHB LNA LTE MAC MB MHB Integrated Circuit Inter-Integrated Circuit Inter-IC Sound Input/Output License Assisted Access Low Band Light Emitting Diode Land Grid Array Low/Middle/High Band Low Noise Amplifier Long Term Evolution Media Access Control Middle Band Middle/High Band MIMO Multiple Input Multiple Output MO MT NR NSA PA PAP PC PCB PCIe PCM Mobile Originated Mobile Terminated New Radio Non-Stand Alone Power Amplifier Password Authentication Protocol Personal Computer Printed Circuit Board Peripheral Component Interconnect Express Pulse Code Modulation RG520F&RG520N_Series_Hardware_Design 108 / 116 5G Module Series PDA PDU PHY PRX QAM QPSK QZSS RF RGMII RHCP Rx SA SCS SD SIB SIMO SMD SMS SoC SPI STB TDD TRX Tx Personal Digital Assistant Protocol Data Unit Physical Layer Primary Receive Quadrature Amplitude Modulation Quadrature Phase Shift Keying Quasi-Zenith Satellite System Radio Frequency Reduced Gigabit Media Independent Interface Right Hand Circularly Polarized Receive Stand Alone Sub-Carrier Space Secure Digital System Information Block Single Input Multiple Output Surface Mount Device Short Message Service System on a Chip Serial Peripheral Interface Set Top Box Time Division Duplexing Transmit & Receive Transmit UART Universal Asynchronous Receiver/Transmitter RG520F&RG520N_Series_Hardware_Design 109 / 116 5G Module Series UHB UL UMTS URC USB

(U)SIM VBAT VIHmax VIHmin VILmax VILmin Vmax Vmin Vnom VOHmax VOHmin VOLmax VSWR Ultra High Band Uplink Universal Mobile Telecommunications System Unsolicited Result Code Universal Serial Bus Universal Subscriber Identity Module Voltage at Battery (Pin) Maximum High-level Input Voltage Minimum High-level Input Voltage Maximum Low-level Input Voltage Minimum Low-level Input Voltage Maximum Voltage Minimum Voltage Nominal Voltage Maximum High-level Output Voltage Minimum High-level Output Voltage Maximum Low-level Output Voltage Voltage Standing Wave Ratio WCDMA Wideband Code Division Multiple Access WLAN WWAN Wireless Local Area Network Wireless Wide Area Network RG520F&RG520N_Series_Hardware_Design 110 / 116 5G Module Series 10 Appendix B Operating Frequency Table 60: Operating Frequencies (5G) 5G n1 n2 n3 n5 n7 n8 n12 n13 n14 n18 n20 n24 n25 n26 n28 n29 n30 n34 n38 Duplex Mode Uplink Operating Band Downlink Operating Band Unit FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD SDL FDD TDD TDD 19201980 18501910 17101785 824849 21102170 19301990 18051880 869894 25002570 26202690 880915 699716 777787 788798 815830 832862 925960 729746 746756 758768 860875 791821 1626.51660.5 15251559 18501915 19301995 814849 703748

23052315 20102025 25702620 859894 758803 717728 23502360 20102025 25702620 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz RG520F&RG520N_Series_Hardware_Design 111 / 116 5G Module Series Duplex Mode Uplink Operating Band Downlink Operating Band Unit TDD TDD TDD TDD TDD TDD TDD TDD TDD FDD FDD SDL FDD FDD FDD SDL SDL TDD TDD TDD 18801920 23002400 24962690 51505925 58555925 35503700 14321517 14271432 18801920 23002400 24962690 51505925 58555925 35503700 14321517 14271432 2483.52495 2483.52495 19202010 17101780

21102200 21102200 738758 16951710 19952020 663698 14271470

33004200 33003800 44005000 SUL 17101785 SUL 880915 SUL 832862 SUL SUL 703748 19201980 617652 14751518 14321517 14271432 33004200 33003800 44005000

MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 5G n39 n40 n41 n46 n47 n48 n50 n51 n53 n65 n66 n67 n70 n71 n74 n75 n76 n77 n78 n79 n80 n81 n82 n83 n84 RG520F&RG520N_Series_Hardware_Design 112 / 116 5G Module Series Duplex Mode Uplink Operating Band Downlink Operating Band Unit 5G n85 n86 n89 n90 n91 n92 n93 n94 n95 n96 n97 n98 n99 n257 n258 n260 n261 FDD 698716 728746 SUL SUL TDD FDD FDD FDD FDD SUL TDD SUL SUL SUL

17101780 824849 24962690 832862 832862 880915 880915 20102025 59257125 23002400 18801920 1626.51660.5

24962690 14271432 14321517 14271432 14321517

59257125

26.5029.50 26.5029.50 24.2527.50 24.2527.50 37.0040.00 37.0040.00 27.5028.35 27.5028.35 Table 61: Operating Frequencies (2G + 3G + 4G) 2G

3G B1 4G Duplex Mode Uplink Downlink B1 FDD 19201980 21102170 PCS1900 B2/BC1 B2 FDD 18501910 19301990 DCS1800 B3 B3 FDD 17101785 18051880

B4 B4 FDD 17101755 21102155 GSM850 B5/BC0 B5 FDD 824849 869894 RG520F&RG520N_Series_Hardware_Design 113 / 116 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz GHz GHz GHz GHz Unit MHz MHz MHz MHz MHz 5G Module Series

B6 B7

FDD 830840 875885 B7 FDD 25002570 26202690 EGSM900 B8 B8 FDD 880915 925960 MHz MHz MHz

B9 B10 B11 B12 B13 B14

B19 B20 B21 B22

B25 B26

B9 FDD 1749.91784.9 1844.91879.9 MHz B10 FDD 17101770 21102170 MHz B11 FDD 1427.91447.9 1475.91495.9 MHz B12 FDD 699716 729746 B13 FDD 777787 746756 B14 FDD 788798 758768 B17 FDD 704716 734746 B18 FDD 815830 860875 B19 FDD 830845 875890 B20 FDD 832862 791821 MHz MHz MHz MHz MHz MHz MHz B21 FDD 1447.91462.9 1495.91510.9 MHz B22 FDD 34103490 35103590 B24 FDD 1626.51660.5 15251559 B25 FDD 18501915 19301995 B26 FDD 814849 859894 B27 FDD 807824 852869 B28 FDD 703748 758803 B29 FDD 15

717728 B30 FDD 23052315 23502360 MHz MHz MHz MHz MHz MHz MHz MHz B31 FDD 452.5457.5 462.5467.5 MHz B32 FDD 15

14521496 MHz MHz B33 B33 TDD 19001920 19001920 15 Restricted to E-UTRA operation when carrier aggregation is configured. The downlink operating band is paired with the uplink operating band (external) of the carrier aggregation configuration that is supporting the configured Pcell. RG520F&RG520N_Series_Hardware_Design 114 / 116 5G Module Series B34 B35 B36 B37 B38 B39 B40

B34 TDD 20102025 20102025 B35 TDD 18501910 18501910 B36 TDD 19301990 19301990 B37 TDD 19101930 19101930 B38 TDD 25702620 25702620 B39 TDD 18801920 18801920 B40 TDD 23002400 23002400 B41 TDD 24962690 24962690 B42 TDD 34003600 34003600 B43 TDD 36003800 36003800 B44 TDD 703803 703803 B45 TDD 14471467 14471467 B46 TDD 51505925 51505925 B47 TDD 58555925 58555925 B48 TDD 35503700 35503700 B50 TDD 14321517 14321517 B51 TDD 14271432 14271432 B52 TDD 33003400 33003400 B65 FDD 19202010 21102200 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz B66 FDD 17101780 21102200 16 MHz B67 FDD 15

738758 B68 FDD 698728 753783 B69 FDD 15

25702620 B70 FDD 17 16951710 19952020 MHz MHz MHz MHz

16 The range 21802200 MHz of the DL operating band is restricted to E-UTRA operation when carrier aggregation is configured. 17 The range 20102020 MHz of the DL operating band is restricted to E-UTRA operation when carrier aggregation is configured and TX-RX separation is 300 MHz. The range 20052020 MHz of the DL operating band is restricted to E-UTRA operation when carrier aggregation is configured and TX-RX separation is 295 MHz. RG520F&RG520N_Series_Hardware_Design 115 / 116 5G Module Series

B71 FDD 663698 617652 B72 FDD 451456 461466 B73 FDD 450455 460465 B74 FDD 14271470 14751518 B75 FDD 15 B76 FDD 15

14321517 14271432 B85 FDD 698716 728746 B87 FDD 410415 420425 B88 FDD 412417 422427 MHz MHz MHz MHz MHz MHz MHz MHz MHz RG520F&RG520N_Series_Hardware_Design 116 / 116 OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.31 (h) and (k): The host manufacturer is responsible for additional testing to verify compliance as a composite system. When testing the host device for compliance with Part 15 Subpart B, the host manufacturer is required to show compliance with Part 15 Subpart B while the transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation should confirm that the module's intentional emissions are compliant (i.e. fundamental and out of band emissions). The host manufacturer must verify that there are no additional unintentional emissions other than what is permitted in Part 15 Subpart B or emissions are complaint with the transmitter(s) rule(s). The Grantee will provide guidance to the host manufacturer for Part 15 B requirements if needed. Important Note notice that any deviation(s) from the defined parameters of the antenna trace, as described by the instructions, require that the host product manufacturer must notify to Quectel that they wish to change the antenna trace design. In this case, a Class II permissive change application is required to be filed by the USI, or the host manufacturer can take responsibility through the change in FCC ID (new application) procedure followed by a Class II permissive change application End Product Labeling When the module is installed in the host device, the FCC/IC ID label must be visible through a window on the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a second label must be placed on the outside of the final device that contains the following text: Contains FCC ID: XMR2022RG520NNA Contains IC: 10224A-2022RG520NA. The FCC ID/IC ID can be used only when all FCC/IC compliance requirements are met. Antenna

(1) The antenna must be installed such that 20 cm is maintained between the antenna and users,

(2) The transmitter module may not be co-located with any other transmitter or antenna. In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC/IC authorization. To comply with FCC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:

- Reorient or relocate the receiving antenna.

- Increase the separation between the equipment and receiver

- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

- Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. List of applicable FCC rules This module has been tested and found to comply with part 22, part 24, part 27, part 90, part 96 requirements for Modular Approval. The modular transmitter is only FCC authorized for the specific rule parts (i.e., FCC transmitter rules) listed on the grant, and that the host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. If the grantee markets their product as being Part 15 Subpart B compliant (when it also contains unintentional-

radiator digital circuity), then the grantee shall provide a notice stating that the final host product still requires Part 15 Subpart B compliance testing with the modular transmitter installed. This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 30 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. Radiation Exposure Statement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 30 cm between the radiator &

your body. Industry Canada Statement This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions:

(1) This device may not cause interference; and

(2) This device must accept any interference, including interference that may cause undesired operation of the device. Le prsent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorise aux deux conditions suivantes:

(1) l'appareil ne doit pas produire de brouillage, et

(2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement."

Radiation Exposure Statement This equipment complies with IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator & your body Dclaration d'exposition aux radiations:

Cet quipement est conforme aux limites d'exposition aux rayonnements ISED tablies pour un environnement non contrl. Cet quipement doit tre install et utilis avec un minimum de 20 cm de distance entre la source de rayonnement et votre corps. This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. Cet appareil est conu uniquement pour les intgrateurs OEM dans les conditions suivantes: (Pour utilisation de dispositif module) 1) L'antenne doit tre installe de telle sorte qu'une distance de 20 cm est respecte entre l'antenne et les utilisateurs, et 2) Le module metteur peut ne pas tre complant avec un autre metteur ou antenne. Tant que les 2 conditions ci-dessus sont remplies, des essais supplmentaires sur l'metteur ne seront pas ncessaires. Toutefois, l'intgrateur OEM est toujours responsable des essais sur son produit final pour toutes exigences de conformit supplmentaires requis pour ce module install. IMPORTANT NOTE:

In the event that these conditions cannot be met (for example certain laptop configurations or colocation with another transmitter), then the Canada authorization is no longer considered valid and the IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate Canada authorization. NOTE IMPORTANTE:

Dans le cas o ces conditions ne peuvent tre satisfaites (par exemple pour certaines configurations d'ordinateur portable ou de certaines co-localisation avec un autre metteur), l'autorisation du Canada n'est plus considr comme valide et l'ID IC ne peut pas tre utilis sur le produit final. Dans ces circonstances, l'intgrateur OEM sera charg de rvaluer le produit final (y compris l'metteur) et l'obtention d'une autorisation distincte au Canada. End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed such that 20 cm may be maintained between the antenna and users. The final end product must be labeled in a visible area with the following: Contains IC: 10224A-2022RG520NA. Plaque signaltique du produit final Ce module metteur est autoris uniquement pour une utilisation dans un dispositif o l'antenne peut tre installe de telle sorte qu'une distance de 20cm peut tre maintenue entre l'antenne et les utilisateurs. Le produit final doit tre tiquet dans un endroit visible avec l'inscription suivante: "Contient des IC: 10224A-2022RG520NA". Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. Manuel d'information l'utilisateur final L'intgrateur OEM doit tre conscient de ne pas fournir des informations l'utilisateur final quant la faon d'installer ou de supprimer ce module RF dans le manuel de l'utilisateur du produit final qui intgre ce module. Le manuel de l'utilisateur final doit inclure toutes les informations rglementaires requises et avertissements comme indiqu dans ce manuel.

 

 

RG520F&RG520N Series Hardware Design 5G Module Series Version: 1.0.1 Date: 2022-01-21 Status: Preliminary 5G Module Series At Quectel, our aim is to provide timely and comprehensive services to our customers. If you require any assistance, please contact our headquarters:

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local offices. For more information, please visit:

http://www.quectel.com/support/sales.htm. For technical support, or to report documentation errors, please visit:

http://www.quectel.com/support/technical.htm. Or email us at: support@quectel.com. Legal Notices We offer information as a service to you. The provided information is based on your requirements and we make every effort to ensure its quality. You agree that you are responsible for using independent analysis and evaluation in designing intended products, and we provide reference designs for illustrative purposes only. Before using any hardware, software or service guided by this document, please read this notice carefully. Even though we employ commercially reasonable efforts to provide the best possible experience, you hereby acknowledge and agree that this document and related services hereunder are provided to you on an as available basis. We may revise or restate this document from time to time at our sole discretion without any prior notice to you. Use and Disclosure Restrictions License Agreements Documents and information provided by us shall be kept confidential, unless specific permission is granted. They shall not be accessed or used for any purpose except as expressly provided herein. Copyright Our and third-party products hereunder may contain copyrighted material. Such copyrighted material shall not be copied, reproduced, distributed, merged, published, translated, or modified without prior written consent. We and the third party have exclusive rights over copyrighted material. No license shall be granted or conveyed under any patents, copyrights, trademarks, or service mark rights. To avoid ambiguities, purchasing in any form cannot be deemed as granting a license other than the normal non-exclusive, royalty-free license to use the material. We reserve the right to take legal action for noncompliance with abovementioned requirements, unauthorized use, or other illegal or malicious use of the material. RG520F&RG520N_Series_Hardware_Design 1 / 116 5G Module Series Trademarks Except as otherwise set forth herein, nothing in this document shall be construed as conferring any rights to use any trademark, trade name or name, abbreviation, or counterfeit product thereof owned by Quectel or any third party in advertising, publicity, or other aspects. Third-Party Rights This document may refer to hardware, software and/or documentation owned by one or more third parties

(third-party materials). Use of such third-party materials shall be governed by all restrictions and obligations applicable thereto. We make no warranty or representation, either express or implied, regarding the third-party materials, including but not limited to any implied or statutory, warranties of merchantability or fitness for a particular purpose, quiet enjoyment, system integration, information accuracy, and non-infringement of any third-party intellectual property rights with regard to the licensed technology or use thereof. Nothing herein constitutes a representation or warranty by us to either develop, enhance, modify, distribute, market, sell, offer for sale, or otherwise maintain production of any our products or any other hardware, software, device, tool, information, or product. We moreover disclaim any and all warranties arising from the course of dealing or usage of trade. Privacy Policy To implement module functionality, certain device data are uploaded to Quectels or third-partys servers, including carriers, chipset suppliers or customer-designated servers. Quectel, strictly abiding by the relevant laws and regulations, shall retain, use, disclose or otherwise process relevant data for the purpose of performing the service only or as permitted by applicable laws. Before data interaction with third parties, please be informed of their privacy and data security policy. Disclaimer a) We acknowledge no liability for any injury or damage arising from the reliance upon the information. b) We shall bear no liability resulting from any inaccuracies or omissions, or from the use of the information contained herein. c) While we have made every effort to ensure that the functions and features under development are free from errors, it is possible that they could contain errors, inaccuracies, and omissions. Unless otherwise provided by valid agreement, we make no warranties of any kind, either implied or express, and exclude all liability for any loss or damage suffered in connection with the use of features and functions under development, to the maximum extent permitted by law, regardless of whether such loss or damage may have been foreseeable. d) We are not responsible for the accessibility, safety, accuracy, availability, legality, or completeness of information, advertising, commercial offers, products, services, and materials on third-party websites and third-party resources. Copyright Quectel Wireless Solutions Co., Ltd. 2022. All rights reserved. RG520F&RG520N_Series_Hardware_Design 2 / 116 5G Module Series Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be paid to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions, such as when the mobile bill is unpaid or the (U)SIM card is invalid. When emergency help is needed in such conditions, use emergency call if the device supports it. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. In an emergency, the device with emergency call function cannot be used as the only contact method considering network connection cannot be guaranteed under all circumstances. The cellular terminal or mobile contains a transceiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV sets, radios, computers or other electric equipment. In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or metal powders. RG520F&RG520N_Series_Hardware_Design 3 / 116 5G Module Series About the Document Revision History Revision Date Author Description

2021-12-22 1.0.0 2021-12-22 Frank PENG/

Six ZHANG Frank PENG/

Six ZHANG Creation of the document Preliminary Preliminary:

1. Updated the dimensions (Table 2). 2. Added n38 HPUE for Class 2 transmitting power;

Changed the Max. transmission data rates of NSA and SA TDD in 5G NR features (Table 4). 3. Updated the functional diagram (Figure 2). 4. Added the note about optional ANT4 and ANT5 for 1.0.1 2022-01-21 Frank PENG/

Six ZHANG pin assignment (Chapter 2.4). 5. Changed pin 135 from RESERVED to HST_LAA_TX_EN (Figure 2 & Table 6). 6. Simplified DC characteristics and added Digital I/O Characteristic chapter (Table 6 & Chapter 6.4). 7. Updated Power-up, Power-down and Reset Timing

(Figure 13 & 14 & 17). 8. Updated the pull-up resistor value of USB_BOOT interface from 4.7 k to 10 k (Figure 19). 9. Added UART interfaces description (Chapter 4.7). RG520F&RG520N_Series_Hardware_Design 4 / 116 5G Module Series Contents Safety Information ...................................................................................................................................... 3 About the Document .................................................................................................................................. 4 Contents ...................................................................................................................................................... 5 Table Index .................................................................................................................................................. 8 Figure Index .............................................................................................................................................. 10 1 Introduction ....................................................................................................................................... 12 Special Marks ....................................................................................................................... 12 1.1. 2 Product Overview ............................................................................................................................. 13 Frequency Bands and Functions ......................................................................................... 14 Key Features ........................................................................................................................ 14 Functional Diagram .............................................................................................................. 18 Pin Assignment ..................................................................................................................... 19 Pin Description ..................................................................................................................... 20 EVB ....................................................................................................................................... 31 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 3.3. 3.1. 3.2. 3 Operating Characteristics ................................................................................................................ 32 Operating Modes .................................................................................................................. 32 Sleep Mode .......................................................................................................................... 33 3.2.1. UART Application Scenario ........................................................................................... 33 3.2.2. USB Application Scenario ............................................................................................. 34 3.2.2.1. USB Application with USB Remote Wakeup Function ................................... 34 3.2.2.2. USB Application with USB Suspend/Resume and MAIN_RI Function .......... 34 USB Application without USB Suspend Function .......................................... 35 3.2.2.3. Airplane Mode ...................................................................................................................... 36 3.3.1. Hardware ....................................................................................................................... 36 3.3.2. Software ........................................................................................................................ 36 Power Supply ....................................................................................................................... 37 3.4.1. Power Supply Pins ........................................................................................................ 37 3.4.2. Reference Design for Power Supply ............................................................................. 38 3.4.3. Power Supply ................................................................................................................ 38 3.4.4. Voltage Stability Requirements ..................................................................................... 39 Turn On ................................................................................................................................. 41 3.5.1. Turn on the Module with PWRKEY ............................................................................... 41 Turn Off ................................................................................................................................. 43 3.6.1. Turn off the Module with PWRKEY ............................................................................... 43 3.6.2. Turn off the Module with AT Command ......................................................................... 43 Reset .................................................................................................................................... 44 3.7. 3.4. 3.5. 3.6. 4 Application Interfaces ...................................................................................................................... 46 USB Interface ....................................................................................................................... 46 USB_BOOT Interface ........................................................................................................... 48 4.1. 4.2. RG520F&RG520N_Series_Hardware_Design 5 / 116 5G Module Series 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. 4.9. 4.10. 4.11. 4.12.

(U)SIM Interfaces ................................................................................................................. 49 I2C Interface* ........................................................................................................................ 51 I2S Interface* ........................................................................................................................ 52 PCM Interface* ..................................................................................................................... 53 UART Interfaces ................................................................................................................... 55 SDIO Interface ...................................................................................................................... 58 ADC Interface ....................................................................................................................... 60 SPI Interface ......................................................................................................................... 61 PCIe Interface ....................................................................................................................... 62 Control Signal ....................................................................................................................... 65 W_DISABLE# ........................................................................................................ 65 Indication Signal ................................................................................................................... 66 Network Status Indication ...................................................................................... 66 STATUS ................................................................................................................. 67 4.14. IPQ Status and Err Fatal Interface* ...................................................................................... 68 4.15. MAIN_RI* .............................................................................................................................. 69 Time Service and Repeater Interface* ................................................................................. 70 4.16. 4.17. GRFC Interfaces* ................................................................................................................. 70 4.13.1. 4.13.2. 4.12.1. 4.13. 5.1. 5.2. 5 RF Specifications .............................................................................................................................. 72 Cellular Network ................................................................................................................... 72 5.1.1. Antenna Interface & Frequency Bands ......................................................................... 72 5.1.2. Tx Power ....................................................................................................................... 76 5.1.3. Rx Sensitivity ................................................................................................................. 76 5.1.4. Reference Design ......................................................................................................... 80 GNSS .................................................................................................................................... 81 5.2.1. Antenna Interface & Frequency Bands ......................................................................... 81 5.2.2. GNSS Performance ...................................................................................................... 82 5.2.3. Reference Design ......................................................................................................... 83 Reference Design of RF Routing ......................................................................................... 83 Antenna Requirements ......................................................................................................... 86 RF Connector Recommendation .......................................................................................... 87 5.5.1. Recommended RF Connector for Installation .............................................................. 88 Assemble Coaxial Cable Plug Manually ........................................................ 88 Assemble Coaxial Cable Plug with Fixture .................................................... 89 5.5.2. Recommended Manufacturers of RF Connector and Cable ........................................ 90 5.5.1.1. 5.5.1.2. 5.3. 5.4. 5.5. 6 Electrical Characteristics & Reliability ........................................................................................... 91 Absolute Maximum Ratings.................................................................................................. 91 Power Supply Ratings .......................................................................................................... 92 Power Consumption ............................................................................................................. 92 Digital I/O Characteristic ....................................................................................................... 93 ESD Protection ..................................................................................................................... 94 Operating and Storage Temperatures .................................................................................. 95 Thermal Consideration ......................................................................................................... 95 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. RG520F&RG520N_Series_Hardware_Design 6 / 116 5G Module Series 7 Mechanical Information .................................................................................................................... 97 Mechanical Dimensions ....................................................................................................... 97 Recommended Footprint ...................................................................................................... 99 Top and Bottom Views ........................................................................................................ 100 7.1. 7.2. 7.3. 8.1. 8.2. 8.3. 8 Storage, Manufacturing & Packaging ........................................................................................... 101 Storage Conditions ............................................................................................................. 101 Manufacturing and Soldering ............................................................................................. 102 Packaging Specifications ................................................................................................... 103 8.3.1. Carrier Tape ................................................................................................................. 103 8.3.2. Plastic Reel ................................................................................................................. 104 8.3.3. Packaging Process ..................................................................................................... 105 9 Appendix A References .................................................................................................................. 106 10 Appendix B Operating Frequency.................................................................................................. 111 RG520F&RG520N_Series_Hardware_Design 7 / 116 5G Module Series Table Index Table 1: Special Marks ............................................................................................................................... 12 Table 2: Brief Introduction of the Module ................................................................................................... 13 Table 3: Wireless Network Type ................................................................................................................. 14 Table 4: Key Features ................................................................................................................................ 14 Table 5: I/O Parameters Definition ............................................................................................................. 20 Table 6: Pin Description ............................................................................................................................. 20 Table 7: Overview of Operating Modes ...................................................................................................... 32 Table 8: Pin Definition of Power Supply ..................................................................................................... 37 Table 9: Pin Definition of PWRKEY ............................................................................................................ 41 Table 10: Pin Definition of RESET ............................................................................................................. 44 Table 11: Functions of the USB Interface ................................................................................................... 46 Table 12: Pin Definition of USB Interface ................................................................................................... 46 Table 13: USB Trace Length in the Module ............................................................................................... 48 Table 14: Pin Definition of (U)SIM Interfaces ............................................................................................. 49 Table 15: Pin Definition of I2C Interface..................................................................................................... 52 Table 16: Pin Definition of I2S Interface ..................................................................................................... 52 Table 17: Pin Definition of PCM Interface .................................................................................................. 53 Table 18: Pin Definition of UART Interfaces ............................................................................................... 56 Table 19: Pin Definition of SD Card Interface ............................................................................................ 58 Table 20: SDC Trace Length in the Module ............................................................................................... 60 Table 21: Pin Definition of ADC Interface ................................................................................................... 61 Table 22: Characteristics of ADC Interface ................................................................................................ 61 Table 23: Pin Definition of SPI Interface .................................................................................................... 61 Table 24: Pin Definition of PCIe Interface .................................................................................................. 62 Table 25: PCIe Trace Length in the Module ............................................................................................... 65 Table 26: Pin Definition of Control Signal .................................................................................................. 65 Table 27: RF Function Status ..................................................................................................................... 66 Table 28: Pin Definition of Indication Signal ............................................................................................... 66 Table 29: Working State of the Network Connection Status/Activity Indication ......................................... 67 Table 30: Pin Definition of IPQ Status and Err Fatal Interface .................................................................. 68 Table 31: Behaviors of the RI ..................................................................................................................... 69 Table 32: Pin Definition of Time Service and Repeater Function .............................................................. 70 Table 33: Pin Definition of GRFC Interfaces .............................................................................................. 71 Table 34: Logic Levels of GRFC Interfaces ............................................................................................... 71 Table 35: Truth Table of GRFC Interfaces .................................................................................................. 71 Table 36: Pin Definition of Cellular Network Interface for RG520F-NA*/RG520N-NA .............................. 72 Table 37: Pin Definition of Cellular Network Interface for RG520F-EU*/RG520N-EU .............................. 73 Table 38: Cellular Network Antenna Mapping for RG520F-NA*/RG520N-NA ........................................... 74 Table 39: Cellular Network Antenna Mapping for RG520F-EU*/RG520N-EU ........................................... 75 Table 40: Tx Power ..................................................................................................................................... 76 Table 41: Conducted RF Receiving Sensitivity of RG520F-NA*/RG520N-NA .......................................... 76 RG520F&RG520N_Series_Hardware_Design 8 / 116 5G Module Series Table 42: Conducted RF Receiving Sensitivity of RG520F-EU*/RG520N-EU .......................................... 78 Table 43: Pin Definition of GNSS Antenna Interface ................................................................................. 81 Table 44: GNSS Frequency ....................................................................................................................... 81 Table 45: GNSS Performance .................................................................................................................... 82 Table 46: Antenna Requirements ............................................................................................................... 86 Table 47: Absolute Maximum Ratings ........................................................................................................ 91 Table 48: Module Power Supply Ratings ................................................................................................... 92 Table 49: Averaged Power Consumption for the Module .......................................................................... 92 Table 50: 1.8 V I/O Requirements .............................................................................................................. 93 Table 51: (U)SIM 1.8 V I/O Requirements ................................................................................................. 94 Table 52: (U)SIM 2.95 V I/O Requirements ............................................................................................... 94 Table 53: Electrostatics Discharge Characteristics (25 C, 45 % Relative Humidity) ............................... 94 Table 54: Operating and Storage Temperatures ........................................................................................ 95 Table 55: Recommended Thermal Profile Parameters ............................................................................ 103 Table 56: Carrier Tape Dimension Table (Unit: mm) ................................................................................ 104 Table 57: Plastic Reel Dimension Table (Unit: mm) ................................................................................. 104 Table 58: Related Documents .................................................................................................................. 106 Table 59: Terms and Abbreviations .......................................................................................................... 106 Table 60: Operating Frequencies (5G) ...................................................................................................... 111 Table 61: Operating Frequencies (2G + 3G + 4G)................................................................................... 113 RG520F&RG520N_Series_Hardware_Design 9 / 116 5G Module Series Figure Index Figure 1: Functional Diagram ..................................................................................................................... 18 Figure 2: Pin Assignment (Top View) ......................................................................................................... 19 Figure 3: DRX Run Time and Current Consumption in Sleep Mode ......................................................... 33 Figure 4: Sleep Mode Application via UART .............................................................................................. 33 Figure 5: Sleep Mode Application with USB Remote Wakeup .................................................................. 34 Figure 6: Sleep Mode Application with RI .................................................................................................. 35 Figure 7: Sleep Mode Application without Suspend Function ................................................................... 36 Figure 8: Reference Design of Power Supply ............................................................................................ 38 Figure 9: Power Supply Limits during Burst Transmission ........................................................................ 39 Figure 10: Star Structure of the Power Supply .......................................................................................... 40 Figure 11: Reference Circuit of Turning on the Module with Driving Circuit .............................................. 41 Figure 12: Reference Circuit of Turning on the Module with a Button ....................................................... 42 Figure 13: Power-up Timing ....................................................................................................................... 42 Figure 14: Power-down Timing .................................................................................................................. 43 Figure 15: Reference Circuit of RESET_N with Driving Circuit ................................................................. 44 Figure 16: Reference Circuit of RESET_N with Button ............................................................................. 45 Figure 17: Reset Timing ............................................................................................................................. 45 Figure 18: Reference Circuit of USB Application ....................................................................................... 47 Figure 19: Reference Circuit of USB_BOOT Interface .............................................................................. 49 Figure 20: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector ......................... 50 Figure 21: Reference Circuit of a 6-Pin (U)SIM Card Connector .............................................................. 51 Figure 22: Reference Circuit of I2S Application with Audio Codec ............................................................ 53 Figure 23: Primary Mode Timing ................................................................................................................ 54 Figure 24: Auxiliary Mode Timing ............................................................................................................... 54 Figure 25: Reference Circuit of PCM Interface .......................................................................................... 55 Figure 26: UART Interface Connection ...................................................................................................... 57 Figure 27: Reference Circuit with Translator Chip ..................................................................................... 57 Figure 28: Reference Circuit with Transistor Circuit .................................................................................. 58 Figure 29: Reference Circuit of SD Card Interface .................................................................................... 59 Figure 30: Reference Circuit of SPI Interface with a Level Translator....................................................... 62 Figure 31: PCIe Interface Connection ........................................................................................................ 64 Figure 32: Reference Circuit of the Network Status Indication .................................................................. 67 Figure 33: Reference Circuits of STATUS ................................................................................................. 68 Figure 34: Module with IPQ GPIO Application ........................................................................................... 69 Figure 35: Reference Circuit for RF Antenna Interfaces ............................................................................ 80 Figure 36: Reference Circuit of GNSS Antenna ........................................................................................ 83 Figure 37: Microstrip Design on a 2-layer PCB ......................................................................................... 84 Figure 38: Coplanar Waveguide Design on a 2-layer PCB ....................................................................... 84 Figure 39: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 84 Figure 40: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 85 Figure 41: Dimensions of the Receptacles (Unit: mm) .............................................................................. 87 RG520F&RG520N_Series_Hardware_Design 10 / 116 5G Module Series Figure 42: Specifications of Mating Plugs Using 0.81 mm Coaxial Cables (Unit: mm) .......................... 88 Figure 43: Plug in a Coaxial Cable Plug .................................................................................................... 89 Figure 44: Pull out a Coaxial Cable Plug ................................................................................................... 89 Figure 45: Install the Coaxial Cable Plug with Fixture ............................................................................... 90 Figure 46: Heatsink Placement .................................................................................................................. 96 Figure 47: Heatsink Fixing ......................................................................................................................... 96 Figure 48: Module Top and Side Dimensions (Unit: mm) .......................................................................... 97 Figure 49: Module Bottom Dimensions (Bottom View, Unit: mm) ............................................................. 98 Figure 50: Recommended Footprint .......................................................................................................... 99 Figure 51: Top & Bottom Views of RG520N Series ................................................................................. 100 Figure 52: Top & Bottom Views of RG520F Series .................................................................................. 100 Figure 53: Recommended Reflow Soldering Thermal Profile ................................................................. 102 Figure 54: Carrier Tape Dimension Drawing ............................................................................................ 104 Figure 55: Plastic Reel Dimension Drawing ............................................................................................ 104 Figure 56: Packaging Process ................................................................................................................. 105 RG520F&RG520N_Series_Hardware_Design 11 / 116 5G Module Series 1 Introduction This document defines RG520F and RG520N series modules and describes their air interfaces and hardware interfaces which relate to customers applications. It can help customers quickly understand interface specifications, electrical and mechanical details, as well as other related information of the module. Associated with application notes and user guides, customers can use this module to design and to set up mobile applications easily. 1.1. Special Marks Table 1: Special Marks Mark Definition

Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin, AT command, or argument is under development and currently not supported; and the asterisk (*) after a model indicates that the sample of such model is currently unavailable. Brackets ([]) used after a pin enclosing a range of numbers indicate all pins of the same type. For example, SDIO_DATA[0:3] refers to all four SDIO pins: SDIO_DATA0, SDIO_DATA1, SDIO_DATA2, and SDIO_DATA3. RG520F&RG520N_Series_Hardware_Design 12 / 116 5G Module Series 2 Product Overview RG520F and RG520N series are 5G NR/LTE-FDD/LTE-TDD/WCDMA 1 wireless communication modules, which provides data connectivity on 5G NR SA and NSA, LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA, and WCDMA networks. It also provides GNSS to meet your specific application demands. RG520F and RG520N series are industrial-grade modules for industrial and commercial applications only. The following tables show the brief introduction and supported frequency bands of the module. For CA and EN-DC configurations, refer to document [1], [2], [3] and [4]. Table 2: Brief Introduction of the Module Categories Packaging and pin counts LGA: 392 Dimensions Weight

(44.0 0.2) mm (41.0 0.2) mm (2.75 0.2) mm Approx. 11 g Wireless network functions 5G NR/LTE/WCDMA 1 Variants RG520F-NA*, RG520F-EU*, RG520N-NA, RG520N-EU 1 WCDMA is only supported by RG520F-EU* and RG520N-EU. RG520F&RG520N_Series_Hardware_Design 13 / 116 5G Module Series 2.1. Frequency Bands and Functions Table 3: Wireless Network Type Wireless Network Type 5G NR LTE-FDD RG520F-NA*

RG520N-NA n2/n5/n7/n12/n13/n14/n25/n26/n29/n30/

n38/n41/n48/n66/n70/n71/n77/n78 RG520F-EU*

RG520N-EU n1/n3/n5/n7/n8/n20/n28/n38/n40/n41/

n75/n76/n77/n78 B2/B4/B5/B7/B12/B13/B14/B17/B25/B26/

B29/B30/B66/B71 B1/B3/B5/B7/B8/B20/B28/B32 LTE-TDD B38/B41/B42/B43/B46 (LAA) /B48 B38/B40/B41/B42/B43 WCDMA

B1/B5/B8 GNSS GPS/GLONASS/BDS/Galileo/QZSS GPS/GLONASS/BDS/Galileo/QZSS 2.2. Key Features Table 4: Key Features Features Details Power Supply SMS Supply voltage: 3.34.4 V Typical supply voltage: 3.8 V Text and PDU mode Point-to-point MO and MT SMS cell broadcast SMS storage: ME by default

(U)SIM Interfaces Supports USIM/SIM card: 1.8 V, 2.95 V Audio Features*

PCM Interface*

SPI Interface Supports two digital audio interfaces: PCM and I2S WCDMA: AMR/AMR-WB LTE: AMR/AMR-WB Supports echo cancellation and noise suppression Supports 16-bit linear data format Supports long frame synchronization and short frame synchronization Supports master and slave modes, but must be in master mode for long frame synchronization Provides a duplex, synchronous and serial communication link with the peripheral devices RG520F&RG520N_Series_Hardware_Design 14 / 116 5G Module Series One SPI interface, only supports master mode 1.8 V operation voltage with clock rates up to 50 MHz One I2C interface Comply with I2C Specification, Version 3.0 Multi-master mode is not supported Supports 16-bit linear data format I2S is a common 4-wire DAI (MCLK is not used in the design normally) used in Hi-Fi, STB and portable devices The Tx and Rx lines are used for audio transmission, whilst the bit clock and left/right clock synchronize the link I2S in either controller or codec state is able to drive (master) the bit clock and left/right clock lines Can be multiplexed into PCM function Compliant with USB 3.1 and 2.0 specifications, with transmission rates up to 10 Gbps on USB 3.1 and 480 Mbps on USB 2.0 Used for AT command communication, data transmission, GNSS NMEA sentence output, software debugging and firmware upgrade USB Serial Driver: supports USB serial driver for Windows 7/8/8.1/10, Linux 2.65.14, Android 4.x11.x systems I2C Interface*

I2S Interface*

USB Interface SDIO Interface Supports SD 3.0 protocol Main UART:

Used for AT command communication Baud rate: 115200 bps by default Debug UART:

Used for Linux console and log output Baud rate: 115200 bps Bluetooth UART*:

Used for Bluetooth communication Baud rate: 115200 bps Supports RTS and CTS hardware flow control COEX UART*:

Used for WWAN/WLAN coexistence mechanism only for Qualcomn platform Complaint with PCIe Gen 3, supports two lanes, 8 Gbps per lane Complaint with PCIe Gen 4, supports one lane, 16 Gbps per lane Supports RC (Root Complex) mode and EP (End Point) mode Can be used to connect an external Wi-Fi IC and used for Wi-Fi communication by default UART Interfaces PCIe Interface eSIM*

A space was reserved for eSIM inside the module Network Indication NET_MODE and NET_STATUS to indicate network connectivity status AT Commands Compliant with 3GPP TS 27.007, 27.005 and Quectel enhanced AT commands RG520F&RG520N_Series_Hardware_Design 15 / 116 5G Module Series Rx-diversity 5G NR/LTE/WCDMA 1 Cellular antenna interfaces:

- RG520F-NA*/RG520N-NA:

4 cellular antenna interfaces

- RG520F-EU*/RG520N-EU:

Antenna Interfaces Transmitting Power 5G NR Features 4 + 2 (optional) cellular antenna interfaces One GNSS antenna interface 50 impedance WCDMA 1: Class 3 (24 dBm + 1/-3 dB) LTE-FDD: Class 3 (23 dBm 2 dB) LTE-TDD: Class 3 (23 dBm 2 dB) LTE B38/B41/B42 HPUE: Class 2 (26 dBm 2 dB) 2 5G NR: Class 3 (23 dBm 2 dB) 5G NR n38/n41/n77/n78 HPUE: Class 2 (26 dBm +2/-3 dB) 2 Supports 3GPP Rel-16 Supports UL 256QAM and DL 256QAM modulations Supports DL 4 4 MIMO 3

- RG520F-NA*/RG520N-NA:

n2/n5/n7/n12/n13/n14/n25/n26/n29/n30/n38/n41/n48/n66/n70/

n71/n77/n78

- RG520F-EU*/RG520N-EU:

n1/n3/n5/n7/n8/n20/n28/n38/n40/n41/n75/n76/n77/n78 Supports UL 2 2 MIMO 4

- RG520F-NA*/RG520N-NA: n38/n41/n77/n78

- RG520F-EU*/RG520N-EU: n38/n41/n77/n78 Supports SCS 15 kHz 5 and 30 kHz 5 Supports SA and NSA operation modes 6 Supports Option 3x, 3a, 3 and Option 2 Max. transmission data rates 7:

NSA TDD:

- RG520N-NA/RG520N-EU:

Max. 3.2 Gbps (DL)/550 Mbps (UL)

- RG520F-NA*/RG520F-EU*:

Max. 4.0 Gbps (DL)/550 Mbps (UL) SA TDD:

- RG520N-NA/RG520N-EU:

Max. 2.4 Gbps (DL)/900 Mbps (UL)

- RG520F-NA*/RG520F-EU*:

2 HPUE only supports single carrier. 3 LB 4 4 MIMO is optional. Even if it is not required, to support LB + LB CA or EN-DC combinations, ANT0ANT3 must support low bands. 4 UL 2 2 MIMO is only supported in 5G SA mode. 5 5G NR FDD bands only support 15 kHz SCS, and NR TDD bands only support 30 kHz SCS. 6 See document [1], [2], [3] and [4] for bandwidth supported by each frequency band in the NSA and SA modes. 7 The maximum rates are theoretical and the actual values refer to the network configuration. RG520F&RG520N_Series_Hardware_Design 16 / 116 5G Module Series Max. 4.0 Gbps (DL)/900 Mbps (UL) Supports FDD and TDD Supports 1.4/3/5/10/15/20 MHz RF bandwidth Supports UL QPSK, 16QAM, 64QAM and 256QAM* modulations Supports DL QPSK, 16QAM, 64QAM and 256QAM modulations Supports DL 4 4 MIMO 3

- RG520F-NA*/RG520N-NA:

B2/B4/B5/B7/B12/B13/B14/B17/B25/B26/B29/B30/B38/B41/B42/

B43/B48/B66/B71

- RG520F-EU*/RG520N-EU:

LTE Features B1/B3/B5/B7/B8/B20/B28/B32/B38/B40/B41/B42/B43 Max. transmission data rates 7:

- RG520N-NA:

LTE: 1.6 Gbps (DL)/200 Mbps (UL)

- RG520F-NA*:

LTE: 2.0 Gbps (DL)/200 Mbps (UL)

- RG520N-EU:

LTE: 1.6 Gbps (DL)/200 Mbps (UL)

- RG520F-EU*:

LTE: 2.0 Gbps (DL)/200 Mbps (UL) Supports 3GPP R9 DC-HSDPA, HSPA+, HSDPA, HSUPA and UMTS Features Internet Protocol Features GNSS Features Temperature Range WCDMA Supports QPSK, 16QAM, 64QAM modulations Max. transmission data rates 7:

- DC-HSDPA: 42 Mbps (DL)

- DC-HSUPA: 5.76 Mbps (UL)

- WCDMA: 384 kbps (DL)/384 kbps (UL) Supports NITZ, PING, QMI protocols Support PAP and CHAP for PPP connections Support Dual-band GNSS: L1 and L5 Supports GPS, GLONASS, BDS, Galileo, QZSS Protocol: NMEA-0183 Data update rate: 1 Hz Operating temperature range 8: -30 to +75 C Extended temperature range 9: -40 to +85 C Storage temperature range: -40 to +90 C Firmware Upgrade Use USB interface or FOTA to upgrade 8 To meet this operating temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module can meet 3GPP specifications. 9 To meet this extended temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module remains the ability to establish and maintain functions such as voice, SMS, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may undergo a reduction in value, exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again. RG520F&RG520N_Series_Hardware_Design 17 / 116 5G Module Series RoHS All hardware components are fully compliant with EU RoHS directive 2.3. Functional Diagram The following figure shows a block diagram of the module and illustrates the major functional parts. Power management Baseband DDR + NAND flash Radio frequency Peripheral interface 0 T N A 1 T N A 2 T N A 3 T N A 4 T N A 5 T N A S S N G _ T N A VBAT_RF QET Tx/Rx Blocks x T x R P x R D S S N G C F R G

P M I I VBAT_BB PWRKEY RESET_N ADC STATUS RFCLK 76.8MHz Transceiver NAND LPDDR4X SDRAM QLINK Control PMIC BBCLK(19.2 MHz) SleepCLK(32.768KHz) PMU 76.8 MHz XO SPMI eSIM Baseband I2S SPI VDD_WIFI_VL VDD_WIFI_VM VDD_WIFI_VH VDD_EXT

(U)SIM2

(U)SIM1 USB 2.0

/3.1 PCM PCIe 3.0/4.0 I2C UART SDIO Figure 1: Functional Diagram RG520F&RG520N_Series_Hardware_Design 18 / 116 5G Module Series NOTE 1. RG520F-NA* and RG520N-NA have 5 antenna interfaces. 2. RG520F-EU* and RG520N-EU have 7 antenna interfaces. ANT4 and ANT5 are used for CA combinations related to 1A-32A or 3A-32A. If there is no need for these CA combinations, ANT4 and ANT5 can be removed. 2.4. Pin Assignment The following figure illustrates the pin assignment of the module. 2 9 3 D N G 5 9 1 D N G 3 9 1 S S N G _ T N A 0 9 1 D N G 7 8 1 D N G 4 8 1 3 T N A 1 8 1 D N G 8 7 1 D N G 5 7 1 5 T N A 2 7 1 D N G 9 6 1 D N G 6 6 1 2 T N A 3 6 1 D N G 0 6 1 D N G 7 5 1 1 T N A 4 5 1 D N G 1 5 1 D N G 8 4 1 D E V R E S E R 5 4 1 D N G 2 4 1 D N G 9 3 1 D E V R E S E R 6 3 1 D N G 3 3 1 D N G 1 9 3 D N G 4 9 1 D N G 1 9 1 D N G 8 8 1 D N G 5 8 1 D N G 2 8 1 D N G 9 7 1 D N G 6 7 1 D N G 3 7 1 D N G 0 7 1 D N G 7 6 1 D N G 4 6 1 D N G 1 6 1 D N G 8 5 1 D N G 5 5 1 D N G 2 5 1 D N G 9 4 1 D N G 6 4 1 D N G 3 4 1 D N G 0 4 1 D N G 7 3 1 D N G 4 3 1 D N G 196 GND 199 RESERVED 202 GND 205 GND 208 RESERVED 211 GND 214 GND 217 RESERVED 220 ETH1_PWR_EN 223 ETH2_PWR_EN 226 GND 229 VBAT_RF1 232 VBAT_RF1 235 VBAT_BB 238 VBAT_BB 241 ADC0 244 USIM1_RST 247 USIM1_CLK 250 USIM2_VDD 253 USIM2_CLK 256 I2S_SCK 259 I2S_WS 262 RESERVED 264 RESERVED 2 9 1 D E V R E S E R 9 8 1 D E V R E S E R 6 8 1 D E V R E S E R 3 8 1 D E V R E S E R 0 8 1 L R T C _ W S _ L W 7 7 1 D E V R E S E R 4 7 1 1 C F R G _ R D S 1 7 1 0 C F R G _ R D S 8 6 1 D N G 5 6 1 D E V R E S E R 2 6 1 I G N T U M _ A P _ N A L W 9 5 1 N E _ S A _ A A L _ L W 6 5 1 D N G 3 5 1 D E V R E S E R 0 5 1 D E V R E S E R 7 4 1 D N G 4 4 1 D N G 1 4 1 D N G 8 3 1 N E _ X T _ L W _ T S H 5 3 1 _ X T _ A A L _ T S H N E 8 9 2 D E V R E S E R 7 9 2 D E V R E S E R 6 9 2 D E V R E S E R 5 9 2 D E V R E S E R 4 9 2 D E V R E S E R 3 9 2 D E V R E S E R 2 9 2 D E V R E S E R 1 9 2 D E V R E S E R 0 9 2 D E V R E S E R 9 8 2 D E V R E S E R 8 8 2 D E V R E S E R 7 8 2 D E V R E S E R 6 8 2 D E V R E S E R 5 8 2 D E V R E S E R 4 8 2 D E V R E S E R 3 8 2 D E V R E S E R 2 8 2 D E V R E S E R 299 GND 300 GND 301 GND 302 GND 303 GND 304 GND 305 GND 306 GND 307 GND 308 GND 309 GND 310 GND 311 GND 312 GND 313 GND 314 GND 315 GND 316 GND 317 GND 318 GND 319 GND 320 GND 321 GND 322 GND 323 GND 324 GND 325 GND 326 GND 327 GND 328 GND 329 GND 330 GND 331 GND 332 GND 333 GND 334 GND 335 GND 336 GND 337 GND 338 GND 339 GND 340 GND 341 GND 342 GND 343 GND 344 GND 345 GND 346 GND 347 GND 348 GND 349 GND 350 GND 351 GND 352 GND 353 GND 354 GND 355 GND 356 GND 357 GND 358 GND 359 GND 360 GND 361 GND 362 GND 363 GND 364 GND 365 GND 366 GND 367 GND 368 GND 369 GND 370 GND 371 GND 372 GND 373 GND 374 GND 375 GND 376 GND 377 GND 378 GND 379 GND 380 GND 381 GND 382 GND 383 GND 384 GND 385 GND 386 GND 387 GND 388 GND 5 6 2 D E V R E S E R 6 6 2 I I L V _ F W _ D D V 7 6 2 I I L V _ F W _ D D V 8 6 2 I I M V _ F W _ D D V 9 6 2 I I H V _ F W _ D D V 0 7 2 D E V R E S E R 1 7 2 D E V R E S E R 2 7 2 D E V R E S E R 3 7 2 D E V R E S E R 4 7 2 D E V R E S E R 5 7 2 I T C _ X D S _ O T _ L W 6 7 2 I T C _ L W _ O T _ X D S 7 7 2 D E V R E S E R 8 7 2 D E V R E S E R 9 7 2 D E V R E S E R 0 8 2 D E V R E S E R 1 8 2 I T N _ T X E 129 GND 126 GND 123 GND 120 RESERVED 117 RESERVED 114 W_DISABLE#

111 RESERVED 108 DBG_RXD 105 DBG_TXD 102 SLEEP_IND 99 RESERVED 96 GND 93 RESERVED 90 GND 87 RESERVED 84 GND 81 USB_BOOT 78 I2C_SDA 75 EXT_RST 72 RESERVED 69 RESERVED 66 VDD_EXT 197 GND 200 GND 203 GND 206 GND 209 GND 212 GND 215 GND 218 RESERVED 221 ETH1_INT_N 224 GND 227 GND 230 VBAT_RF1 233 VBAT_RF1 236 VBAT_BB 239 RESERVED 242 RESERVED 245 USIM1_VDD 248 USIM1_DATA 251 USIM2_DATA 254 USIM2_RST 257 I2S_DIN 260 RESERVED 263 RESERVED 198 RESERVED 201 WL_LAA_RX 204 SPI_MOSI 207 SPI_CS 210 SPI_CLK 213 SPI_MISO 216 WLAN_PWR_EN1 219 WLAN_PWR_EN2 222 WLAN_EN 225 WLAN_SLP_CLK 228 GND 231 GND 234 GND 237 STATUS 240 NET_MODE 243 NET_STATUS 246 RF_CLK3_WL 249 USIM1_DET 252 USIM2_DET 255 I2S_DOUT 258 MAIN_DTR 261 MAIN_DCD 3 D E V R E S E R 6 D E V R E S E R 9 D E V R E S E R 2 1 D N G 5 1 D E V R E S E R 8 1 D N G 1 2 D E V R E S E R 4 2 D E V R E S E R 7 2 D E V R E S E R 0 3 _ E K A W _ E C P I N 3 3 D N G 6 3 Q E R K L C _ E C P I N _ 9 3 N _ T S R _ E C P I 2 4 D N G 5 4 D E V R E S E R 8 4 D M C _ O D S I 1 5 2 A T A D _ O D S I 4 5 D E V R E S E R 7 5 D E V R E S E R 0 6 D D V _ O D S I 2 D E V R E S E R 5 D E V R E S E R 8 N _ T E S E R 1 1 D E V R E S E R 4 1 D E V R E S E R 7 1 D E V R E S E R 0 2 D E V R E S E R 3 2 D E V R E S E R 6 2 D N G 9 2 D E V R E S E R 2 3 M _ 0 X R _ E C P I 5 3 M _ 1 X R _ E C P I 8 3 M _ K L C F E R _ E C P I 1 4 M _ 1 X T _ E C P I 4 4 M _ 0 X T _ E C P I 7 4 K L C _ O D S I 0 5 1 A T A D _ O D S I 3 5 N E _ R W P _ O D S I 6 5 T E S V _ R W P _ O D S I 9 5 D X T _ T B 2 6 S T C _ T B 131 GND 128 GND 125 GND 122 GND 119 GND 116 GND 113 GND 110 VBAT_RF2 107 VBAT_RF2 104 ETH2_INT_N 101 RESERVED 98 GPIO_32 95 RESERVED 92 RESERVED 89 USB_SS_TX_M 86 USB_SS_RX_M 83 USB_DP 80 RESERVED 77 I2C_SCL 74 PCM_DIN 71 PCM_SYNC 68 MAIN_TXD 65 COEX_RXD 132 GND 130 ANT0 127 GND 124 GND 121 ANT4 118 GND 115 GND 112 VBAT_RF2 109 VBAT_RF2 106 RESERVED 103 RESERVED 100 MAIN_RI 97 RESERVED 94 RESERVED 91 USB_SS_TX_P 88 USB_SS_RX_P 85 USB_DM 82 USB_VBUS 79 MCLK 76 PCM_DOUT 73 PCM_CLK 70 MAIN_RXD 67 COEX_TXD 64 BT_EN 389 GND 1 D E V R E S E R 4 D E V R E S E R 7 Y E K R W P 0 1 D E V R E S E R 3 1 D E V R E S E R 6 1 D E V R E S E R 9 1 D E V R E S E R 2 2 D E V R E S E R 5 2 D E V R E S E R 8 2 D E V R E S E R 1 3 D E V R E S E R 4 3 P _ 0 X R _ E C P I 7 3 P _ 1 X R _ E C P I 0 4 P _ K L C F E R _ E C P I 3 4 P _ 1 X T _ E C P I 6 4 P _ 0 X T _ E C P I 9 4 0 A T A D _ O D S I 2 5 3 A T A D _ O D S I 5 5 T E D _ O D S I 8 5 D E V R E S E R 1 6 S T R _ T B 3 6 D X R _ T B 0 9 3 D N G Power Pins PCIe Pins ADC Pins CTL Pins GND Pins PCM Pins UART Pins Peripherals Control GPIO Pins

(U)SIM Pins SPI Pins I2S Pins RESERVED Pins I2C Pins USB Pins ANT Pins GRFC&RFFE SDIO Pins Wi-Fi Pins Figure 2: Pin Assignment (Top View) RG520F&RG520N_Series_Hardware_Design 19 / 116 5G Module Series NOTE 1. Keep all RESERVED or unused pins unconnected. 2. All GND pins should be connected to ground. 3. For RG520F-NA* and RG520N-NA, pins 121 and 175 are RESERVED. For RG520F-EU* and RG520N-EU, pins 121 and 175 are optional for ANT4 and ANT5 separately, which is related to CA configuration. 2.5. Pin Description The following table shows the DC characteristics and pin descriptions. Table 5: I/O Parameters Definition Type AI AO AIO DI DO DIO OD PI PO Description Analog Input Analog Output Analog Input/Output Digital Input Digital Output Digital Input/Output Open Drain Power Input Power Output Table 6: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment VBAT_BB 235, 236, 238 PI Power supply for the modules baseband part Vmax = 4.4 V Vmin = 3.3 V Vnom = 3.8 V RG520F&RG520N_Series_Hardware_Design 20 / 116 5G Module Series VBAT_RF1 VBAT_RF2 10 229, 230, 232, 233 PI 107, 109, 110, 112 PI VDD_WIFI_VL 266, 267 PO Power supply for the modules RF part Power supply for the modules RF part Provides 0.95 V for Wi-Fi/Bluetooth modules Vmax = 4.4 V Vmin = 3.3 V Vnom = 3.8 V Vmax = 4.4 V Vmin = 3.3 V Vnom = 3.8 V Vnom = 0.95 V IOmax = 1.7 A VDD_WIFI_VM 268 PO Provides 1.28 V for Wi-Fi/Bluetooth modules Vmax = 1.35 V Vnom = 1.28 V IOmax = 400 mA Power supply for Wi-Fi/Bluetooth modules. VDD_WIFI_VH 269 PO Provides 1.88 V for Wi-Fi/Bluetooth modules Vnom = 1.88 V IOmax = 400 mA VDD_EXT 66 PO Provides 1.8 V for external circuits Vnom = 1.8 V IOmax = 50 mA Power supply for external GPIOs pull-up circuits. 12, 18, 26, 33, 42, 84, 90, 96, 113, 115, 116, 118, 119, 122129, 131134, 136, 137, 140147, 149, 151, 152, 154156, 158, 160, 161, 163, 164, 167170, 172, 173, 176, 178, 179, 181, 182, 185, 187, 188, 190, 191, 194197, 200, 202, 203, 205, 206, 209, 211, 212, 214, 215, 224, 226, 227, 228, 231, 234, 299392 GND Turn on/off Pin Name Pin No. I/O Description DC Characteristics 1.8 V high level DI Turns on/off the module DI Resets the module 1.8 V Comment Internally pulled up to 1.8 V. Internally pulled up to 1.8 V with a 40 k resistor. PWRKEY RESET_N 7 8 Status Indication Pin Name Pin No. I/O Description DC Characteristics Comment STATUS 237 DO NET_MODE 240 DO Indicates the modules operation status Indicates whether the module has registered on 5G 1.8 V 10 VBAT_RF2 should be connected to an external VBAT power supply while PC 1.5 (which is optional for customers) is designed; otherwise, it is only used to connect decoupling capacitors. RG520F&RG520N_Series_Hardware_Design 21 / 116 5G Module Series network Indicates the modules network activity status Indicates the modules sleep mode NET_STATUS 243 DO SLEEP_IND 102 DO USB Interface Pin Name Pin No. I/O Description USB_VBUS 82 AI USB connection detect USB_DP USB_DM 83 85 AIO AIO USB differential data (+) USB differential data (-) USB_SS_TX_P 91 AO USB_SS_TX_M 89 AO USB_SS_RX_P 88 AI USB_SS_RX_M 86 AI

(U)SIM Interfaces USB 3.1 super-speed transmit (+) USB 3.1 super-speed transmit (-) USB 3.1 super-speed receive (+) USB 3.1 super-speed receive (-) DC Characteristics Vmax = 5.25 V Vmin = 3.3 V Vnom = 5.0 V Comment For USB connection detection only, not power supply. Requires differential impedance of 90 . USB 2.0 compliant. Requires differential impedance of 85 . USB 3.1 Gen2 compliant. Pin Name Pin No. I/O Description DC Characteristics Comment USIM1_VDD 245 PO

(U)SIM1 card power supply 1.8/2.95 V USIM1_DATA 248 DIO

(U)SIM1 card data USIM1_CLK 247 DO

(U)SIM1 card clock USIM1_VDD 1.8/2.95 V USIM1_RST 244 DO

(U)SIM1 card reset RG520F&RG520N_Series_Hardware_Design 22 / 116 5G Module Series USIM1_DET 249 DI USIM2_VDD 250 PO

(U)SIM1 card hot-plug detect

(U)SIM2 card power supply 1.8 V 1.8/2.95 V USIM2_DATA 251 DIO

(U)SIM2 card data USIM2_CLK 253 DO

(U)SIM2 card clock USIM2_VDD 1.8/2.95 V USIM2_RST 254 DO

(U)SIM2 card reset If unused, keep it open. USIM2_DET 252 DI

(U)SIM2 card hot-plug detect 1.8 V If unused, keep it open. Main UART Interface Pin Name Pin No. I/O Description MAIN_TXD MAIN_RXD 68 70 DO DI Main UART transmit Main UART receive DC Characteristics Comment MAIN_RI*

100 DO MAIN_DTR 258 DI MAIN_DCD*

261 DO Bluetooth UART Interface*

1.8 V Main UART ring indication Main UART data terminal ready Main UART data carrier detect Pin Name Pin No. I/O Description DC Characteristics Comment BT_TXD BT_RXD BT_RTS BT_CTS 59 63 61 62 DO DI DI DO Bluetooth UART transmit Bluetooth UART receive DTE request to send signal to DCE DTE clear to send signal from DCE 1.8 V Debug UART Interface Connect to DTEs RTS. Connect to DTEs CTS. Pin Name Pin No. I/O Description DC Characteristics Comment RG520F&RG520N_Series_Hardware_Design 23 / 116 5G Module Series DBG_RXD 108 DI DBG_TXD 105 DO Debug UART receive Debug UART transmit 1.8 V I2C Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment I2C_SCL 77 OD I2C serial clock I2C_SDA 78 OD I2C serial data 1.8 V Pull each of them up to VDD_EXT with an external 4.7 k resistor. If unused, keep them open. I2S Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment I2S_WS 259 DIO I2S word select I2S_SCK 256 DIO I2S clock 1.8 V I2S_DIN 257 DI I2S data in I2S_DOUT 255 DO I2S data out MCLK 79 DO Clock output for codec PCM Interface*

In master mode, it is an output signal. In slave mode, it is an input signal. Can be multiplexed into PCM_SYNC. In master mode, it is an output signal. In slave mode, it is an input signal. Can be multiplexed into PCM_CLK. Can be multiplexed into PCM_DIN. Can be multiplexed into PCM_DOUT. If unused, keep it open. Pin Name Pin No. I/O Description DC Characteristics Comment PCM_SYNC PCM_CLK 71 73 DIO PCM data frame sync DIO PCM clock 1.8 V In master mode, it is an output signal. In slave mode, it is an input signal. RG520F&RG520N_Series_Hardware_Design 24 / 116 5G Module Series PCM_DIN PCM_DOUT 74 76 DI PCM data input DO PCM data output If unused, keep it open. DC Characteristics Comment PCIe Interface Pin Name Pin No. I/O Description PCIE_REFCLK_P 40 AIO PCIE_REFCLK_M 38 AIO PCIe reference clock (+) PCIe reference clock (-) PCIE_TX0_M PCIE_TX0_P PCIE_TX1_M PCIE_TX1_P PCIE_RX0_M PCIE_RX0_P PCIE_RX1_M PCIE_RX1_P 44 46 41 43 32 34 35 37 AO PCIe transmit 0 (-) AO PCIe transmit 0 (+) AO PCIe transmit 1 (-) AO PCIe transmit 1 (+) AI AI AI AI PCIe receive 0 (-) PCIe receive 0 (+) PCIe receive 1 (-) PCIe receive 1 (+) PCIE_CLKREQ_N 36 OD PCIe clock request PCIE_RST_N 39 DIO PCIe reset 1.8 V PCIE_WAKE_N 30 OD PCIe wake up Requires differential impedance of 85 . One PCIe port is supported. It can be either Gen 3 2-lane or Gen 4 1-lane. In root complex mode, it is an input signal. In endpoint mode, it is an output signal. In root complex mode, it is an output signal. In endpoint mode, it is an input signal. In root complex mode, it is an input signal. In endpoint mode, it is an output signal. WWAN/WLAN Application Interface*

Pin Name Pin No. I/O Description DC Comment RG520F&RG520N_Series_Hardware_Design 25 / 116 5G Module Series Characteristics Only for Qualcomn platform. Signal interface used for WWAN/WLAN coexistence mechanism. Pin 65 can be multiplexed into SDX2AP_E911 function. Pin 67 can be multiplexed into SDX2AP_STATUS function. For details, please contact Quectel Technical Supports. This pin is used for the coexistence of n79 and Wi-Fi 5G. If n79 is needed in customer future project with Quectel modules, then this pin shall be pulled out and reserved;

otherwise, the pin can be NC. COEX_RXD 65 DI Coexistence UART receive COEX_TXD 67 DO Coexistence UART transmit HST_LAA_TX_EN 135 DO HST_WL_TX_EN 138 DI WLAN_PWR_ EN1 WLAN_PWR_ EN2 216 DO 219 DO 1.8 V Notifies LAA/n79 transmission from SDR transceiver to WLAN Notifies WLAN transmission from WLAN to SDR transceiver Controls WLAN PA power Controls WLAN other power BT_EN 64 DO Bluetooth enable WLAN_EN 222 DO WLAN enable RG520F&RG520N_Series_Hardware_Design 26 / 116 5G Module Series WL_SW_CTRL 180 DI WLAN_SLP_CLK 225 AO RF_CLK3_WL 246 AO 76.8 MHz system clock request 32.768 kHz sleep clock output 76.8 MHz system clock output SDX_TO_WL_CTI 276 DO

Vmax = 1.08 V Vnom = 1.05 V Vmin = 1.02 V Not used by default. Keep it open. WLAN_PA_ MUTING 162 DO WL_LAA_AS_EN 159 DO WL_LAA_RX 201 DO GPIO from SDX to disable WLAN PA GPIO to allow WWAN to power on WLAN 0.8 V AON domain, when WLAN is sleeping or disabled. Additionally, the control logic in WLAN AON domain allows SDR to control 5G WLAN xLNA (LNA in FEMs) SoC signal to set 5G xLNA to high gains or high isolation when both chains (LAA and 5G WLAN) are active simultaneously. No individual control for each chain 1.8 V WL_TO_SDX_CTI 275 DI

SDIO Interface Not used by default. Keep it open. Pin Name Pin No. I/O Description DC Characteristics Comment RG520F&RG520N_Series_Hardware_Design 27 / 116 5G Module Series SDIO_VDD 60 PI SDIO power supply SDIO_DATA0 SDIO_DATA1 SDIO_DATA2 SDIO_DATA3 SDIO_CMD SDIO_CLK 49 50 51 52 48 47 SDIO_PWR_EN 53 SDIO_PWR_ VSET 56 DIO SDIO data bit 0 DIO SDIO data bit 1 DIO SDIO data bit 2 DIO SDIO data bit 3 DIO SDIO command DO SDIO clock DO DO SDIO power supply enable SDIO power domain set SDIO_DET 55 DI SD hot-plug detect 1.8/2.85 V configurable input. If unused, connect it to VDD_EXT. The power domain of SD I/O pins depends on SDIO_VDD. If unused, keep them open. 1.8 V Pull it up to VDD_EXT with a 470 k resistor. If unused, keep it open. Antenna Interfaces for RG520F-NA*/RG520N-NA Pin Name Pin No. I/O Description Comment ANT0 130 AIO Antenna 0 interface:

5G NR: n41 TRX1 & n77/n78 TRX0 LTE: LMB_TRX0 & HB_TRX1 &

UHB_TRX0 ANT1 157 AIO

Antenna 1 interface:

5G NR: n41 DRX MIMO & n77/n78 DRX MIMO LTE: LMB_PRX MIMO & HB_DRX MIMO & UHB_DRX MIMO &

LAA_PRX 50 impedance. ANT2 166 AIO

Antenna 2 interface:

5G NR: n41 PRX MIMO & n77/n78 PRX MIMO LTE: LMB_DRX MIMO & HB_PRX MIMO & UHB_PRX MIMO &

LAA_DRX RG520F&RG520N_Series_Hardware_Design 28 / 116 5G Module Series ANT3 184 AIO ANT_GNSS 193 AI Antenna 3 interface:

5G NR: n41 TRX0 & n77/n78 TRX1 LTE: LMB_TRX1 & HB_TRX0 &

UHB_TRX1 GNSS antenna interface:

L1/L5 Antenna Interfaces for RG520F-EU*/RG520N-EU Pin Name Pin No. I/O Description Comment ANT0 130 AIO Antenna 0 interface:

5G NR: n41 TRX1 & n77/n78 TRX0 LTE: LMB_TRX0 & HB_TRX1 &

UHB_TRX0

- WCDMA: LMB_TRX ANT1 157 AIO

Antenna 1 interface:

5G NR: n41 DRX MIMO & n77/n78 DRX MIMO LTE: LMB_PRX MIMO & HB_DRX MIMO & UHB_DRX MIMO ANT2 166 AIO

Antenna 2 interface:

5G NR: n41 PRX MIMO & n77/n78 PRX MIMO LTE: LMB_DRX MIMO & HB_PRX MIMO & UHB_PRX MIMO 50 impedance. ANT3 184 AIO Antenna 3 interface:

5G NR: n41 TRX0 & n77/n78 TRX1 LTE: LMB_TRX1 & HB_TRX0 &

UHB_TRX1 ANT4 ANT5 121 175 ANT_GNSS 193

- WCDMA: LMB_DRX Antenna 4 interface:

LTE: B32_PRX (optional) Antenna 5 interface:

LTE: B32_DRX (optional) GNSS antenna interface:

L1/L5 AI AI AI Antenna Tuner Control Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment SDR_GRFC0 171 SDR_GRFC1 174 DO DO GRFC interface dedicated for external antenna tuner control 1.8 V If unused, keep them open. RG520F&RG520N_Series_Hardware_Design 29 / 116 5G Module Series SPI Interface Pin Name Pin No. I/O Description DC Characteristics Comment SPI_CLK SPI_CS 210 207 DO SPI clock DO SPI chip select SPI_MISO 213 DI SPI_MOSI 204 DO SPI master-in slave-out SPI master-out slave-in ADC Interface 1.8 V Only master mode is supported. Pin Name Pin No. I/O Description DC Characteristics Comment ADC0 241 AI General-purpose ADC interface Voltage range:

01.875 V Time Service and Repeater Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment GPIO_32 98 DO Supports time service and repeater functions;

supports 1PPS pulse output and frame synchronization 1.8 V Can be multiplexed into AP2SDX_ STATUS function. For details, please contact Quectel Technical Supports. Other Interface Pins Pin Name Pin No. I/O Description DC Characteristics Comment USB_BOOT 81 DI EXT_RST 75 DO EXT_INT 281 W_DISABLE#

114 DI DI Forces the module to enter emergency download mode External audio reset External audio interrupt Airplane mode control 1.8 V ETH1_PWR_EN*

220 DO Ethernet PHY 1 These pins are the RG520F&RG520N_Series_Hardware_Design 30 / 116 5G Module Series power enable Ethernet PHY 2 power enable Interrupts input from Ethernet PHY 1 Interrupts input from Ethernet PHY 2 ETH2_PWR_EN*

223 DO ETH1_INT_N*

221 DI ETH2_INT_N*

104 DI RESERVED Pins Pin Name Pin No. 16, 9, 10, 11, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29, 31, 45, 54, 57, 58, 69, 72, 80, 87, 9295, 97, 99, 101, 103, 106, 111, 117, 120, 139, 148, 150, 153, 165, 177, 183, 186, 189, 192, 198, 199, 208, 217, 218, 239, 242, 260, 262265, 270, 271273, 274, 277280, 282298 RESERVED NOTE control pins of PHY chip recommended by the platform. Comment Keep these pins unconnected. 1. RG520F-NA* and RG520N-NA: 4 antenna interfaces + 1 GNSS antenna interface (ANT0/1/2/3 +

ANT_GNSS). 2. RG520F-EU* and RG520N-EU: 4 + 2 (optional) cellular antenna interfaces + 1 GNSS antenna interface (ANT0/1/2/3 + ANT4/5 (optional) + ANT_GNSS). 2.6. EVB In order to help customers to develop applications with the module conveniently, Quectel supplies an evaluation board (5G EVB), USB data cable, earphone, antenna, and other peripherals to control or to test the module. For more details, please refer to document [5]. RG520F&RG520N_Series_Hardware_Design 31 / 116 5G Module Series 3 Operating Characteristics 3.1. Operating Modes The table below outlines operating modes of the module. Table 7: Overview of Operating Modes Mode Details Normal Operation Idle Talk/Data Software is active. The module is registered on the network and ready to send and receive data. Network connection is ongoing. In this mode, the power consumption is decided by network setting and data transfer rate. Minimum Functionality Mode Airplane Mode AT+CFUN=0 command can set the module to a minimum functionality mode. In this case, both RF function and (U)SIM card will be invalid. AT+CFUN=4 command or driving W_DISABLE# LOW will set the module to airplane mode. In this case, RF function will be invalid. Sleep Mode In this mode, current consumption of the module will be reduced to the minimal level. In this mode, the module can still receive paging, SMS, voice call and TCP/UDP data from network. Power Down Mode In this mode, the VBAT power supply is constantly turned on and the software stops working. NOTE For more details about AT command, see document [6]. RG520F&RG520N_Series_Hardware_Design 32 / 116 5G Module Series 3.2. Sleep Mode DRX of the module is able to reduce the current consumption to a minimum value during sleep mode. The diagram below illustrates the relationship between the DRX run time and the current consumption of the module in this mode. t n e r r u C DRX OFF ON OFF ON OFF ON OFF ON OFF Run Time Figure 3: DRX Run Time and Current Consumption in Sleep Mode 3.2.1. UART Application Scenario If the host communicates with the module via UART interface, the following two preconditions should be met to set the module enter sleep mode:

Execute AT+QSCLK=1 command to enable sleep mode. Drive MAIN_DTR high. The figure illustrates the connection between the module and the host. Module MAIN_RXD MAIN_TXD MAIN_RI MAIN_DTR GND Host TXD RXD EINT GPIO GND Figure 4: Sleep Mode Application via UART RG520F&RG520N_Series_Hardware_Design 33 / 116 5G Module Series Driving MAIN_DTR low with the host will wake up the module. When the module has a URC to report, MAIN_RI signal will wake up the host. Please refer to Chapter 4.15 for details about RI behavior. 3.2.2. USB Application Scenario 3.2.2.1. USB Application with USB Remote Wakeup Function If the host supports USB suspend/resume and remote wakeup function, the following three preconditions can make the module enter the sleep mode. Execute AT+QSCLK=1 to enable sleep mode. Ensure the MAIN_DTR is held at high level or keep it open. Ensure the hosts USB bus, which is connected with the modules USB interface, enters suspend state. Module USB_VBUS USB_DP USB_DM GND Host VDD USB_DP USB_DM GND Figure 5: Sleep Mode Application with USB Remote Wakeup Sending data to the module through USB will wake up the module. When the module has a URC to report, the module will send remote wake-up signals to USB Bus to wake up the host. 3.2.2.2. USB Application with USB Suspend/Resume and MAIN_RI Function If the host supports USB Suspend/Resume, but does not support remote wakeup function, the MAIN_RI signal is needed to wake up the host. RG520F&RG520N_Series_Hardware_Design 34 / 116 5G Module Series In this case, the following three preconditions can make the module enter the sleep mode. Execute AT+QSCLK=1 command to enable sleep mode. Ensure MAIN_DTR is held at a high level or keep it open. The hosts USB Bus, which is connected with the modules USB interface, enters suspend state. The following figure illustrates the connection between the module and the host. Module USB_VBUS USB_DP USB_DM MAIN_RI GND Host VDD USB_DP USB_DM EINT GND Figure 6: Sleep Mode Application with RI Sending data to the module through USB will wake up the module. When the module has a URC to report, the MAIN_RI signal will wake up the host. 3.2.2.3. USB Application without USB Suspend Function If the host does not support USB suspend function, disconnect USB_VBUS with an external control circuit to make the module enter sleep mode. Execute AT+QSCLK=1 command to enable sleep mode. Ensure the MAIN_DTR is held at a high level or keep it open. Disconnect USB_VBUS. The figure illustrates the connection between the module and the host. RG520F&RG520N_Series_Hardware_Design 35 / 116 5G Module Series Module Host USB_VBUS Power Switch USB_DP USB_DM MAIN_RI GND GPIO VDD USB_DP USB_DM EINT GND Figure 7: Sleep Mode Application without Suspend Function Turn on the power switch and supply power to USB_VBUS will wake up the module. NOTE Please pay attention to the level match shown in dotted line between the module and the host. 3.3. Airplane Mode When the module enters airplane mode, the RF function will be disabled, and all AT commands related to it will be inaccessible. This mode can be set via the following ways. 3.3.1. Hardware The W_DISABLE# pin is pulled up by default. Its control function for airplane mode is disabled by default and AT+QCFG= airplanecontrol, 1 can be used to enable the function. Driving it low will set the module enter airplane mode. 3.3.2. Software AT+CFUN=<fun> command provides choices of the functionality level through setting <fun> into 0, 1 or 4. AT+CFUN=0: Minimum functionality (disable RF function and (U)SIM function). RG520F&RG520N_Series_Hardware_Design 36 / 116 5G Module Series AT+CFUN=1: Full functionality (default). AT+CFUN=4: Airplane mode (disable RF function). NOTE The execution of AT+CFUN command will not affect GNSS function. 3.4. Power Supply 3.4.1. Power Supply Pins The module provides 11 VBAT pins dedicated to the connection with the external power supply. There are three separate voltage domains for VBAT. Four VBAT_RF1 pins and four VBAT_RF2 pins for RF part. Three VBAT_BB pins for baseband part. Table 8: Pin Definition of Power Supply Pin Name Pin No. I/O Description Min. Typ. Max. Unit VBAT_BB VBAT_RF1 VBAT_RF2 11 235, 236, 238 229, 230, 232, 233 107, 109, 110, 112 PI PI PI Power supply for the modules baseband part 3.3 3.8 4.4 V Power supply for the modules RF part Power supply for the modules RF part 3.3 3.8 4.4 V 3.3 3.8 4.4 V GND 12, 18, 26, 33, 42, 84, 90, 96, 113, 115, 116, 118, 119, 122129, 131134, 136, 137, 140147, 149, 151, 152, 154156, 158, 160, 161, 163, 164, 167170, 172, 173, 176, 178, 179, 181, 182, 185, 187, 188, 190, 191, 194197, 200, 202, 203, 205, 206, 209, 211, 212, 214, 215, 224, 226, 227, 228, 231, 234, 299392

0

V 11 VBAT_RF2 should be connected to an external VBAT power supply while PC 1.5 (which is optional for customers) is designed; otherwise, it is only used to connect decoupling capacitors. RG520F&RG520N_Series_Hardware_Design 37 / 116 5G Module Series 3.4.2. Reference Design for Power Supply The performance of the module largely depends on the power source. The power supply of the module should be able to provide sufficient current of 3 A at least. If the voltage drops between input and output is not too high, it is suggested that an LDO should be used to supply power to the module. If there is a big voltage difference between input and the desired output VBAT, a buck converter is preferred as the power supply. The following figure shows a reference design for +5 V input power source. The designed output of the power supply is about 3.8 V and the maximum rated current is 3 A. GND TPS62130

+5 V TV S C1 C2 R1 C3 L1 R2 R3 R4 C5 C6 3V8_EN C4 GND GND GND GND Figure 8: Reference Design of Power Supply NOTE To avoid damaging internal flash, do not switch off the power supply when the module works normally. Only after shutting down the module with PWRKEY or AT command can you cut off the power supply. 3.4.3. Power Supply AT+CBC command can monitor the VBAT_BB voltage value. For more details, please refer to document

[6]. RG520F&RG520N_Series_Hardware_Design 38 / 116 5G Module Series 3.4.4. Voltage Stability Requirements The power supply range of the module is from 3.3 V to 4.4 V. Please make sure the input voltage will never drop below 3.3 V. Burst Transmission Burst Transmission VBAT Drop Figure 9: Power Supply Limits during Burst Transmission To decrease voltage s drop, a bypass capacitor of about 100 F with low ESR should be used, and a same bypass capacitor of about 100 F need to be reserved. On the other hand, a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low ESR. It is recommended to use 22 ceramic capacitors for composing the MLCC array, and place these capacitors close to VBAT pins. The main power supply from an external application must be a single voltage source and can be expanded to two sub paths with the star structure. The width of VBAT_BB trace should be no less than 1.2 mm. The width of VBAT_RF1 and VBAT_RF2 trace should be no less than 2 mm. In principle, the longer the VBAT trace is, the wider it will be. In addition, in order to ensure the stability of the power supply, it is necessary to add a high-power TVS at the front end of the power supply. Reference circuit is shown as below:

RG520F&RG520N_Series_Hardware_Design 39 / 116 5G Module Series VBAT F 0 0 1 _ M N C1 C2 C3 C4 C5 C6 100 F 100 nF 6.8 nF 220 pF 68 pF R1 0R R2 0R 0R F 0 0 1 _ M N R3 NM-0R D1 F 0 0 1 _ M N 100 F 100 nF 220 pF 68 pF 15 pF 9.1 pF 4.7 pF C7 C8 C9 C10 C11 C12 C13 C14 VBAT_BB VBAT_RF1 VBAT_RF2 100 F 100 nF 220 pF 68 pF 15 pF 9.1 pF 4.7 pF C15 C16 C17 C18 C19 C20 C21 C22 Module Figure 10: Star Structure of the Power Supply NOTE 1. MLCC array for VBAT_BB includes 100 F, 100 nF, 6.8 nF, 220 pF, 68 pF and a 100 F is reserved. 2. MLCC array for VBAT_RF1 and VBAT_RF2 includes 100 F, 100 nF, 220 pF, 68 pF, 15 pF, 9.1 pF, 4.7 pF and a 100 F is reserved. 3. R3 needs to be reserved since VBAT_RF2 should be connected to an external VBAT power supply while PC 1.5 (which is optional for customers) is designed. RG520F&RG520N_Series_Hardware_Design 40 / 116 5G Module Series 3.5. Turn On 3.5.1. Turn on the Module with PWRKEY Table 9: Pin Definition of PWRKEY Pin Name Pin No. PWRKEY 7 I/O DI Description Comment Turns on/off the module Internally pulled up. When the module is in power off mode, it can be turned on and enter normal operation mode by driving PWRKEY low for at least 500 ms. It is recommended to use an open drain/collector driver to control PWRKEY. After STATUS pin outputs a high level, PWRKEY can be released. 500 ms Turn on pulse 4.7K 47K Q1 G P IO M C U PWRKEY M odule Figure 11: Reference Circuit of Turning on the Module with Driving Circuit Another way to control the PWRKEY is by using a button directly. When pressing the button, an electrostatic strike may generate from finger. Therefore, a TVS component shall be placed near the button for ESD protection. RG520F&RG520N_Series_Hardware_Design 41 / 116 5G Module Series S1 R1 1K PWRKEY TVS Turn-on pulse Close to S1 M odule Figure 12: Reference Circuit of Turning on the Module with a Button The turn on scenario is illustrated in the following figure. N O TE V B AT P W R K E Y R ES E T_N S TA TU S U AR T U SB V D D _E X T 69 m s 500 m s V IH = 1.8 V 3 m s V IL 0.5 V TB D TB D Inactive TB D A ctive Inactive A ctive 10 m s Figure 13: Power-up Timing RG520F&RG520N_Series_Hardware_Design 42 / 116 5G Module Series

. NOTE Please ensure that VBAT is stable for at least 30 ms before pulling down the PWRKEY. 3.6. Turn Off 3.6.1. Turn off the Module with PWRKEY Driving PWRKEY low for at least 800 ms, then the module will execute power-down procedure after the PWRKEY is released. 800 m s T B D V B A T P W R K E Y S T A TU S M od ule S tatus R unning P ow er-dow n procedure O F F V D D _E X T 17 m s Figure 14: Power-down Timing 3.6.2. Turn off the Module with AT Command It is safe to use AT+QPOWD command to turn off the module, which is similar to turn off the module via PWRKEY pin. Please refer to document [6] for details about AT+QPOWD command. RG520F&RG520N_Series_Hardware_Design 43 / 116 5G Module Series

. NOTE 1. In order to avoid damaging the internal flash, please do not switch off the power supply when the module works normally. Only after the module is power off by PWRKEY or AT command, the power supply can be cut off. 2. When turning off module with AT command, please keep PWRKEY at a high level after the execution of power-off command. Otherwise, the module will be turned on again after turned off. 3.7. Reset The module can be reset by driving RESET_N low for at least 500 ms and then releasing it. The RESET_N signal is sensitive to interference, so it is recommended to route the trace as short as possible and surround it with ground. Table 10: Pin Definition of RESET Pin Name Pin No. RESET_N 8 I/O DI Description Comment Resets the module Internally pulled up to 1.8 V. The recommended circuit is the same as the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET_N. 500 ms Reset pulse 4.7K 47K Q1 G P IO M C U RESET_N M odule Figure 15: Reference Circuit of RESET_N with Driving Circuit RG520F&RG520N_Series_Hardware_Design 44 / 116 5G Module Series S2 TVS RESET_N R1 1K Reset pulse Close to S2 Module Figure 16: Reference Circuit of RESET_N with Button V B A T R E S E T_N S T A TU S M od ule S tatus NOTE T 500 m s 200 m s T B D R unning R esetting R estart Figure 17: Reset Timing 1. Use RESET_N only when you fail to turn off the module with the AT+QPOWD and PWRKEY. 2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins. RG520F&RG520N_Series_Hardware_Design 45 / 116 5G Module Series 4 Application Interfaces 4.1. USB Interface The module provides one USB interface. The USB interface complies with the USB 3.1 and USB 2.0 specifications, and supports Super-Speed (10 Gbps) for USB 3.1, High-Speed (480 Mbps) and Full-Speed (12 Mbps) for USB 2.0. Table 11: Functions of the USB Interface Functions AT command communication Data transmission GNSS NMEA sentence output Software debugging Firmware upgrade Voice over USB*

Pin definition of the USB interface is here as follows:

Table 12: Pin Definition of USB Interface Pin Name Pin No. I/O Description Comment USB_VBUS USB_DP USB_DM 82 83 85 AI USB connection detect AIO USB differential data (+) AIO USB differential data (-) For USB connection detection only, not power supply. Requires differential impedance of 90 . USB 2.0 compliant. RG520F&RG520N_Series_Hardware_Design 46 / 116 5G Module Series USB_SS_TX_P 91 USB_SS_TX_M 89 USB_SS_RX_P 88 USB_SS_RX_M 86 AO AO AI AI USB 3.1 super-speed transmit (+) USB 3.1 super-speed transmit (-) USB 3.1 super-speed receive (+) USB 3.1 super-speed receive (-) Requires differential impedance of 85 . USB 3.1 Gen2 compliant. It is recommended to reserve test points for debugging and firmware upgrading in your designs. Minimize these stubs Test Points Module VDD USB_VBUS USB_DM USB_DP R3 R4 R1 R2 NM_0R NM_0R 0R 0R Close to Module TVS Array USB_SS_TX_P C1 220 nF USB_SS_TX_M C2 220 nF USB_SS_RX_P USB_SS_RX_M GND 220 nF C3 220 nF C4 Host USB_DM USB_DP USB_SS_RX_P USB_SS_RX_M USB_SS_TX_P USB_SS_TX_M GND Figure 18: Reference Circuit of USB Application To ensure the signal integrity of USB data lines, you must place R1, R2, R3, R4, C1 and C2 close to the module, C3 and C4 close to the host, and keep these resistors close to each other. Keep the extra stubs of trace as short as possible. The following principles should be complied with when designing the USB interface, to meet USB specifications. It is important to route the USB signal traces as differential pairs with ground surrounded. The impedance of USB 2.0 differential trace is 90 . The impedance of USB 3.1 differential trace is 85 . For USB 2.0 signal traces, the trace as length should be less than 250 mm, length matching of each differential data pair (DP/DM) should be less than 2 mm (14 ps). For USB 3.1 signal traces, length RG520F&RG520N_Series_Hardware_Design 47 / 116 5G Module Series matching of each differential data pair (Tx/Rx) should be less than 0.7 mm (5 ps), while the matching between Tx and Rx should be less than 10 mm. Do not route signal traces under crystals, oscillators, magnetic devices, PCIe and RF signal traces. It is important to route the USB differential traces in inner-layer of the PCB, and surround the traces with ground on that layer and ground planes above and below. Junction capacitance of the ESD protection components might cause influences on USB data lines, so please pay attention to the selection of the components. Typically, the stray capacitance should be less than 1.0 pF for USB 2.0, and less than 0.15 pF for USB 3.1. Keep the ESD protection components as close to the USB connector as possible If possible, reserve a 0 resistor on USB_DP and USB_DM lines respectively. For more details about the USB specifications, please visit http://www.usb.org/home. Table 13: USB Trace Length in the Module Pin No. Pin Name Length (mm) Length difference (P-M) (mm) USB_DP USB_DM USB_SS_TX_P USB_SS_TX_M USB_SS_RX_P USB_SS_RX_M 31.10 31.15 32.90 33.02 30.90 30.73 83 85 91 89 88 86 NOTE

-0.05

-0.12

-0.17 1. Only USB 2.0 interface supports firmware upgrade. 2. Both USB 3.1 interface and PCIe Gen 3 interface support data transmission, and USB 3.1 interface is used by default. If you want to use PCIe interface for data communication, set it with AT+QCFG via USB 2.0. For more details about AT command, see document [6]. 4.2. USB_BOOT Interface The module provides a USB_BOOT pin. You can pull up USB_BOOT to VDD_EXT before powering on the module, thus the module will enter emergency download mode when powered on. In this mode, the module supports firmware upgrade over USB 2.0 interface. RG520F&RG520N_Series_Hardware_Design 48 / 116 5G Module Series Module USB_BOOT Test point 10K VDD_EXT TVS TVS Close to test point Figure 19: Reference Circuit of USB_BOOT Interface 4.3. (U)SIM Interfaces

(U)SIM interfaces circuitry meet ETSI and IMT-2000 requirements. Both Class B (2.95 V) and Class C

(1.8 V) (U)SIM cards are supported, and Dual SIM Single Standby* function is supported. Table 14: Pin Definition of (U)SIM Interfaces Pin Name Pin No. I/O Description Comment USIM1_VDD 245 PO

(U)SIM1 card power supply Either 1.8 V or 2.95 V is supported by the module automatically. DIO

(U)SIM1 card data USIM1_DATA USIM1_CLK USIM1_RST USIM1_DET 248 247 244 249 DO DO DI USIM2_VDD 250 PO

(U)SIM1 card clock

(U)SIM1 card reset

(U)SIM1 card hot-plug detect 1.8 V power domain. If unused, keep it open.

(U)SIM2 card power supply Either 1.8 V or 2.95 V is supported by the module automatically. USIM2_DATA USIM2_CLK 251 253 DIO DO

(U)SIM2 card data

(U)SIM2 card clock RG520F&RG520N_Series_Hardware_Design 49 / 116 5G Module Series USIM2_RST USIM2_DET 254 252 DO DI

(U)SIM2 card reset

(U)SIM2 card hot-plug detect 1.8 V power domain. If unused, keep it open. The module supports (U)SIM card hot-plug via the USIM_DET pin. The function supports low level and high level detections. It is disabled by default and you can configure it via AT+QSIMDET. See document

[6] for more details about the command. The following figure illustrates a reference design for (U)SIM card interface with an 8-pin (U)SIM card connector. VDD_EXT USIM_VDD 100 K 20K Module USIM_GND USIM_VDD USIM_RST USIM_CLK USIM_DET USIM_DATA 0R 0R 0R F p 0 1 F n 0 0 1

(U)SIM Card Connector VCC RST CLK GND VPP IO 10 pF 10 pF 10 pF GND TVS Array GND GND Figure 20: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_DET unconnected. A reference circuit for (U)SIM card interface with a 6-pin (U)SIM card connector is illustrated in the following figure. RG520F&RG520N_Series_Hardware_Design 50 / 116 5G Module Series Module USIM_VDD F p 0 1 F n 0 0 1 USIM_VDD USIM_RST USIM_CLK USIM_DET USIM_DATA GND 20k 0R 0R 0R F p 0 1 F p 0 1 F p 0 1 TVS Array

(U)SIM Card Connector VPP VCC RST CLK IO GND Figure 21: Reference Circuit of a 6-Pin (U)SIM Card Connector In order to enhance the reliability and availability of the (U)SIM card in applications, please follow the criteria below in (U)SIM circuit design. Keep (U)SIM card connector as close as possible to the module. Keep the trace length as less than 200 mm as possible. Keep (U)SIM card signal traces away from RF and VBAT traces. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with ground surrounded. In order to offer better ESD protection, it is recommended to add a TVS array with a parasitic capacitance not exceeding 10 pF. The 0 resistors should be added in series between the module and the (U)SIM card connector so as to suppress EMI spurious transmission and enhance ESD protection. The 10 pF capacitors are used to filter out RF interference. The 20 k pull-up resistor on USIM_DATA trace improves anti-jamming capability and should be placed close to the (U)SIM card connector.

(U)SIM card hot plug function is not supported by default. A space was reserved for eSIM inside the module on the (U)SIM2 interface. All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout. 4.4. I2C Interface*

The module provides one I2C interface. As an open drain output, it should be pulled up to 1.8 V. Pin definition is here as follows:

RG520F&RG520N_Series_Hardware_Design 51 / 116 5G Module Series Table 15: Pin Definition of I2C Interface Pin Name Pin No. I2C_SCL I2C_SDA 77 78 Description Comment I/O OD I2C serial clock OD I2C serial data Pull each of them up to VDD_EXT with an external 4.7 k resistor. If unused, keep them open. 4.5. I2S Interface*

The module provides one I2S interface. Pin definition is here as follows:

Table 16: Pin Definition of I2S Interface Pin Name Pin No. I/O Description Comment In master mode, it is an output signal. In slave mode, it is an input signal. Can be multiplexed into PCM_SYNC. In master mode, it is an output signal. In slave mode, it is an input signal. Can be multiplexed into PCM_CLK. Can be multiplexed into PCM_DIN. Can be multiplexed into PCM_DOUT. I2S_WS 259 DIO I2S word select I2S_SCK 256 DIO I2S clock I2S_DIN I2S_DOUT MCLK 257 255 79 DI I2S data in DO I2S data out DO Clock output for codec If unused, keep it open. The following figure shows a reference design of I2S interface with an external codec IC. RG520F&RG520N_Series_Hardware_Design 52 / 116 5G Module Series MCLK I2S_SCK I2S_WS I2S_DOUT I2S_DIN I2C_SCL I2C_SDA Module K 7

. 4 K 7

. 4 1.8 V MCLK MICBIAS I2S_SCK I2S_WS I2S_DIN I2S_DOUT SCL SDA Codec INP INN S A B I LOUTP LOUTN Figure 22: Reference Circuit of I2S Application with Audio Codec 4.6. PCM Interface*

The module provides one Pulse Code Modulation (PCM) digital interface and one I2S interface. The PCM interface supports the following modes:

Primary mode (short frame synchronization, works as both master and slave) Auxiliary mode (long frame synchronization, works as master only) In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC falling edge represents the MSB. In this mode, the PCM interface supports 256 kHz, 512 kHz, 1024 kHz or 2048 kHz PCM_CLK at 8 kHz PCM_SYNC, and also supports 4096 kHz PCM_CLK at 16 kHz PCM_SYNC. In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC rising edge represents the MSB. In this mode, PCM interface operates with a 256 kHz, 512 kHz, 1024 kHz or 2048 kHz PCM_CLK and an 8 kHz, 50 % duty cycle PCM_SYNC only. Table 17: Pin Definition of PCM Interface Pin Name Pin No. I/O Description Comment PCM_SYNC PCM_CLK 71 73 DIO PCM data frame sync DIO PCM clock In master mode, it is an output signal. In slave mode, it is an RG520F&RG520N_Series_Hardware_Design 53 / 116 5G Module Series PCM_DIN PCM_DOUT 74 76 DI PCM data input DO PCM data output input signal. If unused, keep it open. The module supports 16-bit linear data format. The following figures show the primary modes timing relationship with 8 kHz PCM_SYNC and 2048 kHz PCM_CLK, as well as the auxiliary modes timing relationship with 8 kHz PCM_SYNC and 256 kHz PCM_CLK. 125 s P CM _CLK 1 2 2 5 5 2 5 6 P CM _S YNC P CM _DOUT P CM _DIN MS B LS B MS B MS B LS B MS B Figure 23: Primary Mode Timing 125 s P CM _CLK 1 2 31 32 P CM _S YNC P CM _DOUT P CM _DIN MS B MS B LS B LS B Figure 24: Auxiliary Mode Timing RG520F&RG520N_Series_Hardware_Design 54 / 116 5G Module Series Clock and mode can be configured by AT command, and the default configuration is master mode using short frame sync format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. Please refer to document [6]

about AT+QDAI command for details. The reference design is illustrated as follows:

PCM_CLK PCM_SYNC PCM_DOUT PCM_DIN I2C_SCL I2C_SDA S A B I MICBIAS INP INN LOUTP LOUTN BCLK LRCK DAC ADC SCL SDA Module K 7

. 4 K 7

. 4 1.8 V Codec Figure 25: Reference Circuit of PCM Interface 4.7. UART Interfaces The module provides four UART interfaces: one main UART interface, one debug UART interface, one Bluetooth UART interface*, and one COEX UART interface*. The following shows their features:

Main UART interface supports 115200 bps baud rate by default. This interface is used for AT command communication. Debug UART interface supports 115200 bps baud rate. It is used for Linux console and log output. Bluetooth UART interface supports 115200 bps baud rate. It is used for Bluetooth communication. It supports RTS and CTS hardware flow control. COEX UART interface is used for WWAN/WLAN coexistence mechanism only for Qualcomn platform. Pin definition of the UART interfaces is here as follows:

RG520F&RG520N_Series_Hardware_Design 55 / 116 5G Module Series Table 18: Pin Definition of UART Interfaces Pin Name Pin No. MAIN_TXD MAIN_RXD MAIN_RI*

MAIN_DTR 68 70 100 258 MAIN_DCD*

261 BT_TXD*

BT_RXD*

BT_RTS*

BT_CTS*

DBG_RXD DBG_TXD 59 63 61 62 108 105 I/O DO DI Description Comment Main UART transmit Main UART receive DO Main UART ring indication DI DO Main UART data terminal ready Main UART data carrier detect DO Bluetooth UART transmit 1.8 V power domain. DI DI DO Bluetooth UART receive DTE request to send signal to DCE Connect to DTEs RTS. 1.8 V power domain. DTE clear to send signal from DCE Connect to DTEs CTS. 1.8 V power domain. DI Debug UART receive DO Debug UART transmit 1.8 V power domain. COEX_RXD*

65 DI Coexistence UART receive Only for Qualcomn COEX_TXD*

67 DO Coexistence UART transmit platform. Signal interface used for WWAN/WLAN coexistence mechanism. Pin 65 can be multiplexed into SDX2AP_E911 function. Pin 67 can be multiplexed into SDX2AP_STATUS function. For details, please contact Quectel Technical Supports. The following figure illustrates the reference design for UART interface connection between different modules. RG520F&RG520N_Series_Hardware_Design 56 / 116 5G Module Series BT_TXD BT_UART_RXD Module BT_RXD BT_CTS BT_RTS FC60E BT_UART_TXD BT_UART_CTS BT_UART_RTS Figure 26: UART Interface Connection The module provides 1.8 V UART interfaces. A level translator should be used if the application is equipped with a 3.3 V UART interface. A level translator is recommended. VDD_1V8 VCCA 0.1 F MAIN_RI MAIN_DCD MAIN_DTR MAIN_TXD MAIN_RXD 51 K OE A1 A2 A3 A4 A5 A6 VCCB GND B1 B2 B3 B4 B5 B6 0.1 F VDD_MCU RI_MCU DCD_MCU DTR_MCU TXD_MCU RXD_MCU 51 K Translator Figure 27: Reference Circuit with Translator Chip Another example with transistor circuit is shown as below. For the design of circuits shown in dotted lines, please refer to that shown in solid lines, but pay attention to the direction of connection. RG520F&RG520N_Series_Hardware_Design 57 / 116 5G Module Series Module MAIN_RXD MAIN_TXD MAIN_DTR MAIN_RI MAIN_DCD GND 4.7 K 1 nF VDD_1V8 VDD_1V8 10 K MCU/ARM VDD_1V8 1 nF 10 K 4.7 K VDD_MCU TXD RXD GPIO EINT GPIO GND Figure 28: Reference Circuit with Transistor Circuit NOTE 1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps. 2. Other baud rates of the main UART are under development. 3. Please note that the module BT_CTS is connected to the host CTS, and the module BT_RTS is connected to the host RTS. 4.8. SDIO Interface The module provides one SDIO interface which support SD 3.0 protocol. SDIO interface is used for SD card interface. Table 19: Pin Definition of SD Card Interface Pin Name Pin No. I/O Description Comment SDIO_VDD 60 PI SDIO power supply 1.8/2.85 V configurable input. If unused, connect it to VDD_EXT. SDIO_DATA0 49 DIO SDIO data bit 0 If unused, keep them RG520F&RG520N_Series_Hardware_Design 58 / 116 SDIO_DATA1 SDIO_DATA2 SDIO_DATA3 SDIO_CMD SDIO_CLK 50 51 52 48 47 SDIO_PWR_EN 53 SDIO_PWR_ VSET SDIO_DET 56 55 5G Module Series DIO SDIO data bit 1 open. DIO SDIO data bit 2 DIO SDIO data bit 3 DIO SDIO command DO DO SDIO clock SDIO power supply enable DO SDIO power domain set DI SD hot-plug detect Pull it up to VDD_EXT with a 470 k resistor. If unused, keep it open. The following figure illustrates a reference design of SD card interface with the module. SDIO_VDD_DUAL VDD_2V95 LDO SDIO_PWR_EN LDO VDD_EXT R13 470 K C9 1 F C8 33 pF R12 NM-100 K SDIO_PWR_EN SDIO_PWR_VSET Module SDIO_VDD R7 100 K R8 100 K R9 100 K R10 100 K R11 100 K R1 0R R2 0R R3 0R R4 0R R5 0R R6 0R SDIO_DATA3 SDIO_DATA2 SDIO_DATA1 SDIO_DATA0 SDIO_CLK SDIO_CMD SDIO_DET C1 NM 27pF C2 NM 27pF C3 NM 27pF C4 NM 27pF C5 NM 27pF C6 NM 27pF TVS Array Figure 29: Reference Circuit of SD Card Interface SD Card Connector VDD CD/DAT3 DAT2 DAT1 DAT0 CLK CMD DETECTIVE VSS In SD card interface design, in order to ensure good communication performance with SD card, the following design principles should be complied with:

The voltage range of SD power supply VDD_2V95 is 2.73.6 V and a sufficient current of up to 0.8 A should be provided. SDIO_VDD_DUAL is an SDIO Bus power domain, which can be used for SD card IO signal pull-up. Note that SDIO_VDD is an input pin for the module. To avoid jitter of Bus, resistors from R7 to R11 are needed to be pulled up to SDIO_VDD_DUAL. Value of these resistors are from 10 to 100 k and the recommended value is 100 k. RG520F&RG520N_Series_Hardware_Design 59 / 116 5G Module Series In order to improve signal quality, it is recommended to add 0 resistors R1 to R6 in series between the module and the SD card connector. The bypass capacitors C1 to C6 are reserved and not mounted by default. All resistors and bypass capacitors should be placed close to the SD card connector. For good ESD protection, it is recommended to add a ESD protection components with capacitance value less than 1.2 pF on each SD card pin. It is important to route the SDIO signal traces with ground surrounded. The impedance of SDIO data trace is 50 (10 %). Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals, etc., as well as noisy signals such as clock signals, DC-DC signals, etc. Keep the trace length difference between SDIO_CLK and SDIO_DATA[0:3]/SDIO_CMD less than 2 mm and the total routing length less than 50 mm for SDR104 mode. For other speed modes, the trace length difference between SDIO_CLK and SDIO_DATA[0:3]/SDIO_CMD should be less than 6 mm and the total trace routing length less than 150 mm. Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of SDIO Bus should be less than 5.0 pF. The DETECT pin of SD card connector must be connected to the module when the SD card function is being used. Table 20: SDC Trace Length in the Module Pin No. Pin Name Length (mm) 49 50 51 52 48 47 SDIO_DATA0 SDIO_DATA1 SDIO_DATA2 SDIO_DATA3 SDIO_CMD SDIO_CLK 33.46 33.50 33.15 33.51 34.38 33.57 4.9. ADC Interface The module provides one Analog-to-Digital Converter (ADC) interface. In order to improve the accuracy of ADC, the trace of ADC interface should be surrounded by ground. RG520F&RG520N_Series_Hardware_Design 60 / 116 5G Module Series Table 21: Pin Definition of ADC Interface Pin Name ADC0 Pin No. 241 I/O AI Description General-purpose ADC interface The voltage value on ADC pin can be read via AT+QADC=<port> command:

AT+QADC=0: read the voltage value on ADC0 For more details about the AT command, please refer to document [6]. Table 22: Characteristics of ADC Interface Name Min. ADC0 Voltage Range 0 ADC Input Resistance 398 ADC Resolution ADC Sample Rate

NOTE Typ.

400 64.879 4.8 Max. 1.875 402

Unit V k V MHz 1. The input voltage of ADC should not exceed its corresponding voltage range. It is prohibited to supply any voltage to ADC pin when VBAT is removed. 2. It is recommended to use resistor divider circuit for ADC application. 3. 4.10. SPI Interface The module provides one SPI interface which only supports master mode with a maximum clock frequency of up to 50 MHz. Table 23: Pin Definition of SPI Interface Pin Name Pin No. SPI_CLK 210 I/O DO Description Comment SPI clock 1.8 V power domain. RG520F&RG520N_Series_Hardware_Design 61 / 116 5G Module Series SPI_CS SPI_MISO SPI_MOSI 207 213 204 DO SPI chip select DI SPI master-in slave-out DO SPI master-out slave-in Only master mode is supported. The module provides a 1.8 V SPI interface. Use a level shifter between the module and the host if the application is equipped with a 3.3 V processor or device interface. The following figure shows a reference design. VDD_EXT VCCA 0.1 F SPI_CS SPI_CLK SPI_MOSI SPI_MISO Translator OE A1 A2 A3 A4 NC VCCB GND B1 B2 B3 B4 NC 0.1 F VDD_MCU SPI_CS_N_MCU SPI_CLK_MCU SPI_MOSI_MCU SPI_MISO_MCU Figure 30: Reference Circuit of SPI Interface with a Level Translator 4.11. PCIe Interface The module provides one integrated PCIe (Peripheral Component Interconnect Express) interface, which follows PCI Express Specification Revision 3.0/4.0. The key features of the PCIe interface are mentioned below:

PCI Express Specification Revision 3.0/4.0 Compliance. Data rate at 8 Gbps per lane for PCIe 3.0 and only lane 0 can be 16 Gbps for PCIe 4.0. Can be used to connect to an external Ethernet IC (MAC and PHY) or Wi-Fi IC. Table 24: Pin Definition of PCIe Interface Pin Name Pin No. I/O Description Comment PCIE_REFCLK_P 40 AIO PCIe reference clock (+) PCIE_REFCLK_M 38 AIO PCIe reference clock (-) Requires differential impedance of 85 . One PCIe port is RG520F&RG520N_Series_Hardware_Design 62 / 116 5G Module Series PCIE_TX0_M PCIE_TX0_P PCIE_TX1_M PCIE_TX1_P PCIE_RX0_M PCIE_RX0_P PCIE_RX1_M PCIE_RX1_P 44 46 41 43 32 34 35 37 AO AO AO AO AI AI AI AI PCIe transmit 0 (-) PCIe transmit 0 (+) PCIe transmit 1 (-) PCIe transmit 1 (+) PCIe receive 0 (-) PCIe receive 0 (+) PCIe receive 1 (-) PCIe receive 1 (+) PCIE_CLKREQ_N 36 OD PCIe clock request PCIE_RST_N 39 DIO PCIe reset PCIE_WAKE_N 30 OD PCIe wake up The following figure illustrates the PCIe interface connection. supported. It can be either Gen 3 2-lane or Gen 4 1-lane. 1.8 V power domain. In root complex mode, it is an input signal. In endpoint mode, it is an output signal. 1.8 V power domain. In root complex mode, it is an output signal. In endpoint mode, it is an input signal. 1.8 V power domain. In root complex mode, it is an input signal. In endpoint mode, it is an output signal. RG520F&RG520N_Series_Hardware_Design 63 / 116 5G Module Series VDD_EXT R1 100K R2 100K R3 NM_100K PCIE_CLKREQ_N PCIE_WAKE_N PCIE_RST_N Module PCIE_REFCLK_P PCIE_REFCLK_M PCIE_TX0_M PCIE_TX0_P PCIE_RX0_M PCIE_RX0_P R4 0R R5 0R C1 220 nF C2 220 nF PCIE_CLKREQ_N PCIE_WAKE_N PCIE_RST_N PCIE_REFCLK_P PCIE_REFCLK_M Other PCIE_RX_M PCIE_RX_P PCIE_TX_M PCIE_TX_P C3 220 nF C4 220 nF Figure 31: PCIe Interface Connection The following principles of PCIe interface design should be complied with to meet PCIe specifications. It is important to route the PCIe signal traces as differential pairs with ground surrounded. The differential impedance is 72.597.5 and 85 is recommended. PCIe signals must be protected from noisy signals (clocks, DC-DC, RF and so forth). All other sensitive/high-speed signals and circuits must be routed far away from PCIe traces. For each differential pair, intra-lane length match should be less than 0.7 mm. Inter-lane length match, that is, the trace length matching between the reference clock, Tx, and Rx pairs) is not required. The space between Tx and Rx, and the spacing between PCIe lanes and all other signals, should be larger than 4 times of the trace width. PCIe Tx AC coupling capacitors can be anywhere along the line, but better to be placed close to source or connector side to keep good signal integrity of main route on PCB. Ensure not to stagger the capacitors. This can affect the differential integrity of the design and can create EMI. PCIe Tx AC coupling capacitors should be 220 nF for Gen 3/Gen 4, and 100 nF is recommended for Gen 2/Gen 1 application. In the case of trace serpentines, one line of a differential pair must be routed to make up a length delta, then it must be routed at the source (breakout) this ensures that lines stay differential thereafter. To reduce the probability for layer-to-layer manufacturing variation, minimize layer transitions on the main route (in other words, apply layer transitions only at module breakouts and connectors to ensure minimum layer transitions on the main route). RG520F&RG520N_Series_Hardware_Design 64 / 116 5G Module Series Table 25: PCIe Trace Length in the Module Pin No. Pin Name Length (mm) Length Difference (P-M) (mm)

-0.06

-0.03

-0.01

-0.17 0.03 40 38 46 44 43 41 34 32 37 35 PCIE_REFCLK_P PCIE_REFCLK_M PCIE_TX0_P PCIE_TX0_M PCIE_TX1_P PCIE_TX1_M PCIE_RX0_P PCIE_RX0_M PCIE_RX1_P PCIE_RX1_M 7.52 7.58 12.87 12.90 10.36 10.37 3.92 4.09 4.88 4.85 4.12. Control Signal Relative interfaces pin descriptions are here as follows:

Table 26: Pin Definition of Control Signal Pin Name Pin No. W_DISABLE#

WL_SW_CTRL 114 180 I/O DI DI Description Airplane mode control 76.8 MHz system clock request 4.12.1. W_DISABLE#

The module provides a W_DISABLE# pin to enable or disable airplane mode through hardware operation. W_DISABLE# is pulled up by default, and driving it low will set the module to airplane mode. The RF function can also be enabled or disabled through software AT commands. RG520F&RG520N_Series_Hardware_Design 65 / 116 5G Module Series Table 27: RF Function Status W_DISABLE# Level AT Commands RF Function Status High Level High Level Low Level AT+CFUN=1 AT+CFUN=0 AT+CFUN=4 AT+CFUN=0 AT+CFUN=1 AT+CFUN=4 Enabled Disabled Disabled 4.13. Indication Signal Relative interfaces pin descriptions are here as follows:

Table 28: Pin Definition of Indication Signal Pin Name Pin No. I/O Description Comment NET_MODE 240 STATUS 237 NET_STATUS 243 SLEEP_IND 102 DO DO DO DO Indicates whether the module has registered on 5G network Indicates the modules operation status Indicates the modules network activity status Indicates the modules sleep mode 1.8 V power domain. 4.13.1. Network Status Indication The network indication pins can be used to drive network status indication LEDs. The module provides two network indication pins: NET_MODE and NET_STATUS. The following tables describe pin definition and logic level changes in different network status. RG520F&RG520N_Series_Hardware_Design 66 / 116 5G Module Series Table 29: Working State of the Network Connection Status/Activity Indication Pin Name Status Description NET_MODE Always High Always Low Registered on 5G network Others Flicker slowly (200 ms High/1800 ms Low) Network searching Flicker slowly (1800 ms High/200 ms Low) Idle NET_STATUS Flicker quickly (125 ms High/125 ms Low) Data transfer is ongoing Always High Voice calling Module VBAT Network Indicator 4.7K 2.2K 47K Figure 32: Reference Circuit of the Network Status Indication 4.13.2. STATUS The STATUS pin is an open drain output for indicating the modules operation status. It will output high level when module is powered ON successfully. A reference circuit is shown as below. RG520F&RG520N_Series_Hardware_Design 67 / 116 5G Module Series Module STATUS 4.7K VBAT 2.2K 47K Figure 33: Reference Circuits of STATUS 4.14. IPQ Status and Err Fatal Interface*

The module provides one IPQ status interface and one Err Fatal interface for connection between the module and IPQ. The following tables show the pin definition. Table 30: Pin Definition of IPQ Status and Err Fatal Interface Pin Name Pin No. I/O Description Comment COEX_RXD 65 DI Coexistence UART receive COEX_TXD 67 DO Coexistence UART transmit Only for Qualcomn platform. Signal interface used for WWAN/WLAN coexistence mechanism. Pin 65 can be multiplexed into SDX2AP_E911 function. Pin 67 can be multiplexed into SDX2AP_STATUS function. For details, please contact Quectel Technical Supports. GPIO_32 98 DO Supports time service and repeater functions;

supports 1PPS pulse output and frame synchronization Can be multiplexed into AP2SDX_STATUS function. For details, please contact Quectel Technical Supports. RG520F&RG520N_Series_Hardware_Design 68 / 116 5G Module Series The following figure shows a reference design of the module with IPQ GPIOs. Module COEX_RXD COEX_TXD GPIO_32 IPQ 5018 SDX2AP_E911 SDX2AP_STATUS AP2SDX_STATUS Figure 34: Module with IPQ GPIO Application NOTE IPQ5018 is used by default here. 4.15. MAIN_RI*

AT+QCFG= risignaltype, physical command can be used to configure MAIN_RI behavior. No matter on which port a URC is presented, the URC will trigger the behavior of MAIN_RI pin. NOTE The URC can be outputted via UART port, USB AT port and USB modem port, which can be set by AT+QURCCFG command. The default port is USB AT port. In addition, MAIN_RI behaviors can be configured flexibly. The default behavior of the MAIN_RI is shown as below. Table 31: Behaviors of the RI State Idle Response MAIN_RI keeps at high level. RG520F&RG520N_Series_Hardware_Design 69 / 116 5G Module Series URC MAIN_RI outputs 120 ms low pulse when a new URC return. The MAIN_RI behavior can be changed via AT+QCFG="urc/ri/ring"*. Please refer to document [6] for details. 4.16. Time Service and Repeater Interface*

Time service provides time information for other devices or systems through standard or customized interfaces and protocols. Its basic channels are shortwave, TV signals, cables, networks, satellites, base stations, etc. Repeater is a kind of wireless signal relay device, which amplifies the base station signal and then transmits it to areas with weak signal coverage, expanding the network coverage. Repeater is a kind of wireless signal relay device, which amplifies the base station signal and then transmits it to areas with weak signal coverage, expanding the network coverage. With GNSS time service and repeater functions, the module can provide 1PPS pulse output, and can execute time service through AT commands based on baseline SIB9 system messages. Table 32: Pin Definition of Time Service and Repeater Function Pin Name Pin No. I/O Description Comment GPIO_32 98 DO Supports time service and repeater functions;

supports 1PPS pulse output and frame synchronization 1.8 V power domain. Can be multiplexed into AP2SDX_STATUS function. For details, please contact Quectel Technical Supports. NOTE If GPIO_32 is needed for other purposes, its default function should be disabled in the relevant software configuration. 4.17. GRFC Interfaces*

The module provides two generic RF control interfaces for the control of external antenna tuners. RG520F&RG520N_Series_Hardware_Design 70 / 116 5G Module Series Table 33: Pin Definition of GRFC Interfaces Pin Name Pin No. I/O Default Status Description Comment SDR_GRFC0 171 SDR_GRFC1 174 DO DO PD PD GRFC interface dedicated for external antenna tuner control If unused, keep them open. Table 34: Logic Levels of GRFC Interfaces Parameter VOL VOH Min. 0 1.35 Max. 0.45 1.8 Unit V V Table 35: Truth Table of GRFC Interfaces GRFC1 Level GRFC2 Level Frequency Range (MHz) Band Low Low High High Low High Low High TBD TBD TBD TBD TBD TBD TBD TBD RG520F&RG520N_Series_Hardware_Design 71 / 116 5G Module Series 5 RF Specifications 5.1. Cellular Network 5.1.1. Antenna Interface & Frequency Bands The pin definition is shown below:

Table 36: Pin Definition of Cellular Network Interface for RG520F-NA*/RG520N-NA Pin Name Pin No. I/O Description Comment ANT0 130 AIO Antenna 0 interface:

5G NR: n41 TRX1 & n77/n78 TRX0 LTE: LMB_TRX0 & HB_TRX1 & UHB_TRX0 ANT1 157 AIO

Antenna 1 interface:

5G NR: n41 DRX MIMO & n77/n78 DRX MIMO LTE: LMB_PRX MIMO & HB_DRX MIMO &

UHB_DRX MIMO & LAA_PRX ANT2 166 AIO

Antenna 2 interface:

5G NR: n41 PRX MIMO & n77/n78 PRX MIMO LTE: LMB_DRX MIMO & HB_PRX MIMO &

UHB_PRX MIMO & LAA_DRX 50 impedance ANT3 184 AIO Antenna 3 interface:

5G NR: n41 TRX0 & n77/n78 TRX1 LTE: LMB_TRX1 & HB_TRX0 & UHB_TRX1 RG520F&RG520N_Series_Hardware_Design 72 / 116 5G Module Series Table 37: Pin Definition of Cellular Network Interface for RG520F-EU*/RG520N-EU Pin Name Pin No. I/O Description Comment ANT0 130 AIO Antenna 0 interface:

5G NR: n41 TRX1 & n77/n78 TRX0 LTE: LMB_TRX0 & HB_TRX1 &

UHB_TRX0

- WCDMA: LMB_TRX ANT1 157 AIO

Antenna 1 interface:

5G NR: n41 DRX MIMO & n77/n78 DRX MIMO LTE: LMB_PRX MIMO & HB_DRX MIMO & UHB_DRX MIMO ANT2 166 AIO

Antenna 2 interface:

5G NR: n41 PRX MIMO & n77/n78 PRX MIMO LTE: LMB_DRX MIMO & HB_PRX MIMO & UHB_PRX MIMO 50 impedance ANT3 184 AIO ANT4 ANT5 121 175 AI AI Antenna 3 interface:

5G NR: n41 TRX0 & n77/n78 TRX1 LTE: LMB_TRX1 & HB_TRX0 &

UHB_TRX1

- WCDMA: LMB_DRX Antenna 4 interface:

LTE: B32_PRX (optional) Antenna 5 interface:

LTE: B32_DRX (optional) RG520F&RG520N_Series_Hardware_Design 73 / 116 5G Module Series Table 38: Cellular Network Antenna Mapping for RG520F-NA*/RG520N-NA Antenna WCDMA LTE 5G NR Refarmed n41 n77/n78 LB (MHz) MHB (MHz) n77/n78

(MHz) Pin No. ANT0 ANT1 ANT2 ANT3

LMB_TRX0, HB_TRX1, UHB_TRX0 LMB_PRX MIMO, HB_DRX MIMO, UHB_DRX MIMO, LAA_PRX LMB_DRX MIMO, HB_PRX MIMO, UHB_PRX MIMO, LAA_DRX LMB_TRX1, HB_TRX0, UHB_TRX1 LMB_TRX0, HB_TRX1 LMB_PRX MIMO, HB_DRX MIMO LMB_DRX MIMO, HB_PRX MIMO LMB_TRX1, HB_TRX0 TRX1 TRX0 617960 17102690 33004200 130 DRX MIMO DRX MIMO 617960 17102690 33004200 157 PRX MIMO PRX MIMO 617960 17102690 33004200 166 TRX0 TRX1 617960 17102690 33004200 184 RG520F&RG520N_Series_Hardware_Design 74 / 116 5G Module Series Table 39: Cellular Network Antenna Mapping for RG520F-EU*/RG520N-EU Antenna WCDMA LTE 5G NR Refarmed n41 n77/n78 LB (MHz) MHB (MHz) n77/n78

(MHz) Pin No. ANT0 LMB_TRX ANT1 ANT2

ANT3 LMB_DRX LMB_TRX0, HB_TRX1, UHB_TRX0 LMB_PRX MIMO, HB_DRX MIMO, UHB_DRX MIMO LMB_DRX MIMO, HB_PRX MIMO, UHB_PRX MIMO LMB_TRX1, HB_TRX0, UHB_TRX1 LMB_TRX0, HB_TRX1 LMB_PRX MIMO, HB_DRX MIMO LMB_DRX MIMO, HB_PRX MIMO LMB_TRX1, HB_TRX0 TRX1 TRX0 617960 14272690 33004200 130 DRX MIMO DRX MIMO 617960 14272690 33004200 157 PRX MIMO PRX MIMO 617960 14272690 33004200 166 TRX0 TRX1 617960 14272690 33004200 184 ANT4 ANT5

B32_PRX (Optional) B32_DRX (Optional)

14271496 14271496

121 175 NOTE 1. LTE L/M/H/UHB_TRX1 is activated when 5G NR FDD L/M/H/UHB bands are supported in NSA mode. 2. LTE UHB frequency range: 34003800 MHz. 3. TRX0/1 = TX0/1 + PRX/DRX. 4. LTE LB 4 4 MIMO is optional. Even if it is not required, to support LB + LB CA or EN-DC combinations, ANT0ANT3 must support low bands. RG520F&RG520N_Series_Hardware_Design 75 / 116 5G Module Series 5.1.2. Tx Power The following table shows the RF output power of the module. Table 40: Tx Power Mode Frequency Max. Min. WCDMA WCDMA bands 24 dBm +1/-3 dB (Class 3)

<-50 dBm LTE bands 23 dBm 2 dB (Class 3)

<-40 dBm LTE HPUE bands (B38/B41/B42) 26 dBm 2 dB (Class 2)

<-40 dBm 5G NR bands 23 dBm 2 dB (Class 3)

<-40 dBm 5G NR HPUE bands

(n38/n41/n77/n78) 26 dBm +2/-3 dB (Class 2)

<-40 dBm LTE 5G NR

. NOTE For 5G NR bands, they have different standards for different channel bandwidth, please refer to the specifications as described in Clause 6.3.1 of TS 38.101-1 [2]. 5.1.3. Rx Sensitivity The following table shows conducted RF receiving sensitivity of the module. Table 41: Conducted RF Receiving Sensitivity of RG520F-NA*/RG520N-NA Frequency LTE-FDD B2

(10 MHz) LTE-FDD B4

(10 MHz) LTE-FDD B5

(10 MHz) Receiving Sensitivity (Typ.) Primary Diversity SIMO TBD TBD TBD TBD TBD TBD TBD TBD TBD 3GPP Requirement

(SIMO)

-95.0 dBm

-97.0 dBm

-95.0 dBm RG520F&RG520N_Series_Hardware_Design 76 / 116 5G Module Series LTE-FDD B7

(10 MHz) LTE-FDD B12

(10 MHz) LTE-FDD B13

(10 MHz) LTE-FDD B14

(10 MHz) LTE-FDD B17

(10 MHz) LTE-FDD B25

(10 MHz) LTE-FDD B26

(10 MHz) LTE-FDD B29

(10 MHz) LTE-FDD B30

(10 MHz) LTE-TDD B38

(10 MHz) LTE-TDD B41

(10 MHz) LTE-TDD B42

(10 MHz) LTE-TDD B43

(10 MHz) LTE-TDD B46

(10 MHz) LTE-TDD B48

(10 MHz) LTE-FDD B66

(10 MHz) LTE-FDD B71

(10 MHz) 5G NR FDD n2

(20 MHz) 5G NR FDD n5

(20 MHz) 5G NR FDD n7

(20 MHz) 5G NR FDD n12

(10 MHz) 5G NR FDD n13

(10 MHz) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

-95.0 dBm

-94.0 dBm

-94.0 dBm

-94.0 dBm

-94.0 dBm

-93.5 dBm

-94.5 dBm TBD

-96.0 dBm

-97.0 dBm

-95.0 dBm

-96.0 dBm

-96.0 dBm TBD

-96.0 dBm

-96.5 dBm

-94.2 dBm

-91.8 dBm

-90.8 dBm

-91.8 dBm

-93.8 dBm TBD RG520F&RG520N_Series_Hardware_Design 77 / 116 5G Module Series 5G NR FDD n14

(10 MHz) 5G NR FDD n25

(20 MHz) 5G NR TDD n26

(20 MHz) 5G NR FDD n29

(10 MHz) 5G NR FDD n30

(10 MHz) 5G NR TDD n38

(20 MHz) 5G NR TDD n41

(100 MHz) 5G NR TDD n48

(20 MHz) 5G NR FDD n66

(20 MHz) 5G NR FDD n70

(20 MHz) 5G NR FDD n71

(20 MHz) 5G NR TDD n77

(100 MHz) 5G NR TDD n78

(100 MHz) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Table 42: Conducted RF Receiving Sensitivity of RG520F-EU*/RG520N-EU Frequency WCDMA B1 WCDMA B5 WCDMA B8 LTE-FDD B1

(10 MHz) LTE-FDD B3

(10 MHz) LTE-FDD B5

(10 MHz) Receiving Sensitivity (Typ.) Primary Diversity SIMO TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

-93.8 dBm

-90.3 dBm

-87.6 dBm TBD

-95.8 dBm

-93.8 dBm

-84.7 dBm

-92.9 dBm

-93.3 dBm

-93.8 dBm

-86.0 dBm

-85.1 dBm

-85.6 dBm 3GPP Requirement

(SIMO)

-106.7 dBm

-104.7 dBm

-103.7 dBm

-97.0 dBm

-94.0 dBm

-95.0 dBm RG520F&RG520N_Series_Hardware_Design 78 / 116 5G Module Series LTE-FDD B7

(10 MHz) LTE-FDD B8

(10 MHz) LTE-FDD B20

(10 MHz) LTE-FDD B28

(10 MHz) LTE-TDD B32

(10 MHz) LTE-TDD B38

(10 MHz) LTE-TDD B40

(10 MHz) LTE-TDD B41

(10 MHz) LTE-TDD B42

(10 MHz) LTE-TDD B43

(10 MHz) 5G NR FDD n1

(20 MHz) 5G NR FDD n3

(20 MHz) 5G NR FDD n5

(20 MHz) 5G NR FDD n7

(20 MHz) 5G NR FDD n8

(20 MHz) 5G NR FDD n20

(20 MHz) 5G NR FDD n28

(20 MHz) 5G NR TDD n38

(20 MHz) 5G NR TDD n40

(20 MHz) 5G NR TDD n41

(100 MHz) 5G NR TDD n75

(20 MHz) 5G NR TDD n76

(5 MHz) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

-95.0 dBm

-94.0 dBm

-94.0 dBm

-95.5 dBm TBD

-97.0 dBm

-97.0 dBm

-95.0 dBm

-96.0 dBm

-96.0 dBm

-93.8 dBm

-90.8 dBm

-90.8 dBm

-91.8 dBm

-90.0 dBm

-89.8 dBm

-90.8 dBm

-94.0 dBm

-94.0 dBm

-84.7 dBm

-93.8 dBm

-100 dBm RG520F&RG520N_Series_Hardware_Design 79 / 116 5G Module Series 5G NR TDD n77

(100 MHz) 5G NR TDD n78

(100 MHz) TBD TBD TBD TBD TBD TBD

-85.1 dBm

-85.6 dBm 5.1.4. Reference Design RG520F-NA* and RG520N-NA modules provide 4 RF cellular antenna interfaces for antenna connection. RG520F-EU* and RG520N-EU modules provide 6 RF cellular antenna interfaces for antenna connection. It is recommended to reserve a -type matching circuit for better RF performance, and the -type matching components (C1, R1, and C2) should be placed as close to the antenna as possible. The capacitors are not mounted by default. Module ANT0 ANT5 R1 0R R6 0R C1 NM C9 NM C2 NM C10 NM Figure 35: Reference Circuit for RF Antenna Interfaces

. NOTE 1. Use a -type circuit for all the antenna circuits to facilitate future debugging. 2. Keep the impedance of the cellular antennas (ANT0ANT5) traces as 50 when routing. 3. Keep at least 15 dB isolation between RF antennas to improve the receiving sensitivity, and at least 20 dB isolation between 5G NR UL MIMO antennas. 4. Keep 75 dB isolation between each two antenna traces. 5. Keep digital circuits such as switch mode power supply, (U)SIM card, USB interface, camera module, display connector and SD card away from the antenna traces. RG520F&RG520N_Series_Hardware_Design 80 / 116 5G Module Series 5.2. GNSS The module includes a fully integrated global navigation satellite system solution that supports GPS, GLONASS, BDS, Galileo and QZSS. The module supports standard NMEA-0183 protocol, and outputs NMEA sentences via USB interface

(data update rate: 110 Hz, 1 Hz by default). By default, the modules GNSS function is switched off. It must be switched on via AT command. For more details about GNSS functions technology and configurations, please refer to document [7]. 5.2.1. Antenna Interface & Frequency Bands The following table shows the pin definition, frequency, and performance of GNSS antenna interface. Table 43: Pin Definition of GNSS Antenna Interface Pin Name Pin No. ANT_GNSS 193 I/O AI Description Comment GNSS antenna interface 50 impedance Table 44: GNSS Frequency Type GPS Frequency Unit 1575.42 1.023 (GPS L1) 1176.45 10.23 (GPS L5) GLONASS 1597.51605.8 Galileo BDS QZSS 1575.42 2.046 MHz 1561.098 2.046 1575.42 (L1) 1176.45 (L5) RG520F&RG520N_Series_Hardware_Design 81 / 116 5G Module Series 5.2.2. GNSS Performance Table 45: GNSS Performance Parameter Description Conditions Cold start Sensitivity (GNSS) Reacquisition Autonomous Tracking Cold start Typ. TBD TBD TBD TBD TTFF (GNSS)

@ open sky XTRA enabled TBD Warm start Autonomous TBD

@ open sky XTRA enabled TBD Hot start Autonomous TBD

@ open sky XTRA enabled TBD Unit dBm s Accuracy (GNSS) CEP-50 Autonomous

@ open sky TBD m

. NOTE 1. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes. 2. Re-acquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can fix position again within 3 minutes after loss of lock. 3. Cold start sensitivity: the lowest GNSS signal value at the antenna port on which the module fixes position within 3 minutes after executing cold start commands. RG520F&RG520N_Series_Hardware_Design 82 / 116 5G Module Series 5.2.3. Reference Design The following is the reference circuit of GNSS antenna. VDD 0.1 F 10 R GNSS Antenna 47 nH 100 pF 0 R NM NM Module ANT_GNSS Figure 36: Reference Circuit of GNSS Antenna

. NOTE If the module is designed with a passive antenna, then the VDD circuit is not needed. 1. An external LDO can be selected to supply power according to the active antenna requirement. 2. 3. Keep the characteristic impedance for ANT_GNSS trace as 50 . 4. Place the -type matching components as close to the antenna as possible. 5. Keep Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card away from the antenna traces. 6. Keep 75 dB isolation between GNSS and cellular antenna traces. 7. Keep 15 dB isolation between GNSS and cellular antennas to improve the receiving sensitivity. 5.3. Reference Design of RF Routing For users PCB, the characteristic impedance of all RF traces should be controlled to 50 . The impedance of the RF traces is usually determined by the trace width (W), the materials dielectric constant, height from the reference ground to the signal layer (H), and the space between RF traces and grounds

(S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB structures. RG520F&RG520N_Series_Hardware_Design 83 / 116 5G Module Series Figure 37: Microstrip Design on a 2-layer PCB Figure 38: Coplanar Waveguide Design on a 2-layer PCB Figure 39: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) RG520F&RG520N_Series_Hardware_Design 84 / 116 5G Module Series Figure 40: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:

Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 . The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground. The distance between the RF pins and the RF connector should be as short as possible, and all the right-angle traces should be changed to curved ones. There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, ground vias around RF traces and the reference ground improves RF performance. The distance between the ground vias and RF traces should be more than two times the width of RF signal traces (2 W). For more details about RF layout, please refer to document [8]. RG520F&RG520N_Series_Hardware_Design 85 / 116 5G Module Series 5.4. Antenna Requirements Table 46: Antenna Requirements Antenna Type Requirements GNSS 5G NR/LTE/WCDMA Frequency range 1: 15591606 MHz Frequency range 2: 11661187 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0 dBi Active antenna noise figure: < 1.5 dB Active antenna gain: > -2 dBi Active antenna embedded LNA gain: 17 dB VSWR: 2 Efficiency: > 30 %

Gain: 1 dBi Max input power: 50 W Input impedance: 50 Polarization: Vertical Cable insertion loss:

< 1 dB: LB (<1 GHz)

< 1.5 dB: MB (12.3 GHz)

< 2 dB: HB (> 2.3 GHz)

RG520F&RG520N_Series_Hardware_Design 86 / 116 5G Module Series 5.5. RF Connector Recommendation The receptacle dimensions are illustrated as below. Figure 41: Dimensions of the Receptacles (Unit: mm) RG520F&RG520N_Series_Hardware_Design 87 / 116 5G Module Series The following figure shows the specifications of mating plugs using 0.81 mm coaxial cables. Figure 42: Specifications of Mating Plugs Using 0.81 mm Coaxial Cables (Unit: mm) 5.5.1. Recommended RF Connector for Installation 5.5.1.1. Assemble Coaxial Cable Plug Manually The illustration for plugging in a coaxial cable plug is shown below, = 90 is acceptable, while 90 is not. RG520F&RG520N_Series_Hardware_Design 88 / 116 5G Module Series Figure 43: Plug in a Coaxial Cable Plug The illustration of pulling out the coaxial cable plug is shown below, = 90 is acceptable, while 90 is not. Figure 44: Pull out a Coaxial Cable Plug 5.5.1.2. Assemble Coaxial Cable Plug with Fixture The pictures of installing the coaxial cable plug with a fixture is shown below, = 90 is acceptable, while 90 is not. RG520F&RG520N_Series_Hardware_Design 89 / 116 5G Module Series Figure 45: Install the Coaxial Cable Plug with Fixture 5.5.2. Recommended Manufacturers of RF Connector and Cable For more details, visit https://www.i-pex.com. RG520F&RG520N_Series_Hardware_Design 90 / 116 5G Module Series 6 Electrical Characteristics &

Reliability 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 47: Absolute Maximum Ratings Parameter VBAT_RF/VBAT_BB USB_VBUS Peak Current of VBAT_BB Peak Current of VBAT_RF Voltage on Digital Pins Voltage at ADC0 Min.

-0.5

-0.3

-0.5

-0.5 Max. 6.0 5.5 TBD TBD 2.2 2.2 Unit V V A A V V RG520F&RG520N_Series_Hardware_Design 91 / 116 5G Module Series 6.2. Power Supply Ratings Table 48: Module Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT VBAT_BB and VBAT_RF USB_VBUS USB connection detection The actual input voltages must stay between the minimum and maximum values 3.3 3.8 4.4 V 3.3 5.0 5.25 V 6.3. Power Consumption Table 49: Averaged Power Consumption for the Module Mode Conditions Band/Combinations Current Unit Power-off Power off RF Disabled AT+CFUN=0 (USB 3.0 suspend) AT+CFUN=4 (USB 3.0 suspend) Sleep State Idle State SA FDD PF = 64 (USB 3.0 suspend) SA TDD PF = 64 (USB 3.0 suspend) SA PF = 64 (USB 2.0 active) SA PF = 64 (USB 3.0 active) LTE LB @ 23 dBm LTE LTE MB @ 23 dBm LTE CA LTE HB @ 23 dBm DL 3CA, 256QAM UL 1CA, 256QAM

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A mA mA mA mA mA mA mA mA mA TBD mA RG520F&RG520N_Series_Hardware_Design 92 / 116 5G Module Series Tx power @ 23 dBm 5G NR LB @ 23 dBm 5G NR MB @ 23 dBm 5G NR HB @ 23 dBm 5G NR UHB @ 26 dBm TBD TBD TBD TBD 5G NR UL 2 2 MIMO @ 26 dBm TBD DL 2CA, 256QAM 5G SA

(1 Tx) 5G SA

(2 Tx) TBD TBD TBD TBD TBD mA mA mA mA mA 5G SA CA UL 1CA, 256QAM TBD TBD mA LTE + 5G EN-DC Tx power @ 26 dBm LTE DL, 256QAM LTE UL QPSK NR DL, 256QAM NR UL QPSK LTE Tx Power @ 23 dBm NR Tx Power @ 23 dBm 6.4. Digital I/O Characteristic Table 50: 1.8 V I/O Requirements Parameter Description VIH VIL VOH VOL Min. 1.26

-0.3 Input high voltage Input low voltage Output high voltage 1.35 Output low voltage 0 TBD TBD mA Max. 2.1 0.54 1.8 0.45 Unit V V V V RG520F&RG520N_Series_Hardware_Design 93 / 116 5G Module Series Table 51: (U)SIM 1.8 V I/O Requirements Parameter Description USIM_VDD Power supply Input high voltage Input low voltage Output high voltage 1.44 Output low voltage 0.0 Table 52: (U)SIM 2.95 V I/O Requirements Parameter Description USIM_VDD Power supply Input high voltage Input low voltage Output high voltage 2.36 Output low voltage 0.0 Min. 1.65 1.26

-0.3 Min. 2.7 2.06

-0.3 VIH VIL VOH VOL VIH VIL VOH VOL Max. Unit 1.95 2.1 0.36 1.8 0.4 V V V V V Max. Unit 3.05 3.25 0.59 2.95 0.4 V V V V V 6.5. ESD Protection If the static electricity generated by various ways discharges to the module, the module maybe damaged to a certain extent. Thus, please take proper ESD countermeasures and handling methods. For example, wearing anti-static gloves during the development, production, assembly and testing of the module;

adding ESD protective components to the ESD sensitive interfaces and points in the product design. Table 53: Electrostatics Discharge Characteristics (25 C, 45 % Relative Humidity) Tested Interfaces Contact Discharge Air Discharge Unit VBAT, GND All Antenna Interfaces 5 4 10 8 kV kV RG520F&RG520N_Series_Hardware_Design 94 / 116 5G Module Series Other Interfaces 0.5 1 kV 6.6. Operating and Storage Temperatures Table 54: Operating and Storage Temperatures Parameter Operating Temperature Range 12 Min.

-30 Extended Operating Temperature Range 13

-40 Storage temperature range

-40 Typ.

+25

Max. Unit

+75

+85

+90 C C C 6.7. Thermal Consideration In order to achieve better performance of the module, it is recommended to comply with the following principles for thermal consideration:

On customers PCB design, keep the module away from heat sources, especially high-power components such as processor, power amplifier, and power supply. Do not place large size components in the area where the module is located on the PCB, in order to facilitate the installation of heatsink. Maintain the integrity of the PCB copper layer and place as many thermal vias as possible. Considering the heat dissipation characteristics of the module, the heatsink should be attached on the top of the module. The heatsink should be designed with adequate fins to dissipate heat, and TIM (Thermal Interface Material) in contact between the heat sink and the module should have high thermal conductivity, good softness and good wettability. The heatsink should be fastened with four screws to ensure that it is in close contact with the module, so as to prevent the heatsink from falling off during the drop, vibration test, and transportation. The following figures show the placement and fixing of the heat sink for reference. 12 To meet this operating temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module can meet 3GPP specifications. 13 To meet this extended temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module remains the ability to establish and maintain functions such as voice, SMS, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may undergo a reduction in value, exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again. RG520F&RG520N_Series_Hardware_Design 95 / 116 5G Module Series Figure 46: Heatsink Placement Figure 47: Heatsink Fixing The module offers the best performance when the internal IC chips stay below its maximum junction temperature, When IC reaches or exceeds this temperature, the module may still work but the performance and function (such as RF output power, data rate, etc.) will be affected to a certain extent. Therefore, the thermal design should be maximally optimized to make sure all internal ICs temperature always maintains below the maximum junction temperature with enough margin. RG520F&RG520N_Series_Hardware_Design 96 / 116 5G Module Series 7 Mechanical Information This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are 0.2 mm unless otherwise specified. 7.1. Mechanical Dimensions Pin 1 Figure 48: Module Top and Side Dimensions (Unit: mm) RG520F&RG520N_Series_Hardware_Design 97 / 116 5G Module Series Figure 49: Module Bottom Dimensions (Bottom View, Unit: mm) NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard. RG520F&RG520N_Series_Hardware_Design 98 / 116 5G Module Series 7.2. Recommended Footprint Pin 1 Figure 50: Recommended Footprint

. NOTE 1. Keep at least 3 mm between the module and other components on the motherboard to improve soldering quality and maintenance convenience. 2. To keep the reliability of the mounting and soldering, keep the motherboard thickness as at least 1.2 mm. RG520F&RG520N_Series_Hardware_Design 99 / 116 5G Module Series 7.3. Top and Bottom Views Figure 51: Top & Bottom Views of RG520N Series Figure 52: Top & Bottom Views of RG520F Series NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. RG520F&RG520N_Series_Hardware_Design 100 / 116 5G Module Series 8 Storage, Manufacturing & Packaging 8.1. Storage Conditions The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 5 C and the relative humidity should be 3560 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in recommended storage condition. 3. The floor life of the module is 168 hours 14 in a plant where the temperature is 23 5 C and relative humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g. a drying cabinet). 4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under the following circumstances:

The module is not stored in recommended storage condition;

Violation of the third requirement above occurs;

Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;

Before module repairing. 5. If needed, the pre-baking should follow the requirements below:

The module should be baked for 8 hours at 120 5 C;

All modules must be soldered to PCB within 24 hours after the baking, otherwise they should be put in a dry environment such as in a drying oven. 14 This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to, or are not sure to conform to IPC/JEDEC J-STD-033. And do not remove the packages of tremendous modules if they are not ready for soldering. RG520F&RG520N_Series_Hardware_Design 101 / 116 5G Module Series NOTE 1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to the air is forbidden. 2. Take out the module from the package and put it on high-temperature-resistant fixtures before baking. All modules must be soldered to PCB within 24 hours after the baking, otherwise put them in the drying oven. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure. 3. Pay attention to ESD protection, such as wearing anti-static gloves, when touching the modules. 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. Apply proper force on the squeegee to produce a clean stencil surface on a single pass. To guarantee module soldering quality, the thickness of stencil for the module is recommended to be 0.150.18 mm. For more details, please refer to document [9]. The peak reflow temperature should be 235246 C, with 246 C as the absolute maximum reflow temperature. To avoid damage to the module caused by repeated heating, it is strongly recommended that the module should be mounted only after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. T em p. (C ) 246 235 217 200 150 100 S oak Z one A M ax slope: 1~3 C /s R eflow Z one M ax slope:

2~3 C /s C C ooling dow n slope:

-1.5 ~ -3 C /s B D Figure 53: Recommended Reflow Soldering Thermal Profile RG520F&RG520N_Series_Hardware_Design 102 / 116 5G Module Series Table 55: Recommended Thermal Profile Parameters Factor Soak Zone Max slope Recommendation 1 to 3 C/s Soak time (between A and B: 150 C and 200 C) 70 to 120 s Reflow Zone Max slope Reflow time (D: over 217C) Max temperature Cooling down slope Reflow Cycle Max reflow cycle NOTE 2 to 3 C/s 40 to 70 s 235 to 246 C

-1.5 to -3 C/s 1 1. If a conformal coating is necessary for the module, do NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module. 2. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the module. 3. Due to the complexity of the SMT process, please contact Quectel Technical Supports in advance for any situation that you are not sure about, or any process (e.g. selective soldering, ultrasonic soldering) that is not mentioned in document [9]. 8.3. Packaging Specifications The module adopts carrier tape packaging and details are as follow:

8.3.1. Carrier Tape Dimension details are as follow:

RG520F&RG520N_Series_Hardware_Design 103 / 116 5G Module Series Figure 54: Carrier Tape Dimension Drawing Table 56: Carrier Tape Dimension Table (Unit: mm) W 72 P 56 T 0.4 A0 B0 44.7 41.7 K0 4.2 K1 5.2 F E 34.2 1.75 8.3.2. Plastic Reel Figure 55: Plastic Reel Dimension Drawing Table 57: Plastic Reel Dimension Table (Unit: mm) D1 380 D2 180 W 72.5 RG520F&RG520N_Series_Hardware_Design 104 / 116 5G Module Series 8.3.3. Packaging Process Place the packaged plastic reel, humidity indicator card and desiccant bag into a vacuum bag, then vacuumize it. Place the module into the carrier tape and use the cover tape to cover them; then wind the heat-sealed carrier tape to the plastic reel and use the protective tape for protection. One plastic reel can load 200 modules. Place the vacuum-packed plastic reel into a pizza box. Put 4 pizza boxes into 1 carton and seal it. One carton can pack 800 modules. Figure 56: Packaging Process RG520F&RG520N_Series_Hardware_Design 105 / 116 5G Module Series 9 Appendix A References Table 58: Related Documents Document Name

[1] Quectel_RG520N-EU_CA&EN-DC_Features

[2] Quectel_RG520N-NA_CA&EN-DC_Features

[3] Quectel_RG520F-EU_CA&EN-DC_Features

[4] Quectel_RG520F-NA_CA&EN-DC_Features

[5] Quectel_5G_EVB_User_Guide

[6] Quectel_RG520N&RG5x0F&RM5x0N&RM5x0F_Series_AT_Commands_Manual

[7] Quectel_RG520N&RG5x0F&RM5x0N&RM5x0F_Series_GNSS_Application_Note

[8] Quectel_RF_Layout_Application_Note

[9] Quectel_Module_Secondary_SMT_Application_Note

[10] Quectel_RG520F&RG520N_Series_Reference_Design Table 59: Terms and Abbreviations Abbreviation Description 1PPS ADC 1 Pulse Per Second Analog-to-Digital Converter AMR-WB Adaptive Multi-Rate Wideband AON AP bps Active Optical Network Application Processor Bits Per Second RG520F&RG520N_Series_Hardware_Design 106 / 116 5G Module Series BPSK CA CTS DAI DCE Binary Phase Shift Keying Carrier Aggregation Clear To Send Digital Audio Interface Data Communications Equipment DC-HSDPA Dual-carrier High Speed Downlink Packet Access DDR DFOTA DL DRX DRX DTE DTR ESD FDD FEM Double Data Rate Delta Firmware Upgrade Over The Air Downlink Discontinuous Reception Diversity Receive Data Terminal Equipment Data Terminal Ready Electrostatic Discharge Frequency Division Duplex Front-End Module GLONASS Global Navigation Satellite System (Russia) GNSS GPS GRFC HB HPUE HSDPA HSPA HSUPA Global Navigation Satellite System Global Positioning System General RF Control High Band High Power User Equipment High Speed Downlink Packet Access High Speed Packet Access High Speed Uplink Packet Access RG520F&RG520N_Series_Hardware_Design 107 / 116 5G Module Series IC I2C I2S I/O LAA LB LED LGA LMHB LNA LTE MAC MB MHB Integrated Circuit Inter-Integrated Circuit Inter-IC Sound Input/Output License Assisted Access Low Band Light Emitting Diode Land Grid Array Low/Middle/High Band Low Noise Amplifier Long Term Evolution Media Access Control Middle Band Middle/High Band MIMO Multiple Input Multiple Output MO MT NR NSA PA PAP PC PCB PCIe PCM Mobile Originated Mobile Terminated New Radio Non-Stand Alone Power Amplifier Password Authentication Protocol Personal Computer Printed Circuit Board Peripheral Component Interconnect Express Pulse Code Modulation RG520F&RG520N_Series_Hardware_Design 108 / 116 5G Module Series PDA PDU PHY PRX QAM QPSK QZSS RF RGMII RHCP Rx SA SCS SD SIB SIMO SMD SMS SoC SPI STB TDD TRX Tx Personal Digital Assistant Protocol Data Unit Physical Layer Primary Receive Quadrature Amplitude Modulation Quadrature Phase Shift Keying Quasi-Zenith Satellite System Radio Frequency Reduced Gigabit Media Independent Interface Right Hand Circularly Polarized Receive Stand Alone Sub-Carrier Space Secure Digital System Information Block Single Input Multiple Output Surface Mount Device Short Message Service System on a Chip Serial Peripheral Interface Set Top Box Time Division Duplexing Transmit & Receive Transmit UART Universal Asynchronous Receiver/Transmitter RG520F&RG520N_Series_Hardware_Design 109 / 116 5G Module Series UHB UL UMTS URC USB

(U)SIM VBAT VIHmax VIHmin VILmax VILmin Vmax Vmin Vnom VOHmax VOHmin VOLmax VSWR Ultra High Band Uplink Universal Mobile Telecommunications System Unsolicited Result Code Universal Serial Bus Universal Subscriber Identity Module Voltage at Battery (Pin) Maximum High-level Input Voltage Minimum High-level Input Voltage Maximum Low-level Input Voltage Minimum Low-level Input Voltage Maximum Voltage Minimum Voltage Nominal Voltage Maximum High-level Output Voltage Minimum High-level Output Voltage Maximum Low-level Output Voltage Voltage Standing Wave Ratio WCDMA Wideband Code Division Multiple Access WLAN WWAN Wireless Local Area Network Wireless Wide Area Network RG520F&RG520N_Series_Hardware_Design 110 / 116 5G Module Series 10 Appendix B Operating Frequency Table 60: Operating Frequencies (5G) 5G n1 n2 n3 n5 n7 n8 n12 n13 n14 n18 n20 n24 n25 n26 n28 n29 n30 n34 n38 Duplex Mode Uplink Operating Band Downlink Operating Band Unit FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD FDD SDL FDD TDD TDD 19201980 18501910 17101785 824849 21102170 19301990 18051880 869894 25002570 26202690 880915 699716 777787 788798 815830 832862 925960 729746 746756 758768 860875 791821 1626.51660.5 15251559 18501915 19301995 814849 703748

23052315 20102025 25702620 859894 758803 717728 23502360 20102025 25702620 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz RG520F&RG520N_Series_Hardware_Design 111 / 116 5G Module Series Duplex Mode Uplink Operating Band Downlink Operating Band Unit TDD TDD TDD TDD TDD TDD TDD TDD TDD FDD FDD SDL FDD FDD FDD SDL SDL TDD TDD TDD 18801920 23002400 24962690 51505925 58555925 35503700 14321517 14271432 18801920 23002400 24962690 51505925 58555925 35503700 14321517 14271432 2483.52495 2483.52495 19202010 17101780

21102200 21102200 738758 16951710 19952020 663698 14271470

33004200 33003800 44005000 SUL 17101785 SUL 880915 SUL 832862 SUL SUL 703748 19201980 617652 14751518 14321517 14271432 33004200 33003800 44005000

MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 5G n39 n40 n41 n46 n47 n48 n50 n51 n53 n65 n66 n67 n70 n71 n74 n75 n76 n77 n78 n79 n80 n81 n82 n83 n84 RG520F&RG520N_Series_Hardware_Design 112 / 116 5G Module Series Duplex Mode Uplink Operating Band Downlink Operating Band Unit 5G n85 n86 n89 n90 n91 n92 n93 n94 n95 n96 n97 n98 n99 n257 n258 n260 n261 FDD 698716 728746 SUL SUL TDD FDD FDD FDD FDD SUL TDD SUL SUL SUL

17101780 824849 24962690 832862 832862 880915 880915 20102025 59257125 23002400 18801920 1626.51660.5

24962690 14271432 14321517 14271432 14321517

59257125

26.5029.50 26.5029.50 24.2527.50 24.2527.50 37.0040.00 37.0040.00 27.5028.35 27.5028.35 Table 61: Operating Frequencies (2G + 3G + 4G) 2G

3G B1 4G Duplex Mode Uplink Downlink B1 FDD 19201980 21102170 PCS1900 B2/BC1 B2 FDD 18501910 19301990 DCS1800 B3 B3 FDD 17101785 18051880

B4 B4 FDD 17101755 21102155 GSM850 B5/BC0 B5 FDD 824849 869894 RG520F&RG520N_Series_Hardware_Design 113 / 116 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz GHz GHz GHz GHz Unit MHz MHz MHz MHz MHz 5G Module Series

B6 B7

FDD 830840 875885 B7 FDD 25002570 26202690 EGSM900 B8 B8 FDD 880915 925960 MHz MHz MHz

B9 B10 B11 B12 B13 B14

B19 B20 B21 B22

B25 B26

B9 FDD 1749.91784.9 1844.91879.9 MHz B10 FDD 17101770 21102170 MHz B11 FDD 1427.91447.9 1475.91495.9 MHz B12 FDD 699716 729746 B13 FDD 777787 746756 B14 FDD 788798 758768 B17 FDD 704716 734746 B18 FDD 815830 860875 B19 FDD 830845 875890 B20 FDD 832862 791821 MHz MHz MHz MHz MHz MHz MHz B21 FDD 1447.91462.9 1495.91510.9 MHz B22 FDD 34103490 35103590 B24 FDD 1626.51660.5 15251559 B25 FDD 18501915 19301995 B26 FDD 814849 859894 B27 FDD 807824 852869 B28 FDD 703748 758803 B29 FDD 15

717728 B30 FDD 23052315 23502360 MHz MHz MHz MHz MHz MHz MHz MHz B31 FDD 452.5457.5 462.5467.5 MHz B32 FDD 15

14521496 MHz MHz B33 B33 TDD 19001920 19001920 15 Restricted to E-UTRA operation when carrier aggregation is configured. The downlink operating band is paired with the uplink operating band (external) of the carrier aggregation configuration that is supporting the configured Pcell. RG520F&RG520N_Series_Hardware_Design 114 / 116 5G Module Series B34 B35 B36 B37 B38 B39 B40

B34 TDD 20102025 20102025 B35 TDD 18501910 18501910 B36 TDD 19301990 19301990 B37 TDD 19101930 19101930 B38 TDD 25702620 25702620 B39 TDD 18801920 18801920 B40 TDD 23002400 23002400 B41 TDD 24962690 24962690 B42 TDD 34003600 34003600 B43 TDD 36003800 36003800 B44 TDD 703803 703803 B45 TDD 14471467 14471467 B46 TDD 51505925 51505925 B47 TDD 58555925 58555925 B48 TDD 35503700 35503700 B50 TDD 14321517 14321517 B51 TDD 14271432 14271432 B52 TDD 33003400 33003400 B65 FDD 19202010 21102200 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz B66 FDD 17101780 21102200 16 MHz B67 FDD 15

738758 B68 FDD 698728 753783 B69 FDD 15

25702620 B70 FDD 17 16951710 19952020 MHz MHz MHz MHz

16 The range 21802200 MHz of the DL operating band is restricted to E-UTRA operation when carrier aggregation is configured. 17 The range 20102020 MHz of the DL operating band is restricted to E-UTRA operation when carrier aggregation is configured and TX-RX separation is 300 MHz. The range 20052020 MHz of the DL operating band is restricted to E-UTRA operation when carrier aggregation is configured and TX-RX separation is 295 MHz. RG520F&RG520N_Series_Hardware_Design 115 / 116 5G Module Series

B71 FDD 663698 617652 B72 FDD 451456 461466 B73 FDD 450455 460465 B74 FDD 14271470 14751518 B75 FDD 15 B76 FDD 15

14321517 14271432 B85 FDD 698716 728746 B87 FDD 410415 420425 B88 FDD 412417 422427 MHz MHz MHz MHz MHz MHz MHz MHz MHz RG520F&RG520N_Series_Hardware_Design 116 / 116 OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.31 (h) and (k): The host manufacturer is responsible for additional testing to verify compliance as a composite system. When testing the host device for compliance with Part 15 Subpart B, the host manufacturer is required to show compliance with Part 15 Subpart B while the transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation should confirm that the module's intentional emissions are compliant (i.e. fundamental and out of band emissions). The host manufacturer must verify that there are no additional unintentional emissions other than what is permitted in Part 15 Subpart B or emissions are complaint with the transmitter(s) rule(s). The Grantee will provide guidance to the host manufacturer for Part 15 B requirements if needed. Important Note notice that any deviation(s) from the defined parameters of the antenna trace, as described by the instructions, require that the host product manufacturer must notify to Quectel that they wish to change the antenna trace design. In this case, a Class II permissive change application is required to be filed by the USI, or the host manufacturer can take responsibility through the change in FCC ID (new application) procedure followed by a Class II permissive change application End Product Labeling When the module is installed in the host device, the FCC/IC ID label must be visible through a window on the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a second label must be placed on the outside of the final device that contains the following text: Contains FCC ID: XMR2022RG520NNA Contains IC: 10224A-2022RG520NA. The FCC ID/IC ID can be used only when all FCC/IC compliance requirements are met. Antenna

(1) The antenna must be installed such that 20 cm is maintained between the antenna and users,

(2) The transmitter module may not be co-located with any other transmitter or antenna. In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC/IC authorization. To comply with FCC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:

- Reorient or relocate the receiving antenna.

- Increase the separation between the equipment and receiver

- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

- Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. List of applicable FCC rules This module has been tested and found to comply with part 22, part 24, part 27, part 90, part 96 requirements for Modular Approval. The modular transmitter is only FCC authorized for the specific rule parts (i.e., FCC transmitter rules) listed on the grant, and that the host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. If the grantee markets their product as being Part 15 Subpart B compliant (when it also contains unintentional-

radiator digital circuity), then the grantee shall provide a notice stating that the final host product still requires Part 15 Subpart B compliance testing with the modular transmitter installed. This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. Radiation Exposure Statement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator &

your body. Industry Canada Statement This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions:

(1) This device may not cause interference; and

(2) This device must accept any interference, including interference that may cause undesired operation of the device. Le prsent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorise aux deux conditions suivantes:

(1) l'appareil ne doit pas produire de brouillage, et

(2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement."

Radiation Exposure Statement This equipment complies with IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator & your body Dclaration d'exposition aux radiations:

Cet quipement est conforme aux limites d'exposition aux rayonnements ISED tablies pour un environnement non contrl. Cet quipement doit tre install et utilis avec un minimum de 20 cm de distance entre la source de rayonnement et votre corps. This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. Cet appareil est conu uniquement pour les intgrateurs OEM dans les conditions suivantes: (Pour utilisation de dispositif module) 1) L'antenne doit tre installe de telle sorte qu'une distance de 20 cm est respecte entre l'antenne et les utilisateurs, et 2) Le module metteur peut ne pas tre complant avec un autre metteur ou antenne. Tant que les 2 conditions ci-dessus sont remplies, des essais supplmentaires sur l'metteur ne seront pas ncessaires. Toutefois, l'intgrateur OEM est toujours responsable des essais sur son produit final pour toutes exigences de conformit supplmentaires requis pour ce module install. IMPORTANT NOTE:

In the event that these conditions cannot be met (for example certain laptop configurations or colocation with another transmitter), then the Canada authorization is no longer considered valid and the IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate Canada authorization. NOTE IMPORTANTE:

Dans le cas o ces conditions ne peuvent tre satisfaites (par exemple pour certaines configurations d'ordinateur portable ou de certaines co-localisation avec un autre metteur), l'autorisation du Canada n'est plus considr comme valide et l'ID IC ne peut pas tre utilis sur le produit final. Dans ces circonstances, l'intgrateur OEM sera charg de rvaluer le produit final (y compris l'metteur) et l'obtention d'une autorisation distincte au Canada. End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed such that 20 cm may be maintained between the antenna and users. The final end product must be labeled in a visible area with the following: Contains IC: 10224A-2020RM502Q. Plaque signaltique du produit final Ce module metteur est autoris uniquement pour une utilisation dans un dispositif o l'antenne peut tre installe de telle sorte qu'une distance de 20cm peut tre maintenue entre l'antenne et les utilisateurs. Le produit final doit tre tiquet dans un endroit visible avec l'inscription suivante: "Contient des IC: 10224A-2020RM502Q". Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. Manuel d'information l'utilisateur final L'intgrateur OEM doit tre conscient de ne pas fournir des informations l'utilisateur final quant la faon d'installer ou de supprimer ce module RF dans le manuel de l'utilisateur du produit final qui intgre ce module. Le manuel de l'utilisateur final doit inclure toutes les informations rglementaires requises et avertissements comme indiqu dans ce manuel.

 

 

 

 

 

 

 

 

 

 

ROECCTEL RG520N-NA Q1=A00K DB RG520NNADB-M28-SGASA FCC ID: XMR2022RG520NNA IC: 10224A-2022RG520NA SN:MP34567890XXxxXX IMEI:8634567890XXxXxXX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Quectel Wireless Solutions Company Limited CIIPC Cover Letter Date: 2022-10-20 We Name: Quectel Wireless Solutions Company Limited Address: Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Declare that:

Product:

FCC ID:

Grant Date:

Model No.:

5G Sub-6 GHz LGA Module XMR2022RG520NNA 2022/08/24 RG520N-NA hereby requests to enable the 5G NR n48 band via software. ________________ Name: Jean Hu Email: Jean.Hu@Quectel.com Date: 2022-10-20

 

 

Quectel Wireless Solutions Company Limited Confidentiality Request Letter Federal Communications Commission Authorization and Evaluation Division FCC ID: XMR2022RG520NNA Pursuant to Sections 0.457 and 0.459 of the Commissions Rules, we hereby request confidential treatment of information accompanying this application as outlined below:

1. Operational Description 2. Tune up procedure The above materials contain trade secrets and proprietary information not customarily released to the public. The public disclosure of these matters might be harmful to the applicant and provide unjustified benefits to its competitors. The applicant understands that pursuant to Rule 0.457, disclosure of this application and all accompanying documentation will not be made before the date of the Grant for this application. Sincerely, _________________ Name: Jean Hu Email: Jean.Hu@Quectel.com Date: 2022-10-20

 

 

Quectel Wireless Solutions Company Limited Declaration of Authorization We Name: Quectel Wireless Solutions Company Limited Address: Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Declare that:

Name Representative of agent: Marlin Chen Agent Company name:

Address:

MRT Technology (Suzhou) Co., Ltd D8 Building, Youxin Industrial Park, No.2 Tian'edang Rd., Wuzhong Economic Development Zone Suzhou China City:

Country:

is authorized to apply for Certification of the following product(s):

5G Sub-6 GHz LGA Module XMR2022RG520NNA RG520N-NA Product:

FCC ID:

Model No.:

Sincerely, ________________ Name: Jean Hu Email: Jean.Hu@Quectel.com Date: 2022-10-20

 

 

Quectel Wireless Solutions Company Limited Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Request for Modular/Limited Modular Approval Date: 2022.10.20 Subject: Manufacturers Declaration for

- Modular Approval

- Split Modular Approval

- Limited Modular Approval - Limited Split Modular Approval Confidentiality Request for: XMR2022RG520NNA 8 Basic Requirements FCC Part 15.212(a)(1) For Items Marked NO(*), the Limited Module Description Must be Filled Out on the Following Pages Modular Approval Requirement 1. The modular transmitter must have its own RF shielding. This is intended to ensure that the module does not have to rely upon the shielding provided by the device into which it is installed in order for all modular transmitter emissions to comply with FCC limits. It is also intended to prevent coupling between the RF circuitry of the module and any wires or circuits in the device into which the module is installed. Such coupling may result in non-compliant operation. The physical crystal and tuning capacitors may be located external to the shielded radio elements. 15.212(a)(1)(i) Requirement Met

- YES - NO(*) Details: <example The module contains a metal shield which covers all RF components and circuitry. The shield is located on the top of the board next to antenna connector>

2. The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with FCC requirements under conditions of excessive data rates or over-modulation. 15.212(a)(1)(ii)

- YES - NO(*) Details: <example Data to the modulation circuit is buffered as described in the operational description provided with the application>

3. The modular transmitter must have its own power supply regulation on the module. This is intended to ensure that the module will comply with FCC requirements regardless of the design of the power supplying circuitry in the device into which the module is installed. 15.212(a)(1)(iii)

- YES - NO(*) Details: <example The module contains its own power supply regulation. Please refer to schematic filed with this application>

4. The modular transmitter must comply with the antenna and transmission system requirements of 15.203, 15.204(b), 15.204(c), 15.212(a), and 2.929(b). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph 15.212(b). 15.212(a)(1)(iv)

- YES - NO(*) Details: <example The module connects to its antenna using an UFL connector which is considered a non-

standard connector. A list of antennas tested and approved with this device may be found in users manual provided with the application>

5. The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing. This is intended to demonstrate that the module is capable of complying with Part 15 emission limits regardless of the device into which it is eventually installed. Unless the transmitter module will be battery powered, it must comply with the AC line conducted requirements found in Section 15.207. AC or DC power lines and data input/output lines connected to the module must not contain ferrites, unless they will be marketed with the module (see Section 15.27(a)). The length of these lines shall be length typical of actual use or, if that length is unknown, at least 10 centimeters to insure that there is no coupling between the case of the module and supporting equipment. Any accessories, peripherals, or support equipment connected to the module during testing shall be unmodified or commercially available (see Section 15.31(i)). 15.212(a)(1)(v)

- YES - NO(*) Details: <example The module was tested stand-alone as shown in test setup photographs filed with this application>

6. The modular transmitter must be labeled with its own FCC ID number, or use an electron display (see KDB Publication 784748). Modular Approval Requirement Requirement Met If using a permanently affixed label with its own FCC ID number, if the FCC ID is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains Transmitter Module FCC ID:

XMR2022RG520NNA or Contains FCC ID: XMR2022RG520NNA Any similar wording that expresses the same meaning may be used. The Grantee may either provide such a label, an example of which must be included in the application for equipment authorization, or, must provide adequate instructions along with the module which explain this requirement. In the latter case, a copy of these instructions must be included in the application for equipment authorization. If the modular transmitter uses an electronic display of the FCC identification number, the information must be readily accessible and visible on the modular transmitter or on the device in which it is installed. If the module is installed inside another device, then the outside of the device into which the module is installed must display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains FCC certified transmitter module(s). Any similar wording that expresses the same meaning may be used. The user manual must include instructions on how to access the electronic display. A copy of these instructions must be included in the application for equipment authorization. 15.212(a)(1)(vi)

- YES - NO(*) Details: <example There is a label on the module as shown in the labeling exhibit filed with this application. Host specific labeling instructions are shown in the installation manual .filed with this application.>

7. The modular transmitter must comply with all specific rule or operating requirements applicable to the transmitter, including all the conditions provided in the integration instructions by the grantee. A copy of these instructions must be included in the application for equipment authorization. For example, there are very strict operational and timing requirements that must be met before a transmitter is authorized for operation under Section 15.231. For instance, data transmission is prohibited, except for operation under Section 15.231(e), in which case there are separate field strength level and timing requirements. Compliance with these requirements must be assured. 15.212(a)(1)(vii)

- YES - NO(*) Details: <example The module complies with FCC Part 15C requirements. Instructions to the OEM installer are provided in the installation manual filed with this application.>

8. The modular transmitter must comply with any applicable RF exposure requirements. For example, FCC Rules in Sections 2.1091, 2.1093 and specific Sections of Part 15, including 15.319(i), 15.407(f), 15.253(f) and 15.255(g), require that Unlicensed PCS, UNII and millimeter wave devices perform routine environmental evaluation for RF Exposure to demonstrate compliance. In addition, spread spectrum transmitters operating under Section 15.247 are required to address RF Exposure compliance in accordance with Section 15.247(b)(4). Modular transmitters approved under other Sections of Part 15, when necessary, may also need to address certain RF Exposure concerns, typically by providing specific installation and operating instructions for users, installers and other interested parties to ensure compliance. 15.212(a)(1)(viii) Details: < The module meets RF exposure in mobile configuration.>

- YES - NO(*) 070920-02b Limited Module Description When Applicable

* If a module does NOT meet one or more of the above 8 requirements, the applicant may request Limited Modular Approval

(LMA). This Limited Modular Approval (LMA) is applied with the understanding that the applicant will demonstrate and will retain control over the final installation of the device, such that compliance of the end product is always assured. The operating condition(s) for the LMA; the module is only approved for use when installed in devices produced by grantee. A description regarding how control of the end product, into which the module will be installed, will be maintained by the applicant/manufacturer, such that full compliance of the end product is always ensured should be provided here. Details: <example - N/A>

Software Considerations KDB 594280 / KDB 442812 (One of the following 2 items must be applied) Requirement 1. For non-Software Defined Radio transmitter modules where software is used to ensure compliance of the device, technical description must be provided about how such control is implemented to ensure prevention of third-party modification; see KDB Publication 594280. Requirement Met

- Provided in Separate Cover Letter

- N/A Details: <example The firmware of the device can not be modified or adjusted by the end user as described in a separate cover letter filed with this application. >

2. For Software Defined Radio (SDR) devices, transmitter module applications must provide a software security description; see KDB Publication 442812.

- Provided in Separate Cover Letter

- N/A Details: <example N/A>

Split Modular Requirements Requirement 1. For split modular transmitters, specific descriptions for secure communications between front-end and control sections, including authentication and restrictions on third-party modifications; also, instructions to third-party integrators on how control is maintained. Provided in Manual

- Provided in Separate Cover Letter

- N/A Details: <example N/A >

070920-02b OEM Integration Manual Guidance KDB 996369 D03 Section 2 Clear and Specific Instructions Describing the Conditions, Limitations, and Procedures for third-parties to use and/or integrate the module into a host device. Requirement Is this module intended for sale to third parties?

- YES

- No, If No, and LMA applies, the applicant can optionally choose to not make the following detailed info public. However there still needs to be basic integration instructions for a users manual and the information below must still be included in the operational description. If the applicant wishes to keep this info confidential, this will require a separate statement cover letter explaining the module is not for sale to third parties and that integration instructions are internal confidential documents. Items required to be in the manual See KDB 996369 D03, Section 2 As of May 1, 2019, the FCC requires ALL the following information to be in the installation manual. Modular transmitter applicants should include information in their instructions for all these items indicating clearly when they are not applicable. For example information on trace antenna design could indicate Not Applicable. Also if a module is limited to only a grantees own products and not intended for sale to third parties, the user instructions may not need to be detailed and the following items can be placed in the operational description, but this should include a cover letter as cited above. 1. List of applicable FCC rules. KDB 996369 D03, Section 2.2 a. Only list rules related to the transmitter. 2. Summarize the specific operational use conditions. KDB 996369 D03, Section 2.3 a. Conditions such as limits on antennas, cable loss, reduction of power for point to 3. Limited Module Procedures. KDB 996369 D03, Section 2.4 point systems, professional installation info a. Describe alternative means that the grantee uses to verify the host meets the necessary limiting conditions b. When RF exposure evaluation is necessary, state how control will be maintained such that compliance is ensured, such as Class II for new hosts, etc. 4. Trace antenna designs. KDB 996369 D03, Section 2.5 a. Layout of trace design, parts list, antenna, connectors, isolation requirements, tests for design verification, and production test procedures for ensuring compliance. If confidential, the method used to keep confidential must be identified and information provided in the operational description. 5. RF exposure considerations. KDB 996369 D03, Section 2.6 a. Clearly and explicitly state conditions that allow host manufacturers to use the module. Two types of instructions are necessary: first to the host manufacturer to define conditions (mobile, portable xx cm from body) and second additional text needed to be provided to the end user in the host product manuals. 6. Antennas. KDB 996369 D03, Section 2.7 a. List of antennas included in the application and all applicable professional installer instructions when applicable. The antenna list shall also identify the antenna types (monopole, PIFA, dipole, etc note that omni-directional is not considered a type) 7. Label and compliance information. KDB 996369 D03, Section 2.8 a. Advice to host integrators that they need to provide a physical or e-label stating Contains FCC ID: with their finished product 8. Information on test modes and additional testing requirements. KDB 996369 D03, Section 2.9 a. Test modes that should be taken into consideration by host integrators including clarifications necessary for stand-alone and simultaneous configurations. b. Provide information on how to configure test modes for evaluation 9. Additional testing, Part 15 Subpart B disclaimer. KDB 996369 D03, Section 2.10

- All Items shown to the left are provided in the Modular Integration Guide (or UM) for Full Modular Approval (MA) or LMA.

- An LMA applies and is approved ONLY for use by the grantee in their own products, and not intended for sale to 3rd parties as provided in a separate cover letter. Therefore the information shown to the left is found in the theory of operation. _____________ Name: Jean Hu Email: Jean.Hu@Quectel.com Date: 2022-10-20 070920-02b