FCC ID: XMR2023RG500LNA 5G Sub-6 GHz LGA Module

 

WARNING:pdfminer.pdfpage:The PDF <_io.BufferedReader name='/Volumes/Scratch/Incoming/eg-scratch/6578130.pdf'> contains a metadata field indicating that it should not allow text extraction. Ignoring this field and proceeding. Use the check_extractable if you want to raise an error in this case RG500L Series QuecOpen Hardware Design 5G Module Series Version: 1.1 Date: 2022-02-08 Status: Released RG500L_Series_QuecOpen_Hardware_Design 0 / 102 5G Module Series At Quectel, our aim is to provide timely and comprehensive services to our customers. If you require any assistance, please contact our headquarters:

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local offices. For more information, please visit:

http://www.quectel.com/support/sales.htm. For technical support, or to report documentation errors, please visit:

http://www.quectel.com/support/technical.htm. Or email us at: support@quectel.com. Legal Notices We offer information as a service to you. The provided information is based on your requirements and we make every effort to ensure its quality. You agree that you are responsible for using independent analysis and evaluation in designing intended products, and we provide reference designs for illustrative purposes only. Before using any hardware, software or service guided by this document, please read this notice carefully. Even though we employ commercially reasonable efforts to provide the best possible experience, you hereby acknowledge and agree that this document and related services hereunder are provided to you on an as available basis. We may revise or restate this document from time to time at our sole discretion without any prior notice to you. Use and Disclosure Restrictions License Agreements Documents and information provided by us shall be kept confidential, unless specific permission is granted. They shall not be accessed or used for any purpose except as expressly provided herein. Copyright Our and third-party products hereunder may contain copyrighted material. Such copyrighted material shall not be copied, reproduced, distributed, merged, published, translated, or modified without prior written consent. We and the third party have exclusive rights over copyrighted material. No license shall be granted or conveyed under any patents, copyrights, trademarks, or service mark rights. To avoid ambiguities, purchasing in any form cannot be deemed as granting a license other than the normal non-exclusive, royalty-free license to use the material. We reserve the right to take legal action for noncompliance with abovementioned requirements, unauthorized use, or other illegal or malicious use of the material. RG500L_Series_QuecOpen_Hardware_Design 1 / 110 5G Module Series Trademarks Except as otherwise set forth herein, nothing in this document shall be construed as conferring any rights to use any trademark, trade name or name, abbreviation, or counterfeit product thereof owned by Quectel or any third party in advertising, publicity, or other aspects. Third-Party Rights This document may refer to hardware, software and/or documentation owned by one or more third parties

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Privacy Policy To implement module functionality, certain device data are uploaded to Quectels or third-partys servers, including carriers, chipset suppliers or customer-designated servers. Quectel, strictly abiding by the relevant laws and regulations, shall retain, use, disclose or otherwise process relevant data for the purpose of performing the service only or as permitted by applicable laws. Before data interaction with third parties, please be informed of their privacy and data security policy. Disclaimer a) We acknowledge no liability for any injury or damage arising from the reliance upon the information. b) We shall bear no liability resulting from any inaccuracies or omissions, or from the use of the information contained herein. c) While we have made every effort to ensure that the functions and features under development are free from errors, it is possible that they could contain errors, inaccuracies, and omissions. Unless otherwise provided by valid agreement, we make no warranties of any kind, either implied or express, and exclude all liability for any loss or damage suffered in connection with the use of features and functions under development, to the maximum extent permitted by law, regardless of whether such loss or damage may have been foreseeable. d) We are not responsible for the accessibility, safety, accuracy, availability, legality, or completeness of information, advertising, commercial offers, products, services, and materials on third-party websites and third-party resources. Copyright Quectel Wireless Solutions Co., Ltd. 2022. All rights reserved. RG500L_Series_QuecOpen_Hardware_Design 2 / 110 5G Module Series Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be paid to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions, such as when the mobile bill is unpaid or the (U)SIM card is invalid. When emergent help is needed in such conditions, use emergency call if the device supports it. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. In an emergency, the device with emergency call function cannot be used as the only contact method considering network connection cannot be guaranteed under all circumstances. The cellular terminal or mobile contains a transceiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV sets, radios, computers or other electric equipment. In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fueling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or metal powders. RG500L_Series_QuecOpen_Hardware_Design 3 / 110 5G Module Series About the Document Revision History Version Date Author Description

2021-09-02 1.0 2021-09-02 Ellen LI/Hank LIU/

Ballon SHI Ellen LI/Hank LIU/

Ballon SHI Creation of the document First official release 1.1 2022-01-28 Ellen LI/Hank LIU/

Ballon SHI 1. Updated supported frequency bands of RG500L-NA;

2. Updated the 5G SA UL maximum transmission rate from 2.5 Gbps to 1.25 Gbps. (Table 4);

3. Updated supported Internet protocol features (Table 4);

4. Added the chapter about USB application scenario

(Chapter 3.2.2);

5. Updated the description about PWRKEY (Chapter 3.5.1);

6. Added operating frequency and cellular antenna mapping of RG500L-NA (Table 32 & 34);

7. Updated the RF receiving sensitivity of RG500L-NA

(Table 37);

8. Added the chapter of the recommended RF connector for installation (Chapter 5.5.1);

9. Added 1.86 V SDIO I/O requirements and 1.8/3.0 V

(U)SIM I/O requirements (Table 47 & 48 & 49);

10. Updated the recommended max slope in Recommended Thermal Profile Parameters (Figure 50 & Table 51);

11. Added the chapter about AT commands (Chapter 9). RG500L_Series_QuecOpen_Hardware_Design 4 / 110 5G Module Series Contents Safety Information ....................................................................................................................................... 3 About the Document ................................................................................................................................... 4 Contents ....................................................................................................................................................... 5 Table Index ................................................................................................................................................... 8 Figure Index ............................................................................................................................................... 10 1 Introduction ........................................................................................................................................ 12 Special Mark ............................................................................................................................ 12 1.1. 2 Product Overview .............................................................................................................................. 13 Frequency Bands and Functions ............................................................................................ 13 Key Features ........................................................................................................................... 14 Functional Diagram ................................................................................................................. 16 Pin Assignment ........................................................................................................................ 17 Pin Description ........................................................................................................................ 18 2.1. 2.2. 2.3. 2.4. 2.5. 3.1. 3.2. 3.3. 3.4. 3 Operating Characteristics ................................................................................................................. 27 Operating Modes ..................................................................................................................... 28 Sleep Mode ............................................................................................................................. 28 3.2.1. UART Application Scenario ............................................................................................ 29 3.2.2. USB Application Scenario .............................................................................................. 29 Airplane Mode ......................................................................................................................... 29 Power Supply .......................................................................................................................... 30 3.4.1. Power Supply Pins ......................................................................................................... 30 3.4.2. Reference Design for Power Supply .............................................................................. 30 3.4.3. Requirements for Voltage Stability ................................................................................. 31 Turn On ................................................................................................................................... 32 Turn on the Module with PWRKEY ................................................................................ 32 Turn on the Module with PON_1 .................................................................................... 34 Turn Off .................................................................................................................................... 35 Turn off the Module with PWRKEY ................................................................................ 35 Turn off the Module with PON_1 .................................................................................... 35 Reset ....................................................................................................................................... 35 3.5.1. 3.5.2. 3.6.1. 3.6.2. 3.6. 3.7. 3.5. 4.1. 4.2. 4 Application Interfaces ....................................................................................................................... 37 USB Interface .......................................................................................................................... 37

(U)SIM Interfaces .................................................................................................................... 39 4.2.1. Normally Closed (U)SIM Card Connector...................................................................... 39 4.2.2. Normally Open (U)SIM Card Connector ........................................................................ 40

(U)SIM Card Connector Without Hot-Plug ..................................................................... 41 4.2.3. I2C Interface ............................................................................................................................ 42 4.3. RG500L_Series_QuecOpen_Hardware_Design 5 / 110 5G Module Series PCM Interfaces ........................................................................................................................ 42 4.4. UART Interfaces ...................................................................................................................... 43 4.5. SDIO Interface ......................................................................................................................... 46 4.6. ADC Interfaces ........................................................................................................................ 47 4.7. LCM Interface .......................................................................................................................... 49 4.8. 4.9. SGMII Interfaces ..................................................................................................................... 50 4.10. SPI Interfaces .......................................................................................................................... 52 4.11. PCIe Interfaces ........................................................................................................................ 53 4.12. WWAN/WLAN Control Interface ............................................................................................. 56 4.13. USB_BOOT Interface .............................................................................................................. 57 4.14. Control Signals ........................................................................................................................ 58 Indication Signals .................................................................................................................... 58 4.15. 4.15.1. STATUS .......................................................................................................................... 59 4.15.2. Network Status Indication* ............................................................................................. 59 4.15.3. AIR_MODE* ................................................................................................................... 60 4.15.4. Other Indication Signals* ............................................................................................... 61 5.2. 5.1. 5 RF Specifications ............................................................................................................................... 62 Cellular Network ...................................................................................................................... 62 5.1.1. Antenna Interfaces & Frequency Bands ........................................................................ 62 Tx Power ........................................................................................................................ 67 5.1.2. 5.1.3. Rx Sensitivity .................................................................................................................. 67 5.1.4. Reference Design .......................................................................................................... 70 GNSS ...................................................................................................................................... 71 5.2.1. Antenna Interface & Frequency Bands .......................................................................... 72 5.2.2. GNSS Performance ....................................................................................................... 72 5.2.3. Reference Design .......................................................................................................... 73 RF Routing Guidelines ............................................................................................................ 73 Requirements for Antenna Design .......................................................................................... 75 RF Connector Recommendation ............................................................................................ 77 5.5.1. Recommended RF Connector for Installation ............................................................... 78 Assemble Coaxial Cable Plug Manually ........................................................ 78 Assemble Coaxial Cable Plug with Jig ........................................................... 79 5.5.2. Recommended Manufacturers of RF Connector and Cable ......................................... 80 5.5.1.1. 5.5.1.2. 5.3. 5.4. 5.5. 6 Electrical Characteristics & Reliability ............................................................................................ 81 Absolute Maximum Ratings .................................................................................................... 81 Power Supply Ratings ............................................................................................................. 81 Power Consumption ................................................................................................................ 82 Digital I/O Characteristic ......................................................................................................... 83 ESD Protection ........................................................................................................................ 84 Operating and Storage Temperatures ..................................................................................... 85 Thermal Consideration ............................................................................................................ 85 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 7 Mechanical Information ..................................................................................................................... 87 7.1. Mechanical Dimensions .......................................................................................................... 87 RG500L_Series_QuecOpen_Hardware_Design 6 / 110 5G Module Series 7.2. 7.3. Recommended Footprint ......................................................................................................... 89 Top and Bottom Views............................................................................................................. 90 8 Storage, Manufacturing & Packaging .............................................................................................. 91 Storage Conditions .................................................................................................................. 91 8.1. 8.2. Manufacturing and Soldering .................................................................................................. 92 Packaging Specifications ........................................................................................................ 93 8.3. 8.3.1. Carrier Tape .................................................................................................................... 93 8.3.2. Plastic Reel .................................................................................................................... 94 8.3.3. Packaging Process ........................................................................................................ 95 9 AT Commands .................................................................................................................................... 96 AT+CFUN Set Phone Functionality ...................................................................................... 96 AT+QSCLK Sleep Mode Setting .......................................................................................... 97 AT+QADC* Read ADC Value ............................................................................................... 98 9.1. 9.2. 9.3. 10 Appendix References ...................................................................................................................... 100 11.2. 11 Warning statements ......................................................................................................................... 104 11.1. FCC ....................................................................................................................................... 104 Important Notice to OEM integrators ........................................................................... 104 11.1.1. Important Note.............................................................................................................. 104 11.1.2. 11.1.3. End Product Labeling ................................................................................................... 104 11.1.4. Antenna Installation ...................................................................................................... 104 11.1.5. Manual Information to the End User ............................................................................ 105 11.1.6. Federal Communication Commission Interference Statement .................................... 106 11.1.7. List of applicable FCC rules ......................................................................................... 106 11.1.8. This device is intended only for OEM integrators under the following conditions:(For module device use) ..................................................................................................................... 106 11.1.9. Radiation Exposure Statement .................................................................................... 107 IC ........................................................................................................................................... 107 Industry Canada Statement ......................................................................................... 107 11.2.1. 11.2.2. Radiation Exposure Statement .................................................................................... 107 11.2.3. Dclaration d'exposition aux radiations: ...................................................................... 107 11.2.4. RSS-247 Section 6.4 (5) (6) (for local area network devices, 5GHz) .......................... 108 11.2.5. This device is intended only for OEM integrators under the following conditions: (For module device use) ..................................................................................................................... 108 11.2.6. Cet appareil est conu uniquement pour les intgrateurs OEM dans les conditions suivantes: (Pour utilisation de dispositif module) ....................................................................... 108 IMPORTANT NOTE: .................................................................................................... 109 11.2.7. 11.2.8. NOTE IMPORTANTE: .................................................................................................. 109 11.2.9. End Product Labeling ................................................................................................... 109 11.2.10. Plaque signaltique du produit final ............................................................................. 109 11.2.11. Manual Information To the End User ........................................................................... 109 11.2.12. Manuel d'information l'utilisateur final ....................................................................... 110 RG500L_Series_QuecOpen_Hardware_Design 7 / 110 5G Module Series Table Index Table 1: Special Mark ................................................................................................................................. 12 Table 2: Brief Introduction of the Module ................................................................................................... 13 Table 3: Wireless Network Type ................................................................................................................. 13 Table 4: Key Features ................................................................................................................................ 14 Table 5: I/O Parameters Definition ............................................................................................................. 18 Table 6: Pin Description ............................................................................................................................. 18 Table 7: Overview of Operating Modes ...................................................................................................... 28 Table 8: Pin Definition of Power Supply ..................................................................................................... 30 Table 9: Pin Definition of PWRKEY ............................................................................................................ 32 Table 10: Pin Definition of PON_1 ............................................................................................................. 34 Table 11: Pin Definition of RESET_N ......................................................................................................... 36 Table 12: Pin Definition of USB Interface ................................................................................................... 37 Table 13: Pin Definition of (U)SIM Interfaces ............................................................................................. 39 Table 14: Pin Definition of I2C Interface..................................................................................................... 42 Table 15: Pin Definition of PCM Interfaces ................................................................................................ 43 Table 16: UART Information ....................................................................................................................... 43 Table 17: Pin Definition of UART Interfaces ............................................................................................... 44 Table 18: Pin Definition of SDIO Interface ................................................................................................. 46 Table 19: Pin Definition of ADC Interfaces ................................................................................................. 47 Table 20: Voltage Range of ADC Interfaces .............................................................................................. 48 Table 21: Pin Definition of LCM Interface .................................................................................................. 49 Table 22: Pin Definition of SGMII Interfaces .............................................................................................. 50 Table 23: Pin Definition of SPI Interfaces .................................................................................................. 52 Table 24: Pin Definition of PCIe Interfaces ................................................................................................ 53 Table 25: Pin Definition of WWAN/WLAN Control Interface ...................................................................... 56 Table 26: Pin Definition of USB_BOOT Interface ...................................................................................... 57 Table 27: Pin Definition of Control Signals ................................................................................................. 58 Table 28: Pin Definition of Indication Signals ............................................................................................. 58 Table 29: Working Mechanism of Network Registration Mode/Network Activity Indication ....................... 59 Table 30: Pin Definition of Cellular Antenna Interfaces .............................................................................. 62 Table 31: Operating Frequency of RG500L-EU ......................................................................................... 63 Table 32: Operating Frequency of RG500L-NA ......................................................................................... 63 Table 33: RG500L-EU Cellular Antenna Mapping ..................................................................................... 65 Table 34: RG500L-NA Cellular Antenna Mapping...................................................................................... 66 Table 35: RG500L Series Tx Power ........................................................................................................... 67 Table 36: Conducted RF Receiving Sensitivity of RG500L-EU ................................................................. 67 Table 37: Conducted RF Receiving Sensitivity of RG500L-NA ................................................................. 68 Table 38: Pin Definition of GNSS Antenna Interface ................................................................................. 72 Table 39: GNSS Frequency ....................................................................................................................... 72 Table 40: GNSS Performance .................................................................................................................... 72 Table 41: Requirements for Antenna Design ............................................................................................. 75 RG500L_Series_QuecOpen_Hardware_Design 8 / 110 5G Module Series Table 42: Absolute Maximum Ratings ........................................................................................................ 81 Table 43: The Modules Power Supply Ratings ......................................................................................... 81 Table 44: Averaged Power Consumption ................................................................................................... 82 Table 45: 1.8 V I/O Requirements .............................................................................................................. 83 Table 46: SDIO 1.86 V I/O Requirements .................................................................................................. 83 Table 47: (U)SIM 1.8 V I/O Requirements ................................................................................................. 83 Table 48: (U)SIM 3.0 V I/O Requirements ................................................................................................. 84 Table 49: Electrostatics Discharge Characteristics (25 C, 45 % Relative Humidity) ............................... 84 Table 50: Operating and Storage Temperatures ........................................................................................ 85 Table 51: Recommended Thermal Profile Parameters .............................................................................. 93 Table 52: Carrier Tape Dimension Table (Unit: mm) .................................................................................. 94 Table 53: Plastic Reel Dimension Table (Unit: mm) ................................................................................... 94 Table 54: Related Documents .................................................................................................................. 100 Table 55: Terms and Abbreviations .......................................................................................................... 100 RG500L_Series_QuecOpen_Hardware_Design 9 / 110 5G Module Series Figure Index Figure 2: Pin Assignment (Top View) ......................................................................................................... 17 Figure 3: DRX Run Time and Current Consumption in Sleep Mode ......................................................... 29 Figure 4: Reference Design of Power Supply ............................................................................................ 31 Figure 5: Power Supply Limits during Burst Transmission ........................................................................ 31 Figure 6: Star Structure of the Power Supply ............................................................................................. 32 Figure 7: Reference Circuit of Turing on the Module with Driving Circuit .................................................. 33 Figure 8: Reference Circuit of Turing on the Module with Keystroke ........................................................ 33 Figure 9: Timing of Turning on the Module ................................................................................................ 34 Figure 10: Timing of Turning off the Module .............................................................................................. 35 Figure 11: Reference Circuit of RESET_N with Driving Circuit ................................................................. 36 Figure 12: Timing of Resetting the Module ................................................................................................ 36 Figure 13: Reference Circuit of USB Interface .......................................................................................... 38 Figure 14: Reference Circuit of Normally Closed (U)SIM Card Connector ............................................... 40 Figure 15: Reference Circuit of Normally Open (U)SIM Card Connector ................................................. 41 Figure 16: Reference Circuit of a 6-Pin (U)SIM Card Connector .............................................................. 41 Figure 17: Bluetooth UART Interface Connection ..................................................................................... 44 Figure 18: Reference Circuit with Level Translator Chip ........................................................................... 45 Figure 19: Reference Circuit with Transistor Circuit .................................................................................. 45 Figure 20: Reference Circuit of SD Card Interface .................................................................................... 46 Figure 21: Reference Circuit Design for LCM Interface ............................................................................. 49 Figure 22: Reference Circuit of LCM External Backlight Driver ................................................................ 50 Figure 23: Reference Circuit of SGMII Interface with PHY Application ..................................................... 51 Figure 24: Reference Circuit of SPI Interface with a Level Translator....................................................... 52 Figure 25: Reference Circuit of PCIe Interface .......................................................................................... 55 Figure 26: Reference Circuit of USB_BOOT Interface .............................................................................. 57 Figure 27: Reference Circuit of KEY .......................................................................................................... 58 Figure 30: Reference Circuit of STATUS Indicator .................................................................................... 59 Figure 28: Reference Circuit of NET_MODE Indicator .............................................................................. 60 Figure 29: Reference Circuit of NET_STATUS Indicator ........................................................................... 60 Figure 31: Reference Circuit of AIR_MODE Indicator ............................................................................... 61 Figure 32: Reference Circuit of Other Indicators ....................................................................................... 61 Figure 33: Reference Circuit for Cellular Antenna Interfaces .................................................................... 70 Figure 34: Reference Circuit of GNSS Antenna Interface ......................................................................... 73 Figure 35: Microstrip Design on a 2-layer PCB ......................................................................................... 74 Figure 36: Coplanar Waveguide Design on a 2-layer PCB ....................................................................... 74 Figure 37: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 74 Figure 38: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 75 Figure 39: Dimensions of the Receptacles (Unit: mm) .............................................................................. 77 Figure 40: Specifications of Mating Plugs Using 0.81 mm Coaxial Cables (Unit: mm) .......................... 78 Figure 41: Plug in a Coaxial Cable Plug .................................................................................................... 79 Figure 42: Pull out a Coaxial Cable Plug ................................................................................................... 79 RG500L_Series_QuecOpen_Hardware_Design 10 / 110 5G Module Series Figure 43: Install the Coaxial Cable Plug with Jig ...................................................................................... 80 Figure 44: Placement and Fixing of Heatsink ............................................................................................ 86 Figure 45: Module Top and Side Dimensions (Unit: mm) .......................................................................... 87 Figure 46: Module Bottom Dimensions (Bottom View, Unit: mm) ............................................................. 88 Figure 47: Recommended Footprint (Top View, Unit: mm) ........................................................................ 89 Figure 48: Top and Bottom Views of the Module ....................................................................................... 90 Figure 49: Recommended Reflow Soldering Thermal Profile ................................................................... 92 Figure 50: Carrier Tape Dimension Drawing .............................................................................................. 94 Figure 51: Plastic Reel Dimension Drawing .............................................................................................. 94 Figure 52: Packaging Process ................................................................................................................... 95 RG500L_Series_QuecOpen_Hardware_Design 11 / 110 5G Module Series 1 Introduction QuecOpen is a solution where the module acts as the main processor. Constant transition and evolution of both the communication technology and the market highlight its merits. It can help you to:

Realize embedded applications quick development and shorten product R&D cycle Simplify circuit and hardware structure design to reduce engineering costs Miniaturize products Reduce product power consumption Apply OTA technology Enhance product competitiveness and price-performance ratio This document defines the RG500L series module under QuecOpen solution and describes its air interfaces and hardware interfaces which relate to your applications. It can help you quickly understand interface specifications, electrical and mechanical details, as well as other related information of the module. Associated with application notes and user guides, you can use this module to design and to set up mobile applications easily. 1.1. Special Mark Table 1: Special Mark Mark Definition

Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin, AT command, or argument is under development and currently not supported; and the asterisk (*) after a model indicates that the sample of such model is currently unavailable. RG500L_Series_QuecOpen_Hardware_Design 12 / 110 5G Module Series 2 Product Overview RG500L series module is an SMD type module which is engineered to meet the demanding requirements in M2M applications, such as 5G wireless router, CPE, MiFi, business router, home gateway, etc. Related information and details are listed in the table below:

Table 2: Brief Introduction of the Module Categories Package Type and Number of Pins LGA; 430 Dimensions Weight

(41.0 0.20) mm (44.0 0.20) mm (2.75 0.20) mm Approx.11 g Wireless Network Functions Cellular: 5G NR/LTE/WCDMA 1/GNSS Variant RG500L-EU/RG500L-NA 2.1. Frequency Bands and Functions Table 3: Wireless Network Type Wireless Network Type RG500L-EU RG500L-NA 5G NR n1/n3/n5/n7/n8/n20/n28/n38/n40/n41/n77

/n78 n2/n5/n7/n12/n25/n38/n41/n48/n66/n71/

n77/n78 LTE-FDD B1/B3/B5/B7/B8/B20/B28/B32 B2/B4/B5/B7/B12/B13/B14/B17/B25/

B26/B30/B66/B71 LTE-TDD B38/B40/B41/B42/B43 B38/B41/B42/B43/B48 LTE-LAA

WCDMA B1/B5/B8 B29/B46

1 WCDMA bands is only supported by RG500L-EU. RG500L_Series_QuecOpen_Hardware_Design 13 / 110 5G Module Series GNSS GPS/BeiDou/GLONASS/Galileo (L1 + L5) GPS/BeiDou/GLONASS/Galileo (L1 only) 2.2. Key Features Table 4: Key Features Features Details Power Supply SMS

(U)SIM Interfaces Supply voltage: 3.34.3 V Typical supply voltage: 3.8 V Text and PDU mode Point-to-point MO and MT SMS cell broadcast SMS storage: (U)SIM card by default Supports USIM/SIM card: 1.8 V, 3.0 V Supports Dual SIM Single Standby Audio Features Supports two digital audio interfaces: PCM PCM Interfaces SPI Interfaces Used for audio function with external SLIC Supports long frame synchronization and short frame synchronization Supports master and slave modes, but must be the master in long frame synchronization Two SPI interfaces which supports slave mode* and mater mode Supports synchronous and serial communication link with the peripheral devices 1.8 V power domain with clock rates up to 52 MHz I2C Interface One I2C interface SGMII Interfaces Interface for WLAN Application IEEE 802.3 compliant Supports 10/100/1000/2500 Mbps in full duplex mode Supports PCIe interface for WLAN application Compliant with USB 3.0 and 2.0 specifications, with transmission rates up to 5 Gbps on USB 3.0 and 480 Mbps on USB 2.0 USB Interface Used for AT command communication, data transmission, GNSS NMEA*

sentence output, software debugging and firmware upgrade USB serial driver: supports USB serial driver for Windows 7/8/8.1/10 SDIO Interface Supports SD 3.0 protocol Only used for SD card UART Interfaces Main UART:

Used for AT command communication and data transmission Baud rate: 115200 bps Supports RTS and CTS hardware flow control RG500L_Series_QuecOpen_Hardware_Design 14 / 110 5G Module Series Debug UART:

Used for Linux console and log output Baud rate: 921600 bps Bluetooth UART:

Used for Bluetooth communication Baud rate: 115200 bps PCIe Interfaces PCI Express Base Specification Revision 3.0 compliant Data rate at 8 Gbps per lane Only supports Root Complex mode Can be used to connect to an external Ethernet IC (MAC and PHY) or WLAN IC Network Indication*

NET_MODE and NET_STATUS to indicate network connectivity status AT Commands Compliant with 3GPP TS 27.007, 27.005 and Quectel enhanced AT commands Antenna Interfaces Cellular: ANT0ANT7 GNSS: ANT_GNSS 50 impedance Supports 3GPP Rel-15 Supports 2CC CA Supports uplink 256QAM* and downlink 256QAM Supports DL 4 4 MIMO:

RG500L-EU: n1/n3/n7/n38/n40/n41/n77/n78 RG500L-NA: n2/n7/n25/n38/n41/n48/n77/n78 Supports UL 2 2 MIMO 2 :

RG500L-EU: n41/n77/n78 RG500L-NA: n41/n48/n77/n78 Supports SCS 15 kHz and 30 kHz Supports SA and NSA operation modes Supports Option 3x, 3a, 3, and Option 2 Maximum transmission rates 3:

NSA: 3.74 Gbps (DL)/ 1.46 Gbps 4 (UL) SA: 4.67 Gbps (DL)/ 1.25 Gbps[SD1] (UL) Supports both FDD and TDD Supports up to CA Cat 19 Supports 1.4 to 20 MHz RF bandwidth Supports LTE DL 4 4 MIMO:

5G NR Features LTE Features RG500L-EU: B1/B3/B7/B38/B40/B41/B42/B43 RG500L-NA: B2/B4/B7/B25/B30/B38/B41/B42/B43/B48/B66 Supports UL QPSK, 16QAM and 64QAM and 256QAM modulation 2 Uplink 2 2 MIMO is only supported in 5G TDD SA mode. 3 The maximum rates are theoretical and the actual values are subject to the network configuration. 4 1.46Gbps is the theoretical data when LTE and 5G NR uplink 256QAM are both powered on. LTE uplink256QAM in EN-DC is not required by operators and has not been verified by the system, so it is powered off by default. RG500L_Series_QuecOpen_Hardware_Design 15 / 110 5G Module Series Supports DL QPSK, 16QAM and 64QAM and 256QAM modulation Maximum transmission rates LTE: 1.6 Gbps (DL)/ 211 Mbps (UL) Supports 3GPP Rel-9 DC-HSDPA/HSPA+/HSDPA/HSUPA/WCDMA Supports QPSK/16QAM/64QAM modulation Maximum transmission rates DC-HSDPA: 42 Mbps HSUPA: 5.76 Mbps WCDMA: 384 kbps (DL)/ 384 kbps (UL) Supports MIPC/TCP/UDP/FTP/HTTP/NTP/PING/HTTPS/MMS/FTPS/

SSL protocols[JW2][JW3]

Support PAP and CHAP for PPP connections Supports GPS/BeiDou/GLONASS/Galileo Protocol: NMEA 0183 Data update rate: 1 Hz by default, max. 5 Hz Operating temperature range 5: -30 C to +70 C Extended temperature range Storage temperature range: -40 C to +90 C 6

: -40 C to +85 C UMTS Features Internet Protocol Features GNSS Features Temperature Range Firmware Upgrade Use USB interface or FOTA for upgrade RoHS All hardware components are fully compliant with EU RoHS directive 2.3. Functional Diagram The following figure shows a block diagram of the module and illustrates the major functional parts. Power management Baseband MCP Radio frequency Peripheral interfaces 5 To meet this operating temperature range, additional thermal dissipation improvements are required, such as passive or active heatsink, heat-pipe, vapor chamber, cold-plate etc. Within this operating temperature range, the module can meet 3GPP specifications. 6 To meet this extended temperature range, additional thermal dissipation improvements are required, such as passive or active heatsink, heat-pipe, vapor chamber, cold-plate etc. Within this extended temperature range, the module remains the ability to establish and maintain functions such as voice, SMS, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may undergo a reduction in value, exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again. RG500L_Series_QuecOpen_Hardware_Design 16 / 110 5G Module Series 2.4. Pin Assignment The following figure illustrates the pin assignment of the module. Figure 1: Pin Assignment (Top View) RG500L_Series_QuecOpen_Hardware_Design 17 / 110 392GND391GND263SGMII1_TX_M260SGMII1_RX_M257SPI0_CLK254USIM2_RST251USIM2_DATA248USIM1_DATA245USIM1_VDD242TP_I2C_SDA239NET_STATUS236VBAT_BB233VBAT_RF1230VBAT_RF1227GND224GND221SPI3_MISO218SPI3_CS215PCM1_CLK212PCM1_DIN209I2S0_MCK206 DBG_TXD203MAIN_RTS200MAIN_TXD197GND390GND389GND299GND300GND301GND302GND303GND304GND305GND306GND307GND308GND309GND310GND311GND312GND313GND314GND315GND316GND317GND318GND319GND320GND321GND322GND323GND324GND325GND326GND327GND331GND332GND328GND329GND330GND333GND334GND335GND336GND340GND341GND337GND338GND339GND342GND343GND344GND345GND349GND350GND346GND347GND348GND351GND352GND353GND354GND355GND356GND357GND358GND359GND360GND361GND362GND363GND364GND365GND366GND367GND368GND369GND370GND371GND372GND373GND374GND375GND376GND377GND378GND379GND380GND381GND382GND383GND384GND385GND386GND387GND388GND65SD_DATA068SD_DATA371SD_DATA174USB_SS_TX_M77USB_SS_RX_M80OTG_PWR_EN83USB_DP86GND89RESERVED92RESERVED95RESERVED98RESERVED101RESERVED104GND107VBAT_RF2110VBAT_RF2113GND116GND119GND122GND125GND128GND131GND64SD_CMD67SD_CLK70SD_DATA273GND76USB_SS_TX_P79USB_SS_RX_P82USB_VBUS85USB_DM88PWM91RESERVED94RESERVED97RESERVED100RESERVED103RESERVED106GND109VBAT_RF2112VBAT_RF2115GND118GND121ANT0124GND127GND130ANT1132GND264SGMII1_TX_P262SGMII1_RX_P259SPI0_MOSI256SPI0_MISO253USIM2_CLK250USIM2_VDD247USIM1_CLK244USIM1_RST241ADC0238VBAT_BB235VBAT_BB232VBAT_RF1229VBAT_RF1226GND223SPI3_MOSI220SPI3_CLK217PCM1_SYNC214SLIC_INT_N211PCM1_DOUT208SLIC_RST_N205 DBG_RXD202MAIN_RXD199RESERVED196GND193ANT_GNSS190GND187GND184ANT7181GND178GND175ANT6172GND166ANT5163GND160GND157ANT4154GND151GND148ANT3145GND142GND169GND139ANT2136GND133GND195GND194GND191GND188GND185GND182GND179GND176GND173GND167GND164GND161GND158GND155GND152GND149GND146GND143GND170GND140GND137GND134GND192GND189RESERVED186RESERVED183RESERVED180GND177RESERVED174RESERVED171RESERVED168GND165RESERVED162GND159GND156GND153RESERVED150RESERVED147GND144GND141GND138ADC2135ADC1298RESERVED297RESERVED296RESERVED295RESERVED294RESERVED293RESERVED292RESERVED291RESERVED290RESERVED289RESERVED288RESERVED287RESERVED286RESERVED285RESERVED284RESERVED283RESERVED282RESERVED281PCIE0_CLKREQ_N280GPIO_15279PTA_TX278PTA_RX277BT_CTS276BT_RXD275BT_PRI_RXD274WLAN_SYSRST_2.4G273PCIE1_CLKREQ_N272WLAN_2.4G_EN271WLAN_SYSRST_5G270PCIE2_WAKE_N269PCIE3_RST_N268PCIE3_WAKE_N267MDIO_DATA266GND265MDIO_CLK60PCIE0_WAKE_N57GND54PCIE0_RST_N51GND48BT_RTS45BT_TXD39WLAN_ACT36BT_ACT_TXD30PCIE1_WAKE_N27PCIE1_RST_N24GND21PCIE2_CLKREQ_N15PCIE3_CLKREQ_N12GND9PON_16GND62PCM0_SYNC59PCM0_DOUT56PCIE0_REFCLK_P53PCIE0_RX_P50PCIE0_TX_M47GND44PCIE1_REFCLK_M41RESERVED35RESERVED32PCIE1_TX0_P29PCIE2_REFCLK_P26PCIE2_TX_P23PCIE2_RX_P17PCIE3_RX_M14PCIE3_TX_M11PCIE3_REFCLK_M38PCIE1_RX0_M8RESET_N5SGMII0_RX_M2SGMII0_TX_M61PCM0_DIN58RESERVED55PCIE0_REFCLK_M52PCIE0_RX_M49PCIE0_TX_P46PCIE1_REFCLK_P43RESERVED40PCIE1_RX0_P34PCIE1_TX0_M31GND28PCIE2_REFCLK_M25PCIE2_TX_M22PCIE2_RX_M16PCIE3_TX_P13PCIE3_REFCLK_P10GND37RESERVED7PWRKEY4SGMII0_RX_P1SGMII0_TX_P63PCM0_CLK237TP_RST234GND231GND228GND225AIR_MODE222STATUS219NET_MODE216USIM_LED213VOIP_LED210WIFI_MESH207RESTORE_KEY204WPS_KEY201MAIN_CTS258EPHY1_INT_N255SPI0_CS252USIM2_DET249USIM1_DET246GND243TP_I2C_SCL240BT_EN198GND261EPHY1_RST_N90GND93LCD_RST96GND99LCD_TE102LSDI105LSCE0B108LSA0111LSDA114LSCK117GND120GND123GND126GND69SD_DET72SDIO_PU_VDD75USB_ID78GND81USB_BOOT84RESERVED87RESERVED129GND66VDD_EXT19PCIE3_RX_P20GND18PCIE2_RST_N33GND42GNDPower PinsGND PinsGPIO PinsRESERVED PinsPCIe PinsKP Pins(U)SIM PinsUSB PinsI2C PinsDBI PinsADC PinsUART PinsSPI PinsANT PinsSDIO PinsSGMII PinsMIPI/BPII2S/PCM PinsCTL PinsWi-Fi Pins411EPHY0_RST_N410EPHY0_INT_N409GND408GND407GND406WLAN_5G_EN405TP_INT404GND403GND402GND401GND400GND399RESERVED398RESERVED397RESERVED396RESERVED395RESERVED394GND393GND412GND413RESERVED414RESERVED415RESERVED416RESERVED417RESERVED418GND419RESERVED420RESERVED421GND422LSRSTB423RESERVED424RESERVED425RESERVED426RESERVED427RESERVED428RESERVED429GND430GND3GND 5G Module Series NOTE Keep all RESERVED pins and unused pins unconnected. 2.5. Pin Description The following table shows the DC characteristics and pin descriptions. Table 5: I/O Parameters Definition Type Description AI AO AIO DI DO DIO OD PI PO Analog Input Analog Output Analog Input/Output Digital Input Digital Output Digital Input/Output Open Drain Power Input Power Output Table 6: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment VBAT_BB VBAT_RF1 235, 236, 238 229, 230, 232, 233 PI PI Power supply for the modules baseband part Power supply for the modules RF part Vmax = 4.3 V Vmin = 3.3 V Vnom = 3.8 V RG500L_Series_QuecOpen_Hardware_Design 18 / 110 5G Module Series VBAT_RF2 107, 109, 110, 112 PI Used to connect decoupling capacitors VDD_EXT 66 PO Provide 1.8 V for external circuit Vnom = 1.8 V IOmax = 50 mA There is no need to connect the pin to the external power supply. Power supply for external GPIOs pull-up circuits. Turn On/Off & Other Control Signals Pin Name Pin No. I/O Description DC Characteristics Comment PWRKEY RESET_N PON_1 7 8 9 DI Turn on/off the module DI Reset the module 1.8 V DI Turn on/off the module VBAT_BB RESTORE_KEY 207 DI Restore the module WPS_KEY*

204 DI Wi-Fi protected setup 1.8 V Internally pulled up to 1.8 V. Internally pulled up to 1.8 V. Active low. DC Characteristics Comment PMIC_ISINK3 1.8 V PMIC_ISINK2 PMIC_ISINK1 Indication Signals Pin Name Pin No. I/O Description STATUS 222 OD NET_MODE*

219 DO NET_STATUS*

239 OD AIR_MODE*

225 WIFI_MESH*

210 USIM_LED*

VOIP_LED*

USB Interface 216 213 OD DO DO DO Indicate the module's operation status Indicate the module's network registration mode Indicate the module's network activity status Indicate the module's flight mode Indicate the Wi-Fi mesh function status Indicate the (U)SIM card function status 1.8 V Indicate the VoIP function status Pin Name Pin No. I/O Description DC Characteristics Comment RG500L_Series_QuecOpen_Hardware_Design 19 / 110 5G Module Series USB_VBUS 82 AI USB connection detect Vmax = 15 V Vmin = 4.2 V Vnom = 5.0 V USB_DP USB_DM 83 85 USB_SS_TX_P 76 USB_SS_TX_M 74 USB_SS_RX_P 79 USB_SS_RX_M USB_ID OTG_PWR_EN

(U)SIM Interfaces 77 75 80 AIO AIO AO AO AI AI USB differential data

(+) USB differential data

(-) USB 3.0 super-speed transmit (+) USB 3.0 super-speed transmit (-) USB 3.0 super-speed receive (+) USB 3.0 super-speed receive (-) DI USB ID detect DO OTG power control 1.8 V Used for USB connection detection

(disabled by default). Cannot be used for power supply. Require differential impedance of 90 . Require differential impedance of 90 . If unused, connect RX to GND directly. Pin Name Pin No. I/O Description DC Characteristics Comment USIM1_VDD USIM1_DATA USIM1_CLK USIM1_RST USIM1_DET USIM2_VDD USIM2_DATA USIM2_CLK USIM2_RST USIM2_DET SDIO Interface 245 248 247 244 249 250 251 253 254 252 PO

(U)SIM1 card power supply DIO

(U)SIM1 card data DO

(U)SIM1 card clock DO

(U)SIM1 card reset DI PO

(U)SIM1 card hot-plug detect

(U)SIM2 card power supply DIO

(U)SIM2 card data DO

(U)SIM2 card clock DO

(U)SIM2 card reset 1.8/3.0 V 1.8 V 1.8/3.0 V DI

(U)SIM2 card hot-plug detect 1.8 V RG500L_Series_QuecOpen_Hardware_Design 20 / 110 5G Module Series Pin Name Pin No. I/O Description DC Characteristics Comment SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 SD_DET 67 64 65 71 70 68 69 SDIO_PU_VDD 72 Main UART Interface DO SD card clock DIO SD card command DIO SDIO data bit 0 DIO SDIO data bit 1 DIO SDIO data bit 2 DIO SDIO data bit 3 DI PO SD card hot-plug detect SD card IO pull-up power supply 1.86/3.0 V Only used for SD card. 1.8 V 1.86/3.0 V Pin Name Pin No. I/O Description DC Characteristics Comment MAIN_CTS 201 DO DTE clear to send signal from DCE MAIN_RTS MAIN_RXD MAIN_TXD 203 202 200 DI DTE request to send signal to DCE 1.8 V DI Main UART receive DO Main UART transmit Bluetooth UART Interface Connect to DTEs CTS Connect to DTEs RTS Pin Name Pin No. I/O Description DC Characteristics Comment BT_TXD 45 DO BT_RXD BT_RTS 276 48 DI DI BT_CTS 277 DO Debug UART Interface Bluetooth UART transmit Bluetooth UART receive DTE request to send signal to DCE DTE clear to send signal from DCE 1.8 V Connect to DTEs RTS Connect to DTEs CTS Pin Name Pin No. I/O Description DC Characteristics Comment DBG_RXD 205 DI Debug UART receive 1.8 V RG500L_Series_QuecOpen_Hardware_Design 21 / 110 5G Module Series DBG_TXD 206 DO Debug UART transmit I2C Interface Pin Name Pin No. I/O Description DC Characteristics Comment TP_I2C_SCL 243 OD I2C serial clock TP_I2C_SDA 242 OD I2C serial data 1.8 V Should be externally pulled up to 1.8 V. If unused, keep them open. PCM Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment PCM0_SYNC*

PCM0_CLK*

PCM0_DIN*

PCM0_DOUT*

62 63 61 59 DIO PCM0 data frame sync DIO PCM0 clock DI PCM0 data input DO PCM0 data output PCM1_SYNC 217 DIO PCM1 data frame sync 1.8 V PCM1_CLK PCM1_DIN PCM1_DOUT PCIe Interfaces 215 212 211 DIO PCM1 clock DI PCM1 data input DO PCM1 data output In master mode, they are output signals. In slave mode, they are input signals. If unused, keep them open. In master mode, they are output signals. In slave mode, they are input signals. If unused, keep them open. Pin Name Pin No. I/O Description DC Characteristics Comment PCIE0_REFCLK_P 56 PCIE0_REFCLK_M 55 PCIE0_TX_M PCIE0_TX_P PCIE0_RX_M PCIE0_RX_P 50 49 52 53 AO AO PCIe0 reference clock (+) PCIe0 reference clock (-) AO PCIe0 transmit (-) AO PCIe0 transmit (+) AI PCIe0 receive (-) AI PCIe0 receive (+) PCIE0_CLKREQ_N 281 DI PCIe0 clock request 1.8 V Require differential impedance of 85 . PCIe Gen3 compliant. If unused, connect RX traces to GND directly. RG500L_Series_QuecOpen_Hardware_Design 22 / 110 5G Module Series PCIE0_RST_N PCIE0_WAKE_N 54 60 PCIE1_REFCLK_P 46 PCIE1_REFCLK_M 44 PCIE1_TX0_M PCIE1_TX0_P PCIE1_RX0_M PCIE1_RX0_P 34 32 38 40 DO PCIe0 reset DI PCIe0 wake up AO AO PCIe1 reference clock (+) PCIe1 reference clock (-) AO PCIe1 transmit (-) AO PCIe1 transmit (+) AI PCIe1 receive (-) AI PCIe1 receive (+) PCIE1_CLKREQ_N 273 DI PCIe1 clock request PCIE1_RST_N PCIE1_WAKE_N 27 30 PCIE2_REFCLK_P 29 PCIE2_REFCLK_M 28 PCIE2_TX_M PCIE2_TX_P PCIE2_RX_M PCIE2_RX_P 25 26 22 23 DO PCIe1 reset 1.8 V DI PCIe1 wake up AO AO PCIe2 reference clock (+) PCIe2 reference clock (-) AO PCIe2 transmit (-) AO PCIe2 transmit (+) AI PCIe2 receive (-) AI PCIe2 receive (+) PCIE2_CLKREQ_N 21 DI PCIe2 clock request PCIE2_RST_N 18 DO PCIe2 reset 1.8 V PCIE2_WAKE_N 270 DI PCIe2 wake up PCIE3_REFCLK_P* 13 PCIE3_REFCLK_M* 11 PCIE3_TX_M*

PCIE3_TX_P*

PCIE3_RX_M*

14 16 17 AO AO PCIe3 reference clock (+) PCIe3 reference clock (-) AO PCIe3 transmit (-) AO PCIe3 transmit (+) AI PCIe3 receive (-) Require differential impedance of 85 . PCIe Gen3 compliant. If unused, connect RX to GND directly. Require differential impedance of 85 . PCIe Gen3 compliant. If unused, connect RX to GND directly. Require differential impedance of 85 . PCIe Gen3 compliant. If unused, connect RX to GND directly. RG500L_Series_QuecOpen_Hardware_Design 23 / 110 5G Module Series PCIE3_RX_P*

19 AI PCIe3 receive (+) PCIE3_CLKREQ_N* 15 DI PCIe3 clock request PCIE3_RST_N*

269 DO PCIe3 reset 1.8 V PCIE3_WAKE_N*

268 DI PCIe3 wake up LCM Interface Pin Name Pin No. I/O Description DC Characteristics Comment LSDI LSA0 LSCE0B LSRSTB LSCK LSDA PWM LCD_TE LCD_RST 102 108 105 422 114 111 88 99 93 DI SPI serial input data DO Indicate transmission of data or command DO SPI chip select DO SPI reset DO SPI serial clock 1.8 V DO SPI serial output data DO PWM output For LCD only. DI LCM tearing effect DO LCM reset SGMII Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment MDIO_DATA MDIO_CLK EPHY0_INT_N 267 265 410 DIO MDIO data DO MDIO clock DI SGMII0 interrupt 1.8 V EPHY0_RST_N 411 DO SGMII0 reset EPHY1_INT_N 258 DI SGMII1 interrupt EPHY1_RST_N 261 DO SGMII1 reset SGMII0_RX_M SGMII0_RX_P SGMII0_TX_P 5 4 1 AI SGMII0 receive (-) AI SGMII0 receive (+) AO SGMII0 transmit (+) Require differential impedance of 100 . If unused, connect RX to GND directly. RG500L_Series_QuecOpen_Hardware_Design 24 / 110 5G Module Series SGMII0_TX_M 2 AO SGMII0 transmit (-) SGMII1_RX_M SGMII1_RX_P SGMII1_TX_P SGMII1_TX_M 260 262 264 263 AI SGMII1 receive (-) AI SGMII1 receive (+) AO SGMII1 transmit (+) AO SGMII1 transmit (-) WWAN/WLAN Control Interface Pin Name Pin No. I/O Description WLAN_SYSRST_5G 271 DO WLAN 5 GHz system reset WLAN_2.4G_EN*

272 DO WLAN_SYSRST_ 2.4G 274 DO WLAN_5G_EN*

406 DO BT_ACT_TXD 7 36 DO BT_PRI_RXD 7 275 DO WLAN_ACT 39 DI PTA_TX 279 DO PTA_RX 278 DO GPIO_15 280 DI RF Antenna Interfaces WLAN 2.4 GHz function enable control WLAN 2.4 GHz system reset WLAN 5 GHz function enable control Coexistence interface for WWAN and 5 GHz Wi-Fi Coexistence interface for WWAN and 5 GHz Wi-Fi Coexistence interface for WWAN and 5 GHz Wi-Fi Coexistence interface for WWAN and 2.4 GHz Wi-Fi Coexistence interface for WWAN and 2.4 GHz Wi-Fi Coexistence interface for WWAN and 2.4 GHz Wi-Fi DC Characteristics Comment 1.8 V Reserved. Reserved. Used for WWAN/WLAN coexistence by default. Used for WWAN/WLAN coexistence by default. 7 Please note that this pin is for WWAN and Wi-Fi coexistence function, not for WWAN and Bluetooth coexistence function. RG500L_Series_QuecOpen_Hardware_Design 25 / 110 5G Module Series Pin Name Pin No. I/O Description DC Characteristics Comment ANT0 ANT1 ANT2 ANT3 ANT4 ANT5 ANT6 ANT7 ANT_GNSS SPI Interfaces 121 130 139 148 157 166 175 184 193 AIO Antenna 0 interface AIO Antenna 1 interface AI Antenna 2 interface AI Antenna 3 interface AI Antenna 4 interface 50 impedance. AI Antenna 5 interface AIO Antenna 6 interface AIO Antenna 7 interface AI GNSS antenna interface Pin Name Pin No. I/O Description DC Characteristics Comment SPI0_CS*

SPI0_CLK*

SPI0_MOSI*

SPI0_MISO*

SPI3_CS SPI3_CLK SPI3_MOSI 255 257 259 256 218 220 223 DO SPI0 chip select DO SPI0 clock DO DI SPI0 master-out slave-in SPI0 master-in salve-out DO SPI3 chip select DO SPI3 clock DO SPI3 master-out slave-in SPI3_MISO 221 DI SPI3 master-in salve-out ADC Interfaces Pin Name Pin No. I/O Description 1.8 V Recommended for SLIC IC communication. DC Characteristics Comment ADC0 ADC1 241 135 AI AI General-purpose ADC interface General-purpose ADC interface 1.78 V 1.45 V Max input 1.78 V. If unused, connect it to GND directly. Max input 1.45 V. If unused, connect RG500L_Series_QuecOpen_Hardware_Design 26 / 110 5G Module Series ADC2 138 AI General-purpose ADC interface them to GND directly. Other Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment USB_BOOT 81 DI Force the module into emergency download mode SLIC_RST_N SLIC_INT_N TP_RST TP_INT BT_EN*

I2S0_MCK Reserved Pins 208 214 237 405 240 209 DO SLIC reset DI SLIC interrupt DO TP reset DI TP interrupt DO Bluetooth enable control DO I2S0 master clock 1.8 V Pin Name Pin No. Reserved. 35, 37, 41, 43, 58, 84, 87, 89, 91, 92, 94, 95, 97, 98, 100, 101, 103, 150, 153, 165, 171, 174, 177, 183, 186, 189, 199, 282298, 395399, 413417, 419, 420, 423428 RESERVED GND Pin Name Pin No. GND 3, 6, 10, 12, 20, 24, 31, 33, 42, 47, 51, 57, 73, 78, 86, 90, 96, 104, 106, 113, 115120, 122129, 131134, 136, 137, 140147, 149, 151, 152, 154156, 158164, 167170, 172, 173, 176, 178182, 185, 187, 188, 190192, 194198, 224, 226228, 231, 234, 246, 266, 299394, 400404, 407409, 412, 418, 421, 429, 430 3 Operating Characteristics RG500L_Series_QuecOpen_Hardware_Design 27 / 110 5G Module Series 3.1. Operating Modes The table below outlines operating modes of the module. Table 7: Overview of Operating Modes Mode Details Normal Operation Minimum Functionality Mode Airplane Mode Sleep Mode Idle Voice/Data Software is active. The module is registered on the network and ready to send and receive data. Network connection is ongoing. In this mode, the power consumption is decided by network setting and data transfer rate. AT+CFUN=0 command can set the module to the minimum functionality mode. In this case, both RF function and (U)SIM card are invalid. AT+CFUN=4 command can set the module to airplane mode. In this case, RF function is invalid. In this mode, current consumption of the module will be reduced to the minimal level. In this mode, the module can still receive paging, SMS, voice call and TCP/UDP data from network. Power Down Mode In this mode, the power management unit shuts down the power supply. Software is not active. The serial interfaces are not accessible. Operating voltage (connected to VBAT_RF1 and VBAT_BB) remains applied. NOTE For more details about AT commands, see Chapter 9.1. 3.2. Sleep Mode DRX of the module is able to reduce the current consumption to a minimum value during sleep mode, and DRX cycle index values are broadcasted by the wireless network. The diagram below illustrates the relationship between the DRX run time and the current consumption of the module in this mode. The longer the DRX cycle is, the lower the current consumption will be. RG500L_Series_QuecOpen_Hardware_Design 28 / 110 5G Module Series Figure 2: DRX Run Time and Current Consumption in Sleep Mode 3.2.1. UART Application Scenario If the host communicates with the module via UART interface, the following precondition should be met to set the module into sleep mode:

Execute AT+QSCLK=1 command to enable sleep mode, for more details, see Chapter 9.2. 3.2.2. USB Application Scenario[JW4]

If the host communicates with the module via USB interface, the following precondition should be met to set the module into sleep mode:

Execute AT+QSCLK=1 command to enable sleep mode, for more details, see Chapter 9.2. 3.3. Airplane Mode When the module enters airplane mode, the RF function will be disabled, and all AT commands related to it will be inaccessible. This mode can be set via AT+CFUN. AT+CFUN=<fun> command provides choices of the functionality level by setting <fun> into 0, 1 or 4. AT+CFUN=0: Minimum functionality (disable RF function and (U)SIM function). AT+CFUN=1: Full functionality (default). AT+CFUN=4: Airplane mode (disable RF function). NOTE RG500L_Series_QuecOpen_Hardware_Design 29 / 110 CurrentRun TimeDRX OFF ON OFF ON ON OFF OFFON OFF 5G Module Series The execution of AT+CFUN command will not affect GNSS function. For more details about AT commands, see Chapter 9.1. 3.4. Power Supply 3.4.1. Power Supply Pins The module provides 7 VBAT pins dedicated to the connection with the external power supply and provides power supply for external GPIOs pull-up circuits with VDD_EXT. There are two separate voltage domains for VBAT and one voltage for external circuits. Four VBAT_RF1 pins for RF part. Three VBAT_BB pins for baseband part. One VDD_EXT pin for external GPIOs pull-up circuits Table 8: Pin Definition of Power Supply Pin Name Pin No. I/O Description Comment VBAT_BB 235, 236, 238 PI VBAT_RF1 229, 230, 232, 233 PI Power supply for the modules baseband part Power supply for the modules RF part VDD_EXT 66 PO Provide 1.8 V for external circuit Power supply for external GPIOs pull-up circuits. 3.4.2. Reference Design for Power Supply The performance of the module largely depends on the power source. The power supply of the module should be able to provide sufficient current of 4.5 A at least. If the voltage difference between input and output is not too high, it is suggested that an LDO should be used to supply power to the module. If there is a big voltage difference between input and the desired output VBAT, a buck converter is preferred as the power supply. The following figure illustrates a reference design for +5 V input power source. RG500L_Series_QuecOpen_Hardware_Design 30 / 110 5G Module Series Figure 3: Reference Design of Power Supply 3.4.3. Requirements for Voltage Stability The power supply range of the module is from 3.3 V to 4.3 V. Please make sure the input voltage will never drop below 3.3 V. Figure 4: Power Supply Limits during Burst Transmission To decrease voltage drop, a bypass capacitor of about 470 F with low ESR (ESR = 0.7 ) should be used, and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low ESR. It is recommended to use ceramic capacitors for composing the MLCC array, and place these capacitors close to VBAT pins. The main power supply from an external application must be a single voltage source and can be expanded to two sub paths with the star structure. The width of VBAT_BB trace should be no less than 2.5 mm. The width of VBAT_RF trace should be no less than 3 mm. In principle, the longer the VBAT trace is, the wider it should be. In addition, to ensure the stability of the power supply, it is necessary to add a high-power TVS diode at the front end of the power supply. Reference circuit is shown as below:

RG500L_Series_QuecOpen_Hardware_Design 31 / 110 C422 FC5100 nFR4 100KR620KR575KL1 2.2 HDC_3V8U1GNDSWSWSWVOSPGFBFSWDEFAGNDPVINPVINPVINENSS/TRPGNDPGNDVCC_5 VC63.3 nFR351KQ1R2 47KR1 4.7K C210 FC1470 FC3100 nFD13V8_ENVBATRippleDropBurst TransmissionBurst Transmission 5G Module Series Figure 5: Star Structure of the Power Supply NOTE To avoid damaging internal flash, do not switch off the power supply when the module works normally. Only after shutting down the module with PWRKEY or PON_1 can you cut off the power supply. 3.5. Turn On 3.5.1. Turn on the Module with PWRKEY Table 9: Pin Definition of PWRKEY Pin Name Pin No. PWRKEY 7 I/O DI Description Comment Turn on/off the module Internally pulled up to 1.8 V. When the module is in power-off mode, you can turn it on to make it enter normal operation mode by driving PWRKEY low for at least 500 ms. It is recommended to use an open drain/collector driver to control PWRKEY. If PWRKEY is kept low for more than 8 s after turning on the module, the module would reset repeatedly.[JW5]

RG500L_Series_QuecOpen_Hardware_Design 32 / 110 220 pFR16.8 nF100 nF 100 nFR2D1VBAT_RF1VBAT_RF2VBAT_BB470 FVBATC1C2C3C4C6C70R0RModule470 F 220 pFC868 pFC9 68 pFC515 pF9.1 pF4.7 pF 100 nF470 F 220 pF68 pF15 pF9.1 pF4.7 pFC10C11C12C13C14C15C16C17C18C19 5G Module Series Figure 6: Reference Circuit of Turing on the Module with Driving Circuit Another way to control PWRKEY is by using a button directly. When pressing the button, an electrostatic strike may be generated from finger. Therefore, a TVS component shall be placed near the button for ESD protection. Figure 7: Reference Circuit of Turing on the Module with Keystroke RG500L_Series_QuecOpen_Hardware_Design 33 / 110 4.7 K47 KQ1GPIOMCUPWRKEYModule 500 ms Turn-on pulse PWRKEYS1Close to S1TVS 5G Module Series The turn-on scenario is illustrated in the following figure. Figure 8: Timing of Turning on the Module

. NOTE 1. Please ensure that VBAT is stable for at least 30 ms before pulling down PWRKEY. 2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins. 3.5.2. Turn on the Module with PON_1 When the module is in power-down mode, you can turn it on to normal mode by driving the PON_1 pin high. Table 10: Pin Definition of PON_1 Pin Name Pin No. PON_1 9 I/O DI Description Turn on/off the module RG500L_Series_QuecOpen_Hardware_Design 34 / 110 VBATPWRKEY 500 msActiveUARTNOTEActiveUSBTBDTBDSTATUSTBDRESET_NOD 5G Module Series 3.6. Turn Off You can use the following ways to turn off the module. 3.6.1. Turn off the Module with PWRKEY You can turn off the module by driving PWRKEY low for at least 1000 ms and then releasing it. The turn-off scenario is illustrated in the following figure. Figure 9: Timing of Turning off the Module 3.6.2. Turn off the Module with PON_1 You can turn off the module by driving PON_1 low. NOTE 1. When turning off the module with PON_1, please keep PWRKEY at a high level after the execution of power-off. Otherwise, the module will be turned on again after power-off. 2. When USB_VBUS is in place, the module always remains in the power-on state. 3. To avoid damaging internal flash, do not switch off the power supply when the module works normally. Only after shutting down the module with PWRKEY or PON_1, can you cut off the power supply. 3.7. Reset You can reset the module by driving RESET_N low for at least 250550 ms* and then releasing it. The RG500L_Series_QuecOpen_Hardware_Design 35 / 110 VBATPWRKEY 1000 msRunningPower-down procedureOFFModuleStatusSTATUSTBD 5G Module Series RESET_N signal is sensitive to interference, so it is recommended to route the trace as short as possible and surround it with ground. Table 11: Pin Definition of RESET_N Pin Name Pin No. RESET_N 8 I/O DI Description Comment Reset the module Internally pulled up to 1.8 V. Active low. The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET_N. Figure 10: Reference Circuit of RESET_N with Driving Circuit Figure 11: Timing of Resetting the Module NOTE 1. Use RESET_N only when you fail to turn off the module with PWRKEY or PON_1. 2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins. RG500L_Series_QuecOpen_Hardware_Design 36 / 110 4.7 K47 KQ1GPIOMCURESET_NModule250550 ms Reset pulse VBATTBDResettingModule StatusRunningRESET_NRestartTBD 5G Module Series 4 Application Interfaces 4.1. USB Interface The module provides one integrated Universal Serial Bus (USB) interface which complies with the USB 3.0/2.0 specifications and supports super speed (5 Gbps) on USB 3.0, high speed (480 Mbps) and full speed (12 Mbps) modes on USB 2.0. The USB interface is used for AT command communication, data transmission, GNSS NMEA* sentence output, software debugging and firmware upgrade. Pin definition of the USB interface is as follows:

Table 12: Pin Definition of USB Interface Pin Name Pin No. I/O Description Comment USB_VBUS 82 AI USB connection detect USB_DP USB_DM 83 85 USB_SS_TX_P 76 USB_SS_TX_M 74 USB_SS_RX_P 79 USB_SS_RX_M 77 USB_ID 75 AIO USB differential data (+) AIO USB differential data (-) AO AO AI AI DI USB 3.0 super-speed transmit (+) USB 3.0 super-speed transmit (-) USB 3.0 super-speed receive (+) USB 3.0 super-speed receive (-) USB ID detect OTG_PWR_EN 80 DO OTG power control Used for USB connection detection

(disabled by default). Cannot be used for power supply. Require differential impedance of 90 . Require differential impedance of 90 . If unused, connect RX to GND directly. RG500L_Series_QuecOpen_Hardware_Design 37 / 110 5G Module Series It is recommended to reserve test points for debugging and firmware upgrading in your design. Figure 12: Reference Circuit of USB Interface To ensure the signal integrity of USB data traces, you must place R1, R2, R3, R4, C1 and C2 close to the module, C3 and C4 close to the device, and keep these resistors close to each other. Keep the extra stubs of traces as short as possible. To meet the USB specifications, the following principles should be complied with when designing the USB interface, It is important to route the USB signal traces as differential pairs with ground surrounded. The impedance of USB 2.0/3.0 differential trace is 90 . For USB 2.0 signal traces, length matching within the differential data pair (between USB_DM and USB_DP) should be less than 0.5 mm. For USB 3.0 signal traces, length matching within each differential data pair (within TX or RX) should be less than 0.125 mm. Do not route signal traces under crystals, oscillators, magnetic devices, PCIe and RF signal traces. It is important to route the USB differential traces in inner-layer of the PCB, and surround the traces with ground on that layer and ground planes above and below. Junction capacitance of the ESD protection components might cause influences on USB data traces, so please pay attention to the selection of the device. Typically, the stray capacitance should be less than 3.0 pF for USB 2.0, and less than 0.5 pF for USB 3.0. If possible, reserve a 0 resistor on USB_DP and USB_DM traces respectively. RG500L_Series_QuecOpen_Hardware_Design 38 / 110 USB_DPUSB_DMGNDUSB_DPUSB_DMGNDR1R2Close to ModuleR3R4Test PointsESD ArrayNM_0RNM_0R0R0RMinimize these stubsModuleUSB_VBUSVBUSUSB_SS_TX_PUSB_SS_TX_MUSB_SS_RX_PUSB_SS_RX_MC1C3C4100 nF100 nF100 nF100 nFUSB_SS_RX_PUSB_SS_RX_MUSB_SS_TX_PUSB_SS_TX_MC2 5G Module Series For more details about the USB specifications, please visit http://www.usb.org/home. NOTE 1. Currently only USB 2.0 interface supports firmware upgrade. 2. When USB_VBUS is in place, the module always remains in the power-on state. 4.2. (U)SIM Interfaces The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both Class B (3.0 V) and Class C

(1.8 V) (U)SIM cards are supported, and Dual SIM Single Standby function is supported. Table 13: Pin Definition of (U)SIM Interfaces Pin Name Pin No. USIM1_VDD USIM1_DATA USIM1_CLK USIM1_RST USIM1_DET USIM2_VDD USIM2_DATA USIM2_CLK USIM2_RST USIM2_DET 245 248 247 244 249 250 251 253 254 252 I/O PO DIO DO DO DI PO DIO DO DO DI Description

(U)SIM1 card power supply

(U)SIM1 card data

(U)SIM1 card clock

(U)SIM1 card reset

(U)SIM1 card hot-plug detect

(U)SIM2 card power supply

(U)SIM2 card data

(U)SIM2 card clock

(U)SIM2 card reset

(U)SIM2 card hot-plug detect The module supports (U)SIM card hot-plug via the USIM_DET pin, which is a level-triggered pin. The hot-plug function is disabled by default. 4.2.1. Normally Closed (U)SIM Card Connector With a normally closed (U)SIM card connector, USIM_DET is normally short-circuited to ground when there is no (U)SIM card inserted. A (U)SIM card insertion will drive USIM_DET from low to high level, and RG500L_Series_QuecOpen_Hardware_Design 39 / 110 5G Module Series the removal of it will drive USIM_DET from high to low level. When the (U)SIM is absent, CD is short-circuited to ground and USIM_DET is at low level. When the (U)SIM is inserted, CD is open from ground and USIM_DET is at high level. The following figure shows a reference design of (U)SIM interface with a normally closed (NC) (U)SIM card connector. Figure 13: Reference Circuit of Normally Closed (U)SIM Card Connector 4.2.2. Normally Open (U)SIM Card Connector With a normally open (U)SIM card connector, USIM_DET is normally open when a (U)SIM card is not inserted. A (U)SIM card insertion will drive USIM_DET from high to low level, and the removal of it will drive USIM_DET from low to high level. When the (U)SIM is absent, CD1 is open from CD2 and USIM_DET is at high level. When the (U)SIM is inserted, CD1 is short-circuited to ground and USIM_DET is at low level. The following figure shows a reference design of (U)SIM interface with a normally open (NO) (U)SIM card connector. RG500L_Series_QuecOpen_Hardware_Design 40 / 110 ModuleUSIM_VDDUSIM_RSTUSIM_CLKUSIM_DATAUSIM_DET33 R33 R33 RVDD_EXT100 K1 F(U)SIM Card ConnectorGNDGNDVCCRSTCLKIOVPPGNDUSIM_VDDNM10 pF10 pF10 pFCD1CD210 pFSwitch1 K 5G Module Series Figure 14: Reference Circuit of Normally Open (U)SIM Card Connector 4.2.3. (U)SIM Card Connector Without Hot-Plug If (U)SIM card detection function is not needed, please keep USIM_DET unconnected. A reference circuit for (U)SIM card interface with a 6-pin (U)SIM card connector without hot-plug function is illustrated in the following figure. Figure 15: Reference Circuit of a 6-Pin (U)SIM Card Connector RG500L_Series_QuecOpen_Hardware_Design 41 / 110 ModuleUSIM_VDDUSIM_RSTUSIM_CLKUSIM_DATAUSIM_DET33 R33 R33 RVDD_EXT100 K1 F(U)SIM Card ConnectorGNDGNDVCCRSTCLKIOVPPGNDUSIM_VDDNM10 pF10 pF10 pFCD1CD210 pFSwitch1 KModuleUSIM_VDDUSIM_RSTUSIM_CLKUSIM_DATA33 R33 R33 R1 F(U)SIM Card ConnectorGNDVCCRSTCLKIOVPPGNDNMUSIM_VDD10 pF10 pF10 pF10 pFESD diode 5G Module Series To enhance the reliability and availability of the (U)SIM card interface in applications, please follow the criteria below in (U)SIM circuit design. Keep (U)SIM card connector as close as possible to the module. Keep the trace length as less than 200 mm as possible. Keep (U)SIM card signal traces away from RF and VCC traces. To avoid crosstalk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with ground surrounded. To offer better ESD protection, it is recommended to add a TVS array with a parasitic capacitance not exceeding 45 pF. The 33 resistors should be added in series between the module and the (U)SIM card connector to suppress EMI spurious transmission and enhance ESD protection. The 10 pF capacitors are used to filter out RF interference. Reserve a 1 F shunt capacitor on the power rails of (U)SIM and place this capacitor close to the

(U)SIM connector. 4.3. I2C Interface The module provides one I2C interface. As an open drain output, I2C interface should be pulled up to 1.8 V. Table 14: Pin Definition of I2C Interface Pin Name Pin No. TP_I2C_SCL 243 TP_I2C_SDA 242 I/O OD OD 4.4. PCM Interfaces Description Comment I2C serial clock I2C serial data Should be externally pulled up to 1.8 V. If unused, keep them open. The module provides two PCM interfaces. The key features of the PCM interfaces are listed below:

Used for audio function with external SLIC Supports long frame synchronization/short frame synchronization Supports master and slave modes, but must be the master in long frame synchronization RG500L_Series_QuecOpen_Hardware_Design 42 / 110 5G Module Series Table 15: Pin Definition of PCM Interfaces Pin Name Pin No. I/O Description Comment PCM0_SYNC*

62 DIO PCM0 data frame sync In master mode, they are output signals. In slave mode, they are input signals. 63 61 59 217 215 212 211 DIO PCM0 clock DI PCM0 data input DO PCM0 data output DIO PCM1 data frame sync DIO PCM1 clock DI PCM1 data input DO PCM1 data output If unused, keep them open. In master mode, they are output signals. In slave mode, they are input signals. If unused, keep them open. PCM0_CLK*

PCM0_DIN*

PCM0_DOUT*

PCM1_SYNC PCM1_CLK PCM1_DIN PCM1_DOUT NOTE PCM1 is used for SLIC by default. 4.5. UART Interfaces The module provides three UART interfaces and the following table shows their features:

Table 16: UART Information UART Types Baud Rate Functions Main UART interface 115200 bps AT command communication and data transmission Debug UART interface 921600 bps Linux console and log output Bluetooth UART interface 115200 bps Bluetooth communication RG500L_Series_QuecOpen_Hardware_Design 43 / 110 5G Module Series Table 17: Pin Definition of UART Interfaces Pin Name Pin No. I/O Description Comment MAIN_CTS MAIN_RTS MAIN_RXD MAIN_TXD BT_TXD BT_RXD BT_RTS BT_CTS DBG_RXD DBG_TXD 201 203 202 200 45 276 48 277 205 206 DO DI DI DO DO DI DI DO DI DO DTE clear to send signal from DCE Connect to DTEs CTS DTE request to send signal to DCE Connect to DTEs RTS Main UART receive Main UART transmit Bluetooth UART transmit Bluetooth UART receive DTE request to send signal to DCE Connect to DTEs RTS DTE clear to send signal from DCE Connect to DTEs CTS Debug UART receive Debug UART transmit The following figure illustrates the reference design for Bluetooth UART interface connection between RG500L series and Wi-Fi/Bluetooth module. Figure 16: Bluetooth UART Interface Connection The module provides 1.8 V UART interfaces. A level shift circuit should be used if the application is equipped with a 3.3 V UART interface. The following figure shows a reference design with voltage level translator chip. RG500L_Series_QuecOpen_Hardware_Design 44 / 110 RG500LBluetoothBT_TXDBT_RXDBT_RTSBT_CTSBT_UART_RXDBT_UART_TXDBT_UART_RTSBT_UART_CTS 5G Module Series Figure 17: Reference Circuit with Level Translator Chip Another example with transistor circuit is shown as below. For the design of circuits shown in dotted lines, see that shown in solid lines, but pay attention to the direction of connection. Figure 18: Reference Circuit with Transistor Circuit NOTE 1. Transistor circuit solution is not suitable for applications with baud rates exceeding 460 kbps. 2. Please note that the module CTS is connected to the device CTS, and the module RTS is connected to the device RTS. RG500L_Series_QuecOpen_Hardware_Design 45 / 110 VCCAVCCBOEA1A2A3A4GNDB1B2B3B4VDD_EXTMAIN_RTSMAIN_RXDMAIN_CTSMAIN_TXD0.1 F0.1 FRXD_MCUCTS_MCUTXD_MCUVDD_MCUTranslatorRTS_MCUMCU/ARMTXDRXDVDD_EXT10 KVDD_MCU4.7 K10 KVDD_EXTMAIN_TXDMAIN_RXDMAIN_RTSMAIN_CTSRTSCTSGNDModuleVDD_EXT4.7 KGND1 nF1 nF 5G Module Series 4.6. SDIO Interface The module provides one SD 3.0 protocol compliant SDIO interface for SD card connection. Table 18: Pin Definition of SDIO Interface Pin Name Pin No. SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 SD_DET SDIO_PU_VDD 67 64 65 71 70 68 69 72 I/O DO Description Comment SD card clock DIO SD card command DIO SDIO data bit 0 DIO SDIO data bit 1 Only used for SD card. DIO SDIO data bit 2 DIO SDIO data bit 3 DI PO SD card hot-plug detect SD card IO pull-up power supply The following figure illustrates a reference design of SD card interface with the module. Figure 19: Reference Circuit of SD Card Interface RG500L_Series_QuecOpen_Hardware_Design 46 / 110 SD Card ConnectorDAT2CD/DAT3CMDVDDCLKVSSDAT0DAT1DETECTIVEModuleSD_DATA3SD_DATA2SD_DATA1SDIO_PU_VDDSD_DATA0SD_CLKSD_CMDSD_DETR1 0 RR7100 KR8100 KR9100 KR10 100KR11 100KR12100 KVDD_EXTVDD_3VR2 0 RR3 0 RR4 0 RR5 0 RR6 0 RC2NMD2C3NMD3C4NMD4C5NMD5C6NMD6C1NMD1C733 pFD7C84.7 F+

5G Module Series To ensure communication performance with SD card, the following design principles should be complied with:

The voltage range of SD card power supply VDD_3V is 2.73.6 V and a sufficient current of up to 0.8 A should be provided. SDIO_PU_VDD is the SDIO bus power domain, which can be used for SD card IO signal pull-up. To avoid jitter of bus, pull up SD_CMD and SD_DATA to SDIO_PU_VDD with R7R11. Value of these resistors can be 10100 k and the recommended value is 100 k. To improve signal quality, it is recommended to add 0 resistors R1 to R6 in series between the module and the SD card connector. The bypass capacitors C1 to C6 are reserved and not mounted by default. All resistors and bypass capacitors should be placed close to the connector. For good ESD protection, it is recommended to add a TVS diode with capacitance value less than 3 pF on each SD card pins. It is important to route the SDIO signal traces with ground surrounded. The impedance of SDIO data trace is 50 (10 %). Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals, etc., as well as noisy signals such as clock signals, DC-DC signals, etc. It is recommended to keep the trace length difference between SD_CLK and SD_DATA/CMD less than 7.7 mm and the total routing length less than 102 mm. The total trace length inside the module is 18 mm, so the exterior total trace length should be less than 84 mm. Ensure the adjacent trace spacing is two times the trace width and the load capacitance of SDIO bus should be less than 5 pF. NOTE For SD 3.0 SDR104 mode, a sufficient current of up to 800 mA and a 4.7 F capacitor for the power supply is necessary. 4.7. ADC Interfaces The module provides three Analog-to-Digital Converter (ADC) interfaces. To improve the accuracy of ADC, the traces of ADC interfaces should be surrounded by ground. Table 19: Pin Definition of ADC Interfaces Pin Name Pin No. I/O Description Comment ADC0 241 AI General-purpose ADC interface Max input 1.78 V. If unused, connect it to GND directly. RG500L_Series_QuecOpen_Hardware_Design 47 / 110 5G Module Series ADC1 ADC2 135 138 AI AI General-purpose ADC interface General-purpose ADC interface Max input 1.45 V. If unused, connect them to GND directly. The voltage value on ADC pins can be read via AT+QADC=<port>* command:

AT+QADC=0: read the voltage value on ADC0 AT+QADC=1: read the voltage value on ADC1 AT+QADC=2: read the voltage value on ADC2 For more details about the AT command, see Chapter 9.3. The resolution of the ADC interfaces is up to 12 bits. The following table describes the voltage range of the ADC interfaces. Table 20: Voltage Range of ADC Interfaces Min. 0.04 0.05 0.05 ADC Interfaces ADC0 ADC1 ADC2 NOTE Max. 1.78 1.45 1.45 Unit V V V 1. The input voltage of ADC should not exceed its corresponding voltage range. It is prohibited to supply any voltage to ADC pin when VBAT is removed. 2. It is recommended to use voltage divider circuit for ADC application. 3. RG500L_Series_QuecOpen_Hardware_Design 48 / 110 5G Module Series 4.8. LCM Interface The module provides an LCM interface, the pin definition of the LCM interface is shown below. Table 21: Pin Definition of LCM Interface Pin Name Pin No. LSDI LSA0 LSCE0B LSRSTB LSCK LSDA PWM LCD_TE LCD_RST 102 108 105 422 114 111 88 99 93 I/O DI DO DO DO DO DO DO DI DO Description SPI serial input data Indicate transmission of data or command SPI chip select SPI reset SPI serial clock SPI serial output data PWM output

(For LCD only) LCM tearing effect LCM reset The following figures show the reference design for LCM interface. Figure 20: Reference Circuit Design for LCM Interface RG500L_Series_QuecOpen_Hardware_Design 49 / 110 LCMSCLKSDILSCKLCD_TELSA0LSRSTBSDORESETGNDModuleGNDTERSCSLSDALSCE0BLSDI 5G Module Series Figure 21: Reference Circuit of LCM External Backlight Driver 4.9. SGMII Interfaces The module includes two integrated Ethernet MAC with two SGMII interfaces and one MDIO management interface. Key features of the SGMII interfaces are shown below:

IEEE 802.3 compliant Full duplex mode for 10/100/1000/2500 Mbps Can be connected to an external Ethernet Switch or PHY, such as MT7531AE and RTL8221B The MDIO management interface and SGMII interrupt/reset signals support 1.8 V power domain Table 22: Pin Definition of SGMII Interfaces Pin Name Pin No. MDIO_DATA MDIO_CLK EPHY0_INT_N EPHY0_RST_N EPHY1_INT_N EPHY1_RST_N SGMII0_RX_M SGMII0_RX_P 267 265 410 411 258 261 5 4 I/O DIO DO DI DO DI DO AI AI Description Comment MDIO data MDIO clock SGMII0 interrupt SGMII0 reset SGMII1 interrupt SGMII1 reset SGMII0 receive (-) SGMII0 receive (+) Require differential impedance of 100 . RG500L_Series_QuecOpen_Hardware_Design 50 / 110 LCM_LED+Module2.2 FBacklight DriverLCM_LED-VPH_PWRC1PWMGND 5G Module Series SGMII0_TX_P SGMII0_TX_M SGMII1_RX_M SGMII1_RX_P SGMII1_TX_P SGMII1_TX_M 1 2 260 262 264 263 AO AO AI AI AO AO SGMII0 transmit (+) SGMII0 transmit (-) SGMII1 receive (-) SGMII1 receive (+) SGMII1 transmit (+) SGMII1 transmit (-) If unused, connect RX to GND directly. Figure 22: Reference Circuit of SGMII Interface with PHY Application To enhance the reliability and availability of customers application, please follow the criteria below in the Ethernet PHY circuit design:

Keep SGMII data and control signals away from RF and VBAT traces. Keep the maximum trace length less than 150 mm and keep length matching within each differential pair less than 0.125 mm. The differential impedance of SGMII data traces is 100 10%. To minimize crosstalk, the distance between separate adjacent pairs on the same layer must be equal to or larger than 1 mm. Less than 2 vias should be designed in each differential pair. Reserve enough GND plane between MDC and MDIO to prevent crosstalk. RG500L_Series_QuecOpen_Hardware_Design 51 / 110 MDIO_DATAEPHY_INT_NMDIORSTNMDCR1R2NMVDD_EXTModule PHYEPHY_RST_NINTMDIO_CLKSGMII_TX_MSGMII_TX_PSGMII_RX_PSGMII_RX_MRX_PRX_MTX_PTX_MControlSGMII Data10 K100 nF100 nF100 nF100 nF 5G Module Series 0.1 F AC coupling capacitors should be placed close to the transmitter source. 4.10. SPI Interfaces The module provides two SPI interfaces which supports slave mode* and master mode with a maximum clock frequency of up to 52 MHz. Table 23: Pin Definition of SPI Interfaces Pin Name Pin No. I/O Description Comment SPI0_CS*

SPI0_CLK*

255 257 SPI0_MOSI*

259 SPI0_MISO*

256 SPI3_CS SPI3_CLK 218 220 SPI3_MOSI 223 SPI3_MISO 221 DO DO DO DI DO DO DO DI SPI0 chip select SPI0 clock SPI0 master-out slave-in SPI0 master-in salve-out SPI3 chip select SPI3 clock SPI3 master-out slave-in SPI3 master-in salve-out The module provides 1.8 V SPI interfaces. A level translator between the module and the host should be used if the application is equipped with a 3.3 V processor or device interface. Figure 23: Reference Circuit of SPI Interface with a Level Translator RG500L_Series_QuecOpen_Hardware_Design 52 / 110 VCCAVCCBOEA1A2A3A4NCGNDB1B2B3B4NCVDD_EXTSPI_CSSPI_CLKSPI_MISOSPI_MOSI0.1 F0.1 FSPI_CS_N_MCUSPI_CLK_MCUSPI_MISO_MCUSPI_MOSI_MCUVDD_MCUTranslator 5G Module Series 4.11. PCIe Interfaces The module provides four integrated PCIe (Peripheral Component Interconnect Express) interfaces which follow PCI Express Base Specification Revision 3.0. The key features of the PCIe interfaces are listed below:

PCI Express Base Specification Revision 3.0 compliant Data rate at 8 Gbps per lane Only supports Root Complex mode Can be used to connect to an external Ethernet IC (MAC and PHY) or WLAN IC Table 24: Pin Definition of PCIe Interfaces Pin Name Pin No. I/O Description Comment PCIE0_REFCLK_P PCIE0_REFCLK_M PCIE0_TX_M PCIE0_TX_P PCIE0_RX_M PCIE0_RX_P 56 55 50 49 52 53 PCIE0_CLKREQ_N 281 PCIE0_RST_N PCIE0_WAKE_N PCIE1_REFCLK_P PCIE1_REFCLK_M PCIE1_TX0_M PCIE1_TX0_P PCIE1_RX0_M PCIE1_RX0_P 54 60 46 44 34 32 38 40 PCIE1_CLKREQ_N 273 AO AO AO AO AI AI DI DO DI AO AO AO AO AI AI DI PCIe0 reference clock (+) PCIe0 reference clock (-) PCIe0 transmit (-) PCIe0 transmit (+) PCIe0 receive (-) PCIe0 receive (+) PCIe0 clock request PCIe0 reset PCIe0 wake up PCIe1 reference clock (+) PCIe1 reference clock (-) PCIe1 transmit (-) PCIe1 transmit (+) PCIe1 receive (-) PCIe1 receive (+) PCIe1 clock request Require differential impedance of 85 . PCIe Gen3 compliant. If unused, connect RX to GND directly. Require differential impedance of 85 . PCIe Gen3 compliant. If unused, connect RX to GND directly. RG500L_Series_QuecOpen_Hardware_Design 53 / 110 5G Module Series PCIE1_RST_N PCIE1_WAKE_N PCIE2_REFCLK_P PCIE2_REFCLK_M PCIE2_TX_M PCIE2_TX_P PCIE2_RX_M PCIE2_RX_P PCIE2_CLKREQ_N PCIE2_RST_N 27 30 29 28 25 26 22 23 21 18 PCIE2_WAKE_N 270 PCIE3_REFCLK_P*

PCIE3_REFCLK_M*

PCIE3_TX_M*

PCIE3_TX_P*

PCIE3_RX_M*

PCIE3_RX_P*

PCIE3_CLKREQ_N*

PCIE3_RST_N*

PCIE3_WAKE_N*

13 11 14 16 17 19 15 269 268 DO DI AO AO AO AO AI AI DI DO DI AO AO AO AO AI AI DI DO DI PCIe1 reset PCIe1 wake up PCIe2 reference clock (+) PCIe2 reference clock (-) PCIe2 transmit (-) PCIe2 transmit (+) PCIe2 receive (-) PCIe2 receive (+) PCIe2 clock request PCIe2 reset PCIe2 wake up PCIe3 reference clock (+) PCIe3 reference clock (-) PCIe3 transmit (-) PCIe3 transmit (+) PCIe3 receive (-) PCIe3 receive (+) PCIe3 clock request PCIe3 reset PCIe3 wake up Require differential impedance of 85 . PCIe Gen3 compliant. If unused, connect RX to GND directly. Require differential impedance of 85 . PCIe Gen3 compliant. If unused, connect RX to GND directly. RG500L_Series_QuecOpen_Hardware_Design 54 / 110 5G Module Series The following figure illustrates the PCIe interface connection. Figure 24: Reference Circuit of PCIe Interface The following principles of PCIe interface design should be complied with to meet PCIe specifications. It is important to route the PCIE_TX/RX/REFCLK signal traces as differential pairs with ground surrounded. The differential impedance is 85 is recommended. PCIe signals must be protected from noisy signals (clocks, DC-DC, RF and so forth). All other sensitive/high-speed signals and circuits must be routed far away from PCIe traces. For each differential pair, intra-lane length matching should be less than 0.125 mm. Inter-lane length matching, that is, (the trace length matching between the PCIE_TX/RX/REFCLK pairs) is not required. The PCIe inter-lane spacing, and the spacing between PCIe lanes and all other signals, should be larger than 4 times the trace width. It is better to place the PCIe AC coupling capacitors close to the transmitter source. Ensure not to stagger the capacitors. This can affect the differential integrity of the design and can create EMI. PCIe TX AC coupling capacitors should be 220 nF for Gen 3, and 100 nF is recommended for Gen 2 application. To reduce the probability for layer-to-layer manufacturing variation, minimize layer transitions on the main route (in other words, apply layer transitions only at module breakouts and connectors to RG500L_Series_QuecOpen_Hardware_Design 55 / 110 PCIE_TX_MPCIE_TX_PPCIE_RST_NPCIE_RX_PRG500LPCIE_REFCLK_MPCIE_REFCLK_PPCIE_WAKE_NPCIE_CLKREQ_NPCIE_RX_MPCIE_CLKREQ_NPCIE_WAKE_NPCIE_RST_NPCIE_REFCLK_PPCIE_REFCLK_MPCIE_RX_MPCIE_RX_PPCIE_TX_PPCIE_TX_MR1100KR2100KVDD_EXTC1220nFC2220nFC3220nFC4220nFR3NM_100KDeviceR449.9 R +/-1%R449.9 R +/-1%R549.9 R +/-1%R549.9 R +/-1%

5G Module Series ensure minimum layer transitions on the main route). Hardware acceleration is supported by PCIe0 and PCIe1 only. For the PCIE_REFCLK pair, add resistors near the slot (EP) side and the recommended resister value is 49.9 +/-1 %. 4.12. WWAN/WLAN Control Interface Table 25: Pin Definition of WWAN/WLAN Control Interface Pin Name Pin No. I/O Description Comment WLAN_SYSRST_5G 271 DO WLAN 5 GHz system reset WIFI_2.4G_EN*

272 DO WLAN 2.4 GHz function enable control Reserved. WLAN_SYSRST_2.4G 274 DO WLAN 2.4 GHz system reset WLAN_5G_EN*

406 DO WLAN 5 GHz function enable control Reserved. BT_ACT_TXD 8 36 DO BT_PRI_RXD 8 275 DO WLAN_ACT 39 DI PTA_TX 279 DO PTA_RX 278 DO GPIO_15 280 DI Coexistence interface for WWAN and 5 GHz Wi-Fi Coexistence interface for WWAN and 5 GHz Wi-Fi Coexistence interface for WWAN and 5 GHz Wi-Fi Coexistence interface for WWAN and 2.4 GHz Wi-Fi Coexistence interface for WWAN and 2.4 GHz Wi-Fi Coexistence interface for WWAN and 2.4 GHz Wi-Fi Used for WWAN/WLAN coexistence by default. Used for WWAN/WLAN coexistence by default. 8 Please note that this pin is for WWAN and Wi-Fi coexistence function, not for WWAN and Bluetooth coexistence function. RG500L_Series_QuecOpen_Hardware_Design 56 / 110 5G Module Series 4.13. USB_BOOT Interface Table 26: Pin Definition of USB_BOOT Interface Pin Name Pin No. I/O Description USB_BOOT 81 DI Force the module into emergency download mode The module provides a USB_BOOT pin. You can pull up USB_BOOT to VDD_EXT before powering on the module, and then the module will enter emergency download mode when powered on. In this mode, the module supports firmware upgrade over USB 2.0 interface. Figure 25: Reference Circuit of USB_BOOT Interface NOTE It is not recommended to pull up USB_BOOT to 1.8 V before powering up VBAT. Directly connecting the test points as shown in the above figure can manually force the module to enter download mode. RG500L_Series_QuecOpen_Hardware_Design 57 / 110 ModuleUSB_BOOTTVSTVS1 KVDD_EXTTest pointClose to test point 5G Module Series 4.14. Control Signals Table 27: Pin Definition of Control Signals Pin Name Pin No. RESTORE_KEY WPS_KEY*

207 204 I/O DI DI Description Restore the module Wi-Fi protected setup Reference circuit is shown as below. Figure 26: Reference Circuit of KEY 4.15. Indication Signals Table 28: Pin Definition of Indication Signals Pin Name Pin No. I/O Description Comment STATUS 222 OD Indicate the module's operation status PMIC_ISINK3 NET_MODE*

219 DO Indicate the module's network registration mode NET_STATUS*

239 OD Indicate the module's network activity status PMIC_ISINK2 AIR_MODE*

225 OD Indicate the module's airplane mode PMIC_ISINK1 WIFI_MESH*

210 DO Indicate the Wi-Fi mesh function status RG500L_Series_QuecOpen_Hardware_Design 58 / 110 S2TVSClose to S2KEY 5G Module Series USIM_LED*

216 DO Indicate the (U)SIM card function status VOIP_LED*

213 DO Indicate the VoIP function status 4.15.1. STATUS The STATUS pin is an open drain output to indicate the modules operation status. It will output low level when the module is powered ON successfully. A reference circuit is shown as below. Figure 27: Reference Circuit of STATUS Indicator 4.15.2. Network Status Indication*

The network indication pins can be used to drive network status indication LEDs. The module provides two network indication pins: NET_MODE and NET_STATUS. The following tables describe pin definition and logic level changes in different network status. Table 29: Working Mechanism of Network Registration Mode/Network Activity Indication Pin Name Status Description NET_MODE Always High Always Low Registered on 5G network Others Flicker slowly (200 ms High/1800 ms Low) Network searching NET_STATUS Flicker slowly (1800 ms High/200 ms Low) Idle RG500L_Series_QuecOpen_Hardware_Design 59 / 110 VBAT2.2KModule STATUS 5G Module Series Flicker quickly (125 ms High/125 ms Low) Data transfer is ongoing Always High Voice calling Reference circuit is shown as below. Figure 28: Reference Circuit of NET_MODE Indicator Figure 29: Reference Circuit of NET_STATUS Indicator 4.15.3. AIR_MODE*

The AIR_MODE pin is an open drain output for indicating the modules flight mode status. It will output low level when the module enters airplane mode successfully. RG500L_Series_QuecOpen_Hardware_Design 60 / 110 NET_MODEModuleVBAT4.7 K47 K2.2 KVBAT2.2KModuleNET_STATUS 5G Module Series A reference circuit is shown as below. Figure 30: Reference Circuit of AIR_MODE Indicator 4.15.4. Other Indication Signals*

The WIFI_MESH, USIM_LED and VOIP_LED pins are output signals for indicating the functional state of the module. A reference circuit is shown as below. Figure 31: Reference Circuit of Other Indicators RG500L_Series_QuecOpen_Hardware_Design 61 / 110 VBAT2.2KModuleAIR_MODEIndicatorModuleVBAT4.7 K47 K2.2 K 5G Module Series 5 RF Specifications 5.1. Cellular Network 5.1.1. Antenna Interfaces & Frequency Bands The module provides 8 cellular antenna interfaces and the pin definition is shown below:

Table 30: Pin Definition of Cellular Antenna Interfaces Pin Name Pin No. I/O Description Comment ANT0 ANT1 ANT2 ANT3 ANT4 ANT5 ANT6 ANT7 121 130 139 148 157 166 175 184 AIO AIO AI AI AI AI AIO AIO Antenna 0 interface Antenna 1 interface Antenna 2 interface Antenna 3 interface Antenna 4 interface Antenna 5 interface Antenna 6 interface Antenna 7 interface 50 impedance. RG500L_Series_QuecOpen_Hardware_Design 62 / 110 5G Module Series Table 31: Operating Frequency of RG500L-EU Operating Frequency Transmit

(MHz) Receive

(MHz) 5G NR LTE UMTS IMT (2100) 19201980 21102170 n1 DCS (1800) 17101785 18051880 n3 Cell (850) 824849 869894 n5 IMT-E (2600) 25002570 26202690 n7 EGSM (950) 880915 925960 n8 EU800 832862 791821 700 APAC 703748 758803 n20 n28 L-band

14521496 B38 B40 25702620 25702620 n38 23002400 23002400 n40 B41/B41-XGP 24962690 24962690 n41 B42 B43 n77 n78 34003600 34003600 36003800 36003800 33004200 33004200 n77 33003800 33003800 n78 B1 B5 B8 B1 B3 B5 B7 B8 B20 B28 B32 B38 B40 B41 B42 B43 Table 32: Operating Frequency of RG500L-NA Operating Frequency Transmit

(MHz) Receive

(MHz) 5G NR LTE UMTS PCS (1900) 18501910 19301990 n2 B4 17101755 21102155

Cell (850) 824849 869894 n5 IMT-E (2600) 25002570 26202690 n7 B2 B4 B5 B7 B12 699716 729746 n12 B12

RG500L_Series_QuecOpen_Hardware_Design 63 / 110 5G Module Series B13 B14 B17 B25 B26 B29 B30 B38 B41 B42 B43 B46 B48 B66 B71 n77 n78 777787 746756 788798 758768 704-716 734746

1850-1915 1930-1995 n25 814-849 859-894

717-728 2305-2315 2350-2360

2570-2620 2570-2620 n38 2496-2690 2496-2690 n41 3400-3600 3400-3600 3600-3800 3600-3800

5150-5925

3550-3700 3550-3700 n48 1710-1780 2110-2200 n66 663-698 617-652 n71 33004200 33004200 n77 33003800 33003800 n78 B13 B14 B17 B25 B26 B29 B30 B38 B41

B43 B46 B48 B66 B71

RG500L_Series_QuecOpen_Hardware_Design 64 / 110 5G Module Series Table 33: RG500L-EU Cellular Antenna Mapping Antenna WCDMA LTE LB (MHz) MHB (MHz) n77/n78 (MHz) Pin No. Refarmed n41 n77/n78 5G NR ANT0 B42/B43_TRX n77/n78 TRX0 33004200 121 ANT1 B1 TRX MHB TRX0 9 n1/n3/n7/n38/n40 TRX0 n28 TRX0 10 TRX0 703803 17102700 ANT2 ANT3 B42/B43 DRX1 B42/B43 PRX1 n77/n78 DRX0 n77/n78 PRX1 33004200 33004200 MHB DRX1 n1/n3/n7/n38/n40 ANT4 B5/B8 DRX LB DRX DRX1 DRX0 703960 14502700 B32 DRX n5/n8/n20/n28 DRX ANT5 ANT6 ANT7 MHB PRX1 n1/n3/n7/n38/n40 PRX1 PRX0 14502700 B42/B43 DRX n77/n78 TRX1 33004200 B1 DRX MHB TRX1 9 B5/B8 TRX LB TRX0 n1/n3/n7/n38/n40 TRX1 n28 TRX1 10 n5/n8/n20 TRX0 TRX1 703960 17102700 130 139 148 157 166 175 184 9 LTE MHB TRX is activated when 5G NR FDD middle/high bands are supported in NSA mode. 10 n28 TRX is activated when 5G NR FDD low bands are supported in NSA mode. RG500L_Series_QuecOpen_Hardware_Design 65 / 105 5G Module Series Table 34: RG500L-NA Cellular Antenna Mapping Antenna LTE 5G NR Refarmed n41 n48/n77/n78 LB (MHz) MHB (MHz) n48/n77/n78

(MHz) Pin No. ANT0 B42/B43/B48 TRX0 n48/n77/n78 TRX0 33004200 121 n2/n7/n25/n38/n66 TX0 n2/n7/n25/n38/n66 DRX0 TRX0 814894 17102690 130 n5 TRX ANT1 ANT2 ANT3 MHB DRX0 B5/B26 TRX MHB TRX0 9 B46 PRX1 B42/B43/B48 PRX1 B46 DRX1 B42/B43/B48 DRX1 B12/B13/B14/B17/B71 DRX ANT4 MHB DRX1 ANT5 B29 DRX1 MHB PRX1 B5/B26 DRX ANT6 B42/B43/B48 DRX0 n2/n7/n25/n38/n66 DRX1 n12/n71 DRX n2/n7/n25/n38/n66 PRX1 n5 DRX B12/B13/B14/B17/B71 TRX n12/n71 TRX ANT7 MHB TRX0 9 n2/n7/n25/n38/n66 TX1 B29 PRX1 n2/n7/n25/n38/n66 PRX0 n48/n77/n78 PRX1 51505925 33004200 139 n48/n77/n78 DRX1 51505925 33004200 148 DRX1 PRX1 TX1 DRX0 617798 17102690 814894 17102690 157 166 n48/n77/n78 TX1 n48/n77/n78 DRX0 33004200 175 617798 17102690 184 NOTE TRX0/1 = TX + PRX/DRX; DRX1 = DRX MIMO; PRX1 = PRX MIMO RG500L_Series_QuecOpen_Hardware_Design 66 / 105 5G Module Series 5.1.2. Tx Power The following table shows the RF output power of the module. Table 35: RG500L Series Tx Power Bands WCDMA bands LTE bands 5G NR bands Max. Power Class 24 dBm +1/-3 dB 23 dBm 2 dB 23 dBm 2 dB PC3 PC3 PC3 PC2 5G NR n41/n77/n78 bands UL MIMO HPUE 11 26 dBm +2/-3 dB 5.1.3. Rx Sensitivity The following table shows conducted RF receiving sensitivity of the module. Table 36: Conducted RF Receiving Sensitivity of RG500L-EU Frequency Receiving Sensitivity (Typ.) Primary Diversity SIMO 3GPP Requirement

(SIMO 12) LTE-FDD B1 (10 MHz)

-98.0 LTE-FDD B3 (10 MHz)

-98.5

-98.5

-99.0

-102.0

-96.3 dBm

-102.0

-93.3 dBm LTE-FDD B5 (10 MHz)

-99.0

-101.0

-102.0

-94.3 dBm LTE-FDD B7 (10 MHz)

-96.5

-97.5

-100.0

-94.3 dBm LTE-FDD B8 (10 MHz)

-99.0

-100.0

-102.0

-93.3 dBm LTE-FDD B20 (10 MHz)

-98.5

-100.5

-101.5

-93.3 dBm LTE-FDD B28 (10 MHz)

-98.5 LTE-TDD B38 (10 MHz)

-98.5

-98.0

-98.0

-101.5

-94.3 dBm

-101.0

-96.3 dBm 11 HPUE is only for single carrier. 12 SIMO is a smart antenna technology that uses a single antenna at the transmitter side and multiple antennas at the receiver side, which improves Rx performance. RG500L_Series_QuecOpen_Hardware_Design 67 / 110 5G Module Series LTE-TDD B40 (10 MHz)

-98.5 LTE-TDD B41 (10 MHz)

-97.5 LTE-TDD B42 (10 MHz)

-99.0 LTE-TDD B43 (10 MHz)

-99.0 5G NR-FDD n1 (20 MHz)

(SCS: 15 kHz) 5G NR-FDD n3 (20 MHz)

(SCS: 15 kHz) 5G NR-FDD n5 (10 MHz)

(SCS: 15 kHz) 5G NR-FDD n7 (20 MHz)

(SCS: 15 kHz) 5G NR-FDD n8 (10 MHz)

(SCS: 15 kHz) 5G NR-FDD n20 (10 MHz)

(SCS: 15 kHz) 5G NR-FDD n28 (10 MHz)

(SCS: 15 kHz) 5G NR-TDD n38 (20 MHz)

(SCS: 30 kHz) 5G NR-TDD n40 (20 MHz)

(SCS: 30 kHz) 5G NR-TDD n41 (100 MHz)

(SCS: 30 kHz) 5G NR-TDD n77 (100 MHz)

(SCS: 30 kHz) 5G NR-TDD n78 (100 MHz)

(SCS: 30 kHz)

-97

-96

-97

-96

-96

-97

-96

-97

-95

-91

-89

-89

-97.0

-97.5

-99.0

-98.5

-97

-96

-97

-96

-96

-97

-96

-97

-95

-91

-89

-89

-100.0

-96.3 dBm

-101.0

-94.3 dBm

-103.0

-95 dBm

-101.5

-95 dBm

-100

-94 dBm

-99

-91 dBm

-100

-95 dBm

-99

-99

-92 dBm

-94 dBm

-100

-94 dBm

-99

-96 dBm

-100

-94 dBm

-98

-94

-92

-92

-94 dBm

-92 dBm

-85 dBm

-85 dBm Table 37: Conducted RF Receiving Sensitivity of RG500L-NA Frequency Receiving Sensitivity (Typ.) Primary Diversity SIMO 3GPP Requirement

(SIMO13) LTE-FDD B2 (10 MHz)

-99.0 LTE-FDD B4 (10 MHz)

-98.0

-99.0

-98.0

-102.0

-94.3 dBm

-101.0

-96.3 dBm 13 SIMO is a smart antenna technology that uses a single antenna at the transmitter side and multiple antennas at the receiver side, which improves Rx performance. RG500L_Series_QuecOpen_Hardware_Design 68 / 110 5G Module Series LTE-FDD B5 (10 MHz)

-100.0

-100.0

-103.0

-94.3 dBm LTE-FDD B7 (10 MHz)

-97.0 LTE-FDD B12 (10 MHz)

-99.0 LTE-FDD B13 (10 MHz)

-98.0 LTE-FDD B14 (10 MHz)

-99.0 LTE-FDD B17 (10 MHz)

-99.0 LTE-FDD B25 (10 MHz)

-99.0

-97.0

-99.0

-98.0

-99.0

-99.0

-99.0

-100.0

-94.3 dBm

-102.0

-93.3 dBm

-101.0

-93.3 dBm

-102.0

-93.3 dBm

-102.0

-93.3 dBm

-102.0

-92.8 dBm LTE-FDD B26 (10 MHz)

-100.0

-100.0

-103.0

-93.8 dBm LTE-FDD B30 (10 MHz)

-97.0 LTE-TDD B38 (10 MHz)

-98.0 LTE-TDD B41 (10 MHz)

-96.0 LTE-TDD B42 (10 MHz)

-98.0 LTE-TDD B43 (10 MHz)

-97.5 LTE-TDD B48 (10 MHz)

-98.0 LTE-FDD B66 (10 MHz)

-97.5

-97.0

-98.5

-96.5

-97.5

-97.0

-97.0

-98.0

-100.0

-95.3 dBm

-101.0

-96.3 dBm

-99.0

-94.3 dBm

-101.0

-95.0 dBm

-100.5

-95.0 dBm

-100.5

-95.0 dBm

-100.5

-95.8 dBm LTE-FDD B71 (10 MHz)

-100.0

-101.0

-103.0

-93.5 dBm

-100

-100 5G NR-FDD n2 (10 MHz)

(SCS: 15 kHz) 5G NR-FDD n5 (10 MHz)

(SCS: 15 kHz) 5G NR-FDD n7 (10 MHz)

(SCS: 15 kHz) 5G NR-FDD n12 (10 MHz)

(SCS: 15 kHz) 5G NR-FDD n25 (10 MHz)

(SCS: 15 kHz) 5G NR-TDD n38 (10 MHz)

(SCS: 30 kHz) 5G NR-TDD n41 (100 MHz)

(SCS: 30 kHz) 5G NR-TDD n48 (100 MHz)

(SCS: 30 kHz)

-97

-97

-97

-97

-98

-88

-89 5G NR-FDD n66 (10 MHz)

-98

-97

-97

-97

-97

-98

-88

-89

-98

-103

-100

-100

-100

-100

-101

-91

-92

-94.8 dBm

-94.8 dBm

-94.8 dBm

-93.8 dBm

-93.3 dBm

-97.1 dBm

-84.7 dBm

-86.7

-101

-96.3 dBm RG500L_Series_QuecOpen_Hardware_Design 69 / 110 5G Module Series

(SCS: 15 kHz) 5G NR-FDD n71 (10 MHz)

(SCS: 15 kHz) 5G NR-TDD n77 (100 MHz)

(SCS: 30 kHz) 5G NR-TDD n78 (100 MHz)

(SCS: 30 kHz)

-97

-90

-90 5.1.4. Reference Design

-97

-90

-90

-100

-94 dBm

-93

-93

-85.1 dBm

-85.6 dBm The module provides 8 cellular antenna interfaces for antenna connection. It is recommended to reserve a -type matching circuit for better RF performance, and the -type matching components should be placed as close to the antenna as possible. The capacitors are not mounted by default. Figure 32: Reference Circuit for Cellular Antenna Interfaces

. NOTE 1. Use a -type circuit for all the antenna circuits to facilitate future debugging. 2. Keep the characteristic impedance of the cellular antenna (ANT0ANT7) traces as 50 . 3. Keep at least 15 dB isolation between RF antennas to improve the receiving sensitivity, and at least 20 dB isolation between 5G NR UL MIMO antennas. 4. Keep 75 dB isolation between each two antenna traces. 5. Keep digital circuits such as switch mode power supply, (U)SIM card, USB interface, camera RG500L_Series_QuecOpen_Hardware_Design 70 / 110 ANT0R10RC1NMC2NMR70RC13NMC14NMANT7Module 5G Module Series module, display connector and SD card away from the antenna traces. The characteristic impedance depends on the dielectric of PCB, the track width and theground plane spacing. Microstrip type is required. The detail simulation as below. The RF trace of the test board which was used in the FCC test is defined as below. Ant0~7 share the same design. 5.2. GNSS The module includes a fully integrated global navigation satellite system solution that supports GPS/BeiDou/GLONASS/Galileo. The module supports NMEA 0183 protocol, and outputs NMEA* sentences via USB interface (data update rate: 15 Hz, 1 Hz by default). For more details about configuration of GNSS function, see document [2]. RG500L_Series_QuecOpen_Hardware_Design 71 / 110 5G Module Series 5.2.1. Antenna Interface & Frequency Bands The following table shows the pin definition, frequency, and performance of GNSS antenna interface. Table 38: Pin Definition of GNSS Antenna Interface Pin Name Pin No. ANT_GNSS 193 I/O AI Description Comment GNSS antenna interface 50 impedance. Table 39: GNSS Frequency Type GPS Frequency 1575.42 1.023 (GPS L1) 1176.45 10.23 (GPS L5) (RG500L-EU only) GLONASS 1597.51605.8 Galileo BeiDou 1575.42 2.046 1561.098 2.046 Unit MHz 5.2.2. GNSS Performance Table 40: GNSS Performance

. NOTE 1. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes. 2. Re-acquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can fix position again within 3 minutes after loss of lock. 3. Cold start sensitivity: the lowest GNSS signal value at the antenna port on which the module fixes position within 3 minutes after executing cold start commands. RG500L_Series_QuecOpen_Hardware_Design 72 / 110 5G Module Series 5.2.3. Reference Design The following is the reference circuit of GNSS antenna. Figure 33: Reference Circuit of GNSS Antenna Interface

. NOTE If the module is designed with a passive antenna, then the VDD circuit is not needed. 1. You can select an external LDO for power supply according to the active antenna requirements. 2. 3. Keep the characteristic impedance of GNSS antenna trace as 50 . 4. Place the -type matching components as close to the antenna as possible. 5. Keep digital circuits such as switch mode power supply, (U)SIM card, USB interface, camera module, display connector and SD card away from the antenna traces. 6. Keep 75 dB isolation between GNSS and cellular antenna traces. 7. Keep 15 dB isolation between GNSS and cellular antennas to improve the receiving sensitivity. 5.3. RF Routing Guidelines For users PCB, the characteristic impedance of all RF traces should be controlled to 50 . The impedance of the RF traces is usually determined by the trace width (W), the materials dielectric constant, the height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB structures. RG500L_Series_QuecOpen_Hardware_Design 73 / 110 GNSS AntennaVDDModuleANT_GNSS47 nH10 R0.1 F0 RNMNM100 pF 5G Module Series Figure 34: Microstrip Design on a 2-layer PCB Figure 35: Coplanar Waveguide Design on a 2-layer PCB Figure 36: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) RG500L_Series_QuecOpen_Hardware_Design 74 / 110 5G Module Series Figure 37: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, follow the principles below in RF layout design:

Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 . The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground. The distance between the RF pins and the RF connector should be as short as possible and all the right-angle traces should be changed to curved ones. The recommended trace angle is 135. There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be no less than two times the width of RF signal traces (2 W). Keep RF traces away from interference sources, and avoid intersection and paralleling between traces on adjacent layers. For more details about RF layout, see document [3]. 5.4. Requirements for Antenna Design Table 41: Requirements for Antenna Design Antenna Type Requirements GNSS Frequency range:

GNSS L1: 15591606 MHz GNSS L5: 11661187 MHz (RG500L-EU only) Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0 dBi RG500L_Series_QuecOpen_Hardware_Design 75 / 110 5G Module Series 5G NR/LTE/UMTS Active antenna embedded LNA gain: < 17 dB VSWR: 3 Efficiency: > 30%

Gain: > 0 dBi Max input power: 50 W Input impedance: 50 Polarization: Vertical Cable insertion loss:

< 1 dB: LB (<1 GHz)

< 1.5 dB: MB (12.3 GHz)

< 2 dB: HB (> 2.3 GHz) RG500L_Series_QuecOpen_Hardware_Design 76 / 110 5G Module Series 5.5. RF Connector Recommendation The receptacle dimensions are illustrated as below. Figure 38: Dimensions of the Receptacles (Unit: mm) RG500L_Series_QuecOpen_Hardware_Design 77 / 110 5G Module Series The following figure shows the specifications of mating plugs using 0.81 mm coaxial cables. Figure 39: Specifications of Mating Plugs Using 0.81 mm Coaxial Cables (Unit: mm) For more details, please visit https://www.i-pex.com. 5.5.1. Recommended RF Connector for Installation 5.5.1.1. Assemble Coaxial Cable Plug Manually The illustration for plugging in a coaxial cable plug is shown below, = 90 is acceptable, while 90 is not. RG500L_Series_QuecOpen_Hardware_Design 78 / 110 5G Module Series Figure 40: Plug in a Coaxial Cable Plug The illustration of pulling out the coaxial cable plug is shown below, = 90 is acceptable, while 90 is not. Figure 41: Pull out a Coaxial Cable Plug 5.5.1.2. Assemble Coaxial Cable Plug with Jig The pictures of installing the coaxial cable plug with a jig is shown below, = 90 is acceptable, while 90 is not. RG500L_Series_QuecOpen_Hardware_Design 79 / 110 5G Module Series Figure 42: Install the Coaxial Cable Plug with Jig 5.5.2. Recommended Manufacturers of RF Connector and Cable RF connecters and cables by I-PEX are recommended. For more details, visit https://www.i-pex.com. RG500L_Series_QuecOpen_Hardware_Design 80 / 110 5G Module Series 6 Electrical Characteristics & Reliability 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 42: Absolute Maximum Ratings Parameter VBAT_RF/VBAT_BB USB_VBUS Peak Current of VBAT_BB Peak Current of VBAT_RF Voltage on Digital Pins Voltage at ADC0 Voltage at ADC1 Voltage at ADC2 Min.

-0.5 0

-0.3

-0.5 0 0 Max. Unit 5 21 2 2.5 1.98 1.98 1.45 1.45 V V A A V V V V 6.2. Power Supply Ratings Table 43: The Modules Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT VBAT_BB and VBAT_RF The actual input voltages must stay between the minimum and maximum 3.3 3.8 4.3 V RG500L_Series_QuecOpen_Hardware_Design 81 / 110 5G Module Series values. IVBAT USB_VBUS Peak supply current

(during transmission slot) USB connection detection Maximum power control level at n41

1.5 2 4.2 5.0 15 A V 6.3. Power Consumption Table 44: Averaged Power Consumption Mode Conditions Band/Combinations Current Unit Power-off Power off RF Disabled AT+CFUN=0 (USB 3.0 disable) AT+CFUN=4 (USB 3.0 disable) Sleep State AT+CFUN=0 (USB 3.0 disable) SA PF = 64 (USB 2.0 active) SA PF = 64 (USB 3.0 active) Idle State NOTE

80 120 125 6.5 125 125 A mA mA mA mA mA 1. Power consumption test is carried out under 3.8 V, 25 C with EVB and thermal dissipation measures. 2. The power consumption above is for reference only, which may vary among variants of the module. Please contact Quectel Technical Supports for detailed power consumption test report of the specific model. RG500L_Series_QuecOpen_Hardware_Design 82 / 110 5G Module Series 6.4. Digital I/O Characteristic Table 45: 1.8 V I/O Requirements Parameter Description VIH VIL VOH VOL Input high voltage Input low voltage Output high voltage 1.35 Output low voltage

Table 46: SDIO 1.86 V I/O Requirements Parameter Description VIH VIL VOH VOL Input high voltage Input low voltage Output high voltage Output low voltage Table 47: (U)SIM 1.8 V I/O Requirements Parameter Description USIM_VDD Power supply VIH VIL VOH VOL Input high voltage Input low voltage Output high voltage 1.4 Output low voltage 0 Min. 1.17

-0.3 Min. 1.27

-0.3 1.4

-0.3 Min. 1.65 1.4 0 Max. 1.83 0.63

0.45 Max. 2.16 0.58 2.16 0.45 Unit V V V V Unit V V V V Max. Unit 1.95 1.9 0.27 1.9 0.27 V V V V V RG500L_Series_QuecOpen_Hardware_Design 83 / 110 5G Module Series Table 48: (U)SIM 3.0 V I/O Requirements Parameter Description Min. USIM_VDD Power supply VIH VIL VOH VOL 2.7 2.6 0 Input high voltage Input low voltage Output high voltage 2.6 Output low voltage 0 Max. 3.05 3.0 0.4 3.1 0.4 Unit V V V V V 6.5. ESD Protection If the static electricity generated by various ways discharges to the module, the module maybe damaged to a certain extent. Thus, please take proper ESD countermeasures and handling methods. For example, wearing anti-static gloves during the development, production, assembly and testing of the module;

adding ESD protective component to the ESD sensitive interfaces and points in the product design of the module. ESD characteristics of the modules pins are as follows:

Table 49: Electrostatics Discharge Characteristics (25 C, 45 % Relative Humidity) Tested Interfaces Contact Discharge Air Discharge Unit VBAT, GND 5 All Antenna Interfaces 4 10 8 kV kV RG500L_Series_QuecOpen_Hardware_Design 84 / 110 5G Module Series 6.6. Operating and Storage Temperatures Table 50: Operating and Storage Temperatures Parameter Min. Typ. Max. Unit Operating Temperature Range14 Extended Operating Temperature Range 15 Storage Temperature Range

-30

-40

-40

+25

+25

+70

+85

+90 C C C 6.7. Thermal Consideration The module offers the best performance when all internal IC chips are working within their operating temperatures. When the IC reaches or exceeds the maximum junction temperature, the module may still work but the performance and function (such as RF output power, data rate, etc.) will be affected to a certain extent. Therefore, the thermal design should be maximally optimized to ensure all internal ICs always work within in the recommended operating temperature. The following principles for thermal consideration are provided for reference:

Keep the module away from heat sources on your PCB, especially high-power components such as processor, power amplifier, and power supply. Do not place large size components in the area where the module is mounted on your PCB to reserve enough place for heatsink installation. Maintain the integrity of the PCB copper layer and drill as many thermal vias as possible. Follow the principles below when the heatsink is necessary:

- Attach the heatsink to the shielding cover of the module;

- Choose the heatsink with adequate fins to dissipate heat;

- Choose a TIM (Thermal Interface Material) with high thermal conductivity, good softness and good wettability and place it between the heatsink and the module;

- Fasten the heatsink with four screws to ensure that it is in close contact with the module to prevent the heatsink from falling off during the drop, vibration test, or transportation. 14 To meet this operating temperature range, additional thermal dissipation improvements are required, such as passive or active heatsink, heat-pipe, vapor chamber, cold-plate etc. Within this operating temperature range, the module can meet 3GPP specifications. 15 To meet this extended temperature range, additional thermal dissipation improvements are required, such as passive or active heatsink, heat-pipe, vapor chamber, cold-plate etc. Within this extended temperature range, the module remains the ability to establish and maintain functions such as voice, SMS, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may undergo a reduction in value, exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again. RG500L_Series_QuecOpen_Hardware_Design 85 / 110 5G Module Series Figure 43: Placement and Fixing of Heatsink RG500L_Series_QuecOpen_Hardware_Design 86 / 110 5G Module Series 7 Mechanical Information This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are 0.2 mm unless otherwise specified. 7.1. Mechanical Dimensions Pin 1 Figure 44: Module Top and Side Dimensions (Unit: mm) RG500L_Series_QuecOpen_Hardware_Design 87 / 110 5G Module Series Pin 1 Figure 45: Module Bottom Dimensions (Bottom View, Unit: mm) NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard. RG500L_Series_QuecOpen_Hardware_Design 88 / 110 5G Module Series 7.2. Recommended Footprint Figure 46: Recommended Footprint (Top View, Unit: mm)

. NOTE Keep at least 3 mm between the module and other components on the motherboard to improve soldering quality and maintenance convenience. RG500L_Series_QuecOpen_Hardware_Design 89 / 110 5G Module Series 7.3. Top and Bottom Views Figure 47: Top and Bottom Views of the Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. RG500L_Series_QuecOpen_Hardware_Design 90 / 110 5G Module Series 8 Storage, Manufacturing & Packaging 8.1. Storage Conditions The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 5 C and the relative humidity should be 3560 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition. 3. The floor life of the module is 168 hours16 in a plant where the temperature is 23 5 C and relative humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g. a drying cabinet). 4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under the following circumstances:

The module is not stored in Recommended Storage Condition;

Violation of the third requirement above occurs;

Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;

Before module repairing. 5. If needed, the pre-baking should follow the requirements below:

The module should be baked for 8 hours at 120 5 C;

All modules must be soldered to PCB within 24 hours after the baking, otherwise they should be put in a dry environment such as in a drying oven. 16 This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to, or are not sure to conform to IPC/JEDEC J-STD-033. And do not remove the packages of tremendous modules if they are not ready for soldering. RG500L_Series_QuecOpen_Hardware_Design 91 / 110 5G Module Series NOTE 1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to the air is forbidden. 2. Take out the module from the package and put it on high-temperature-resistant fixtures before baking. All modules must be soldered to PCB within 24 hours after the baking, otherwise put them in the drying oven. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure. 3. Pay attention to ESD protection, such as wearing anti-static gloves, when touching the modules. 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. Apply proper force on the squeegee to produce a clean stencil surface on a single pass. To guarantee module soldering quality, the thickness of stencil for the module is recommended to be 0.150.18 mm. For more details, see document [4]. The peak reflow temperature should be 235246 C, with 246 C as the absolute maximum reflow temperature. To avoid damage to the module caused by repeated heating, it is strongly recommended that the module should be mounted only after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. Figure 48: Recommended Reflow Soldering Thermal Profile RG500L_Series_QuecOpen_Hardware_Design 92 / 110 Temp. (C)Reflow ZoneSoak Zone246200217235CDBA150100 Max slope: 1 3 C/s Cooling down slope: -1.5 to -3 C/s Max slope: 13 C/s 5G Module Series Table 51: Recommended Thermal Profile Parameters Factor Soak Zone Max slope Recommendation 13 C/s Soak time (between A and B: 150 C and 200 C) 70120 s Reflow Zone Max slope Reflow time (D: over 217 C) Max temperature Cooling down slope Reflow Cycle Max reflow cycle NOTE 13 C/s 4070 s 235 C to 246 C

-1.5 to -3 C/s 1 1. If a conformal coating is necessary for the module, do NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module. 2. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the module. 3. Due to the complexity of the SMT process, please contact Quectel Technical Supports in advance for any situation that you are not sure about, or any process (e.g. selective soldering, ultrasonic soldering) that is not mentioned in document [4]. 8.3. Packaging Specifications The module adopts carrier tape packaging and details are as follows:

8.3.1. Carrier Tape Dimension details are as follows:

RG500L_Series_QuecOpen_Hardware_Design 93 / 110 5G Module Series Figure 49: Carrier Tape Dimension Drawing Table 52: Carrier Tape Dimension Table (Unit: mm) W 72 P 56 T A0 B0 0.4 44.7 41.7 K0 4.2 K1 5.2 F E 34.2 1.75 8.3.2. Plastic Reel Figure 50: Plastic Reel Dimension Drawing Table 53: Plastic Reel Dimension Table (Unit: mm) D1 380 D2 180 W 72.5 RG500L_Series_QuecOpen_Hardware_Design 94 / 110 5G Module Series 8.3.3. Packaging Process Place the module into the carrier tape and use the cover tape to cover them; then wind the heat-sealed carrier tape to the plastic for reel and use protection. One plastic reel can load 200 modules. the protective tape Place the packaged plastic reel, humidity indicator card and desiccant bag into a vacuum bag, then vacuumize it. Place the vacuum-packed plastic reel into the pizza box. Put 4 pizza boxes into 1 carton and seal it. One carton can pack 800 modules. Figure 51: Packaging Process RG500L_Series_QuecOpen_Hardware_Design 95 / 110 5G Module Series 9 AT Commands 9.1. AT+CFUN Set Phone Functionality This command controls the functionality level. AT+CFUN=0 turns off radio and SIM power (supported only for feature phone with feature option). AT+CFUN=1,1 or AT+CFUN=4,1 can reset the target. AT+CFUN=1 enters normal mode (supported only for module solution). AT+CFUN=4 enters flight mode (supported only for module solution). AT+CFUN Set Phone Functionality Test Command AT+CFUN=?

Response

+CFUN: (list of supported <fun>s),(list of supported <rst>s) Read Command AT+CFUN?

Write Command AT+CFUN=<fun>[,<rst>]

OK Response

+CFUN: <fun>

OK Response OK If there is any error related to MT functionality:

+CME ERROR: <err>

Or ERROR Maximum Response Time 15 s, determined by the network. Characteristics Reference 3GPP TS 27.007

RG500L_Series_QuecOpen_Hardware_Design 96 / 110 5G Module Series Parameter

<fun>

Integer type. 0 1 4 Minimum functionality, turn off radio and SIM power. Full functionality. Disable both transmitting and receiving RF signals.

(supported only for module solution) 15 Reboot the modem and AP synchronously.

<rst>

Integer type. 0 Do not reset the UE before setting it to <fun> power level.

(Default value when <rst> is omitted.) 1 Reset the MT before setting it to <fun> power level.

<err> Error codes. For more details, see Table 7. Example AT+CFUN=0 OK AT+CFUN=1 OK NOTE 1. The supported parameters are subject to change according to different compile directives (options). 2. AT+CFUN=1,1 or AT+CFUN=4,1 can only reset the UE, not fully compliable with 3GPP TS 27.007. 3. <fun> = 0,1,4 only supported in projects with __ATCFUN_FLIGHTMODE_SUPPORT__ option. 9.2. AT+QSCLK Sleep Mode Setting This command controls whether MT enters sleep mode. When entering into sleep mode is enabled, the MT can directly enter sleep mode. AT+QSCLK Sleep Mode Setting Test Command AT+QSCLK=?

Read Command AT+QSCLK?

Response

+QSCLK: (list of supported <n>s) OK Response

+QSCLK: <n>

RG500L_Series_QuecOpen_Hardware_Design 97 / 110 5G Module Series Write Command AT+QSCLK=<n>[,<saved>]

Maximum Response Time Characteristics OK Response OK 300 ms

Parameter

<n>

NOTE Integer type. Slow clock mode. 0 Disable slow clock 1 Enable slow clock. 1. Execute AT+QSCLK=1 enables the module enter into sleep mode. At this time, the USB is powered down and the modules modem part enters airplane mode. 2. Execute AT+QSCLK=0 will disable the module from sleep mode. At this time, the USB is powered up and the modules modem part is in normal operating mode. Under such condition, the module will never go into sleep mode. 9.3. AT+QADC* Read ADC Value This command reads the voltage value of ADC channel. AT+QADC Read ADC Value Test Command AT+QADC=?

Response

+QADC: (list of supported <port>s) Read Command AT+QADC=<port>

Maximum Response Time Characteristics OK Response

+QADC: <status>,<value>

OK 300 ms

RG500L_Series_QuecOpen_Hardware_Design 98 / 110 5G Module Series Parameter

<port>

<status>

<value>

Integer type. Channel number of the ADC. 0 ADC channel 0 1 ADC channel 1 Integer type. Indicate whether the ADC value read is successful. 0 Failed 1 Successful Integer type. The voltage of specified ADC channel. Unit: mV. RG500L_Series_QuecOpen_Hardware_Design 99 / 110 5G Module Series 10 Appendix References Table 54: Related Documents Document Name

[1] Quectel_RG500L_EVB_User_Guide

[2] Quectel_RG500L_Series_Quecopen_GNSS_Application_Note

[3] Quectel_RF_Layout_Application_Note

[4] Quectel_Module_Secondary_SMT_Application_Note Table 55: Terms and Abbreviations Abbreviation Description ADC bps CA Analog-to-Digital Converter Bits Per Second Carrier Aggregation CHAP Challenge Handshake Authentication Protocol CPE CS CTS Customer-Premises Equipment Coding Scheme Clear To Send DC-HSDPA Dual-carrier High Speed Downlink Packet Access DL DRX ESD FDD FR Downlink Discontinuous Reception Electrostatic Discharge Frequency Division Duplex Full Rate RG500L_Series_QuecOpen_Hardware_Design 100 / 110 5G Module Series GLONASS Global Navigation Satellite System (Russia) GNSS GPS HB HPUE HR HSDPA HSPA HSUPA IC I2C I2S I/O LB LED LGA LNA LTE MAC MB MCU MDC MDIO MHB MIMO NR NSA Global Navigation Satellite System Global Positioning System High Band High Power User Equipment Half Rate High Speed Downlink Packet Access High Speed Packet Access High Speed Uplink Packet Access Integrated Circuit Inter-Integrated Circuit Inter-IC Sound Input/Output Low Band Light Emitting Diode Land Grid Array Low Noise Amplifier Long Term Evolution Media Access Control Middle Band Microcontroller Unit Management Data Clock Management Data Input/Output Middle/High Band Multiple Input Multiple Output New Radio Non-Stand Alone RG500L_Series_QuecOpen_Hardware_Design 101 / 110 5G Module Series PA PAP PC PCB PCIe PCM PDU PHY PMIC PRX QAM QPSK RF RHCP RX SA SCS SD SIMO SMD SMS SPI TDD TRX TX UART UL Power Amplifier Password Authentication Protocol Personal Computer Printed Circuit Board Peripheral Component Interconnect Express Pulse Code Modulation Protocol Data Unit Physical Layer Power Management Integrated Circuit Primary Receive Quadrature Amplitude Modulation Quadrature Phase Shift Keying Radio Frequency Right Hand Circularly Polarized Receive Stand Alone Sub-Carrier Space Secure Digital Single Input Multiple Output Surface Mount Device Short Message Service Serial Peripheral Interface Time Division Duplexing Transmit & Receive Transmit Universal Asynchronous Receiver/Transmitter Uplink RG500L_Series_QuecOpen_Hardware_Design 102 / 110 5G Module Series UMTS USB

(U)SIM VBAT Vmax Vnom Vmin VIHmax VIHmin VILmax VILmin VImax VImin VOHmax VOHmin VOLmax VOLmin VSWR Universal Mobile Telecommunications System Universal Serial Bus Universal Subscriber Identity Module Voltage at Battery (Pin) Maximum Voltage Value Nominal Voltage Value Minimum Voltage Value Maximum Input High Level Voltage Value Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Minimum Input Low Level Voltage Value Absolute Maximum Input Voltage Value Absolute Minimum Input Voltage Value Maximum Output High Level Voltage Value Minimum Output High Level Voltage Value Maximum Output Low Level Voltage Value Minimum Output Low Level Voltage Value Voltage Standing Wave Ratio WCDMA Wideband Code Division Multiple Access WLAN WWAN Wireless Local Area Network Wireless Wide Area Network RG500L_Series_QuecOpen_Hardware_Design 103 / 110 5G Module Series 11 Warning statements 11.1. FCC 11.1.1. Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.31 (h) and (k): The host manufacturer is responsible for additional testing to verify compliance as a composite system. When testing the host device for compliance with Part 15 Subpart B, the host manufacturer is required to show compliance with Part 15 Subpart B while the transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation should confirm that the module's intentional emissions are compliant (i.e. fundamental and out of band emissions). The host manufacturer must verify that there are no additional unintentional emissions other than what is permitted in Part 15 Subpart B or emissions are complaint with the transmitter(s) rule(s). The Grantee will provide guidance to the host manufacturer for Part 15 B requirements if needed. 11.1.2. Important Note notice that any deviation(s) from the defined parameters of the antenna trace, as described by the instructions, require that the host product manufacturer must notify to XXXX that they wish to change the antenna trace design. In this case, a Class II permissive change application is required to be filed by the USI, or the host manufacturer can take responsibility through the change in FCC ID (new application) procedure followed by a Class II permissive change application. 11.1.3. End Product Labeling When the module is installed in the host device, the FCC/IC ID label must be visible through a window on the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a second label must be placed on the outside of the final device that contains the following text: Contains FCC ID: XMR2023RG500LNA Contains IC: 10224A-2023RG500NA The FCC ID/IC ID can be used only when all FCC/IC compliance requirements are met. 11.1.4. Antenna Installation

(1) The antenna must be installed such that 20 cm is maintained between the antenna and users, RG500L_Series_QuecOpen_Hardware_Design 104 / 110 5G Module Series

(2) The transmitter module may not be co-located with any other transmitter or antenna.

(3) Only antennas of the same type and with equal or less gains as shown below may be used with this module. Other types of antennas and/or higher gain antennas may require additional authorization for operation. Band LTE-FDD B2 5G NR n2 LTE-FDD B4 LTE-FDD B5/5G NR n5 LTE-FDD B7 5G NR n7 LTE-FDD B12/5G NR n12 LTE-FDD B13 LTE-FDD B14 LTE-FDD B17 LTE-FDD B25 5G NR n25 LTE-FDD B26 LTE-FDD B30 LTE-FDD B38 5G NR n38 LTE-FDD B41 5G NR n41 LTE-FDD B42 LTE-FDD B43 LTE-FDD B48/5G NR n48 LTE-FDD B66/5G NR n66 LTE-FDD B71 5G NR n71 5G NR n77 5G NR n78 RG500L-NA: Dipole antenna Frequency (MHz) Gain (dBi) 1850-1910 1850-1910 17101755 824849 25002570 25002570 699716 777787 788798 704-716 1850-1915 1850-1915 814-849 2305-2315 2570-2620 2570-2620 2496-2690 2496-2690 3400-3600 3600-3800 3550-3700 1710-1780 663-698 663-698 33004200 33003800 0.75 0.75 0.33 0.49 1.42 1.42

-8.65

-0.92

-10.95

-8.65 0.75 0.75 0.49

-3.06 1.69 1.69 2.61 2.61

-4.29

-4.11

-4.29 0.33

-6.05

-6.05

-3.48

-4.11 In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC/IC authorization. 11.1.5. Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end RG500L_Series_QuecOpen_Hardware_Design 105 / 110 5G Module Series user manual shall include all required regulatory information/warning as show in this manual. 11.1.6. Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:

- Reorient or relocate the receiving antenna.

- Increase the separation between the equipment and receiver.

- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

- Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. 11.1.7. List of applicable FCC rules This module has been tested and found to comply with part 22, part 24, part 27, part 90, 15.247 and 15.407 requirements for Modular Approval. The modular transmitter is only FCC authorized for the specific rule parts (i.e., FCC transmitter rules) listed on the grant, and that the host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. If the grantee markets their product as being Part 15 Subpart B compliant (when it also contains unintentional-radiator digital circuity), then the grantee shall provide a notice stating that the final host product still requires Part 15 Subpart B compliance testing with the modular transmitter installed. 11.1.8. This device is intended only for OEM integrators under the following conditions:(For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and RG500L_Series_QuecOpen_Hardware_Design 106 / 110 5G Module Series 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. 11.1.9. Radiation Exposure Statement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator &

your body. 11.2. IC 11.2.1. Industry Canada Statement This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions:

(1) This device may not cause interference; and

(2) This device must accept any interference, including interference that may cause undesired operation of the device. Le prsent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorise aux deux conditions suivantes:

(1) l'appareil ne doit pas produire de brouillage, et

(2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement."

11.2.2. Radiation Exposure Statement This equipment complies with IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator & your body. 11.2.3. Dclaration d'exposition aux radiations:

Cet quipement est conforme aux limites d'exposition aux rayonnements ISED tablies pour un environnement non contrl. Cet quipement doit tre install et utilis avec un minimum de 20 cm de distance entre la source de rayonnement et votre corps. RG500L_Series_QuecOpen_Hardware_Design 107 / 110 5G Module Series 11.2.4. RSS-247 Section 6.4 (5) (6) (for local area network devices, 5GHz) The device could automatically discontinue transmission in case of absence of information to transmit, or operational failure. Note that this is not intended to prohibit transmission of control or signaling information or the use of repetitive codes where required by the technology. The device for operation in the band 51505250 MHz is only for indoor use to reduce the potential for harmful interference to co-channel mobile satellite systems;

The maximum antenna gain permitted for devices in the bands 52505350 MHz and 54705725 MHz shall comply with the e.i.r.p. limit; and The maximum antenna gain permitted for devices in the band 57255825 MHz shall comply with the e.i.r.p. limits specified for point-to-point and non point-to-point operation as appropriate. L'appareil peut interrompre automatiquement la transmission en cas d'absence d'informations transmettre ou de panne oprationnelle. Notez que ceci n'est pas destin interdire la transmission d'informations de contrle ou de signalisation ou l'utilisation de codes rptitifs lorsque cela est requis par la technologie. Le dispositif utilis dans la bande 5150-5250 MHz est rserv une utilisation en intrieur afin de rduire le risque de brouillage prjudiciable aux systmes mobiles par satellite dans le mme canal;

Le gain d'antenne maximal autoris pour les dispositifs dans les bandes 5250-5350 MHz et 5470-5725 MHz doit tre conforme la norme e.r.p. limite; et Le gain d'antenne maximal autoris pour les appareils de la bande 5725-5825 MHz doit tre conforme la norme e.i.r.p. les limites spcifies pour un fonctionnement point point et non point point, selon le cas. 11.2.5. This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. 11.2.6. Cet appareil est conu uniquement pour les intgrateurs OEM dans les conditions suivantes: (Pour utilisation de dispositif module) 1) L'antenne doit tre installe de telle sorte qu'une distance de 20 cm est respecte entre l'antenne et les utilisateurs, et 2) Le module metteur peut ne pas tre complant avec un autre metteur ou antenne. Tant que les 2 conditions ci-dessus sont remplies, des essais supplmentaires sur l'metteur ne RG500L_Series_QuecOpen_Hardware_Design 108 / 110 5G Module Series seront pas ncessaires. Toutefois, l'intgrateur OEM est toujours responsable des essais sur son produit final pour toutes exigences de conformit supplmentaires requis pour ce module install. 11.2.7. IMPORTANT NOTE:

In the event that these conditions can not be met (for example certain laptop configurations or colocation with another transmitter), then the Canada authorization is no longer considered valid and the IC ID can not be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate Canada authorization. 11.2.8. NOTE IMPORTANTE:

Dans le cas o ces conditions ne peuvent tre satisfaites (par exemple pour certaines configurations d'ordinateur portable ou de certaines co-localisation avec un autre metteur), l'autorisation du Canada n'est plus considr comme valide et l'ID IC ne peut pas tre utilis sur le produit final. Dans ces circonstances, l'intgrateur OEM sera charg de rvaluer le produit final (y compris l'metteur) et l'obtention d'une autorisation distincte au Canada. 11.2.9. End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed such that 20 cm may be maintained between the antenna and users. The final end product must be labeled in a visible area with the following: Contains IC: 10224A-2023RG500NA. 11.2.10. Plaque signaltique du produit final Ce module metteur est autoris uniquement pour une utilisation dans un dispositif o l'antenne peut tre installe de telle sorte qu'une distance de 20cm peut tre maintenue entre l'antenne et les utilisateurs. Le produit final doit tre tiquet dans un endroit visible avec l'inscription suivante:

"Contient des IC: 10224A-2023RG500NA ". 11.2.11. Manual Information To the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. RG500L_Series_QuecOpen_Hardware_Design 109 / 110 5G Module Series 11.2.12. Manuel d'information l'utilisateur final L'intgrateur OEM doit tre conscient de ne pas fournir des informations l'utilisateur final quant la faon d'installer ou de supprimer ce module RF dans le manuel de l'utilisateur du produit final qui intgre ce module. Le manuel de l'utilisateur final doit inclure toutes les informations rglementaires requises et avertissements comme indiqu dans ce manuel. RG500L_Series_QuecOpen_Hardware_Design 110 / 110