FCC ID: XMR2021RM502QGL 5G Sub-6 GHz M.2 Module

RM502Q-GL Hardware Design Rev. RM502Q-GL_Hardware_Design_V1.0 5G Module Series Date: 2020-07-06 Status: Preliminary www.quectel.com 5G Module Series RM502Q-GL Hardware Design Our aim is to provide customers with timely and comprehensive services. For any assistance, please contact our company headquarters:

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http://www.quectel.com/support/technical.htm Or email to: support@quectel.com GENERAL NOTES QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION PROVIDED IS BASED UPON CUSTOMERS REQUIREMENTS. QUECTEL MAKES EVERY EFFORT TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR RELIANCE UPON THE INFORMATION. ALL INFORMATION SUPPLIED HEREIN IS SUBJECT TO CHANGE WITHOUT PRIOR NOTICE. COPYRIGHT THE INFORMATION CONTAINED HERE IS PROPRIETARY TECHNICAL INFORMATION OF QUECTEL WIRELESS SOLUTIONS CO., LTD. TRANSMITTING, REPRODUCTION, DISSEMINATION AND EDITING OF THIS DOCUMENT AS WELL AS UTILIZATION OF THE CONTENT WITHOUT PERMISSION ARE FORBIDDEN. OFFENDERS WILL BE HELD LIABLE FOR PAYMENT OF DAMAGES. ALL RIGHTS ARE RESERVED IN THE EVENT OF A PATENT GRANT OR REGISTRATION OF A UTILITY MODEL OR DESIGN. Copyright Quectel Wireless Solutions Co., Ltd. 2020. All rights reserved. RM502Q-GL_Hardware_Design 1 / 77 5G Module Series RM502Q-GL Hardware Design About the Document Revision History Version Date Author Description 1.0 2020-07-06 Kingson ZHANG/

Qiqi WANG Initial RM502Q-GL_Hardware_Design 2 / 77 5G Module Series RM502Q-GL Hardware Design Contents About the Document ................................................................................................................................... 2 Contents ....................................................................................................................................................... 3 Table Index ................................................................................................................................................... 5 Figure Index ................................................................................................................................................. 6 1 Introduction .......................................................................................................................................... 8 1.1. Safety Information ....................................................................................................................... 9 2 Product Concept ................................................................................................................................ 10 2.1. General Description .................................................................................................................. 10 2.2. Key Features ............................................................................................................................. 11 2.3. Functional Diagram ................................................................................................................... 13 2.4. Evaluation Board ....................................................................................................................... 14 3.4.2.1. 3.4.2.2. 3.4.1.1. 3.4.1.2. 3.4.1.3. 3 Application Interfaces ....................................................................................................................... 15 3.1. Pin Assignment ......................................................................................................................... 16 3.2. Pin Description .......................................................................................................................... 17 3.3. Power Supply ............................................................................................................................ 21 3.3.1. Decrease Voltage Drop .................................................................................................. 21 3.3.2. Reference Design for Power Supply .............................................................................. 22 3.4. Turn on and off Scenarios ......................................................................................................... 23 3.4.1. Turn on the Module ........................................................................................................ 23 Turn on the Module with a Host GPIO ................................................................ 24 Turn on the Module Automatically ...................................................................... 24 Turn on the Module with Compatible Design ...................................................... 25 3.4.2. Turn off the Module ........................................................................................................ 26 Turn off the Module through FULL_CARD_POWER_OFF# .............................. 26 Turn off the Module through AT Command ........................................................ 26 3.5. Reset ......................................................................................................................................... 28 3.6.

(U)SIM Interfaces ...................................................................................................................... 30 3.7. USB Interface ............................................................................................................................ 32 3.8. PCIe Interface ........................................................................................................................... 35 3.8.1. Endpoint Mode ............................................................................................................... 35 3.8.2. USB Version and PCIe Version ..................................................................................... 37 3.9. PCM Interface* .......................................................................................................................... 38 3.10. Control and Indication Interfaces .............................................................................................. 40 3.10.1. W_DISABLE1#* ............................................................................................................. 41 3.10.2. W_DISABLE2#* ............................................................................................................. 41 3.10.3. WWAN_LED#* ............................................................................................................... 42 3.10.4. WAKE_ON_WAN#* ....................................................................................................... 43 3.10.5. DPR* .............................................................................................................................. 44 3.10.6. STATUS* ........................................................................................................................ 44 3.11. Cellular/WLAN Interface* .......................................................................................................... 45 RM502Q-GL_Hardware_Design 3 / 77 5G Module Series RM502Q-GL Hardware Design 3.12. Antenna Tuner Control Interface* ............................................................................................. 45 3.13. Configuration Pins ..................................................................................................................... 46 4 GNSS Receiver ................................................................................................................................... 47 4.1. General Description .................................................................................................................. 47 4.2. GNSS Performance .................................................................................................................. 48 5 Antenna Connection .......................................................................................................................... 49 5.1. RF Antenna Interfaces .............................................................................................................. 49 5.1.1. Antenna Pin Definition.................................................................................................... 49 5.1.2. RF Antenna Port Mapping ............................................................................................. 50 5.1.3. Operating Frequency ..................................................................................................... 50 5.1.4. Reference Design of RF Antenna Interface ................................................................... 52 5.2. GNSS Antenna Interface .......................................................................................................... 52 5.3. Reference Design of RF Layout ............................................................................................... 53 5.4. Antenna Connectors ................................................................................................................. 55 5.4.1 RF Bands Supported by Antenna Connectors .................................................................... 56 5.5. Antenna Installation .................................................................................................................. 57 5.5.1. Antenna Requirements .................................................................................................. 57 5.5.2. Recommended RF Connector for Antenna Installation ................................................. 57 6 Electrical, Reliability and Radio Characteristics ............................................................................ 60 6.1. Absolute Maximum Ratings ...................................................................................................... 60 6.2. Power Supply Requirements .................................................................................................... 60 I/O Requirements ...................................................................................................................... 61 6.3. 6.4. Operation and Storage Temperatures ...................................................................................... 61 6.5. Current Consumption ................................................................................................................ 62 6.6. RF Output Power ...................................................................................................................... 67 6.7. RF Receiving Sensitivity ........................................................................................................... 67 6.8. ESD Characteristics .................................................................................................................. 70 6.9. Thermal Dissipation .................................................................................................................. 70 7 Mechanical Dimensions and Packaging ......................................................................................... 73 7.1. Mechanical Dimensions of the Module ..................................................................................... 73 7.2. Top and Bottom Views of the Module ....................................................................................... 74 7.3. M.2 Connector ........................................................................................................................... 74 7.4. Packaging ................................................................................................................................. 75 8 Appendix References ........................................................................................................................ 76 RM502Q-GL_Hardware_Design 4 / 77 5G Module Series RM502Q-GL Hardware Design Table Index Table 1: Frequency Bands and GNSS Type of RM502Q-GL Module ....................................................... 10 Table 2: Key Features of RM502Q-GL ...................................................................................................... 11 Table 3: Definition of I/O Parameters ......................................................................................................... 17 Table 4: Pin Description ............................................................................................................................. 17 Table 5: Definition of VCC and GND Pins ................................................................................................. 21 Table 6: Definition of FULL_CARD_POWER_OFF# Pin ........................................................................... 23 Table 7: Definition of RESET_N Pin .......................................................................................................... 28 Table 8: Pin Definition of (U)SIM Interfaces .............................................................................................. 30 Table 9: Pin Definition of USB Interface .................................................................................................... 33 Table 10: Pin Definition of PCIe Interface .................................................................................................. 35 Table 11: Pin Definition of PCM Interface* ................................................................................................ 40 Table 12: Pin Definition of Control and Indication Interfaces..................................................................... 40 Table 13: RF Function Status .................................................................................................................... 41 Table 14: GNSS Function Status ............................................................................................................... 42 Table 15: Network Status Indications of WWAN_LED# Signal ................................................................. 43 Table 16: State of the WAKE_ON_WAN# Signal ...................................................................................... 43 Table 17: Function of the DPR Signal ........................................................................................................ 44 Table 18: Pin Definition of COEX Interface ............................................................................................... 45 Table 20: Pin Definition of Antenna Tuner Control Interface ..................................................................... 45 Table 21: Definition of Configuration Pins.................................................................................................. 46 Table 22: Configuration Pins List of M.2 Specification .............................................................................. 46 Table 23: GNSS Performance ................................................................................................................... 48 Table 24: Pin Definition of RF Antenna Interfaces..................................................................................... 49 Table 25: RM502Q-GL RF Antenna Mapping ........................................................................................... 50 Table 26: RM502Q-GL Module Operating Frequencies ............................................................................ 50 Table 27: GNSS Frequency ....................................................................................................................... 53 Table 28: RF Bands Supported by RM502Q-GL Antenna Connectors ..................................................... 56 Table 29: Antenna Requirements .............................................................................................................. 57 Table 30: Major Specifications of the RF Connector ................................................................................. 58 Table 31: Absolute Maximum Ratings ....................................................................................................... 60 Table 32: Power Supply Requirements ..................................................................................................... 60 Table 33: I/O Requirements ....................................................................................................................... 61 Table 34: Operation and Storage Temperatures ....................................................................................... 61 Table 35: RM502Q-GL Current Consumption ........................................................................................... 62 Table 36: RF Output Power ....................................................................................................................... 67 Table 37: RM502Q-GL Conducted RF Receiving Sensitivity .................................................................... 68 Table 38: Electrostatic Discharge Characteristics (Temperature: 25C, Humidity: 40%) ......................... 70 Table 39: Related Documents .................................................................................................................... 76 Table 40: Terms and Abbreviations ........................................................................................................... 76 RM502Q-GL_Hardware_Design 5 / 77 5G Module Series RM502Q-GL Hardware Design Figure Index Figure 1: Functional Diagram ..................................................................................................................... 13 Figure 2: Pin Assignment ........................................................................................................................... 16 Figure 3: Power Supply Limits during Radio Transmission ....................................................................... 22 Figure 4: Reference Circuit of VCC Pins ................................................................................................... 22 Figure 5: Reference Design of Power Supply ............................................................................................ 23 Figure 6: Turn on the Module with a Host GPIO ........................................................................................ 24 Figure 7: Turn on the Module Automatically .............................................................................................. 24 Figure 8: Turn on the Module with Compatible Design ............................................................................. 25 Figure 9: Turn-on Timing of the Module ..................................................................................................... 25 Figure 10: Turn-off Timing through FULL_CARD_POWER_OFF# ........................................................... 26 Figure 11: Turn-off Timing through AT Command and FULL_CARD_POWER_OFF# ............................ 27 Figure 12: Turn-off Timing through AT Command and Power Supply ...................................................... 27 Figure 13: Reference Circuit of RESET_N with NPN Driving Circuit ........................................................ 28 Figure 14: Reference Circuit of RESET_N with NMOS Driving Circuit ..................................................... 29 Figure 15: Reference Circuit of RESET_N with Button ............................................................................. 29 Figure 16: Resetting Timing of the Module ................................................................................................ 29 Figure 17: Reference Circuit of Normally Closed (U)SIM Card Connector ............................................... 31 Figure 18: Reference Circuit of Normally Open (U)SIM Card Connector ................................................. 31 Figure 19: Reference Circuit of a 6-Pin (U)SIM Card Connector .............................................................. 32 Figure 20: Reference Circuit of USB 3.1 & 2.0 Interface ........................................................................... 33 Figure 21: PCIe Interface Reference Circuit (EP Mode) ........................................................................... 36 Figure 22: PCIe Power-on Timing Requirements of M.2 Specification ..................................................... 36 Figure 23: PCIe Power-on Timing Requirements of the Module ............................................................... 37 Figure 24: Primary Mode Timing ................................................................................................................ 39 Figure 25: Auxiliary Mode Timing .............................................................................................................. 39 Figure 26: W_DISABLE1# and W_DISABLE2# Reference Circuit ........................................................... 42 Figure 27: WWAN_LED# Reference Circuit .............................................................................................. 43 Figure 28: WAKE_ON_WAN# Signal Reference Circuit ........................................................................... 44 Figure 29: Recommended Circuit of Configuration Pins ........................................................................... 46 Figure 30: Reference Circuit of RF Antenna .............................................................................................. 52 Figure 31: Microstrip Design on a 2-layer PCB ......................................................................................... 54 Figure 32: Coplanar Waveguide Design on a 2-layer PCB ....................................................................... 54 Figure 33: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 54 Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 55 Figure 35: Antenna Connectors on the Module ......................................................................................... 56 Figure 36: RM502Q-GL RF Connector Dimensions (Unit: mm) ................................................................ 58 Figure 37: Specifications of Mating Plugs Using 0.81 mm Coaxial Cables ............................................ 58 Figure 38: Connection between RF Connector and Mating Plug Using 0.81 mm Coaxial Cable .......... 59 Figure 39: Connection between RF Connector and Mating Plug Using 1.13 mm Coaxial Cable .......... 59 Figure 40: Thermal Dissipation Area on Bottom Side of Module (Bottom View)....................................... 71 Figure 41: Mechanical Dimensions of RM502Q-GL (Unit: mm) ................................................................ 73 RM502Q-GL_Hardware_Design 6 / 77 5G Module Series RM502Q-GL Hardware Design Figure 42: Top and Bottom Views of the Module ....................................................................................... 74 Figure 43: Tray Size (Unit: mm) ................................................................................................................. 75 Figure 44: Tray Packaging Procedure ....................................................................................................... 75 RM502Q-GL_Hardware_Design 7 / 77 5G Module Series RM502Q-GL Hardware Design 1 Introduction This document defines RM502Q-GL module and describes its air interface and hardware interfaces which are connected with customers applications. This document helps customers quickly understand the interface specifications, electrical and mechanical details, as well as other related information of RM502Q-GL module. To facilitate its application in different fields, reference design is also provided for reference. Associated with application notes and user guides, customers can use the module to design and set up mobile applications easily. RM502Q-GL_Hardware_Design 8 / 77 5G Module Series RM502Q-GL Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating RM502Q-GL module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be given to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If the device offers an Airplane Mode, then it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on boarding the aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signals and cellular network cannot be guaranteed to connect in all possible conditions (for example, with unpaid bills or with an invalid (U)SIM card). When emergent help is needed in such conditions, please remember using emergency call. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV set, radio, computer or other electric equipment. In locations with potentially explosive atmospheres, obey all posted signs to turn off wireless devices such as your phone or other cellular terminals. Areas with potentially explosive atmospheres include fueling areas, below decks on boats, fuel or chemical transfer or storage facilities, areas where the air contains chemicals or particles such as grain, dust or metal powders, etc. RM502Q-GL_Hardware_Design 9 / 77 5G Module Series RM502Q-GL Hardware Design 2 Product Concept 2.1. General Description RM502Q-GL is a 5G NR/LTE-A/UMTS/HSPA+ wireless communication module with receive diversity. It provides data connectivity on 5G NR SA and NSA, LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA and WCDMA networks with standard PCI Express M.2 interface. It supports embedded operating systems such as Windows, Linux and Android, and also provides GNSS and voice functionality to meet specific application demands. The following table shows the frequency bands and GNSS type of RM502Q-GL module. Table 1: Frequency Bands and GNSS Type of RM502Q-GL Module RM502Q-GL n1/n2/n3/n5/n7/n8/n12/n20/n25/n28/n38/n40/n41/n48/n66/n71/n77/n78 B1/B2/B3/B4/B5/B7/B8/B9/B12/B13/B14/B17/B18/B19/B20/B25/B26/B28/B29/B30

/B32/B66/B71 B34/B38/B39/B40/B41/B42/B43/B46/B48 WCDMA B1/B2/B3/B4/B5/B8/B19 GNSS GPS/GLONASS/BeiDou/Galileo LTE-FDD B29/B32 and LTE-TDD B46 support receving only. Mode 5G NR LTE-FDD LTE-TDD NOTE RM502Q-GL_Hardware_Design 10 / 77 5G Module Series RM502Q-GL Hardware Design RM502Q-GL can be applied in the following fields:

Rugged tablet PC and laptop computer Remote monitor system Vehicle system Wireless POS system Smart metering system Wireless router and switch Other wireless terminal devices 2.2. Key Features The following table describes key features of RM502Q-GL. Table 2: Key Features of RM502Q-GL Feature Details Function Interface PCI Express M.2 Interface Power Supply Supply voltage: 3.1354.4 V Typical supply voltage: 3.7 V Transmitting Power 5G NR Features LTE Features Class 3 (24 dBm +1/-3 dB) for WCDMA bands Class 3 (23 dBm 2 dB) for LTE bands Class 3 (23 dBm 2 dB) for 5G NR bands Class 2 (26 dBm 2 dB) for LTE B38/B40/B41/B42/B43 bands HPUE 1) Class 2 (26 dBm +2/-3 dB) for 5G NR n41/n77/n78 bands HPUE 1) Support 3GPP Rel.15 Support uplink 256QAM and downlink 256QAM Support downlink 4 4 MIMO on n1/n2/n3/n7/25/n38/n40/n41/n48/n66/n77/n78 Support uplink 2 2 UL MIMO on n41/n77/n78 Support SCS 15 kHz and 30 kHz Support SA and NSA operation modes Support NSA on n41/n77/n78 Support SA on all the 5G bandsSupport Option 3X, 3 A, and Option 2 NSA TDD: Max 2.5 Gbps(DL)/650 Mbps (UL) SA TDD: Max 2.1 Gbps(DL)/900 Mbps (UL) Support up to CA Cat 16 FDD and TDD Support uplink QPSK, 16QAM and 64QAM and 256QAM modulation Support downlink QPSK, 16QAM and 64QAM and 256QAM modulation Support 1.4 MHz to 20 MHz (5 CA) RF bandwidth Support downlink MIMO 4 4 on RM502Q-GL_Hardware_Design 11 / 77 5G Module Series RM502Q-GL Hardware Design UMTS Features B1/B2/B3/B4/B7/B25/B30/B38/B39/B40/B41/B42/B43/B48/B66 LTE: Max 1.0 Gbps(DL)/200 Mbps (UL) Support 3GPP R8 DC-HSDPA, HSPA +, HSDPA, HSUPA and WCDMA Support QPSK, 16QAM and 64QAM modulation DC-HSDPA: Max 42 Mbps (DL) HSUPA: Max 5.76 Mbps (UL) WCDMA: Max 384 kbps (DL)/384 kbps (UL) Internet Protocol Features Support QMI/NTP* protocols Support the protocols PAP and EIRP usually used for PPP connections SMS Text and PDU modes Point-to-point MO and MT SMS cell broadcast SMS storage: ME by default

(U)SIM Interfaces Support (U)SIM card: Class B (3.0 V) and Class C(1.8 V)

(U)SIM1 and (U)SIM2 interfaces Support Dual SIM Single Standby*

USB Interface Compliant with USB 3.1 and 2.0 specifications, with maximum transmission rates up to 10 Gbps on USB 3.1 and 480 Mbps on USB 2.0. Used for AT command communication, data transmission, firmware upgrade, software debugging, GNSS NMEA sentence output and voice over USB*

Support USB serial drivers for: Windows 7/8/8.1/10, Linux 2.65.4, Android 4.x/5.x/6.x/7.x/8.x/9.x/10 PCIe 1 Interface Complaint with PCIe GEN3, support 8 Gbps per lane, PCIe 1. Used for AT command communication, data transmission, firmware upgrade, software debugging, GNSS NMEA sentence output Rx-diversity Support 5G NR/LTE/WCDMA Rx-diversity GNSS Features Gen9 Lite of Qualcomm Protocol: NMEA 0183 Data Update Rate: 1 Hz AT Commands Compliant with 3GPP TS 27.007, 27.005 and Quectel enhanced AT commands Antenna Interfaces ANT0, ANT1, ANT2_GNSSL1, and ANT3 Physical Characteristics Size: (52.0 0.15) mm (30.0 0.15) mm (2.3 0.2) mm Weight: approx. 8.6 g Temperature Range Operation temperature range: -30C to +60C 2) Restricted Operation temperature range: -30C to -20C, +60C to +75C Extended temperature range: -40C to -30C, +75C to +85C 3) Storage temperature range: -40C to +90C Firmware Upgrade USB 2.0 interface, PCIe interface and DFOTA RM502Q-GL_Hardware_Design 12 / 77 RoHS All hardware components are fully compliant with EU RoHS directive 5G Module Series RM502Q-GL Hardware Design NOTES 1. 2. 3. 4. 1) HPUE is only for single carrier. 2) Within operation temperature range, the module meets 3GPP specifications. 3) Within extended temperature range, the module remains the ability to establish and maintain functions such as voice, SMS, data transmission without any unrecoverable malfunction. Radio spectrum and radio network will not be influenced, while one or more specifications, such as Pout may undergo a reduction in value, exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again.

* means under development. 2.3. Functional Diagram The following figure shows a block diagram of RM502Q-GL. Figure 1: Functional Diagram RM502Q-GL_Hardware_Design 13 / 77 BasebandPMICSub-6 GHzTransceiver ANT0 ANT3 ANT2_GNSSL1ETVCCRESET_N38.4MXOSPMIIQControlTxPRxDRxPCI Express M.2 Key-B InterfaceFULL_CARD_POWER_OFF#W_DISABLE2#USB 2.0 & USB 3.1(U)SIM1WWAN_LED#WAKE_ON_WAN#NAND Flash 4Gb x 8LPDDR4 SDRAM 4Gb x 16RFFEW_DISABLE1#GPIOsTx/Rx Blocks ANT1PCIe 1(U)SIM2GND 5G Module Series RM502Q-GL Hardware Design 2.4. Evaluation Board To help with the development of applications conveniently with RM502Q-GL, Quectel supplies the evaluation board (PCIe Card EVB), a USB to RS-232 converter cable, a USB type-C cable, antennas and other peripherals to control or test the module. For more details, please refer to document [1]. RM502Q-GL_Hardware_Design 14 / 77 5G Module Series RM502Q-GL Hardware Design 3 Application Interfaces

(U)SIM interfaces The physical connections and signal levels of RM502Q-GL comply with PCI Express M.2 specification. This chapter mainly describes the definition and application of the following interfaces/pins of RM502Q-GL:

Power supply USB interface PCIe interface PCM interface*

Control and indication interfaces*

COEX UART interface*

Antenna tuner control interface*

Configuration pins NOTE

* means under development. RM502Q-GL_Hardware_Design 15 / 77 5G Module Series RM502Q-GL Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of RM502Q-GL. The top side contains RM502Q-GL module and antenna connectors. Figure 2: Pin Assignment RM502Q-GL_Hardware_Design 16 / 77 PIN2PIN74BOTPIN1PIN75TOPPin NameNo.CONFIG_275GND73GND71CONFIG_169RESET_N67RFFE_VIO_1V865RFFE0_CLK63RFFE0_DATA61LAA_TX_EN59GND57PCIE_REFCLK_P55PCIE_REFCLK_M53GND51PCIE_RX_P49PCIE_RX_M47GND45PCIE_TX_P43PCIE_TX_M41GND39USB_SS_RX_P37USB_SS_RX_M35GND33USB_SS_TX_P31USB_SS_TX_M29GND27DPR25WAKE_ON_WAN#23CONFIG_021NotchNotchNotchNotchGND11USB_DM9USB_DP7GND5GND3CONFIG_31PIN11PIN10No.Pin Name74VCC72VCC70VCC68AP2SDX_STATUS66USIM1_DET64COEX_TXD62COEX_RXD60WLAN_TX_EN58RFFE1_DATA56RFFE1_CLK54PCIE_WAKE_N52PCIE_CLKREQ_N50PCIE_RST_N48USIM2_VDD46USIM2_RST44USIM2_CLK42USIM2_DATA40USIM2_DET38SDX2AP_STATUS36USIM1_VDD34USIM1_DATA32USIM1_CLK30USIM1_RST28PCM_SYNC26W_DISABLE2#24PCM_DOUT22PCM_DIN20PCM_CLKNotchNotchNotchNotch10WWAN_LED#8W_DISABLE1#64VCC2VCCFULL_CARD_POWER_OFF# 5G Module Series RM502Q-GL Hardware Design 3.2. Pin Description Table 3: Definition of I/O Parameters Type AI AO DI DO IO OD PI PO Description Analog Input Analog Output Digital Input Digital Output Bidirectional Open Drain Power Input Power Output The following table shows the pin definition and description of RM502Q-GL. Table 4: Pin Description Pin No. M.2 Socket 2 PCIe-based Pinout RM502Q-GL Pin Name I/O Description Comment 1 CONFIG_3 CONFIG_3 DO Not connected internally 2 3.3 V VCC PI Power supply 3 GND GND Ground 4 3.3 V VCC PI Power supply 5 6 GND GND Ground FULL_CARD_ POWER_OFF#

FULL_CARD_ POWER_OFF#

DI Turn on/off of the module. When it is at low level, the Internally pulled down with a Vmin = 3.135 V Vnorm = 3.7 V Vmax = 4.4 V Vmin = 3.135 V Vnorm = 3.7 V Vmax = 4.4 V RM502Q-GL_Hardware_Design 17 / 77 5G Module Series RM502Q-GL Hardware Design module is turned off. When it is at high level, the module is turned on. 100k resistor USB_D+

USB_DP USB 2.0 differential data (+) W_DISABLE1#

(I)(0/1.8 V) W_DISABLE1#

DI Airplane mode control. Active LOW. 1.8/3.3 V power domain USB_D-

USB_DM USB 2.0 differential data (-) 10 GPIO_9/LED_1#

(OD)(0/3.3 V) WWAN_LED#

OD RF status indication LED It is an open drain and active LOW signal.

(I)(0/1.8 V) 7 8 9 11 GND 12 Key 13 Key 14 Key 15 Key 16 Key 17 Key 18 Key 19 Key 20 GPIO_5

/AUDIO_0 GPIO_6

/AUDIO_1 GPIO_11

/WOWWAN#

GPIO_7

/AUDIO_2 DPR

(I)(0/1.8 V) 22 23 24 25 26 GND Notch Notch Notch Notch Notch Notch Notch Notch Ground Notch Notch Notch Notch Notch Notch Notch Notch AI, AO AI, AO DI DI PCM_CLK IO PCM data bit clock 21 CONFIG_0 CONFIG_0 DO Not connected internally PCM_DIN DI PCM data input WAKE_ON_WAN# OD Wake up the host. Active LOW. PCM_DOUT DO PCM data output DPR Dynamic power reduction. High level by default. GPIO_10

/W_DISABLE2#

W_DISABLE2#

GNSS disable control. Active LOW. 1.8/3.3 V power domain 27 GND GND Ground RM502Q-GL_Hardware_Design 18 / 77 1.8 V power domain 1.8 V power domain Open drain 1.8 V power domain 1.8 V power domain 5G Module Series RM502Q-GL Hardware Design 28 GPIO_8

/AUDIO_3 PCM_SYNC IO PCM data frame sync 29 PETn1 USB_SS_TX_M AO USB 3.1 transmit data (-) 30 UIM_RESET(O) USIM1_RST DO

(U)SIM1 card reset 31 PETp1 USB_SS_TX_P AO USB 3.1 transmit data (+) 32 UIM_CLK(O) USIM1_CLK DO

(U)SIM1 card clock 33 GND GND Ground 34 UIM_DATA(I/O) USIM1_DATA IO

(U)SIM1 card data 1.8 V power domain 1.8/3.0 V power domain 1.8/3.0 V power domain 1.8/3.0 V power domain 35 PERn1 USB_SS_RX_M AI USB 3.1 receive data (-) 36 UIM_PWR(O) USIM1_VDD PO Power supply for (U)SIM1 card 1.8/3.0 V power domain 37 PERp1 USB_SS_RX_P AI USB 3.1 receive data (+) 38 NC SDX2AP_STATUS DO Status indication to AP 1.8 V power domain 39 GND GND Ground 40 GPIO_0

/SIM_DET2 USIM2_DET DI

(U)SIM2 card insertion detection Internally pulled up to 1.8 V 41 PETn0 PCIE_TX_M AO PCIe transmit data (-) USIM2_DATA IO

(U)SIM2 card data 43 PETp0 PCIE_TX_P AO PCIe transmit data (+) USIM2_CLK DO

(U)SIM2 card clock 45 GND GND Ground 42 GPIO_1

/SIM_DAT2 44 GPIO_2

/SIM_CLK2 46 GPIO_3

/SIM_RST2 USIM2_RST DO

(U)SIM2 card reset 1.8/3.0 V power domain 1.8/3.0 V power domain 1.8/3.0 V power domain 47 PERn0 PCIE_RX_M AI PCIe receive data (-) 48 GPIO_4

(SIM_PWR2) USIM2_VDD PO Power supply for (U)SIM2 card 1.8/3.0 V power domain 49 PERp0 PCIE_RX_P AI PCIe receive data (+) 50 PERST#

PCIE_RST_N DI Open drain PCIe reset. Active LOW. RM502Q-GL_Hardware_Design 19 / 77 5G Module Series RM502Q-GL Hardware Design 51 GND GND Ground 52 CLKREQ#

PCIE_CLKREQ_N DO Open drain 53 REFCLKn PCIE_REFCLK_M PCIe reference clock (-) 54 PEWAKE#

PCIE_WAKE_N DO Open drain PCIe clock request. Active LOW. PCIe PME wake. Active LOW. AI, AO AI, AO 55 REFCLKp PCIE_REFCLK_P PCIe reference clock (+) 56 NC RFFE1_CLK DO RFFE1 serial interface clock 57 GND GND Ground 58 NC RFFE1_DATA DO RFFE1 serial interface data 59 ANTCTL0

(O)(0/1.8 V) LAA_TX_EN DO 60 COEX3 WLAN_TX_EN DI Notification from SDR to WL when LTE transmitting 1.8 V power domain Notification from WL to SDR while transmitting 1.8 V power domain RFFE0_DATA DO RFFE0 serial interface data 62 COEX2 COEX_RXD DI LTE/WLAN coexistence receive data RFFE0_CLK DO RFFE0 serial interface clock 64 COEX1 COEX_TXD DO LTE/WLAN coexistence transmit data RFFE_VIO_1V8 PO Power supply for RFFE 66 SIM_DETECT USIM1_DET DI

(U)SIM1 card insertion detection 61 ANTCTL1

(O)(0/1.8 V) 63 ANTCTL2

(O)(0/1.8 V) 65 ANTCTL3

(O)(0/1.8 V) 67 68 RESET#

(I)(0/1.8 V) SUSCLK(32 kHz) RESET_N DI Reset the module. Active LOW. AP2SDX_STATUS DI Status indication from AP 69 CONFIG_1 CONFIG_1 DO Connected to GND internally 70 3.3 V VCC PI Power supply 1.8 V power domain 1.8 V power domain 1.8 V power domain 1.8 V power domain 1.8 V power domain 1.8 V power domain 1.8 V power output Internally pulled up to 1.8 V Internally pulled up to 1.8 V with a 100k resistor 1.8 V power domain Vmin = 3.135 V Vnorm = 3.7 V Vmax = 4.4 V RM502Q-GL_Hardware_Design 20 / 77 5G Module Series RM502Q-GL Hardware Design 71 GND GND Ground 72 3.3 V VCC PI Power supply 73 GND GND Ground 74 3.3 V VCC PI Power supply 75 CONFIG_2 CONFIG_2 DO Not connected internally Vmin = 3.135 V Vnorm = 3.7 V Vmax = 4.4 V Vmin = 3.135 V Vnorm = 3.7 V Vmax = 4.4 V NOTE Keep all NC, reserved and unused pins unconnected. 3.3. Power Supply The following table shows pin definition of VCC pins and ground pins. Table 5: Definition of VCC and GND Pins Pin No. Pin Name I/O Power Domain Description 2, 4, 70, 72, 74 VCC PI 3.135-4.4 V 3.7 V typical DC supply 3, 5, 11, 27, 33, 39, 45, 51, 57, 71, 73 GND Ground 3.3.1. Decrease Voltage Drop The power supply range of the module is from 3.135 V to 4.4 V. Please ensure that the input voltage will never drop below 3.135 V, otherwise the module will be powered off automatically. The following figure shows the maximum voltage drop during radio transmission in 3G/4G/5G networks. RM502Q-GL_Hardware_Design 21 / 77 Figure 3: Power Supply Limits during Radio Transmission The main power supply from an external system must be a single voltage source. To decrease voltage drop, a bypass capacitor of about 100 F with low ESR (ESR = 0.7 ) should be used, and a multi-layer ceramic chip capacitor (MLCC) array also should be used due to its ultra-low ESR. It is recommended to use four ceramic capacitors (1 F, 100 nF, 33 pF, 10 pF) for composing the MLCC array, and place these capacitors close to VCC pins. The width of VCC trace should be no less than 2 mm. In principle, the longer the VCC trace is, the wider it should be. In addition, in order to get a stable power source, it is recommended to use a zener diode with a reverse zener voltage of 5.1 V and a dissipation power of more than 0.5 W. The following figure shows a reference circuit of VCC. 5G Module Series RM502Q-GL Hardware Design Figure 4: Reference Circuit of VCC Pins 3.3.2. Reference Design for Power Supply Power design for the module is very important, as the performance of the module largely depends on the power source. The power supply is capable of providing a sufficient current of at least 3 A. If the voltage drop between the input and output is not too high, it is suggested that an LDO is used to supply power for the module. If there is a big voltage difference between the input source and the desired output (VCC =

3.7 V Typ.), a buck DC-DC converter is preferred as the power supply. RM502Q-GL_Hardware_Design 22 / 77 VCCMax Tx powerMin.3.135VVoltage Ripple< 100mVVoltage DropMax Tx powerModulePMU2, 4, 70, 72, 74C1100FD15.1V3, 5, 11, 27, 33, 39, 45, 51, 57, 71, 73VCCVCCGNDC510pFC433pFC3100nFC31F+The following figure shows a reference design for +5 V input power source based on an DC-DC TPS54319. The typical output of the power supply is about 3.7 V and the maximum load current is 3 A. 5G Module Series RM502Q-GL Hardware Design Figure 5: Reference Design of Power Supply NOTE In order to avoid damages to the internal flash, please do not switch off the power supply directly when the module is working. It is suggested that the power supply can be cut off after the module is powered off by pulling down the FULL_CARD_POWER_OFF# pin for more than 10 s. 3.4. Turn on and off Scenarios 3.4.1. Turn on the Module FULL_CARD_POWER_OFF# asynchronous signal is an Active Low input that is used to turn off the entire module. When the input signal is asserted high ( 1.19 V) the Module will be enabled. When the input signal is driven low signal ( 0.2 V) or Tri-stated, it will force the module to shut down. This input signal is 3.3 V tolerant and can be driven by either 1.8 V or 3.3 V GPIO. Also, it has internally pulled down with a 100 k resistor. The following table shows the definition of FULL_CARD_POWER_OFF#. Table 6: Definition of FULL_CARD_POWER_OFF# Pin Pin No. Pin Name Description DC Characteristics Comment 6 FULL_CARD_ POWER_ OFF#

Turn on/off of the module. When it is at low level, the module is powered off. VIH(max) = 4.4 V VIH(min) = 1.19 V VIL(max) = 0.2 V Internally pulled down with a 100 k resistor RM502Q-GL_Hardware_Design 23 / 77 D1TVSPWR_INC8220 FC1110 pFC1033 pFC9100 nF+R1205kU1Q1NPNR847kR74.7kPWR_ENR4182kPWR_OUTL11.5 HTPS5431916121567891011121314345VINVINVINENVSNSCOMPRT/CLKSSPHPHPHBOOTPWRGDGNDGNDAGNDVFBR5330k 1%R6100k 1%C6100 nFPWRGDEP17R280.6kC710 nFR310kC410 nFC5NMVFBC2100 nFC333 pFC1470 F+

5G Module Series RM502Q-GL Hardware Design When it is at high level, the module is powered on. 3.4.1.1. Turn on the Module with a Host GPIO It is recommended to use a host GPIO to control FULL_CARD_POWER_OFF#. A simple reference circuit is illustrated in the following figure. Figure 6: Turn on the Module with a Host GPIO 3.4.1.2. Turn on the Module Automatically If FULL_CARD_POWER_OFF# is pulled up to VCC with a 510 k resistor, the module will be powered on automatically when the power supply for VCC is applied. A reference circuit is shown in the following figure. Figure 7: Turn on the Module Automatically RM502Q-GL_Hardware_Design 24 / 77 HostModuleFULL_CARD_POWER_OFF#PMUGPIO61.8V or 3.3VNote: The voltage of pin 6 should be no less than 1.19V when it is at HIGH level.R4100kHostModuleFULL_CARD_POWER_OFF#PMUGPIO6VCCNotes:1. The voltage of pin 6 should be no less than 1.19V when it is at HIGH level.2. The VCC represents the power supply of the module.R4100kR110k 5G Module Series RM502Q-GL Hardware Design 3.4.1.3. Turn on the Module with Compatible Design The following figure shows a compatible design to turn on the module automatically after power-up or by host. Figure 8: Turn on the Module with Compatible Design The turn-on scenario is illustrated in the following figure. Figure 9: Turn-on Timing of the Module NOTES 1. 2. tpower-on is time the interval between VCC and RESET_N HIGH level, which is a typically 33 ms. It is measured when RESET_N is not pulled down by the host device. tturn-on is the time interval between FULL_CARD_POWER_OFF# HIGH level and RFFE_VIO_1V8(an RM502Q-GL_Hardware_Design 25 / 77 HostModuleFULL_CARD_POWER_OFF#PMUGPIO6VCCNotes:1. The voltage of pin 6 should be no less than 1.19V when it is at HIGH level.2. The VCC represents the power supply of the module.Auto turn onTurn on by hostR1R210kNMNM0R4100kR110kR2NM_0VCCRESET_NTBDModule power-on or insertion detectionUSIM1_VDD / USIM2_VDDModule StatusFULL_CARD_POWER_OFF#RFFE_VIO_1V833 msSystem turn-on and bootingVIH 1.19 V1.8 V or 3.0 VSystem bootingInactiveActivetpower-ontturn-ontbooting68 mst0 3. 5G Module Series RM502Q-GL Hardware Design internal LDO output) HIGH level, which is typically 68 ms. t0 is the time interval between VCC and FULL_CARD_POWER_OFF# HIGH level. It could be 0 by turning on the module automatically as shown in Figure 7, or any other time decided by the host as shown in Figure 6. tbooting is the time interval between RFFE_VIO_1V8 HIGH level and the USIM_VDD power-on. 3.4.2. Turn off the Module 3.4.2.1. Turn off the Module through FULL_CARD_POWER_OFF#

In Figure 6, pulling down the FULL_CARD_POWER_OFF# pin will turn off the module. The turn off scenario is illustrated in the following figure. Figure 10: Turn-off Timing through FULL_CARD_POWER_OFF#

3.4.2.2. Turn off the Module through AT Command It is a safe way to use AT+QPOWD command to turn off the module. For more details about the command, please refer to document [2]. For the circuit design of Figure 6, please pull down FULL_CARD_POWER_OFF# pin, or cut off power supply of VCC after the module USB/PCIe is removed. Otherwise, the module will be powered on again. RM502Q-GL_Hardware_Design 26 / 77 VCCFULL_CARD_POWER_OFF#RUNNINGOFFModule StatusPower-off procedureRESET_N(H)10 s 5G Module Series RM502Q-GL Hardware Design Figure 11: Turn-off Timing through AT Command and FULL_CARD_POWER_OFF#

For the circuit design of Figure 7, please cut off power supply of VCC after the module USB/PCIe is removed, as illustrated in Figure 11. Otherwise, the module will be powered on again. Figure 12: Turn-off Timing through AT Command and Power Supply Please pull down FULL_CARD_POWER_OFF# pin immediately or cut off the power supply VCC when the host detects that the module USB/PCIe is removed. NOTE RM502Q-GL_Hardware_Design 27 / 77 VCCFULL_CARD_POWER_OFF#RUNNINGOFFModule StatusTurn off procedureRESET_N(H)USB/PCIeAT+QPOWDUSB/PCIe removedVCCFULL_CARD_POWER_OFF#(H)RUNNINGOFFModule StatusTurn off procedureRESET_N(H)USB/PCIeAT+QPOWDUSB/PCIe removed 5G Module Series RM502Q-GL Hardware Design 3.5. Reset RESET_N is an asynchronous and active low signal (1.8 V logic level). Whenever this pin is active, the modem will immediately be placed in a Power On Reset(POR) condition. CAUTION: Triggering the RESET# signal will lead to loss of all data in the modem and the removal of system drivers. It will also disconnect the modem from the network. Table 7: Definition of RESET_N Pin Pin No. Pin Name Description DC Characteristics Comment 67 RESET_N Reset the module VIH(max) = 2.1 V VIH(min) = 1.3 V VIL(max) = 0.5 V Internally pulled up to 1.8 V with a 100 k resistor The module can be reset by pulling down the RESET_N pin for 200700 ms. An open collector/drain driver or button can be used to control the RESET_N pin. Figure 13: Reference Circuit of RESET_N with NPN Driving Circuit RM502Q-GL_Hardware_Design 28 / 77 HostModuleRESET_NResetLogicGPIO67VDD 1.8VReset pulse200-700msR1100kR3100kR21kQ1NPN 5G Module Series RM502Q-GL Hardware Design Figure 14: Reference Circuit of RESET_N with NMOS Driving Circuit Figure 15: Reference Circuit of RESET_N with Button The reset scenario is illustrated in the following figure. Figure 16: Resetting Timing of the Module RM502Q-GL_Hardware_Design 29 / 77 HostModuleRESET_NResetLogicGPIO67VDD 1.8VReset pulse200-700 msR1100kR5100kR410RQ2NMOSModuleRESET_NResetLogic67VDD 1.8V200-700msS1TVSR1100k33pFC1Note: The capacitor C1 is recommended to be less than 47pF.VIL 0.5VVCC 200msResettingModule StatusRunningRESET_NRestart 700ms 5G Module Series RM502Q-GL Hardware Design 3.6. (U)SIM Interfaces The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both Class B (3.0 V) and Class C

(1.8 V) (U)SIM cards are supported, and Dual SIM Single Standby* function is supported. Table 8: Pin Definition of (U)SIM Interfaces Pin No. Pin Name I/O Description Comment 36 34 32 30 66 48 42 44 46 40 USIM1_VDD PO Power supply for (U)SIM1 card Class B (3.0 V) and Class C (1.8 V) USIM1_DATA IO

(U)SIM1 card data 1.8/3.0 V power domain USIM1_CLK DO

(U)SIM1 card clock 1.8/3.0 V power domain USIM1_RST DO

(U)SIM1 card reset 1.8/3.0 V power domain USIM1_DET DI Internally pulled up

(U)SIM1 card insertion detection. USIM2_VDD PO Power supply for (U)SIM2 card Either 1.8 V or 3.0 V is supported automatically. USIM2_DATA IO

(U)SIM2 card data 1.8/3.0 V power domain USIM2_CLK DO

(U)SIM2 card clock 1.8/3.0 V power domain USIM2_RST DO

(U)SIM2 card reset 1.8/3.0 V power domain USIM2_DET DI Internally pulled up to 1.8 V

(U)SIM2 card insertion detection. NOTE

* means under development. RM502Q-GL supports (U)SIM card hot-plug via the USIM_DET pin, which is a level trigger pin. With a normally closed (U)SIM card connector, the USIM_DET is normally short-circuited to ground when a

(U)SIM card is not inserted, and the USIM_DET will change from low to high level when the (U)SIM card is inserted. The rising edge indicates insertion of the (U)SIM card. When the (U)SIM card is removed, the USIM_DET will change from high to low level. This falling edge indicates the absence of the (U)SIM card. The following figure shows a reference design of (U)SIM interface with a normally closed (NC) (U)SIM card connector. RM502Q-GL_Hardware_Design 30 / 77 5G Module Series RM502Q-GL Hardware Design Figure 17: Reference Circuit of Normally Closed (U)SIM Card Connector Normally Closed (U)SIM Card Connector:

When the (U)SIM is absent, CD is short-circuited to ground and USIM_DET is at low level. When the (U)SIM is inserted, CD is open from ground and USIM_DET is at high level. The following figure shows a reference design of (U)SIM interface with a normally open (NO) (U)SIM card connector. Figure 18: Reference Circuit of Normally Open (U)SIM Card Connector Normally Open (U)SIM Card Connector:

When the (U)SIM is absent, CD1 is open from CD2 and USIM_DET is at low level. When the (U)SIM is inserted, CD1 is short-circuited to 1.8 V and USIM_DET is at high level. RM502Q-GL_Hardware_Design 31 / 77 Module(U)SIM CardConnectorUSIM1_DETUSIM1_DATAUSIM1_CLKRSTCLKCDIOUSIM1_VDDUSIM1_VDDUSIM1_RSTVCCGNDVPPGNDTVSNote: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout.363032663410-20k22R 22R 22R 33 pF33 pF33 pF100 nFModule(U)SIM CardConnectorUSIM1_DETUSIM1_DATAUSIM1_CLKRSTCLKCD1IOUSIM1_VDDUSIM1_VDDUSIM1_RSTVCCGNDVPPGNDTVSNote: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout.363032663410-20k22R 22R 22R 33 pF33 pF33 pF100 nF33k1.8V4.7kCD2 5G Module Series RM502Q-GL Hardware Design If (U)SIM card detection function is not needed, please keep USIM_DET unconnected. A reference circuit for (U)SIM card interface with a 6-pin (U)SIM card connector is illustrated in the following figure. Figure 19: Reference Circuit of a 6-Pin (U)SIM Card Connector In order to enhance the reliability and availability of the (U)SIM card in applications, please follow the criteria below in (U)SIM circuit design. Keep (U)SIM card connector as close as possible to the module. Keep the trace length as less than 200 mm as possible. Keep (U)SIM card signal traces away from RF and VCC traces. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with ground surrounded. In order to offer good ESD protection, it is recommended to add a TVS diode array with parasitic capacitance not exceeding 10 pF. The 22 resistors should be added in series between the module and the (U)SIM card connector so as to suppress EMI spurious transmission and enhance ESD protection. The 33 pF capacitors are used to filter out RF interference. The pull-up resistor on USIM_DATA trace improves anti-jamming capability and should be placed close to the (U)SIM card connector. 3.7. USB Interface RM502Q-GL provides one integrated Universal Serial Bus (USB) interface which complies with the USB 3.1 & 2.0 specifications and supports super speed (10) on USB 3.1 and high speed (480 Mbps) and full speed (12 Mbps) modes on USB 2.0. The USB interface is used for AT command communication, data transmission, GNSS NMEA sentence output, software debugging, firmware upgrade and voice over USB*. RM502Q-GL_Hardware_Design 32 / 77 Module(U)SIM CardConnectorUSIM1_DETUSIM1_DATAUSIM1_CLKRSTCLKIOUSIM1_VDDUSIM1_VDDUSIM1_RSTVCCGNDVPPGNDTVSNote: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout.363032663410-20k22R 22R 22R 33 pF33 pF33 pF100 nF 5G Module Series RM502Q-GL Hardware Design Please note that only USB 2.0 can be used for firmware upgrade currently. The following table shows the pin definition of USB interface. Table 9: Pin Definition of USB Interface Pin No. Pin Name I/O Description Comment USB_DP AI/AO USB 2.0 differential data bus (+) USB_DM AI/AO USB 2.0 differential data bus (-) USB_SS_TX_M AO USB 3.1 transmit data (-) USB_SS_TX_P AO USB 3.1 transmit data (+) USB_SS_RX_M AI USB 3.1 receive data (-) USB_SS_RX_P AI USB 3.1 receive data (+) Require differential impedance of 90 Require differential impedance of 90 Require differential impedance of 90

* means under development. For more details about the USB 3.1 & 2.0 specifications, please visit http://www.usb.org/home. The USB 2.0 interface is recommended to be reserved for firmware upgrade in designs. The following figure shows a reference circuit of USB 3.1 & 2.0 interface. Figure 20: Reference Circuit of USB 3.1 & 2.0 Interface RM502Q-GL_Hardware_Design 33 / 77 7 9 29 31 35 37 NOTE HostModuleUSB_DMUSB_DPUSB_SS_RX_PUSB_SS_RX_MUSB_SS_TX_PUSB_SS_TX_MBBUSB_DMUSB_DPUSB_SS_RX_PUSB_SS_RX_MUSB_SS_TX_PUSB_SS_TX_M9737353129ESDTest PointsMinimize these stubs in PCB layout.C5 220nFC6 220nFC1 220nFC2 220nFR1 0 R2 0 R3 NM-0 R4 NM-0 5G Module Series RM502Q-GL Hardware Design AC coupling capacitors C5 and C6 must be placed close to the host and close to each other. C1 and C2 have been integrated inside the module, so do not place these two capacitors on customers schematic and PCB. In order to ensure the signal integrity of USB 2.0 data traces, R1, R2, R3 and R4 must be placed close to the module, and the stubs must be minimized in PCB layout. In order to ensure that the USB interface designs corresponds with USB specifications, please comply with the following principles:

Do not route USB traces under or close to crystals, oscillators, magnetic components, RF signal traces or other high noisy signal traces. It is important to route USB differential pairs in inner layer of the PCB, and surround the traces with ground on that layer and with ground planes above and below. The impedance of USB 3.1 & 2.0 differential trace is 90 . For USB 2.0 signal traces, the trace length must be less than 120 mm, the differential data pair matching is less than 2 mm (15 ps). If USB connector is used, please keep the ESD protection components as close as possible to the USB connector. Pay attention to the influence of junction capacitance of ESD protection components on USB 2.0 data traces. The capacitance value of ESD protection components should be less than 2.0 pF for USB 2.0. If possible, reserve four 0 resistors (R1R4) on USB_DP and USB_DM as shown in the above figure. RM502Q-GL_Hardware_Design 34 / 77 5G Module Series RM502Q-GL Hardware Design 3.8. PCIe Interface RM502Q-GL provides one integrated PCIe (Peripheral Component Interconnect Express) interface which complies with the PCI Express Base Specification, Revision 3.0 and supports up to 8 Gbps per lane. PCI Express Base Specification Revision 3.0 compliance Data rate up to 8 Gbps per lane The following table shows the pin definition of PCIe interface. Table 10: Pin Definition of PCIe Interface Pin No. Pin Name I/O Description Comment 55 53 49 47 43 41 50 52 54 PCIE_REFCLK_P AI/AO PCIe reference clock (+) PCIE_REFCLK_M AI/AO PCIe reference clock (-) PCIE_RX_P AI PCIe receive data (+) PCIE_RX_M AI PCIe receive data (-) PCIE_TX_P AO PCIe transmit data (+) PCIE_TX_M AO PCIe transmit data (-) PCIE_RST_N DI PCIE_CLKREQ_N DO PCIE_WAKE_N DO PCIe reset. Active LOW. PCIe clock request. Active LOW. PCIe PME wake. Active LOW. 100 MHz. Require differential impedance of 85 Require differential impedance of 85 Require differential impedance of 85 Open drain Open drain Open drain 3.8.1. Endpoint Mode RM502Q-GL supports endpoint (EP) mode. In this mode, the module is configured as a PCIe EP device. The following figure shows a reference circuit of PCIe EP mode. RM502Q-GL_Hardware_Design 35 / 77 5G Module Series RM502Q-GL Hardware Design Figure 21: PCIe Interface Reference Circuit (EP Mode) In order to ensure the signal integrity of PCIe interface, AC coupling capacitors C5 and C6 should be placed close to the host on PCB. C1 and C2 have been integrated inside the module, so do not place these two capacitors on customers schematic and PCB. Figure 22: PCIe Power-on Timing Requirements of M.2 Specification RM502Q-GL_Hardware_Design 36 / 77 HostModulePCIE_REFCLK_PPCIE_REFCLK_MPCIE_RX_PPCIE_RX_MPCIE_TX_PPCIE_TX_MBBPCIE_REFCLK_PPCIE_REFCLK_MPCIE_RX_PPCIE_RX_MPCIE_TX_PPCIE_TX_M555349474341PCIE_CLKREQ_NPCIE_RST_NPCIE_WAKE_NPCIE_CLKREQ_NPCIE_RST_NPCIE_WAKE_NVCC_IO_HOST545250Note: The voltage level of VCC_IO_HOST depends on the host side due to the open drain in pins 50, 52 and 54.C6 220nFC5 220nFC2 220nFC1 220nFR1100kR2100kR3100k 5G Module Series RM502Q-GL Hardware Design Figure 23: PCIe Power-on Timing Requirements of the Module The following principles of PCIe interface design should be complied with, so as to meet PCIe V2.1 specification. Do not route signal traces under crystals, oscillators, magnetic devices or RF signal traces. It is important to route the PCIe differential signal traces in inner layer of the PCB, and surround the traces with ground on that layer and with ground planes above and below. For PCIe signal traces, the recommended maximum length for TX and RX differential data pairs is less than 250 mm, and the intra-lane length matching of TX and RX differential data pairs is less than 0.7 mm (5 ps). 3.8.2. USB Version and PCIe Version Begin with ES2 (Engineering Samples 2), RM502Q-GL supports USB version and PCIe only version described as below:

USB version Support all USB 2.0/3.1 features Support MBIM/QMI/QRTR/AT Support switch between USB and PCIe by AT command USB is the default communication interface between RM502Q-GL module and a host. If PCIe interface is desired, an AT command under USB interface mode could be used. For more details about the AT command, please refer to document [2]. It is suggested that USB 2.0 interface could be reserved for firmware upgrade. RM502Q-GL_Hardware_Design 37 / 77 VCCFULL_CARD_POWER_OFF#Module power-on or insertion detectionRESET_NRFFE_VIO_1V8System turn-on and bootingVIH 1.19 V23 msPCIE_CLKREQ_NPCIE_RST_NPCIE_REFCLKTPVPGL > 50 mstturn-on68 ms33 mstpower-onTPERST#-CLK > 100 us 5G Module Series RM502Q-GL Hardware Design USB-AT-based PCIe Version Support MBIM/QMI/QRTR/AT Support switch back to USB interface by AT command Support Non-X86 systems, need to be initiated in X86 system to meet BIOS PCIe early initial requirement When RM502Q-GL module works at USB-AT-based PCIe version, it supports MBIM/QMI/QRTR/AT, and can be switched back to USB version by AT command. But it does not support firmware upgrade by PCIE interface, therefore RM502Q-GL USB 2.0 interface must be reserved for firmware upgrade. Please note that the USB-AT-based PCIe version cannot support BIOS PCIe early initial in X86 systems, but it could be initiated by other module which supports BIOS PCIe early initial. And Non-X86 systems does not have this problem. eFuse-based PCIe version Support MBIM/QMI/QRTR/AT Support Non-X86 Systems and X86 system (could meet BIOS PCIe early initial) If RM502Q-GL works at eFuse-based PCIe interface by burnt eFuse, the module cannot be switched back to USB version. Please note that PCIe firmware upgrade may not be supported on non-Qualcomm AP chips. If the host does not support firmware upgrade at the PCIe only version, then RM502Q-GL USB 2.0 interface (pins 7 and 9) and two test points (VREG_L6E_1P8 and FORCE_USB_BOOT, reserved on bottom side) must be used for firmware upgrade. Also, the firmware could be upgraded by the PCIe Card EVB, which could be inserted into a PC. For more details, please refer to document [1]. 3.9. PCM Interface*

RM502Q-GL supports audio communication via Pulse Code Modulation (PCM) digital interface. The PCM interface supports the following modes:

Primary mode (short frame synchronization): the module works as both master and slave Auxiliary mode (long frame synchronization): the module works as master only In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC falling edge represents the MSB. In this mode, the PCM interface supports 256 kHz, 512 kHz, 1024 kHz or 2048 kHz PCM_CLK at 8 kHz PCM_SYNC, and also supports 4096 kHz PCM_CLK at 16 kHz PCM_SYNC. RM502Q-GL_Hardware_Design 38 / 77 5G Module Series RM502Q-GL Hardware Design In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC rising edge represents the MSB. In this mode, PCM interface operates with a 256 kHz PCM_CLK and an 8 kHz, 50% duty cycle PCM_SYNC only. RM502Q-GL supports 16-bit linear data format. The following figures show the primary modes timing relationship with 8 kHz PCM_SYNC and 2048 kHz PCM_CLK, as well as the auxiliary modes timing relationship with 8 kHz PCM_SYNC and 256 kHz PCM_CLK. Figure 24: Primary Mode Timing Figure 25: Auxiliary Mode Timing The following table shows the pin definition of PCM interface which can be applied on audio codec design. RM502Q-GL_Hardware_Design 39 / 77 PCM_CLKPCM_SYNCPCM_DOUTMSBLSBMSB125s12256255PCM_DINMSBLSBMSBPCM_CLKPCM_SYNCPCM_DOUTMSBLSBPCM_DIN125sMSB123231LSB 5G Module Series RM502Q-GL Hardware Design Table 11: Pin Definition of PCM Interface*

Pin No. Pin Name I/O Description Comment 20 PCM_CLK IO PCM data bit clock 1.8 V power domain In master mode, it is an output signal. In slave mode, it is an input signal. If unused, keep it open. PCM_DIN DI PCM data input 1.8 V power domain PCM_DOUT DO PCM data output 1.8 V power domain PCM_SYNC IO PCM data frame sync 1.8 V power domain The clock and mode can be configured by AT command, and the default configuration is master mode using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. Please refer to document [2] for details about AT+QDAI command. NOTE

* means under development. 3.10. Control and Indication Interfaces The following table shows the pin definition of control and indication pins. Table 12: Pin Definition of Control and Indication Interfaces Pin No. Pin Name I/O Description Comment W_DISABLE1#*

DI Airplane mode control. Active LOW. 1.8/3.3 V WWAN_LED#*

OD WAKE_ON_WAN#* OD It is an open drain and active low signal. Indicate RF status of the module. Wake up the host. It is an open drain and active low signal. DPR*

DI Dynamic power reduction. High level by default. 1.8 V W_DISABLE2#*

DI GNSS disable control. Active LOW. 1.8/3.3 V SDX2AP_STATUS DO Status indication to AP 1.8 V power domain RM502Q-GL_Hardware_Design 40 / 77 22 24 28 8 10 23 25 26 38 68 AP2SDX_STATUS DI Status indication from AP 1.8 V power domain 5G Module Series RM502Q-GL Hardware Design NOTE

* means under development. 3.10.1. W_DISABLE1#*

RM502Q-GL provides a W_DISABLE1# pin to disable or enable airplane mode through hardware operation. The W_DISABLE1# pin is pulled up by default. Driving it low will set the module to airplane mode. In airplane mode, the RF function will be disabled. The RF function can also be enabled or disabled through software AT commands. The following table shows the RF function status of the module. Table 13: RF Function Status W_DISABLE1# Level AT Commands RF Function Status High Level AT+CFUN=1 Enabled High Level Low Level AT+CFUN=0 AT+CFUN=4 AT+CFUN=0 AT+CFUN=1 AT+CFUN=4 Disabled Disabled 3.10.2. W_DISABLE2#*

RM502Q-GL provides a W_DISABLE2# pin to disable or enable the GNSS function. The W_DISABLE2#

pin is pulled up by default. Driving it low will disable the GNSS function. The combination of W_DISABLE2# pin and AT commands can control the GNSS function. RM502Q-GL_Hardware_Design 41 / 77 5G Module Series RM502Q-GL Hardware Design Table 14: GNSS Function Status W_DISABLE2# Level AT Commands GNSS Function Status High Level AT+QGPS=1 Enabled High Level AT+QGPSEND Low Level AT+QGPS=1 Disabled Low Level AT+QGPSEND A simple level shifter based on diodes is used on W_DISABLE1# pin and W_DISABLE2# pin which are pulled up to a 1.8 V voltage in the module, as shown in the following figure. So the control signals (GPIO) of the host device could be a 1.8 V or 3.3 V voltage level. W_DISABLE1# and W_DISABLE2# are active low signals, and a reference circuit is shown as below. Figure 26: W_DISABLE1# and W_DISABLE2# Reference Circuit 3.10.3. WWAN_LED#*

The WWAN_LED# signal is used to indicate RF status of the module, and its sink current is up to 10 mA. In order to reduce current consumption of the LED, a current-limited resistor must be placed in series with the LED, as illustrated in the figure below. The LED is ON when the WWAN_LED# signal is at low level. RM502Q-GL_Hardware_Design 42 / 77 HostModuleW_DISABLE2#W_DISABLE1#BBGPIOGPIO268VDD 1.8VNotes: The voltage level of VCC_IO_HOST could be 1.8V or 3.3V typically.R3100kR2100kR510kVCC_IO_HOSTR610k 5G Module Series RM502Q-GL Hardware Design Figure 27: WWAN_LED# Reference Circuit The following table shows the RF status indicated by WWAN_LED# signal. Table 15: Network Status Indications of WWAN_LED# Signal WWAN_LED# Level Description Low Level (LED ON) RF function is turned on RF function is turned off if any of the following occurs:

The (U)SIM card is not powered. W_DISABLE1# is at low level (airplane mode enabled). AT+CFUN=4 (RF function disabled). High Level (LED OFF) 3.10.4. WAKE_ON_WAN#*

The WAKE_ON_WAN# is an open drain pin, which requires a pull-up resistor on the host. When a URC returns, a 1 s low level pulse signal will be outputted to wake up the host. The module operation status indicated by WAKE_ON_WAN# is shown as below. Table 16: State of the WAKE_ON_WAN# Signal WAKE_ON_WAN# State Module Operation Status Output a 1 s low level pulse signal Call/SMS/Data is incoming (to wake up the host) Always at high level Idle/Sleep RM502Q-GL_Hardware_Design 43 / 77 HostModuleWWAN_LED#PMUGPIO10VCCNote: This VCC could be the power supply of the module.LEDR1330 5G Module Series RM502Q-GL Hardware Design Figure 28: WAKE_ON_WAN# Signal Reference Circuit 3.10.5. DPR*

RM502Q-GL provides a DPR (Dynamic Power Reduction) pin for body SAR (Specific Absorption Rate) detection. The signal is sent from a host system proximity sensor to RM502Q-GL module to provide an input trigger, which will reduce the output power in radio transmission. Table 17: Function of the DPR Signal DPR Level Function High/Floating Max transmitting power will NOT back off Low Max transmitting power will back off by executing AT+QCFG="sarcfg" command Please refer to document [2] for more details about AT+QCFG="sarcfg" command. NOTE 3.10.6. STATUS*

RM502Q-GL provides two status indication pins for communication with IPQ807x device. Pin 38

(SDX2AP_STATUS) outputs IPQ807x device, and pin 68 the status

(AP2SDX_STATUS) inputs the status indication signal from IPQ807x device. indication signal to RM502Q-GL_Hardware_Design 44 / 77 HostModuleWAKE_ON_WAN#BBGPIO23VCC_IO_HOSTNote: The voltage level on VCC_IO_HOST depends on the host side due to the open drain in pin 23.Wake up the host1sHLR110k 5G Module Series RM502Q-GL Hardware Design 3.11. Cellular/WLAN Interface*

RM502Q-GL provides a cellular/WLAN COEX interface, the following table shows the pin definition of this interface. Table 18: Pin Definition of COEX Interface Pin No. Pin Name I/O Description Comment COEX_RXD DI LTE/WLAN coexistence receive data 1.8 V power domain COEX_TXD DO LTE/WLAN coexistence transmit data 1.8 V power domain LAA_TX_EN DO 1.8 V power domain Notification from SDR to WL when LTE transmitting Notification from WL to SDR while transmitting WLAN_TX_EN DI 1.8 V power domain

* means under development. 3.12. Antenna Tuner Control Interface*

ANTCTL[1:2] are used for antenna tuner control and should be routed to an appropriate antenna control circuit. More details about the interface will be added in the future version of this document. Table 19: Pin Definition of Antenna Tuner Control Interface Pin No. Pin Name I/O Description DC Characteristics 61 63 SDR_GRFC15 DO SDR_GRFC14 DO GRFC interface dedicated for external antenna tuner control VOLmax = 0.45 V VOHmin = 1.35 V VOHmax = 1.8 V NOTE support based on CS2 and later. RM502Q-GL_Hardware_Design 45 / 77 62 64 59 60 NOTE 5G Module Series RM502Q-GL Hardware Design 3.13. Configuration Pins RM502Q-GL provides four configuration pins, which are defined as below. Table 20: Definition of Configuration Pins Pin No. Pin Name Power Domain Description 21 69 75 1 CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 I/O DO DO DO DO 0 0 0 0 Connected to GND internally NC internally NC internally NC internally The following figure shows a reference circuit of these four pins. Figure 29: Recommended Circuit of Configuration Pins Table 21: Configuration Pins List of M.2 Specification Config_0

(Pin 21) Config_1

(Pin 69) Config_2

(Pin 75) Config_3

(Pin 1) Module Type and Main Host Interface Port Configuration NC GND NC NC Quectel defined N/A RM502Q-GL_Hardware_Design 46 / 77 HostModuleCONFIG_0CONFIG_1CONFIG_2CONFIG_3GPIOGPIOGPIOGPIO2169751VCC_IO_HOSTR110kR210kR310kR410kNM-0 NM-0 NM-0 0 Note: The voltage level of VCC_IO_HOST depends on the host side and could be 1.8V or 3.3V. 5G Module Series RM502Q-GL Hardware Design 4 GNSS Receiver 4.1. General Description RM502Q-GL includes a fully integrated global navigation satellite system solution that supports Gen9-Lite of Qualcomm (GPS, GLONASS, BeiDou/Compass, and Galileo). The module supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1 Hz data update rate via USB interface by default. By default, RM502Q-GL GNSS engine is switched off. It has to be switched on via AT command. For more details about GNSS engine technology and configurations, please refer to document [3]. RM502Q-GL_Hardware_Design 47 / 77 5G Module Series RM502Q-GL Hardware Design 4.2. GNSS Performance The following table shows GNSS performance of RM502Q-GL series module. Table 22: GNSS Performance Parameter Description Conditions Sensitivity

(GNSS) Cold start Autonomous Reacquisition Autonomous Tracking Autonomous TTFF

(GNSS) Warm start

@ open sky Cold start

@ open sky Hot start

@ open sky CEP-50 Autonomous XTRA enabled Autonomous XTRA enabled Autonomous XTRA enabled Autonomous

@ open sky Typ. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit dBm dBm dBm s s s s s s m 1. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep 2. Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock positioning for at least 3 minutes continuously). within 3 minutes after the loss of lock. 3. Cold start sensitivity: the minimum GNSS signal power at which the module can fix position successfully within 3 minutes after executing cold start command. Accuracy

(GNSS) NOTES RM502Q-GL_Hardware_Design 48 / 77 5G Module Series RM502Q-GL Hardware Design 5 Antenna Connection RM502Q-GL provides four antenna interfaces, the impedance of antenna port is 50 . 5.1. RF Antenna Interfaces 5.1.1. Antenna Pin Definition The pin definition of RF antenna interfaces is shown below. Table 23: Pin Definition of RF Antenna Interfaces Pin Name I/O Description ANT0 AI/AO ANT1 AI/AO ANT2_ GNSSL1 AI/AO ANT3 AI/AO Antenna0 interface, 5GNR (n41/n77/n78 TRx1) &

LTE LMHB TRx0 & B42/B43/B48 MIMO1 Antenna1 interface, 5GNR (n77/n78 DRx) & n41 TRx0 & LTE MHB MIMO1 & B42/B43/B48 DRX &

LAA PRx Antenna2 interface, 5GNR (n77/n78 MIMO2,n41 DRx) & LTE MHB MIMO2 & B42/B43/B48 MIMO2 &

LAA DRx & GNSS L1 Comment 50 impedance 50 impedance 50 impedance Antenna3 interface, 5GNR (n77/n78 TRx0, n41 MIMO2) & LTE LMHB DRx & B42/B43/B48 TRx0 50 impedance LTE LMHB TRx0 also supports 5G NR FDD low, middle and high bands in SA mode (under development). NOTE RM502Q-GL_Hardware_Design 49 / 77 5G Module Series RM502Q-GL Hardware Design 5.1.2. RF Antenna Port Mapping Table 24: RM502Q-GL RF Antenna Mapping 4G 5G NR n41 n77/n78 Antenna LB

(MHz) MHB

(MHz) n77/78

(MHz) NOTE TRx1 TRx1 ANT0 Div1 TRx0 ANT3 617 to 960 1452 to 2690 3300 to 4200 617 to 960 1452 to 2690 3300 to 4200 TRx0 Div0 ANT1 1452 to 2690 3300 to 4200 Div0 Div1 ANT2_ GNSSL1 1452 to 2690 3300 to 4200 LB/MHB TRx0 B42/B43/B48 MIMO1 LB/MHB DRx B42/B43/B48 TRx0 MHB PRx MIMO B42/B43/B48 DRX, LAA PRX MHB DRx MIMO B42/B43/B48 MIMO2, LAA DRx n77 group also includes B42/B48 function. 5.1.3. Operating Frequency Table 25: RM502Q-GL Module Operating Frequencies Band Name Transmit (MHz) Receive (MHz) LTE-FDD LTE-TDD UMTS 5G NR IMT (2100) 19201980 21102170 PCS (1900) 18501910 19301990 DCS (1800) 17101785 18051880 AWS 17101755 21102155 Cell (850) 824849 869894 JCELL (800) 830840 875885 B1 B2 B3 B4 B5 B1 B2 B3 B4 B5 B6 n1 n2 n3 n5 RM502Q-GL_Hardware_Design 50 / 77 5G Module Series RM502Q-GL Hardware Design 830845 875890 B19 IMT-E (2600) 25002570 26202690 EGSM (950) 880915 925960 J1700 17501785 18451880 700 lower AC 699716 729746 700 upper C 777787 746756 700 D 788798 758768 704716 734746 815830 860875 EU800 832862 791821 PCS + G 18501915 19301995 B26 814849 859894 700 APAC 703748 758803 FLO WCS L-band 23052315 23502360 717728 14521496 B41/B41-XGP 24962690 24962690 20102025 20102025 25702620 25702620 18801920 18801920 23002400 23002400 34003600 34003600 36003800 36003800 51505925 51505925 35503700 35503700 17101780 21102200 663698 617652 33004200 33004200 B17 B18 B19 B34 B38 B39 B40 B42 B43 B46 B48 B66 B71 n77 B7 B8 B9 B12 B13 B14 B17 B18 B19 B20 B25 B26 B28 B29 B30 B32 B66 B71 B34 B38 B39 B40 B41 B42 B43 B46 B48 B8 B9 n7 n8 n12 n20 n28 n38 n40 n41 n48 n66 n71 n77 RM502Q-GL_Hardware_Design 51 / 77 5G Module Series RM502Q-GL Hardware Design n78 33003800 33003800 n78 5.1.4. Reference Design of RF Antenna Interface A reference design of antenna interface is shown as below. A -type matching circuit should be reserved for better RF performance. The capacitors are not mounted by default. Figure 30: Reference Circuit of RF Antenna 1. Keep the characteristic impedance for antenna trace as 50 . 2. Place the -type matching components as close to the antenna as possible. 3. Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card should be kept away from the antenna traces. 4. Keep 75 dB PCB isolation between two antenna traces. 5. Keep 15 dB isolation between each antenna to improve the receiving sensitivity. 6. It is suggested to keep 20 dB isolation between 5G NR UL MIMO Tx0 and Tx1 antennas. NOTES 5.2. GNSS Antenna Interface The following table shows frequency specification of GNSS antenna connector. RM502Q-GL_Hardware_Design 52 / 77 ModuleANT3ANT0R1 0 R4 0 C1NMC2NMC8NMC7NM Galileo QZSS GLONASS BeiDou NOTES Table 26: GNSS Frequency 5G Module Series RM502Q-GL Hardware Design Type Frequency GPS/Galileo/QZSS 1575.42 1.023 (L1) 1575.42 2.046 (E1) 1575.42 (L1) 1597.51605.8 1561.098 2.046 Unit MHz MHz MHz MHz MHz 1. Keep the characteristic impedance for ANT_GNSS trace as 50 . 2. Place the -type matching components as close to the antenna as possible. 3. Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card should be kept away from the antenna traces. 4. Keep 75 dB isolation between two antenna traces. 5. Keep 15 dB isolation between each antenna to improve the receiving sensitivity. 5.3. Reference Design of RF Layout For users PCB, the characteristic impedance of all RF traces should be controlled as 50 . The impedance of the RF traces is usually determined by the trace width (W), the materials dielectric constant, the height from the signal layer to reference ground (H), and the space between RF trace and ground (S). Microstrip or coplanar waveguide is typically used in RF layout for characteristic impedance control. The following are reference designs of microstrip or coplanar waveguide with different PCB structures. RM502Q-GL_Hardware_Design 53 / 77 5G Module Series RM502Q-GL Hardware Design Figure 31: Microstrip Design on a 2-layer PCB Figure 32: Coplanar Waveguide Design on a 2-layer PCB Figure 33: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) RM502Q-GL_Hardware_Design 54 / 77 5G Module Series RM502Q-GL Hardware Design Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:

Use impedance simulation tool to control the characteristic impedance of RF traces as 50 . The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground. The distance between the RF pins and the RF connector should be as short as possible. All the right angle traces should be changed to curved ones, and the recommended angle is 135. There should be clearance area under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground improves RF performance. The distance between the ground vias and RF traces should be no less than two times the width of RF signal traces (2*W). For more details about RF layout, please refer to document [4]. 5.4. Antenna Connectors The ANT0, ANT1, ANT2_GNSSL1 and ANT3 antenna connectors are shown as below. RM502Q-GL_Hardware_Design 55 / 77 5G Module Series RM502Q-GL Hardware Design Figure 35: Antenna Connectors on the Module 5.4.1 RF Bands Supported by Antenna Connectors Table 27: RF Bands Supported by RM502Q-GL Antenna Connectors Pin Name Description Antenna0 interface, 5GNR (n41/n77/n78 TRx1) & LTE LMHB TRx0 & B42/B43/B48 MIMO1 Antenna1 interface, 5GNR (n77/n78 DRx) & N41 TRx0 &

LTE MHB MIMO1 & B42/B43/B48 DRX & LAA PRx Antenna2 interface, 5GNR (n77/n78 MIMO2, N41 DRx)

& LTE MHB MIMO2 & B42/B43/B48 MIMO2 & LAA DRx

& GNSS L1 Frequency 6005000 MHz 11006000 MHz 14006000 MHz Antenna3 interface, 5GNR (n77/n78 TRx0, N41 MIMO2)

& LTE LMHB DRx & B42/B43/B48 TRX 6005000 MHz ANT2_GNSSL1 ANT0 ANT1 ANT3 NOTE n77 group also includes B42/B48 function. RM502Q-GL_Hardware_Design 56 / 77 5G Module Series RM502Q-GL Hardware Design 5.5. Antenna Installation 5.5.1. Antenna Requirements The following table shows the requirements on WCDMA, LTE, 5G NR antenna and GNSS antenna. Table 28: Antenna Requirements Type Requirements Frequency range: 15591606 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: >0 dBi VSWR: 3 Efficiency: > 30%

Input Impedance: 50 WCDMA LB, LTE LB: Cable insertion loss: < 1 dB WCDMA MB, LTE MB: Cable insertion loss: < 1.5 dB LTE HB, 5G NR TDD MHB: Cable insertion loss < 2 dB GNSS WCDMA/LTE/5G NR 5.5.2. Recommended RF Connector for Antenna Installation RM502Q-GL is mounted with standard 2 mm 2 mm receptacle RF connectors for convenient antenna connection. The connector dimensions are illustrated as below:

RM502Q-GL_Hardware_Design 57 / 77 5G Module Series RM502Q-GL Hardware Design Figure 36: RM502Q-GL RF Connector Dimensions (Unit: mm) Item Table 29: Major Specifications of the RF Connector Specification Nominal Frequency Range DC to 6 GHz Nominal Impedance 50 Temperature Rating

-40C to +85C Voltage Standing Wave Ratio (VSWR) Meet the requirements of:

Max 1.3 (DC3 GHz) Max 1.45 (36 GHz) The receptacle RF connector used in conjunction with RM502Q-GL will accept two types of mating plugs that will meet a maximum height of 1.2 mm using a 0.81 mm coaxial cable or a maximum height of 1.45 mm utilizing a 1.13 mm coaxial cable. The following figure shows the specifications of mating plugs using 0.81 mm coaxial cables. Figure 37: Specifications of Mating Plugs Using 0.81 mm Coaxial Cables The following figure illustrates the connection between the receptacle RF connector on RM502Q-GL and the mating plug using a 0.81 mm coaxial cable. RM502Q-GL_Hardware_Design 58 / 77 5G Module Series RM502Q-GL Hardware Design Figure 38: Connection between RF Connector and Mating Plug Using 0.81 mm Coaxial Cable The following figure illustrates the connection between the receptacle RF connector on RM502Q-GL and the mating plug using a 1.13 mm coaxial cable. Figure 39: Connection between RF Connector and Mating Plug Using 1.13 mm Coaxial Cable RM502Q-GL_Hardware_Design 59 / 77 5G Module Series RM502Q-GL Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 30: Absolute Maximum Ratings Parameter VCC Voltage at Digital Pins Min.

-0.3

-0.3 Max. Unit 4.7 2.3 V V 6.2. Power Supply Requirements The typical input voltage of RM502Q-GL is 3.7 V, as specified by PCIe M.2 Electromechanical Specification Rev 1.0. The following table shows the power supply requirements of RM502Q-GL. Table 31: Power Supply Requirements Parameter Description Min. Typ. Max. Unit VCC Power Supply 3.135 3.7 Voltage Ripple Voltage Drop 30 4.4 100 165 V mV mV RM502Q-GL_Hardware_Design 60 / 77 5G Module Series RM502Q-GL Hardware Design 6.3. I/O Requirements Table 32: I/O Requirements Parameter Description Min. Max. Unit Input high voltage 0.7 VDD18 1) VDD18 +0.3 Input low voltage

-0.3 0.3 VDD18 Output high voltage VDD18-0.5 Output low voltage 0 VDD18 0.4 V V V V 1) VDD18 is the I/O power domain of the module. 6.4. Operation and Storage Temperatures Table 33: Operation and Storage Temperatures Parameter Min. Typ. Max. Unit Operation Temperature Range1)

-30 Extended Temperature Range2)

-40 Storage temperature Range

-40

+25

+25

+25

+60

+85

+90 C C C VIH VIL VOH VOL NOTE NOTES 1. 1) Within operation temperature range, the module is 3GPP compliant. 2. 2) Within extended temperature range, the module remains the ability to establish and maintain a voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce in their values and exceed the specified tolerances. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again. RM502Q-GL_Hardware_Design 61 / 77 6.5. Current Consumption Table 34: RM502Q-GL Current Consumption Parameter Description Conditions OFF state Power down AT+CFUN=0 (USB disconnected) WCDMA PF = 64 (USB disconnected) WCDMA PF = 128 (USB disconnected) WCDMA PF = 512 (USB disconnected) Sleep state LTE-FDD PF = 32 (USB disconnected) LTE-FDD PF = 64 (USB disconnected) LTE-FDD PF = 128 (USB disconnected) IVBAT LTE-TDD PF = 32 (USB disconnected) LTE-TDD PF = 64 (USB disconnected) LTE-TDD PF = 128 (USB disconnected) WCDMA PF = 64 (USB disconnected) WCDMA PF = 64 (USB connected) LTE-FDD PF = 64 (USB disconnected) LTE-FDD PF = 64 (USB connected) LTE-TDD PF = 64 (USB disconnected) LTE-TDD PF = 64 (USB connected) Idle state 5G Module Series RM502Q-GL Hardware Design Typ. Unit TBD A TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA IVBAT WCDMA data transfer

(GNSS OFF) WCDMA B1 HSDPA CH10700 @ 23 dBm TBD WCDMA B1 HSUPA CH10700 @ 23 dBm TBD WCDMA B2 HSDPA CH9800 @ 23 dBm WCDMA B2 HSUPA CH9800 @ 23 dBm RM502Q-GL_Hardware_Design 62 / 77 5G Module Series RM502Q-GL Hardware Design IVBAT WCDMA data transfer

(GNSS OFF) IVBAT WCDMA B3 HSDPA CH1338 @ 23 dBm WCDMA B3 HSUPA CH1338 @ 23 dBm WCDMA B4 HSDPA CH1638 @ 23 dBm WCDMA B4 HSUPA CH1638 @ 23 dBm WCDMA B5 HSDPA CH4407 @ 23 dBm WCDMA B5 HSUPA CH4407 @ 23 dBm WCDMA B6 HSDPA CH4400 @ 23 dBm WCDMA B6 HSUPA CH4400 @ 23 dBm WCDMA B8 HSDPA CH3012 @ 23 dBm WCDMA B8 HSUPA CH3012 @ 23 dBm WCDMA B19 HSDPA CH738 @ 23 dBm WCDMA B19 HSUPA CH738 @ 23 dBm LTE data transfer

(GNSS OFF) LTE-FDD B1 CH300 @ 23 dBm LTE-FDD B2 CH900 @ 23 dBm LTE-FDD B3 CH1575 @ 23 dBm LTE-FDD B4 CH2175 @ 23 dBm LTE-FDD B5 CH2525 @ 23 dBm LTE-FDD B7 CH3100 @ 23 dBm LTE-FDD B8 CH3625 @ 23 dBm LTE-FDD B9 CH3975 @ 23 dBm LTE-FDD B12 CH5095 @ 23 dBm LTE-FDD B13 CH5230 @ 23 dBm LTE-FDD B14 CH5330 @ 23 dBm LTE-FDD B17 CH5790 @ 23 dBm LTE-FDD B18 CH5925 @ 23 dBm LTE-FDD B19 CH6075 @ 23 dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA RM502Q-GL_Hardware_Design 63 / 77 5G Module Series RM502Q-GL Hardware Design IVBAT IVBAT LTE Data transfer

(GNSS OFF) LTE-FDD B20 CH6300 @ 23 dBm LTE-FDD B25 CH8365 @ 23 dBm LTE-FDD B26 CH8865 @ 23 dBm LTE-FDD B28 CH9435 @ 23 dBm LTE-FDD B30 CH9820 @ 23 dBm LTE-TDD B34 CH36275 @ 23 dBm LTE-TDD B38 CH38000 @ 23 dBm LTE-TDD B39 CH38450 @ 23 dBm LTE-TDD B40 CH39150 @ 23 dBm LTE-TDD B41 CH40620 @ 23 dBm LTE-TDD B42 CH42590 @ 23 dBm LTE-TDD B43 CH44590 @ 23 dBm LTE-TDD B48 CH55990 @ 23 dBm LTE-FDD B66 CH66886 @ 23 dBm LTE-FDD B71 CH68761 @ 23 dBm 5G NR data transfer

(GNSS OFF) 5G NR-TDD n41 CH501204 @ 23 dBm 5G NR-TDD n41 CH518598 @ 23 dBm 5G NR-TDD n41 CH535998 @ 23 dBm 5G NR-TDD n77 CH620668 @ 23 dBm 5G NR-TDD n77 CH650000 @ 23 dBm 5G NR-TDD n77 CH679332 @ 23 dBm 5G NR-TDD n78 CH620668 @ 23 dBm 5G NR-TDD n78 CH636666 @ 23 dBm 5G NR-TDD n78 CH652666 @ 23 dBm 5G NR-FDD n1 CH423000 @ 23 dBm 5G NR-FDD n1 CH428000 @ 23 dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA RM502Q-GL_Hardware_Design 64 / 77 5G Module Series RM502Q-GL Hardware Design IVBAT 5G NR data transfer

(GNSS OFF) 5G NR-FDD n1 CH433000 @ 23 dBm 5G NR-FDD n2 CH387000 @ 23 dBm 5G NR-FDD n2 CH392000 @ 23 dBm 5G NR-FDD n2 CH397000 @ 23 dBm 5G NR-FDD n3 CH362000 @ 23 dBm 5G NR-FDD n3 CH368500 @ 23 dBm 5G NR-FDD n3 CH375000 @ 23 dBm 5G NR-FDD n5 CH174800 @ 23 dBm 5G NR-FDD n5 CH176300 @ 23 dBm 5G NR-FDD n5 CH177800 @ 23 dBm 5G NR-FDD n7 CH525000 @ 23 dBm 5G NR-FDD n7 CH531000 @ 23 dBm 5G NR-FDD n7 CH537000 @ 23 dBm 5G NR-FDD n8 CH186000 @ 23 dBm 5G NR-FDD n8 CH188500 @ 23 dBm 5G NR-FDD n8 CH191000 @ 23 dBm 5G NR-FDD n12 CH146800 @ 23 dBm 5G NR-FDD n12 CH147500 @ 23 dBm 5G NR-FDD n12 CH148200 @ 23 dBm 5G NR-FDD n20 CH159200 @ 23 dBm 5G NR-FDD n20 CH161200 @ 23 dBm 5G NR-FDD n20 CH163200 @ 23 dBm 5G NR-FDD n28 CH152600 @ 23 dBm 5G NR-FDD n28 CH156100 @ 23 dBm 5G NR-FDD n28 CH159600 @ 23 dBm 5G NR-TDD n38 CH515000 @ 23 dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA RM502Q-GL_Hardware_Design 65 / 77 5G Module Series RM502Q-GL Hardware Design IVBAT 5G NR data transfer

(GNSS OFF) 5G NR-TDD n38 CH519000 @ 23 dBm 5G NR-TDD n38 CH523000 @ 23 dBm 5G NR-TDD n40 CH461000 @ 23 dBm 5G NR-TDD n40 CH470000 @ 23 dBm 5G NR-TDD n40 CH479000 @ 23 dBm 5G NR-FDD n66 CH423000 @ 23 dBm 5G NR-FDD n66 CH429000 @ 23 dBm 5G NR-FDD n66 CH435000 @ 23 dBm 5G NR-FDD n71 CH124400 @ 23 dBm 5G NR-FDD n71 CH126900 @ 23 dBm 5G NR-FDD n71 CH129400 @ 23 dBm WCDMA B1 CH10700 @ 23 dBm WCDMA B2 CH9800 @ 23 dBm WCDMA B3 CH1338 @ 23 dBm IVBAT WCDMA voice call WCDMA B4 CH1638 @ 23 dBm WCDMA B5 CH4408 @ 23 dBm WCDMA B6 CH4175 @ 23 dBm WCDMA B8 CH3012 @ 23 dBm WCDMA B19 CH338 @ 23 dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA RM502Q-GL_Hardware_Design 66 / 77 5G Module Series RM502Q-GL Hardware Design 6.6. RF Output Power The following table shows the RF output power of RM502Q-GL module. Table 35: RF Output Power LTE 5G NR NOTE Mode Frequency Max. Min. WCDMA WCDMA bands 24 dBm +1/-3 dB (Class 3) < -50 dBm LTE bands 23 dBm 2 dB (Class 3)

< -40 dBm LTE HPUE bands

(B38/B40/B41/B42/B43) 26 dBm 2 dB (Class 2)

< -40 dBm 5G NR bands 23 dBm 2 dB (Class 3) 5G NR HUPE bands

(n41/n77/n78) 26 dBm +2/-3 dB (Class 2)

< -40 dBm

(BW: 520 MHz)1)

< -40 dBm

(BW: 520 MHz)1) 1) For 5G NR TDD bands, the normative reference for this requirement is TS 38.101-1 [2] clause 6.3.1 6.7. RF Receiving Sensitivity The following tables show conducted RF receiving sensitivity of RM502Q-GL module. RM502Q-GL_Hardware_Design 67 / 77 Table 36: RM502Q-GL Conducted RF Receiving Sensitivity Mode Frequency Primary Diversity SIMO1) WCDMA B1 WCDMA B2 WCDMA B3 WCDMA B4 WCDMA B5 WCDMA B8 WCDMA WCDMA 5G Module Series RM502Q-GL Hardware Design TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 3GPP

(SIMO)

-106.7 dBm

-104.7 dBm

-103.7 dBm

-106.7 dBm

-104.7 dBm

-103.7 dBm

-104.7 dBm WCDMA B19 TBD TBD TBD LTE-FDD B1 (10 MHz) TBD TBD TBD

-96.3 dBm LTE-FDD B2 (10 MHz) TBD TBD TBD

-94.3 dBm LTE-FDD B3 (10 MHz) TBD TBD TBD

-93.3 dBm LTE-FDD B4 (10 MHz) TBD TBD TBD

-96.3 dBm LTE-FDD B5 (10 MHz) TBD TBD TBD

-94.3 dBm LTE-FDD B7 (10 MHz) TBD TBD TBD

-94.3 dBm LTE-FDD B8 (10 MHz) TBD TBD TBD

-93.3 dBm LTE-FDD B9 (10 MHz) TBD TBD TBD

-95.3 dBm LTE-FDD B12 (10 MHz) TBD TBD TBD

-93.3 dBm LTE-FDD B13 (10 MHz) TBD TBD TBD

-93.3 dBm LTE-FDD B14 (10 MHz) TBD TBD TBD

-93.3 dBm LTE-FDD B17 (10 MHz) TBD TBD TBD

-93.3 dBm LTE-FDD B18 (10 MHz) TBD TBD TBD

-96.3 dBm LTE-FDD B19 (10 MHz) TBD TBD TBD

-96.3 dBm LTE-FDD B20 (10 MHz) TBD TBD TBD

-93.3 dBm LTE RM502Q-GL_Hardware_Design 68 / 77 LTE 5G NR 5G Module Series RM502Q-GL Hardware Design LTE-FDD B25 (10 MHz) TBD TBD TBD

-92.8 dBm LTE-FDD B26 (10 MHz) TBD TBD TBD

-93.8 dBm LTE-FDD B28 (10 MHz) TBD TBD TBD

-94.8 dBm LTE-FDD B30 (10 MHz) TBD TBD TBD

-95.3 dBm LTE-FDD B32 (10 MHz) TBD TBD TBD

-95.3 dBm LTE-TDD B34 (10 MHz) TBD TBD TBD

-96.3 dBm LTE-TDD B38 (10 MHz) TBD TBD TBD

-96.3 dBm LTE-TDD B39 (10 MHz) TBD TBD TBD

-96.3 dBm LTE-TDD B40 (10 MHz) TBD TBD TBD

-96.3 dBm LTE-TDD B41 (10 MHz) TBD TBD TBD

-94.3 dBm LTE-TDD B42 (10 MHz) TBD TBD TBD

-95 dBm LTE-TDD B43 (10 MHz) TBD TBD TBD

-95 dBm LTE-TDD B48 (10 MHz) TBD TBD TBD

-95 dBm 5G NR-FDD n1 (20 MHz) (SCS: 15 kHz) TBD TBD TBD

-94.0 dBm 5G NR-FDD n2 (20 MHz) (SCS: 15 kHz) TBD TBD TBD

-92.0 dBm 5G NR-FDD n3 (20 MHz) (SCS: 15 kHz) TBD TBD TBD

-91.0 dBm 5G NR-FDD n5 (10 MHz) (SCS: 15 kHz) TBD TBD TBD

-95.0 dBm 5G NR-FDD n7 (20 MHz) (SCS: 15 kHz) TBD TBD TBD

-92.0 dBm 5G NR-FDD n8 (10 MHz) (SCS: 15 kHz) TBD TBD TBD

-94.0 dBm 5G NR-FDD n12 (10 MHz) (SCS: 15 kHz) TBD TBD TBD

-94.0 dBm 5G NR-FDD n20 (10 MHz) (SCS: 15 kHz) TBD TBD TBD

-94.0 dBm 5G NR-FDD n25 (20 MHz) (SCS: 15 kHz) TBD TBD TBD

-90.5 dBm 5G NR-FDD n28 (10 MHz) (SCS: 15 kHz) TBD TBD TBD

-96.0 dBm 5G NR-TDD n38 (20 MHz) (SCS: 30 kHz) TBD TBD TBD

-94.0 dBm 5G NR-TDD n40 (20 MHz) (SCS: 30 kHz) TBD TBD TBD

-94.0 dBm RM502Q-GL_Hardware_Design 69 / 77 5G Module Series RM502Q-GL Hardware Design 5G NR-TDD n41 (20 MHz) (SCS: 30 kHz) TBD TBD TBD

-92.0 dBm 5G NR-FDD n66 (20 MHz) (SCS: 15 kHz) TBD TBD TBD

-93.5 dBm 5G NR-FDD n71 (10 MHz) (SCS: 15 kHz) TBD TBD TBD

-94.0 dBm 5G NR-TDD n77 (20 MHz) (SCS: 30 kHz) TBD TBD TBD

-92.9 dBm 5G NR-TDD n78 (20 MHz) (SCS: 30 kHz) TBD TBD TBD

-92.9 dBm NOTE 1) SIMO is a smart antenna technology that uses a single antenna at the transmitter side and two antennas at the receiver side, which improves Rx performance. 6.8. ESD Characteristics The module is not protected against electrostatic discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. The following table shows the module electrostatic discharge characteristics. Table 37: Electrostatic Discharge Characteristics (Temperature: 25C, Humidity: 40%) Tested Interfaces Contact Discharge Air Discharge Unit VCC, GND Antenna Interfaces 5 4 Other Interfaces 0.5 10 8 1 kV kV kV 6.9. Thermal Dissipation RM502Q-GL is designed to work over an extended temperature range. In order to achieve a maximum performance while working under extended temperatures or extreme conditions (such as with maximum power or data rate) for a long time, it is strongly recommended to add a thermal pad or other thermally RM502Q-GL_Hardware_Design 70 / 77 5G Module Series RM502Q-GL Hardware Design conductive compounds between the module and the main PCB for thermal dissipation. The thermal dissipation area (i.e. the area for adding thermal pad) is shown as below. The dimensions are measured in mm. Figure 40: Thermal Dissipation Area on Bottom Side of Module (Bottom View) There are other measures to enhance heat dissipation performance:

Add ground vias as many as possible on PCB. Maximize airflow over/around the module. Place the module away from other heating sources. Module mounting holes must be used to attach (ground) the device to the main PCB ground. It is NOT recommended to apply solder mask on the main PCB where the modules thermal dissipation area is located. Select an appropriate material, thickness and surface for the outer housing (i.e. the mechanical enclosure) of the application device that integrates the module so that it provides good thermal dissipation. Customers may also need active cooling to pull heat away from the module. If possible, add a heatsink on the top of the module. A thermal pad should be used between the heatsink and the module, and the heatsink should be designed with as many fins as possible to increase heat dissipation area. RM502Q-GL_Hardware_Design 71 / 77 5G Module Series RM502Q-GL Hardware Design NOTE For more detailed guidelines on thermal design, please refer to document [5]. RM502Q-GL_Hardware_Design 72 / 77 5G Module Series RM502Q-GL Hardware Design 7 Mechanical Dimensions and Packaging This chapter mainly describes mechanical dimensions and packaging specifications of RM502Q-GL module. All dimensions are measured in mm, and the tolerances are 0.05 mm unless otherwise specified. 7.1. Mechanical Dimensions of the Module Figure 41: Mechanical Dimensions of RM502Q-GL (Unit: mm) RM502Q-GL_Hardware_Design 73 / 77 5G Module Series RM502Q-GL Hardware Design 7.2. Top and Bottom Views of the Module Top View Bottom View Figure 42: Top and Bottom Views of the Module NOTE These are rendering images of RM502Q-GL module. For authentic appearance, please refer to the module that you receive from Quectel. 7.3. M.2 Connector RM502Q-GL adopts a standard PCI Express M.2 connector which compiles with the directives and standards listed in document [4]. RM502Q-GL_Hardware_Design 74 / 77 5G Module Series RM502Q-GL Hardware Design 7.4. Packaging RM502Q-GL modules are packaged in trays. The following figure shows the tray size. Figure 43: Tray Size (Unit: mm) Each tray contains 10 modules. The smallest package contains 100 modules. Tray packaging procedures are as below. 1. Use 10 trays to package 100 modules at a time (tray size: 247 mm 172 mm). 2. Place an empty tray on the top of the 10-tray stack. 3. Fix the stack with masking tape in # shape as shown in the following figure. 4. Pack the stack with conductive bag, and then fix the bag with masking tape. 5. Place the list of IMEI No. into a small carton. 6. Seal the carton and then label the seal with sealing sticker (small carton size: 250 mm 175 mm 128 mm). Figure 44: Tray Packaging Procedure RM502Q-GL_Hardware_Design 75 / 77 5G Module Series RM502Q-GL Hardware Design 8 Appendix References Table 38: Related Documents SN. Document Name Remark

[1]

Quectel_PCIe_Card_EVB_User_Guide PCIe card EVB user guide

[2]

Quectel_RG500Q&RM502Q&RM510Q_AT_Commands_ Manual AT commands manual for RG500Q, RM502Q and RM510Q

[3]

Quectel_RM502Q_GNSS_Application_Note RM502Q GNSS application note

[4]

Quectel_RF_Layout_Application_Note RF layout application note

[5]

Quectel_RM502Q_Module_Thermal_Simulation RM502Q module thermal simulation

[6]

PCI Express M.2 Specification Rev3.0 PCI express M.2 specification Table 39: Terms and Abbreviations Abbreviation Description Bit Per Second Challenge Handshake Authentication Protocol DC-HSPA+

Dual-carrier High Speed Packet Access+

DFOTA Delta Firmware Upgrade Over-The-Air Downlink Dynamic Power Reduction Equivalent Isotropically Radiated Power Electrostatic Discharge Frequency Division Duplexing bps CHAP DL DPR EIRP ESD FDD RM502Q-GL_Hardware_Design 76 / 77 GLONASS Global Navigation Satellite System (Russia) 5G Module Series RM502Q-GL Hardware Design GNSS GPS GSM HR HSPA HSUPA kbps LAA LED LTE Mbps ME MIMO MLCC MMS MO MT PAP PCB PCIe PCM PDU PME PPP Global Navigation Satellite System Global Positioning System Global System for Mobile Communications Half Rate High Speed Packet Access High Speed Uplink Packet Access Kilo Bits Per Second License Assisted Access Light Emitting Diode Long Term Evolution Mega Bits Per Second Mobile Equipment Multiple-Input Multiple-Output Multiplayer Ceramic Chip Capacitor Multimedia Messaging Service Mobile Originated Mobile Terminated Password Authentication Protocol Printed Circuit Board Peripheral Component Interconnect Express Pulse Code Modulation Protocol Data Unit Power Management Event Point-to-Point Protocol RM502Q-GL_Hardware_Design 77 / 77 5G Module Series RM502Q-GL Hardware Design Universal Asynchronous Receiver & Transmitter

(U)SIM

(Universal) Subscriber Identity Module RF Rx SAR SMS Tx UART UL URC USB VIH VIL VOH VOL Radio Frequency Receive Specific Absorption Rate Short Message Service Transmit Uplink Unsolicited Result Code Universal Serial Bus Input High Voltage Level Input Low Voltage Level Output High Voltage Level Output Low Voltage Level WCDMA Wideband Code Division Multiple Access Installation engineers need to be aware of the potential risk of the thermal effects of radio frequency energy and how to stay protected against undue risk. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the user's body and must not transmit simultaneously with any other antenna or transmitter. RM502Q-GL_Hardware_Design 78 / 77 OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.31 (h) and (k): The host manufacturer is responsible for additional testing to verify compliance as a composite system. When testing the host device for compliance with Part 15 Subpart B, the host manufacturer is required to show compliance with Part 15 Subpart B while the transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation should confirm that the module's intentional emissions are compliant (i.e. fundamental and out of band emissions). The host manufacturer must verify that there are no additional unintentional emissions other than what is permitted in Part 15 Subpart B or emissions are complaint with the transmitter(s) rule(s). The Grantee will provide guidance to the host manufacturer for Part 15 B requirements if needed. Important Note notice that any deviation(s) from the defined parameters of the antenna trace, as described by the instructions, require that the host product manufacturer must notify to Quectel that they wish to change the antenna trace design. In this case, a Class II permissive change application is required to be filed by the USI, or the host manufacturer can take responsibility through the change in FCC ID (new application) procedure followed by a Class II permissive change application End Product Labeling When the module is installed in the host device, the FCC/IC ID label must be visible through a window on the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a second label must be placed on the outside of the final device that contains the following text: Contains FCC ID: XMR2021RM502QGL Contains IC: 10224A-2020RM502Q. The FCC ID/IC ID can be used only when all FCC/IC compliance requirements are met. Antenna authorization.

(1) The antenna must be installed such that 20 cm is maintained between the antenna and users,

(2) The transmitter module may not be co-located with any other transmitter or antenna. In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC/IC To comply with FCC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed Test Mode Antenna Gain (dBi) Test Mode Antenna Gain (dBi) WCDMA B2 WCDMA B4 WCDMA B5 LTE B2 LTE B4 LTE B5 LTE B7 LTE B12 LTE B13 LTE B14 LTE B17 LTE B25 LTE B26 LTE B30 8.00 5.00 5.00 8.00 5.00 5.00 8.00 5.00 5.00 5.00 5.00 8.00 5.00

-1.02 LTE B38 LTE B41 LTE B48 LTE B66 LTE B71 n2 n5 n7 n12 n25 n41 n66 n71 n77 2.00 2.00

-2.00 5.00 5.00 8.00 5.00 8.00 5.00 8.00 5.00 5.00 5.00 5.00 Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:

- Reorient or relocate the receiving antenna.

- Increase the separation between the equipment and receiver

- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

- Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. List of applicable FCC rules This module has been tested and found to comply with part 22, part 24, part 27, part 90, part 96 requirements for Modular Approval. The modular transmitter is only FCC authorized for the specific rule parts (i.e., FCC transmitter rules) listed on the grant, and that the host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. If the grantee markets their product as being Part 15 Subpart B compliant (when it also contains unintentional-

radiator digital circuity), then the grantee shall provide a notice stating that the final host product still requires Part 15 Subpart B compliance testing with the modular transmitter installed. This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. Radiation Exposure Statement your body. This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator &

Industry Canada Statement This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following

(1) This device may not cause interference; and

(2) This device must accept any interference, including interference that may cause undesired operation two conditions:

of the device. Le prsent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorise aux deux conditions suivantes:

(1) l'appareil ne doit pas produire de brouillage, et

(2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement."

Radiation Exposure Statement body Dclaration d'exposition aux radiations:

This equipment complies with IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator & your Cet quipement est conforme aux limites d'exposition aux rayonnements ISED tablies pour un environnement non contrl. Cet quipement doit tre install et utilis avec un minimum de 20 cm de distance entre la source de rayonnement et votre corps. This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. Cet appareil est conu uniquement pour les intgrateurs OEM dans les conditions suivantes: (Pour utilisation de dispositif module) 1) L'antenne doit tre installe de telle sorte qu'une distance de 20 cm est respecte entre l'antenne et les utilisateurs, et 2) Le module metteur peut ne pas tre complant avec un autre metteur ou antenne. Tant que les 2 conditions ci-dessus sont remplies, des essais supplmentaires sur l'metteur ne seront pas ncessaires. Toutefois, l'intgrateur OEM est toujours responsable des essais sur son produit final pour toutes exigences de conformit supplmentaires requis pour ce module install. IMPORTANT NOTE:

In the event that these conditions cannot be met (for example certain laptop configurations or colocation with another transmitter), then the Canada authorization is no longer considered valid and the IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate Canada authorization. NOTE IMPORTANTE:

Dans le cas o ces conditions ne peuvent tre satisfaites (par exemple pour certaines configurations d'ordinateur portable ou de certaines co-localisation avec un autre metteur), l'autorisation du Canada n'est plus considr comme valide et l'ID IC ne peut pas tre utilis sur le produit final. Dans ces circonstances, l'intgrateur OEM sera charg de rvaluer le produit final (y compris l'metteur) et l'obtention d'une autorisation distincte au Canada. End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed such that 20 cm may be maintained between the antenna and users. The final end product must be labeled in a visible area with the following: Contains IC: 10224A-2020RM502Q. Plaque signaltique du produit final Ce module metteur est autoris uniquement pour une utilisation dans un dispositif o l'antenne peut tre installe de telle sorte qu'une distance de 20cm peut tre maintenue entre l'antenne et les utilisateurs. Le produit final doit tre tiquet dans un endroit visible avec l'inscription suivante: "Contient des IC: 10224A-2020RM502Q". Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. Manuel d'information l'utilisateur final L'intgrateur OEM doit tre conscient de ne pas fournir des informations l'utilisateur final quant la faon d'installer ou de supprimer ce module RF dans le manuel de l'utilisateur du produit final qui intgre ce module. Le manuel de l'utilisateur final doit inclure toutes les informations rglementaires requises et avertissements comme indiqu dans ce manuel.

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