FCC ID: XMR2020RM510QGL 5G Sub-6 GHz & mmWave M.2 Module

 

RM510Q-GL Hardware Design 5G Module Series Version: 1.0 Date: 2021-02-07 Status: Released www.quectel.com 5G Module Series RM510Q-GL Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters:

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit:

http://www.quectel.com/support/sales.htm. For technical support, or to report documentation errors, please visit:

http://www.quectel.com/support/technical.htm Or email to support@quectel.com. General Notes Quectel offers the information as a service to its customers. The information provided is based upon customers requirements. Quectel makes every effort to ensure the quality of the information it makes available. Quectel does not make any warranty as to the information contained herein, and does not accept any liability for any injury, loss or damage of any kind incurred by use of or reliance upon the information. All information supplied herein is subject to change without prior notice. Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors, it is possible that these functions and features could contain errors, inaccuracies and omissions. Unless otherwise provided by valid agreement, Quectel makes no warranties of any kind, implied or express, with respect to the use of features and functions under development. To the maximum extent permitted by law, Quectel excludes all liability for any loss or damage suffered in connection with the use of the functions and features under development, regardless of whether such loss or damage may have been foreseeable. Duty of Confidentiality The Receiving Party shall keep confidential all documentation and information provided by Quectel, except when the specific permission has been granted by Quectel. The Receiving Party shall not access or use Quectels documentation and information for any purpose except as expressly provided herein. Furthermore, the Receiving Party shall not disclose any of the Quectel's documentation and information to any third party without the prior written consent by Quectel. For any noncompliance to the above requirements, unauthorized use, or other illegal or malicious use of the documentation and information, Quectel will reserve the right to take legal action. RM510Q-GL_Hardware_Design 1 / 88 5G Module Series RM510Q-GL Hardware Design Copyright The information contained here is proprietary technical information of Quectel wireless solutions co., ltd. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design. Copyright Quectel Wireless Solutions Co., Ltd. 2021. All rights reserved. RM510Q-GL_Hardware_Design 2 / 88 5G Module Series RM510Q-GL Hardware Design Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be paid to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions, such as when the mobile bill is unpaid or the (U)SIM card is invalid. When emergency help is needed in such conditions, use emergency call if the device supports it. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. In an emergency, the device with emergency call function cannot be used as the only contact method considering network connection cannot be guaranteed under all circumstances. The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV set, radio, computer or other electric equipment. In locations with potentially explosive atmospheres, obey all posted signs to turn off wireless devices such as mobile phone or other cellular terminals. Areas with potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, areas where the air contains chemicals or particles such as grain, dust or metal powders. RM510Q-GL_Hardware_Design 3 / 88 5G Module Series RM510Q-GL Hardware Design About the Document Revision History Version Date Author Description

2020-10-22 1.0 2021-02-07 Kingson ZHANG

/Jumping HE Kingson ZHANG

/Jumping HE Creation of the document First official release RM510Q-GL_Hardware_Design 4 / 88 5G Module Series RM510Q-GL Hardware Design Contents Safety Information ....................................................................................................................................... 3 About the Document ................................................................................................................................... 4 Contents ....................................................................................................................................................... 5 Table Index ................................................................................................................................................... 8 Figure Index ............................................................................................................................................... 10 1 Introduction ........................................................................................................................................ 12 1.1. Introduction ............................................................................................................................... 12 1.2. Reference Standard .................................................................................................................. 12 1.3. Special Mark ............................................................................................................................. 13 2 Product Concept ................................................................................................................................ 14 2.1. General Description .................................................................................................................. 14 2.2. Key Features ............................................................................................................................. 15 2.3. Evaluation Board ....................................................................................................................... 18 2.4. Functional Diagram ................................................................................................................... 18 2.5. Pin Assignment ......................................................................................................................... 19 2.6. Pin Description .......................................................................................................................... 20 3 Operating Characteristics ................................................................................................................. 25 3.1. Operating Modes ....................................................................................................................... 25 3.1.1. Sleep Mode .................................................................................................................... 25 3.1.2. Airplane Mode ................................................................................................................ 27 3.2. Communication Interface with Host .......................................................................................... 27 3.3. Power Supply ............................................................................................................................ 28 3.3.1. Decrease Voltage Drop .................................................................................................. 28 3.3.2. Reference Design for Power Supply .............................................................................. 29 3.3.3. Monitor the Power Supply .............................................................................................. 30 3.4. Turn on ...................................................................................................................................... 30 Turn on the Module ........................................................................................................ 30 3.5. Turn off ...................................................................................................................................... 32 Turn off the Module through FULL_CARD_POWER_OFF# ......................................... 32 Turn off the Module through AT Command and FULL_CARD_POWER_OFF# ........... 32 3.6. Reset ......................................................................................................................................... 33 3.5.1. 3.5.2. 3.4.1. 4.1. 4 Application Interfaces ....................................................................................................................... 36

(U)SIM Interface ........................................................................................................................ 36 4.1.1. Pin Definition of (U)SIM.................................................................................................. 36 4.1.2. Hot-plug of (U)SIM ......................................................................................................... 37 4.1.3. Normally Closed (U)SIM Card Connector...................................................................... 38 4.1.4. Normally Open (U)SIM Card Connector ........................................................................ 38 RM510Q-GL_Hardware_Design 5 / 88 5G Module Series RM510Q-GL Hardware Design 4.1.5. Without Hot-plug (U)SIM Card Connector ..................................................................... 39

(U)SIM Design Notices................................................................................................... 39 4.1.6. 4.2. USB Interface ............................................................................................................................ 40 4.3. PCIe Interface ........................................................................................................................... 42 4.3.1. PCIe Operating Mode .................................................................................................... 42 4.3.2. Pin Definition of PCIe ..................................................................................................... 42 4.3.3. Reference Design of PCIe ............................................................................................. 43 4.3.4. PCIe Timing .................................................................................................................... 44 PCM Interface ........................................................................................................................... 45 4.4. 45 4.5. Control and Indication Interfaces .............................................................................................. 47 4.5.1. W_DISABLE1# ............................................................................................................... 47 4.5.2. W_DISABLE2# ............................................................................................................... 48 4.5.3. WWAN_LED#................................................................................................................. 49 4.5.4. WAKE_ON_WAN# ......................................................................................................... 50 4.5.5. DPR* .............................................................................................................................. 50 4.5.6. STATUS ......................................................................................................................... 51 4.6. Cellular/WLAN Coexistence Interface* ..................................................................................... 51 4.7. Antenna Tuner Control Interface* ............................................................................................. 52 4.8. Configuration Pins ..................................................................................................................... 52 5 RF Characteristics ............................................................................................................................. 54 5.1. mmWave IF Interfaces .............................................................................................................. 54 5.1.1. Assignment and Definition of mmWave IF Interfaces ................................................... 54 5.1.2. Characteristics of mmWave IF Interfaces ...................................................................... 55 VSWR Requirements of mmWave IF Interfaces ................................................ 55 5.1.2.1. Insertion Loss Requirements of mmWave IF Interfaces..................................... 55 5.1.2.2. 5.1.2.3. IF Isolation ........................................................................................................... 56 5.1.2.4. mmWave and Sub-6 GHz Antennas Coexistence .............................................. 56 5.1.3. mmWave IF Port Mapping ............................................................................................. 56 IF Connector................................................................................................................... 57 5.1.4. 5.2. Cellular Antenna Interfaces....................................................................................................... 58 5.2.1. Pin Definition .................................................................................................................. 58 5.2.2. Port Mapping .................................................................................................................. 58 5.2.3. Operating Frequency ..................................................................................................... 59 5.2.4. Sensitivity ....................................................................................................................... 61 5.2.5. Output Power ................................................................................................................. 63 5.3. GNSS Antenna Interface .......................................................................................................... 64 5.3.1. General Description ....................................................................................................... 64 5.3.2. GNSS Frequency ........................................................................................................... 64 5.3.3. GNSS Performance ....................................................................................................... 65 5.4. Antenna Connectors ................................................................................................................. 66 5.4.1. Antenna Connector Location ......................................................................................... 66 5.4.2. Antenna Connector Size ................................................................................................ 66 5.4.3. Antenna Connector Installation ...................................................................................... 67 RM510Q-GL_Hardware_Design 6 / 88 5G Module Series RM510Q-GL Hardware Design 5.4.4.1. 5.4.4.2. 5.4.4. Recommended RF Connector for Installation ............................................................... 69 Assemble Coaxial Cable Plug Manually ............................................................. 69 Assemble Coaxial Cable Plug with Jig ............................................................... 70 5.4.5. Recommended Manufacturers of RF Connector and Cable ......................................... 71 5.5. Antenna Requirements ............................................................................................................. 71 6 Electrical Characteristics and Reliability ...................................................................................... 73 6.1. Power Supply Requirements .................................................................................................... 73 6.2. Current Consumption ................................................................................................................ 73 6.3. Digital I/O Characteristic ........................................................................................................... 78 6.4. Electrostatic Discharge ............................................................................................................. 79 6.5. Thermal Dissipation .................................................................................................................. 79 6.6. Absolute Maximum Ratings ...................................................................................................... 81 6.7. Operating and Storage Temperatures ...................................................................................... 81 7 Mechanical Dimensions and Packaging ......................................................................................... 83 7.1. Mechanical Dimensions of the Module ..................................................................................... 83 7.2. Top and Bottom Views of the Module ....................................................................................... 84 7.3. M.2 Connector ........................................................................................................................... 84 7.4. Packaging ................................................................................................................................. 84 8 Appendix References ........................................................................................................................ 86 RM510Q-GL_Hardware_Design 7 / 88 5G Module Series RM510Q-GL Hardware Design Table Index Table 1: Special Mark................................................................................................................................. 13 Table 1: Frequency Bands and GNSS Type of RM510Q-GL Module ....................................................... 14 Table 2: Key Features of RM510Q-GL ...................................................................................................... 15 Table 3: Definition of I/O Parameters ......................................................................................................... 20 Table 4: Pin Description ............................................................................................................................. 20 Table 5: Overview of Operating Modes ..................................................................................................... 25 Table 6: Definition of VCC and GND Pins ................................................................................................. 28 Table 7: Definition of FULL_CARD_POWER_OFF# ................................................................................. 30 Table 8: Turn-on Time of the Module ......................................................................................................... 31 Table 9: Turn-off Time through FCPO# ..................................................................................................... 32 Table 10: Turn-off Time through AT Command and FULL_CARD_POWER_OFF# ................................ 33 Table 11: Definition of RESET# Pin ........................................................................................................... 33 Table 12: Resetting Time through RESET# .............................................................................................. 35 Table 13: Pin Definition of (U)SIM Interface .............................................................................................. 36 Table 14: Pin Definition of USB Interface .................................................................................................. 40 Table 15: Pin Definition of PCIe Interface .................................................................................................. 43 Table 16: PCIe Power-up Timing of M.2 Specification .............................................................................. 44 Table 17: PCIe Power-up Timing of Module .............................................................................................. 45 Table 18: Pin Definition of PCM Interface .................................................................................................. 45 Table 19: Pin Definition of Control and Indication Interfaces..................................................................... 47 Table 20: RF Function Status .................................................................................................................... 48 Table 21: GNSS Function Status ............................................................................................................... 48 Table 22: Network Status Indications of WWAN_LED# ............................................................................ 49 Table 23: State of the WAKE_ON_WAN# ................................................................................................. 50 Table 24: Function of the DPR Signal ........................................................................................................ 51 Table 25: Pin Definition of Coexistence Interface ...................................................................................... 51 Table 26: Pin Definition of Antenna Tuner Control Interface ..................................................................... 52 Table 27: Configuration Pins List of M.2 Specification .............................................................................. 52 Table 28: Definition of Configuration Pins.................................................................................................. 52 Table 29: Definition of mmWave IF Interfaces ........................................................................................... 55 Table 30: VSWR Requirements of mmWave IF Interfaces ....................................................................... 55 Table 31: Insertion Loss Requirements of mmWave IF Interfaces ........................................................... 55 Table 32: Isolation Requirements between IF cable to Sub-6 GHz Antennas .......................................... 56 Table 33: mmWave IF Port Mapping ......................................................................................................... 56 Table 34: RM510Q-GL Pin Definition of Antenna Interfaces ..................................................................... 58 Table 35: Antenna Mapping ....................................................................................................................... 58 Table 36: RM510Q-GL Module Operating Frequency ............................................................................... 59 Table 37: RM510Q-GL Conducted Receiving Sensitivity .......................................................................... 61 Table 38: Cellular Output Power ................................................................................................................ 63 Table 39: GNSS Frequency ....................................................................................................................... 64 Table 40: GNSS Performance ................................................................................................................... 65 RM510Q-GL_Hardware_Design 8 / 88 5G Module Series RM510Q-GL Hardware Design Table 41: Major Specifications of the RF Connector ................................................................................. 67 Table 42: Cellular Bands Supported by RM510Q-GL Antenna Connectors ............................................. 71 Table 43: Antenna Requirements .............................................................................................................. 71 Table 44: Power Supply Requirements ..................................................................................................... 73 Table 45: RM510Q-GL Current Consumption ........................................................................................... 73 Table 46: Logic Levels of Digital I/O (1.8 V) .............................................................................................. 78 Table 47: (U)SIM 1.8 V I/O Requirements ................................................................................................. 78 Table 48: (U)SIM 3.0 V I/O Requirements ................................................................................................. 79 Table 49: Electrostatic Discharge Characteristics (Temperature: 25 C, Humidity: 40 %) ....................... 79 Table 50: Absolute Maximum Ratings ....................................................................................................... 81 Table 51: Operating and Storage Temperatures ....................................................................................... 81 Table 52: Related Documents .................................................................................................................... 86 Table 53: Terms and Abbreviations ........................................................................................................... 86 RM510Q-GL_Hardware_Design 9 / 88 5G Module Series RM510Q-GL Hardware Design Figure Index Figure 1: Functional Diagram ..................................................................................................................... 18 Figure 2: Pin Assignment ........................................................................................................................... 19 Figure 3: DRX Run Time and Current Consumption in Sleep Mode ......................................................... 26 Figure 4: Sleep Mode Application with USB Remote Wakeup .................................................................. 26 Figure 5: Power Supply Limits during Radio Transmission ....................................................................... 28 Figure 6: Reference Circuit of VCC ........................................................................................................... 29 Figure 7: Reference Circuit of Power Supply ............................................................................................. 29 Figure 8: Turn on the Module with a Host GPIO ........................................................................................ 31 Figure 9: Turn-on Timing through FULL_CARD_POWER_OFF# ............................................................. 31 Figure 10: Turn-off Timing through FULL_CARD_POWER_OFF# ........................................................... 32 Figure 11: Turn-off Timing through AT Command and FULL_CARD_POWER_OFF# ............................ 33 Figure 12: Reference Circuit of RESET# with NPN Driving Circuit ........................................................... 34 Figure 13: Reference Circuit of RESET# with a Button ............................................................................. 34 Figure 14: Resetting Timing through RESET# .......................................................................................... 35 Figure 15: Reference Circuit for Normally Closed (U)SIM Card Connector .............................................. 38 Figure 16: Reference Circuit for Normally Open (U)SIM Card Connector ................................................ 39 Figure 17: Reference Circuit for a 6-Pin (U)SIM Card Connector ............................................................. 39 Figure 18: Reference Circuit of USB 3.1 & 2.0 Interface ........................................................................... 41 Figure 19: PCIe Interface Reference Circuit .............................................................................................. 43 Figure 20: PCIe Power-up Timing of M.2 Specification ............................................................................. 44 Figure 21: PCIe Power-up Timing of the Module ....................................................................................... 45 Figure 22: Primary Mode Timing ................................................................................................................ 46 Figure 23: Auxiliary Mode Timing .............................................................................................................. 46 Figure 24: W_DISABLE1# and W_DISABLE2# Reference Circuit ........................................................... 49 Figure 25: WWAN_LED# Reference Circuit .............................................................................................. 49 Figure 26: WAKE_ON_WAN# Signal Reference Circuit ........................................................................... 50 Figure 27: Recommended Circuit of Configuration Pins ........................................................................... 53 Figure 28: Assignment of mmWave IF Interfaces ...................................................................................... 54 Figure 29: Dimensions of IF Connectors ................................................................................................... 57 Figure 30: RM510Q-GL Antenna Connectors ........................................................................................... 66 Figure 31: RF Connector Dimensions (Unit: mm) ...................................................................................... 67 Figure 32: Specifications of Mating Plugs Using 0.81 mm Coaxial Cables ............................................ 68 Figure 33: Connection between RF Connector and Mating Plug Using 0.81 mm Coaxial Cable .......... 68 Figure 34: Connection between RF Connector and Mating Plug Using 1.13 mm Coaxial Cable .......... 69 Figure 35Plug in A Coaxial Cable Plug .................................................................................................. 69 Figure 36Pull out Coaxial Cable Plug..................................................................................................... 70 Figure 37Install the Coaxial Cable Plug with Jig .................................................................................... 70 Figure 38: Thermal Dissipation Area on Bottom Side of Module .............................................................. 80 Figure 39: Mechanical Dimensions of the Module (Unit: mm) ................................................................... 83 Figure 40: RM510Q-GL Top View and Bottom View ................................................................................. 84 Figure 41: Tray Size (Unit: mm) ................................................................................................................. 85 RM510Q-GL_Hardware_Design 10 / 88 Figure 42: Tray Packaging Procedure ....................................................................................................... 85 5G Module Series RM510Q-GL Hardware Design RM510Q-GL_Hardware_Design 11 / 88 5G Module Series RM510Q-GL Hardware Design 1 Introduction 1.1. Introduction The hardware design defines RM510Q-GL and describes the air and hardware interfaces which are connected with customers applications. This document helps you quickly understand the interface specifications, electrical and mechanical details, as well as other related information of RM510Q-GL. To facilitate its application in different fields, reference design is also provided for reference. Associated with application notes and user guides, customers can use the module to design and set up mobile applications easily. 1.2. Reference Standard The module complies with the following standards:

PCI Express M.2 Specification Revision 3.0, Version 1.2 PCI Express Base Specification Revision 3.0 Universal Serial Bus Specification, Revision 3.1 MIPI Alliance Specification for RF Front-End Control Interface Version 2.0 3GPP TS 27.007 and 27.005 ISO/IEC 7816-3 RM510Q-GL_Hardware_Design 12 / 88 5G Module Series RM510Q-GL Hardware Design 1.3. Special Mark Table 1: Special Mark Mark Definition

When an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin name, AT command, or argument is under development and currently not supported, unless otherwise specified. Brackets ([]) used after a pin enclosing a range of numbers indicate all pin of the same type. For example, ANTCTL [0:3] refers to all four ANTCTL pins, ANTCTL0, ANTCTL1, ANTCTL2, and ANTCTL3. RM510Q-GL_Hardware_Design 13 / 88 5G Module Series RM510Q-GL Hardware Design 2 Product Concept 2.1. General Description RM510Q-GL is a 5G NR/LTE-FDD/LTE-TDD/WCDMA wireless communication module with receive diversity. It provides data connectivity on 5G NR SA and NSA, LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA and WCDMA networks. It is a standard M.2 Key-B WWAN module. For more details, see PCI Express M.2 Specification Revision 3.0, Version 1.2. RM510Q-GL is an industrial-grade module for industrial and commercial applications only. It supports embedded operating systems such as Windows, Linux and Android, and also provide GNSS and voice functionality to meet specific application demands. The following table shows the frequency bands and GNSS type of the module. Table 2: Frequency Bands and GNSS Type of RM510Q-GL Module Mode RM510Q-GL 5G NR SA n1/n2/n3/n5/n7/n8/n12/n20/n25/n28/n38/n40/n41/n48*/n66/n71/n77/n78/n79/

n257 1)/n258 1)/n260 1)/n261 1) 5G NR NSA n1/n2/n3/n5/n7/n8/n12/n20/n25/n28/n38/n40/n41/n48*/n66/n71/n77/n78/n79 LTE-FDD B1/B2/B3/B4/B5/B7/B8/B12(B17)/B13/B14/B18/B19/B20/B25/B26/B28/B29 2)/B30/

B32 2)/B66/B71 LTE-TDD B34/B38/B39/B40/B41/B42/B43/B48 LAA B46 2) WCDMA B1/B2/B3/B4/B5/B6/B8/B19 GNSS GPS/GLONASS/QZSS/BeiDou(Campass)/Galileo RM510Q-GL_Hardware_Design 14 / 88 NOTES 1. 2. 1) These bands work with mmWave antennas, 2) These bands receiving only. support 5G Module Series RM510Q-GL Hardware Design and they support NSA only. 3: This module supports mmWave Bands, and marketing without active mmWave antenna. We will provide software to host manufacturers when they use an active mmWave antenna with this module, this software will control the module work with active mmWave antenna. The host manufacturer can't use the active mmWave antenna directly. The Host Manufacturer will execute the mmWave bands' certification. The module can be applied to the following fields:

tablet PC and laptop computer Rugged Remote monitor system Smart metering system Wireless CPE Smart TV Outdoor live devices Wireless router and switch Other wireless terminal devices 2.2. Key Features The following table describes key features of RM510Q-GL. Table 3: Key Features of RM510Q-GL Feature Details Function Interface PCI Express M.2 Interface Power Supply Supply voltage: 3.1354.4 V Typical supply voltage: 3.7 V

(U)SIM Interface Compliant with ISO/IEC 7816-3 Support (U)SIM card: Class B (3.0 V) and Class C(1.8 V) Support single (U)SIM slot USB Interface Compliant with USB 3.1 and 2.0 specifications, with maximum transmission rates up to 10 Gbps on USB 3.1 and 480 Mbps on USB 2.0. Used for AT command communication, data transmission, firmware upgrade, software debugging, GNSS NMEA sentence output and voice over USB. Supports USB serial drivers for: Windows 7/8/8.1/10, Linux 2.65.4, Android 4.x/5.x/6.x/7.x/8.x/9.x/10 PCIe Interface Complaint with PCIe Gen 3, support 8 Gbps per lane, PCIe 1. Used for AT command communication, data transmission, firmware upgrade, software debugging, GNSS NMEA sentence output RM510Q-GL_Hardware_Design 15 / 88 PCM Transmitting Power 5G NR Features LTE Features 5G Module Series RM510Q-GL Hardware Design Used for audio function with external codec Support 16-bit linear data format Support long and short frame synchronization Support master and slave modes, but must be the master in long frame synchronization Class 3 (24 dBm +1/-3 dB) for WCDMA bands Class 3 (23 dBm 2 dB) for LTE bands Class 3 (23 dBm 2 dB) for 5G NR bands Class 2 (26 dBm 2 dB) for LTE B38/B40/B41/B42/B43 bands HPUE 1) Class 2 (26 dBm +2/-3 dB) for 5G NR n41/n77/n78/n79 bands HPUE Class 1 for 5G NR FR2 n257/n258/n260/n261 with QTM527 Class 3 for 5G NR FR2 n257/n258/n260/n261 with QTM525 Supports 3GPP Rel-15 Supports Modulations:

Uplink: /2-BPSK, QPSK, 16QAM, 64QAM and 256QAM Downlink: QPSK, 16QAM, 64QAM and 256QAM Supports MIMO:

Uplink: 2 2 MIMO2) on n41 Downlink: 4 4 MIMO on n1/n2/n3/n7/25/n38/n40/n41/n48*/n66/n77/n78/n79 Uplink and downlink support 2 x 2 MIMO on FR2(mmWave) bands. Supports SCS 15 kHz 3) and 30 kHz 3) on sub6 bands. Supports SCS 120kHz on FR2(mmWave) bands. Supports QTM525(power class 3) and QTM527(power class 1). Supports SA4) and NSA4) operation modes on all the 5G band Supports Option 3x, 3a, 3 and Option 2 Max. transmission data rates 5):NSA: Max 5 Gbps(DL)/ 650 Mbps (UL) SA: Max 4.2 Gbps(DL)/ 450 Mbps (UL) Sub-6 NSA: Max 5 Gbps(DL)/ 650 Mbps (UL) mmWave NSA: Max 7.5 Gbps(DL)/ 2.9 Gbps (UL) Supports 3GPP Rel-15 Supports up to CA Cat 20 Supports modulations:

Uplink: QPSK, 16QAM and 64QAM and 256QAM*

Downlink: QPSK, 16QAM and 64QAM and 256QAM Supports 1.4/3/5/10/15/20 MHz RF bandwidth Supports downlink 4 4 MIMO on:

B1/B2/B3/B4/B7/B25/B30/B38/B39/B40/B41/B42/B43/B48/B66 Max. transmission data rates 5):

LTE: Max 2.0 Gbps (DL)/200 Mbps (UL) UMTS Features Supports 3GPP Rel-9 DC-HSDPA, HSPA +, HSDPA, HSUPA and WCDMA Supports QPSK, 16QAM and 64QAM modulation Max. transmission data rates 5):

DC-HSDPA: Max 42 Mbps (DL) RM510Q-GL_Hardware_Design 16 / 88 5G Module Series RM510Q-GL Hardware Design HSUPA: Max 5.76 Mbps (UL) WCDMA: Max 384 kbps (DL)/384 kbps (UL) Rx-diversity Supports 5G NR/LTE/WCDMA Rx-diversity GNSS Features Protocol: NMEA 0183 Data Update Rate: 1 Hz Antenna Interfaces ANT0, ANT1, ANT2, and ANT3_GNSSL1 AT Commands Compliant with 3GPP TS 27.007 and 3GPP TS 27.005 Quectel enhanced AT commands Internet Protocol Features Supports QMI/NTP* protocols Supports the protocols PAP and EIRP usually used for PPP connections Firmware Upgrade USB 2.0 interface, PCIe interface and DFOTA SMS Text and PDU modes Point-to-point MO and MT SMS cell broadcast SMS storage: ME by default Physical Characteristics M.2 Key-B Size: (30.0 0.15) mm (52.0 0.15) mm (2.3 0.2) mm Weight: approx. 9.1 g Temperature Range Operating temperature range: -30 ~ +70 C 6) Extended temperature range: -40 ~ +85 C 7) Storage temperature range: -40 to +90C RoHS All hardware components are fully compliant with EU RoHS directive NOTES 1. 2. 3. 4. 5. 6. 7. 1) HPUE is only for single carrier. 2) Uplink 2 2 MIMO is only supported in 5G SA mode. 3) 5G NR FDD bands only support 15 kHz SCS, and NR TDD bands only support 30 kHz SCS. 4) See document [1] for bandwidth supported by each frequency band in the NSA and SA modes. 5) The maximum rates are theoretical and the actual values refer to the network configuration. 6) To meet this operating temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module can meet 3GPP specifications. 7) To meet this extended temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module remains the ability to establish and maintain functions such as voice, SMS, emergency call, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may undergo a reduction in value, exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again. RM510Q-GL_Hardware_Design 17 / 88 5G Module Series RM510Q-GL Hardware Design 2.3. Evaluation Board To help you develop applications conveniently with the module, Quectel supplies an evaluation board

(5G-mmWave-EVB), a USB micro-B cable, a USB type-C cable, antennas and other peripherals to control or test the module. For more details, see document [2] & document [3]. 2.4. Functional Diagram The following figure shows a block diagram of RM510Q-GL. Power management Baseband LPDDR4X SDRAM + NAND Flash Radio frequency M.2 Key-B interface Figure 1: Functional Diagram RM510Q-GL_Hardware_Design 18 / 88 ANT0 ANT3_GNSSL1 ANT238.4MHz XOQlinkControlTxPRxDRx ANT1SPMIClock ICBB_CLK 19.2MHzRF_CLK 38.4MHzEBI1EBI232.768kHzPMICMCPNAND 4Gb x 8LPDDR4X 4Gb x 16BasebandSub-6 GHzTransceiverTx/Rx BlocksETmmWaveTransceiverQlinkControlIFV4IFH1IFH2IFV3IFV2IFH3IFV1IFH4(U)SIMUSB 2.0 & USB 3.1PCIe 3.0 1RFFEGPIOsWWAN_LED#WAKE_ON_WAN#W_DISABLE1#W_DISABLE2#PCI Express M.2 Key-B InterfaceRESET_NFULL_CARD_POWER_OFF#GNDVCC 5G Module Series RM510Q-GL Hardware Design 2.5. Pin Assignment The following figure shows the pin assignment of the module. The top side contains module and antenna connectors. Figure 2: Pin Assignment RM510Q-GL_Hardware_Design 19 / 88 PIN2PIN74BOTPIN1PIN75TOPPin NameNo.CONFIG_275GND73GND71CONFIG_169RESET#67RFFE_VIO_1V865ANTCTL263ANTCTL161LAA_TX_EN59GND57PCIE_REFCLK_P55PCIE_REFCLK_M53GND51PCIE_RX_P49PCIE_RX_M47GND45PCIE_TX_P43PCIE_TX_M41GND39USB_SS_RX_P37USB_SS_RX_M35GND33USB_SS_TX_P31USB_SS_TX_M29GND27DPR25WAKE_ON_WAN#23CONFIG_021NotchNotchNotchNotchGND11USB_DM9USB_DP7GND5GND3CONFIG_31PIN11PIN10No.Pin Name74VCC72VCC70VCC68AP2SDX_STATUS66USIM1_DET64COEX_TXD62COEX_RXD60WLAN_TX_EN58RFFE_DATA56RFFE_CLK54PCIE_WAKE_N52PCIE_CLKREQ_N50PCIE_RST_N48QTM_VDD_1V946QTM3_PON44QTM2_PON42QTM1_PON40QTM0_PON38SDX2AP_STATUS36USIM1_VDD34USIM1_DATA32USIM1_CLK30USIM1_RST28PCM_SYNC26W_DISABLE2#24PCM_DOUT22PCM_DIN20PCM_CLKNotchNotchNotchNotch10WWAN_LED#8W_DISABLE1#64VCC2VCCFULL_CARD_POWER_OFF#

5G Module Series RM510Q-GL Hardware Design 2.6. Pin Description Table 4: Definition of I/O Parameters Type Description AI AO AIO DI DO DIO OD PI PO PU PD Analog Input Analog Output Analog Input/Output Digital Input Digital Output Digital Input/Output Open Drain Power Input Power Output Pull Up Pull Down The following table shows the pin definition and description of the module. Table 5: Pin Description Pin No. 1 2 3 4 Pin Name I/O Description CONFIG_3 DO Not connected internally VCC GND VCC PI Power supply Ground PI Power supply DC Characteristic Comment Vmin = 3.135 V Vnom = 3.7 V Vmax = 4.4 V Vmin = 3.135 V Vnom = 3.7 V Vmax = 4.4 V RM510Q-GL_Hardware_Design 20 / 88 5G Module Series RM510Q-GL Hardware Design GND Ground FULL_CARD_ POWER_OFF#

DI, PD Turn on/off the module. High level: Turn on Low level: Turn off VIHmax = 4.4 V VIHmin = 1.19 V VILmax = 0.2 V Internally pulled down with a 100 k resistor. USB_DP AIO USB 2.0 differential data (+) W_DISABLE1#

DI, OD Airplane mode control. Active LOW. 1.8/3.3 V USB_DM AIO 10 WWAN_LED#

DO, OD USB 2.0 differential data (-) RF status indication LED Active LOW. Ground VCC Notch Notch Notch Notch Notch Notch Notch Notch 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 GND Notch Notch Notch Notch Notch Notch Notch Notch PCM_CLK DI, PD PCM data bit clock 1.8 V 21 CONFIG_0 DO Not connected internally 22 PCM_DIN DI, PD PCM data input 1.8 V 23 WAKE_ON_WAN# DO, OD Wake up the host. Active LOW 24 PCM_DOUT DO, PD PCM data output 1.8 V 25 DPR*

DI, PU 26 W_DISABLE2#

DI, OD Dynamic power reduction. High level by default. GNSS disable control. Active LOW 1.8 V 1.8/3.3 V RM510Q-GL_Hardware_Design 21 / 88 5G Module Series RM510Q-GL Hardware Design 27 28 GND Ground PCM_SYNC DI, PD PCM data frame sync 1.8 V 29 USB_SS_TX_M AO USB 3.1 super-speed transmit (-) 30 USIM1_RST DO, PD

(U)SIM1 card reset 31 USB_SS_TX_P AO USB 3.1 super-speed transmit (+) 32 USIM1_CLK DO, PD

(U)SIM1 clock 33 GND Ground 34 USIM1_DATA DIO, PU

(U)SIM1 card data USIM_VDD 1.8/3.0 V USIM_VDD 1.8/3.0 V USIM_VDD 1.8/3.0 V 35 USB_SS_RX_M AI 36 USIM1_VDD PO 37 USB_SS_RX_P AI USB 3.1 super-speed receive (-)

(U)SIM1 card power supply USIM_VDD 1.8/3.0 V USB 3.1 super-speed receive (+) 38 39 SDX2AP_STATUS DO, PD Status indication to AP 1.8 V GND Ground 40 QTM0_PON DO mmWave antenna control 0 1.8 V 41 PCIE_TX_M AO PCIe transmit (-) 42 QTM1_PON DO mmWave antenna control 1 1.8 V 43 PCIE_TX_P AO PCIe transmit (+) 44 QTM2_PON DO mmWave antenna control 2 1.8 V 45 GND Ground 46 QTM3_PON DO mmWave antenna control 3 1.8 V 47 PCIE_RX_M AI PCIe receive (-) 48 QTM_VDD_1V9 PO Power supply for mmWave antenna modules RM510Q-GL_Hardware_Design 22 / 88 5G Module Series RM510Q-GL Hardware Design 49 PCIE_RX_P AI PCIe receive (+) 50 PCIE_RST_N DI, OD 51 GND 52 PCIE_CLKREQ_N DO, OD PCIe reset. Active LOW Ground PCIe clock request. Active LOW 53 PCIE_REFCLK_M AI, AO PCIe reference clock (-) 54 PCIE_WAKE_N DO, OD 55 PCIE_REFCLK_P AI, AO PCIe wake up Active LOW PCIe reference clock

(+) 56 RFFE_CLK* 1) DO, PD Used for external MIPI IC control 1.8 V 57 GND Ground 58 RFFE_DATA* 1) DO, PD 59 LAA_TX_EN*

DO 60 WLAN_TX_EN*

DI Used for external MIPI IC control 1.8 V Notification from transceiver to WLAN when LTE transmitting Notification from WLAN to SDR while transmitting 1.8 V 1.8 V 61 ANTCTL1*

DO, PD Antenna GPIO control 1.8 V 62 COEX_RXD*

DI, PD LTE/WLAN coexistence receive data 1.8 V 63 ANTCTL2*

DO, PD Antenna GPIO control 1.8 V 64 COEX_TXD*

DO, PD 65 RFFE_VIO_1V8 1) PO 66 USIM1_DET DI; PD LTE/WLAN coexistence transmit data 1.8 V Power supply for antenna tuner

(U)SIM1 card hot-plug detect 1.8 V 1.8 V 67 RESET#

DI, PU Reset the module. Active LOW. VIHmax = 1.575 V VIHmin = 1.25 V VILmax = 0.45 V Internally pulled up to 1.5 V with a 100 k resistor 68 AP2SDX_STATUS DI, PD Status indication from AP 1.8 V 69 CONFIG_1 DO Connected to GND RM510Q-GL_Hardware_Design 23 / 88 5G Module Series RM510Q-GL Hardware Design internally 70 VCC PI Power supply 71 GND Ground 72 VCC PI Power supply 73 GND Ground 74 VCC PI Power supply 75 CONFIG_2 DO Not connected internally Vmin = 3.135 V Vnom = 3.7 V Vmax = 4.4 V Vmin = 3.135 V Vnom = 3.7 V Vmax = 4.4 V Vmin = 3.135 V Vnom = 3.7 V Vmax = 4.4 V NOTES 1) If the function is required, please contact us for more details. 1. 2. Keep all NC, reserved and unused pins unconnected. RM510Q-GL_Hardware_Design 24 / 88 5G Module Series RM510Q-GL Hardware Design 3 Operating Characteristics 3.1. Operating Modes The table below briefly summarizes the various operating modes to be mentioned in the following chapters. Table 6: Overview of Operating Modes Mode Details Normal Operation Idle Software is active. The module has registered on the network, and it is ready to send and receive data. Talk/Data The module is connected to network. In this mode, the power consumption is decided by network setting and data transfer rate. Minimum Functionality Mode AT+CFUN=0 command sets the module to a minimum functionality mode without removing the power supply. In this mode, both RF function and (U)SIM card are invalid. Airplane Mode AT+CFUN=4 command or driving W_DISABLE1# pin low will set the module to airplane mode. In this mode, the RF function is invalid. Sleep Mode In this mode, the current consumption of the module is reduced to the minimal level, while the module keeps receiving paging messages, SMS, voice calls and TCP/UDP data from the network. Power Down Mode In this mode, the power management unit shuts down the power supply. Software is inactive, the serial interfaces are inaccessible, and the operating voltage (connected to VCC) remains applied. 3.1.1. Sleep Mode DRX of module is able to reduce the current consumption to a minimum value during the sleep mode, and DRX cycle index values are broadcasted by the wireless network. The figure below shows the relationship between the DRX run time and the current consumption in sleep mode. The longer the DRX cycle is, the lower the current consumption will be. RM510Q-GL_Hardware_Design 25 / 88 5G Module Series RM510Q-GL Hardware Design Figure 3: DRX Run Time and Current Consumption in Sleep Mode The following section describes power saving procedure of module. If the host supports USB suspend/resume and remote wakeup function, the following two preconditions must be met to enable the module enter sleep mode. Execute AT+QSCLK=1 command to enable the sleep mode. The hosts USB bus, which is connected with the modules USB interface, has entered into suspend state. The following figure shows the connection between the module and the host. Figure 4: Sleep Mode Application with USB Remote Wakeup Sending data to module through USB will wake up the module. When module has a URC to report, the module will send remote wake-up signals via USB bus to wake up the host. RM510Q-GL_Hardware_Design 26 / 88 Current ConsumptionRun TimeDRX OFF ON OFF ON OFF ON OFF ON OFF USB InterfaceUSB InterfaceModuleHostGNDGND 5G Module Series RM510Q-GL Hardware Design 3.1.2. Airplane Mode The module provides a W_DISABLE1# pin to disable or enable airplane mode through hardware operation. See Chapter 4.5.1 for more details 3.2. Communication Interface with Host The module supports to communicate through both USB and PCIe interfaces, respectively referring to the USB mode and the PCIe mode as described below:

USB Mode Supports all USB 2.0/3.1 features Supports MBIM/QMI/QRTR/AT Communication can be switched to PCIe mode by AT command USB is the default communication interface between the module and the host. To use PCIe interface for the communication between a host, an AT command under USB mode can be used. For more details about the AT command, see document [4]. It is suggested that USB 2.0 interface be reserved for firmware upgrade. USB-AT-based PCIe Mode Supports MBIM/QMI/QRTR/AT Communication can be switched back to USB mode by AT command When the module works at the USB-AT-based (switched from USB mode by AT command) PCIe mode, it supports MBIM/QMI/QRTR/AT, and can be switched back to USB mode by AT command. But the firmware upgrade via PCIe interface is not supported, so USB 2.0 interface must be reserved for the firmware upgrade. eFuse-based PCIe Mode Supports MBIM/QMI/QRTR/AT Supports Non-X86 systems and X86 system (supports BIOS PCIe early initial) RM510Q-GL can also be reprogrammed to PCIe mode based on eFuse. If the communication is switched to PCIe mode by burnt eFuse, the communication cannot be switched back to USB mode. RM510Q-GL_Hardware_Design 27 / 88 5G Module Series RM510Q-GL Hardware Design 3.3. Power Supply The following table shows pin definition of VCC pins and ground pins. Table 7: Definition of VCC and GND Pins Pin Pin Name I/O Description DC Characteristics 2, 4, 70, 72, 74 VCC PI Power supply 3.1354.4 V 3.7 V typical DC supply 3, 5, 11, 27, 33, 39, 45, 51, 57, 71, 73 GND Ground 3.3.1. Decrease Voltage Drop The input power supply range of the module is from 3.135 V to 4.4 V. Please ensure that the input voltage will never drop below 3.135 V, otherwise the module will be powered off automatically. The voltage ripple of the input power supply should be less than 100 mV, and the voltage drop should be less than 165 mV. Figure 5: Power Supply Limits during Radio Transmission To decrease voltage drop, two 100 F with low ESR should be used, and some multi-layer ceramic chip capacitor (MLCC) array also should be used due to its ultra-low ESR. These capacitors should be close to VCC pins and the width of VCC trace should be no less than 2 mm. In principle, the longer the VCC trace is, the wider width it should be. In addition, to get a stable power source, it is recommended to use a zener diode with reverse zener voltage of 5.1 V and dissipation power of more than 0.5 W. RM510Q-GL_Hardware_Design 28 / 88 VCC 3.7 VBurst TransmissionVoltage Ripple < 100 mVVoltage Drop < 165 mVBurst Transmission 5G Module Series RM510Q-GL Hardware Design Figure 6: Reference Circuit of VCC 3.3.2. Reference Design for Power Supply Power design for the module is important, as the performance of the module largely depends on the power source. The power supply is capable of providing a sufficient current of at least 5.0 A. If the voltage drop between the input and output is not too high, it is suggested that an LDO is used to supply power for the module. If there is a big voltage difference between the input source and the desired output (VCC =

3.7 V Typ.), a buck DC-DC converter is preferred as the power supply. The following figure shows a reference design for +5.0 V input power source based on a DC-DC converter. The typical output of the power supply is about 3.7 V and the maximum load current is 5.0 A. Figure 7: Reference Circuit of Power Supply RM510Q-GL_Hardware_Design 29 / 88 ModuleET2, 4C2100 F3, 5, 11VCC (3.7 V Typ.)VCCGNDC1010 pFC833 pFC6100 nFC41 F+C1100 FD15.1 VVCCGNDC910 pFC733 pFC5100 nFC31 F+27, 33, 39, 45, 51, 57, 71, 7370, 72, 74PMUD1TVSPWR_INC8220 FC1110 pFC1033 pFC9100 nF+R1205kU1Q1NPNR847kR74.7kPWR_ENR4182kPWR_OUTL11.5 HVINVINVINENVSNSCOMPRT/CLKSSPHPHPHBOOTPWRGDGNDGNDAGNDVFBR5374k 1%R6100k 1%C6100 nFPWRGDEPR280.6kC710 nFR310kC410 nFC5NMVFBC2100 nFC333 pFC1470 F+

5G Module Series RM510Q-GL Hardware Design NOTE To avoid damages to the internal flash, please cut off power supply after the module is turned off by pulling down FULL_CARD_POWER_OFF# pin for more than 7 s, and DON'T cut off power supply directly when the module is working. 3.3.3. Monitor the Power Supply AT+CBC command can be used to monitor the voltage value of VCC. For more details, see document [4]

3.4. Turn on 3.4.1. Turn on the Module FULL_CARD_POWER_OFF# (FCPO#) is used to turn on/off the module. When the input signal is asserted high ( 1.19 V), the module will turn on. When the input signal is driven low signal ( 0.2 V) or tri-stated, the module will turn off. This input signal is 3.3 V tolerant and can be driven by either 1.8 V or 3.3 V GPIO. Also, it has internally pulled down with a 100 k resistor. Table 8: Definition of FULL_CARD_POWER_OFF#

Pin No. 6 Pin Name I/O Description FULL_CARD_ POWER_OFF#

DI, PD Turn on/off the module. High level: Turn on Low level: Turn off DC Characteristics VIHmax = 4.4 V VIHmin = 1.19 V VILmax = 0.2 V Comment Pull down with a 100 k resistor. It is recommended to use a host GPIO to control FULL_CARD_POWER_OFF#. A simple reference circuit is illustrated in the following figure. RM510Q-GL_Hardware_Design 30 / 88 5G Module Series RM510Q-GL Hardware Design Figure 8: Turn on the Module with a Host GPIO The timing of turn-on scenario is illustrated in the following figure. Figure 9: Turn-on Timing through FULL_CARD_POWER_OFF#

Table 9: Turn-on Time of the Module Symbol Min. Typ. Max. Comment Tpower-on 0 ms 20 ms Tturn-on Tbooting

68 ms 20 s 22 s Tregistering

System power-on time. It depends on host device. System turn-on time System booting time Network registering time related to network CSQ. RM510Q-GL_Hardware_Design 31 / 88 HostModuleFULL_CARD_POWER_OFF#PMICGPIO61.8 V or 3.3 VNote: The voltage of pin 6 should be no less than 1.19V when it is at HIGH level.R4100kVCCRESET#20 sModule power-on or insertion detectionUSIM_VDDModule StatusFCPO#RFFE_VIO_1V868 msSystem turn-on and bootingVIH 1.19 V1.8 V or 3.0 VSystem bootingInactiveActiveTpower-onTturn-onTbootingTregistering1.5 V3.7 V1.8 V 5G Module Series RM510Q-GL Hardware Design 3.5. Turn off 3.5.1. Turn off the Module through FULL_CARD_POWER_OFF#

For the design that turns on the module with a host GPIO, when the power is supplied to VCC, pulling down FULL_CARD_POWER_OFF# will turn off the module. The timing of turning-off scenario is illustrated in the following figure. Figure 10: Turn-off Timing through FULL_CARD_POWER_OFF#

Table 10: Turn-off Time through FULL_CARD_POWER_OFF#

Symbol Min. Typ. Max. Comment Tturn-off 6.84 s

System turn-off time 3.5.2. Turn off the Module through AT Command and FULL_CARD_POWER_OFF#

It is also a safe way to use AT+QPOWD command to turn off the module. For more details about the command, see document [4]. The module is designed to be turned on with a host GPIO. Pull down FULL_CARD_POWER_OFF# pin after the modules USB/PCIe is removed. Otherwise, the module will be powered on again. RM510Q-GL_Hardware_Design 32 / 88 VCC(H)RESET#(H)Module StatusFCPO#RFFE_VIO_1V8VIL 0.2 VTurn-off procedureRunningOFF1.5 V3.7 VUSIM_VDDTturn-offVIH 1.19 V1.8 V or 3.0 V1.8 V 5G Module Series RM510Q-GL Hardware Design Figure 11: Turn-off Timing through AT Command and FULL_CARD_POWER_OFF#

Table 11: Turn-off Time through AT Command and FULL_CARD_POWER_OFF#

Symbol Min. Typ. Max. Comment Tturn-off 6.84 s

System turn-off time NOTES 1. After the host detects that the module USB/PCIe is removed, FCPO# pin must be pulled down. 2. After turning off the module, it is recommended to cut of VCC power supply. 3.6. Reset RESET# is an asynchronous and active low signal (1.5 V logic level). Whenever this pin is active, the module will immediately enter Power On Reset (POR) condition. Table 12: Definition of RESET# Pin Pin No. Pin Name I/O Description DC Characteristics Comment 67 RESET#

DI, PU Reset the module Active LOW. VIHmax = 1.575 V VIHmin = 1.25 V VILmax = 0.45 V Internally pulled up to 1.5 V with a 100 k resistor RM510Q-GL_Hardware_Design 33 / 88 VCC(H)RESET#(H)USB/PCIeModule StatusFCPO#RFFE_VIO_1V8Turn-off procedureRunningOFFAT+QPOWDUSB/PCIe removed1.5 V3.7 VVIH 1.19 V1.8 V or 3.0 V1.8 VUSIM_VDDTturn-off 5G Module Series RM510Q-GL Hardware Design NOTE Triggering the RESET# signal will lead to loss of all data in the modem and removal of system drivers. It will also disconnect the modem from the network. The module can be reset by pulling down the RESET# pin for 250600 ms. An open collector/drain driver or a button can be used to control the RESET# pin. Figure 12: Reference Circuit of RESET# with NPN Driving Circuit Figure 13: Reference Circuit of RESET# with a Button RM510Q-GL_Hardware_Design 34 / 88 HostModuleRESET#PMICGPIO67VDD 1.5VReset pulse250-600 msR1100kR3100kR21kQ1NPNModuleRESET#PMIC67VDD 1.5V250-600 msS1TVSR1100k33 pFC1Note: The capacitor C1 is recommended to be less than 47 pF. The reset scenario is illustrated in the following figure. 5G Module Series RM510Q-GL Hardware Design Figure 14: Resetting Timing through RESET#

Table 13: Resetting Time through RESET#

Symbol Min. Typ. Max. Comment TRST#-USIM 200 ms

(U)SIM card turn-off time TRST#

250 ms 400 ms 600 ms More than 600 ms will cause reset repeatedly RM510Q-GL_Hardware_Design 35 / 88 VCC(H)RESET#Module StatusFCPO#(H)RFFE_VIO_1V8ResettingRunningRestarting1.5 V3.7 VUSIM_VDD250 ms TRST# 600 msVIH 1.19 V1.8 V or 3.0 V1.8 VTRST#-USIM 5G Module Series RM510Q-GL Hardware Design 4 Application Interfaces The physical connections and signal levels of RM510Q-GL comply with PCI Express M.2 specification. This chapter mainly describes the definition and application of the following interfaces/pins of the module:

(U)SIM interfaces USB interface PCIe interface PCM interface Control and indication interfaces Cellular/WLAN COEX interface*

Antenna tuner control interface*

Configuration pins 4.1. (U)SIM Interface The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both Class B (3.0 V) and Class C

(1.8 V) (U)SIM cards are supported. RM510Q-GL only supports single (U)SIM slot. 4.1.1. Pin Definition of (U)SIM Table 14: Pin Definition of (U)SIM Interface Pin No. Pin Name 36 USIM1_VDD I/O PO Description DC Characteristics Power supply for (U)SIM1 card 1.8/3.0 V 34 USIM1_DATA DIO, PU

(U)SIM1 card data 32 USIM1_CLK DO, PD

(U)SIM1 card clock 30 USIM1_RST DO, PD

(U)SIM1 card reset USIM_VDD 1.8/3.0 V USIM_VDD 1.8/3.0 V USIM_VDD 1.8/3.0 V 66 USIM1_DET DI, PU

(U)SIM1 card hot-plug detect 1.8 V RM510Q-GL_Hardware_Design 36 / 88 5G Module Series RM510Q-GL Hardware Design 4.1.2. Hot-plug of (U)SIM The module supports (U)SIM card hot-plug via the USIM_DET pin. (U)SIM card is detected by USIM_DET interrupt. (U)SIM card hot-plug is disabled by default. This is command enables (U)SIM card hot-plug function. The level of (U)SIM card detection pin should also be set when the (U)SIM card is inserted. AT+QSIMDET (U)SIM Card Detection Test Command AT+QSIMDET=?

Read Command AT+QSIMDET?

Response

+QSIMDET:

supported <insert_level>s)

(list of supported <enable>s),(list of OK Response

+QSIMDET: <enable>,<insert_level>

Write Command AT+QSIMDET=<enable>,<insert_level>

Maximum Response Time Characteristics Parameter OK Response OK Or ERROR 300 ms The command takes effect after rebooting. The configuration will be saved automatically.

<enable>

Integer type. Enable or disable (U)SIM card detection. 0 Disable 1 Enable Integer type. The level of (U)SIM detection pin when a (U)SIM card is inserted. 0 Low level 1 High level

<insert_level>

NOTES 1. Hot-plug function is invalid if the configured value of <insert_level> is inconsistent with hardware design. 2. Hot-plug function takes effect after the module is restarted. 3. USIM_DET is internally pulled up to 1.8 V by software configuration when (U)SIM hot-plug is enabled by AT+QSIMDET. RM510Q-GL_Hardware_Design 37 / 88 5G Module Series RM510Q-GL Hardware Design 4.1.3. Normally Closed (U)SIM Card Connector With a normally closed (U)SIM card connector, the USIM_DET is normally short-circuited to ground when a (U)SIM card is not inserted, and the USIM_DET will change from low to high voltage level when a

(U)SIM card is inserted. The rising edge indicates an insertion of the (U)SIM card. When the (U)SIM card is removed, USIM_DET will change from high to low voltage level. The falling edge indicates a removal of the (U)SIM card. When the (U)SIM is absent, CD is short-circuited to ground and USIM_DET is at low voltage level. When the (U)SIM is inserted, CD is open from ground and USIM_DET is at high voltage level. The following figure shows a reference design of (U)SIM interface with a normally closed (U)SIM card connector. Figure 15: Reference Circuit for Normally Closed (U)SIM Card Connector 4.1.4. Normally Open (U)SIM Card Connector With a normally open (U)SIM card connector, the USIM_DET is normally pulled down to ground through an external resistance when a (U)SIM card is not inserted, and the USIM_DET will change from low to high voltage level when a (U)SIM card is inserted. The rising edge indicates an insertion of the (U)SIM card. When the (U)SIM card is removed, USIM_DET will change from high to low voltage level. The falling edge indicates a removal of the (U)SIM card. When the (U)SIM is absent, CD1 is open from CD2 and USIM_DET is at low voltage level. When the (U)SIM is inserted, CD1 is pulled up to 1.8 V and USIM_DET is at high voltage level. The following figure shows a reference design of (U)SIM interface with a normally open (NO) (U)SIM card connector. RM510Q-GL_Hardware_Design 38 / 88 Module(U)SIM CardConnectorUSIM_DETUSIM_DATAUSIM_CLKRSTCLKCDIOUSIM_VDDUSIM_VDDUSIM_RSTVCCGNDVPPGNDTVS22 22 22 10k-20k100 nF33 pF33 pF33 pFNote: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout. 5G Module Series RM510Q-GL Hardware Design Figure 16: Reference Circuit for Normally Open (U)SIM Card Connector 4.1.5. Without Hot-plug (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_DET disconnected. A reference circuit for (U)SIM card interface with a 6-pin (U)SIM card connector is illustrated by the following figure. Figure 17: Reference Circuit for a 6-Pin (U)SIM Card Connector 4.1.6. (U)SIM Design Notices To enhance the reliability and availability of the (U)SIM card in applications, please follow the criteria below in (U)SIM circuit design. Place the (U)SIM card connector as close to the module as possible. Keep the trace length less than 200 mm. RM510Q-GL_Hardware_Design 39 / 88 Module(U)SIM CardConnectorUSIM_DETUSIM_DATAUSIM_CLKRSTCLKCD1IOUSIM_VDDUSIM_VDDUSIM_RSTVCCGNDVPPGNDTVS22 22 22 10k-20k100 nF33 pF33 pF33 pFCD21.8 V4.7kNote: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout.33kModule(U)SIM CardConnectorUSIM_DETUSIM_DATAUSIM_CLKRSTCLKIOUSIM_VDDUSIM_VDDUSIM_RSTVCCGNDVPPGNDTVS22 22 22 10k-20k100 nF33 pF33 pF33 pFNote: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout. 5G Module Series RM510Q-GL Hardware Design Keep (U)SIM card signals away from RF and VCC traces. Make sure the ground between the module and the (U)SIM card connector is short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5 mm to maintain the same electric potential. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with surrounded ground. To offer better ESD protection, add a TVS diode array of which the parasitic capacitance should be not higher than 10 pF. Add 22 resistors in series between the module and the (U)SIM card connector to suppress EMI such as spurious transmission, and to enhance ESD protection. The 33 pF capacitors are used to filter out RF interference. For USIM_DATA, a 1020 k pull-up resistor must be added near the (U)SIM card connector. 4.2. USB Interface The module provides one integrated Universal Serial Bus (USB) interface which complies with the USB 3.1 & 2.0 specifications and supports super speed (10 Gbps) on USB 3.1 and high speed (480 Mbps) and full speed (12 Mbps) modes on USB 2.0. The USB interface is used for AT command communication, data transmission, GNSS NMEA sentence output, software debugging, firmware upgrade. For more details about the USB 3.1 & 2.0 specifications, please visit http://www.usb.org/home. Table 15: Pin Definition of USB Interface Pin No. Pin Name I/O Description Comment 7 9 29 31 35 37 USB_DP AIO USB differential data bus (+) USB_DM AIO USB differential data bus (-) USB_SS_TX_M AO USB 3.1 super-speed transmit (-) USB_SS_TX_P AO USB 3.1 super-speed transmit (+) Require differential impedance of 90 USB_SS_RX_M AI USB 3.1 super-speed receive (-) USB_SS_RX_P AI USB 3.1 super-speed receive (+) The USB 2.0 interface is recommended to be reserved for firmware upgrade in designs. The following figure shows a reference circuit of USB 3.1 & 2.0 interface. RM510Q-GL_Hardware_Design 40 / 88 5G Module Series RM510Q-GL Hardware Design Figure 18: Reference Circuit of USB 3.1 & 2.0 Interface AC coupling capacitors C5 and C6 must be placed close to the host and close to each other. C1 and C2 have been integrated inside the module, so do not place these two capacitors on design. To ensure the signal integrity of USB 2.0 data traces, R1, R2, R3 and R4 must be placed close to the module, and the stubs must be minimized in PCB layout. You should follow the principles below when designing for the USB interface to meet USB 3.1 and 2.0 specifications:

Route the USB signal traces as differential pairs with ground surrounded. The impedance of differential trace of USB 2.0 and 3.1 is 90 . For USB 2.0 signal traces, the trace length should be less than 120 mm, and the differential data pair matching should be less than 2 mm. For USB 3.1 signal traces, length matching of each differential data pair (Tx/Rx) should be less than 0.7 mm, while the matching between Tx and Rx should be less than 10 mm. Do not route signal traces under crystals, oscillators, magnetic devices, PCIe and RF signal traces. Route the USB differential traces in inner-layer of the PCB, and surround the traces with ground on that layer and with ground planes above and below. Junction capacitance of the ESD protection device might cause influences on USB data lines, so you should pay attention to the selection of the device. Typically, the stray capacitance should be less than 1.0 pF for USB 2.0, and less than 0.15 pF for USB 3.1. Keep the ESD protection devices as close to the USB connector as possible. If possible, reserve 0 resistors on USB_DP and USB_DM lines respectively. NOTES 1. Only USB 2.0 can be used for firmware upgrade currently. 2. If no USB interface is designed, make sure AT and DM port OK. RM510Q-GL_Hardware_Design 41 / 88 HostModuleUSB_DMUSB_DPUSB_SS_RX_PUSB_SS_RX_MUSB_SS_TX_PUSB_SS_TX_MBBUSB_DMUSB_DPUSB_SS_RX_PUSB_SS_RX_MUSB_SS_TX_PUSB_SS_TX_M9737353129ESDTest PointsC5 220 nFC6 220 nFC1 220 nFC2 220 nFR1 0R2 0R4 NM-0R3 NM-0Minimize these stubs in PCB layout. 5G Module Series RM510Q-GL Hardware Design 4.3. PCIe Interface The module provides one integrated PCIe (Peripheral Component Interconnect Express) interface. PCI Express Base Specification Revision 3.0 compliant Data rate up to 8 Gbps per lane 4.3.1. PCIe Operating Mode The module supports endpoint (EP) mode and root complex (RC) mode. In EP mode, the module is configured as a PCIe EP device. In RC mode, the module is configured as a PCIe root complex. AT+QCFG="pcie/mode" is used to set PCIe RC/EP mode. AT+QCFG="pcie/mode" Set PCIe RC/EP Mode Write Command AT+QCFG="pcie/mode"[,<mode>]

Response If the optional parameter is omitted, query the current setting:

+QCFG: "pcie/mode",<mode>

OK If the optional parameter is specified, set PCIe RC/EP mode:

OK Or ERROR Maximum Response Time 300 ms Characteristics Parameter

<mode>

This command will take effect after rebooting. The configuration will be saved automatically. Integer type. Set PCIe RC or EP mode. 0 PCIe EP mode. 1 PCIe RC mode. For more details about the command, see document [4]. 4.3.2. Pin Definition of PCIe The following table shows the pin definition of PCIe interface. RM510Q-GL_Hardware_Design 42 / 88 5G Module Series RM510Q-GL Hardware Design Table 16: Pin Definition of PCIe Interface Pin No. Pin Name I/O Description Comment 55 53 49 47 43 41 50 52 54 PCIE_REFCLK_P AIO PCIe reference clock (+) PCIE_REFCLK_M AIO PCIe reference clock (-) PCIE_RX_P AI PCIe receive (+) PCIE_RX_M PCIE_TX_P PCIE_TX_M AI AO AO PCIE_RST_N DI, OD PCIE_CLKREQ_N DO, OD PCIE_WAKE_N DO, OD PCIe receive (-) PCIe transmit (+) PCIe transmit (-) PCIe reset. Active LOW. PCIe clock request. Active LOW. PCIe wake up. Active LOW. 100 MHz. Require differential impedance of 85 Require differential impedance of 85 Require differential impedance of 85 Open drain Open drain Open drain 4.3.3. Reference Design of PCIe The following figure shows a reference circuit for the PCIe interface. Figure 19: PCIe Interface Reference Circuit RM510Q-GL_Hardware_Design 43 / 88 HostModulePCIE_REFCLK_PPCIE_REFCLK_MPCIE_RX_PPCIE_RX_MPCIE_TX_PPCIE_TX_MBBPCIE_REFCLK_PPCIE_REFCLK_MPCIE_RX_PPCIE_RX_MPCIE_TX_PPCIE_TX_M555349474341PCIE_CLKREQ_NPCIE_RST_NPCIE_WAKE_NPCIE_CLKREQ_NPCIE_RST_NPCIE_WAKE_NVCC_IO_HOST545250Note. The voltage level VCC_IO_HOST of these three signals depend on the host side due to open drain.R5 0R4 0C5 220 nFC6 220 nFC1 220 nFC2 220 nFR110kR210kR3NM/10kR410k 5G Module Series RM510Q-GL Hardware Design To ensure the signal integrity of PCIe interface, AC coupling capacitors C5 and C6 should be placed close to the host on PCB. C1 and C2 have been embedded into the module, so do not place these two capacitors on your schematic and PCB. The following principles of PCIe interface design should be complied with, so as to meet PCIe specification. Keep the PCIe data and control signals away from sensitive circuits and signals, such as RF, audio, crystal and oscillator signals. Add a capacitor in series on Tx/Rx traces to prevent any DC bias. Keep the maximum trace length less than 300 mm. Keep the length matching of each differential data pair (Tx/Rx) less than 0.7 mm for PCIe routing traces. Keep the differential impedance of PCIe data trace as 85 10 %. You must not route PCIe data traces under components or cross them with other traces. 4.3.4. PCIe Timing Figure 20: PCIe Power-up Timing of M.2 Specification Table 17: PCIe Power-up Timing of M.2 Specification Symbol Min. Typ. Max. Comment TPVPGL 50 ms TPERST#-CLK 100 s

Power Valid to PERST# Input inactive REFCLK stable before PERST# inactive RM510Q-GL_Hardware_Design 44 / 88 5G Module Series RM510Q-GL Hardware Design Figure 21: PCIe Power-up Timing of the Module Table 18: PCIe Power-up Timing of Module Symbol Min. Typ. Max. Comment Tpower-on 0m s 20 ms Tturn-on

68 ms TFCPO#-CLKREQ#

90 ms 100 ms TFCPO#-PERST#

100 ms

TPERST#-CLK 100 s -

System power-on time. It is depend on host device. System turn-on time Power valid to CLKREQ# output active Power valid to PERST# input inactive REFCLK stable before PERST# inactive 4.4. PCM Interface The following table shows the pin definition of PCM interface which can be applied to audio codec design. Table 19: Pin Definition of PCM Interface Pin No. Pin Name I/O Description DC Characteristics 20 22 24 28 PCM_CLK DI, PD PCM data bit clock PCM_DIN DI, PD PCM data input PCM_DOUT DO, PD PCM data output PCM_SYNC DI,PD PCM data frame sync 1.8 V 1.8 V 1.8 V 1.8 V RM510Q-GL_Hardware_Design 45 / 88 TFCPO#-CLKREQ# > 90 msPCIE_CLKREQ_NPCIE_RST_NPCIE_REFCLKTpower-onTturn-onVCCRESET_NModule power-on or insertion detectionFCPO#RFFE_VIO_1V8System turn-on and bootingVIH 1.19 V1.5 V3.7 V1.8 VTFCPO#-PERST# > 100 msTPERST#-CLK > 100 us 5G Module Series RM510Q-GL Hardware Design The module supports audio communication via Pulse Code Modulation (PCM) digital interface. The PCM interface supports the following modes:

Primary mode (short frame synchronization): the module works as both master and slave Auxiliary mode (long frame synchronization): the module works as master only In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC falling edge represents the MSB. In this mode, the PCM interface supports 256 kHz, 512 kHz, 1024 kHz or 2048 kHz PCM_CLK at 8 kHz PCM_SYNC, and also supports 4096 kHz PCM_CLK at 16 kHz PCM_SYNC. In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC rising edge represents the MSB. In this mode, PCM interface operates with a 256 kHz PCM_CLK and an 8 kHz, 50 % duty cycle PCM_SYNC only. The module supports 16-bit linear data format. The following figures show the primary modes timing relationship with 8 kHz PCM_SYNC and 2048 kHz PCM_CLK, as well as the auxiliary modes timing relationship with 8 kHz PCM_SYNC and 256 kHz PCM_CLK. Figure 22: Primary Mode Timing Figure 23: Auxiliary Mode Timing RM510Q-GL_Hardware_Design 46 / 88 12255256125 sPCM_CLKPCM_SYNCMSBMSBLSBPCM_DOUTMSBMSBLSBPCM_DIN123132125 sPCM_CLKPCM_SYNCMSBMSBLSBPCM_DOUTMSBMSBLSBPCM_DIN 5G Module Series RM510Q-GL Hardware Design The clock and mode can be configured by AT command, and the default configuration is master mode using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See document [4] for details about AT+QDAI command. 4.5. Control and Indication Interfaces The following table shows the pin definition of control and indication pins. Table 20: Pin Definition of Control and Indication Interfaces Pin No. Pin Name I/O Description DC Characteristics 8 W_DISABLE1#

DI, OD 26 W_DISABLE2#

DI, OD Airplane mode control. Pulled up by default. Active LOW. GNSS disable control. Pulled up by default. Active LOW. 1.8/3.3 V 1.8/3.3 V 10 23 25 38 68 WWAN_LED#

DO,OD Indicate RF status of the module. Open drain. VCC WAKE_ON_WAN# DO,OD DPR*

DI, PU Wake up the host. Open drain. Dynamic power reduction. High level by default. SDX2AP_STATUS DO, PD Status indication to AP AP2SDX_STATUS DI, PD Status indication from AP 1.8 V 1.8 V 1.8 V 4.5.1. W_DISABLE1#

The module provides a W_DISABLE1# pin to disable or enable airplane mode through hardware operation. W_DISABLE1# is pulled up by default. Driving it low will set the module to airplane mode. In airplane mode, the RF function will be disabled. The RF function can also be enabled or disabled through software AT commands. The following table shows the RF function status of the module. RM510Q-GL_Hardware_Design 47 / 88 5G Module Series RM510Q-GL Hardware Design Table 21: RF Function Status W_DISABLE1# Level AT Commands RF Function Status High Level AT+CFUN=1 Enabled (RF operation allowed) High Level AT+CFUN=0 AT+CFUN=4 Low Level AT+CFUN=1 Disabled (no RF operation allowed) Low Level AT+CFUN=0 AT+CFUN=4 4.5.2. W_DISABLE2#

The module provides a W_DISABLE2# pin to disable or enable the GNSS function. The W_DISABLE2#

pin is pulled up by default. Driving it low will disable the GNSS function. The combination of W_DISABLE2# pin and AT commands can control the GNSS function. Table 22: GNSS Function Status W_DISABLE2# Level AT Commands GNSS Function Status High Level AT+QGPS=1 Enabled (GNSS function allowed) High Level AT+QGPSEND Low Level AT+QGPS=1 Disabled (no GNSS function allowed) Low Level AT+QGPSEND A simple level shifter based on diodes is used on W_DISABLE1# pin and W_DISABLE2# pin which are pulled up to a 1.8 V voltage in the module, as shown in the following figure, so the control signals (GPIO) of the host device could be at 1.8 V or 3.3 V voltage level. W_DISABLE1# and W_DISABLE2# are active low signals, and a reference circuit is shown as below. RM510Q-GL_Hardware_Design 48 / 88 5G Module Series RM510Q-GL Hardware Design Figure 24: W_DISABLE1# and W_DISABLE2# Reference Circuit 4.5.3. WWAN_LED#

The WWAN_LED# signal is used to indicate RF status of the module, and its sink current is up to 10 mA. To reduce current consumption of the LED, a current-limited resistor must be placed in series with the LED, as illustrated in the figure below. The LED is ON when the WWAN_LED# signal is at low level. Figure 25: WWAN_LED# Reference Circuit The following table shows the RF status indicated by WWAN_LED# . Table 23: Network Status Indications of WWAN_LED#

WWAN_LED# Level Description Low Level (LED ON) RF function is turned on RM510Q-GL_Hardware_Design 49 / 88 HostModuleW_DISABLE2#W_DISABLE1#BBGPIOGPIO268VDD 1.8VR510kR610kNotes: The voltage level of VCC_IO_HOST could be 1.8 V or 3.3 V typically.VCC_IO_HOSTR2100kR3100kModuleWWAN_LED#PMIC10VCC(Typ. 3.7V)R1330 LED12, 470,72,74VCC 5G Module Series RM510Q-GL Hardware Design High Level (LED OFF) RF function is turned off if any of the following occurs:

The (U)SIM card is not powered. W_DISABLE1# is at low level (airplane mode enabled). AT+CFUN=4 (RF function disabled). 4.5.4. WAKE_ON_WAN#

The WAKE_ON_WAN# is an open drain pin, which requires a pull-up resistor on the host. When a URC returns, a 1 s low level pulse signal will be outputted to wake up the host. The module operation status indicated by WAKE_ON_WAN# is shown as below. Table 24: State of the WAKE_ON_WAN#

WAKE_ON_WAN# State Module Operation Status Output a 1 s low level pulse signal Call/SMS/Data is incoming (to wake up the host) Always at high level Idle/Sleep Figure 26: WAKE_ON_WAN# Signal Reference Circuit 4.5.5. DPR*

The module provides the DPR (Dynamic Power Reduction) pin for body SAR (Specific Absorption Rate) detection. The signal is sent from a host system proximity sensor to the module to provide an input trigger, which will reduce the output power in radio transmission. RM510Q-GL_Hardware_Design 50 / 88 HostModuleWAKE_ON_WAN#BBGPIO23VCC_IO_HOST (Typ. 1.8 V or 3.3 V)Note. The voltage level VCC_IO_HOST depends on the host side due to open drain in pin23.Wake up the host1sHLR110k 5G Module Series RM510Q-GL Hardware Design Table 25: Function of the DPR Signal DPR Level Function High/Floating NO max. transmitting power backoff Low Max. transmitting power backoff by AT+QCFG="sarcfg"

NOTE See document [4] for more details about AT+QCFG="sarcfg" command. 4.5.6. STATUS The module provides two status indication pins for communication with IPQ807x device. Pin 38

(SDX2AP_STATUS) outputs IPQ807x device, and pin 68 the status

(AP2SDX_STATUS) inputs the status indication signal from IPQ807x device. indication signal to 4.6. Cellular/WLAN Coexistence Interface*

The module provides the cellular/WLAN Coexistence interface, the following table shows the pin definition of this interface. Table 26: Pin Definition of Coexistence Interface Pin No. Pin Name I/O Description DC Characteristics 59 60 62 64 LAA_TX_EN DO WLAN_TX_EN DI Notification from SDR to WLAN when LTE transmitting 1.8 V Notification from WLAN to SDR while transmitting 1.8 V COEX_RXD DI, PD LTE/WLAN coexistence receive data 1.8 V COEX_TXD DO, PD LTE/WLAN coexistence transmit data 1.8 V RM510Q-GL_Hardware_Design 51 / 88 5G Module Series RM510Q-GL Hardware Design 4.7. Antenna Tuner Control Interface ANTCTL[1:2] and RFFE interface are used for antenna tuner control and should be routed to an appropriate antenna control circuit. More details about the interface will be added in the future version of this document. Table 27: Pin Definition of Antenna Tuner Control Interface Pin No. Pin Name I/O Description DC Characteristics RFFE_CLK* 1) DO Used for external MIPI IC control 1.8 V RFFE_DATA* 1) IO Used for external MIPI IC control 1.8 V RFFE_VIO_1V8 1) PO Power supply for antenna tuner 1.8 V ANTCTL1*

DO, PD Antenna Control GPIO ANTCTL2*

DO, PD Antenna Control GPIO 1.8 V 1.8 V 56 58 65 61 63 NOTE 1) If customers have this function requirement, please contact us for more details. 4.8. Configuration Pins The module provides four configuration pins, which are defined as below. Table 28: Configuration Pins List of M.2 Specification Config_0

(Pin 21) Config_1

(Pin 69) Config_2

(Pin 75) Config_3

(Pin 1) Module Type and Main Host Interface Port Configuration NC GND NC NC Quectel defined 2 Table 29: Definition of Configuration Pins Pin No. 21 Pin Name I/O Description DC Characteristics CONFIG_0 DO Not connected internally

RM510Q-GL_Hardware_Design 52 / 88 5G Module Series RM510Q-GL Hardware Design 69 75 1 CONFIG_1 DO Connected to GND internally CONFIG_2 DO Not connected internally CONFIG_3 DO Not connected internally

The following figure shows a reference circuit of these four pins. Figure 27: Recommended Circuit of Configuration Pins RM510Q-GL_Hardware_Design 53 / 88 HostModuleCONFIG_0CONFIG_1CONFIG_2CONFIG_3GPIOGPIOGPIOGPIO2169751VCC_IO_HOSTR110kR210kR310kR410kNM-0 NM-0 0 NM-0 Notes: The voltage level of VCC_IO_HOST could be 1.8 V or 3.3 V typically. 5G Module Series RM510Q-GL Hardware Design 5 RF Characteristics This chapter mainly describes RF characteristics of the module. 5.1. mmWave IF Interfaces 5.1.1. Assignment and Definition of mmWave IF Interfaces The following figure and table show the assignment and definition of RM510Q-GL mmWave IF interfaces respectively. Figure 28: Assignment of mmWave IF Interfaces RM510Q-GL_Hardware_Design 54 / 88 IFV4IFH1IFH2IFV3IFV2IFH3IFH4IFV1ANT2ANT1ANT0ANT3_GNSSL1 5G Module Series RM510Q-GL Hardware Design Table 30: Definition of mmWave IF Interfaces mmWave IF Interface IFH1 IFH2 IFH3 IFH4 IFV1 IFV2 IFV3 IFV4 I/O AIO AIO AIO AIO AIO AIO AIO AIO Functional Description Horizontal polarization IF output signal and control signal for mmWave RFIC device 1 Horizontal polarization IF output signal and control signal for mmWave RFIC device 2 Horizontal polarization IF output signal and control signal for mmWave RFIC device 3 Horizontal polarization IF output signal and control signal for mmWave RFIC device 4 Vertical polarization IF output signal and local oscillator (LO) signal for mmWave RFIC device 4 Vertical polarization IF output signal and LO signal for mmWave RFIC device 3 Vertical polarization IF output signal and LO signal for mmWave RFIC device 2 Vertical polarization IF output signal and LO signal for mmWave RFIC device 1 5.1.2. Characteristics of mmWave IF Interfaces 5.1.2.1. VSWR Requirements of mmWave IF Interfaces Table 31: VSWR Requirements of mmWave IF Interfaces Range VSWR Requirement 10 MHz to 1.2 GHz Better than 2:1 1.23.6 GHz Better than 2:1 610 GHz Better than 2:1; variation over 1.4 GHz < 0.5 5.1.2.2. Insertion Loss Requirements of mmWave IF Interfaces Table 32: Insertion Loss Requirements of mmWave IF Interfaces Range Insertion Loss Requirement 10 MHz to 1.2 GHz

< 2 dB RM510Q-GL_Hardware_Design 55 / 88 5G Module Series RM510Q-GL Hardware Design 1.23.6 GHz

< 4 dB 610 GHz

< 7 dB (from the IFIC to the RFIC)

< 5 dB (from the RM510-GL to QTM525) 5.1.2.3. IF Isolation IF isolation requirements for proper operation at 610 GHz operating frequency are as follows:

Total system isolation between an IF path (combined PCB, cables, connectors, and so on) and the connected antenna module should be more than 35 dB, and the isolation between an IF path and other antenna modules should be more than 25 dB. 5.1.2.4. mmWave and Sub-6 GHz Antennas Coexistence Isolation between mmWave and sub-6 GHz antennas: > 20 dB The following table shows the isolation requirements between IF cable and Sub-6 GHz antennas. Table 33: Isolation Requirements between IF cable to Sub-6 GHz Antennas Range Isolation Requirement 100 MHz 1 GHz 16 GHz 610 GHz 75 dB 70 dB 65 dB 5.1.3. mmWave IF Port Mapping RM510Q-GL supports QTM525(power class 3) and QTM527(power class 1). IF port mapping as shown below. Table 34: mmWave IF Port Mapping Group QTM_Pon RM510Q-GL QTM527 QTM525 1 QTM0_PON IFV4 IFH1 QTM527-1_IF2 (V) IF2 (V) QTM527-1_IF1 (H) IF1 (H) RM510Q-GL_Hardware_Design 56 / 88 5G Module Series RM510Q-GL Hardware Design IFH2 IFV3 IFV2 IFH3 IFV1 IFH4 QTM527-2_IF1 (H) IF1 (H) QTM527-2_IF2 (V) IF2 (V) QTM527-3_IF2 (V) IF2 (V) QTM527-3_IF1 (H) IF1 (H) QTM527-4_IF2 (V) IF2 (V) QTM527-4_IF1 (H) IF1 (H) 2 3 4 QTM2_PON QTM3_PON QTM1_PON 5.1.4. IF Connector The dimensions of antenna receptacle (IPEX: 20981-001E-02) on the RM510Q-GL and plug (IPEX:

20980-001R-13) are illustrated as below. Figure 29: Dimensions of IF Connectors RM510Q-GL_Hardware_Design 57 / 88 5G Module Series RM510Q-GL Hardware Design 5.2. Cellular Antenna Interfaces 5.2.1. Pin Definition The pin definition of antenna interfaces is shown below. Table 35: RM510Q-GL Pin Definition of Antenna Interfaces Pin Name I/O Description Comment Antenna0 interface:

5G NR: MHB_TRX & n41 TRX11)

& n77/n78/n79_PRX MIMO;

LTE: MHB_TRX & UHB2)_PRX MIMO WCDMA: MHB_TRX Antenna1 interface:

5G NR: LB_TRX & MHB_DRX MIMO &

n41_DRX11) & n77/n78/n79_DRx MIMO LTE: LB_TRX & MHB_DRX MIMO & UHB2)_DRX MIMO &

LAA PRX WCDMA: LB_TRX Antenna2 interface:

5G NR: LB_DRX & MHB_PRX MIMO &

n41 TRX0 1) & n77/n78/n79_TRX LTE: LB_DRX & MHB_PRX MIMO & UHB 2) _TRX WCDMA: LB_DRX Antenna3 interface:

5G NR: MHB_DRX MIMO & n41 DRX0 1)

& n77/n78/n79_DRX LTE: MHB_DRX & UHB 2)_DRX & LAA DRX WCDMA: MHB_DRX GNSS: L1 50 impedance 50 impedance 50 impedance 50 impedance ANT0 AIO ANT1 AIO ANT2 AIO ANT3_ GNSSL1 AI NOTES 1.1) NR TRX1 = TX MIMO + PRX MIMO; NR DRX1 = DRX MIMO 2.2) UHB frequency range: 34003800 MHz 5.2.2. Port Mapping Table 36: Antenna Mapping RM510Q-GL_Hardware_Design 58 / 88 5G Module Series RM510Q-GL Hardware Design Antenna WCDMA 4G 5G NR Refarmed n41 n77/n78/

n79 LB MHB

(MHz)

(MHz) n77/

n78

(MHz) n79

(MHz) 1452 3300 4400 to to to 2690 4200 5000 TRX1 2 PRX TRX1 2 MIMO ANT0 MHB_TRX UHB1) _PRX UHB 1) _PRX MHB_TRX MHB_TRX ANT1 LB_TRX ANT2 LB_DRX MIMO LB_TRX MHB_DRX MIMO, UHB1)_DRX MIMO, LAA PRX MIMO LB_TRX MHB_DRX MIMO UHB 1)_DRX MIMO, LB_DRX, LB_DRX, MHB_PRX MHB_PRX MIMO, UHB 1) MIMO, _TRX UHB 1) _ TRX ANT3_ GNSSL1 MHB_DRX, MHB_DRX UHB 1) _DRX, LAA_DRX MHB_DRX, UHB 1) _DRX, DRX1 2 DRX MIMO 617 1452 3300 4400 to to to to 960 2690 4200 6000 TRX0 2 TRX to to to to 617 1452 3300 4400 960 2690 4200 5000 1452 3300 4400 DRX0 2 DRX

to to to 2690 4200 6000 NOTES 1. 1) UHB frequency range: 34003800 MHz 2. 2) NR TRX1 = TX MIMO + PRX MIMO; NR DRX1 = DRX MIMO 5.2.3. Operating Frequency Table 37: RM510Q-GL Module Operating Frequency Band Name Transmit

(MHz) Receive (MHz) LTE-FDD LTE-TDD UMTS 5G NR IMT (2100) 19201980 21102170 PCS (1900) 18501910 19301990 DCS (1800) 17101785 18051880 AWS 17101755 21102155 Cell (850) 824849 869894 JCELL (800) 830840 875885 B1 B2 B3 B4 B5 IMT-E (2600) 25002570 26202690 B7 B1 B2 B3 B4 B5 B6 n1 n2 n3 n5 n7 RM510Q-GL_Hardware_Design 59 / 88 EGSM (950) 880915 925960 B8 700 lower AC 699716 729746 B12(B17) 700 upper C 777787 746756 700 D 788798 758768 B18 B19 815830 860875 830845 875890 EU800 832862 791821 B13 B14 B18 B19 B20 PCS + G 18501915 19301995 B25 B26 814849 859894 700 APAC 703748 758803 FLO WCS 717728 23052315 23502360 B30 L-band 14521496 B32 B34 B38 B39 B40 20102025 20102025 25702620 25702620 18801920 18801920 23002400 23002400 B41/B41-XGP 24962690 24962690 B42 B43 B46 B48 B66 B71 n77 n78 n79 34003600 34003600 36003800 36003800 51505925 51505925 35503700 35503700 17101780 21102200 B66 663698 617652 B71 33004200 33004200 33003800 33003800 44005000 44005000 B26 B28 B29 5G Module Series RM510Q-GL Hardware Design B34 B38 B39 B40 B41 B42 B43 B46 B48 B8 B19 n8 n12 n20 n25 n28 n38 n40 n41 n48*

n66 n71 n77 n78 n79 RM510Q-GL_Hardware_Design 60 / 88 5G Module Series RM510Q-GL Hardware Design 5.2.4. Sensitivity The following tables show conducted receiving sensitivity of RM510Q-GL. Table 38: RM510Q-GL Conducted Receiving Sensitivity Mode Frequency Primary Diversity SIMO 1) 3GPP

(SIMO) WCDMA B1 WCDMA B2 WCDMA B3

-109.5

-110.3

-110.5

-106.7 dBm

-109.5

-110.6

-110.5

-104.7 dBm

-109.5

-110.4

-110.5

-103.7 dBm WCDMA WCDMA B4

-109

-110.1

-110

-106.7 dBm WCDMA B5 WCDMA B8

-110.5

-112

-112

-104.7 dBm

-109.5

-112

-111.5

-103.7 dBm WCDMA B19

-111

-112

-112

-104.7 dBm LTE-FDD B1 (10 MHz)

-98.0

-99.2

-101.0

-96.3 dBm LTE-FDD B2 (10 MHz)

-97.0

-99.2

-101.5

-94.3 dBm LTE-FDD B3 (10 MHz)

-97.0

-98.7

-101.2

-93.3 dBm LTE-FDD B4 (10 MHz)

-97.5

-98.7

-101.0

-96.3 dBm LTE-FDD B5 (10 MHz)

-99.0

-101.0

-102.5

-94.3 dBm LTE-FDD B7 (10 MHz)

-97.0

-98.5

-100.5

-94.3 dBm LTE LTE-FDD B8 (10 MHz)

-98.5

-100.5

-102.2

-93.3 dBm LTE-FDD B12(B17) (10 MHz)

-99.5

-101.5

-102.5

-93.3 dBm LTE-FDD B13 (10 MHz)

-100.0

-101.5

-102.5

-93.3 dBm LTE-FDD B14 (10 MHz)

-100.0

-101.2

-102.5

-93.3 dBm LTE-FDD B18 (10 MHz)

-99.5

-101.5

-102.5

-96.3 dBm LTE-FDD B19 (10 MHz)

-98.7

-101.0

-102.0

-96.3 dBm LTE-FDD B20 (10 MHz)

-99.0

-101.2

-102.1

-93.3 dBm RM510Q-GL_Hardware_Design 61 / 88 5G Module Series RM510Q-GL Hardware Design LTE-FDD B25 (10 MHz)

-100.0

-101.5

-102.5

-92.8 dBm LTE-FDD B26 (10 MHz)

-97.0

-99.3

-101.0

-93.8 dBm LTE-FDD B28 (10 MHz)

-99.0

-101.3

-102.2

-94.8 dBm LTE-FDD B30 (10 MHz)

-100.0

-101.5

-102.5

-95.3 dBm LTE-FDD B32 (10 MHz) TBD TBD TBD

-95.3 dBm LTE-TDD B34 (10 MHz)

-97.0

-98.5

-100.5

-96.3 dBm LTE-TDD B38 (10 MHz)

-97.0

-98.3

-100.5

-96.3 dBm LTE-TDD B39 (10 MHz)

-97.0

-97.0

-100.0

-96.3 dBm LTE-TDD B40 (10 MHz)

-96.0

-97.0

-100.0

-96.3 dBm LTE-TDD B41 (10 MHz)

-96.8

-98.3

-100.5

-94.3 dBm LTE-TDD B42 (10 MHz)

-96.8

-99.0

-100.5

-95 dBm LTE-TDD B43 (10 MHz)

-96.8

-99.0

-100.5

-95 dBm LTE-TDD B48 (10 MHz)

-96.8

-96.8

-99.0

-95 dBm LTE-FDD B66 (10 MHz)

-96.8

-98.3

-100.2

-96.5 dBm LTE-FDD B71 (10 MHz)

-100.0

-101.0

-102.5

-94.2 dBm 5G NR-FDD n1 (20 MHz)

(SCS: 15 kHz) 5G NR-FDD n2 (20 MHz)

(SCS: 15 kHz) 5G NR-FDD n3 (20 MHz)

(SCS: 15 kHz) 5G NR-FDD n5 (10 MHz)

(SCS: 15 kHz) 5G NR-FDD n7 (20 MHz)

(SCS: 15 kHz) 5G NR-FDD n8 (10 MHz)

(SCS: 15 kHz) 5G NR-FDD n12 (10 MHz)

(SCS: 15 kHz) 5G NR-FDD n20 (10 MHz)

(SCS: 15 kHz)

-94.5

-95.5

-97.5

-94.0 dBm

-94.5

-95.5

-97.5

-92.0 dBm

-93.5

-95.5

-97.0

-91.0 dBm

-95.5

-97.0

-99.5

-95.0 dBm

-93.5

-94

-96.5

-92.0 dBm

-95.0

-97.0

-98.5

-94.0 dBm

-95.0

-98.0

-99.5

-94.0 dBm

-95.0

-97.0

-99.0

-94.0 dBm 5G NR-FDD n25 (20 MHz)

-94.5

-95.0

-97.5

-90.5 dBm 5G NR RM510Q-GL_Hardware_Design 62 / 88 5G Module Series RM510Q-GL Hardware Design

-95.0

-97.0

-99.0

-96.0 dBm

-94.0

-95.0

-97.0

-94.0 dBm

-93.5

-93.5

-95.5

-94.0 dBm

-85.0

-87.0

-88.5

-92.0 dBm

-94.0

-95.5

-97

-93.5 dBm

-91.5

-92.0

-94.5

-93.5 dBm

-95.0

-97.5

-99.5

-94.0 dBm

-86.0

-87.0

-89.0

-92.9 dBm

-86.0

-87.5

-89.0

-92.9 dBm

-86.0

-86.5

-89.5

-89.7 dBm

(SCS: 15 kHz) 5G NR-FDD n28 (10 MHz)

(SCS: 15 kHz) 5G NR-TDD n38 (20 MHz)

(SCS: 30 kHz) 5G NR-TDD n40 (20 MHz)

(SCS: 30 kHz) 5G NR-TDD n41 (20 MHz)

(SCS: 30 kHz) 5G NR-FDD n48 (20 MHz)

(SCS: 30 kHz) 5G NR-FDD n66 (20 MHz)

(SCS: 15 kHz) 5G NR-FDD n71 (10 MHz)

(SCS: 15 kHz) 5G NR-TDD n77 (20 MHz)

(SCS: 30 kHz) 5G NR-TDD n78 (20 MHz)

(SCS: 30 kHz) 5G NR-TDD n79 (40 MHz)

(SCS: 30 kHz) NOTE 1) SIMO is a smart antenna technology that uses a single antenna at the transmitter side and two antennas at the receiver side, which improves Rx performance. 5.2.5. Output Power The following table shows the RF output power of the module. Table 39: Cellular Output Power Mode Frequency Max. Min. WCDMA WCDMA bands 24 dBm +1/-3 dB (Class 3)

< -50 dBm LTE bands 23 dBm 2 dB (Class 3)

< -40 dBm LTE LTE HPUE bands

(B38/B40/B41/B42/B43) 26 dBm 2 dB (Class 2)

< -40 dBm RM510Q-GL_Hardware_Design 63 / 88 5G Module Series RM510Q-GL Hardware Design 5G NR bands 23 dBm 2 dB (Class 3) 5G NR HPUE bands

(n41/n77/n78/n79) 26 dBm +2/-3 dB (Class 2)

< -40 dBm

(BW: 520 MHz) 1)

< -40 dBm

(BW: 520 MHz) 1) 5G NR NOTE 1) For 5G NR TDD bands, the normative reference for this requirement is TS 38.101-1 [2] clause 6.3.1 5.3. GNSS Antenna Interface The following table shows frequency specification of GNSS antenna connector. 5.3.1. General Description The module includes a fully integrated global navigation satellite system solution (GPS, GLONASS, BeiDou/Compass, and Galileo). The module supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1 Hz data update rate via USB interface by default. By default, the module GNSS engine is switched off. It has to be switched on via AT command. For more details about GNSS engine technology and configurations, see document [5]. 5.3.2. GNSS Frequency Table 40: GNSS Frequency Type Frequency GPS/Galileo/QZSS 1575.42 1.023 (L1) Galileo QZSS GLONASS BeiDou 1575.42 2.046 (E1) 1575.42 (L1) 1597.51605.8 1561.098 2.046 Unit MHz MHz MHz MHz MHz RM510Q-GL_Hardware_Design 64 / 88 5G Module Series RM510Q-GL Hardware Design NOTES 1. Keep the characteristic impedance for the trace of GNSS antenna (ANT3_GNSSL1) to 50 . 2. Place the -type matching components as close to the antenna as possible. 3. Keep the digital circuits, such as that of (U)SIM card, USB interface, camera module, display connector and SD card, away from the antenna traces. 4. Keep 75 dB isolation between each two antenna traces. 5. Keep 15 dB isolation between each two antennas to improve the receiving sensitivity. and 20 dB isolation between 5G NR UL MIMO TRX0 and TRX1 antennas. 5.3.3. GNSS Performance The following table shows GNSS performance of RM510Q-GL. Table 41: GNSS Performance Parameter Description Conditions Sensitivity

(GNSS) Cold start Autonomous Reacquisition Autonomous Tracking Autonomous Cold start

@ open sky TTFF

(GNSS) Warm start

@ open sky Hot start

@ open sky CEP-50 Accuracy

(GNSS) NOTES Autonomous XTRA enabled Autonomous XTRA enabled Autonomous XTRA enabled Autonomous

@ open sky Typ.

-148

-159

-159 33.99 13.56 22.55 2.02 1.33 1.47 1.8 Unit dBm dBm dBm s s s s s s m RM510Q-GL_Hardware_Design 65 / 88 5G Module Series RM510Q-GL Hardware Design 1. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep positioning for at least 3 minutes continuously). 2. Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock within 3 minutes after the loss of lock. 3. Cold start sensitivity: the minimum GNSS signal power at which the module can fix position successfully within 3 minutes after executing cold start command. 5.4. Antenna Connectors 5.4.1. Antenna Connector Location RM510Q-GL have four antenna connectors each: ANT0, ANT1, ANT2 and ANT3_GNSSL1, which are shown as below. Figure 30: RM510Q-GL Antenna Connectors 5.4.2. Antenna Connector Size RM510Q-GL are mounted with standard 2 mm 2 mm receptacle antenna connectors for convenient antenna connection. The antenna connectors PN is IPEX 20579-001E, and the connector dimensions are illustrated as below:

RM510Q-GL_Hardware_Design 66 / 88 IFV4IFH1IFH2IFV3IFV2IFH3IFH4IFV1ANT2ANT1ANT0ANT3_GNSSL1 5G Module Series RM510Q-GL Hardware Design Figure 31: RF Connector Dimensions (Unit: mm) Table 42: Major Specifications of the RF Connector Item Specification Nominal Frequency Range DC to 6 GHz Nominal Impedance 50 Temperature Rating

-40 to +85 C Voltage Standing Wave Ratio (VSWR) Meet the requirements of:

Max 1.3 (DC3 GHz) Max 1.4 (36 GHz) 5.4.3. Antenna Connector Installation The receptacle RF connector used in conjunction with the module will accept two types of mating plugs that will meet a maximum height of 1.2 mm using a 0.81 mm coaxial cable or a maximum height of 1.45 mm utilizing a 1.13 mm coaxial cable. The following figure shows the specifications of mating plugs using 0.81 mm coaxial cables. RM510Q-GL_Hardware_Design 67 / 88 5G Module Series RM510Q-GL Hardware Design Figure 32: Specifications of Mating Plugs Using 0.81 mm Coaxial Cables The following figure illustrates the connection between the receptacle RF connector on the module and the mating plug using a 0.81 mm coaxial cable. Figure 33: Connection between RF Connector and Mating Plug Using 0.81 mm Coaxial Cable The following figure illustrates the connection between the receptacle RF connector on the module and the mating plug using a 1.13 mm coaxial cable. RM510Q-GL_Hardware_Design 68 / 88 5G Module Series RM510Q-GL Hardware Design Figure 34: Connection between RF Connector and Mating Plug Using 1.13 mm Coaxial Cable 5.4.4. Recommended RF Connector for Installation 5.4.4.1. Assemble Coaxial Cable Plug Manually The pictures for plugging in a coaxial cable plug is shown below, = 90 OK, 90 NG. Figure 35Plug in A Coaxial Cable Plug The pictures of pulling out the coaxial cable plug is shown below, = 90 OK, 90 NG. RM510Q-GL_Hardware_Design 69 / 88 5G Module Series RM510Q-GL Hardware Design Figure 36Pull out Coaxial Cable Plug 5.4.4.2. Assemble Coaxial Cable Plug with Jig The pictures of installing the coaxial cable plug with a jig is shown below, = 90 OK, 90 NG. Figure 37Install the Coaxial Cable Plug with Jig RM510Q-GL_Hardware_Design 70 / 88 5G Module Series RM510Q-GL Hardware Design 5.4.5. Recommended Manufacturers of RF Connector and Cable For more details, visit https://www.i-pex.com. 5.5. Antenna Requirements Table 43: Cellular Bands Supported by RM510Q-GL Antenna Connectors Antenna Description ANT0 ANT1 ANT2 Antenna0 interface:

5G NR: MHB_TRX & n41 TRX1 & n77/n78/n79_PRx MIMO;

LTE: MHB_TRX & UHB_PRX MIMO WCDMA: MHB_TRX Antenna1 interface:

5G NR: LB_TRX & MHB_DRX MIMO & n41_DRx1

& n77/n78/n79_DRx MIMO LTE: LB_TRX & MHB_DRX MIMO & UHB_DRX MIMO & LAA_PRX WCDMA: LB_TRX Antenna2 interface:

5G NR: LB_DRX & MHB_PRX MIMO & n41 TRX0 & n77/n78/n79 TRX LTE: LB_DRX & MHB_PRX MIMO & UHB_TRX WCDMA: LB_DRX ANT3_ GNSSL1 Antenna3 interface:

5GNR: MHB_DRX & n41 DRX0 & n77/n78/n79_DRX LTE: MHB_DRX & UHB_DRX & LAA_DRX WCDMA: MHB_DRX GNSS: L1 Frequency 14005000 MHz 6006000 MHz 6005000 MHz 14006000 MHz The following table shows the requirements on WCDMA, LTE, 5G NR antenna and GNSS antenna. Table 44: Antenna Requirements Type Requirements WCDMA/LTE/5G NR VSWR: 3 Efficiency: > 30 %

Input Impedance: 50 Cable insertion loss: < 1 dB WCDMA B5/B6/B8/B19 LTE B5/B8/B12(B17)/B13/B14/B18/B19/B20/B26/B28/B29/B71 5G NR n5/n8/n12/n20/n28/n71 Cable insertion loss: < 1.5 dB RM510Q-GL_Hardware_Design 71 / 88 5G Module Series RM510Q-GL Hardware Design WCDMA B1/B2/B3/B4 LTE B1/B2/B3/B4/B25/B32/B34/B39/B66 5G NR n1/n2/n3/n25/n66 Cable insertion loss: < 2 dB LTE B7/B30/B38/B40/B41/B42/B43/B46/B48 5G NR n7/n38/n40/n41/n48/n77/n78/n79 Frequency range: 15591606 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: >0 dBi GNSS RM510Q-GL_Hardware_Design 72 / 88 5G Module Series RM510Q-GL Hardware Design 6 Electrical Characteristics and Reliability 6.1. Power Supply Requirements The typical input voltage of the module is 3.7 V, The following table shows the power supply requirements of the module. Table 45: Power Supply Requirements Parameter Description Min. Typ. Max. Unit VCC Power Supply 3.135 3.7 Voltage Ripple Voltage Drop 30 4.4 100 165 V mV mV 6.2. Current Consumption Table 46: RM510Q-GL Current Consumption Description Conditions OFF state Power off Sleep state AT+CFUN=0 (USB Suspend) WCDMA @DRX =0. 64s, USB Suspend LTE-FDD @DRX = 0.64s, USB Suspend LTE-TDD @DRX = 0.64s, USB Suspend Typ. Unit 82 A 5.11 5.389 5.689 5.803 mA mA mA mA RM510Q-GL_Hardware_Design 73 / 88 5G Module Series RM510Q-GL Hardware Design WCDMA @Paging Frame=64 WCDMA @Paging Frame=64, USB Active Idle state LTE-FDD @DRX=0.64s LTE-FDD @DRX=0.64s, USB Active LTE-TDD @DRX=0.64s LTE-TDD @DRX=0.64s, USB Active WCDMA B1 HSDPA CH10700 @ 23 dBm WCDMA B1 HSUPA CH10700 @ 23 dBm WCDMA B2 HSDPA CH9800 @ 23 dBm WCDMA B2 HSUPA CH9800 @ 23 dBm WCDMA B3 HSDPA CH1338 @ 23 dBm WCDMA B3 HSUPA CH1338 @ 23 dBm WCDMA B4 HSDPA CH1638 @ 23 dBm WCDMA B4 HSUPA CH1638 @ 23 dBm WCDMA B5 HSDPA CH4407 @ 23 dBm WCDMA B5 HSUPA CH4407 @ 23 dBm WCDMA B6 HSDPA CH4400 @ 23 dBm WCDMA B6 HSUPA CH4400 @ 23 dBm WCDMA B8 HSDPA CH3012 @ 23 dBm WCDMA B8 HSUPA CH3012 @ 23 dBm WCDMA B19 HSDPA CH738 @ 23 dBm WCDMA B19 HSUPA CH738 @ 23 dBm WCDMA

(GNSS OFF) LTE

(GNSS OFF) LTE-FDD B1 CH300 @ 23 dBm LTE-FDD B2 CH900 @ 23 dBm LTE-FDD B3 CH1575 @ 23 dBm LTE-FDD B4 CH2175 @ 23 dBm 31.06 52.42 32.93 54.77 32.85 54.56 595 540 650 615 570 545 520 505 430 405 420 415 430 420 420 420 795 715 770 680 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA RM510Q-GL_Hardware_Design 74 / 88 LTE-FDD B5 CH2525 @ 23 dBm LTE-FDD B7 CH3100 @ 23 dBm LTE-FDD B8 CH3625 @ 23 dBm LTE-FDD B12(B17) CH5095 @ 23 dBm LTE-FDD B13 CH5230 @ 23 dBm LTE-FDD B14 CH5330 @ 23 dBm LTE-FDD B18 CH5925 @ 23 dBm LTE-FDD B19 CH6075 @ 23 dBm LTE-FDD B20 CH6300 @ 23 dBm LTE-FDD B25 CH8365 @ 23 dBm LTE-FDD B26 CH8865 @ 23 dBm LTE-FDD B28 CH9435 @ 23 dBm LTE-FDD B30 CH9820 @ 23 dBm LTE-TDD B34 CH36275 @ 23 dBm LTE-TDD B38 CH38000 @ 23 dBm LTE-TDD B39 CH38450 @ 23 dBm LTE-TDD B40 CH39150 @ 23 dBm LTE-TDD B41 CH40620 @ 23 dBm LTE-TDD B42 CH42590 @ 23 dBm LTE-TDD B43 CH44590 @ 23 dBm LTE-TDD B48 CH55990 @ 23 dBm LTE-FDD B66 CH66886 @ 23 dBm LTE-FDD B71 CH68761 @ 23 dBm 5G NR

(GNSS OFF) 5G NR-TDD n41 CH501204 @ 26 dBm 5G NR-TDD n41 CH518598 @ 26 dBm 5G NR-TDD n41 CH535998 @ 26 dBm 5G Module Series RM510Q-GL Hardware Design 485 745 495 485 560 480 515 490 480 695 470 490 860 440 420 380 345 440 460 500 480 765 460 500 500 515 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA RM510Q-GL_Hardware_Design 75 / 88 5G NR-TDD n77 CH620668 @ 26 dBm 5G NR-TDD n77 CH650000 @ 26 dBm 5G NR-TDD n77 CH679332 @ 26 dBm 5G NR-TDD n78 CH620668 @ 26 dBm 5G NR-TDD n78 CH636666 @ 26 dBm 5G NR-TDD n78 CH652666 @ 26 dBm 5G NR-TDD n79 CH695090 @ 26 dBm 5G NR-TDD n79 CH713522 @ 26 dBm 5G NR-TDD n79 CH731976 @ 26 dBm 5G NR-FDD n1 CH423000 @ 23 dBm 5G NR-FDD n1 CH428000 @ 23 dBm 5G NR-FDD n1 CH433000 @ 23 dBm 5G NR-FDD n2 CH387000 @ 23 dBm 5G NR-FDD n2 CH392000 @ 23 dBm 5G NR-FDD n2 CH397000 @ 23 dBm 5G NR-FDD n3 CH362000 @ 23 dBm 5G NR-FDD n3 CH368500 @ 23 dBm 5G NR-FDD n3 CH375000 @ 23 dBm 5G NR-FDD n5 CH174800 @ 23 dBm 5G NR-FDD n5 CH176300 @ 23 dBm 5G NR-FDD n5 CH177800 @ 23 dBm 5G NR-FDD n7 CH525000 @ 23 dBm 5G NR-FDD n7 CH531000 @ 23 dBm 5G NR-FDD n7 CH537000 @ 23 dBm 5G NR-FDD n8 CH186000 @ 23 dBm 5G NR-FDD n8 CH188500 @ 23 dBm 5G Module Series RM510Q-GL Hardware Design 500 500 520 500 530 500 550 550 530 950 880 930 610 740 610 780 780 870 515 510 510 690 690 670 550 520 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA RM510Q-GL_Hardware_Design 76 / 88 5G NR-FDD n8 CH191000 @ 23 dBm 5G NR-FDD n12 CH146800 @ 23 dBm 5G NR-FDD n12 CH147500 @ 23 dBm 5G NR-FDD n12 CH148200 @ 23 dBm 5G NR-FDD n20 CH159200 @ 23 dBm 5G NR-FDD n20 CH161200 @ 23 dBm 5G NR-FDD n20 CH163200 @ 23 dBm 5G NR-FDD n25 CH387000 @ 23 dBm 5G NR-FDD n25 CH392500 @ 23 dBm 5G NR-FDD n25 CH398000 @ 23 dBm 5G NR-FDD n28 CH152600 @ 23 dBm 5G NR-FDD n28 CH156100 @ 23 dBm 5G NR-FDD n28 CH159600 @ 23 dBm 5G NR-TDD n38 CH515000 @ 23 dBm 5G NR-TDD n38 CH519000 @ 23 dBm 5G NR-TDD n38 CH523000 @ 23 dBm 5G NR-TDD n40 CH461000 @ 23 dBm 5G NR-TDD n40 CH470000 @ 23 dBm 5G NR-TDD n40 CH479000 @ 23 dBm 5G NR-TDD n48 CH637000 @ 23 dBm 5G NR-TDD n48 CH641667 @ 23 dBm 5G NR-TDD n48 CH646333@ 23 dBm 5G NR-FDD n66 CH423000 @ 23 dBm 5G NR-FDD n66 CH429000 @ 23 dBm 5G NR-FDD n66 CH435000 @ 23 dBm 5G NR-FDD n71 CH124400 @ 23 dBm 5G Module Series RM510Q-GL Hardware Design 520 480 480 480 480 480 490 640 750 680 550 560 530 310 310 310 580 580 580 420 420 410 790 880 850 500 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA RM510Q-GL_Hardware_Design 77 / 88 5G Module Series RM510Q-GL Hardware Design 5G NR-FDD n71 CH126900 @ 23 dBm 5G NR-FDD n71 CH129400 @ 23 dBm WCDMA B1 CH10700 @ 23 dBm WCDMA B2 CH9800 @ 23 dBm WCDMA B3 CH1338 @ 23 dBm WCDMA voice call*

WCDMA B4 CH1638 @ 23 dBm WCDMA B5 CH4408 @ 23 dBm WCDMA B6 CH4175 @ 23 dBm WCDMA B8 CH3012 @ 23 dBm WCDMA B19 CH338 @ 23 dBm 480 490 670 730 650 600 460 460 475 460 mA mA mA mA mA mA mA mA mA mA 6.3. Digital I/O Characteristic Table 47: Logic Levels of Digital I/O (1.8 V) Parameter Description VIH VIL VOH VOL Min. 1.65

-0.3 1.3 Input high voltage Input low voltage Output high voltage Output low voltage 0 Max. 2.1 0.54 1.8 0.4 Unit V V V V Table 48: (U)SIM 1.8 V I/O Requirements Parameter Description USIM_VDD Power supply Min. 1.65 Max. 1.95 Unit V VIH Input high voltage 0.7 USIM_VDD USIM_VDD + 0.3 V RM510Q-GL_Hardware_Design 78 / 88 V V Unit V 5G Module Series RM510Q-GL Hardware Design Input low voltage

-0.3 0.2 USIM_VDD V Output high voltage 0.8 USIM_VDD USIM_VDD Output low voltage 0 0.4 VIL VOH VOL Table 49: (U)SIM 3.0 V I/O Requirements Parameter Description USIM_VDD Power supply Min. 2.7 Max. 3.05 VIH VIL VOH VOL Input high voltage 0.7 USIM_VDD USIM_VDD + 0.3 V Input low voltage

-0.3 0.2 USIM_VDD V Output high voltage 0.8 USIM_VDD USIM_VDD Output low voltage 0 0.4 V V 6.4. Electrostatic Discharge The module is not protected against electrostatic discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. Table 50: Electrostatic Discharge Characteristics (Temperature: 25 C, Humidity: 40 %) Tested Interfaces Contact Discharge Air Discharge Unit VCC, GND Antenna Interfaces 5 4 Other Interfaces 0.5 10 8 1 kV kV kV 6.5. Thermal Dissipation RM510Q-GL are designed to work over an extended temperature range. To achieve a maximum RM510Q-GL_Hardware_Design 79 / 88 5G Module Series RM510Q-GL Hardware Design performance while working under extended temperatures or extreme conditions (such as with maximum power or data rate) for a long time, it is strongly recommended to add a thermal pad or other thermally conductive compounds between the module and the main PCB for thermal dissipation. The thermal dissipation area on the bottom (i.e. the area for adding thermal pad) is shown as below, and conductive compounds are also added on the BB, MCP, PMU, WTR, PA-1, PA-2 chips inside the module. The dimensions are measured in mm. Figure 38: Thermal Dissipation Area on Bottom Side of Module There are other measures to enhance heat dissipation performance:

Add ground vias as many as possible on PCB. Maximize airflow over/around the module. Place the module away from other heating sources. Module mounting holes must be used to attach (ground) the device to the main PCB ground. It is NOT recommended to apply solder mask on the main PCB where the modules thermal dissipation area is located. Select appropriate material, thickness and surface for the outer housing of the application device that integrates the module (i.e. the mechanical enclosure) to enhance thermal dissipation ability. Customers may also need active cooling to dissipate heat of the module. If possible, add a heatsink on the top of the module. A thermal pad should be used between the RM510Q-GL_Hardware_Design 80 / 88 5G Module Series RM510Q-GL Hardware Design heatsink and the module, and the heatsink should be designed with as many fins as possible to increase heat dissipation area. NOTE If a conformal coating is necessary for the module, do NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module. 6.6. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 51: Absolute Maximum Ratings Parameter VCC Voltage at Digital Pins Min.

-0.3

-0.3 Typ. Max. Unit 4.7 2.3 V V 6.7. Operating and Storage Temperatures Table 52: Operating and Storage Temperatures Parameter Min. Operating Temperature Range1)

-30 Extended Temperature Range2)

-40 Storage temperature Range

-40 Typ.

+25

Max. Unit

+70

+85

+90 C C C NOTES 1. 1) To meet this operating temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, RM510Q-GL_Hardware_Design 81 / 88 5G Module Series RM510Q-GL Hardware Design the module meets 3GPP specifications. 2. 2) To meet this extended temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module remains the ability to establish and maintain functions such as voice, SMS, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may undergo a reduction in value, exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again. RM510Q-GL_Hardware_Design 82 / 88 5G Module Series RM510Q-GL Hardware Design 7 Mechanical Dimensions and Packaging This chapter mainly describes mechanical dimensions and packaging specifications of RM510Q-GL. All dimensions are measured in mm, and the tolerances are 0.05 mm unless otherwise specified. 7.1. Mechanical Dimensions of the Module Figure 39: Mechanical Dimensions of the Module (Unit: mm) NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. RM510Q-GL_Hardware_Design 83 / 88 7.2. Top and Bottom Views of the Module 5G Module Series RM510Q-GL Hardware Design Figure 40: RM510Q-GL Top View and Bottom View 7.3. M.2 Connector The module adopts a standard PCI Express M.2 connector which compiles with the directives and standards listed in PCI Express M.2 Specification Rev3.0. 7.4. Packaging The modules are packaged in trays. The following figure shows the tray size. RM510Q-GL_Hardware_Design 84 / 88 TOP VIEWBOT VIEW 5G Module Series RM510Q-GL Hardware Design Figure 41: Tray Size (Unit: mm) Each tray contains 10 modules. The smallest package contains 100 modules. Tray packaging procedures are as below. 1. Use 10 trays to package 100 modules at a time (tray size: 247 mm 172 mm). 2. Place an empty tray on the top of the 10-tray stack. 3. Fix the stack with masking tape in # shape as shown in the following figure. 4. Pack the stack with conductive bag, and then fix the bag with masking tape. 5. Place the list of IMEI No. into a small carton. 6. Seal the carton and then label the seal with sealing sticker (small carton size: 250 mm 175 mm 128 mm). Figure 42: Tray Packaging Procedure RM510Q-GL_Hardware_Design 85 / 88 5G Module Series RM510Q-GL Hardware Design 8 Appendix References Table 53: Related Documents SN. Document Name Description

[1]

Quectel_RM510Q-GL_CA&EN-DC_Features

[2]

Quectel_5G-mmWave_EVB_LP(525)_User_Guide

[3]

Quectel_5G-mmWave_EVB_HP(527)_User_Guide CA&EN-DC combinations of RM510Q-GL RM510Q-GL EVB user guide

(QTM525) RM510Q-GL EVB user guide

(QTM527)

[4]

[5]

Quectel_RG50xQ&RM5xxQ_Series_AT_Commands_ Manual AT commands manual for RG50xQ, RM5xxQ series Quectel_RG50xQ&RM5xxQ_Series_GNSS_ Application_Note The GNSS application note for RG50xQ and RM5xxQ series Table 54: Terms and Abbreviations Abbreviation Description BIOS bps CPE CSQ Basic Input Output System Bit Per Second Customer Premise Equipment Cellular Signal Quality DFOTA Delta Firmware Upgrade Over-The-Air DL DPR EIRP ESD Downlink Dynamic Power Reduction Equivalent Isotropically Radiated Power Electrostatic Discharge RM510Q-GL_Hardware_Design 86 / 88 5G Module Series RM510Q-GL Hardware Design ET FDD FR2 Envelope tracking Frequency Division Duplexing Frequency Range 2 GLONASS Global Navigation Satellite System (Russia) GNSS GPS GSM HSPA Global Navigation Satellite System Global Positioning System Global System for Mobile Communications High Speed Packet Access HSUPA High Speed Uplink Packet Access IF kbps LAA LED LO LTE Mbps ME MIMO MLCC MMS Intermediate Frequency Kilo Bits Per Second License Assisted Access Light Emitting Diode Local Oscillator Long Term Evolution Mega Bits Per Second Mobile Equipment Multiple-Input Multiple-Output Multilayer Ceramic Chip Capacitor Multimedia Messaging Service mmWave Millimeter wave MO MSB MT PAP Mobile Originated Most Significant Bit Mobile Terminated Password Authentication Protocol RM510Q-GL_Hardware_Design 87 / 88 5G Module Series RM510Q-GL Hardware Design PCB PCIe PCM PDU PPP RF RFFE RFIC Rx SAR SCS SMS TCP Tx UART UDP UL URC USB Printed Circuit Board Peripheral Component Interconnect Express Pulse Code Modulation Protocol Data Unit Point-to-Point Protocol Radio Frequency RF Front-End Radio-frequency Integrated Circuit Receive Specific Absorption Rate Sub-carrier Spacing Short Message Service Transmission Control Protocol Transmit Universal Asynchronous Receiver & Transmitter User Datagram Protocol Uplink Unsolicited Result Code Universal Serial Bus

(U)SIM

(Universal) Subscriber Identity Module VIH VIL VOH VOL Input High Voltage Level Input Low Voltage Level Output High Voltage Level Output Low Voltage Level VSWR Voltage Standing Wave Ratio RM510Q-GL_Hardware_Design 88 / 88 WCDMA Wideband Code Division Multiple Access 5G Module Series RM510Q-GL Hardware Design RM510Q-GL_Hardware_Design 89 / 88 OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.31 (h) and (k): The host manufacturer is responsible for additional testing to verify compliance as a composite system. When testing the host device for compliance with Part 15 Subpart B, the host manufacturer is required to show compliance with Part 15 Subpart B while the transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation should confirm that the module's intentional emissions are compliant (i.e. fundamental and out of band emissions). The host manufacturer must verify that there are no additional unintentional emissions other than what is permitted in Part 15 Subpart B or emissions are complaint with the transmitter(s) rule(s). The Grantee will provide guidance to the host manufacturer for Part 15 B requirements if needed. Important Note notice that any deviation(s) from the defined parameters of the antenna trace, as described by the instructions, require that the host product manufacturer must notify to Quectel that they wish to change the antenna trace design. In this case, a Class II permissive change application is required to be filed by the USI, or the host manufacturer can take responsibility through the change in FCC ID (new application) procedure followed by a Class II permissive change application End Product Labeling When the module is installed in the host device, the FCC/IC ID label must be visible through a window on the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a second label must be placed on the outside of the final device that contains the following text: Contains FCC ID: XMR2020RM510QGL Contains IC: XMR2020RM510QGL. The FCC ID/IC ID can be used only when all FCC/IC compliance requirements are met. Antenna

(1) The antenna must be installed such that 20 cm is maintained between the antenna and users,

(2) The transmitter module may not be co-located with any other transmitter or antenna. In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC/IC authorization. To comply with FCC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed Test Mode Antenna Gain (dBi) Test Mode Antenna Gain (dBi) WCDMA B2 WCDMA B4 WCDMA B5 LTE B2 LTE B4 LTE B5 LTE B7 LTE B12 LTE B13 LTE B14 LTE B17 LTE B25 LTE B26 LTE B30 8.00 5.00 5.00 8.00 5.00 5.00 8.00 5.00 5.00 5.00 5.00 8.00 5.00

-1.02*

LTE B38 LTE B41 LTE B48 LTE B66 LTE B71 n2 n5 n7 n12 n25 n41 n66 n71 n77 2.00 2.00

-2.00*

5.00 5.00 8.00 5.00 8.00 5.00 8.00 5.00 5.00 5.00 5.00 Note: * means when using higher gain antenna, the host manufacturer should reduce the conducted power to meet the FCC maximum RF output power limit. Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:

- Reorient or relocate the receiving antenna.

- Increase the separation between the equipment and receiver

- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

- Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. List of applicable FCC rules This module has been tested and found to comply with part 22, part 24, part 27, part 90 requirements for Modular Approval. The modular transmitter is only FCC authorized for the specific rule parts (i.e., FCC transmitter rules) listed on the grant, and that the host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. If the grantee markets their product as being Part 15 Subpart B compliant (when it also contains unintentional-

radiator digital circuity), then the grantee shall provide a notice stating that the final host product still requires Part 15 Subpart B compliance testing with the modular transmitter installed. This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. Radiation Exposure Statement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator &

your body. Industry Canada Statement This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions:

(1) This device may not cause interference; and

(2) This device must accept any interference, including interference that may cause undesired operation of the device. Le prsent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorise aux deux conditions suivantes:

(1) l'appareil ne doit pas produire de brouillage, et

(2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement."

Radiation Exposure Statement This equipment complies with IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator & your body Dclaration d'exposition aux radiations:

Cet quipement est conforme aux limites d'exposition aux rayonnements ISED tablies pour un environnement non contrl. Cet quipement doit tre install et utilis avec un minimum de 20 cm de distance entre la source de rayonnement et votre corps. This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. Cet appareil est conu uniquement pour les intgrateurs OEM dans les conditions suivantes: (Pour utilisation de dispositif module) 1) L'antenne doit tre installe de telle sorte qu'une distance de 20 cm est respecte entre l'antenne et les utilisateurs, et 2) Le module metteur peut ne pas tre complant avec un autre metteur ou antenne. Tant que les 2 conditions ci-dessus sont remplies, des essais supplmentaires sur l'metteur ne seront pas ncessaires. Toutefois, l'intgrateur OEM est toujours responsable des essais sur son produit final pour toutes exigences de conformit supplmentaires requis pour ce module install. IMPORTANT NOTE:

In the event that these conditions cannot be met (for example certain laptop configurations or colocation with another transmitter), then the Canada authorization is no longer considered valid and the IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate Canada authorization. NOTE IMPORTANTE:

Dans le cas o ces conditions ne peuvent tre satisfaites (par exemple pour certaines configurations d'ordinateur portable ou de certaines co-localisation avec un autre metteur), l'autorisation du Canada n'est plus considr comme valide et l'ID IC ne peut pas tre utilis sur le produit final. Dans ces circonstances, l'intgrateur OEM sera charg de rvaluer le produit final (y compris l'metteur) et l'obtention d'une autorisation distincte au Canada. End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed such that 20 cm may be maintained between the antenna and users. The final end product must be labeled in a visible area with the following: Contains IC: 10224A-2021AG521R. Plaque signaltique du produit final Ce module metteur est autoris uniquement pour une utilisation dans un dispositif o l'antenne peut tre installe de telle sorte qu'une distance de 20cm peut tre maintenue entre l'antenne et les utilisateurs. Le produit final doit tre tiquet dans un endroit visible avec l'inscription suivante: "Contient des IC: 10224A-2021RM510GL". Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. Manuel d'information l'utilisateur final L'intgrateur OEM doit tre conscient de ne pas fournir des informations l'utilisateur final quant la faon d'installer ou de supprimer ce module RF dans le manuel de l'utilisateur du produit final qui intgre ce module. Le manuel de l'utilisateur final doit inclure toutes les informations rglementaires requises et avertissements comme indiqu dans ce manuel.