FCC ID: XMR202002EG18NA LTE-A Cat 18 LGA Module

 

EG18 Hardware Design LTE-A Module Series Rev. EG18_Hardware_Design_V1.1 Date: 2019-12-21 Status: Released www.quectel.com LTE-A Module Series EG18 Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters:

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http://www.quectel.com/support/technical.htm Or Email to: support@quectel.com GENERAL NOTES QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION PROVIDED IS BASED UPON CUSTOMERS REQUIREMENTS. QUECTEL MAKES EVERY EFFORT TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR RELIANCE UPON THE INFORMATION. ALL INFORMATION SUPPLIED HEREIN IS SUBJECT TO CHANGE WITHOUT PRIOR NOTICE. COPYRIGHT THE INFORMATION CONTAINED HERE IS PROPRIETARY TECHNICAL INFORMATION OF QUECTEL WIRELESS SOLUTIONS CO., LTD. TRANSMITTING, REPRODUCTION, DISSEMINATION AND EDITING OF THIS DOCUMENT AS WELL AS UTILIZATION OF THE CONTENT ARE FORBIDDEN WITHOUT PERMISSION. OFFENDERS WILL BE HELD LIABLE FOR PAYMENT OF DAMAGES. ALL RIGHTS ARE RESERVED IN THE EVENT OF A PATENT GRANT OR REGISTRATION OF A UTILITY MODEL OR DESIGN. Copyright Quectel Wireless Solutions Co., Ltd. 2019. All rights reserved EG18_Hardware_Design 1 / 104 LTE-A Module Series EG18 Hardware Design About the Document History Revision Date Author Description 1.0 2019-07-25 Initial Oscar LIU/

Xavier XIA 1.1 2019-12-21 Archibald JIANG/

Xavier XIA 1. Updated the current consumption and sensitivity data of EG18-NA;

2. Updated the timing information of powering on, in powering off, resetting, (U)SIM and USB Chapter 3;

3. Added description about the the temperature sensors corresponding temperatures obtained with AT+QTEMP command in Chapter 6.8. the position of to EG18_Hardware_Design 2 / 104 LTE-A Module Series EG18 Hardware Design Contents About the Document ................................................................................................................................... 2 Contents ....................................................................................................................................................... 3 Table Index ................................................................................................................................................... 6 Figure Index ................................................................................................................................................. 8 1 Introduction ........................................................................................................................................ 10 1.1. Safety Information.................................................................................................................... 11 2 Product Concept ................................................................................................................................ 12 2.1. General Description ................................................................................................................. 12 Key Features ........................................................................................................................... 14 2.2. 2.3. Functional Diagram ................................................................................................................. 16 Evaluation Board ..................................................................................................................... 17 2.4. 3.5. 3 Application Interfaces ....................................................................................................................... 18 Pin Assignment ........................................................................................................................ 19 3.1. 3.2. Pin Description ......................................................................................................................... 20 3.3. Operating Modes ..................................................................................................................... 31 Power Saving ........................................................................................................................... 32 3.4. 3.4.1. Sleep Mode .................................................................................................................... 32 3.4.1.1. UART Application ................................................................................................. 32 3.4.1.2. USB Application with USB Remote Wakeup Function ........................................ 33 3.4.1.3. USB Application with USB Suspend/Resume and RI Function .......................... 34 3.4.1.4. USB Application without USB Suspend Function ................................................ 34 3.4.2. Airplane Mode ................................................................................................................ 35 Power Supply ........................................................................................................................... 36 3.5.1. Power Supply Pins ......................................................................................................... 36 3.5.2. Decrease Voltage Drop .................................................................................................. 37 3.5.3. Reference Design for Power Supply .............................................................................. 38 3.5.4. Monitor the Power Supply .............................................................................................. 38 Turn on and off Scenarios ....................................................................................................... 39 3.6.1. Turn on the Module Through PWRKEY ......................................................................... 39 3.6.2. Turn off the Module ........................................................................................................ 41 3.6.2.1. Turn off the Module Through PWRKEY .............................................................. 41 3.6.2.2. Turn off the Module Through AT Command ........................................................ 41 3.7. Reset the Module..................................................................................................................... 42 3.8.

(U)SIM Interfaces..................................................................................................................... 44 3.9. USB Interface .......................................................................................................................... 47 3.10. UART Interfaces ...................................................................................................................... 50 3.10.1. Main UART Interface ...................................................................................................... 50 3.10.2. Debug UART Interface ................................................................................................... 51 3.10.3. BT UART Interface ......................................................................................................... 51 3.10.4. UART Application ........................................................................................................... 51 3.6. EG18_Hardware_Design 3 / 104 LTE-A Module Series EG18 Hardware Design 3.11. SPI Interface* ........................................................................................................................... 53 3.12. PCM and I2C Interfaces .......................................................................................................... 55 3.13. ADC Interfaces ........................................................................................................................ 57 3.14. Network Status Indication ........................................................................................................ 58 3.15. Operation Status Indication ..................................................................................................... 60 3.16. RI Behaviors ............................................................................................................................ 60 3.17. PCIe Interface* ........................................................................................................................ 61 3.17.1. Root Complex Mode ...................................................................................................... 63 3.17.2. Endpoint Mode ............................................................................................................... 64 3.18. SDIO Interface* ........................................................................................................................ 65 3.19. Antenna Tuner Control Interfaces* .......................................................................................... 67 3.20. USB_BOOT Interface .............................................................................................................. 68 3.21. GPIOs ...................................................................................................................................... 69 4 GNSS Receiver ................................................................................................................................... 70 4.1. General Description ................................................................................................................. 70 4.2. GNSS Performance ................................................................................................................. 70 Layout Guidelines .................................................................................................................... 71 4.3. 5 Antenna Interfaces ............................................................................................................................. 72 5.1. Main/Rx-diversity/MIMO Antenna Interfaces ........................................................................... 72 5.1.1. Pin Definition .................................................................................................................. 72 5.1.2. Operating Frequencies................................................................................................... 72 5.1.3. Reference Design of RF Antenna Interfaces ................................................................. 74 5.2. GNSS Antenna Interface ......................................................................................................... 75 5.2.1. Pin Definition .................................................................................................................. 75 5.2.2. GNSS Frequency ........................................................................................................... 75 5.2.3. Reference Design of GNSS Antenna Interface ............................................................. 76 5.3. Reference Design of RF Layout .............................................................................................. 77 5.4. Antenna Installation ................................................................................................................. 78 5.4.1. Antenna Requirements .................................................................................................. 78 5.4.2. Recommended RF Connector for Antenna Installation ................................................. 79 6 Electrical, Reliability and Radio Characteristics ............................................................................ 81 Absolute Maximum Ratings ..................................................................................................... 81 6.1. 6.2. Power Supply Ratings ............................................................................................................. 82 6.3. Operation and Storage Temperatures .................................................................................... 82 6.4. Current Consumption .............................................................................................................. 83 6.4.1. EG18-EA Current Consumption..................................................................................... 83 6.4.2. EG18-NA Current Consumption .................................................................................... 85 6.5. RF Output Power ..................................................................................................................... 87 6.6. RF Receiving Sensitivity .......................................................................................................... 87 6.6.1. EG18-EA Receiving Sensitivity ...................................................................................... 87 6.6.2. EG18-NA Receiving Sensitivity ...................................................................................... 88 Electrostatic Discharge ............................................................................................................ 89 Thermal Considerations .......................................................................................................... 89 6.7. 6.8. EG18_Hardware_Design 4 / 104 LTE-A Module Series EG18 Hardware Design 7 Mechanical Dimensions .................................................................................................................... 93 7.1. Mechanical Dimensions of the Module.................................................................................... 93 7.2. Recommended Footprint ......................................................................................................... 95 7.3. Design Effect Drawings of the Module .................................................................................... 96 8 Storage, Manufacturing and Packaging .......................................................................................... 97 8.1. Storage .................................................................................................................................... 97 8.2. Manufacturing and Soldering .................................................................................................. 98 Packaging ................................................................................................................................ 99 8.3. 9 Appendix A References ................................................................................................................... 101 EG18_Hardware_Design 5 / 104 LTE-A Module Series EG18 Hardware Design Table Index TABLE 1: FREQUENCY BANDS, CA COMBINATIONS AND GNSS TYPES OF EG18 MODULE................. 12 TABLE 2: KEY FEATURES OF EG18 ............................................................................................................... 14 TABLE 3: I/O PARAMETERS DEFINITION ...................................................................................................... 20 TABLE 4: PIN DESCRIPTION ........................................................................................................................... 20 TABLE 5: OVERVIEW OF OPERATING MODES ............................................................................................ 31 TABLE 6: RF FUNCTION STATUS AND RELEVANT AT COMMANDS .......................................................... 35 TABLE 7: VBAT AND GND PINS ...................................................................................................................... 36 TABLE 8: PWRKEY PIN DESCRIPTION .......................................................................................................... 39 TABLE 9: RESET_N PIN DESCRIPTION ......................................................................................................... 42 TABLE 10: PIN DEFINITION OF THE (U)SIM INTERFACES .......................................................................... 44 TABLE 11: PIN DEFINITION OF USB INTERFACE ......................................................................................... 47 TABLE 12: PIN DEFINITION OF MAIN UART INTERFACE ............................................................................ 50 TABLE 13: PIN DEFINITION OF DEBUG UART INTERFACE......................................................................... 51 TABLE 14: PIN DEFINITION OF THE BT UART INTERFACE......................................................................... 51 TABLE 15: LOGIC LEVELS OF DIGITAL I/O ................................................................................................... 51 TABLE 16: PIN DEFINITION OF SPI INTERFACE .......................................................................................... 53 TABLE 17: PARAMETERS OF SPI INTERFACE TIMING ............................................................................... 54 TABLE 18: PIN DEFINITION OF PCM INTERFACE AND I2C INTERFACE ................................................... 56 TABLE 19: PIN DEFINITION OF THE ADC INTERFACES .............................................................................. 58 TABLE 20: CHARACTERISTICS OF ADC INTERFACES ................................................................................ 58 TABLE 21: PIN DEFINITION OF NETWORK STATUS/ACTIVITY INDICATOR .............................................. 58 TABLE 22: WORKING STATE OF THE NETWORK STATUS/ACTIVITY INDICATOR ................................... 59 TABLE 23: PIN DEFINITION OF STATUS........................................................................................................ 60 TABLE 24: RI BEHAVIORS ............................................................................................................................... 61 TABLE 25: PIN DEFINITION OF THE PCIE INTERFACE ................................................................................ 61 TABLE 26: PIN DEFINITION OF SDIO INTERFACE ....................................................................................... 65 TABLE 27: PIN DEFINITION OF RFFE INTERFACE USED TO CONTROL ANTENNA TUNER ................... 67 TABLE 28: PIN DEFINITION OF GPIO INTERFACE USED TO CONTROL ANTENNA TUNER .................... 67 TABLE 29: PIN DEFINITION OF USB_BOOT INTERFACE ............................................................................. 68 TABLE 30: PIN DEFINITION OF GPIOS .......................................................................................................... 69 TABLE 31: GNSS PERFORMANCE ................................................................................................................. 70 TABLE 32: PIN DEFINITION OF THE MAIN/RX-DIVERSITY/MIMO ANTENNA INTERFACES ..................... 72 TABLE 33: EG18-EA OPERATING FREQUENCIES ........................................................................................ 72 TABLE 34: EG18-NA OPERATING FREQUENCIES ....................................................................................... 73 TABLE 35: PIN DEFINITION OF GNSS ANTENNA INTERFACE .................................................................... 75 TABLE 36: GNSS FREQUENCY ...................................................................................................................... 75 TABLE 37: ANTENNA REQUIREMENTS ......................................................................................................... 78 TABLE 38: ABSOLUTE MAXIMUM RATINGS ................................................................................................. 81 TABLE 39: THE MODULES POWER SUPPLY RATINGS .............................................................................. 82 TABLE 40: OPERATION AND STORAGE TEMPERATURES ......................................................................... 82 TABLE 41: EG18-EA CURRENT CONSUMPTION .......................................................................................... 83 EG18_Hardware_Design 6 / 104 LTE-A Module Series EG18 Hardware Design TABLE 42: EG18-NA CURRENT CONSUMPTION .......................................................................................... 85 TABLE 43: RF OUTPUT POWER ..................................................................................................................... 87 TABLE 44: EG18-EA CONDUCTED RF RECEIVING SENSITIVITY ............................................................... 87 TABLE 45: EG18-NA CONDUCTED RF RECEIVING SENSITIVITY ............................................................... 88 TABLE 46: ELECTROSTATIC DISCHARGE CHARACTERISTICS ................................................................. 89 TABLE 47: RECOMMENDED THERMAL PROFILE PARAMETERS .............................................................. 98 TABLE 48: RELATED DOCUMENTS ............................................................................................................. 101 TABLE 49: TERMS AND ABBREVIATIONS ................................................................................................... 101 EG18_Hardware_Design 7 / 104 LTE-A Module Series EG18 Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 16 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 19 FIGURE 3: DRX RUN TIME AND CURRENT CONSUMPTION IN SLEEP MODE ......................................... 32 FIGURE 4: SLEEP MODE APPLICATION VIA UART INTERFACES .............................................................. 33 FIGURE 5: SLEEP MODE APPLICATION WITH USB REMOTE WAKEUP .................................................... 33 FIGURE 6: SLEEP MODE APPLICATION WITH RI ......................................................................................... 34 FIGURE 7: SLEEP MODE APPLICATION WITHOUT SUSPEND FUNCTION................................................ 35 FIGURE 8: POWER SUPPLY LIMITS DURING TX POWER ........................................................................... 37 FIGURE 9: STAR STRUCTURE OF THE POWER SUPPLY ........................................................................... 37 FIGURE 10: REFERENCE CIRCUIT OF POWER SUPPLY ............................................................................ 38 FIGURE 11: TURN ON THE MODULE WITH A DRIVING CIRCUIT ............................................................... 39 FIGURE 12: TURN ON THE MODULE USING A BUTTON ............................................................................. 40 FIGURE 13: TIMING OF TURNING ON THE MODULE ................................................................................... 40 FIGURE 14: TIMING OF TURNING OFF THE MODULE ................................................................................. 41 FIGURE 15: REFERENCE CIRCUIT OF RESET_N WITH A DRIVING CIRCUIT ........................................... 42 FIGURE 16: REFERENCE CIRCUIT OF RESET_N WITH A BUTTON ........................................................... 43 FIGURE 17: TIMING OF RESETTING THE MODULE ..................................................................................... 43 FIGURE 18: REFERENCE CIRCUIT OF A (U)SIM INTERFACE WITH AN 8-PIN (U)SIM CARD CONNECTOR

................................................................................................................................................................... 45 FIGURE 19: REFERENCE CIRCUIT OF A (U)SIM INTERFACE WITH A 6-PIN (U)SIM CARD CONNECTOR

................................................................................................................................................................... 45 FIGURE 20: TIMING OF (U)SIM ....................................................................................................................... 46 FIGURE 21: TIMING OF HOT-PLUG ................................................................................................................ 46 FIGURE 22: REFERENCE CIRCUIT OF USB APPLICATION ......................................................................... 48 FIGURE 23: TIMING OF USB ENUMERATION ............................................................................................... 49 FIGURE 24: LEVEL TRANSLATION REFERENCE CIRCUIT WITH AN IC ..................................................... 52 FIGURE 25: LEVEL TRANSLATION REFERENCE CIRCUIT WITH MOSFETS ............................................. 53 FIGURE 26: TIMING OF SPI INTERFACE ....................................................................................................... 54 FIGURE 27: PRIMARY MODE TIMING ............................................................................................................ 55 FIGURE 28: AUXILIARY MODE TIMING .......................................................................................................... 56 FIGURE 29: REFERENCE CIRCUIT OF PCM APPLICATION WITH AUDIO CODEC ................................... 57 FIGURE 30: REFERENCE CIRCUIT OF THE NETWORK INDICATOR ......................................................... 59 FIGURE 31: REFERENCE CIRCUITS OF STATUS ........................................................................................ 60 FIGURE 32: PCIE INTERFACE REFERENCE CIRCUIT (RC MODE) ............................................................. 63 FIGURE 33: PCIE INTERFACE REFERENCE CIRCUIT (EP MODE) ............................................................. 64 FIGURE 34: REFERENCE CIRCUIT OF SD CARD APPLICATION ................................................................ 66 FIGURE 35: REFERENCE CIRCUIT OF USB_BOOT INTERFACE ................................................................ 68 FIGURE 36: REFERENCE CIRCUIT OF RF ANTENNA INTERFACES .......................................................... 74 FIGURE 37: REFERENCE CIRCUIT OF GNSS ANTENNA INTERFACE ....................................................... 76 FIGURE 38: MICROSTRIP DESIGN ON A 2-LAYER PCB .............................................................................. 77 FIGURE 39: COPLANAR WAVEGUIDE DESIGN ON A 2-LAYER PCB .......................................................... 77 EG18_Hardware_Design 8 / 104 LTE-A Module Series EG18 Hardware Design FIGURE 40: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE GROUND)

................................................................................................................................................................... 77 FIGURE 41: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE GROUND)

................................................................................................................................................................... 78 FIGURE 42: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) ............................................... 79 FIGURE 43: MECHANICALS OF U.FL-LP CONNECTORS ............................................................................. 80 FIGURE 44: SPACE FACTOR OF MATING PLUGS (UNIT: MM) .................................................................... 80 FIGURE 45: REFERENCE DESIGN OF HEATSINK (HEATSINK AT THE TOP OF THE MODULE) ............. 90 FIGURE 46: REFERENCE DESIGN OF HEATSINK (HEATSINK AT THE BACKSIDE OF PCB) ................... 90 FIGURE 47: RESPONSE OF AT+QTEMP ....................................................................................................... 91 FIGURE 48: TEMPERATURE SENSOR DISTRIBUTION ................................................................................ 92 FIGURE 49: MODULE TOP AND SIDE DIMENSIONS (UNIT: MM) ................................................................ 93 FIGURE 50: MODULE BOTTOM DIMENSIONS (TOP VIEW, UNIT: MM) ....................................................... 94 FIGURE 51: RECOMMENDED FOOTPRINT (TOP VIEW, UNIT: MM) ........................................................... 95 FIGURE 52: TOP VIEW OF THE MODULE ...................................................................................................... 96 FIGURE 53: BOTTOM VIEW OF THE MODULE .............................................................................................. 96 FIGURE 54: REFLOW SOLDERING THERMAL PROFILE .............................................................................. 98 FIGURE 55: TAPE SPECIFICATIONS (UNIT: MM) .......................................................................................... 99 FIGURE 56: REEL SPECIFICATIONS (UNIT: MM) ........................................................................................ 100 EG18_Hardware_Design 9 / 104 LTE-A Module Series EG18 Hardware Design 1 Introduction This document defines EG18 module and describes its air interface and hardware interfaces which are connected to customers applications. This document helps customers quickly understand interface specifications, electrical and mechanical details, as well as other related technical information of EG18 module. Associated with relevant application notes and user guides, the module will be used to design and set up mobile applications easily. EG18_Hardware_Design 10 / 104 LTE-A Module Series EG18 Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating EG18 module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals supplied with the product. If not so, Quectel assumes no liability for any users failure to observe these precautions. Full attention must be paid to driving at all times in order to reduce the risk of accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on aircraft. Wireless devices may cause interference with sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signals and cellular network cannot be guaranteed to connect in all possible conditions (for example, with unpaid bills or with an invalid (U)SIM card). When emergent help is needed in such conditions, please remember to use emergency call. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it receives and transmits radio frequency signals. RF interference may occur if it is used close to TV set, radio, computer or other electric equipment. In locations with potentially explosive atmospheres, obey all posted signs to turn off wireless devices such as mobile phone or other cellular terminals. Areas with potentially explosive atmospheres include fueling areas, below decks on boats, fuel or chemical transfer or storage facilities, areas where the air contains chemicals or particles such as grain, dust or metal powders, etc. EG18_Hardware_Design 11 / 104 LTE-A Module Series EG18 Hardware Design 2 Product Concept 2.1. General Description EG18 is a series LTE-FDD/LTE-TDD/WCDMA wireless communication module with diversity reception. It provides data connectivity on LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA, and WCDMA networks. EG18 supports embedded operating systems such as Windows, Linux and Android. It also provides GNSS 1) and voice functionality 2) to meet specific application demands. The module comprises two variants: EG18-EA and EG18-NA. Customers can choose a dedicated variant based on the region or operator. The following table shows the frequency bands, CA combinations 3) and GNSS types of EG18 module. Table 1: Frequency Bands, CA Combinations and GNSS Types of EG18 Module Mode EG18-EA EG18-NA LTE-FDD

(with Rx-diversity) LTE-TDD

(with Rx-diversity) 2CA (DL) B1/B3/B5/B7/B8/B20/B28 B2/B4/B5/B7/B12/B13/B14/B25/B26/

B29 4)/B30/B66/B71 B38/B40/B41 B41 B1+B1/B3/B5/B7/B8/B20/B28/B38/B40/

B41;

B3+B3/B5/B7/B8/B20/B28/B38/B40/B41;

B7+B5/B7/B8/B20/B28;

B20+B38/B40;

B38+B38;

B40+B40;

B41+B41 B2+B2/B4*/B5/B7/B12/B13/B14/

B29/B30/B66/B71;

B25+B5/B12/B25/B26/B41;

B4+B4/B5/B7/B12/B13/B29/B30/

B71;

B66+B5/B7/B12/B13/B14/B29/B30/

B66/B71;

B7+B5/B7/B12;

B30+B5/B12/B14/B29;

B26+B41 2CA (UL) B3+B3; B7+B7; B38+B38; B40+B40;

B41+B41 B7+B7; B41+B41 EG18_Hardware_Design 12 / 104 LTE-A Module Series EG18 Hardware Design B1+B3+B3/B5/B7/B8/B20/B28/B38/B41;

B1+B40+B40; B1+B41+B41;

B1+B7+B20;

B3+B3+B7/B20/B28;

B3+B7+B7/B8/B20/B28;

B3+B40+B40;

B3+B41+B41;

B7+B7+B20/B28;

B40+B40+B40;

B41+B41+B41 B1+B3+B3+B5/B7/B8/B28/B41;

B1+B3+B7+B5/B7/B8/B20/B28;

B3+B3+B7+B7/B20/B28;

B3+B7+B7+B20/B28;

B3+B41+B41+B41;

3CA (DL) 4CA (DL) 5CA (DL) 5) B1+B3+B3+B7+B7;

B1+B3+B7+B7+B28;

WCDMA

(with Rx-diversity) B1/B3/B5/B8 GPS;

GLONASS;

BeiDou;

Galileo;

QZSS;

GNSS NOTES B2+B4+B5*/B13*/B71*;

B2+B5+B66; B2+B12+B30;

B2+B13+B66; B2+B7+B12/B66;

B4+B30+B5/B12/B29;

B4+B7+B12;

B30+B66+B5/B12/B29;

B2+B2+B5/B12/B13/B29/B66;

B5+B5+B2/B30/B66;

B7+B7+B2/B4/B5;

B66+B66+B2/B5/B13/B66;

B41+B41+B25/B26/B41;

B2+B4+B30+B5/B12;

B2+B66+B66+B5/B13;

B5+B5+B66+B66;

B12+B30+B66+B66;

B2+B5+B5+B66+B66/B30;

B2+B13+B66+B66+B66;

B5+B5+B30+B66+B6;

B2/B4/B5 GPS;

GLONASS;

BeiDou;

Galileo;

QZSS;

1. 1) GNSS function is optional. 2. 2) EG18 module contains Telematics version and Data-only version. Telematics version supports both voice and data functions, while Data-only version only supports data function. 3. 3) For more details about CA combinations, please refer to document [1]. 4. 4) LTE-FDD B29 support Rx only, and in CA mode it is only for secondary component. 5. 5) 5CA (DL) cannot support 44 MIMO. 6. * means under development. With a compact profile of 37.0mm 39.5mm 2.8mm, EG18 meets almost all requirements for M2M applications such as automotive, security, 4G router, CPE, wireless POS Terminal, mobile computing device, PDA phone, and tablet PC. EG18 is an SMD type module and can be embedded in applications through its 299 LGA pins. EG18_Hardware_Design 13 / 104 LTE-A Module Series EG18 Hardware Design 2.2. Key Features The following table describes the detailed features of EG18. Table 2: Key Features of EG18 Feature Details Power Supply Supply voltage: 3.3V~4.3V Typical supply voltage: 3.8V Transmitting Power Class 3 (23dBm2dB) for LTE-TDD bands Class 3 (23dBm2dB) for LTE-FDD bands Class 3 (24dBm+1/-3dB) for WCDMA bands Internet Protocol Features LTE Features UMTS Features SMS

(U)SIM Interfaces Audio Features PCM Interface Support FDD/TDD LTE Category 18 with CA and MIMO Support uplink QPSK and 16-QAM and 64-QAM modulation Support downlink QPSK, 16-QAM and 64-QAM and 256-QAM modulation Support 1.4MHz to 100MHz (5CA) RF bandwidth Support 44 MIMO in DL direction FDD: Max 1.175Gbps (DL)/150Mbps (UL) TDD: Max 545Mbps (DL)/90.6Mbps (UL) Support 3GPP R9 DC-HSDPA, DC-HSUPA, HSPA+, HSDPA, HSUPA and WCDMA Support QPSK, 16-QAM and 64-QAM modulation DC-HSDPA: Max 42Mbps DC-HSUPA: Max 11.5Mbps WCDMA: Max 384Kbps (DL)/384Kbps (UL) Support PPP/QMI/TCP*/UDP*/FTP*/HTTP*/NTP*/PING*/HTTPS*/SMTP*/

MMS*/FTPS*/SMTPS*/SSL* protocols Support PAP (Password Authentication Protocol) and CHAP (Challenge Handshake Authentication Protocol) usually used for PPP connections Text and PDU mode Point to point MO and MT SMS cell broadcast SMS storage: ME by default Support (U)SIM card: 1.8V/3.0V Dual SIM Single Standby Provide one digital audio interface: PCM interface LTE: AMR/AMR-WB Support echo cancellation and noise suppression Used for audio function with external codec Support 16-bit linear data format Support long frame synchronization and short frame synchronization EG18_Hardware_Design 14 / 104 LTE-A Module Series EG18 Hardware Design Support master and slave modes, but must be the master in long frame synchronization Comply with USB 3.0 and 2.0 specifications, with maximum transmission rates up to 5Gbps on USB 3.0 and 480Mbps on USB 2.0 Used for AT command communication, data transmission, firmware upgrade, software debugging, GNSS NMEA sentence output, and voice over USB*

Support USB serial drivers for: Windows 7/8/8.1/10; Linux 2.6/3.x/4.1~4.15;

Android 4.x/5.x/6.x/7.x/8.x/9.x Main UART interface:

Used for AT command communication and data transmission Baud rate reaches up to 921600bps, 115200bps by default Support RTS and CTS hardware flow control Debug UART interface:

Used for Linux console and log output 115200bps baud rate BT UART interface:

Used for Bluetooth communication and can be multiplexed into SPI interface*

115200bps baud rate Comply with PCI Express Specification Revision 2.1 and support 5Gbps per lane Used for data transmission Gen9HT-Lite of Qualcomm Protocol: NMEA 0183 Comply with 3GPP TS 27.007 and 27.005, and Quectel enhanced AT commands Two pins (NET_MODE and NET_STATUS) to indicate network connectivity status Main antenna interface (ANT_MAIN) Rx-diversity antenna interface (ANT_DIV) Two MIMO antenna interfaces (ANT_MIMO1, ANT_MIMO2) GNSS antenna interface (ANT_GNSS) USB Interface UART Interfaces PCIe 1 Interface*

GNSS Features AT Commands Network Indication Antenna Interfaces Rx-diversity Support LTE/WCDMA Rx-diversity and LTE HO-diversity Physical Characteristics Size: (37.00.15)mm (39.50.15)mm (2.80.20)mm Weight: approx. 9.0g Temperature Range Operation temperature range: -30C~ +70C 1) Extended temperature range: -40C~ +85C 2) Storage temperature range: -40C ~ +90C Firmware Upgrade USB 2.0 interface and DFOTA RoHS All hardware components are fully compliant with EU RoHS directive EG18_Hardware_Design 15 / 104 LTE-A Module Series EG18 Hardware Design NOTES 1. 2. 3.

* means under development. 1) Within operating temperature range, the module is 3GPP compliant. 2) Within extended temperature range, proper mounting, heating sinks and active cooling may be required to make certain functions of the module such as voice, SMS, data transmission to be realized. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances. When the temperature returns to normal operating temperature levels, the module will meet 3GPP specifications again. 2.3. Functional Diagram The following figure shows a block diagram of EG18 and illustrates the major functional parts. Power management Baseband LPDDR2 SDRAM+NAND Flash Radio frequency Peripheral interfaces Figure 1: Functional Diagram EG18_Hardware_Design 16 / 104 VBAT_RF VBAT_BB VDD_EXT VDD_RF PWRKEY RESET_N ADCs ANT_DIV ANT_GNSS ANT_MIMO2 ANT_MAIN ANT_MIMO1 ET/APT Tx/Rx Blocks PRx DRx Tx Transceiver NAND Flash LPDDR2 SDRAM PMIC Control QLINK Control Baseband STATUS I2S_MCLK BT_UART/SPI 38.4M XO USB2.0/3.0 USIMx2 PCM PCIe*

I2C UART GPIOs SDIO*

LTE-A Module Series EG18 Hardware Design 2.4. Evaluation Board To help with the development of applications with EG18, Quectel supplies the evaluation board (EVB), USB to RS-232 converter cable, earphone, antenna, and other peripherals to control or test the module. For more details, please refer to document [2]. EG18_Hardware_Design 17 / 104 LTE-A Module Series EG18 Hardware Design 3 Application Interfaces

(U)SIM interfaces EG18 is designed with 299 LGA pins that can be connected to cellular application platform. This chapter mainly describes the following application interfaces and indication signals of EG18:

Power supply USB interface UART interfaces SPI interface* 1) PCM and I2C interfaces ADC interfaces Network status indication Operation status indication RI Behaviors PCIe interface*

SDIO interface*

Antenna tuner control interfaces*

USB_BOOT interface GPIOs NOTES 1. 2.

* means under development. 1) SPI interface is multiplexed from BT UART interface. EG18_Hardware_Design 18 / 104 LTE-A Module Series EG18 Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of EG18. Figure 2: Pin Assignment (Top View) EG18_Hardware_Design 19 / 104 D E V R E S E R D E V R E S E R D E V R E S E R D E V R E S E R D E V R E S E R S S N G _ T N A I V D _ T N A I 2 O M M _ T N A I N A M _ T N A D E V R E S E R I 1 O M M _ T N A D E V R E S E R D E V R E S E R D E V R E S E R D E V R E S E R D E V R E S E R D E V R E S E R 9 2 1 7 2 1 5 2 1 3 2 1 1 2 1 9 1 1 7 1 1 5 1 1 3 1 1 1 1 1 9 0 1 7 0 1 5 0 1 3 0 1 1 0 1 9 9 7 9 5 9 3 9 1 9 9 8 8 9 2 8 2 1 6 2 1 4 2 1 2 2 1 0 2 1 8 1 1 6 1 1 4 1 1 2 1 1 0 1 1 8 0 1 6 0 1 4 0 1 2 0 1 0 0 1 8 9 6 9 4 9 2 9 0 9 4 1 2 3 1 2 2 1 2 1 1 2 0 1 2 9 0 2 8 0 2 7 0 2 6 0 2 5 0 2 4 0 2 3 0 2 2 0 2 1 0 2 0 0 2 9 9 1 8 9 1 7 9 1 6 9 1 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 VBAT_RF VBAT_RF GND GND VBAT_RF VBAT_RF GND GND USIM2_CLK USIM2_DET GND USIM2_VDD RESERVED GND PCM_OUT PCM_IN USIM2_RST USIM2_DATA GND RFFE_DATA RFFE_CLK GND PCM_CLK PCM_SYNC GND RI DCD RTS GND GND DTR TXD RXD CTS GND SD_CLK SD_CMD SD_DATA0 SD_DATA2 GND I2C_SCL SD_DET SD_DATA1 SD_DATA3 SD_VDD GND I2C_SDA 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 7 9 2 9 9 2 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 GND GND RESERVED DBG_RXD GPIO_1 USB_BOOT GND SLEEP_IND GND WAKEUP_IN I2S_MCLK GND VBAT_BB GND GND VDD_P2 DBG_TXD GPIO_2 GND NET_MODE WLAN_EN W_DISABLE#

VBAT_BB GND GND OTG_PWR_EN COEX_UART_TX COEX_UART_RX GND GPIO_3 WAKE_ON_WIRELESS GPIO_4 VDD_RF BT_CTS BT_RTS VDD_EXT BT_TXD BT_RXD GND NET_STATUS GPIO_5 GND RESERVED STATUS ADC0 ADC1 WLAN_SLP_CLK 287 288 289 290 291 292 293 294 295 7 7 1 8 7 1 9 7 1 0 8 1 1 8 1 2 8 1 3 8 1 4 8 1 5 8 1 6 8 1 7 8 1 8 8 1 9 8 1 0 9 1 1 9 1 2 9 1 3 9 1 4 9 1 5 9 1 2 4 6 8 0 1 2 1 4 1 6 1 8 1 0 2 2 2 4 2 6 2 8 2 0 3 2 3 4 3 6 3 8 3 0 4 296 1 3 5 7 9 1 1 3 1 5 1 7 1 9 1 1 2 3 2 5 2 7 2 9 2 1 3 3 3 5 3 7 3 9 3 1 4 D E V R E S E R Y E K R W P D E V R E S E R D E V R E S E R D E V R E S E R D E V R E S E R D N G D E V R E S E R D E V R E S E R D E V R E S E R D N G P _ K L C F E R _ E C P I D E V R E S E R D N G D N G N E _ R W P _ N A L W M _ K L C F E R _ E C P I M _ X T _ E C P I P _ X T _ E C P I D N G M _ X R _ E C P I D N G D E V R E S E R D N G D N G D E V R E S E R D N G D E V R E S E R D E V R E S E R GND Pins PCM Pins UART Pins N _ T E S E R N E _ T B Power Pins PCIe Pins ADC Pins N _ Q E R _ K L C _ E C P I T E D _ 1 M S U I N _ E K A W _ E C P I T S R _ 1 M S U I A T A D _ 1 M S U I N _ T S R _ E C P I D D V _ 1 M S U I K L C _ 1 M S U I P _ X R _ E C P I D E V R E S E R D N G D E V R E S E R D E V R E S E R D E V R E S E R P D _ B S U I D _ B S U D N G S U B V _ B S U D N G M D _ B S U D N G D N G D E V R E S E R P _ X T _ S S _ B S M U _ X T _ S S _ B S U D E V R E S E R P _ X R _ S S _ B S U D N G M _ X R _ S S _ B S U GPIO and Other Pins RESERVED Pins

(U)SIM Pins SPI Pins USB Pins ANT Pins I2C Pins SDIO Pins CLK Pins LTE-A Module Series EG18 Hardware Design 1. Keep all RESERVED pins and unused pins unconnected. 2. The GND pins 215~299 should be connected to ground in the design. 3.2. Pin Description Table 3: I/O Parameters Definition NOTES Type AI AO DI DO IO OD PI PO Description Analog Input Analog Output Digital Input Digital Output Bidirectional Open Drain Power Input Power Output The following table exhibits the pin definition and description of EG18. Table 4: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment VBAT_BB 155, 156 PI Power supply for the modules baseband part. Vmax=4.3V Vmin=3.3V Vnorm=3.8V VBAT_RF 85, 86, 87, 88 PI Power supply for the modules RF part. Vmax=4.3V Vmin=3.3V Vnorm=3.8V It must be able to provide sufficient current up to 1.2A. It must be able to provide with sufficient current up to 1.5A in a burst transmission. EG18_Hardware_Design 20 / 104 LTE-A Module Series EG18 Hardware Design If an SD card is used, connect VDD_P2 to SD_VDD. If an eMMC* is used or SDIO interface is unused, connect VDD_P2 to VDD_EXT. VDD_P2 135 PI SD card power supply VDD_EXT 168 VDD_RF 162 PO PO Provide 1.8V for external circuit. Vnorm=1.8V IOmax=50mA Provide 2.85V for external RF circuit. Vnorm=2.85V IOmax=120mA GND Ground 10, 13, 16, 17, 24, 30, 31, 35, 39, 44, 45, 54, 55, 63, 64, 69, 70, 75, 76, 81~84, 89, 90, 92~94, 96~100, 102~106, 108~112, 114~118, 120~126, 128~133, 141, 142, 148, 153, 154, 157, 158, 167, 174, 177, 178, 181, 184, 187, 191, 196, 202~208, 214~299 Turn on/off Pin Name Pin No. I/O Description DC Characteristics Comment RESET_N DI Reset the module PWRKEY DI Turn on/off the module 1 2 VIHmax=2.1V VIHmin=1.3V VILmax=0.5V VIHmax=2.1V VIHmin=1.3V VILmax=0.5V 1.8V power domain. Pulled up internally. Active low. 1.8V power domain. Pulled up internally. Active low. EG18_Hardware_Design 21 / 104 LTE-A Module Series EG18 Hardware Design Pin Name Pin No. I/O Description DC Characteristics Comment Status Indication NET_MODE 147 DO NET_STATUS 170 DO STATUS 171 DO

(U)SIM Interfaces Indicate the modules network registration mode. Indicate the modules network activity status. Indicate the modules operation status. VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. Pin Name Pin No. I/O Description DC Characteristics Comment USIM1_DET 25 DI

(U)SIM1 card insertion detection USIM1_VDD 26 PO Power supply for

(U)SIM1 card USIM1_CLK 27 DO Clock signal of

(U)SIM1 card 1.8V power domain. If unused, keep it open. Either 1.8V or 3.0V is supported by the module automatically. VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V For 1.8V (U)SIM:

Vmax=1.9V Vmin=1.7V For 3.0V (U)SIM:

Vmax=3.05V Vmin=2.75V IOmax=50mA For 1.8V (U)SIM:

VOLmax=0.4V VOHmin=1.45V For 3.0V (U)SIM:

VOLmax=0.4V VOHmin=2.3V For 1.8V (U)SIM:

VOLmax=0.4V VOHmin=1.45V For 3.0V (U)SIM:

VOLmax=0.4V VOHmin=2.3V USIM1_RST 28 DO Reset signal of

(U)SIM1 card USIM1_DATA 29 IO Data signal of For 1.8V (U)SIM:

EG18_Hardware_Design 22 / 104 LTE-A Module Series EG18 Hardware Design

(U)SIM1 card VILmax=0.36V VIHmin=1.26V VOLmax=0.4V VOHmin=1.45V For 3.0V (U)SIM:

VILmax=0.57V VIHmin=2.0V VOLmax=0.4V VOHmin=2.3V For 1.8V (U)SIM:

Vmax=1.9V Vmin=1.7V For 3.0V (U)SIM:

Vmax=3.05V Vmin=2.75V Iomax=50mA For 1.8V (U)SIM:

VILmax=0.36V VIHmin=1.26V VOLmax=0.4V VOHmin=1.45V For 3.0V (U)SIM:

VILmax=0.57V VIHmin=2V VOLmax=0.4V VOHmin=2.3V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V For 1.8V (U)SIM:

VOLmax=0.4V VOHmin=1.45V For 3.0V (U)SIM:

VOLmax=0.4V VOHmin=2.3V For 1.8V (U)SIM:

VOLmax=0.4V VOHmin=1.45V Either 1.8V or 3.0V is supported by the module automatically. If (U)SIM2 interface is unused, keep it open. If (U)SIM2 interface is unused, keep it open. 1.8V power domain. If (U)SIM2 interface is unused, keep it open. If (U)SIM2 interface is unused, keep it open. If (U)SIM2 interface is unused, keep it open. USIM2_VDD 74 PO Power supply for

(U)SIM2 card USIM2_DATA 77 IO Data signal of

(U)SIM2 card USIM2_DET 78 DI

(U)SIM2 card insertion detection USIM2_RST 79 DO Reset signal of

(U)SIM2 card USIM2_CLK 80 DO Clock signal of

(U)SIM2 card EG18_Hardware_Design 23 / 104 LTE-A Module Series EG18 Hardware Design USB Interface Pin Name Pin No. I/O Description DC Characteristics Comment For 3.0V (U)SIM:

VOLmax=0.4V VOHmin=2.3V Vmax=5.25V Vmin=3.3V Vnorm=5.0V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V Comply with USB 2.0 standard specifications. Require differential impedance of 90. Comply with USB 3.0 standard specifications. Require differential impedance of 90. 1.8V power domain. If unused, keep it open. USB_VBUS 32 DI USB_DM 33 IO USB_DP 34 IO USB_SS_ TX_M 37 AO USB_SS_ TX_P 38 AO USB_SS_ RX_P 40 USB_SS_ RX_M 41 AI AI USB connection detection USB 2.0 differential data bus (-) USB 2.0 differential data bus (+) USB 3.0 super speed transmission (-) USB 3.0 super speed transmission (+) USB 3.0 super speed receiving (+) USB 3.0 super speed receiving (-) USB_ID 36 DI OTG identification OTG_PWR_EN 143 DO OTG power control SDIO Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment SD_VDD 46 PO SD card application:

SDIO pull up power source eMMC application:

Keep it open when used for eMMC For 1.8V SD card:

Vmax=1.9V Vmin=1.75V For 3.0V SD card:

Vmax=3.05V Vmin=2.75V IOmax=50mA For 1.8V SD card:

VOLmax=0.45V VOHmin=1.4V Either 1.8V or 3.0V is supported by the module automatically. Power of SD card must be provided by an external power supply. If unused, keep it open. If unused, keep it SD_DATA0 49 50 SD_DATA1 IO SDIO data signal (bit IO SDIO data signal (bit 0) EG18_Hardware_Design 24 / 104 LTE-A Module Series EG18 Hardware Design Pin Name Pin No. I/O Description DC Characteristics Comment 1) IO IO SDIO data signal (bit 2) SDIO data signal (bit 3) DO SDIO command signal SD_DATA2 SD_DATA3 SD_CMD 47 48 51 SD_CLK 53 DO SDIO clock signal SD_ DET 52 DI SD card insertion detection Main UART Interface CTS 56 DO Clear to send RTS 57 DI Request to send RXD 58 DI Receive data DCD 59 DO Data carrier detection TXD 60 DO Transmit data RI 61 DO Ring indication DTR 62 DI Data terminal ready, sleep mode control VILmin=-0.3V VILmax=0.58V VIHmin=1.3V VIHmax=2.0V For 3.0V SD card:

VOLmax=0.35V VOHmin=2.15V VILmin=-0.3V VILmax=0.7V VIHmin=1.8V VIHmax=3.15V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V open. If unused, keep it open. If unused, keep it open. If unused, keep it open. If unused, keep it open. 1.8V power domain, If unused, keep it open. VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. 1.8V power domain. Pulled up by default. Pulling down to low level EG18_Hardware_Design 25 / 104 LTE-A Module Series EG18 Hardware Design will wake up the module. If unused, keep it open. 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. BT UART interface pin by default. Can be multiplexed into SPI_MOSI. 1.8V power domain. If unused, keep it open. BT UART interface pin by default. Can be multiplexed into SPI_CLK. 1.8V power domain. If unused, keep it open. BT UART interface pin by default. Can be multiplexed into SPI_MISO. 1.8V power domain. If unused, keep it Debug UART Interface Pin Name Pin No. I/O Description DC Characteristics Comment DBG_RXD 136 DI Receive data VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. DBG_TXD 137 DO Transmit data BT UART Interface (Can be multiplexed into SPI interface*) Pin Name Pin No. I/O Description DC Characteristics Comment BT_EN 3 DO BT function enable control VOLmax=0.45V VOHmin=1.35V BT_TXD 163 DO Transmit data VOLmax=0.45V VOHmin=1.35V BT_CTS 164 DO Clear to send VOLmax=0.45V VOHmin=1.35V BT_RXD 165 DI Receive data BT_RTS 166 DI Request to send VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VILmin=-0.3V VILmax=0.6V EG18_Hardware_Design 26 / 104 LTE-A Module Series EG18 Hardware Design VIHmin=1.2V VIHmax=2.0V open. BT UART interface pin by default. Can be multiplexed into SPI_CS. PCM & I2C Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment I2C_SDA 42 OD I2C_SCL 43 OD I2C serial interface used for external codec PCM_SYNC 65 IO PCM data frame synchronization signal PCM_IN 66 DI PCM data input PCM_CLK 67 IO PCM clock PCM_OUT 68 DO PCM data output I2S_MCLK 152 DO Clock output Antenna Interfaces VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V 1.8V power domain. An external pull-up resistor is required. If unused, keep it open. 1.8V power domain. In master mode, it is an output signal. In slave mode, it is an input signal. If unused, keep it open. 1.8V power domain. If unused, keep it open. 1.8V power domain. In master mode, it is an output signal. In slave mode, it is an input signal. If unused, keep it open. 1.8V power domain. If unused, keep it open. Provide a digital clock output for an external audio codec. If unused, keep it open. Pin Name Pin No. I/O Description DC Characteristics Comment ANT_MAIN 107 IO ANT_DIV 127 AI Support all band main antenna interface Support all band RXD antenna interface 50 impedance 50 impedance If unused, keep EG18_Hardware_Design 27 / 104 LTE-A Module Series EG18 Hardware Design them open. Support all band 4x4 MIMO antenna interface Support all band 4x4 MIMO antenna interface GNSS antenna interface ANT_ MIMO1 101 AI ANT_MIMO2 113 AI ANT_GNSS 119 AI WLAN Control Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment WLAN_PWR_EN 5 DO WLAN power supply enable control VOLmax=0.45V VOHmin=1.35V COEX_UART_TX 145 DO LTE/WLAN coexistence signal VOLmax=0.45V VOHmin=1.35V COEX_UART_RX 146 DI LTE/WLAN coexistence signal VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V WLAN_EN 149 DO WLAN function enable control VOLmax=0.45V VOHmin=1.35V WAKE_ON_ WIRELESS 160 DI Wake up the host

(EG18) by an external Wi-Fi module VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. 1.8V power domain. Active high. If unused, keep it open. 1.8V power domain. Active low. If unused, keep it open. WLAN_SLP_ CLK ADC Interfaces 169 DO WLAN sleep clock VOLmax=0.45V VOHmin=1.35V If unused, keep it open. Pin Name Pin No. I/O Description DC Characteristics Comment ADC0 173 AI ADC1 175 AI General purpose analog to digital converter interface General purpose analog to digital converter interface Voltage range:

0V to 1.875V If unused, keep it open. Voltage range:

0V to 1.875V If unused, keep it open. EG18_Hardware_Design 28 / 104 LTE-A Module Series EG18 Hardware Design PCIe Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment PCIE_REFCLK_P 179 PCIE_REFCLK_ M 180 AI/

AO AI/

AO Input/Output PCIe reference clock (+) Input/Output PCIe reference clock (-) PCIE_TX_M 182 AO PCIe transmission (-) PCIE_TX_P 183 AO PCIe transmission (+) PCIE_RX_M 185 AI PCIe receiving (-) PCIE_RX_P 186 AI PCIe receiving (+) PCIE_CLK_ REQ_N 188 IO PCIe clock request PCIE_RST_N 189 IO PCIe reset PCIE_WAKE_N 190 IO PCIe wake up Comply with PCIe 2.1 standard specifications. Require differential impedance of 95. In master mode, it is an input signal. In slave mode, it is an output signal. If unused, keep it open. In master mode, it is an output signal. In slave mode, it is an input signal. If unused, keep it open. In master mode, it is an input signal. In slave mode, it is an output signal. If unused, keep it open. VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V Pin Name Pin No. I/O Description DC Characteristics Comment GPIO Pins GPIO_1 138 IO GPIO_2 139 IO General purpose input/output port If unused, keep them open. EG18_Hardware_Design 29 / 104 LTE-A Module Series EG18 Hardware Design Antenna Tuner Control Interfaces* (RFFE Interface/GPIO Interface) Pin Name Pin Name I/O Description DC Characteristics Comment RFFE_CLK 71 DO RFFE_DATA 73 IO RFFE serial interface used for external tuner control 159 161 172 IO IO IO GPIO interface dedicated for external tuner control GPIO_3 GPIO_4 GPIO_5 Other Pins Pin Name Pin No. I/O Description DC Characteristics Comment USB_BOOT 140 DI Force the module to enter emergency download mode VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V SLEEP_IND 144 DO Sleep indication VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V If unused, keep them open. If unused, keep them open. 1.8V power domain. Active high If unused, keep it open. 1.8V power domain. If unused, keep it open. 1.8V power domain. Pulled up by default. Low level wakes up the module. If unused, keep it open. 1.8V power domain. Pulled up by default. In low voltage level, the module will enter airplane mode. If unused, keep it open. WAKEUP_IN 150 DI Sleep mode control W_DISABLE#

151 DI Airplane mode control EG18_Hardware_Design 30 / 104 LTE-A Module Series EG18 Hardware Design RESERVED Pins Pin Name Pin No. I/O Description DC Characteristics Comment RESERVED Reserved Keep these pins unconnected. 4, 6~9, 11, 12, 14, 15, 18~23, 72, 91, 95, 134, 176, 192~195, 197~201, 209~213 3.3. Operating Modes The table below summarizes different operating modes of EG18. Table 5: Overview of Operating Modes Mode Details Normal Operation Modes Idle Software is active. The module has registered on the network, and it is ready to send and receive data. Talk/Data Network connection is ongoing. In this mode, the power consumption is decided by network setting and data transfer rate. Minimum Functionality Mode AT+CFUN=0 command can set the module to a minimum functionality mode without removing the power supply. In this case, both RF function and (U)SIM card will be invalid. Airplane Mode AT+CFUN=4 command or driving W_DISABLE# pin to low level can set the module to airplane mode. In this case, RF function will be invalid. In this mode, the current consumption of the module will be reduced to the minimal level. In this mode, the module can still receive paging message, SMS, voice call and TCP/UDP data from the network normally. In this mode, the power management unit shuts down the power supply. Software is not active. The serial interfaces are not accessible. Operating voltage (connected to VBAT_RF and VBAT_BB) remains applied. Sleep Mode Power Down Mode NOTE Please refer to document [3] for details about AT+CFUN command. EG18_Hardware_Design 31 / 104 LTE-A Module Series EG18 Hardware Design 3.4. Power Saving 3.4.1. Sleep Mode DRX of EG18 is able to reduce the current consumption to a minimum value during the sleep mode, and DRX cycle index values are broadcasted by the wireless network. The figure below shows the relationship between the DRX run time and the current consumption in sleep mode. The longer the DRX cycle is, the lower the current consumption will be. Figure 3: DRX Run Time and Current Consumption in Sleep Mode The following sections describes power saving procedure of EG18. 3.4.1.1. UART Application If the host communicates with the module via UART interfaces, both of the following preconditions should be met to make the module enter into sleep mode. Keep DTR at high level (pulled up by default). Execute AT+QSCLK=1 command to enable sleep mode. EG18_Hardware_Design 32 / 104 n o i t p m u s n o C t n e r r u C DRX OFF ON OFF ON OFF ON OFF ON OFF Run Time LTE-A Module Series EG18 Hardware Design The following figure shows the connection between the module and the host. Figure 4: Sleep Mode Application via UART Interfaces Driving the host DTR to low level will wake up the module. When EG18 has a URC to report, RI signal will wake up the host. Please refer to Chapter 3.16 for details about RI behaviors. 3.4.1.2. USB Application with USB Remote Wakeup Function If the host supports USB suspend/resume and remote wakeup function, the following three preconditions must be met to let the module enter sleep mode. Keep DTR at high level (pulled up by default). Execute AT+QSCLK=1 command to enable the sleep mode. The hosts USB bus, which is connected with the modules USB interface, has entered into suspend state. The following figure shows the connection between the module and the host. Figure 5: Sleep Mode Application with USB Remote Wakeup EG18_Hardware_Design 33 / 104 Module Host RXD TXD RI DTR GND TXD RXD EINT GPIO GND Module USB_VBUS Host VDD USB Interface USB Interface GND GND LTE-A Module Series EG18 Hardware Design Sending data to EG18 through USB will wake up the module. When EG18 has a URC to report, the module will send remote wake-up signals via USB bus to wake up the host. 3.4.1.3. USB Application with USB Suspend/Resume and RI Function If the host supports USB suspend/resume, but does not support remote wake-up function, RI signal is needed to wake up the host. There are three preconditions to make the module enter into sleep mode. Keep DTR at high level (pulled up by default). Execute AT+QSCLK=1 command to enable the sleep mode. The hosts USB bus, which is connected with the modules USB interface, has entered into suspend state. The following figure shows the connection between the module and the host. Figure 6: Sleep Mode Application with RI Sending data to EG18 through USB will wake up the module. When EG18 has a URC to report, RI signal will wake up the host. 3.4.1.4. USB Application without USB Suspend Function If the host does not support USB suspend function, USB_VBUS should be disconnected with an external control circuit to make the module enter into sleep mode. Keep DTR at high level (pulled up by default). Execute AT+QSCLK=1 command to enable the sleep mode. Disconnect USB_VBUS. EG18_Hardware_Design 34 / 104 Module USB_VBUS Host VDD USB Interface USB Interface RI GND EINT GND LTE-A Module Series EG18 Hardware Design The following figure shows the connection between the module and the host. Figure 7: Sleep Mode Application without Suspend Function Switching on the power switch to supply power to USB_VBUS will wake up the module. Please pay attention to the level match of the connection shown in dotted line between the module and the host. NOTE 3.4.2. Airplane Mode EG18 provides a W_DISABLE# signal to disable or enable airplane mode through hardware operation. The W_DISABLE# pin is pulled up by default. Driving it to low level will make the module enter into airplane mode. In airplane mode, RF function will be disabled. The RF function can also be enabled or disabled through AT commands. The following table shows the RF function status of the module and relevant AT commands. Table 6: RF Function Status and Relevant AT Commands W_DISABLE# AT Commands RF Function Module Operation AT+CFUN=1 RF Enabled Normal operation mode High Level AT+CFUN=0 AT+CFUN=4 RF Disabled AT+CFUN=0: Minimum functionality mode AT+CFUN=4: Airplane mode EG18_Hardware_Design 35 / 104 Module USB_VBUS Power Switch Host GPIO VDD EINT GND USB Interface USB Interface RI GND LTE-A Module Series EG18 Hardware Design Low Level RF Disabled Airplane mode AT+CFUN=0 AT+CFUN=1 AT+CFUN=4 1. The W_DISABLE# control function is disabled in firmware by default. It can be enabled by AT+QCFG="airplanecontrol" command, and this command is under development. 2. The execution of AT+CFUN command will not affect GNSS function. NOTES 3.5. Power Supply 3.5.1. Power Supply Pins EG18 provides six VBAT pins dedicated to the connection with an external power supply. There are two separate voltage domains for VBAT. Four VBAT_RF pins for RF part Two VBAT_BB pins for baseband part The following table shows details of VBAT pins and ground pins. Table 7: VBAT and GND Pins Pin Name Pin No. Description Min. Typ. Max. Unit VBAT_RF 85, 86, 87, 88 3.3 3.8 4.3 Power supply for the modules RF part Power supply for the modules baseband part V V VBAT_BB 155, 156 3.3 3.8 4.3 GND Ground

0

V 10, 13, 16, 17, 24, 30, 31, 35, 39, 44, 45, 54, 55, 63, 64, 69, 70, 75, 76, 81~84, 89, 90, 92~94, 96~100, 102~106, 108~112, 114~118, 120~126, 128~133, 141, 142, 148, 153, 154, 157, 158, 167, 174, 177, 178, 181, 184, 187, 191, 196, 202~208, 214~299 EG18_Hardware_Design 36 / 104 LTE-A Module Series EG18 Hardware Design 3.5.2. Decrease Voltage Drop The power supply range of the module is from 3.3V to 4.3V. Please make sure the input voltage will never drop below 3.3V. The following figure shows the maximum voltage drop when burst transmission occurs during radio transmission in 3G and 4G networks. Figure 8: Power Supply Limits during Tx Power To decrease voltage drop, a bypass capacitor of about 100F with low ESR should be used, and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low ESR. It is recommended to use three ceramic capacitors (100nF, 33pF, 10pF) for composing of the MLCC array, and to place these capacitors close to VBAT pins. The main power supply from an external application has to be a single voltage source and can be expanded to two sub paths with star structure. The width of VBAT_BB trace should be no less than 1mm; and the width of VBAT_RF trace should be no less than 2mm. In principle, the longer the VBAT trace is, the wider it should be. In addition, in order to get a stable power source, it is suggested to use a zener diode of which reverse zener voltage is 5.1V and dissipation power is more than 0.5W. The following figure shows the star structure of the power supply. Figure 9: Star Structure of the Power Supply EG18_Hardware_Design 37 / 104 Max Tx Power Max Tx Power VCC Min. 3.3V Drop Ripple VBAT

D1 C1 C2 C3 C4 C5

C6

C7 C8 C9 5.1V 100F 100nF 33pF 10pF 100F 100F 100nF 33pF 10pF VBAT_RF VBAT_BB Module LTE-A Module Series EG18 Hardware Design 3.5.3. Reference Design for Power Supply Power design for the module is very important, as the performance of the module largely depends on the power source. The power supply of EG18 should be able to provide sufficient current up to 2A at least. If the voltage drop between the input and output is not too high, an LDO is suggested to be used to supply power for the module. If there is a big voltage difference between the input source and the desired output

(VBAT), a buck converter is preferred to be used as the power supply. The following figure shows a reference design for +5V input power source. In this design, output of the power supply is about 3.8V and the maximum load current is 3A. Figure 10: Reference Circuit of Power Supply NOTE To avoid damages to the internal flash, please do not switch off the power supply directly when the module is working. Only after the module is shut down by PWRKEY or AT command can the power supply be cut off. 3.5.4. Monitor the Power Supply AT+CBC command can be used to monitor the voltage value of VBAT_BB. For more details, please refer to document [3]. EG18_Hardware_Design 38 / 104 DC_IN VBAT MIC29302WU 2 IN N E 1 OUT 4 J D A D N G 51K 3 5 100K 1%

47K 1%

470F 100nF 4.7K VBAT_EN 47K 470R 470F 100nF LTE-A Module Series EG18 Hardware Design 3.6. Turn on and off Scenarios 3.6.1. Turn on the Module Through PWRKEY The following table shows the pin definition of PWRKEY. Table 8: PWRKEY Pin Description Pin Name Pin No. Description DC Characteristics Comment PWRKEY 2 Turn on/off the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V 1.8V power domain. Pulled-up internally. Active low. When EG18 is in power down mode, it can be turned on and enter into normal operation mode by driving the PWRKEY pin to a low level voltage for at least 500ms. It is recommended to use an open drain/collector driver to control the PWRKEY. After STATUS pin outputs a high level, PWRKEY can be released. A simple reference circuit is illustrated by the following figure. Figure 11: Turn on the Module with a Driving Circuit EG18_Hardware_Design 39 / 104 PWRKEY 500ms Turn on pulse 4.7K 47K LTE-A Module Series EG18 Hardware Design Another way to control the PWRKEY is using a button. Electrostatic strike may generate from fingers when the button is pressed. Therefore, it is necessary to place a TVS component nearby the button for ESD protection. A reference circuit is shown by the following figure:

Figure 12: Turn on the Module Using a Button The timing of turn-on scenario is illustrated by the following figure. Figure 13: Timing of Turning on the Module NOTE Please ensure that VBAT is stable for no less than 30ms before pulling down the PWRKEY. EG18_Hardware_Design 40 / 104 S1 PWRKEY TVS Close to S1 NOTE VBAT 500ms VIH1.3V PWRKEY VIL0.5V RESET_N STATUS VDD_EXT VDD_RF USIM_VDD 29ms 11.5s 100ms 17s 16s 13s UART Inactive Active LTE-A Module Series EG18 Hardware Design 3.6.2. Turn off the Module The following two methods can be used to turn off the module: through PWRKEY or AT+QPOWD command. 3.6.2.1. Turn off the Module Through PWRKEY Driving PWRKEY to a low level voltage for at least 800ms, then the module will execute power-down procedure after the PWRKEY is released. The timing of turn-off scenario is illustrated by the following figure. Figure 14: Timing of Turning off the Module 3.6.2.2. Turn off the Module Through AT Command It is also a safe way to use AT+QPOWD command to turn off the module. Please refer to document [3]

for more details about the command. EG18_Hardware_Design 41 / 104 800ms 30s 10s 1.5s 1.6s VBAT PWRKEY STATUS VDD_EXT VDD_RF USIM_VDD Module Status RUNNING Power-down procedure OFF LTE-A Module Series EG18 Hardware Design NOTES 1. To avoid damages to the internal flash, please do not switch off the power supply directly when the module is working. Only after the module is shut down by PWRKEY or AT command can the power supply be cut off. 2. When turning off the module with AT command, please keep PWRKEY at high level after execution of the power-off command. Otherwise, the module will be turned on again after a successful turning-off. 3.7. Reset the Module The module can be reset by driving RESET_N pin to a low level voltage for 250ms~600ms and then releasing it. Table 9: RESET_N Pin Description Pin Name Pin No. Description DC Characteristics Comment RESET_N 1 Reset the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V An open drain/collector driver or button can be used to control the RESET_N pin. A reference circuit is shown as below. Figure 15: Reference Circuit of RESET_N with a Driving Circuit EG18_Hardware_Design 42 / 104 RESET_N 250ms~600ms Reset pulse 4.7K 47K LTE-A Module Series EG18 Hardware Design Figure 16: Reference Circuit of RESET_N with a Button The timing of reset scenario is illustrated by the following figure. Figure 17: Timing of Resetting the Module NOTES 1. RESET_N can only be used when the module failed to be turned off either by AT+QPOWD command or PWRKEY. 2. Please ensure that there is no capacitor with high capacitance on PWRKEY and RESET_N pins. EG18_Hardware_Design 43 / 104 S2 RESET_N TVS Close to S2 600ms VIL0.5V 212.5ms 2.5ms VIH1.3V 17s 16s VBAT RESET_N VDD_EXT VDD_RF USIM_VDD Module Status 204ms 205ms 250ms Running Resetting Restart LTE-A Module Series EG18 Hardware Design 3.8. (U)SIM Interfaces EG18 provides two (U)SIM interfaces. The circuitry of (U)SIM interfaces meets ETSI and IMT-2000 requirements. Both 1.8V and 3.0V (U)SIM cards are supported. Dual SIM Single Standby function is supported and (U)SIM card switching is enabled by AT+QUIMSLOT command. For more details about this command, please refer to document [3]. Table 10: Pin Definition of the (U)SIM Interfaces Pin Name Pin No. I/O Description Comment USIM1_DET 25 DI

(U)SIM1 card insertion detection USIM1_VDD 26 PO Power supply for (U)SIM1 card Either 1.8V or 3.0V is supported by the module automatically. USIM1_CLK 27 DO Clock signal of (U)SIM1 card USIM1_RST 28 DO Reset signal of (U)SIM1 card USIM1_DATA 29 IO Data signal of (U)SIM1 card USIM2_VDD 74 PO Power supply for (U)SIM2 card USIM2_DATA 77 IO Data signal of (U)SIM2 card USIM2_DET 78 DI

(U)SIM2 card insertion detection USIM2_RST 79 DO Reset signal of (U)SIM2 card USIM2_CLK 80 DO Clock signal of (U)SIM2 card Either 1.8V or 3.0V is supported by the module automatically. If (U)SIM2 interface is unused, keep it open. If (U)SIM2 interface is unused, keep it open. If (U)SIM2 interface is unused, keep it open. If (U)SIM2 interface is unused, keep it open. If (U)SIM2 interface is unused, keep it open. EG18 supports (U)SIM card hot-plug via USIM_DET pins. The function supports low level and high level detections, and is disabled by default. Please refer to document [3] for more details about AT+QSIMDET command. EG18_Hardware_Design 44 / 104 LTE-A Module Series EG18 Hardware Design The following figure shows a reference design for a (U)SIM interface with an 8-pin (U)SIM card connector. Figure 18: Reference Circuit of a (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_DET pins unconnected. A reference circuit for a (U)SIM interface with a 6-pin (U)SIM card connector is illustrated by the following figure. Figure 19: Reference Circuit of a (U)SIM Interface with a 6-Pin (U)SIM Card Connector EG18_Hardware_Design 45 / 104 VDD_EXT USIM_VDD 51K 15K Module USIM_VDD USIM_RST USIM_CLK USIM_DET USIM_DATA 22R 22R 22R 100nF

(U)SIM Card Connector VCC RST CLK CD1 GND VPP IO CD2 NM NM NM GND GND USIM_VDD 15K 22R 22R 22R Module USIM_VDD USIM_RST USIM_CLK USIM_DATA 100nF

(U)SIM Card Connector VCC RST CLK GND VPP IO NM NM NM GND LTE-A Module Series EG18 Hardware Design The (U)SIM scenario is illustrated by the following figure. Figure 20: Timing of (U)SIM When AT+QSIMDET=1,0 is set, the scenario of hot-plug is illustrated by the following figure. Figure 21: Timing of Hot-Plug In order to enhance the reliability and availability of the (U)SIM card in applications, please follow the criteria below in the (U)SIM circuit design:

Keep the (U)SIM card connector as close as possible to the module. Keep the trace length less than 200mm. EG18_Hardware_Design 46 / 104 5.8ms ATR 1.1ms 1.7ms USIM_VDD USIM_DATA USIM_CLK USIM_CLK USIM_RST 20.8ms USIM_DET 103ms 1.1ms 1.7ms USIM_VDD USIM_DATA USIM_CLK USIM_RST 5.8ms ATR 20.8ms LTE-A Module Series EG18 Hardware Design Keep (U)SIM card signals away from RF and VBAT traces. Keep the ground traces between the module and the (U)SIM card connector short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5mm to maintain the same electric potential. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with surrounded ground. To offer good ESD protection, it is recommended to add a TVS diode array with parasitic capacitance not exceeding 50pF. The 22 resistors should be added in series between the module and the

(U)SIM card connector to facilitate debugging. Please note that the (U)SIM peripheral circuit should be close to the (U)SIM card connector. The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace and sensitive occasion are applied, and should be placed close to the (U)SIM card connector. 3.9. USB Interface EG18 provides one integrated Universal Serial Bus (USB) interface which complies with the USB 3.0 and USB 2.0 specifications. It supports super speed (5Gbps) on USB 3.0 and high speed (480Mbps) and full speed (12Mbps) modes on USB 2.0. The USB interface is used for AT command communication, data transmission, GNSS NMEA sentence output, software debugging, firmware upgrade, and voice over USB*. The following table shows the pin definition of USB interface. Table 11: Pin Definition of USB Interface 32 34 33 Pin Name Pin No. I/O Description Comment USB_VBUS DI Used for detecting the USB connection Typical 5.0V USB_DP USB_DM IO USB 2.0 differential data bus (+) IO USB 2.0 differential data bus (-) USB_SS_ TX_M 37 AO USB 3.0 super-speed transmission (-) USB_SS_ TX_P 38 AO USB 3.0 super-speed transmission (+) USB_SS_ RX_P 40 USB 3.0 super-speed receiving (+) USB_SS_ RX_M 41 USB 3.0 super-speed receiving (-) AI AI USB_ID 36 DI OTG identification Require differential impedance of 90 Require differential impedance of 90 Require differential impedance of 90 1.8V power domain. If unused, keep it open OTG_PWR_EN 143 DO OTG power control EG18_Hardware_Design 47 / 104 LTE-A Module Series EG18 Hardware Design For more details about the USB 2.0 and USB 3.0 specifications, please visit http://www.usb.org/home. The USB interface is recommended to be reserved for firmware upgrade in design. The following figure shows a reference circuit of USB 2.0 and USB 3.0 interface. Figure 22: Reference Circuit of USB Application In order to ensure the signal integrity of USB data lines, C1, and C2 have been installed in the module; C3 and C4 must be placed close to the host; and R1, R2, R3 and R4 should be placed close to each other. The extra stubs of trace must be as short as possible. EG18_Hardware_Design 48 / 104 Minimize these stubs Test Points Module VDD R3 R4 R1 R2 NM_0R NM_0R 0R 0R Close to Module ESD Array USB_VBUS USB_DM USB_DP 100nF C1 100nF USB_SS_TX_P USB_SS_TX_M C2 USB_SS_RX_P USB_SS_RX_M USB_ID GND Host USB_DM USB_DP USB_SS_RX_P USB_SS_RX_M USB_SS_TX_P USB_SS_TX_M GPIO GND 100nF C3 100nF C4 LTE-A Module Series EG18 Hardware Design The USB enumeration scenario is illustrated by the following figure. Figure 23: Timing of USB Enumeration The following principles of USB interface should be complied with, so as to meet USB 2.0 and USB 3.0 specifications. It is important to route the USB 2.0 & 3.0 signal traces as differential pairs with total grounding. The impedance of USB differential trace is 90. For USB 2.0 signal traces, the trace length should be less than 120mm, and the differential data pair matching should be less than 2mm (15ps). For USB 3.0 signal traces, the maximum length of each differential data pair (TX/RX) is recommended to be less than 100mm, and each differential data pair matching should be less than 0.7mm (5ps). Do not route signal traces under crystals, oscillators, magnetic devices, PCIe and RF signal traces. It is important to route the USB differential traces in inner-layer of the PCB, and surround the traces with ground on that layer and with ground planes above and below. If a USB connector is used, please keep the ESD protection components as close to the USB connector as possible. Pay attention to the influence of junction capacitance of ESD protection components on USB data traces. Typically, the capacitance value of ESD protection componetns should be less than 2.0pF for USB 2.0, and less than 0.4pF for USB 3.0. If possible, reserve a 0 resistor on USB_DP and USB_DM lines respectively. NOTE

* means under development. EG18_Hardware_Design 49 / 104 STATUS USB_VBUS 525ms 200ms USB Inactive Enumeration procedure Active LTE-A Module Series EG18 Hardware Design 3.10. UART Interfaces The module provides three UART interfaces: main UART interface, debug UART interface, and BT UART interface. Features of these interfaces are shown as below:

Main UART interface supports 4800bps, 9600bps, 19200bps, 38400bps, 57600bps, 115200bps

(default), 230400bps, 460800bps, and 921600bps baud rates. It is used for data transmission and AT command communication. And it supports RTS and CTS hardware flow control. Debug UART interface supports 115200bps baud rate. It is used for Linux console and log output. BT UART interface supports 115200bps baud rate. It is used for BT communication and can be multiplexed into SPI interface*. NOTE

* means under development. 3.10.1. Main UART Interface The following table shows the main UART interface pin definition. Table 12: Pin Definition of Main UART Interface Pin Name Pin No. I/O Description Comment 56 57 58 59 60 61 62 DO Clear to send 1.8V power domain DI DI DO DO DO DI Request to send 1.8V power domain Receive data 1.8V power domain Data carrier detection 1.8V power domain Transmit data 1.8V power domain Ring indication 1.8V power domain Data terminal ready, sleep mode control 1.8V power domain CTS RTS RXD DCD TXD RI DTR EG18_Hardware_Design 50 / 104 LTE-A Module Series EG18 Hardware Design DI DO DO DO DO DI DI 3.10.2. Debug UART Interface The following table shows the pin definition of debug UART interface. Table 13: Pin Definition of Debug UART Interface Pin Name Pin No. I/O Description Comment DBG_RXD 136 Receive data 1.8V power domain DBG_TXD 137 Transmit data 1.8V power domain 3.10.3. BT UART Interface The following table shows the pin definition of BT UART interface. Table 14: Pin Definition of the BT UART Interface Pin Name Pin No. I/O Description Comment BT_EN BT_TXD BT_CTS BT_RXD BT_RTS 3 163 164 165 166 3.10.4. UART Application BT function enable control Transmit data Clear to send Receive data Request to send 1.8V power domain If unused, keep it open. EG18 provides 1.8V UART interfaces. A level translator should be used if the application is equipped with a 3.3V UART interface. The logic levels are described in the following table. Table 15: Logic Levels of Digital I/O Parameter VIL Min.

-0.3 Max. 0.6 Unit V EG18_Hardware_Design 51 / 104 LTE-A Module Series EG18 Hardware Design VIH VOL VOH 1.2 0 1.35 2.0 0.45 1.8 V V V A level translator TXS0108EPWR provided by Texas Instruments is recommended. The following figure shows a reference design. Figure 24: Level Translation Reference Circuit with an IC Please visit http://www.ti.com for more information. EG18_Hardware_Design 52 / 104 VDD_EXT 0.1F VCCA 0.1F VDD_MCU VDD_EXT 10K 120K RI DCD CTS RTS DTR TXD RXD Translator VCCB GND B1 B2 B3 B4 B5 B6 B7 B8 OE A1 A2 A3 A4 A5 A6 A7 A8 51K 51K RI_MCU DCD_MCU CTS_MCU RTS_MCU DTR_MCU RXD_MCU TXD_MCU LTE-A Module Series EG18 Hardware Design Another example with transistor translation circuit is shown as below. The circuit designs for the parts shown with dotted lines refer to the design of TXD and RXD, and please pay attention to the direction of connection. Figure 25: Level Translation Reference Circuit with MOSFETs NOTE Transistor circuit solution is not suitable for applications with high baud rates exceeding 460kbps. 3.11. SPI Interface*

EG18 provides one SPI interface multiplexed from BT UART interface. The interface only supports master mode with a maximum clock frequency up to 50MHz. The following table shows the pin definition of SPI interface. Table 16: Pin Definition of SPI Interface Pin Name Pin No. I/O Description Comment BT_TXD 163 Can be multiplexed into SPI_MOSI. BT_CTS 164 Can be multiplexed into SPI_CLK. DO DO 1.8V power domain EG18_Hardware_Design 53 / 104 VDD_EXT VDD_EXT 4.7K 1nF MCU/ARM 10K Module 10K 1nF VCC_MCU 4.7K VDD_EXT TXD RXD RTS CTS GPIO EINT GPIO GND RXD TXD RTS CTS DTR RI DCD GND LTE-A Module Series EG18 Hardware Design BT_RXD 165 Can be multiplexed into SPI_MISO. BT_RTS 166 Can be multiplexed into SPI_CS. DI DI The following figure shows the timing of SPI Interface.

ns ns ns ns ns ns Figure 26: Timing of SPI Interface The related parameters of SPI timing are listed in the following table. Table 17: Parameters of SPI Interface Timing Parameter Description Typ. Max. Unit SPI clock period SPI clock high level time SPI clock low level time SPI master data input setup time SPI master data input hold time Min. 20.0 9.0 9.0 5.0 1.0

t(mov) SPI master data output valid time

-5.0 5.0 T t(ch) t(cl) t(mis) t(mih) NOTE

* means under development. EG18_Hardware_Design 54 / 104 T t(ch) t(cl) 1 2 3 4 MSB t(mov) t(mis) t(mih) SPI_CS_N SPI_CLK SPI_MOSI SPI_MISO LTE-A Module Series EG18 Hardware Design 3.12. PCM and I2C Interfaces EG18 supports audio communication via Pulse Code Modulation (PCM) digital interface and I2C interfaces. The PCM interface supports the following modes:

Primary mode (short frame synchronization, works as both master and slave) Auxiliary mode (long frame synchronization, works as master only) In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC falling edge represents the MSB. In this mode, PCM interface supports 256kHz, 512kHz, 1024kHz or 2048kHz PCM_CLK at 8kHz PCM_SYNC, and also supports 4096kHz PCM_CLK at 16kHz PCM_SYNC. In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge. The PCM_SYNC rising edge represents the MSB. In this mode, PCM interface operates with a 256kHz PCM_CLK and an 8kHz, 50% duty cycle PCM_SYNC only. EG18 supports 16-bit linear data format. The following figures show the primary modes timing relationship with 8kHz PCM_SYNC and 2048kHz PCM_CLK, as well as the auxiliary modes timing relationship with 8kHz PCM_SYNC and 256kHz PCM_CLK. Figure 27: Primary Mode Timing EG18_Hardware_Design 55 / 104 125us PCM_CLK 1 2 255 256 PCM_SYNC PCM_OUT PCM_IN MSB LSB MSB MSB LSB MSB LTE-A Module Series EG18 Hardware Design Figure 28: Auxiliary Mode Timing The following table shows the pin definition of PCM interface and I2C interface, both of which can be applied on audio codec design. Table 18: Pin Definition of PCM interface and I2C Interface Pin Name Pin No. I/O Description Comment PCM_IN 66 DI PCM data input PCM_OUT 68 DO PCM data output PCM_SYNC 65 IO PCM data frame synchronization signal 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open. 1.8V power domain. In master mode, it is an output signal. In slave mode, it is an input signal. If unused, keep it open. 1.8V power domain. In master mode, it is an output signal. In slave mode, it is an input signal. If unused, keep it open. An external pull-up resistor is required. If unused, keep it open. An external pull-up resistor is required. If unused, keep it open. Provide a digital clock output for an external audio codec. If unused, keep it open. PCM_CLK 67 IO PCM data clock I2C_SDA 42 OD I2C serial data I2C_SCL 43 OD I2C serial clock I2S_MCLK 152 DO Clock output EG18_Hardware_Design 56 / 104 125s PCM_CLK 1 2 31 32 PCM_SYNC PCM_OUT PCM_IN MSB MSB LSB LSB LTE-A Module Series EG18 Hardware Design Clock and mode can be configured by AT command, and the default configuration is master mode using short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to document [3] for details about AT+QDAI command. The following figure shows a reference design of PCM interface with an external codec IC. Figure 29: Reference Circuit of PCM Application with Audio Codec NOTES 1. It is recommended to reserve an RC (R=22, C=22pF) circuit on the PCM lines, especially for PCM_CLK. 2. EG18 works as a master device pertaining to I2C interface. 3.13. ADC Interfaces The module provides two Analog-to-Digital Converters (ADC) interfaces. AT+QADC=0 command can be executed to read the voltage value on ADC0. AT+QADC=1 command can be executed to read the voltage value on ADC1 pin. For more details about these AT+QADC commands, please refer to document [3]. EG18_Hardware_Design 57 / 104 PCM_CLK PCM_SYNC PCM_OUT PCM_IN I2C_SCL I2C_SDA S A B I MICBIAS INP INN LOUTP LOUTN BCLK LRCK DAC ADC SCL SDA Module K 7

. 4 K 7

. 4 VDD_EXT Codec LTE-A Module Series EG18 Hardware Design In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground. Table 19: Pin Definition of the ADC Interfaces Pin Name Pin No. Description ADC0 ADC1 173 175 General purpose analog to digital converter interface. If unused, keep it open. General purpose analog to digital converter interface If unused, keep it open. The following table describes characteristics of ADC interfaces. Table 20: Characteristics of ADC Interfaces Parameter Min. Typ. Max. ADC0 Voltage Range ADC1 Voltage Range 0 0 ADC Resolution 15 1.875 1.875 Unit V V bits NOTES 1. The input voltage of ADC should not exceed 1.875V. 2. 3. It is prohibited to supply any voltage to ADC pins when the power supply to VBAT is cut off. It is recommended to use resistor divider circuit for ADC application. 3.14. Network Status Indication The network indication pins can be used to drive network status indication LEDs. The following tables describe pin definition and logic level changes in different network status. Table 21: Pin Definition of Network Status/Activity Indicator Pin Name Pin No. I/O Description Comment NET_MODE 147 DO Indicate the modules network registration mode. 1.8V power domain If unused, keep it open. EG18_Hardware_Design 58 / 104 LTE-A Module Series EG18 Hardware Design NET_STATUS 170 DO Indicate the modules network activity status. 1.8V power domain If unused, keep it open. Table 22: Working State of the Network Status/Activity Indicator Pin Name Status Description NET_MODE Always High Always Low Registered on network Others Flicker slowly (200ms High/1800ms Low) Network searching NET_STATUS Flicker slowly (1800ms High/200ms Low) Idle Flicker quickly (125ms High/125ms Low) Data transfer ongoing Always High Voice calling A reference circuit is shown by the following figure. Figure 30: Reference Circuit of the Network Indicator EG18_Hardware_Design 59 / 104 Module VBAT Network Indicator 4.7K 2.2K 47K LTE-A Module Series EG18 Hardware Design 3.15. Operation Status Indication The STATUS pin is set as the module status indicator. It outputs high level voltage when the module is turned on. The following table describes pin definition of STATUS pin. Table 23: Pin Definition of STATUS Pin Name Pin No. I/O Description Comment STATUS 171 DO Indicate the modules operation status 1.8V power domain If unused, keep it open. A reference circuit is shown as below. Figure 31: Reference Circuits of STATUS NOTE 3.16. RI Behaviors AT+QCFG="risignaltype","physical" command can be executed to configure RI behaviors. No matter on which port a URC is presented, the URC will trigger the behavior of RI pin. The URC can be output from UART port, USB AT port and USB modem port by executing AT+QURCCFG command. The default port is USB AT port. EG18_Hardware_Design 60 / 104 Module STATUS 4.7K VBAT 2.2K 47K LTE-A Module Series EG18 Hardware Design In addition, RI behavior can be configured flexibly. The default behavior of the RI is shown as below. Table 24: RI Behaviors State Idle URC Response RI keeps at high level RI outputs 120ms low pulse when a new URC returns The RI behavior can be changed by executing AT+QCFG="urc/ri/ring" command. Please refer to document [3] for more details. 3.17. PCIe Interface*

EG18 provides one integrated PCIe (Peripheral Component Interconnect Express) interface which complies with the PCI Express Specification, Revision 2.1 and supports 5Gbps per lane. The PCIe interface of EG18 is only used for data transmission. PCI Express Specification Revision 2.1 compliance Data rate at 5Gbps per lane Can be used to connect to an external Ethernet IC (MAC and PHY) or WLAN IC The following table shows the pin definition of PCIe interface. Table 25: Pin Definition of the PCIe Interface Input/Output PCIe reference clock (+) Input/Output PCIe reference clock (-) Pin Name Pin No. I/O Description Comment PCIE_REFCLK_P 179 AI/AO If unused, keep it open. PCIE_REFCLK_M 180 AI/AO If unused, keep it open. PCIE_TX_M PCIE_TX_P PCIE_RX_M PCIE_RX_P 182 183 185 186 AO AO AI AI PCIe transmit (-) If unused, keep it open. PCIe transmit (+) If unused, keep it open. PCIe receive (-) If unused, keep it open. PCIe receive (+) If unused, keep it open. EG18_Hardware_Design 61 / 104 LTE-A Module Series EG18 Hardware Design PCIE_CLK_REQ_N 188 IO PCIe clock request PCIE_RST_N 189 IO PCIe reset PCIE_WAKE_N 190 IO PCIe wake In master mode, it is an input signal. In slave mode, it is an output signal. If unused, keep it open. In master mode, it is an output signal. In slave mode, it is an input signal. If unused, keep it open. In master mode, it is an input signal. In slave mode, it is an output signal. If unused, keep it open. EG18 supports either Root Complex (RC) or Endpoint (EP) Mode through software configuration. NOTE

* means under development. EG18_Hardware_Design 62 / 104 LTE-A Module Series EG18 Hardware Design 3.17.1. Root Complex Mode In this mode, the module is configured to act as a PCIe RC device. The following figure shows a reference circuit of PCIe RC mode. Figure 32: PCIe Interface Reference Circuit (RC Mode) EG18_Hardware_Design 63 / 104 Module PCIE_RX_P PCIE_RX_M C1 C2 100nF 100nF PCIE_REFCLK_P PCIE_REFCLK_M PCIE_TX_P PCIE_TX_M PCIE_RST_N PCIE_CLKREQ_N PCIE_WAKE_N C3 100nF C4 100nF VDD_EXT 2 R K 0 0 1 1 R K 0 0 1 Wi-Fi Antenna WLAN PCIE_TX_P PCIE_TX_M PCIE_RX_P PCIE_RX_M PCIE_REFCLK_P PCIE_REFCLK_M PCIE_RST_N PCIE_CLKREQ_N PCIE_WAKE_N GND GND 3 R M N LTE-A Module Series EG18 Hardware Design 3.17.2. Endpoint Mode In this mode, the module is configured to act as a PCIe EP device. The following figure shows a reference circuit of PCIe EP mode. Figure 33: PCIe Interface Reference Circuit (EP Mode) In order to ensure the signal integrity of PCIe interface, C1 and C2 have been placed inside the module. C3 and C4 should be placed close to the host, and R1, R2, R3 and R4 should be placed close to the module and also close to each other. The extra stubs of trace must be as short as possible. The following principles of PCIe interface design should be complied with, so as to meet PCIe V2.1 specifications. For USB 2.0 signal traces, the trace lengths should be less than 120mm, the differential data pair It is important to route the USB 2.0 & PCIe signal traces as differential pairs with total grounding. EG18_Hardware_Design 64 / 104 Minimize these stubs Test Points NM_0R NM_0R R3 R4 ESD Array R1 R2 0R 0R C3 100nF C4 100nF VDD_EXT 6 R K 0 0 1 5 R K 0 0 1 7 R M N PCIE_TX_P PCIE_TX_M Module USB_DM USB_DP PCIE_RX_P PCIE_RX_M C1 C2 100nF 100nF PCIE_REFCLK_P PCIE_REFCLK_M PCIE_RST_N PCIE_CLKREQ_N PCIE_WAKE_N GND Host USB_DM USB_DP PCIE_TX_P PCIE_TX_M PCIE_RX_P PCIE_RX_M PCIE_REFCLK_P PCIE_REFCLK_M PCIE_RST_N PCIE_CLKREQ_N PCIE_WAKE_N GND LTE-A Module Series EG18 Hardware Design matching should be less than 2mm (15ps). For PCIe signal traces, the maximum length of each differential data pair (TX/RX) is recommended to be less than 250mm, and each differential data pair matching should be less than 0.7mm (5ps). Do not route signal traces under crystals, oscillators, magnetic devices or RF signal traces. It is important to route the PCIe differential traces in inner-layer of the PCB, and surround the traces with ground on that layer and with ground planes above and below. If possible, reserve a 0 resistor on USB_DP and USB_DM lines, respectively. NOTE USB is required because PCIe does not support features such as firmware upgrade, GNSS NMEA output and software debugging. Firmware upgrade must be realized over USB 2.0, while GNSS NMEA output and software debugging can be realized over USB 2.0/3.0 (USB 2.0 is recommended). 3.18. SDIO Interface*

EG18 provides one SDIO interface which supports SD 3.0 protocol and eMMC*. The following table shows the pin definition. Table 26: Pin Definition of SDIO Interface Pin Name Pin No. I/O Description Comment SD_VDD 46 PO SD_DATA3 SD_DATA2 SD_DATA1 SD_DATA0 SD_CMD SD_DET SD_CLK IO IO IO IO IO DI 48 47 50 49 51 52 53 SD card application: SDIO pull up power source eMMC application: Keep it open when used for eMMC 1.8V/3.0V configurable output. Cannot be used for SD card power supply. SDIO data signal (bit 3) If unused, keep it open. SDIO data signal (bit 2) If unused, keep it open. SDIO data signal (bit 1) If unused, keep it open. SDIO data signal (bit 0) If unused, keep it open. SDIO command signal If unused, keep it open. SD card insertion detection 1.8V power domain. If unused, keep it open. DO SDIO clock signal If unused, keep it open. EG18_Hardware_Design 65 / 104 LTE-A Module Series EG18 Hardware Design The following figure shows an SDIO interface reference design. Figure 34: Reference Circuit of SD Card Application Please follow the principles below in the SD card circuit design:

The voltage range of SD power supply is 2.7V~3.6V and a sufficient current up to 0.8A should be provided. As the maximum output current of SD_VDD is 50mA which can only be used for SDIO pull-up resistors, an external power supply is needed for SD card. To avoid jitter of bus, resistors R7 to R11 are needed to pull up the SDIO to SD_VDD. Value of these resistors is among 10k~100k and the recommended value is 100k. In order to improve signal quality, it is recommended to add 0 resistors R1 to R6 in series between the module and the SD card. The bypass capacitors C1 to C6 are reserved and not mounted by default. All resistors and bypass capacitors should be placed close to the module. In order to offer good ESD protection, it is recommended to add a TVS diode on SD card pins. The load capacitance of SDIO bus needs to be less than 40pF. It is important to route the SDIO signal traces with total grounding. The impedance of SDIO data trace is 50 (10%). Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, and analog signals, as well as noisy signals such as clock signals, and DCDC signals. It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm and the total routing length less than 50mm. The total trace length inside the module is 36mm, so the exterior total trace length should be less than 14mm. Make sure the spacing between two adjacent traces is two times of the trace width and the load capacitance of SDIO bus should be less than 40pF. EG18_Hardware_Design 66 / 104 R7 100K R8 100K R9 100K R10 100K R11 100K R12 470K

C10 100F C9 100nF C8 33pF C7 10pF VDD_EXT VDD_2V85 SD Card Connector Module SD_VDD SD_DATA3 SD_DATA2 SD_DATA1 SD_DATA0 SD_CLK SD_CMD SD_DET R1 0R R2 0R R3 0R R4 0R R5 0R R6 0R C1 NM D1 C2 NM D2 C3 NM D3 C4 NM D4 C5 NM D5 D7 D6 C6 NM CD/DAT3 VDD DAT2 DAT1 DAT0 CLK CMD VSS DETECTIVE LTE-A Module Series EG18 Hardware Design 3.19. Antenna Tuner Control Interfaces*

The module provides two methods to control external antenna tuner: through RFFE signals or GPIO signals. Customers can choose either one according to their tuner design. The following table lists the pin definitions of these RFFE and GPIO signals. Table 27: Pin Definition of RFFE Interface Used to Control Antenna Tuner Pin Name Pin No. I/O Description Comment RFFE_CLK 71 RFFE_DATA 73 DO IO RFFE serial interface used for external tuner control. If unused, keep it open. If unused, keep it open. VDD_EXT 168 PO Provide 1.8V for external RF Circuit VIO. If unused, keep it open. VDD_RF 162 PO Provide 2.85V for external RF circuit. If unused, keep it open. The following figure shows sketch map of MIPI Tuner control:

Figure 32: Sketch map of MIPI Tuner control Table 28: Pin Definition of GPIO Interface Used to Control Antenna Tuner Pin Name Pin No. I/O Description Comment GPIO_3 GPIO_4 159 161 IO IO GPIO interface dedicated for external tuner control. If unused, keep it open. If unused, keep it open. EG18_Hardware_Design 67 / 104 Module RFFE_CLK RFFE_DATA 71 73 VDD_EXT 168 VDD_RF 162 Tuner SCLK SDATA VIO VDD LTE-A Module Series EG18 Hardware Design PO Provide 2.85V for external RF circuit. If unused, keep it open. If unused, keep it open. GPIO_5 VDD_RF 172 162 IO NOTE

* means under development. 3.20. USB_BOOT Interface EG18 provides a USB_BOOT pin. Developers can pull up USB_BOOT to VDD_EXT before powering on the module, to make the module enter into emergency download mode when powered on. In this mode, the module supports firmware upgrade over USB interface. Table 29: Pin Definition of USB_BOOT Interface Pin Name Pin No. I/O Description Comment USB_BOOT 140 DI Force the module to enter into emergency download mode The following figure shows a reference circuit of USB_BOOT interface. 1.8V power domain. Active high. If unused, keep it open. Figure 35: Reference Circuit of USB_BOOT Interface EG18_Hardware_Design 68 / 104 Module VDD_EXT USB_BOOT Test Point 10K Close to module TVS LTE-A Module Series EG18 Hardware Design 3.21. GPIOs In addition to the three GPIOs dedicated for external tuner control, the module provides 2 GPIOs for customers design. Table 30: Pin Definition of GPIOs Pin Name Pin No. I/O Description Comment GPIO_1 138 GPIO_2 139 IO IO General purpose input/output port If unused, keep it open. If unused, keep it open. EG18_Hardware_Design 69 / 104 LTE-A Module Series EG18 Hardware Design 4 GNSS Receiver 4.1. General Description EG18 includes a fully integrated global navigation satellite system solution that supports Gen9HT-Lite of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). EG18 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via USB interface by default. By default, EG18 GNSS engine is switched off. It has to be switched on via AT command. For more details about GNSS engine technology and configurations, please refer to document [4]. 4.2. GNSS Performance The following table shows GNSS performance of EG18. Table 31: GNSS Performance Parameter Description Conditions Sensitivity

(GNSS) TTFF

(GNSS) Cold start Autonomous Reacquisition Autonomous Tracking Autonomous Cold start

@open sky Warm start

@open sky Autonomous XTRA enabled Autonomous XTRA enabled Typ.

-147

-159

-159 35 18 30 2.5 Unit dBm dBm dBm s s s s EG18_Hardware_Design 70 / 104 LTE-A Module Series EG18 Hardware Design Autonomous XTRA enabled Autonomous

@open sky 3 2 1.5 s s m Hot start

@open sky CEP-50 Accuracy

(GNSS) 4.3. Layout Guidelines The following layout guidelines should be taken into account in customers design. Maximize the distance among GNSS antenna, main antenna and Rx-diversity antenna. Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card should be kept away from the antennas. Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar isolation and protection. Keep the characteristic impedance for ANT_GNSS trace to 50. Please refer to Chapter 5 for GNSS reference design and antenna installation. EG18_Hardware_Design 71 / 104 LTE-A Module Series EG18 Hardware Design 5 Antenna Interfaces EG18 provides a main antenna interface, an Rx-diversity antenna interface, two MIMO antenna interfaces, and a GNSS antenna interface. The impedance of antenna ports is 50. 5.1. Main/Rx-diversity/MIMO Antenna Interfaces 5.1.1. Pin Definition The pin definition of main antenna interface, Rx-diversity antenna interface and MIMO antenna interfaces is shown as below. Table 32: Pin Definition of the Main/Rx-diversity/MIMO Antenna Interfaces Pin Name Pin No. I/O Description Comment ANT_MAIN ANT_DIV ANT_MIMO1 ANT_MIMO2 107 127 101 113 IO AI AI AI Main antenna interface 50 impedance Rx-diversity antenna interface 50 impedance 44 MIMO antenna interface 50 impedance 44 MIMO antenna interface 50 impedance 5.1.2. Operating Frequencies Table 33: EG18-EA Operating Frequencies 3GPP Band Transmit WCDMA B1 1920~1980 WCDMA B3 1710~1785 WCDMA B5 WCDMA B8 824~849 880~915 Receive 2110~2170 1805~1880 869~894 925~960 Unit MHz MHz MHz MHz EG18_Hardware_Design 72 / 104 LTE-A Module Series EG18 Hardware Design 1920~1979.9 2110~2169.9 1710~1784.9 1805~1879.9 824~848.9 869~893.9 2500~2569.9 2620~2689.9 880~914.9 832~861.9 703~747.9 925~959.9 791~820.9 758~802.9 2570~2619.9 2570~2619.9 2300~2399.9 2300~2399.9 2496~2689.9 2496~2689.9 Receive 1930~1990 2110~2155 869~894 1930~1990 2110~2155 869~894 729~746 746~756 758~768 859~894 717~728 1850~1910 1710~1755 824~849 699~716 777~787 788~798 814~849

2500~2570 2620~2690 1850~1915 1930~1995 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz LTE B1 LTE B3 LTE B5 LTE B7 LTE B8 LTE B20 LTE B28 LTE B38 LTE B40 LTE B41 LTE B2 LTE B4 LTE B5 LTE B7 LTE B12 LTE B13 LTE B14 LTE B25 LTE B26 LTE B29 Table 34: EG18-NA Operating Frequencies 3GPP Band Transmit WCDMA B2 1850~1910 WCDMA B4 1710~1755 WCDMA B5 824~849 EG18_Hardware_Design 73 / 104 LTE-A Module Series EG18 Hardware Design 2305~2315 2350~2360 2496~2689.9 2496~2689.9 1710~1780 2110~2200 617~652 663~698 MHz MHz MHz MHz LTE B30 LTE B41 LTE B66 LTE B71 5.1.3. Reference Design of RF Antenna Interfaces A reference design of ANT_MAIN, ANT_DIV, ANT_MIMO1 and ANT_MIMO2 interfaces is shown as below. It should reserve a -type matching circuit for better RF performance. The -type matching components (R1/C1/C2, R2/C3/C4, R3/C5/C6, R4/C7/C8) should be placed as close to the antennas as possible and are mounted according to the actual debugging. C1 to C8 are not mounted and a 0 resistor is mounted on R1 to R4 respectively by default. Figure 36: Reference Circuit of RF Antenna Interfaces NOTE Please keep a proper distance between the main antenna and the Rx-diversity antenna to improve the receiving sensitivity. EG18_Hardware_Design 74 / 104 Module ANT_MAIN R1 0R Main Antenna ANT_DIV R2 0R Diversity Antenna R3 0R MIMO Antenna ANT_MIMO1 C1 NM C3 NM C5 NM C7 NM C2 NM C4 NM C6 NM C8 NM ANT_MIMO2 R4 0R MIMO Antenna LTE-A Module Series EG18 Hardware Design 5.2. GNSS Antenna Interface 5.2.1. Pin Definition The following tables show pin definition and frequency specification of GNSS antenna interface. Table 35: Pin Definition of GNSS Antenna Interface Pin Name Pin No. I/O Description Comment ANT_GNSS 119 AI GNSS antenna interface 50 impedance 5.2.2. GNSS Frequency Table 36: GNSS Frequency GLONASS 1597.5~1605.8 Frequency 1575.421.023 1575.422.046 1561.0982.046 1575.42 Unit MHz MHz MHz MHz MHz Type GPS Galileo BeiDou QZSS EG18_Hardware_Design 75 / 104 LTE-A Module Series EG18 Hardware Design 5.2.3. Reference Design of GNSS Antenna Interface A reference design of GNSS antenna is shown as below. Figure 37: Reference Circuit of GNSS Antenna Interface 1. An external LDO can be selected to supply power according to the active antenna requirement. 2. If the module is designed with a passive antenna, then the VDD circuit is not needed. NOTES EG18_Hardware_Design 76 / 104 VDD 0.1F 10R GNSS Antenna Module ANT_GNSS 47nH 100pF 0R NM NM LTE-A Module Series EG18 Hardware Design 5.3. Reference Design of RF Layout For users PCB, the characteristic impedance of all RF traces should be controlled to 50. The impedance of the RF traces is usually determined by the trace width (W), the materials dielectric constant, height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds

(S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB structures. Figure 38: Microstrip Design on a 2-layer PCB Figure 39: Coplanar Waveguide Design on a 2-layer PCB Figure 40: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) EG18_Hardware_Design 77 / 104 LTE-A Module Series EG18 Hardware Design Figure 41: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:

Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50. connected to ground. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully The distance between the RF pins and the RF connector should be as short as possible, and all the right-angle traces should be changed to curved ones. There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be no less than two times as wide as RF signal traces (2*W). For more details about RF layout, please refer to document [7]. 5.4. Antenna Installation 5.4.1. Antenna Requirements The following table shows the requirements on main antenna, Rx-diversity antenna and GNSS antenna. Table 37: Antenna Requirements Type Requirements GNSS 1) Frequency range: 1559MHz~1609 MHz Polarization: RHCP or linear VSWR: <2 (Typ.) Passive antenna gain: >0dBi Active antenna noise figure: <1.5dB EG18_Hardware_Design 78 / 104 LTE-A Module Series EG18 Hardware Design Active antenna gain: >0dBi Active antenna embedded LNA gain: <17dB VSWR: 2 Efficiency: >30%

Max Input Power: 50W Input Impedance: 50 Cable Insertion Loss: <1dB

(WCDMA B5/B8/, LTE B5/B8/B12/B13/B14/B20/B26/B28/B29/B71) Cable Insertion Loss: <1.5dB

(WCDMA B1/B2/B3/B4/, LTE B1/B2/B3/B4/B25/B66) Cable Insertion Loss <2dB

(LTE B7/B38/B40/B41/B30) 1) It is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use of active antenna may generate harmonics which will affect the GNSS performance. 5.4.2. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector provided by Hirose. WCDMA/LTE NOTE Figure 42: Dimensions of the U.FL-R-SMT Connector (Unit: mm) EG18_Hardware_Design 79 / 104 LTE-A Module Series EG18 Hardware Design U.FL-LP serial connector listed in the following figure can be used to match the U.FL-R-SMT. Figure 43: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mating plugs. Figure 44: Space Factor of Mating Plugs (Unit: mm) For more details, please visit http://www.hirose.com. EG18_Hardware_Design 80 / 104 LTE-A Module Series EG18 Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 38: Absolute Maximum Ratings Parameter VBAT_RF/VBAT_BB USB_VBUS Peak Current of VBAT_BB Peak Current of VBAT_RF Voltage at ADC0 Voltage at ADC1 Min.

-0.3

-0.3 0 0 0 0 Voltage at Digital Pins

-0.3 Max. Unit 4.7 5.5 1.2 1.5 2.3 1.875 1.875 V V A A V V V EG18_Hardware_Design 81 / 104 LTE-A Module Series EG18 Hardware Design 6.2. Power Supply Ratings Table 39: The Modules Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT VBAT_BB and VBAT_RF USB_VBUS USB connection detection The actual input voltages must stay between the minimum and maximum values. 3.3 3.8 4.3 V 3.3 5.0 5.25 V 6.3. Operation and Storage Temperatures The operation and storage temperatures are listed in the following table. Table 40: Operation and Storage Temperatures Parameter Min. Max. Unit Operation Temperature Range 1)

-30 Extended Operation Range 2) Storage temperature range

-40

-40 Typ.

+25

+70

+85

+90 C C C NOTES 1. 2. 1) Within operating temperature range, the module is 3GPP compliant. 2) Within extended temperature range, proper mounting, heating sinks and active cooling may be required to make certain functions of the module such as voice, SMS, data transmission to be realized. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances. When the temperature returns to normal operating temperature levels, the module will meet 3GPP specifications again. EG18_Hardware_Design 82 / 104 LTE-A Module Series EG18 Hardware Design 6.4. Current Consumption 6.4.1. EG18-EA Current Consumption Table 41: EG18-EA Current Consumption Parameter Description Conditions IVBAT OFF state Power down IVBAT Sleep state Typ. Unit 20 A AT+CFUN=0 (USB disconnected) 0.98 mA WCDMA PF=64 (USB disconnected) 2.51 mA WCDMA PF=128 (USB disconnected) 1.94 mA WCDMA PF=256 (USB disconnected) 1.62 mA WCDMA PF=512 (USB disconnected) 1.49 mA LTE-FDD PF=32 (USB disconnected) 4.32 mA LTE-FDD PF=64 (USB disconnected) 2.74 mA LTE-FDD PF=128 (USB disconnected) 2.11 mA LTE-FDD PF=256 (USB disconnected) 1.72 mA LTE-TDD PF=32 (USB disconnected) 4.39 mA LTE-TDD PF=64 (USB disconnected) 2.87 mA LTE-TDD PF=128 (USB disconnected) 2.21 mA LTE-TDD PF=256 (USB disconnected) 1.78 mA WCDMA PF=64 (USB Suspend) 2.74 mA LTE-FDD PF=64 (USB Suspend) 2.83 mA LTE-TDD PF=64 (USB Suspend) 2.96 mA WCDMA PF=64 (USB disconnected) 9.23 mA WCDMA PF=64 (USB active) 24.41 mA IVBAT Idle state LTE-FDD PF=64 (USB disconnected) 8.91 mA LTE-FDD PF=64 (USB active) 24.82 mA LTE-TDD PF=64 (USB disconnected) 9.13 mA EG18_Hardware_Design 83 / 104 LTE-A Module Series EG18 Hardware Design LTE-TDD PF=64 (USB active) 24.97 mA WCDMA B1 HSDPA CH10700 @23.4dBm 460 mA WCDMA B1 HSUPA CH10700 @23.5dBm WCDMA B3 HSDPA CH1338 @23.3dBm IVBAT WCDMA data transfer (GNSS OFF) WCDMA B3 HSUPA CH1338 @23.4dBm WCDMA B5 HSDPA CH4407 @23.4dBm WCDMA B5 HSUPA CH4407 @23.3dBm WCDMA B8 HSDPA CH3012 @23.3dBm WCDMA B8 HSUPA CH3012 @23.4dBm LTE-FDD B1 CH300 @23.4dBm LTE-FDD B3 CH1575 @23.3dBm LTE-FDD B5 CH2525 @23.1dBm LTE-FDD B7 CH3100 @23.1dBm LTE-FDD B8 CH3625 @23.2dBm LTE-FDD B20 CH6300 @23.1dBm LTE-FDD B28 CH9435 @23.1dBm LTE-TDD B38 CH38000 @23.3dBm LTE-TDD B40 CH39150 @23.2dBm LTE-TDD B41 CH40620 @23.1dBm WCDMA B1 CH10700 @23.5dBm IVBAT LTE data transfer (GNSS OFF) 460 502 508 558 539 569 571 550 606 515 764 571 540 533 352 336 339 463 502 557 569 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA IVBAT WCDMA voice call WCDMA B3 CH1338 @23.4dBm WCDMA B5 CH4407 @23.4dBm WCDMA B8 CH3012 @23.5dBm NOTE For detailed power consumption data of EG18-EA CA combinations, please refer to document [1]. EG18_Hardware_Design 84 / 104 LTE-A Module Series EG18 Hardware Design 6.4.2. EG18-NA Current Consumption Table 42: EG18-NA Current Consumption Parameter Description Conditions IVBAT OFF state Power down Typ. Unit 15 A AT+CFUN=0 (USB disconnected) 1.08 mA WCDMA PF=64 (USB disconnected) 2.53 mA WCDMA PF=128 (USB disconnected) 2.05 mA WCDMA PF=256 (USB disconnected) 1.81 mA WCDMA PF=512 (USB disconnected) 1.7 mA LTE-FDD PF=32 (USB disconnected) 4.55 mA LTE-FDD PF=64 (USB disconnected) 3.11 mA LTE-FDD PF=128 (USB disconnected) 2.45 mA LTE-FDD PF=256 (USB disconnected) 2.07 mA LTE-TDD PF=32 (USB disconnected) 4.49 mA LTE-TDD PF=64 (USB disconnected) 3.11 mA LTE-TDD PF=128 (USB disconnected) 2.44 mA LTE-TDD PF=256 (USB disconnected) 2.1 mA WCDMA PF=64 (USB Suspend) 2.89 mA LTE-FDD PF=64 (USB Suspend) 3.49 mA LTE-TDD PF=64 (USB Suspend) 3.49 mA WCDMA PF=64 (USB disconnected) 8.45 mA WCDMA PF=64 (USB active) 22.71 mA LTE-FDD PF=64 (USB disconnected) 9.07 mA LTE-FDD PF=64 (USB active) 23.41 mA LTE-TDD PF=64 (USB disconnected) 9.25 mA LTE-TDD PF=64 (USB active) 23.4 mA IVBAT Sleep state IVBAT Idle state EG18_Hardware_Design 85 / 104 LTE-A Module Series EG18 Hardware Design WCDMA B2 HSDPA CH9800 @22.89dBm 678.24 mA WCDMA B2 HSUPA CH9800 @22.94dBm 669.07 mA IVBAT WCDMA data transfer

(GNSS OFF) WCDMA B4 HSDPA CH1412 @23.22dBm 543.58 mA WCDMA B4 HSUPA CH1412 @23.2dBm 579.04 mA IVBAT LTE data transfer

(GNSS OFF) WCDMA B5 HSDPA CH4407 @23.4dBm 553.84 mA WCDMA B5 HSUPA CH4407 @23.3dBm 558.13 mA LTE-FDD B2 CH900 @23.3dBm 748.15 mA LTE-FDD B4 CH2175 @23.4dBm 652.72 mA LTE-FDD B5 CH2525 @22.83dBm 523.46 mA LTE-FDD B7 CH3100 @22.85dBm 894.89 mA LTE-FDD B12 CH5095 @22.86dBm 517.59 mA LTE-FDD B13 CH5230 @23.1dBm 587.83 mA LTE-FDD B14 CH5330 @23.35dBm 530.37 mA LTE-FDD B25 CH8365 @23.34dBm 770.79 mA LTE-FDD B26 CH8865 @23.39dBm 586.49 mA LTE-FDD B30 CH9820 @23.35dBm 797.07 mA LTE-FDD B66 CH66886 @23.24dBm 690.17 mA LTE-FDD B71 CH68786 @23.3dBm 585.93 mA LTE-TDD B41 CH40620 @22.76dBm 369.83 mA WCDMA B2 CH9800 @23.02dBm 661.07 mA IVBAT WCDMA voice call WCDMA B4 CH1412 @22.76dBm 515.02 mA WCDMA B5 CH4407 @23.11dBm 550.38 mA For detailed power consumption data of EG18-NA CA combinations, please refer to document [1]. NOTE EG18_Hardware_Design 86 / 104 LTE-A Module Series EG18 Hardware Design 6.5. RF Output Power The following table shows the RF output power of EG18. Table 43: RF Output Power Frequency Max. WCDMA bands 24dBm+1/-3dB LTE FDD bands 23dBm2dB LTE TDD bands 23dBm2dB Min.

<-50dBm

<-40dBm

<-40dBm 6.6. RF Receiving Sensitivity The following tables show conducted RF receiving sensitivity of EG18 module. 6.6.1. EG18-EA Receiving Sensitivity Table 44: EG18-EA Conducted RF Receiving Sensitivity Frequency Primary Diversity SIMO 1) 3GPP (SIMO) WCDMA B1

-110.5dBm

-111dBm

-113.5dBm

-106.7dBm WCDMA B3

-110dBm

-110.5dBm

-113.5dBm

-103.7dBm WCDMA B5

-111dBm

-112dBm

-114.5dBm

-104.7dBm WCDMA B8

-110dBm

-111.5dBm

-114dBm

-103.7dBm LTE-FDD B1 (10M)

-98.2dBm

-98.7dBm

-101.2dBm

-96.3dBm LTE-FDD B3 (10M)

-98.9dBm

-98.6dBm

-101.7dBm

-93.3dBm LTE-FDD B5 (10M)

-99.2dBm

-99.4dBm

-102.7dBm

-94.3dBm LTE-FDD B7 (10M)

-97.5dBm

-97.7dBm

-100.2dBm

-94.3dBm LTE-FDD B8 (10M)

-98.2dBm

-98.5dBm

-101.7dBm

-93.3dBm EG18_Hardware_Design 87 / 104 LTE-A Module Series EG18 Hardware Design LTE-FDD B20 (10M)

-98.7dBm

-98.8dBm

-102.2dBm

-93.3dBm LTE-FDD B28 (10M)

-99.7dBm

-99.7dBm

-102.7dBm

-94.8dBm LTE-TDD B38 (10M)

-98.2dBm

-98.5dBm

-100.7dBm

-96.3dBm LTE-TDD B40 (10M)

-98.2dBm

-98.9dBm

-100.7dBm

-96.3dBm LTE-TDD B41 (10M)

-97.2dBm

-97.4dBm

-99.7dBm

-94.3dBm 6.6.2. EG18-NA Receiving Sensitivity Table 45: EG18-NA Conducted RF Receiving Sensitivity Frequency Primary Diversity SIMO 1) 3GPP (SIMO) WCDMA B2

-110dBm

-109.5dBm

-112.5dBm

-104.7dBm WCDMA B4

-110dBm

-109.5dBm

-112.5dBm

-106.7dBm WCDMA B5

-110.5dBm

-111dBm

-113dBm

-104.7dBm LTE-FDD B2 (10M)

-98.7dBm

-97.3dBm

-101.3dBm

-94.3dBm LTE-FDD B4 (10M)

-98.6dBm

-97.8dBm

-101.2dBm

-96.3dBm LTE-FDD B5 (10M)

-98.1dBm

-100.2dBm

-102.7dBm

-94.3dBm LTE-FDD B7 (10M)

-97.5dBm

-99dBm

-99.7dBm

-94.3dBm LTE-FDD B12 (10M)

-99.6dBm

-101.2dBm

-103.0dBm

-93.3dBm LTE-FDD B13 (10M)

-99.2dBm

-101dBm

-102.6dBm

-93.3dBm LTE-FDD B14 (10M)

-98.6dBm

-101.2dBm

-102.4dBm

-93.3dBm LTE-FDD B25 (10M)

-98.4dBm

-97.7dBm

-101.3dBm

-92.8dBm LTE-FDD B26 (10M)

-99.0dBm

-100.6dBm

-102.6dBm

-93.8dBm LTE-FDD B30 (10M)

-97.3dBm

-97.5dBm

-100.2dBm LTE-TDD B41 (10M)

-96.5dBm

-96.6dBm

-99.0dBm LTE-FDD B66 (10M)

-97.7dBm

-98.4dBm

-101.2dBm LTE-FDD B71 (10M)

-100.1dBm

-100.8dBm

-102.9dBm

-95.3dBm

-94.3dBm

-95.8dBm

-93.5dBm EG18_Hardware_Design 88 / 104 LTE-A Module Series EG18 Hardware Design NOTES 1) SIMO is a smart antenna technology that uses a single antenna at the transmitter side and multiple antennas at the receiver side, which can improve Rx performance. 6.7. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is important to refer ESD handling precautions applying ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. The following table shows the modules electrostatic discharge characteristics (at temperature of 25C and relative humidity of 45%). Table 46: Electrostatic Discharge Characteristics Tested Points Contact Discharge Air Discharge Unit VBAT, GND Antenna Interfaces 5 4 Other Interfaces 0.5 10 8 1 kV kV kV 6.8. Thermal Considerations In order to achieve better performance of the module, it is recommended to comply with the following principles for thermal considerations:

For PCB design, please keep placement of the module away from heat sources, especially high power components such as ARM processor, audio power amplifier, power supply, etc. Do not place components on the opposite side of the PCB area where the module is mounted and do not fill that area with solder mask considering the need of adding heatsink when necessary. The reference ground of the area where the module is mounted should be complete, and add ground vias as many as possible for better heat dissipation. Make sure the ground pads of the module and PCB are fully connected. According to demands for specific applications, the heatsink can be mounted on the top of the module, or the opposite side of the PCB area where the module is mounted, or both of them. EG18_Hardware_Design 89 / 104 LTE-A Module Series EG18 Hardware Design The heatsink should be designed with as many fins as possible to increase heat dissipation area. Meanwhile, a thermal pad with high thermal conductivity should be used between the heatsink and module/PCB. The following figures manifest two kinds of heatsink designs for reference. Please choose one or both of them according to particular application structure. Figure 45: Reference Design of Heatsink (Heatsink at the Top of the Module) Figure 46: Reference Design of Heatsink (Heatsink at the Backside of PCB) EG18_Hardware_Design 90 / 104 EG18 Module Heatsink Heatsink Thermal Pad Shielding Cover Application Board Application Board EG18 Module Thermal Pad Thermal Pad Heatsink Application Board Shielding Cover Application Board Heatsink LTE-A Module Series EG18 Hardware Design In order to protect the components from damage, the thermal design should be optimized to guarantee that the modules internal temperature maintains below 105C constantly. AT+QTEMP command can be used to obtain the modules internal temperature. As shown in the figure below. Figure 47: Response of AT+QTEMP EG18_Hardware_Design 91 / 104 LTE-A Module Series EG18 Hardware Design The following figure shows the corresponding position of the eight temperature sensors of the EG18. Figure 48: Temperature Sensor Distribution NOTES 1. Make sure that the PCB design provides sufficient cooling solutions for the module: proper mounting, heatsinks, and active cooling may be required depending on the integrated application. 2. For more detailed guidelines on thermal design, please refer to document [8]. EG18_Hardware_Design 92 / 104 LTE-A Module Series EG18 Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm, and dimensional tolerances are 0.05mm unless otherwise specified. 7.1. Mechanical Dimensions of the Module Figure 49: Module Top and Side Dimensions (Unit: mm) EG18_Hardware_Design 93 / 104 Pin1 LTE-A Module Series EG18 Hardware Design Figure 50: Module Bottom Dimensions (Top View, Unit: mm) EG18_Hardware_Design 94 / 104 LTE-A Module Series EG18 Hardware Design 7.2. Recommended Footprint Figure 51: Recommended Footprint (Top View, Unit: mm) NOTE For easy maintenance of the module, please keep about 3mm between the module and other components in the host PCB. EG18_Hardware_Design 95 / 104 LTE-A Module Series EG18 Hardware Design 7.3. Top and Bottom Views of the Module Figure 52: Top View of the Module Figure 53: Bottom View of the Module NOTE These are rendering images of EG18. For authentic appearance, please refer to the module received from Quectel. EG18_Hardware_Design 96 / 104 LTE-A Module Series EG18 Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage EG18 is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are listed below. 1. Shelf life in vacuum-sealed bag: 12 months at <40C/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be:

Mounted within 168 hours at the factory environment of 30C/60%RH. Stored at <10% RH. 3. Devices require baking before mounting, if any circumstance below occurs:

When the ambient temperature is 23C5C and the humidity indicator card shows the humidity Device mounting cannot be finished within 168 hours at factory conditions of 30C/60%RH. is >10% before opening the vacuum-sealed bag. If baking is required, devices may be baked for 8 hours at 120C5C. As the plastic container cannot be subjected to high temperature, it should be removed from devices temperature (120C) baking. before high to IPC/JEDECJ-STD-033 for baking procedure. is desired, please refer If shorter baking time 4. NOTE EG18_Hardware_Design 97 / 104 LTE-A Module Series EG18 Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module should be 0.13-0.15mm. For more details, please refer to document

[5]. It is suggested that the peak reflow temperature is 238C ~ 245C (for SnAg3.0Cu0.5 alloy). The absolute max reflow temperature is 245C. To avoid damage to the module caused by repeated heating, it is strongly recommended that the module should be mounted after reflow soldering for the other side of PCB has been completed. Recommended reflow soldering thermal profile is shown below:

Figure 54: Reflow Soldering Thermal Profile Factor Soak Zone Max slope Table 47: Recommended Thermal Profile Parameters Recommendation 1 to 3C/sec Soak time (between A and B: 150C and 200C) 60 to 120 sec EG18_Hardware_Design 98 / 104 Temp. (C) 245 238 220 200 150 100 Soak Zone A Max slope: 1~3C/sec Reflow Zone Max slope:

2~3C/sec C Cooling down slope: 1~4C/sec B D LTE-A Module Series EG18 Hardware Design Reflow Zone Max slope Reflow time (D: over 220C) Max temperature Cooling down slope Reflow Cycle Max reflow cycle 8.3. Packaging 2 to 3C/sec 40 to 60 sec 238C ~ 245C 1 to 4C/sec 1 EG18 is packaged in tape and reel carriers. Each reel is 10.56m long and contains 200 modules. The figures below show the packaging details, measured in mm. Figure 55: Tape Specifications (Unit: mm) EG18_Hardware_Design 99 / 104 LTE-A Module Series EG18 Hardware Design Figure 56: Reel Specifications (Unit: mm) EG18_Hardware_Design 100 / 104 LTE-A Module Series EG18 Hardware Design 9 Appendix A References Table 48: Related Documents SN Document Name Remark

[1] Quectel_EG18_CA_Feature EG18 CA features.

[2] Quectel_UMTS&LTE_EVB_R2.0_User_Guide

[3] Quectel_EM12&EG12&EG18_AT_Commands_Manual

[4] Quectel_EM12&EG12&EG18_GNSS_Application_Note EVB R2.0 user guide of UMTS and LTE modules. AT commands manual for EM12, EG12 and EG18 modules. GNSS application note for EM12, EG12 and EG18 modules.

[5] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide

[6] Quectel_EM12&EG12&EG18_Reference_Design Reference design for EM12, EG12 and EG18 modules.

[7] Quectel_RF_Layout_Application_Note RF layout application note

[8] Quectel_LTE_Module_Thermal_Design_Guide Thermal design guide for LTE modules.

[9] Quectel_EG06&EG12&EG18_Difference_Introduction Difference introduction of EG06, EG12 and EG18 modules. Table 49: Terms and Abbreviations Abbreviation Description AMR bps CA Adaptive Multi-rate Bits Per Second Carrier Aggregation CHAP Challenge Handshake Authentication Protocol CPE Customer Premises Equipment EG18_Hardware_Design 101 / 104 LTE-A Module Series EG18 Hardware Design DC-HSPA+

Dual-carrier High Speed Packet Access DFOTA Delta Firmware Upgrade Over The Air Coding Scheme Circuit Switched Data Clear To Send Downlink Discontinuous Reception Data Terminal Ready Discontinuous Transmission Enhanced Full Rate Electrostatic Discharge Equivalent Series Resistance Full Rate CS CSD CTS DL DRX DTR DTX EFR ESD ESR FR GMSK GNSS GPS HR I/O Inorm LED LNA LTE GLONASS GLObalnaya NAvigatsionnaya Sputnikovaya Sistema, the Russian Global Navigation Satellite System Gaussian Minimum Shift Keying Global Navigation Satellite System Global Positioning System HO-RXD Higher-order Receiver Diversity Half Rate Input/Output Normal Current Light Emitting Diode Low Noise Amplifier Long Term Evolution MIMO Multiple Input Multiple Output EG18_Hardware_Design 102 / 104 LTE-A Module Series EG18 Hardware Design MO Mobile Originated MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor MS MT PAP PCB PDU PPP QAM SIMO SMS TDD Tx UL UMTS URC Mobile Station Mobile Terminated Password Authentication Protocol Printed Circuit Board Protocol Data Unit Point-to-Point Protocol Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SGMII Serial Gigabit Media Independent Interface Single Input Multiple Output Short Message Service Time Division Duplexing Transmitting Direction Uplink Universal Mobile Telecommunications System Unsolicited Result Code

(U)SIM Universal Subscriber Identity Module Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value EG18_Hardware_Design 103 / 104 LTE-A Module Series EG18 Hardware Design VIHmax Maximum Input High Level Voltage Value VIHmin VILmax VILmin VImax VImin Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Minimum Input Low Level Voltage Value Absolute Maximum Input Voltage Value Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value VSWR Voltage Standing Wave Ratio EG18_Hardware_Design 104 / 104 LTE-A Module Series EG18 Hardware Design OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.31 (h) and (k): The host manufacturer is responsible for additional testing to verify compliance as a composite system. When testing the host device for compliance with Part 15 Subpart B, the host manufacturer is required to show compliance with Part 15 Subpart B while the transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation should confirm that the module's intentional emissions are compliant (i.e. fundamental and out of band emissions). The host manufacturer must verify that there are no additional unintentional emissions other than what is permitted in Part 15 Subpart B or emissions are complaint with the transmitter(s) rule(s). The Grantee will provide guidance to the host manufacturer for Part 15 B requirements if needed. Important Note notice that any deviation(s) from the defined parameters of the antenna trace, as described by the instructions, require that the host product manufacturer must notify to Quectel that they wish to change the antenna trace design. In this case, a Class II permissive change application is required to be filed by the USI, or the host manufacturer can take responsibility through the change in FCC ID (new application) procedure followed by a Class II permissive change application. End Product Labeling When the module is installed in the host device, the FCC/IC ID label must be visible through a window on the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a second label must be placed on the outside of the final device that contains the following text: Contains FCC ID: XMR202002EG18NA Contains IC: 10224A-20202EG18NA The FCC ID/IC ID can be used only when all FCC/IC compliance requirements are met. Antenna Installation

(1) The antenna must be installed such that 20 cm is maintained between the antenna and users,

(2) The transmitter module may not be co-located with any other transmitter or antenna. In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for EG18_Hardware_Design 105 / 104 LTE-A Module Series EG18 Hardware Design re-evaluating the end product (including the transmitter) and obtaining a separate FCC/IC authorization. Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:

- Reorient or relocate the receiving antenna.

- Increase the separation between the equipment and receiver.

- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

- Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. List of applicable FCC rules This module has been tested and found to comply with part 22, part 24, part 27, part 90, 15.247 and 15.407 requirements for Modular Approval. The modular transmitter is only FCC authorized for the specific rule parts (i.e., FCC transmitter rules) listed on the grant, and that the host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. If the grantee markets their product as being Part 15 Subpart B compliant (when it also contains unintentional-radiator digital circuity), then the grantee shall provide a notice stating that the final host product still requires Part 15 Subpart B compliance testing with the modular transmitter installed. EG18_Hardware_Design 106 / 104 LTE-A Module Series EG18 Hardware Design This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. Radiation Exposure Statement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator &

your body. EG18_Hardware_Design 107 / 104 LTE-A Module Series EG18 Hardware Design Industry Canada Statement This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions:

(1) This device may not cause interference; and

(2) This device must accept any interference, including interference that may cause undesired operation of the device. Le prsent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorise aux deux conditions suivantes:

(1) l'appareil ne doit pas produire de brouillage, et

(2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement."

Radiation Exposure Statement This equipment complies with IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator & your body. Dclaration d'exposition aux radiations:

Cet quipement est conforme aux limites d'exposition aux rayonnements ISED tablies pour un environnement non contrl. Cet quipement doit tre install et utilis avec un minimum de 20 cm de distance entre la source de rayonnement et votre corps. This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed. Cet appareil est conu uniquement pour les intgrateurs OEM dans les conditions suivantes: (Pour utilisation de dispositif module) 1) L'antenne doit tre installe de telle sorte qu'une distance de 20 cm est respecte entre l'antenne et les utilisateurs, et EG18_Hardware_Design 108 / 104 LTE-A Module Series EG18 Hardware Design 2) Le module metteur peut ne pas tre complant avec un autre metteur ou antenne. Tant que les 2 conditions ci-dessus sont remplies, des essais supplmentaires sur l'metteur ne seront pas ncessaires. Toutefois, l'intgrateur OEM est toujours responsable des essais sur son produit final pour toutes exigences de conformit supplmentaires requis pour ce module install. IMPORTANT NOTE:

In the event that these conditions cannot be met (for example certain laptop configurations or colocation with another transmitter), then the Canada authorization is no longer considered valid and the IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate Canada authorization. NOTE IMPORTANTE:

Dans le cas o ces conditions ne peuvent tre satisfaites (par exemple pour certaines configurations d'ordinateur portable ou de certaines co-localisation avec un autre metteur), l'autorisation du Canada n'est plus considr comme valide et l'ID IC ne peut pas tre utilis sur le produit final. Dans ces circonstances, l'intgrateur OEM sera charg de rvaluer le produit final (y compris l'metteur) et l'obtention d'une autorisation distincte au Canada. End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed such that 20 cm may be maintained between the antenna and users. The final end product must be labeled in a visible area with the following: Contains IC: 10224A-20202EG18NA. Plaque signaltique du produit final Ce module metteur est autoris uniquement pour une utilisation dans un dispositif o l'antenne peut tre installe de telle sorte qu'une distance de 20cm peut tre maintenue entre l'antenne et les utilisateurs. Le produit final doit tre tiquet dans un endroit visible avec l'inscription suivante:

"Contient des IC: 10224A-20202EG18NA ". Manual Information To the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. Manuel d'information l'utilisateur final EG18_Hardware_Design 109 / 104 LTE-A Module Series EG18 Hardware Design L'intgrateur OEM doit tre conscient de ne pas fournir des informations l'utilisateur final quant la faon d'installer ou de supprimer ce module RF dans le manuel de l'utilisateur du produit final qui intgre ce module. Le manuel de l'utilisateur final doit inclure toutes les informations rglementaires requises et avertissements comme indiqu dans ce manuel. EG18_Hardware_Design 110 / 104

 

 

 

 

 

 

 

 

 

 

QUECTEL EG18-NA PA FCC ID: XMR202002EG18NA IC: 10224A-20202EG18NA SN:E1A17KF1AX0OXX1 IMEI:86481 803XXXXXX0 Q1-A4104 EG18NAPA-512-SGAS

 

 

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Applicant/Grantee Quectel Wireless Solutions Company Limited / XMR FCC ID:

XMR202002EG18NA Section 15.212 Modular Transmitters Request for Modular Approval Request for Limited Modular Approval Requirements EUT Conditions Comply (Y/N) Single Modular Approval Requirements The radio portion of this module is shielded, please see exhibition external photos. Y The module has buffer modulation/data inputs. Y The module has its own power supply regulation. Please see the schem.pdf The requirements of antenna connector and spurious emission have been fulfilled. Please refer to the Test Report exhibition. Y Y Please refer to the Setup Photo exhibition for the stand-alone test configuration. Y 1 2 3 4 5 The radio elements of the modular transmitter must have their own shielding. The physical crystal and tuning capacitors may be located external to the shielded radio elements. The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with Part 15 requirements under conditions of excessive data rates or over-modulation. The modular transmitter must have its own power supply regulation. The modular transmitter must comply with the antenna and transmission system requirements of Sections 15.203, 15.204(b) and 15.204(c). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of Section 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph (b) of this section. The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing for compliance with Part 15 requirements. Unless the transmitter module will be battery powered, it must comply with the AC line conducted requirements found in Section 15.207. AC or DC power lines and data input/output lines connected to the module must not contain ferrites, unless they will be marketed with the module (see Section 15.27(a)). The length of these lines shall be the length typical of actual use or, if that length is unknown, at least 10 centimeters to insure that there is no coupling between the case of the module and supporting 6 7 equipment. Any accessories, peripherals, or support equipment connected to the module during testing shall be unmodified and commercially available

(see Section 15.31(i)). The modular transmitter must be equipped with either a permanently affixed label or must be capable of electronically displaying its FCC identification number.

(A) If using a permanently affixed label, the modular transmitter must be labeled with its own FCC identification number, and, if the FCC identification number is not visible when the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following: Contains Transmitter Module FCC ID: XYZMODEL1 or Contains FCC ID:

XYZMODEL1. Any similar wording that expresses the same meaning may be used. The Grantee may either provide such a label, an example of which must be included in the application for equipment authorization, or, must provide adequate instructions along with the module which explain this requirement. In the latter case, a copy of these instructions must be included in the application for equipment authorization.

(B) If the modular transmitter uses an electronic display of the FCC identification number, the information must be readily accessible and visible on the modular transmitter or on the device in which it is installed. If the module is installed inside another device, then the outside of the device into which the module is installed must display a label referring to the enclosed module. This exterior label can use wording such as the following:

Contains FCC certified transmitter module(s). Any similar wording that expresses the same meaning may be used. The user manual must include instructions on how to access the electronic display. A copy of these instructions must be included in the application for equipment authorization. The modular transmitter must comply with any specific rules or operating requirements that ordinarily apply to a complete transmitter and the manufacturer must provide adequate instructions along with the module to explain any such requirements. A copy of these instructions must be included in the application for equipment authorization. The Module will be labeled with its own FCC ID, and the instruction on the labeling rule of the end product has been stated in the User Manual of this module. Please refer to the Label and User Manual exhibition. Y The required FCC rule has been fulfilled and all the instructions for maintaining compliance have been clearly stated in the User Manual. Y 8 The modular transmitter must comply with any applicable RF exposure requirements in its final configuration. Please refer exhibition RF Exposure for the compliance of MPE RF exposure rule. Y