FCC ID: XMR201912BG77 LTE Cat M1 & Cat NB2 Module

BG77 Hardware Design LPWA Module Series Rev. BG77_Hardware_Design_V1.1 Date: 2019-10-08 Status: Preliminary www.quectel.com LPWA Module Series BG77 Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters:

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http://www.quectel.com/support/technical.htm Or email to: support@quectel.com GENERAL NOTES QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION PROVIDED IS BASED UPON CUSTOMERS REQUIREMENTS. QUECTEL MAKES EVERY EFFORT TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR RELIANCE UPON THE INFORMATION. ALL INFORMATION SUPPLIED HEREIN IS SUBJECT TO CHANGE WITHOUT PRIOR NOTICE. COPYRIGHT THE INFORMATION CONTAINED HERE IS PROPRIETARY TECHNICAL INFORMATION OF QUECTEL WIRELESS SOLUTIONS CO., LTD. TRANSMITTING, REPRODUCTION, DISSEMINATION AND EDITING OF THIS DOCUMENT AS WELL AS UTILIZATION OF THE CONTENT ARE FORBIDDEN WITHOUT PERMISSION. OFFENDERS WILL BE HELD LIABLE FOR PAYMENT OF DAMAGES. ALL RIGHTS ARE RESERVED IN THE EVENT OF A PATENT GRANT OR REGISTRATION OF A UTILITY MODEL OR DESIGN. Copyright Quectel Wireless Solutions Co., Ltd. 2019. All rights reserved. BG77_Hardware_Design 1 / 76 LPWA Module Series BG77 Hardware Design About the Document History Revision Date Author Description 1.0 2019-06-17 Jake JIANG/

Newgate HUA Initial 1.1 2019-10-08 Lyndon LIU/

Watt ZHU PSM in Chapter 3.4.2. 1. Delete GNSS optional information. 2. Updated the power supply in Table 3. 3. Updated Pin Assignment in Figure 2. 4. Updated Pin Description in Table 3. 5. Added PON_TRIG pin to wake-up the module from 6. Updated the power supply in Chapter 3.5. 7. Added automatically turn-on circuit in chapter 3.61. 8. Added PON_TRIG information in chapter 3.8. 9. Added GRFC interfaces description in chapter 3.20. 10. Updated the absolute maximum ratings in Chapter 6.1. 11. Updated the power supply ratings in Chapter 6.3. BG77_Hardware_Design 2 / 76 LPWA Module Series BG77 Hardware Design Contents About the Document ................................................................................................................................ 2 Contents .................................................................................................................................................... 3 Table Index ............................................................................................................................................... 5 Figure Index .............................................................................................................................................. 7 1 Introduction ....................................................................................................................................... 9 1.1. Safety Information .................................................................................................................. 10 2 Product Concept ............................................................................................................................. 11 2.1. General Description ................................................................................................................ 11 2.2. Key Features .......................................................................................................................... 12 2.3. Functional Diagram ................................................................................................................ 13 2.4. Evaluation Board .................................................................................................................... 14 3 Application Interfaces ..................................................................................................................... 15 3.1. Pin Assignment ...................................................................................................................... 16 3.2. Pin Description ....................................................................................................................... 17 3.3. Operating Modes .................................................................................................................... 24 3.4. Power Saving ......................................................................................................................... 25 3.4.1. Airplane Mode .............................................................................................................. 25 3.4.2. Power Saving Mode (PSM).......................................................................................... 26 3.4.3. Extended Idle Mode DRX (e-I-DRX) ............................................................................ 27 3.4.4. Sleep Mode.................................................................................................................. 27 3.4.4.1. UART Application .............................................................................................. 27 3.5. Power Supply ......................................................................................................................... 28 3.5.1. Power Supply Pins ....................................................................................................... 28 3.5.2. Decrease Voltage Drop ............................................................................................... 29 3.5.3. Monitor the Power Supply ............................................................................................ 29 3.6. Power on and off Scenarios ................................................................................................... 30 3.6.1. Turn on Module Using the PWRKEY Pin ..................................................................... 30 3.6.2. Turn off Module ............................................................................................................ 32 3.6.2.1. Turn off Module Using the PWRKEY Pin ........................................................... 32 3.6.2.2. Turn off Module Using AT Command ................................................................ 32 3.7. Reset the Module* .................................................................................................................. 32 3.8. PON_TRIG Interface .............................................................................................................. 34 3.9.

(U)SIM Interface ..................................................................................................................... 35 3.10. USB Interface ......................................................................................................................... 37 3.11. UART Interfaces ..................................................................................................................... 39 3.12. PCM and I2C Interfaces* ........................................................................................................ 42 3.13. Network Status Indication ....................................................................................................... 43 3.14. STATUS ................................................................................................................................. 44 BG77_Hardware_Design 3 / 76 LPWA Module Series BG77 Hardware Design 3.15. Behaviors of RI* ..................................................................................................................... 45 3.16. USB_BOOT Interface ............................................................................................................. 45 3.17. ADC Interfaces ....................................................................................................................... 46 3.18. SPI Interface* ......................................................................................................................... 47 3.19. GPIO Interfaces* .................................................................................................................... 48 3.20. GRFC Interfaces* ................................................................................................................... 49 4 GNSS Receiver ................................................................................................................................ 50 4.1. General Description ................................................................................................................ 50 4.2. GNSS Performance ................................................................................................................ 50 4.3. Layout Guidelines ................................................................................................................... 51 5 Antenna Interfaces .......................................................................................................................... 52 5.1. Main Antenna Interface .......................................................................................................... 52 5.1.1. Pin Definition ................................................................................................................ 52 5.1.2. Operating Frequency ................................................................................................... 52 5.1.3. Reference Design of RF Antenna Interface ................................................................. 53 5.1.4. Reference Design of RF Layout ................................................................................... 54 5.2. GNSS Antenna Interface ........................................................................................................ 56 5.3. Antenna Installation ................................................................................................................ 57 5.3.1. Antenna Requirements ................................................................................................ 57 5.3.2. Recommended RF Connector for Antenna Installation ................................................ 58 6 Electrical, Reliability and Radio Characteristics .......................................................................... 60 6.1. Absolute Maximum Ratings .................................................................................................... 60 6.2. Power Supply Ratings ............................................................................................................ 60 6.3. Operation and Storage Temperatures .................................................................................... 61 6.4. Current Consumption ............................................................................................................. 61 6.5. RF Output Power .................................................................................................................... 63 6.6. RF Receiving Sensitivity ......................................................................................................... 64 6.7. Electrostatic Discharge ........................................................................................................... 65 7 Mechanical Dimensions.................................................................................................................. 66 7.1. Mechanical Dimensions of the Module ................................................................................... 66 7.2. Recommended Footprint ........................................................................................................ 68 7.3. Design Effect Drawings of the Module .................................................................................... 69 8 Storage, Manufacturing and Packaging ........................................................................................ 70 8.1. Storage ................................................................................................................................... 70 8.2. Manufacturing and Soldering .................................................................................................. 71 8.3. Packaging ............................................................................................................................... 72 9 Appendix A References .................................................................................................................. 74 BG77_Hardware_Design 4 / 76 LPWA Module Series BG77 Hardware Design Table Index TABLE 1: FREQUENCY BANDS AND GNSS TYPES OF BG77 MODULE ..................................................... 11 TABLE 2: KEY FEATURES OF BG77 MODULE .............................................................................................. 12 TABLE 3: DEFINITION OF I/O PARAMETERS ................................................................................................ 17 TABLE 4: PIN DESCRIPTION ........................................................................................................................... 17 TABLE 5: OVERVIEW OF OPERATING MODES ............................................................................................ 25 TABLE 6: VBAT AND GND PINS ...................................................................................................................... 28 TABLE 7: PIN DEFINITION OF PWRKEY ........................................................................................................ 30 TABLE 8: PIN DEFINITION OF RESET_N ....................................................................................................... 33 TABLE 9: PIN DEFINITION OF PON_TRIG INTERFACE ................................................................................ 34 TABLE 10: PIN DEFINITION OF (U)SIM INTERFACE ..................................................................................... 35 TABLE 11: PIN DEFINITION OF USB INTERFACE ......................................................................................... 37 TABLE 12: PIN DEFINITION OF MAIN UART INTERFACE ............................................................................ 40 TABLE 13: PIN DEFINITION OF DEBUG UART INTERFACE......................................................................... 40 TABLE 14: PIN DEFINITION OF GNSS UART INTERFACE ........................................................................... 40 TABLE 15: LOGIC LEVELS OF DIGITAL I/O ................................................................................................... 41 TABLE 16: PIN DEFINITION OF PCM AND I2C INTERFACES ...................................................................... 42 TABLE 17: PIN DEFINITION OF NETLIGHT .................................................................................................... 43 TABLE 18: WORKING STATE OF NETLIGHT ................................................................................................. 43 TABLE 19: PIN DEFINITION OF STATUS ....................................................................................................... 44 TABLE 20: DEFAULT BEHAVIORS OF RI ....................................................................................................... 45 TABLE 21: PIN DEFINITION OF USB_BOOT INTERFACE............................................................................. 46 TABLE 22: PIN DEFINITION OF ADC INTERFACES ...................................................................................... 47 TABLE 23: CHARACTERISTICS OF ADC INTERFACES ................................................................................ 47 TABLE 24: PIN DEFINITION OF SPI INTERFACE .......................................................................................... 48 TABLE 25: PIN DEFINITION OF GPIO INTERFACES ..................................................................................... 48 TABLE 26: LOGIC LEVELS OF GPIO INTERFACES ...................................................................................... 48 TABLE 27: PIN DEFINITION OF GRFC INTERFACES .................................................................................... 49 TABLE 28: LOGIC LEVELS OF GRFC INTERFACES ..................................................................................... 49 TABLE 29: GNSS PERFORMANCE ................................................................................................................. 50 TABLE 30: PIN DEFINITION OF MAIN ANTENNA INTERFACE ..................................................................... 52 TABLE 31: BG77 OPERATING FREQUENCY ................................................................................................. 52 TABLE 32: PIN DEFINITION OF GNSS ANTENNA INTERFACE .................................................................... 56 TABLE 33: GNSS FREQUENCY ...................................................................................................................... 56 TABLE 34: ANTENNA REQUIREMENTS ......................................................................................................... 57 TABLE 35: ABSOLUTE MAXIMUM RATINGS ................................................................................................. 60 TABLE 36: POWER SUPPLY RATINGS .......................................................................................................... 60 TABLE 37: OPERATION AND STORAGE TEMPERATURES ......................................................................... 61 TABLE 38: BG77 CURRENT CONSUMPTION ................................................................................................ 61 TABLE 39: BG77 RF OUTPUT POWER ........................................................................................................... 64 TABLE 40: BG77 CONDUCTED RF RECEIVING SENSITIVITY ..................................................................... 64 TABLE 41: ELECTROSTATIC DISCHARGE CHARACTERISTICS (25C, 45% RELATIVE HUMIDITY) ....... 65 BG77_Hardware_Design 5 / 76 LPWA Module Series BG77 Hardware Design TABLE 42: RECOMMENDED THERMAL PROFILE PARAMETERS .............................................................. 71 TABLE 43: REEL PACKAGING ........................................................................................................................ 73 TABLE 44: RELATED DOCUMENTS ............................................................................................................... 74 TABLE 45: TERMS AND ABBREVIATIONS ..................................................................................................... 74 BG77_Hardware_Design 6 / 76 LPWA Module Series BG77 Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 14 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 16 FIGURE 3: SLEEP MODE APPLICATION VIA UART ...................................................................................... 28 FIGURE 4: STAR STRUCTURE OF THE POWER SUPPLY ........................................................................... 29 FIGURE 5: TURN ON THE MODULE USING DRIVING CIRCUIT ................................................................... 30 FIGURE 6: TURN ON THE MODULE USING KEYSTROKE ........................................................................... 31 FIGURE 7: TIMING OF TURNING ON MODULE ............................................................................................. 31 FIGURE 8: TIMING OF TURNING OFF MODULE ........................................................................................... 32 FIGURE 9: TIMING OF RESET MODULE ........................................................................................................ 33 FIGURE 10: REFERENCE CIRCUIT OF RESET_N BY USING DRIVING CIRCUIT ...................................... 33 FIGURE 11: REFERENCE CIRCUIT OF RESET_N BY USING BUTTON ...................................................... 34 FIGURE 12: REFERENCE CIRCUIT OF PON_TRIG CIRCUIT ....................................................................... 35 FIGURE 13: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH AN 8-PIN (U)SIM CARD CONNECTOR

................................................................................................................................................................... 36 FIGURE 14: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH A 6-PIN (U)SIM CARD CONNECTOR 36 FIGURE 15: REFERENCE DESIGN OF USB PHY .......................................................................................... 38 FIGURE 16: REFERENCE DESIGN OF USB INTERFACE ............................................................................. 38 FIGURE 17: REFERENCE CIRCUIT WITH TRANSLATOR CHIP ................................................................... 41 FIGURE 18: REFERENCE CIRCUIT WITH TRANSISTOR CIRCUIT .............................................................. 42 FIGURE 19: REFERENCE CIRCUIT OF PCM APPLICATION WITH AUDIO CODEC ................................... 43 FIGURE 20: REFERENCE CIRCUIT OF THE NETWORK STATUS INDICATOR .......................................... 44 FIGURE 21: REFERENCE CIRCUIT OF STATUS ........................................................................................... 45 FIGURE 22: REFERENCE CIRCUIT OF USB_BOOT INTERFACE ................................................................ 46 FIGURE 23: REFERENCE CIRCUIT OF RF ANTENNA INTERFACE ............................................................ 54 FIGURE 24: MICROSTRIP LINE DESIGN ON A 2-LAYER PCB ..................................................................... 54 FIGURE 25: COPLANAR WAVEGUIDE LINE DESIGN ON A 2-LAYER PCB ................................................. 55 FIGURE 26: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE GROUND) .................................................................................................................................................. 55 FIGURE 27: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE GROUND) .................................................................................................................................................. 55 FIGURE 28: REFERENCE CIRCUIT OF GNSS ANTENNA INTERFACE ....................................................... 57 FIGURE 29: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) ............................................... 58 FIGURE 30: MECHANICALS OF U.FL-LP CONNECTORS ............................................................................. 59 FIGURE 31: SPACE FACTOR OF MATED CONNECTOR (UNIT: MM) .......................................................... 59 FIGURE 32: MODULE TOP AND SIDE DIMENSIONS .................................................................................... 66 FIGURE 33: MODULE BOTTOM DIMENSIONS (BOTTOM VIEW) ................................................................. 67 FIGURE 34: RECOMMENDED FOOTPRINT (TOP VIEW) .............................................................................. 68 FIGURE 35: TOP VIEW OF THE MODULE ...................................................................................................... 69 FIGURE 36: BOTTOM VIEW OF THE MODULE .............................................................................................. 69 FIGURE 37: RECOMMENDED REFLOW SOLDERING THERMAL PROFILE ............................................... 71 FIGURE 38: TAPE DIMENSIONS ..................................................................................................................... 72 BG77_Hardware_Design 7 / 76 LPWA Module Series BG77 Hardware Design FIGURE 39: REEL DIMENSIONS ..................................................................................................................... 73 BG77_Hardware_Design 8 / 76 LPWA Module Series BG77 Hardware Design 1 Introduction This document defines BG77 module and describes its air interface and hardware interfaces which are connected with customers applications. This document can help customers quickly understand the interface specifications, electrical and mechanical details, as well as other related information of BG77. To facilitate its application in different fields, reference design is also provided for customers reference. Associated with application notes and user guides, customers can use the module to design and set up mobile applications easily. BG77_Hardware_Design 9 / 76 LPWA Module Series BG77 Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating BG77. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product. If not so, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be given to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If the device offers an Airplane Mode, then it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on boarding the aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signals and cellular network cannot be guaranteed to connect in all possible conditions (for example, with unpaid bills or with an invalid (U)SIM card). When emergent help is needed in such conditions, please remember using emergency call. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV set, radio, computer or other electric equipment. In locations with potentially explosive atmospheres, obey all posted signs to turn off wireless devices such as your phone or other cellular terminals. Areas with potentially explosive atmospheres include fueling areas, below decks on boats, fuel or chemical transfer or storage facilities, areas where the air contains chemicals or particles such as grain, dust or metal powders, etc. BG77_Hardware_Design 10 / 76 1.2 FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met:

1. This Modular Approval is limited to OEM installation for mobile and fixed applications only. The antenna installation and operating configurations of this transmitter, including any applicable source-based time- averaging duty factor, antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements of 2.1091. 2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the users body and must not transmit simultaneously with any other antenna or transmitter. 3.A label with the following statements must be attached to the host end product: This device contains FCC ID: XMR201912BG77. 4.To comply with FCC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed:

Catm LTE Band2/25:11.000dBi Catm LTE Band4/66:8.000dBi Catm LTE Band5:12.416dBi Catm LTE Band12:11.734dBi Catm LTE Band13:12.173dBi Catm LTE Band14:12.255 dBi Catm LTE Band26:15.013 dBi Catm LTE Band85:12.770 dBi NB LTE Band2/25:11.000dBi NB LTE Band4/66:8.000dBi NB LTE Band5/26:15.013dBi NB LTE Band12/85:12.416dBi NB LTE Band13:11.734dBi BNLTE Band14:12.272 dBi NB LTE Band71:11.447 dBi NB LTE Band85:12.770 dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093 If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations. For this device, OEM integrators must be provided with labeling instructions of finished products. Please refer to KDB784748 D01 v07, section 8. Page 6/7 last two paragraphs:

A certified modular has the option to use a permanently affixed label, or an electronic label. For a permanently affixed label, the module must be labeled with an FCC ID -

Section 2.926 (see 2.2 Certification (labeling requirements) above). The OEM manual must provide clear instructions explaining to the OEM the labeling requirements, options and OEM user manual instructions that are required (see next paragraph). For a host using a certified modular with a standard fixed label, if (1) the modules FCC ID is not visible when installed in the host, or (2) if the host is marketed so that end users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible; then an additional permanent label referring to the enclosed module:Contains Transmitter Module FCC ID:

XMR201912BG77 or Contains FCC ID: XMR201912BG77 must be used. The host OEM user manual must also contain clear instructions on how end users can find and/or access the module and the FCC ID. The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The users manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. In cases where the manual is provided only in a form other than paper, such as on a computer disk or over the Internet, the information required by this section may be included in the manual in that alternative form, provided the user can reasonably be expected to have the capability to access information in that form. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the manufacturer could void the users authority to operate the equipment. LPWA Module Series BG77 Hardware Design 2 Product Concept 2.1. General Description BG77 is an embedded IoT (LTE Cat M1, LTE Cat NB2) wireless communication module. It provides data connectivity on LTE-FDD network, and supports half-duplex operation in LTE network. It also provides GNSS and voice 1) functionality to meet customers specific application demands. Table 1: Frequency Bands and GNSS Types of BG77 Module Module Supported Bands LTE Bands Power Class GNSS BG77 Power Class 5 (21dBm) GPS, GLONASS, BeiDou, Galileo, QZSS Cat M1:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B14/B18/

B19/B20/B25/B26*/ B27/B28/B66/B85 Cat NB2 2):

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/

B20/B25/B26*/B28/B66/B71/B85 NOTES 1. 2. 3. 1) BG77 supports VoLTE (Voice over LTE) under LTE Cat M1. This voice function is still under development. 2) LTE Cat NB2 is backward compatible with LTE Cat NB1.

* means under development. With a compact profile of 14.9mm 12.9mm 1.7mm, BG77 can meet almost all requirements for M2M applications such as smart metering, tracking system, security, wireless POS, etc. It is especially suitable for size and weight sensitive applications such as smart watch and other wearable devices. BG77 is an SMD type module which can be embedded into applications through its 94 LGA pads. It supports internet service protocols like TCP, UDP and PPP. Extended AT commands have been developed for customers to use these internet service protocols easily. BG77_Hardware_Design 11 / 76 LPWA Module Series BG77 Hardware Design 2.2. Key Features The following table describes the detailed features of BG77 module. Table 2: Key Features of BG77 Module Features Details Power Supply Supply voltage: 2.6V~4.8V Typical supply voltage: 3.3V Transmitting Power Class 5 (21dBm+1/-3dB) for LTE-FDD bands LTE Features Support 3GPP Rel. 14 Support LTE Cat M1 and LTE Cat NB2 Support 1.4MHz RF bandwidth for LTE Cat M1 Support 200KHz RF bandwidth for LTE Cat NB2on Cat M1: Max. 588Kbps (DL)/1119Kbps (UL) Cat NB2: Max. 127Kbps (DL)/158.5Kbps (UL) Support PPP/TCP/UDP/SSL/TLS/FTP(S)/HTTP(S)/NITZ/PING/MQTT/

Internet Protocol Features CoAP protocols Support PAP

(Password Authentication Protocol) and CHAP

(Challenge Handshake Authentication Protocol) protocols which are usually used for PPP connections SMS Text and PDU mode Point to point MO and MT SMS cell broadcast SMS storage: ME by default

(U)SIM Interface Support 1.8V USIM/SIM card only Audio Feature Support one digital audio interface: PCM interface*

USB Interface UART Interfaces Compliant with USB 2.0 specification (slave only) Support operations at low-speed and full-speed Used for AT command communication, data transmission, GNSS NMEA output, software debugging and firmware upgrade Support USB serial drivers for Windows 7/8/8.1/10, Linux 2.6/3.x (3.4 or later)/4.1~4.15, Android 4.x/5.x/6.x/7.x/8.x/9.x Main UART:

Used for data transmission and AT command communication 115200bps baud rate by default The default frame format is 8N1 (8 data bits, no parity, 1 stop bit) Support RTS and CTS hardware flow control Debug UART:

BG77_Hardware_Design 12 / 76 LPWA Module Series BG77 Hardware Design Used for software debugging and log output Support 115200bps baud rate GNSS UART:

Used for GNSS data and NMEA sentences output 115200bps baud rate by default AT Commands 3GPP TS 27.007 and 3GPP TS 27.005 AT commands, as well as Quectel enhanced AT commands Network Indication One NETLIGHT pin for network connectivity status indication Antenna Interfaces Main antenna (ANT_MAIN) and GNSS antenna (ANT_GNSS) interfaces Physical Characteristics Temperature Range Size: (14.90.15)mm (12.90.15)mm (1.70.2)mm Weight: approx. 0.73g Operation temperature range: -35C ~ +75C 1) Extended temperature range: -40C ~ +85C 2) Storage temperature range: -40C ~ +90C Firmware Upgrade USB interface and DFOTA*

RoHS All hardware components are fully compliant with EU RoHS directive NOTES 1. * means under development. 2. 1) Within operation temperature range, the module is 3GPP compliant. 3. 2) Within extended temperature range, the module remains the ability to establish and maintain a voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances. When the temperature returns to the normal operating temperature levels, the module will meet 3GPP specifications again. 2.3. Functional Diagram The following figure shows a block diagram of BG77 and illustrates the major functional parts. Power management Baseband Radio frequency Peripheral interfaces BG77_Hardware_Design 13 / 76 LPWA Module Series BG77 Hardware Design ANT_MAIN ANT_GNSS C O U P L E R SAW+LNA GNSS Transceiver/PA/switch IQ Control Baseband VBAT PWRKEY RESET_N PON_TRIG ADC1 ADC0 PMIC Control 19.2M XO NOTES VDD_EXT USB (U)SIM PCM UARTs I2C GPIOs SPI STATUS NETLIGHT Figure 1: Functional Diagram 1. PWRKEY output voltage is 1.5V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, PWRKEY should never be pulled down to GND permanently. 2. RESET_N is multiplexed from PWRKEY. 2.4. Evaluation Board In order to help customers to develop applications conveniently with BG77, Quectel supplies the evaluation board (EVB), USB to RS-232 converter cable, USB data cable, earphone, antenna and other peripherals to control or test the module. For more details, please refer to document [1]. BG77_Hardware_Design 14 / 76 LPWA Module Series BG77 Hardware Design 3 Application Interfaces

(U)SIM interface BG77 is equipped with 94 LGA pads that can be connected to customers cellular application platforms. The following sub-chapters will provide detailed description of interfaces listed below:

Power supply USB interface UART interfaces PCM and I2C interfaces*

Status indication USB_BOOT interface ADC interfaces GPIO interfaces*

GRFC interfaces*

NOTE

* means under development. BG77_Hardware_Design 15 / 76 LPWA Module Series BG77 Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of BG77. 32 ANT_GNSS 72 PON_TRIG 26 ANT_MAIN 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 33 34 35 36 37 38 39 40 56 55 54 53 57 58 59 60 61 62 63 73 74 75 76 77 78 85 86 87 88 89 72 64 94 93 92 91 90 84 83 82 81 80 79 71 70 69 68 67 66 65 41 42 43 44 52 51 50 49 48 47 46 45 25 24 23 22 21 20 19 18 17 1 GPIO1 33 GPIO2 2 PCM_DIN 57 GPIO3 34 PCM_DOUT 3 PCM_CLK 35 PCM_SYNC 4 GNSS_RXD 36 GNSS_TXD 5 I2C_SDA 60 DBG_TXD 87 USB_BOOT 37 I2C_SCL 76 RI 6 RXD 61 DBG_RXD 38 RTS 77 AP_READY 7 TXD 62 DTR 39 CTS 78 STATUS 8 SPI_MISO 63 SPI_CS 40 SPI_MOSI 9 SPI_CLK GRFC2 94 GRFC1 83 VDD_EXT 21 VBAT 20 VBAT 19 DCD 90 NETLI GHT 79 PWRKEY 46 USIM_GND 65 ADC1 18 RESET_N 45 ADC0 17 10 11 12 13 14 15 16 64 EXT_PWR_EN 41 42 W_DISABLE#

USB_VDDA_3P3 44 USIM_DET 10 11 12 USB_DM USB_DP USB_VBUS 4) 13 14 15 16 USIM_CLK USIM_DATA USIM_RST USIM_VDD POWER USIM USB USB PCM UART ANT I2C SPI RESERVED GND OTHERS Figure 2: Pin Assignment (Top View) NOTES 1. PWRKEY output voltage is 1.5V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, PWRKEY should never be pulled down to GND permanently. 2. RESET_N is multiplexed from PWRKEY . BG77_Hardware_Design 16 / 76 LPWA Module Series BG77 Hardware Design 3. ADC input voltage must not exceed 1.8V 4. The input voltage range of USB_VBUS is 1.3V~1.8V. 5. Keep all RESERVED pins and unused pins unconnected. 6. GND pins should be connected to ground in the design. 7. W_DISABEL#, AP_READY, USIM_DET, PCM, I2C, GRFC and GPIO functions are under 8. SPI_MOSI(pin40), NETLIGHT(pin79) and GPRC1(pin83) are BOOT_CONFIG pins, They should not development. be pulled up before startup. 3.2. Pin Description The following tables show the pin definition and description of BG77. Table 3: Definition of I/O Parameters Type AI AO DI DO IO OD PI PO Description Analog Input Analog Output Digital Input Digital Output Bidirectional Open Drain Power Input Power Output Table 4: Pin Description Power Supply Pin No. Pin Name I/O Description DC Characteristics Comment VBAT 19, 20 PI Power supply for the module Vmax=4.8V Vmin=2.6V Vnorm=3.3V BG77_Hardware_Design 17 / 76 22~25, 27, 28, 30, 31, 43, 47, 52~56, 58, 66, 73~75, 84~86, 88, 89 Pin No. Pin No. Pin No. LPWA Module Series BG77 Hardware Design VDD_EXT 21 PO Vnorm=1.8V IOmax=50mA 1.8V output power supply for external circuit Power supply for external GPIOs pull-up circuits. If unused, keep this pin open. GND Ground Turn on/off Reset Pin Name I/O Description DC Characteristics Comment PWRKEY 46 DI Turn on/off the module Vnorm=1.5V VILmax=0.45V PWRKEY should never be pulled down to GND permanently. Pin Name I/O Description DC Characteristics Comment RESET_N 45 DI Reset the module Vnorm=1.5V VILmax=0.45V Status Indication Pin Name I/O Description DC Characteristics Comment STATUS 78 DO NETLIGHT 79 DO USB Interface Indicate the modules operation status Indicate the modules network activity status VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V 1.8V power domain. If unused, keep this pin open. it up BOOT_CONFIG. Do not pull before startup. 1.8V power domain. If unused, keep this pin open. Pin Name Pin I/O Description DC Characteristics Comment BG77_Hardware_Design 18 / 76 LPWA Module Series BG77 Hardware Design No. Pin No. USB_VBUS 12 AI USB detection VIHmax=1.8V VIHmin=1.3V USB_DP 11 IO USB_DM 10 IO USB differential data bus (+) USB differential data bus (-) Power for USB PHY circuit Compliant with USB 2.0 standard specification. Require differential impedance of 90. USB_VDDA_3P3 42 PI Vnorm=3.3V EXT_PWR_EN 64 DO 1.8V power domain. External LDO enable of USB VOLmax=0.45V VOHmin=1.35V

(U)SIM Interface Pin Name I/O Description DC Characteristics Comment USIM_DET 44 DI USIM_VDD 16 PO USIM_RST 15 DO

(U)SIM card insertion detection VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V Power supply for (U)SIM card Vmax=1.9V Vmin=1.7V Reset signal of

(U)SIM card VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep this pin open. The pin function is under development. Only 1.8V (U)SIM card is supported. 1.8V power domain. USIM_DATA 14 IO 1.8V power domain. VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V Data signal of

(U)SIM card Specified ground for

(U)SIM card USIM_CLK 13 DO 1.8V power domain. Clock signal of

(U)SIM card VOLmax=0.45V VOHmin=1.35V USIM_GND 65 Main UART Interface Pin No. DTR 62 DI Pin Name I/O Description DC Characteristics Comment Data terminal ready. Sleep mode control. VILmin=-0.3V VILmax=0.6V VIHmin=1.2V 1.8V power domain. If unused, keep this pin open. BG77_Hardware_Design 19 / 76 LPWA Module Series BG77 Hardware Design 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. RXD 6 DI Receive data TXD 7 DO Transmit data CTS 39 DO Clear to send RTS 38 DI Request to send VIHmax=2.0V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V DCD 90 DO Data carrier detection VOLmax=0.45V VOHmin=1.35V RI 76 DO Ring indication signal VOLmax=0.45V VOHmin=1.35V Debug UART Interface Pin No. Pin No. Pin Name I/O Description DC Characteristics Comment DBG_RXD 61 DI Receive data DBG_TXD 60 DO Transmit data GNSS UART Interface VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. Pin Name I/O Description DC Characteristics Comment GNSS_UART_TXD 36 DO Transmit data GNSS_UART_RXD 4 DI Receive data VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. BG77_Hardware_Design 20 / 76 LPWA Module Series BG77 Hardware Design PCM Interface*

Pin No. Pin Name I/O Description DC Characteristics Comment PCM_CLK 3 DO PCM clock output VOLmax=0.45V VOHmin=1.35V PCM_SYNC 35 DO PCM frame synchronization output PCM_DIN 2 DI PCM data input VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V PCM_DOUT 34 DO PCM data output VOLmax=0.45V VOHmin=1.35V I2C Interface*

Pin Name I/O Description DC Characteristics Comment I2C_SCL 37 OD I2C_SDA 5 OD Antenna Interfaces I2C serial clock. Used for external codec. I2C serial data. Used for external codec. ANT_MAIN 26 IO ANT_GNSS 32 AI Main antenna interface GNSS antenna interface SPI Interface*

Pin No. Pin No. Pin No. Pin Name I/O Description DC Characteristics Comment 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. External pull-up resistor is required. 1.8V only. If unused, keep this pin open. External pull-up resistor is required. 1.8V only. If unused, keep this pin open. 50 impedance 50 impedance. If unused, keep this pin open. Pin Name I/O Description DC Characteristics Comment BG77_Hardware_Design 21 / 76 LPWA Module Series BG77 Hardware Design Pin Name I/O Description DC Characteristics Comment SPI_MOSI 40 DO SPI master-out slave-in VOLmax=0.45V VOHmin=1.35V SPI_MISO 8 DI SPI master-in slave-out SPI_CS_N 63 DO SPI chip select SPI_CLK 9 DO SPI clock GPIO Interfaces*

Pin No. GPIO1 1 IO GPIO2 33 IO GPIO3 57 IO General-

purpose input/

output interface General-

purpose input/

output interface General-

purpose input/

output interface VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V it up BOOT_CONFIG. Do not pull before startup . 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. ADC Interfaces Pin No. Pin Name I/O Description DC Characteristics Comment ADC0 17 AI General purpose analog Voltage range:

0.1V to 1.8V If unused, keep this pin open. BG77_Hardware_Design 22 / 76 LPWA Module Series BG77 Hardware Design to digital converter interface General purpose analog to digital converter interface ADC1 18 AI Voltage range:

0.1V to 1.8V If unused, keep this pin open. Other Interface Pins Pin No. Pin Name I/O Description DC Characteristics Comment W_DISABLE#

41 DI Airplane mode control VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V AP_READY 77 DI USB_BOOT 87 DI Application processor sleep state detection VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V Force the module to enter into emergency download mode VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V PON_TRIG 72 DI Wake up the module from PSM 1.8V power domain. Pulled up by default. When it is in low voltage level, the module can enter into airplane mode. If unused, keep this pin open. The pin function is under development 1.8V power domain. If unused, keep this pin open. The pin function is under development 1.8V power domain. If unused, keep this pin open. 1.8V power domain. Rising-edge triggered. Pulled-down by default. If unused, keep this pin open. GRFC pins*

Pin No. Pin Name I/O Description DC Characteristics Comment GRFC1 83 DO General RF control VOLmax=0.45V VOHmin=1.35V BOOT_CONFIG. Do not pull it up BG77_Hardware_Design 23 / 76 LPWA Module Series BG77 Hardware Design interface before startup 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. GRFC2 94 DO RESERVED Pins General RF control interface VOLmax=0.45V VOHmin=1.35V Pin Name I/O Description DC Characteristics Comment RESERVED Reserved Keep these pins open. Pin No. 29, 48~51, 59, 67~71, 80~82, 91~93 NOTES 1. PWRKEY output voltage is 1.5V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, PWRKEY should never be pulled down to GND permanently. 2. RESET_N is multiplexed from PWRKEY. 3. The input voltage range of USB_VBUS is 1.3V ~ 1.8V. 4. USB_VDDA_3P3 and EXT_PWR_EN pins are used for USB PHY circuits. 5. W_DISABEL#, AP_READY, USIM_DET, PCM, I2C, GRFC and GPIO functions are under development. 6. SPI_MOSI(pin40), NETLIGHT(pin79) and GPRC1(pin83) are BOOT_CONFIG pins, They should not be pulled up before startup. 7. ADC input voltage must not exceed 1.8V. 8. Keep all RESERVED pins and unused pins unconnected. 9. * means under development. 3.3. Operating Modes The table below briefly summarizes the various operating modes of BG77. BG77_Hardware_Design 24 / 76 LPWA Module Series BG77 Hardware Design Table 5: Overview of Operating Modes Mode Details Normal Operation Connected Network has been connected. In this mode, the power consumption may vary with the network setting and data transfer rate. Idle Software is active. The module remains registered on network, and it is ready to send and receive data. Extended Idle Mode DRX

(e-I-DRX) BG77 module and the network may negotiate over non-access stratum signaling the use of e-I-DRX for reducing power consumption, while being available for mobile terminating data and/or network originated procedures within a certain delay dependent on the DRX cycle value. Airplane Mode AT+CFUN=4 or W_DISABLE# pin can set the module into airplane mode. In this case, RF function will be invalid. Minimum Functionality Mode Sleep Mode*

AT+CFUN=0 can set the module into a minimum functionality mode without removing the power supply. In this case, both RF function and (U)SIM card will be invalid. In this mode, the current consumption of the module will be reduced to a lower level. During this mode, the module can still receive paging message, SMS and TCP/UDP data from the network normally. Power Saving Mode

(PSM) BG77 module may enter into Power Saving Mode to further reduce its power consumption. PSM is similar to power-off, but the module remains registered on the network and there is no need to re-attach or re-establish PDN connections. Power OFF Mode In this mode, the power management unit shuts down the power supply. Software is not active. The serial interfaces are not accessible. But the operating voltage

(connected to VBAT) remains applied. NOTES 1. During e-I-DRX, it is recommended to use UART interface for data communication, as the use of USB interface will increase power consumption. 2. W_DISABLE# function is still under development. 3.4. Power Saving 3.4.1. Airplane Mode When the module enters into airplane mode, the RF function does not work, and all AT commands correlative with RF function will be inaccessible. This mode can be set via the following ways. BG77_Hardware_Design 25 / 76 LPWA Module Series BG77 Hardware Design W_DISABLE# is pulled up by default. Driving it to low level will let the module enter into airplane mode. AT+CFUN=<fun> provides choice of the functionality level, through setting <fun> into 0, 1 or 4. AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled. AT+CFUN=1: Full functionality mode (by default). AT+CFUN=4: Airplane mode. RF function is disabled. Hardware:

Software:

NOTES 1. Airplane mode control via W_DISABLE# is disabled in firmware by default. It can be enabled by AT+QCFG="airplanecontrol" command which is still under development. Details about the command will be provided in document [2]. W_DISABLE# function is also under development. 2. The execution of AT+CFUN command will not affect GNSS function. 3.4.2. Power Saving Mode (PSM) BG77 module can enter into PSM for reducing its power consumption. The mode is similar to power-off, but the module remains registered on the network and there is no need to re-attach or re-establish PDN connections. So BG77 in PSM cannot immediately respond users requests. When the module wants to use the PSM it shall request an Active Time value during every Attach and TAU procedures. If the network supports PSM and accepts that the module uses PSM, the network confirms usage of PSM by allocating an Active Time value to the module. If the module wants to change the Active Time value, e.g. when the conditions are changed in the module, the module consequently requests the value it wants in the TAU procedure. If PSM is supported by the network, then it can be enabled via AT+CPSMS command. Either of the following methods will wake up the module from PSM:

A rising edge on PON_TRIG will wake up the module from PSM. (Recommended) Drive PWRKEY pin low will wake up the module. When the T3412_Ext timer expires, the module will be woken up automatically. NOTES Please refer to document [2] for details about AT+CPSMS command. BG77_Hardware_Design 26 / 76 LPWA Module Series BG77 Hardware Design 3.4.3. Extended Idle Mode DRX (e-I-DRX) The module (UE) and the network may negotiate over non-access stratum signalling the use of e-I-DRX for reducing its power consumption, while being available for mobile terminating data and/or network originated procedures within a certain delay dependent on the DRX cycle value. Applications that want to use e-I-DRX need to consider specific handling of mobile terminating services or data transfers, and in particular they need to consider the delay tolerance of mobile terminated data. In order to negotiate the use of e-I-DRX, the UE requests e-I-DRX parameters during attach procedure and RAU/TAU procedure. The EPC may reject or accept the UE request for enabling e-I-DRX. In case the EPC accepts e-I-DRX, the EPC based on operator policies and, if available, the e-I-DRX cycle length value in the subscription data from the HSS, may also provide different values of the e-I-DRX parameters than what was requested by the UE. If the EPC accepts the use of e-I-DRX, the UE applies e-I-DRX based on the received e-I-DRX parameters. If the UE does not receive e-I-DRX parameters in the relevant accept message because the EPC rejected its request or because the request was received by EPC not supporting e-I-DRX, the UE shall apply its regular discontinuous reception. If e-I-DRX is supported by the network, then it can be enabled by AT+CEDRXS=1 command. Please refer to document [2] for details about AT+CEDRXS command. NOTE 3.4.4. Sleep Mode 3.4.4.1. UART Application BG77 is able to reduce its current consumption to a lower value during the sleep mode. The following sub-chapters describe the power saving procedure of BG77 module. If the host communicates with module via UART interface, the following preconditions can let the module enter into sleep mode. Execute AT+QSCLK=1 command to enable sleep mode. Drive DTR to high level. The following figure shows the connection between the module and the host. BG77_Hardware_Design 27 / 76 LPWA Module Series BG77 Hardware Design Figure 3: Sleep Mode Application via UART When BG77 has URC to report, RI signal will wake up the host. Please refer to Chapter 3.14 for details about RI behavior. Driving the host DTR to low level will wake up the module. AP_READY will detect the sleep state of the host (can be configured to high level or low level detection). Please refer to AT+QCFG="apready" command in document [2] for details. NOTE AP_READY function is still under development. 3.5. Power Supply 3.5.1. Power Supply Pins BG77 provides two VBAT pins for connection with an external power supply. The following table shows the details of VBAT pins and ground pins. Table 6: VBAT and GND Pins Pin Name Pin No. Description Min. Typ. Max. Unit VBAT 19, 20 2.6 3.3 4.8 V Power supply for the module GND Ground

22~25, 27, 28, 30, 31, 47, 52~56, 58, 66, 73~75, 84~86, 88, 89 BG77_Hardware_Design 28 / 76 LPWA Module Series BG77 Hardware Design 3.5.2. Decrease Voltage Drop The power supply range of BG77 is from 2.6V to 4.8V. Please make sure that the input voltage will never drop below 2.6V. To decrease voltage drop, a bypass capacitor of about 100F with low ESR should be used, and a multi-layer ceramic chip capacitor (MLCC) array should also be reserved due to its low ESR. It is recommended to use three ceramic capacitors (100nF, 33pF, 10pF) for composing the MLCC array, and place these capacitors close to VBAT pins. The main power supply from an external application has to be a single voltage source and can be expanded to two sub paths with star structure. The width of VBAT trace should be no less than 1mm. In principle, the longer the VBAT trace is, the wider it will be. In addition, in order to get a stable power source, it is suggested to use a TVS with low leakage current and suitable reverse stand-off voltage, and also it is recommended to place it as close to the VBAT pins as possible. The following figure shows the star structure of the power supply. VBAT Module R1 0R

C1 D1 TVS C2 C3 C4 100uF 100nF 33pF 10pF VBAT Figure 4: Star Structure of the Power Supply 3.5.3. Monitor the Power Supply AT+CBC* command can be used to monitor the VBAT voltage value. For more details, please refer to document [2]. NOTE BG77_Hardware_Design 29 / 76 LPWA Module Series BG77 Hardware Design

* means under development. 3.6. Power on and off Scenarios 3.6.1. Turn on Module Using the PWRKEY Pin The following table shows the pin definition of PWRKEY. Table 7: Pin Definition of PWRKEY Pin Name Pin No. Description DC Characteristics Comment PWRKEY 46 Turn on/off the module Vnorm=1.5V VILmax=0.45V The output voltage is 1.5V because of the voltage drop inside the Qualcomm chipset. When BG77 is in power off mode, it can be turned on to normal mode by driving the PWRKEY pin to a low level for a duration between 500ms and 1000ms. It is recommended to use an open drain/collector driver to control the PWRKEY. A simple reference circuit is illustrated in the following figure. 500ms~1000ms Turn on pulse 4.7K PWRKEY 10nF 47K Figure 5: Turn on the Module Using Driving Circuit Another way to control the PWRKEY is using a button directly. When pressing the key, electrostatic strike may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the button for ESD protection. A reference circuit is shown in the following figure. BG77_Hardware_Design 30 / 76 LPWA Module Series BG77 Hardware Design Figure 6: Turn on the Module Using Keystroke The power on timing is illustrated in the following figure. NOTE VBA T 500ms~1000ms PWRKEY VIL0.45V RESET_N STATUS

(DO) Typ. 2.1s USB Inactive Active Typ. 2.55s Typ. 2.5s UART Inactive Active Figure 7: Timing of Turning on Module NOTES 30ms. 1. Make sure that VBAT is stable before pulling down PWRKEY pin and keep the interval no less than 2. PWRKEY output voltage is 1.5V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, PWRKEY should never be pulled down to GND permanently. BG77_Hardware_Design 31 / 76 LPWA Module Series BG77 Hardware Design 3.6.2. Turn off Module Either of the following methods can be used to turn off the module:

Normal power down procedure: Turn off the module using the PWRKEY pin. Normal power down procedure: Turn off the module using AT+QPOWD command. 3.6.2.1. Turn off Module Using the PWRKEY Pin Driving the PWRKEY pin to a low level voltage for a duration between 650ms and 1500ms, the module will execute power-down procedure after the PWRKEY is released. The power-off timing is illustrated in the following figure. VBA T PWRKEY STATUS Module Status 650ms~1500ms VIL0.45V 1.3s RUNNING Power-down procedure OFF Figure 8: Timing of Turning off Module 3.6.2.2. Turn off Module Using AT Command It is also a safe way to use AT+QPOWD command to turn off the module, which is similar to turning off the module via PWRKEY pin. Please refer to document [2] for details about AT+QPOWD command. 3.7. Reset the Module*

RESET_N, which is multiplexed from PWRKEY, is used to reset the module. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. BG77_Hardware_Design 32 / 76 LPWA Module Series BG77 Hardware Design The module can be reset by driving RESET_N low for a duration between 2s and 3.8s. Table 8: Pin Definition of RESET_N Pin Name Pin No. Description DC Characteristics Comment RESET_N 45 Reset the module VILmax=0.45V Multiplexed from PWRKEY. The reset timing is illustrated in the following figure. The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET_N pin. VBA T 3.8s 2s RESET_N VIL0.45V Module Status Running Resetting Restart Figure 9: Timing of Reset Module RESET_N 2s~3.8s Reset pulse 4.7K 47K Figure 10: Reference Circuit of RESET_N by Using Driving Circuit BG77_Hardware_Design 33 / 76 LPWA Module Series BG77 Hardware Design S2 TVS RESET_N Close to S2 Figure 11: Reference Circuit of RESET_N by Using Button NOTES Please assure that there is no large capacitance on RESET_N pin. 3.8. PON_TRIG Interface BG77 provides one PON_TRIG pin which is used to wake up the module from PSM. When the pin detects a rising edge, the module will be woken up from PSM. Table 9: Pin Definition of PON_TRIG Interface Pin Name Pin No. I/O Description Comment PON_TRIG 72 DI Wake up the module from PSM A reference circuit is shown in the following figure. Rising-edge triggered. Pulled-down by default. 1.8V power domain. BG77_Hardware_Design 34 / 76 LPWA Module Series BG77 Hardware Design 10K VDD_1V8 PON_TRIG_MCU 10K 100K 100K PON_TRIG Figure 12: Reference Circuit of PON_TRIG Circuit NOTE VDD_1V8 is provided by an external LDO. 3.9. (U)SIM Interface BG77 supports 1.8V (U)SIM card only. The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Table 10: Pin Definition of (U)SIM Interface Pin Name Pin No. I/O Description Comment USIM_DET 44 DI

(U)SIM card insertion detection is under 1.8V power domain. The pin function development. Only 1.8V (U)SIM card is supported. USIM_VDD 16 PO Power supply for (U)SIM card USIM_RST 15 DO Reset signal of (U)SIM card 1.8V power domain. USIM_DATA 14 IO Data signal of (U)SIM card 1.8V power domain. USIM_CLK 13 DO Clock signal of (U)SIM card 1.8V power domain. USIM_GND 65 Specified ground for (U)SIM card BG77_Hardware_Design 35 / 76 LPWA Module Series BG77 Hardware Design BG77 supports (U)SIM card hot-plug via USIM_DET. The function supports low level or high level detections, and is disabled by default. Please refer to document [2] about AT+QSIMDET command for details. The following figure shows a reference design of (U)SIM interface with an 8-pin (U)SIM card connector. VDD_EXT USIM_VDD 51K 15K Module USIM_GND USIM_VDD USIM_RST USIM_CLK USIM_DET USIM_DATA 0R 0R 0R 100nF

(U)SIM Card Connector VCC RST CLK GND VPP IO 33pF 33pF 33pF GND GND GND Figure 13: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_DET unconnected. A reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure. USIM_VDD USIM_GND USIM_VDD USIM_RST USIM_CLK USIM_DATA 15K 0R 0R 0R Module 33pF 33pF 33pF 100nF

(U)SIM Card Connector VCC RST CLK GND VPP IO GND GND Figure 14: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector In order to enhance the reliability and availability of the (U)SIM card in applications, please follow the BG77_Hardware_Design 36 / 76 LPWA Module Series BG77 Hardware Design criteria below in (U)SIM circuit design:

Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace length as less than 200mm as possible. Keep (U)SIM card signals away from RF and VBAT traces. Assure the ground between the module and the (U)SIM card connector short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5mm to maintain the same electric potential. Make sure the bypass capacitor between USIM_VDD and USIM_GND less than 1uF, and place it as close to (U)SIM card connector as possible. If the system ground plane is complete, USIM_GND can be connected to the system ground directly. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with surrounded ground. USIM_RST should also be ground shielded. In order to offer good ESD protection, it is recommended to add a TVS diode array with parasitic capacitance not exceeding 15pF. In order to facilitate debugging, it is recommended to reserve series resistors for the (U)SIM signals of the module. The 33pF capacitors are used for filtering interference of GSM 900MHz. Please note that the (U)SIM peripheral circuit should be close to the

(U)SIM card connector. The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace and sensitive occasion are applied, and should be placed close to the (U)SIM card connector. NOTE USIM_DET function is still under development. 3.10. USB Interface BG77 contains one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0 specification and supports low-speed (1.5Mbps) and full-speed (12Mbps) modes. The USB interface is used for AT command communication, data transmission, software debugging and firmware upgrade. The following table shows the pin definition of USB interface. Table 11: Pin Definition of USB Interface Pin Name Pin No. I/O Description Comment USB_VBUS AI USB connection detection The input range is 1.3V~1.8V USB_DP USB_DM IO USB differential data bus (+) IO USB differential data bus (-) Require differential impedance of 90 12 11 10 BG77_Hardware_Design 37 / 76 LPWA Module Series BG77 Hardware Design USB_VDDA_3P3 42 PI Power supply for USB PHY circuit Vnorm=3.3V EXT_PWR_EN 64 DO External LDO enable of USB 1.8V power domain GND 43 Ground For more details about USB 2.0 specification, please visit http://www.usb.org/home. The USB interface is recommended to be reserved for firmware upgrade in customers design. The following figures illustrate reference designs of USB PHY and USB interface. VBAT VI N VO UT VDD_USB_3V3 U1 C1 1uF VDD_EXT EXT_PWR_EN R1 R2 10K EN GND 0R SG M2040-3.3 C2 1uF Figure 15: Reference Design of USB PHY Minimize these stubs Test Points Module VDD (1.3~1.8V) USB_VBUS USB_DM USB_DP NM_0R NM_0R R1 R2 L1 ESD Array Close to Module MCU USB_DM USB_DP GND USB_VDDA_3P3 EXT_PWR_EN 3.3V OUT EN IN GND VBAT GND R3 10K LDO VDD_EXT Figure 16: Reference Design of USB Interface BG77_Hardware_Design 38 / 76 LPWA Module Series BG77 Hardware Design A common mode choke L1 is recommended to be added in series between the module and customers MCU in order to suppress EMI spurious transmission. Meanwhile, the 0 resistors (R3 and R4) should be added in series between the module and the test points so as to facilitate debugging, and the resistors are not mounted by default. In order to ensure the integrity of USB data line signal, L1/R3/R4 components must be placed close to the module, and also these resistors should be placed close to each other. The extra stubs of trace must be as short as possible. The following principles should be complied with when design the USB interface, so as to meet USB 2.0 specification. It is important to route the USB signal traces as differential pairs with total grounding. The impedance of USB differential trace is 90. Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is important to route the USB differential traces in inner-layer with ground shielding on not only upper and lower layers but also right and left sides. Pay attention to the influence of junction capacitance of ESD protection components on USB data lines. Typically, the capacitance value should be less than 2pF. Keep the ESD protection components as close to the USB connector as possible. NOTES 1. BG77 can only be used as a slave device. 2. The input voltage range of USB_VBUS is 1.3V~1.8V. 3.11. UART Interfaces The module provides three UART interfaces: Main UART, Debug UART and GNSS UART interfaces. Features of them are illustrated below:

The Main UART interface supports 9600bps, 19200bps, 38400bps, 57600bps, 115200bps, 230400bps, 460800bps and 921600bps baud rates, and the default is 115200bps. It is used for data transmission and AT command communication, and supports RTS and CTS hardware flow control. The default frame format is 8N1 (8 data bits, no parity, 1 stop bit). The Debug UART interface supports a fixed baud rate of 115200bps, and is used for software The GNSS UART interface supports 115200bps baud rate by default, and is used for GNSS data and debugging and log output. NMEA sentences output. The following tables show the pin definition of the three UART interfaces. BG77_Hardware_Design 39 / 76 DTR RXD TXD CTS RTS DCD RI NOTE LPWA Module Series BG77 Hardware Design Table 12: Pin Definition of Main UART Interface Pin Name Pin No. I/O Description Comment 62 6 7 39 38 90 76 DI DI DO DO DI DO DO Data terminal ready. Sleep mode control. 1.8V power domain Receive data 1.8V power domain Transmit data 1.8V power domain Clear to send 1.8V power domain Request to send 1.8V power domain Data carrier detection 1.8V power domain Ring indication signal 1.8V power domain AT+IPR command can be used to set the baud rate of the Main UART interface, and AT+IFC command can be used to set the hardware flow control (hardware flow control is disabled by default). Please refer to document [2] for more details about these AT commands. Table 13: Pin Definition of Debug UART Interface Pin Name Pin No. I/O Description Comment DBG_TXD DBG_RXD 60 61 DO DI Transmit data 1.8V power domain Receive data 1.8V power domain Table 14: Pin Definition of GNSS UART Interface Pin Name Pin No. I/O Description Comment GNSS_UART_TXD 36 DO Transmit data 1.8V power domain GNSS_UART_RXD 4 DI Receive data 1.8V power domain The logic levels of UART interfaces are described in the following table. BG77_Hardware_Design 40 / 76 LPWA Module Series BG77 Hardware Design Table 15: Logic Levels of Digital I/O Parameter VIL VIH VOL VOH Min.

-0.3 1.2 0 1.35 Max. 0.6 2.0 0.45 1.8 Unit V V V V The module provides 1.8V UART interfaces. A level translator should be used if customers application is equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments is recommended. The following figure shows a reference design of the Main UART interface:

VDD_EXT VCCA VCCB 0.1uF VDD_MCU 0.1uF 1 0 K 120K RI DCD CTS RTS DTR TXD RXD OE A1 A2 A3 A4 A5 A6 A7 A8 Translator GND B1 B2 B3 B4 B5 B6 B7 B8 51K 51K RI_MCU DCD_MCU CTS_MCU RTS_MCU DTR_MCU TXD_MCU RXD_MCU Figure 17: Reference Circuit with Translator Chip Please visit http://www.ti.com for more information. Another example with transistor translation circuit is shown as below. The circuit design of dotted line section can refer to that of solid line section, in terms of both module input and output circuit designs, but please pay attention to the direction of connection. BG77_Hardware_Design 41 / 76 LPWA Module Series BG77 Hardware Design Figure 18: Reference Circuit with Transistor Circuit NOTE Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps. 3.12. PCM and I2C Interfaces*

BG77 provides one Pulse Code Modulation (PCM) digital interface and one I2C interface. The following table shows the pin definition of the two interfaces which can be applied on audio codec design. Table 16: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Description Comment PCM_CLK 3 DO PCM clock output 1.8V power domain PCM_SYNC 35 DO 1.8V power domain PCM frame synchronization output PCM_DIN 2 DI PCM data input 1.8V power domain PCM_DOUT 34 DO PCM data output 1.8V power domain I2C_SCL I2C_SDA 37 5 OD I2C serial clock Require external pull-up to 1.8V OD I2C serial data Require external pull-up to 1.8V BG77_Hardware_Design 42 / 76 LPWA Module Series BG77 Hardware Design The following figure shows a reference design of PCM and I2C interfaces with an external codec IC. BCLK WCLK ADC DAC SCL SDA MICBIAS INP INN LOUTP LOUTN S A B I Module K 7

. 4 K 7

. 4 1.8V Codec Figure 19: Reference Circuit of PCM Application with Audio Codec PCM_CLK PCM_SYNC PCM_DIN PCM_DOUT I2C_SCL I2C_SDA NOTE

* means under development. 3.13. Network Status Indication BG77 provides one network status indication pin: NETLIGHT. The pin is used to drive a network status indication LED. The following tables describe the pin definition and logic level changes of NETLIGHT in different network activity status. Table 17: Pin Definition of NETLIGHT Pin Name Pin No. I/O Description NETLIGHT 79 DO Indicate the modules network activity status Comment BOOT_CONFIG. Do not pull it up before startup. 1.8V power domain. Table 18: Working State of NETLIGHT Pin Name Logic Level Changes Network Status BG77_Hardware_Design 43 / 76 LPWA Module Series BG77 Hardware Design Flicker slowly (200ms High/1800ms Low) Network searching NETLIGHT Flicker slowly (1800ms High/200ms Low) Idle Flicker quickly (125ms High/125ms Low) Data transfer is ongoing Always high Voice calling A reference circuit is shown in the following figure. Module NETLIGHT 4.7K VBAT 2.2K 47K Figure 20: Reference Circuit of the Network Status Indicator NETLIGHT is a BOOT_CONFIG pin. It should not be pulled up before startup. NOTES 3.14. STATUS The STATUS pin is used to indicate the operation status of BG77 module. It will output high level when the module is powered on. The following table describes the pin definition of STATUS. Table 19: Pin Definition of STATUS Pin Name Pin No. I/O Description Comment STATUS 78 DO Indicate the modules operation status 1.8V power domain The following figure shows a reference circuit of STATUS. BG77_Hardware_Design 44 / 76 LPWA Module Series BG77 Hardware Design Figure 21: Reference Circuit of STATUS State Idle URC NOTES 3.15. Behaviors of RI*

AT+QCFG="risignaltype","physical" command can be used to configure RI behavior. No matter on which port URC is presented, URC will trigger the behavior of RI pin. The default behaviors of RI are shown as below. Table 20: Default Behaviors of RI Response RI keeps in high level. RI outputs 120ms low pulse when new URC returns. The default RI behaviors can be configured flexibly by AT+QCFG=urc/ri/ring command. For more details about AT+QCFG*, please refer to document [2]. 1. URC can be outputted from UART port, USB AT port and USB modem port, through configuration via AT+QURCCFG command. The default port is USB AT port. 2. * means under development. 3.16. USB_BOOT Interface BG77_Hardware_Design 45 / 76 LPWA Module Series BG77 Hardware Design BG77 provides a USB_BOOT pin. During development or factory production, USB_BOOT can force the module to boot from USB port for firmware upgrade. Table 21: Pin Definition of USB_BOOT Interface Pin Name Pin No. I/O Description Comment USB_BOOT 87 DI Force the module to enter into emergency download mode The following figure shows a reference circuit of USB_BOOT interface. 1.8V power domain. Active high. If unused, keep it open. Figure 22: Reference Circuit of USB_BOOT Interface It is recommended to reserve the above circuit design during application design. NOTE 3.17. ADC Interfaces The module provides two analog-to-digital converter (ADC) interfaces. AT+QADC=0 command can be used to read the voltage value on ADC0 pin. AT+QADC=1 command can be used to read the voltage value on ADC1 pin. For more details about the AT command, please refer to document [2]. In order to improve the accuracy of ADC voltage values, the trace of ADC should be surrounded by ground. BG77_Hardware_Design 46 / 76 LPWA Module Series BG77 Hardware Design Table 22: Pin Definition of ADC Interfaces Pin Name Pin No. Description ADC0 ADC1 17 18 General purpose analog to digital converter interface General purpose analog to digital converter interface The following table describes the characteristics of ADC interfaces. Table 23: Characteristics of ADC Interfaces Min. 0.1 Typ. 64.979 500 4.8 Max. 1.8 Unit V uV kHz MHz M Parameter Voltage Range Resolution (LSB) Analog Bandwidth Sample Clock NOTES Input Resistance 10 1. ADC input voltage must not exceed 1.8V. 2. 3. It is prohibited to supply any voltage to ADC pin when VBAT is removed. It is recommended to use resistor divider circuit for ADC application, and the divider resistor accuracy should be no less than 1%. 3.18. SPI Interface*

BG77 module provides one SPI interface which support master/slave mode. Master mode: up to 50MHz Slave mode: up to 25MHz BG77_Hardware_Design 47 / 76 LPWA Module Series BG77 Hardware Design Table 24: Pin Definition of SPI Interface Pin Name Pin No. I/O Description Comment SPI_MOSI 40 DO SPI master-out slave-in BOOT_CONFIG. Do not pull it up before startup. 1.8V power domain SPI_MISO 8 SPI master-in slave-out 1.8V power domain SPI_CS_N 63 SPI chip select 1.8V power domain SPI_CLK 9 SPI clock 1.8V power domain DI DO DO NOTES 1. SPI_MOSI cannot be pulled up before the module powers up. 2. The module provides 1.8V SPI interface. A level translator should be used between the module and the host if customers application is equipped with a 3.3V processor or device interface. 3. * means under development. 3.19. GPIO Interfaces*

The module provides three general-purpose input and output (GPIO) interfaces. AT+QCFG="gpio"*

command can be used to configure corresponding GPIO pins status. For more details about the AT command, please refer to document [2]. Table 25: Pin Definition of GPIO Interfaces Pin Name Pin No. Description GPIO1 GPIO2 GPIO3 1 33 57 General-purpose input and output interface General purpose input and output interface General purpose input and output interface The following table describes the characteristics of GPIO interfaces. Table 26: Logic Levels of GPIO Interfaces Parameter Min. Max. Unit BG77_Hardware_Design 48 / 76 LPWA Module Series BG77 Hardware Design VIL VIH VOL VOH

-0.3 1.2 0 1.35 0.6 2.0 0.45 1.8 V V V V NOTE

* means under development. 3.20. GRFC Interfaces*

The module provides two general RF control interfaces. Those can be used for control external antenna tuner. This function is under development. Table 27: Pin Definition of GRFC Interfaces Pin Name Pin No. Description Comments GRFC1 83 General RF control interface BOOT_CONFIG. Do not pull it up before startup. 1.8V power domain. GRFC2 94 General RF control interface 1.8V power domain. Table 28: Logic Levels of GRFC Interfaces Min. 0 1.35 Max. 0.45 1.8 Unit V V Parameter VOL VOH NOTE 1. * means under development. 2. GRFC1 is a BOOT_CONFIG pin. It should not be pulled up before startup. BG77_Hardware_Design 49 / 76 LPWA Module Series BG77 Hardware Design 4 GNSS Receiver 4.1. General Description BG77 includes a fully integrated global navigation satellite system solution that supports Gen9 VT of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). BG77 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via USB interface by default. By default, BG77 GNSS engine is switched off. It has to be switched on via AT command. For more details about GNSS engine technology and configurations, please refer to document [3]. 4.2. GNSS Performance The following table shows the GNSS performance of BG77. Table 29: GNSS Performance Parameter Description Conditions Sensitivity

(GNSS) TTFF

(GNSS) Cold start Autonomous Reacquisition Autonomous Tracking Autonomous Cold start

@open sky Warm start

@open sky Autonomous XTRA enabled Autonomous XTRA enabled Typ. TBD TBD TBD TBD TBD TBD TBD Unit dBm dBm dBm s s s s BG77_Hardware_Design 50 / 76 LPWA Module Series BG77 Hardware Design Hot start

@open sky CEP-50 Autonomous XTRA enabled Autonomous

@open sky TBD TBD TBD s s m Accuracy

(GNSS) NOTES 1. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes. 2. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can fix position again within 3 minutes after loss of lock. 3. Cold start sensitivity: the lowest GNSS signal value at the antenna port on which the module fixes position within 3 minutes after executing cold start command. 4.3. Layout Guidelines The following layout guidelines should be taken into account in customers designs. Maximize the distance between GNSS antenna and main antenna. Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar should be kept away from the antennas. isolation and protection. Keep 50 characteristic impedance for the ANT_GNSS trace. Please refer to Chapter 5 for GNSS antenna reference design and antenna installation information. BG77_Hardware_Design 51 / 76 LPWA Module Series BG77 Hardware Design 5 Antenna Interfaces BG77 includes a main antenna interface and a GNSS antenna interface. The antenna ports have an impedance of 50. 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of main antenna interface is shown below. Table 30: Pin Definition of Main Antenna Interface 5.1.2. Operating Frequency Table 31: BG77 Operating Frequency Pin Name Pin No. I/O Description Comment ANT_MAIN 26 IO Main antenna interface 50 characteristic impedance 3GPP Band Transmit Receive LTE-FDD B1 1920~1980 2110~2170 LTE-FDD B2 1850~1910 1930~1990 LTE-FDD B3 1710~1785 1805~1880 LTE-FDD B4 1710~1755 2110~2155 LTE-FDD B5 LTE-FDD B8 LTE-FDD B12 824~849 880~915 699~716 869~894 925~960 729~746 Unit MHz MHz MHz MHz MHz MHz MHz BG77_Hardware_Design 52 / 76 LPWA Module Series BG77 Hardware Design MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 777~787 788~798 815~830 830~845 832~862 807~824 703~748 663~698 698~716 746~756 758~768 860~875 875~890 791~821 859~894 852~869 758~803 617~652 728~746 LTE-FDD B25 1850~1915 1930~1995 LTE-FDD B26*

814~849 LTE-FDD B66 1710~1780 2110~2180 LTE-FDD B13 LTE-FDD B14 1) LTE-FDD B18 LTE-FDD B19 LTE-FDD B20 LTE-FDD B27 1) LTE-FDD B28 LTE-FDD B71 2) LTE-FDD B85 NOTES 1. 1) LTE-FDD B14 and B27 are supported by Cat M1 only. 2. 2) LTE-FDD B71 is supported by Cat NB2 only. 3. * means under development. 5.1.3. Reference Design of RF Antenna Interface A reference design of main antenna pad is shown as below. A -type matching circuit should be reserved for better RF performance, and the -type matching components (R1/C1/C2) should be placed as close to the antenna as possible. The capacitors are not mounted by default. BG77_Hardware_Design 53 / 76 LPWA Module Series BG77 Hardware Design Figure 23: Reference Circuit of RF Antenna Interface 5.1.4. Reference Design of RF Layout For users PCB, the characteristic impedance of all RF traces should be controlled as 50. The impedance of the RF traces is usually determined by the trace width (W), the materials dielectric constant, the distance between signal layer and reference ground (H), and the clearance between RF trace and ground (S). Microstrip line or coplanar waveguide line is typically used in RF layout for characteristic impedance control. The following are reference designs of microstrip line or coplanar waveguide line with different PCB structures. Figure 24: Microstrip Line Design on a 2-layer PCB BG77_Hardware_Design 54 / 76 LPWA Module Series BG77 Hardware Design Figure 25: Coplanar Waveguide Line Design on a 2-layer PCB Figure 26: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 27: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground) BG77_Hardware_Design 55 / 76 LPWA Module Series BG77 Hardware Design In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:

Use impedance simulation tool to control the characteristic impedance of RF traces as 50. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground. The distance between the RF pins and the RF connector should be as short as possible, and all the right angle traces should be changed to curved ones. There should be clearance area under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be no less than two times the width of RF signal traces (2*W). For more details about RF layout, please refer to document [4]. 5.2. GNSS Antenna Interface The following tables show the pin definition and frequency specification of GNSS antenna interface. Table 32: Pin Definition of GNSS Antenna Interface Pin Name Pin No. I/O Description Comment ANT_GNSS 32 AI GNSS antenna interface 50 impedance Table 33: GNSS Frequency Type GPS Galileo BeiDou QZSS GLONASS 1597.5~1605.8 Frequency 1575.421.023 1575.422.046 1561.0982.046 1575.421.023 Unit MHz MHz MHz MHz MHZ A reference design of GNSS antenna interface is shown as below. BG77_Hardware_Design 56 / 76 LPWA Module Series BG77 Hardware Design 1. An external LDO can be selected to supply power according to the active antenna requirement. 2. If the module is designed with a passive antenna, then the VDD circuit is not needed. Figure 28: Reference Circuit of GNSS Antenna Interface NOTES GNSS 1) LTE 5.3. Antenna Installation 5.3.1. Antenna Requirements The following table shows the requirements on main antenna and GNSS antenna. Table 34: Antenna Requirements Antenna Type Requirements Frequency range: 1559MHz ~1609MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0dBi Active antenna noise figure: < 1.5dB Active antenna gain: > 0dBi Active antenna embedded LNA gain: < 17dB VSWR: 2 Efficiency: > 30%

Max Input Power (W): 50 Input Impedance (): 50 BG77_Hardware_Design 57 / 76 LPWA Module Series BG77 Hardware Design Cable Insertion Loss: < 1dB

(LTE B5/B8/B12/B13/B14 2)/B18/B19/B20/B26*/B27 2)/B28/B71 3)/ B85) Cable Insertion Loss: < 1.5dB

(LTE B1/B2/B3/B4/B25/B66) NOTES 1. 1) It is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use of active antenna may generate harmonics which will affect the GNSS performance. 2. 2) LTE-FDD B14 and B27 are supported by Cat M1 only. 3. 3) LTE-FDD B71 is supported by Cat NB2 only. 4. * means under development. 5.3.2. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector provided by HIROSE. Figure 29: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. BG77_Hardware_Design 58 / 76 LPWA Module Series BG77 Hardware Design Figure 30: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector. Figure 31: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com. BG77_Hardware_Design 59 / 76 LPWA Module Series BG77 Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 35: Absolute Maximum Ratings Parameter VBAT USB_VBUS Voltage at Digital Pins Min.

-0.5 1.3

-0.3 6.2. Power Supply Ratings Table 36: Power Supply Ratings Max. 6.0 1.8 2.09 Unit V V V Parameter Description Conditions Min. Typ. Max. Unit VBAT Power supply for the module USB_VDDA_3P3 Power for USB PHY circuit The actual input voltages must stay between the minimum and maximum values. USB_VBUS USB detection 1.3 1.8 3.3 V V 2.6 3.3 4.8 V BG77_Hardware_Design 60 / 76 LPWA Module Series BG77 Hardware Design 6.3. Operation and Storage Temperatures The operation and storage temperatures of the module are listed in the following table. Table 37: Operation and Storage Temperatures Parameter Min. Max. Unit Operation Temperature Range 1)

-35 Extended Temperature Range 2)

-40 Storage Temperature Range

-40 Typ.

+25

+75

+85

+90 C C C NOTES 1. 2. 1) Within operation temperature range, the module is 3GPP compliant. 2) Within extended temperature range, the module remains the ability to establish and maintain a voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances. When the temperature returns to the normal operating temperature levels, the module will meet 3GPP specifications again. 6.4. Current Consumption The following table shows current consumption of BG77 module. Table 38: BG77 Current Consumption Parameter Description Conditions Average Max. Unit Leakage Power-off TBD TBD PSM Power Saving Mode TBD TBD uA uA AT+CFUN=0 @Sleep State TBD TBD mA IVBAT Rock Bottom Current BG77_Hardware_Design 61 / 76 LPWA Module Series BG77 Hardware Design DRX=1.28s DRX=1.28s e-I-DRX=81.92s e-I-DRX=81.92s DRX=1.28s DRX=1.28s Sleep State Idle State TBD TBD mA TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD e-I-DRX=20.48s TBD TBD e-I-DRX=20.48s TBD TBD LTE-FDD B1 @TBDdBm TBD TBD LTE-FDD B2 @TBDdBm TBD TBD LTE-FDD B3 @TBDdBm TBD TBD LTE-FDD B4 @TBDdBm TBD TBD LTE-FDD B5 @TBDdBm TBD TBD LTE-FDD B8 @TBDdBm TBD TBD LTE-FDD B12 @TBDdBm TBD TBD LTE Cat M1 data transfer

(GNSS OFF) LTE-FDD B13 @TBDdBm TBD TBD LTE-FDD B14 @TBDdBm TBD TBD LTE-FDD B18 @TBDdBm TBD TBD LTE-FDD B19 @TBDdBm TBD TBD LTE-FDD B20 @TBDdBm TBD TBD LTE-FDD B25 @TBDdBm TBD TBD LTE-FDD B26 @TBDdBm TBD TBD LTE-FDD B27 @TBDdBm TBD TBD LTE-FDD B28 @TBDdBm TBD TBD LTE-FDD B66 @TBDdBm TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA BG77_Hardware_Design 62 / 76 LPWA Module Series BG77 Hardware Design LTE-FDD B85 @TBDdBm TBD TBD LTE-FDD B1 @TBDdBm TBD TBD LTE-FDD B2 @TBDdBm TBD TBD LTE-FDD B3 @TBDdBm TBD TBD LTE-FDD B4 @TBDdBm TBD TBD LTE-FDD B5 @TBDdBm TBD TBD LTE-FDD B8 @TBDdBm TBD TBD LTE-FDD B12 @TBDdBm TBD TBD LTE-FDD B13 @TBDdBm TBD TBD LTE-FDD B18 @TBDdBm TBD TBD LTE-FDD B19 @TBDdBm TBD TBD LTE-FDD B20 @TBDdBm TBD TBD LTE-FDD B25 @TBDdBm TBD TBD LTE-FDD B26 @TBDdBm TBD TBD LTE-FDD B28 @TBDdBm TBD TBD LTE-FDD B66 @TBDdBm TBD TBD LTE-FDD B71 @TBDdBm TBD TBD LTE-FDD B85 @TBDdBm TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA LTE Cat NB2 data transfer

(GNSS OFF) 6.5. RF Output Power The following table shows the RF output power of BG77. BG77_Hardware_Design 63 / 76 LPWA Module Series BG77 Hardware Design Table 39: BG77 RF Output Power Frequency Max. Min. LTE-FDD B1/B2/B3/B4/B5/B8/B12/B13/B14 1)/B18/B19/B20/B25/

B26/B27 2) /B28/B66/B71/B85 21dBm+1/-3dB

<-39dBm NOTES 1. 2. 3. 1) LTE-FDD B14 and B27 are supported by Cat M1 only. 2) LTE-FDD B71 is supported by Cat NB2 only.

* means under development. 6.6. RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of BG77. Table 40: BG77 Conducted RF Receiving Sensitivity Network Band Primary Diversity LTE-FDD B1 LTE-FDD B2 LTE-FDD B3 LTE-FDD B4 LTE-FDD B5 LTE-FDD B12 LTE-FDD B13 LTE-FDD B14 2) LTE-FDD B18 LTE-FDD B19 Sensitivity (dBm) Cat M1/3GPP Cat NB2 1)/3GPP TBD/-102.3 TBD/-107.5 TBD/-100.3 TBD/-107.5 TBD/-99.3 TBD/-107.5 TBD/-102.3 TBD/-107.5 TBD/-100.8 TBD/-107.5 TBD/-99.3 TBD/-107.5 TBD/-99.3 TBD/-107.5 TBD/-99.3 NOT Supported TBD/-102.3 TBD/-107.5 TBD/-102.3 TBD/-107.5 LTE LTE-FDD B8 Supported TBD/-99.8 TBD/-107.5 Not Supported BG77_Hardware_Design 64 / 76 LPWA Module Series BG77 Hardware Design LTE-FDD B20 LTE-FDD B25 LTE-FDD B26*

LTE-FDD B27 2) LTE-FDD B28 LTE-FDD B66 LTE-FDD B71 3) LTE-FDD B85 TBD/-99.8 TBD/-107.5 TBD/-100.3 TBD/-107.5 TBD/-100.3 TBD/-107.5 TBD/-100.8 NOT Supported TBD/-100.8 TBD/-107.5 TBD/-101.8 TBD/-107.5 NOT Supported TBD/-107.5 TBD/-99.3 TBD/-107.5 NOTES 1. 1) LTE Cat NB2 receiving sensitivity without repetitions. 2. 2) LTE-FDD B14 and B27 are supported by Cat M1 only. 3. 3) LTE-FDD B71 is supported by Cat NB2 only. 4. * means under development. 6.7. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. The following table shows the electrostatic discharge characteristics of BG77 module. Table 41: Electrostatic Discharge Characteristics (25C, 45% Relative Humidity) Tested Points Contact Discharge Air Discharge Unit VBAT, GND Main/GNSS Antenna Interfaces TBD TBD TBD TBD kV kV BG77_Hardware_Design 65 / 76 LPWA Module Series BG77 Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm, and the tolerances for dimensions without tolerance values are 0.05mm. 7.1. Mechanical Dimensions of the Module 12.900.15 1.70.2 Pin 1 5 1

. 0 0 9

. 4 1 Figure 32: Module Top and Side Dimensions BG77_Hardware_Design 66 / 76 LPWA Module Series BG77 Hardware Design 12.900.15 11.90 6.45 1.00 1.00 Pin 1 R0.35

. 7 4 5 1.30 1

. 9 5

. 1 4 9 0 0 1 5

. 0.65 0.85

. 4 1 5

. 5 3 0 6

. 4 5 0.85 0.65 0.65 1.15 R0.35 1 3

. 9 0 7

. 4 5 1.30 6.45 Figure 33: Module Bottom Dimensions (Bottom View) BG77_Hardware_Design 67 / 76 LPWA Module Series BG77 Hardware Design 7.2. Recommended Footprint 12.900.15 11.90 6.45 1.00 1.00 Pin 1 R0.35 7

. 4 5 1.30 1.95 0.65 1 4

. 9 0 0

. 1 5 1 3

. 9 0 7

. 4 5 0.85 0.65

. 4 1 5 5

. 3 0 6

. 4 5 0.85 0.65 1.15 R0.35 1.30 6.45 Figure 34: Recommended Footprint (Top View) NOTES 1. For easy maintenance of the module, please keep about 3mm between the module and other components on the host PCB. 2. Keep all reserved pins open. 3. For stencil design requirements of the module, please refer to document [5]. BG77_Hardware_Design 68 / 76 LPWA Module Series BG77 Hardware Design 7.3. Design Effect Drawings of the Module Figure 35: Top View of the Module Figure 36: Bottom View of the Module NOTE These are renderings of BG77 module. For authentic appearance, please refer to the module that you receive from Quectel. BG77_Hardware_Design 69 / 76 LPWA Module Series BG77 Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage BG77 is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are listed below. 1. Shelf life in the vacuum-sealed bag: 12 months at <40C/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be:

Mounted within 168 hours at the factory environment of 30C/60%RH. Stored at <10%RH. 3. Devices require baking before mounting, if any circumstance below occurs. When the ambient temperature is 23C5C and the humidity indication card shows the humidity is >10% before opening the vacuum-sealed bag. Device mounting cannot be finished within 168 hours at factory conditions of 30C/60% RH. If baking is required, devices may be baked for 8 hours at 120C5C. As the plastic package cannot be subjected to high temperature, it should be removed from devices before high temperature (120C) baking. to IPC/JEDECJ-STD-033 for baking procedure. is desired, please refer If shorter baking time 4. NOTE BG77_Hardware_Design 70 / 76 LPWA Module Series BG77 Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.13mm~0.15mm. For more details, please refer to document [5]. It is suggested that the peak reflow temperature is 238~245C, and the absolute maximum reflow temperature is 245C. To avoid damage to the module caused by repeated heating, it is strongly recommended that the module should be mounted after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. Reflow Zone Max slope:

2~3C/sec C Cooling down slope: 1~4C/sec B D Soak Zone A Max slope: 1~3C/sec Temp. (C) 245 238 220 200 150 100 Factor Soak Zone Max slope Figure 37: Recommended Reflow Soldering Thermal Profile Table 42: Recommended Thermal Profile Parameters Recommendation 1 to 3C/sec Soak time (between A and B: 150C and 200C) 60 to 120 sec BG77_Hardware_Design 71 / 76 LPWA Module Series BG77 Hardware Design Reflow Zone Max slope Reflow time (D: over 220C) Max temperature Cooling down slope Reflow Cycle Max reflow cycle 8.3. Packaging 2 to 3C/sec 40 to 60 sec 238C ~ 245C 1 to 4C/sec 1 BG77 is packaged in a vacuum-sealed bag which is ESD protected. The bag should not be opened until the devices are ready to be soldered onto the application. The following figures show the packaging details, measured in mm. Figure 38: Tape Dimensions BG77_Hardware_Design 72 / 76 LPWA Module Series BG77 Hardware Design Figure 39: Reel Dimensions Table 43: Reel Packaging Model Name MOQ for MP Minimum Package: 250pcs Minimum Package x 4=1000pcs BG77 TBD TBD TBD BG77_Hardware_Design 73 / 76 LPWA Module Series BG77 Hardware Design 9 Appendix A References Table 44: Related Documents SN Document Name Remark

[1] Quectel_UMTS&LTE_EVB_User_Guide UMTS&LTE EVB User Guide

[2] Quectel_BG77_AT_Commands_Manual BG77 AT Commands Manual

[3] Quectel_BG77_GNSS_AT_Commands_Manual BG77 GNSS AT Commands Manual

[4] Quectel_RF_Layout_Application_Note RF Layout Application Note

[5] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide Table 45: Terms and Abbreviations Abbreviation Description Adaptive Multi-rate Bits Per Second Coding Scheme Clear To Send Challenge Handshake Authentication Protocol Delta Firmware Upgrade Over The Air Downlink Data Terminal Ready Discontinuous Transmission Extended Idle Mode Discontinuous Reception Evolved Packet Core AMR bps CHAP CS CTS DFOTA DL DTR DTX e-I-DRX EPC BG77_Hardware_Design 74 / 76 LPWA Module Series BG77 Hardware Design ESD FDD FR GMSK GSM HSS I/O Inorm LED LNA LTE MO MS MT PAP PCB PDU PPP PSM RF RHCP Rx SISO SMS TDD Electrostatic Discharge Frequency Division Duplex Full Rate Gaussian Minimum Shift Keying Global System for Mobile Communications Home Subscriber Server Input/Output Normal Current Light Emitting Diode Low Noise Amplifier Long Term Evolution Mobile Originated Mobile Station (GSM engine) Mobile Terminated Password Authentication Protocol Printed Circuit Board Protocol Data Unit Point-to-Point Protocol Power Saving Mode Radio Frequency Right Hand Circularly Polarized Receive Single Input Single Output Short Message Service Time Division Duplexing BG77_Hardware_Design 75 / 76 LPWA Module Series BG77 Hardware Design Transmitting Direction Uplink User Equipment Unsolicited Result Code Maximum Voltage Value Normal Voltage Value Minimum Voltage Value

(Universal) Subscriber Identity Module Maximum Input High Level Voltage Value Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Minimum Input Low Level Voltage Value Absolute Maximum Input Voltage Value Absolute Minimum Input Voltage Value Maximum Output High Level Voltage Value Minimum Output High Level Voltage Value Maximum Output Low Level Voltage Value Minimum Output Low Level Voltage Value Voltage Standing Wave Ratio TX UL UE URC

(U)SIM Vmax Vnorm Vmin VIHmax VIHmin VILmax VILmin VImax VImin VOHmax VOHmin VOLmax VOLmin VSWR BG77_Hardware_Design 76 / 76

BG?

BG77 SNi1:

IMEI 1C:10;

FCC |

JE Tua

'LA-64-S 23456789

| 2345678:

224A-201 D:XMR201 E a Free Q1-A14 3GNS 1012345. 9012345 1912BG7;

1912BG77 OF I or

red Orme Cer ase Seat IMEI: 86

Quectel Wireless Solutions Co., Ltd Statement We Quectel Wireless Solutions Co., Ltd declare the following models:

Model Number: BG77 According to the markets requirement, we will close LTE CatM1 Band 14 and NB-IoT Band 26 through software, and the hardware is the same as before. The change will not impact RF performance of Cat M1 and NB-IoT. Your assistance on this matter is highly appreciated. Sincerely, Signature Name: Jean Hu Title: Certification Section

Quect tel Wire eless S BG77 Solution 7Declaration s Com Letter pany L imited BG7 date 77 original c e of grant :04 certifite numb 4/02/2020 ber: 202180 0226AA00 , FCC ID : XM MR201912B BG77 Acc ording to the e market's re equirement,

, we will clos se LTE NB2

&CatM1 Ba nd 14, NB-I oT Ban nd 26 throug h software, their hardwa are are the s same as bef fore. The ch hange will no ot impa act RF perfo ormance of C Cat M1 and NB-IoT. All r reports of So oftware Vers sion have be een updated d from BG77 7LAR02A02 to BG7 77LAR02A0 04 without an ny modificat ion of the da ata. Sign nature:

Prin nt name: Jea an Hu Date e: 07/03/202 20 Com mpany: Quec ctel Wireles s Solutions Co., Ltd. dress: Buildin hang Distric ail: jean.hu ng 5, Shang ct, Shanghai u@quectel.c ghai Busines

, China 200 com ss Park Pha 233 Add Min Ema se III (Area B), No.1016 6 Tianlin Roa ad,

WirelessModuleExpert Procedure:

QuectelWirelessSolutionsCo.,Ltd. 1.Setthemoduletooperationalvoltageandononecertainchannelinaspecialservicemodebymeansof companyproprietarysoftware. 2.Theactualpowerismeasuredatminimalandmaximumpowerlevels. 3.ThegainfactorsofeachindividualmoduleareadjustedviatheBoardtestSWusingautomaticadjustment arithmeticuntilthetargetvalueismet. 4Thetuneuptargetvalue(Conductedpower)isbelow:

CatmB2/B4/B5/B12/B13/B25/B26/B66/B85:20dBm[2~+2dB]

NBIoTB2/B4/B5/B12/B13/B25/B66/B71/B85:20dBm[2~+2dB]

7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, ChinaEmail: info@quectel.comWebsite: www.quectel.compage 1

Quectel Wireless Solutions Company Limited Request for Confidentiality Date: _2020/03/12 Subject: Confidentiality Request for: _____ FCC ID: XMR201912BG77 ______ Pursuant to FCC 47 CRF 0.457(d) and 0.459 and IC RSP-100, Section 10, the applicant requests that a part of the subject FCC application be held confidential. Type of Confidentiality Requested Short Term Short Term Short Term Short Term Short Term Short Term Short Term Short Term Short Term Permanent Permanent*1 Permanent Permanent Permanent Permanent Permanent*

Exhibit Block Diagrams External Photos Internal Photos Operation Description/Theory of Operation Parts List & Placement/BOM Tune-Up Procedure Schematics Test Setup Photos Users Manual

*Note: ______(Insert Explanation as Necessary)______ ______ FCC ID: XMR201912BG77_____ has spent substantial effort in developing this product and it is one of the first of its kind in industry. Having the subject information easily available to "competition" would negate the advantage they have achieved by developing this product. Not protecting the details of the design will result in financial hardship. Permanent Confidentiality:

The applicant requests the exhibits listed above as permanently confidential be permanently withheld from public review due to materials that contain trade secrets and proprietary information not customarily released to the public. Short-Term Confidentiality:

The applicant requests the exhibits selected above as short term confidential be withheld from public view for a period of ______ days from the date of the Grant of Equipment Authorization and prior to marketing. This is to avoid premature release of sensitive information prior to marketing or release of the product to the public. Applicant is also aware that they are responsible to notify TCB in the event information regarding the product or the product is made available to the public. TCB will then release the documents listed above for public disclosure pursuant to FCC Public Notice DA 04-1705. NOTE for Industry Canada Applications:

The applicant understands that until such time that IC distinguishes between Short Term and Permanent Confidentiality, either type of marked exhibit above will simply be marked Confidential when submitted to IC. Sincerely, By:

Jean Hu

(Signature/Title2)

(Print name) 7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, ChinaEmail: info@quectel.comWebsite: www.quectel.compage 1

RF_160, Issue 04

< Quectel Wireless Solutions Company Limited >

Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin

(Quectel Wireless Solutions Company Limited) Declaration of Authorization We Name:

Address:

Road, Minhang District . City:

Country:

Declare that:

Name Representative of agent:

Agent Company name:

Jinnan Han. (1) Shanghai . CHINA . TA Technology(Shanghai) Company, Limited No.145,Jintang Rd,Tangzhen IndustryPark,Pudong .. Shanghai.. China. Quectel BG77 . Address:

City:

Country is authorized to apply for Certification of the following product(s):

Product description: LTE Cat M1 & Cat NB2 Module . Type designation: BG77 . Trademark:

Validity/ expiry date on our behalf. Date:

City:

Name:

Function:

Signature:

Notes:

(1): Required for FCC application

(2): For FCC it must be the Grantee Code owner or the authorized agent. Jean Hu.. (2) 2020/3/12.. shanghai.. Project Manager.

Quectel Wireless Solutions Company Limited Declaration of the Modular Approval Applicant / Grantee FCC ID:

Model:

The single module transmitter has been evaluated then tested meeting the requirements under Part 15C Section 212 as below:

Quectel Wireless Solutions Company Limited XMR201912BG77 BG77 Modular approval requirement EUT Condition

(a) The radio elements of the modular transmitter must have their own shielding. The physical crystal and tuning capacitors may be located external to the shielded radio elements. The radio elements of the modular transmitter have their own shielding. Com ply YES

(b) The modular transmitter have inputs are buffered modulation/data provided) to ensure that the module will comply with part 15 requirements under conditions of excessive data rates or over-modulation. inputs (if such must

(c)The modular transmitter must have its own power supply regulation. The modular has buffered data inputs, it is integrated in chip. Please see schematic.pdf YES All power lines derived from the host device are regulated before energizing other circuits internal to the BG77. Please see schematic.pdf YES Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Website: www.quectel.com page 1 Quectel Wireless Solutions Company Limited A permanently attached antenna or unique antenna connector is not a requirement for licensed modules. YES

(d)

(e)The The must modular transmitter comply with the antenna and transmission system requirements of Sections 15.203, 15.204(b) and 15.204(c). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of Section 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph (b) of this section. be must modular transmitter tested in a stand-alone configuration, i.e., the module must not be inside another device during testing for compliance with part 15 requirements. Unless the transmitter module will be battery powered, it must comply with the AC line conducted requirements found in Section 15.207. AC or DC power lines and data input/output lines connected to the module must not contain ferrites, unless they will be marketed with the module (see Section 15.27(a)). The length of these lines shall be the length typical of actual use or, if that length is unknown, at least 10 centimeters to insure that there is no coupling between the case of the module and supporting equipment. Any accessories, peripherals, or support equipment connected to the module during testing shall be unmodified and commercially available (see Section 15.31(i))mustnotbeinsideanotherdeviceduringtesting.

(f)The modular be equipped with either a permanently affixed label or must be capable of electronically displaying its FCC identification number. transmitter must

(g) The modular transmitter must comply with any specific rules or operating requirements that ordinarily apply to a complete transmitter and the manufacturer must provide adequate instructions along with the module to explain any suchrequirements. A copy of these instructions must be included in the application for equipmentauthorizationrequirements,whicharebasedonthei ntendeduse/configurations.

(h)The modular transmitter must comply with any applicable RF exposure requirements in its final configuration. The BG77 was tested in a standalone configuration via a PCMCIA extender. Please see spurious setup YES The label position of BG77 is clearly indicated. If the FCC ID of the module cannot be seen when it is installed, then the host label must include the text:

Contains FCC ID: XMR201912BG77. Please see the label.pdf The BG77 is compliant with all applicable FCC rules. Detail instructions are given in the User Manual. YES YES The BG77 is approved to comply with the applicable RF exposure requirement, please see the MPE evaluation with 20cm as the distance restriction. YES Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Website: www.quectel.com page 2 Quectel Wireless Solutions Company Limited 2020/3/12 Signature Jean Hu Printed Title: Project Manager Company Limited) On behalf of :

(Quectel Wireless Solutions Telephone:

86-21-5445 3668 Dated By:

Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Website: www.quectel.com page 3

Quectel Wireless Solutions Company Limited POWER OF ATTORNEY DATE: March 12, 2020 To:

Federal Communications Commission, Authorization & Evaluation Division, 7435 Oakland Mills Road, Columbia, MD 21046 own. We, the undersigned, hereby authorize TA Technology (Shanghai) Co., Ltd.

/Han jinnan on our behalf, to apply to FCC on our equipment for FCC ID:

XMR201912BG77. Any and all acts carried out by TA Technology (Shanghai) Co., Ltd. / Han jinnan on our behalf shall have the same effect as acts of our Sincerely, Signature:

Print name: Jean Hu Company: Quectel Wireless Solutions Company Limited Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 page 1