FCC ID: XMR2022BG772AGL LTE Cat M1 & Cat NB2 Module

BG772A-GL Hardware Design LPWA Module Series Version: 1.0.0 Date: 2021-01-28 Status: Preliminary www.quectel.com LPWA Module Series BG772A-GL Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters:

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit:

http://www.quectel.com/support/sales.htm. For technical support, or to report documentation errors, please visit:

http://www.quectel.com/support/technical.htm Or email to support@quectel.com. General Notes Quectel offers the information as a service to its customers. The information provided is based upon customers requirements. Quectel makes every effort to ensure the quality of the information it makes available. Quectel does not make any warranty as to the information contained herein, and does not accept any liability for any injury, loss or damage of any kind incurred by use of or reliance upon the information. All information supplied herein is subject to change without prior notice. Disclaimer it is possible that these functions and features could contain errors, While Quectel has made efforts to ensure that the functions and features under development are free from errors, inaccuracies and omissions. Unless otherwise provided by valid agreement, Quectel makes no warranties of any kind, implied or express, with respect to the use of features and functions under development. To the maximum extent permitted by law, Quectel excludes all liability for any loss or damage suffered in connection with the use of the functions and features under development, regardless of whether such loss or damage may have been foreseeable. Duty of Confidentiality The Receiving Party shall keep confidential all documentation and information provided by Quectel, except when the specific permission has been granted by Quectel. The Receiving Party shall not access or use Quectels documentation and information for any purpose except as expressly provided herein. Furthermore, the Receiving Party shall not disclose any of the Quectel's documentation and information to any third party without the prior written consent by Quectel. For any noncompliance to the above requirements, unauthorized use, or other illegal or malicious use of the documentation and information, Quectel will reserve the right to take legal action. BG772A-GL_Hardware_Design 1 / 75 LPWA Module Series BG772A-GL Hardware Design Copyright The information contained here is proprietary technical information of Quectel. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design. Copyright Quectel Wireless Solutions Co., Ltd. 2021. All rights reserved. BG772A-GL_Hardware_Design 2 / 75 LPWA Module Series BG772A-GL Hardware Design Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be paid to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation interference with of wireless appliances in an aircraft communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft. is forbidden to prevent Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions, such as when the mobile bill is unpaid or the (U)SIM card is invalid. When emergency help is needed in such conditions, use emergency call if the device supports it. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. In an emergency, the device with emergency call function cannot be used as the only contact method considering network connection cannot be guaranteed under all circumstances. The cellular terminal or mobile contains a transceiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV sets, radios, computers or other electric equipment. In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or metal powders. BG772A-GL_Hardware_Design 3 / 75 LPWA Module Series BG772A-GL Hardware Design About the Document Revision History Version Date Author Description

2021-01-28 Creation of the document 1.0.0 2021-01-28 Preliminary Besson RONG/

Ben JIANG Besson RONG/

Ben JIANG BG772A-GL_Hardware_Design 4 / 75 LPWA Module Series BG772A-GL Hardware Design Contents Safety Information...................................................................................................................................................... 3 About the Document..................................................................................................................................................4 Contents........................................................................................................................................................................5 Table Index................................................................................................................................................................... 7 Figure Index................................................................................................................................................................. 9 1 2 3 Introduction....................................................................................................................................................... 10 Special Mark............................................................................................................................................13 1.1. Product Concept...............................................................................................................................................14 2.1. General Description............................................................................................................................... 14 Key Features........................................................................................................................................... 15 2.2. Functional Diagram................................................................................................................................17 2.3. Evaluation Board.................................................................................................................................... 18 2.4. 3.5. 3.6. 3.4.4.1. 3.5.1. 3.5.2. 3.4.1. 3.4.2. 3.4.3. 3.4.4. Application Interfaces.....................................................................................................................................19 Pin Assignment.......................................................................................................................................20 3.1. Pin Description........................................................................................................................................21 3.2. 3.3. Operating Modes.................................................................................................................................... 27 Power Saving.......................................................................................................................................... 28 3.4. Airplane Mode.............................................................................................................................28 Power Saving Mode (PSM)*.....................................................................................................28 Extended Idle Mode DRX (e-I-DRX).......................................................................................29 Sleep Mode................................................................................................................................. 29 UART Application............................................................................................................29 Power Supply.......................................................................................................................................... 30 Power Supply Pins..................................................................................................................... 30 Decrease Voltage Drop.............................................................................................................31 Turn on and off Scenarios.................................................................................................................... 32 Pin Definition of PWRKEY........................................................................................................32 Turn on Module Using PWRKEY............................................................................................ 32 Turn off Module...........................................................................................................................34 Turn off Module through PWRKEY..............................................................................34 Turn off Module through AT Command...................................................................... 34 3.7. Reset the Module................................................................................................................................... 35 PON_TRIG*.............................................................................................................................................36 3.8.

(U)SIM Interface..................................................................................................................................... 37 3.9. 3.10. USB Interface*........................................................................................................................................ 39 3.11. UART Interfaces..................................................................................................................................... 41 3.12. PCM and I2C Interfaces*...................................................................................................................... 44 3.13. Network Status Indication*....................................................................................................................45 3.14. STATUS................................................................................................................................................... 46 3.15. Behaviors of MAIN_RI*......................................................................................................................... 46 3.6.1. 3.6.2. 3.6.3. 3.6.3.1. 3.6.3.2. BG772A-GL_Hardware_Design 5 / 75 LPWA Module Series BG772A-GL Hardware Design 3.16. ADC Interfaces*...................................................................................................................................... 47 3.17. GPIO Interfaces*.................................................................................................................................... 48 3.18. GRFC Interfaces*................................................................................................................................... 49 4 GNSS Receiver*................................................................................................................................................ 50 4.1. General Description............................................................................................................................... 50 4.2. GNSS Performance............................................................................................................................... 50 Layout Guidelines...................................................................................................................................51 4.3. 5 6 Antenna Interfaces...........................................................................................................................................52 5.1. Main Antenna Interface......................................................................................................................... 52 Pin Definition............................................................................................................................... 52 5.1.1. 5.1.2. Operating Frequency.................................................................................................................52 Reference Design of Main Antenna Interface....................................................................... 53 5.1.3. 5.2. GNSS Antenna Interface...................................................................................................................... 54 Pin Definition............................................................................................................................... 54 5.2.1. 5.2.2. GNSS Operating Frequency.................................................................................................... 54 Reference Design of GNSS Antenna Interface.................................................................... 54 5.2.3. Antenna Installation............................................................................................................................... 55 Reference Design of RF Layout.............................................................................................. 55 Antenna Requirements..............................................................................................................57 Recommended RF Connector for Antenna Installation.......................................................58 5.3.1. 5.3.2. 5.3.3. 5.3. Electrical, Reliability and Radio Characteristics.....................................................................................60 Absolute Maximum Ratings..................................................................................................................60 6.1. Power Supply Ratings........................................................................................................................... 60 6.2. 6.3. Operating and Storage Temperatures................................................................................................61 6.4. Current Consumption.............................................................................................................................62 6.5. Digital I/O Characteristic....................................................................................................................... 64 6.6. RF Output Power....................................................................................................................................65 6.7. RF Receiving Sensitivity....................................................................................................................... 65 Electrostatic Discharge..........................................................................................................................67 6.8. 7 Mechanical Dimensions................................................................................................................................. 68 Top and Side Dimensions.....................................................................................................................68 7.1. 7.2. Recommended Footprint...................................................................................................................... 70 Top and Bottom Views.......................................................................................................................... 71 7.3. 8 Storage, Manufacturing and Packaging.................................................................................................... 72 Storage.....................................................................................................................................................72 8.1. 8.2. Manufacturing and Soldering............................................................................................................... 73 Packaging................................................................................................................................................ 74 8.3. 9 Appendix A References..................................................................................................................................76 BG772A-GL_Hardware_Design 6 / 75 LPWA Module Series BG772A-GL Hardware Design Table Index Table 1: Special Mark............................................................................................................................................... 13 Table 2: Frequency Bands and GNSS Types of BG772A-GL Module........................................................... 14 Table 3: Key Features of BG772A-GL...................................................................................................................15 Table 4: Definition of I/O Parameters.....................................................................................................................21 Table 5: Pin Description........................................................................................................................................... 22 Table 6: Overview of Operating Modes................................................................................................................. 27 Table 7: VBAT and GND Pins................................................................................................................................. 30 Table 8: Pin Definition of PWRKEY........................................................................................................................32 Table 9: Pin Definition of RESET_N.......................................................................................................................35 Table 10: Pin Definition of PON_TRIG.................................................................................................................. 36 Table 11: Pin Definition of (U)SIM Interface......................................................................................................... 37 Table 12: Pin Definition of USB Interface..............................................................................................................39 Table 13: Pin Definition of Main UART Interface................................................................................................. 41 Table 14: Pin Definition of Debug UART Interface.............................................................................................. 42 Table 15: Pin Definition of Auxiliary UART Interface...........................................................................................42 Table 16: Pin Definition of PCM and I2C Interfaces............................................................................................44 Table 17: Pin Definition of NET_STATUS.............................................................................................................45 Table 18: Working State of NET_STATUS........................................................................................................... 45 Table 19: Pin Definition of STATUS....................................................................................................................... 46 Table 20: Default Behaviors of MAIN_RI.............................................................................................................. 46 Table 21: Pin Definition of ADC Interfaces............................................................................................................47 Table 22: Characteristics of ADC Interfaces.........................................................................................................47 Table 23: Pin Definition of GPIO Interfaces.......................................................................................................... 48 Table 24: Pin Definition of GRFC Interfaces.........................................................................................................49 Table 25: Truth Table of GRFC Interfaces............................................................................................................49 Table 26: GNSS Performance.................................................................................................................................50 Table 27: Pin Definition of Main Antenna Interface............................................................................................. 52 Table 28: BG772A-GL Operating Frequency....................................................................................................... 52 Table 29: Pin Definition of GNSS Antenna Interface.......................................................................................... 54 Table 30: GNSS Operating Frequency..................................................................................................................54 Table 31: Antenna Requirements........................................................................................................................... 57 Table 32: Absolute Maximum Ratings................................................................................................................... 60 Table 33: Power Supply Ratings.............................................................................................................................60 Table 34: Operating and Storage Temperatures................................................................................................. 61 Table 35: BG772A-GL Current Consumption (Power Supply: 3.3 V, Room Temperature)......................... 62 Table 36: GNSS Current Consumption (Power Supply: 3.3 V, Room Temperature)....................................64 Table 37: 1.8 V I/O Requirements.......................................................................................................................... 64 Table 38: (U)SIM 1.8 V I/O Requirements............................................................................................................ 64 Table 39: BG772A-GL RF Output Power.............................................................................................................. 65 Table 40: BG772A-GL Conducted RF Receiving Sensitivity............................................................................. 65 Table 41: Electrostatic Discharge Characteristics (Temperature: 25 C, Relative Humidity: 45 %)...........67 BG772A-GL_Hardware_Design 7 / 75 LPWA Module Series BG772A-GL Hardware Design Table 42: Recommended Thermal Profile Parameters...................................................................................... 74 Table 43: BG772A-GL Packaging Specifications................................................................................................ 75 Table 44: Related Documents.................................................................................................................................76 Table 45: Terms and Abbreviations....................................................................................................................... 76 BG772A-GL_Hardware_Design 8 / 75 LPWA Module Series BG772A-GL Hardware Design Figure Index Figure 1: Functional Diagram.................................................................................................................................. 17 Figure 2: Pin Assignment (Top View).................................................................................................................... 20 Figure 3: Sleep Mode Application via UART........................................................................................................ 30 Figure 4: Star Structure of the Power Supply....................................................................................................... 31 Figure 5: Turn on the Module by Using Driving Circuit....................................................................................... 32 Figure 6: Turn on the Module by Using Keystroke.............................................................................................. 33 Figure 7: Power-up Timing.......................................................................................................................................33 Figure 8: Power-down Timing..................................................................................................................................34 Figure 9: Reset Timing............................................................................................................................................. 35 Figure 10: Reference Circuit of RESET_N by Using Driving Circuit................................................................ 35 Figure 11: Reference Circuit of RESET_N by Using Button.............................................................................. 36 Figure 12: Reference Circuit of PON_TRIG......................................................................................................... 37 Figure 13: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector.............................38 Figure 14: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector...............................38 Figure 15: Reference Design of USB PHY........................................................................................................... 40 Figure 16: Reference Design of USB Interface....................................................................................................40 Figure 17: Main UART Reference Design (Translator Chip)............................................................................. 43 Figure 18: Main UART Reference Design (Transistor Circuit).......................................................................... 43 Figure 19: Reference Circuit of PCM Application with Audio Codec................................................................44 Figure 20: Reference Design of NET_STATUS...................................................................................................45 Figure 21: Reference Design of STATUS............................................................................................................. 46 Figure 22: Reference Design of Main Antenna Interface................................................................................... 53 Figure 23: Reference Circuit of GNSS Antenna Interface..................................................................................54 Figure 24: Microstrip Design on a 2-layer PCB....................................................................................................55 Figure 25: Coplanar Waveguide Design on a 2-layer PCB................................................................................55 Figure 26: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground).......................56 Figure 27: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground).......................56 Figure 28: Dimensions of the U.FL-R-SMT Connector (Unit: mm)................................................................... 58 Figure 29: Mechanicals of U.FL-LP Connectors.................................................................................................. 58 Figure 30: Space Factor of Mated Connector (Unit: mm).................................................................................. 59 Figure 31: Module Top and Side Dimensions...................................................................................................... 68 Figure 32: Bottom Dimensions (Bottom View)..................................................................................................... 69 Figure 33: Recommended Footprint (Top View)..................................................................................................70 Figure 34: Top and Bottom View of the Module...................................................................................................71 Figure 35: Recommended Reflow Soldering Thermal Profile........................................................................... 73 Figure 36: Tape Dimensions....................................................................................................................................75 Figure 37: Reel Dimensions.................................................................................................................................... 75 BG772A-GL_Hardware_Design 9 / 75 LPWA Module Series BG772A-GL Hardware Design 1 Introduction This document defines BG772A-GL module and describes its air interface and hardware interfaces which are connected with customers applications. This document helps customers quickly understand the interface specifications, electrical and mechanical details, as well as other related information of the module. To facilitate application designs, it also includes some reference designs for customers reference. The document, coupled with application notes and user guides, makes it easy to design and to set up mobile applications with BG772A-GL. Hereby, [Quectel Wireless Solutions Co., Ltd.] declares that the radio equipment type [BG772A-GL] is in compliance with Directive 2014/53/EU. The full http://www.quectel.com the EU declaration of conformity is available at the following internet address:

text of The device could be used with a separation distance of 20cm to the human body. FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met:

1. This Modular Approval is limited to OEM installation for mobile and fixed applications only. The antenna installation and operating configurations of this transmitter, including any applicable source-based timeaveraging duty factor, antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements of 2.1091. 2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the users body and must not transmit simultaneously with any other antenna or transmitter. 3. A label with the following statements must be attached to the host end product: This device contains FCC ID: XMR2022BG772AGL 4. To comply with FCC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed:

radiation, maximum antenna gain (including cable loss) FCC Max Antenna GaindBi IC Max Antenna GaindBi BG772A-GL_Hardware_Design 10 / 75 LPWA Module Series BG772A-GL Hardware Design must not exceed: Operating Band LTE BAND 26(814-824) LTE BAND 26(824-849) LTE BAND 2 LTE BAND 4 LTE BAND 5 LTE BAND 12 LTE BAND 13 LTE BAND 25 LTE BAND 66 NB-IOT Band 2 NB-IOT Band 4 NB-IOT Band 5 NB-IOT Band 12 NB-IOT Band 13 NB-IOT Band 25 NB-IOT Band 26 NB-IOT Band 66 7.300 4.300 8.841 8.098 8.514 7.300 8.841 8.841 4.300 7.300 4.300 8.841 8.098 8.514 7.300 8.841 4.300 7.30 4.30 5.40 4.91 5.23 7.30 5.36 5.36 4.30 7.30 4.30 5.40 4.91 5.23 4.93 7.30 4.30 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093 If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations. For this device, OEM integrators must be provided with labeling instructions of finished products. Please refer to KDB784748 D01 v07, section 8. Page 6/7 last two paragraphs:

A certified modular has the option to use a permanently affixed label, or an electronic label. For a permanently affixed label, the module must be labeled with an FCC ID - Section 2.926 (see 2.2 Certification (labeling requirements) above). The OEM manual must provide clear instructions explaining to the OEM the labeling requirements, options and OEM user manual instructions that are required (see next paragraph). For a host using a certified modular with a standard fixed label, if (1) the modules FCC ID is not visible when installed in the host, or (2) if the host is marketed so that end users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible;

then an additional permanent label referring to the enclosed module: Contains Transmitter Module FCC ID: XMR2022BG772AGL or Contains FCC ID: XMR2022BG772AGL must be used. The host OEM user manual must also contain clear instructions on how end users can find and/or access the module and the FCC ID. The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for BG772A-GL_Hardware_Design 11 / 75 LPWA Module Series BG772A-GL Hardware Design unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The users manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. In cases where the manual is provided only in a form other than paper, such as on a computer disk or over the Internet, the information required by this section may be included in the manual in that alternative form, provided the user can reasonably be expected to have the capability to access information in that form. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the manufacturer could void the users authority to operate the equipment. To ensure compliance with all non-transmitter functions the host manufacturer is responsible for ensuring compliance with the module(s) installed and fully operational. For example, if a host was previously authorized as an unintentional radiator under the Suppliers Declaration of Conformity procedure without a transmitter certified module and a module is added, the host manufacturer is responsible for ensuring that the after the module is installed and operational the host continues to be compliant with the Part 15B unintentional radiator requirements. Manual Information To the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. IC Statement IRSS-GEN

"This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device." or "Le prsent appareil est conforme aux CNR dIndustrie Canada applicables aux appareils radio exempts de licence. Lexploitation est autorise aux deux conditions suivantes :

1) lappareil ne doit pas produire de brouillage; 2) lutilisateur de lappareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible den compromettre le fonctionnement."

Dclaration sur l'exposition aux rayonnements RF L'autre utilis pour l'metteur doit tre install pour fournir une distance de sparation d'au moins 20 cm de toutes les personnes et ne doit pas tre colocalis ou fonctionner conjointement avec une autre antenne ou un autre metteur. The host product shall be properly labeled to identify the modules within the host product. The Innovation, Science and Economic Development Canada certification label of a module shall be clearly visible at all times when installed in the host product; otherwise, the host product must be labeled to display the Innovation, Science and Economic Development Canada certification number for the module, preceded by the word Contains or similar wording expressing the same meaning, as follows:

Contains IC: 10224A-2022BG772A or where: 10224A-2022BG772A is the modules certification number. Le produit hte doit tre correctement tiquet pour identifier les modules dans le produit hte. L'tiquette de certification d'Innovation, Sciences et Dveloppement conomique Canada d'un module BG772A-GL_Hardware_Design 12 / 75 LPWA Module Series BG772A-GL Hardware Design doit tre clairement visible en tout temps lorsqu'il est installdans le produit hte; sinon, le produit hte doit porter une tiquette indiquant le numro de certification d'Innovation, Sciences et Dveloppement conomique Canada pour le module, prcd du mot Contient ou d'un libell semblable exprimant la mme signification, comme suit:

"Contient IC: 10224A-2022BG772A " ou "o: 10224A-2022BG772A est le numro de certification du module". 1.1. Special Mark Table 1: Special Mark Mark Definition

When an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin name, AT command, or argument is under development and currently not supported, unless otherwise specified. BG772A-GL_Hardware_Design 13 / 75 LPWA Module Series BG772A-GL Hardware Design 2 Product Concept 2.1. General Description BG772A-GL is an embedded IoT (LTE Cat M1, LTE Cat NB1/Cat NB2*) wireless communication module. It provides data connectivity on LTE-FDD network, and supports half-duplex operation in LTE network. It also provides optional GNSS* and voice* 1) functionality to meet customers specific application demands. The module is based on an architecture in which WWAN (LTE) and GNSS Rx chains share certain hardware blocks. However, the module does not support concurrent operation of WWAN and GNSS. The solution adopted in the module is a form of coarse time-division multiplexing (TDM) between WWAN and GNSS Rx chains. Given the relaxed latency requirements of most LPWA applications, time-division sharing of to applications. For more details, see document [1]. resources can be made largely transparent Table 2: Frequency Bands and GNSS Types of BG772A-GL Module Module Supported Bands Power Class GNSS*

Cat M1 1):

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/

B20/B25/B26/B27/B28/B66 Cat NB2 2):

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B17/B18/

B19/B20/B25/B28/B66 BG772A-GL NOTES 1. 2. 1) BG772A-GL supports VoLTE* (Voice over LTE) under LTE Cat M1. 2) LTE Cat NB2* is backward compatible with LTE Cat NB1. Power Class 3

(23 dBm 2.7 dB) GPS, GLONASS BG772A-GL_Hardware_Design 14 / 75 LPWA Module Series BG772A-GL Hardware Design With a compact profile of 14.9 mm 12.9 mm 1.9 mm, BG772A-GL can meet almost all requirements for M2M applications such as smart metering, tracking system, security, wireless POS, etc. It is especially suitable for size and weight sensitive applications such as smart watch and other wearable devices. BG772A-GL is an SMD type module which can be embedded into applications through its 94 LGA pads. It supports internet service protocols like TCP, UDP and PPP. Extended AT commands have been developed for customers to use these internet service protocols easily. 2.2. Key Features Table 3: Key Features of BG772A-GL Features Details Power Supply 1) VBAT_BB: 2.24.35 V, typical 3.3 V VBAT_RF: 3.14.2 V, typical 3.3 V Transmitting Power Class 3 (23 dBm 2.7 dB) for LTE-FDD bands LTE Features Internet Protocol Features SMS Supports 3GPP Rel-14*

Supports LTE Cat M1 and LTE Cat NB2*

Supports 1.4 MHz RF bandwidth for LTE Cat M1 Supports 200 kHz RF bandwidth for LTE Cat NB2 Cat M1: Max. 600 kbps (DL)/1000 kbps (UL) Cat NB2*: Max. 120 kbps (DL)/140 kbps (UL) Supports PPP/TCP/UDP/SSL/TLS/FTP(S)/HTTP(S)/NITZ*/PING/

MQTT/LwM2M*/CoAP* protocols Support PAP and CHAP for PPP connections Text and PDU modes Point-to-point MO and MT SMS cell broadcast SMS storage: ME by default

(U)SIM Interface Supports 1.8 V USIM/SIM card only PCM Interface*

Supports one digital audio interface: PCM interface for VoLTE only USB Interface*

Compliant with USB 2.0 specification Supports operation at full-speed (12 Mbps) only UART Interfaces Main UART:

Used for data transmission and AT command communication 115200 bps baud rate by default The default frame format is 8N1 (8 data bits, no parity, 1 stop bit) Supports RTS and CTS hardware flow control BG772A-GL_Hardware_Design 15 / 75 LPWA Module Series BG772A-GL Hardware Design Debug UART:

Used for firmware upgrade, software debugging and log output 115200 bps baud rate by default The default frame format is 8N1 (8 data bits, no parity, 1 stop bit) Support RTS and CTS hardware flow control AUX UART:

Used for RF calibration debugging and log output 921600 bps baud rate by default The default frame format is 8N1 (8 data bits, no parity, 1 stop bit) Supports RTS and CTS hardware flow control GNSS*

GPS, GLONASS AT Commands 3GPP TS 27.007 and 3GPP TS 27.005 AT commands Quectel enhanced AT commands Network Indication One NET_STATUS pin for network connectivity status indication Antenna Interfaces Main antenna (ANT_MAIN) and GNSS antenna (ANT_GNSS) interfaces Physical Characteristics Temperature Range Firmware Upgrade Dimensions: (14.9 0.2) mm (12.9 0.2) mm (1.9 0.2) mm Package: LGA Weight: TBD Operating temperature range: -35 C to +75 C 2) Extended temperature range: -40 C to +85 C 3) Storage temperature range: -40 C to +90 C Debug UART DFOTA*

RoHS All hardware components are fully compliant with EU RoHS directive. NOTES 1. 2. 3. 1) When the module starts up normally, to ensure full-function mode, the minimum power supply voltage should be higher than 3.1 V. 2) Within the operating temperature range, the module meets 3GPP specifications. 3) Within the extended temperature range, the module remains the ability to establish and maintain functions such as voice*, SMS and data transmission, without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may exceed the specified tolerances of 3GPP. When the temperature returns to the operating temperature range, the module meets 3GPP specifications again. BG772A-GL_Hardware_Design 16 / 75 LPWA Module Series BG772A-GL Hardware Design The following figure shows a block diagram of BG772A-GL and illustrates the major functional parts. 2.3. Functional Diagram Power management Baseband Radio frequency Peripheral interfaces Figure 1: Functional Diagram NOTE PCM and I2C interfaces are for VoLTE* only. BG772A-GL_Hardware_Design 17 / 75 LPWA Module Series BG772A-GL Hardware Design 2.4. Evaluation Board To facilitate application development with BG772A-GL conveniently, Quectel supplies the evaluation board (EVB), USB to RS-232 converter cables, USB data cables, earphone, antennas and other peripherals to control or test the module. For more details, see document [2]. BG772A-GL_Hardware_Design 18 / 75 LPWA Module Series BG772A-GL Hardware Design 3 Application Interfaces BG772A-GL is equipped with 94 LGA pads that can be connected to customers cellular application platforms. The subsequent chapters will provide detailed description of interfaces listed below:

Power supply PON_TRIG interface*

(U)SIM interface USB interface*

UART interfaces PCM and I2C interfaces*

Status indication interfaces ADC interfaces*

GPIO interfaces*

BG772A-GL_Hardware_Design 19 / 75 LPWA Module Series BG772A-GL Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of BG772A-GL. Figure 2: Pin Assignment (Top View) BG772A-GL_Hardware_Design 20 / 75 LPWA Module Series BG772A-GL Hardware Design NOTES 1. ADC input voltage must not exceed 1.8 V. 2. The input voltage range of USB_VBUS is 1.192.0 V. 3. Keep all RESERVED pins and unused pins unconnected. 4. GND pins should be connected to ground in the design. 5. PCM and I2C interfaces are for VoLTE* only. 3.2. Pin Description The following tables show the pin definition of BG772A-GL. Table 4: Definition of I/O Parameters Type AI AO AIO DI DO DIO NP OD PI PO PU PD Description Analog Input Analog Output Analog Input/Output Digital Input Digital Output Digital Input/Output No Pull Open Drain Power Input Power Output Pull Up Pull Down BG772A-GL_Hardware_Design 21 / 75 LPWA Module Series BG772A-GL Hardware Design Table 5: Pin Description Power Supply VBAT_RF VDD_EXT 20 21 Turn on/off Reset DC Characteristics Vmax = 4.35 V Vmin = 2.2 V Vnom = 3.3 V Vmax = 4.2 V Vmin = 3.1 V Vnom = 3.3 V DC Characteristics VILmax = 0.3 V VIHmin = 1.0 V DC Characteristics VILmax = 0.3 V VIHmin = 1.3 V Pin Name Pin No. I/O Description Comment VBAT_BB 19 Refer to NOTE 1 PI PI PO Power supply for the modules baseband part Power supply for the modules RF part Provide 1.8 V for external circuit Refer to NOTE 1 Vnom = 1.8 V IOmax = 50 mA If this pin is unused, keep it open. GND 2225, 27, 28, 30, 31, 43, 47, 5256, 58, 66, 7375, 8486, 88, 89 Pin Name Pin No. I/O Description Comment PWRKEY*

46 DI/PU Turn on/off the module Pin Name Pin No. I/O Description Comment RESET_N 45 DI/PU Reset the module Status Indication Pin Name Pin No. I/O Description DC Characteristics Comment STATUS 78 DO/PD NET_STATUS* 79 DO/PU USB Interface*

Indicate the module's operation status Indicate the module's network activity status 1.8 V 1.8 V If this pin is unused, keep it open. Pin Name Pin No. I/O Description Comment USB_VBUS 12 AI USB connection detect DC Characteristics VIHmax = 2.0 V VIHmin = 1.19 V BG772A-GL_Hardware_Design 22 / 75 LPWA Module Series BG772A-GL Hardware Design Compliant with USB 2.0 standard specification. Require differential impedance of 90 . USB_DP USB_DM 11 10 DIO DIO USBPHY_3P3 42 PI Vnom = 3.3 V 64 DO/PU 1.8 V USB differential data (+) USB differential data (-) Power supply for USB PHY circuit External LDO enable control for USB USBPHY_3P3 _EN

(U)SIM Interface USIM_DET*

USIM_VDD Pin Name Pin No. I/O Description DC Characteristics Comment DI/PD PO

(U)SIM card hot-plug detect 1.8 V If this pin is unused, keep it open.

(U)SIM card power supply Vmax = 1.9 V Vmin = 1.7 V Only 1.8 V (U)SIM card is supported. USIM_RST DO/PD

(U)SIM card reset 1.8 V USIM_DATA DIO/PU (U)SIM card data 1.8 V USIM_CLK DO/PD

(U)SIM card clock 1.8 V USIM_GND Main UART Interface Specified ground for (U)SIM card Pin Name Pin No. I/O Description DC Characteristics Comment MAIN_DTR 62 DI/PU MAIN_RXD MAIN_TXD MAIN_CTS MAIN_RTS MAIN_DCD MAIN_RI*

Main UART data terminal ready Main UART receive Main UART transmit Main UART clear to send Main UART request to send Main UART data carrier detect Main UART ring indication 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V DI/PU DO/PU DO/PU DI/PU DO/PU DO/PU 44 16 15 14 13 65 6 7 39 38 90 76 this pin is unused, If keep it open. BG772A-GL_Hardware_Design 23 / 75 LPWA Module Series BG772A-GL Hardware Design Debug UART Interface Pin Name Pin No. I/O Description DC Characteristics Comment Auxiliary UART Interface Pin Name Pin No. I/O Description DC Characteristics Comment DI/PU DO/PU DO/PU DI/PD Debug UART receive Debug UART transmit Debug UART clear to send Debug UART request to send DO/PU DI/PU DO/PU DI/PU Auxiliary UART transmit Auxiliary UART receive Auxiliary UART clear to send Auxiliary UART request to send 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V DBG_RXD DBG_TXD DBG_CTS DBG_RTS AUX_TXD AUX_RXD AUX_CTS AUX_RTS PCM Interface*

61 60 51 92 93 82 70 59 3 35 2 34 Pin Name Pin No. I/O Description DC Characteristics Comment PCM_CLK DO/PD PCM clock PCM_SYNC DO/PU PCM data frame sync PCM_DIN DI/PU PCM data input 1.8 V PCM_DOUT DO/PU PCM data output 1.8 V I2C Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment I2C_SCL 37 OD I2C serial clock

(for external codec) this pin is unused, If keep it open. If this pin is unused, keep it open. If this pin is unused, keep it open. External pull-up resistor is required. 1.8 V only. If keep it open. this pin is unused, BG772A-GL_Hardware_Design 24 / 75 LPWA Module Series BG772A-GL Hardware Design External pull-up resistor is required. 1.8 V only. If this pin is unused, keep it open. I2C_SDA 5 OD I2C serial data (for external codec) Antenna Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment Pin Name Pin No. I/O Description DC Characteristics Comment 50 impedance. 50 impedance. If keep it open. this pin is unused, If this pin is unused, keep it open. BOOT_CONFIG. Do not pull it up before startup. If this pin is unused, keep it open. If this pin is unused, keep it open. ANT_MAIN 26 AIO ANT_GNSS 32 AI GPIO Interfaces*

Main antenna interface GNSS antenna interface DIO/PU DIO/PD DIO/PD General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output 1.8 V 1.8 V 1.8 V 1.8 V GPIO4 33 DIO/PD GPIO5 40 DIO/PD General-purpose input/output 1.8 V DIO/PU DIO/PU General-purpose input/output General-purpose input/output 1.8 V 1.8 V GPIO1 GPIO2 GPIO3 GPIO6 GPIO7 ADC0 ADC1 1 8 9 57 63 17 18 ADC Interfaces*

Pin Name Pin No. I/O Description Comment AI AI General-purpose ADC interface General-purpose ADC interface DC Characteristics Voltage range:

01.8 V Voltage range:

01.8 V If this pin is unused, keep it open. BG772A-GL_Hardware_Design 25 / 75 Other Interface Pins Pin Name Pin No. I/O Description DC Characteristics Comment W_DISABLE#*

41 DI/PU Airplane mode control 1.8 V AP_READY*

77 DI/PU Application processor ready 1.8 V PON_TRIG*

72 DI/NP Wake up the module from PSM 1.8 V LPWA Module Series BG772A-GL Hardware Design Pulled up by default. When it is at low voltage level, the module can enter airplane mode. If this pin is unused, keep it open. If this pin is unused, keep it open. Wakeup active high for minimum assertion time 100 s. No pulled by default. If this pin is unused, keep it open. Pin Name Pin No. I/O Description DC Characteristics Comment DO/PD DO/PD Generic RF controller Generic RF controller 1.8 V 1.8 V If this pin is unused, keep it open. GRFC Interfaces*

GRFC1 GRFC2 83 94 RESERVED Pins Pin Name Pin No. I/O Description DC Characteristics Comment RESERVED 4, 29, 36, 4850, 6769, 71, 8081, 87,91 Keep these pins open. NOTES 1. When the module starts up normally, to ensure full-function mode, the minimum power supply voltage should be higher than 3.1 V. 2. The input voltage range of USB_VBUS is 1.192.0 V. 3. USBPHY_3P3 and USBPHY_3P3_EN pins are used for USB PHY circuits. 4. ADC input voltage must not exceed 1.8 V. 5. Keep all RESERVED pins and unused pins unconnected. 6. PCM and I2C interfaces are for VoLTE* only. BG772A-GL_Hardware_Design 26 / 75 LPWA Module Series BG772A-GL Hardware Design 3.3. Operating Modes The table below briefly summarizes the various operating modes of BG772A-GL. Table 6: Overview of Operating Modes Mode Details Connected The module is connected to network. Its current consumption varies with the network setting and data transfer rate. Idle The module remains registered on network, and is ready to send and receive data. In this mode, the software is active. The module and the network may negotiate over non-access stratum signaling the use of e-I-DRX for reducing power consumption, while being available for mobile terminating data and/or network originated procedures within a certain delay dependent on the DRX cycle value. AT+CFUN=4 or W_DISABLE#* pin can set the module into airplane mode where the RF function is invalid. AT+CFUN=0 can set the module into a minimum functionality mode without removing the power supply. In this mode, both RF function and (U)SIM card are invalid. The module remains the ability to receive paging message, SMS and TCP/UDP data from the network normally. In this mode, the current consumption is reduced to a low level. The modules power supply is shut down by its power management unit. In this mode, the software is inactive, the serial interfaces are inaccessible, while the operating voltage (connected to VBAT) remains applied. PSM is similar to power-off, but the module remains registered on the network and there is no need to re-attach or re-establish PDN connections. The current consumption is reduced to a minimized level. Normal Operation Extended Idle Mode DRX

(e-I-DRX) Airplane Mode Minimum Functionality Mode Sleep Mode*

Power OFF Mode Power Saving Mode (PSM)*

NOTE During e-I-DRX, it is recommended to use UART interface for data communication, as the use of USB interface will increase power consumption. BG772A-GL_Hardware_Design 27 / 75 LPWA Module Series BG772A-GL Hardware Design 3.4. Power Saving 3.4.1. Airplane Mode When the module enters airplane mode, the RF function does not work, and all AT commands correlative with RF function will be inaccessible. This mode can be set via the following ways. W_DISABLE#* is pulled up by default. Driving it low will let the module enter airplane mode. AT+CFUN=<fun> provides choice of the functionality level, through setting <fun> into 0, 1 or 4. AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled. AT+CFUN=1: Full functionality mode (by default). AT+CFUN=4: Airplane mode. RF function is disabled. Hardware:

Software:

NOTES 1. Airplane mode control via W_DISABLE#* is disabled in firmware by default. It can be enabled by AT+QCFG="airplanecontrol". For details of the command, see document [3]. 2. The execution of AT+CFUN command will not affect GNSS function. 3.4.2. Power Saving Mode (PSM)*

BG772A-GL module minimizes its power consumption through entering PSM. The mode is similar to power-off, but the module remains registered on the network and there is no need to re-attach or re-establish PDN connections. So BG772A-GL in PSM cannot immediately respond users requests. When the module wants to use the PSM, it shall request an Active Time value during every Attach and TAU procedures. If the network supports PSM and accepts that the module uses PSM, the network confirms usage of PSM by allocating an Active Time value to the module. If the module wants to change the Active Time value, e.g. when the conditions are changed in the module, the module requests the value it wants in the TAU procedure. If PSM is supported by the network, then it can be enabled via AT+CPSMS*. Either of the following methods will wake up the module from PSM:

PON_TRIG active high for minimum assertion time 100 s will wake up the module from PSM.

(recommended) When RTC expiration will wake up the module. BG772A-GL_Hardware_Design 28 / 75 LPWA Module Series BG772A-GL Hardware Design NOTE See document [4] for details about AT+CPSMS. 3.4.3. Extended Idle Mode DRX (e-I-DRX) The module (UE) and the network may negotiate over non-access stratum signalling the use of e-I-DRX for reducing its power consumption, while being available for mobile terminating data and/or network originated procedures within a certain delay dependent on the DRX cycle value. Applications that want to use e-I-DRX need to consider specific handling of mobile terminating services or data transfers, and in particular they need to consider the delay tolerance of mobile terminated data. In order to negotiate the use of e-I-DRX, the UE requests e-I-DRX parameters during attach procedure and RAU/TAU procedure. The EPC may reject or accept the UE request for enabling e-I-DRX. In case the EPC accepts e-I-DRX, the EPC based on operator policies and, if available, the e-I-DRX cycle length value in the subscription data from the HSS, may also provide different values of the e-I-DRX parameters than what was requested by the UE. If the EPC accepts the use of e-I-DRX, the UE applies e-I-DRX based on the received e-I-DRX parameters. If the UE does not receive e-I-DRX parameters in the relevant accept message because the EPC rejected its request or because the request was received by EPC not supporting e-I-DRX, the UE shall apply its regular discontinuous reception. If e-I-DRX is supported by the network, then it can be enabled by AT+CEDRXS=1. NOTE See document [4] for details about AT+CEDRXS. 3.4.4. Sleep Mode 3.4.4.1.UART Application BG772A-GL can reduce its current consumption to a lower value during the sleep mode. The following sub-chapters describe the power saving procedure of BG772A-GL. If the host communicates with the module via UART interface, the following preconditions can let the module enter sleep mode. Execute AT+QSCLK=1 command to enable sleep mode. Drive MAIN_DTR high. BG772A-GL_Hardware_Design 29 / 75 The following figure shows the connection between the module and the host. LPWA Module Series BG772A-GL Hardware Design Figure 3: Sleep Mode Application via UART When BG772A-GL has a URC to report, MAIN_RI signal will wake up the host. See Chapter 3.14 for details about MAIN_RI behavior. Driving the MAIN_DTR low will wake up the module. AP_READY* will detect the sleep state of the host (can be configured to high voltage level or low voltage level detection). See AT+QCFG="apready" in document [3] for details. 3.5. Power Supply 3.5.1. Power Supply Pins BG772A-GL provides VBAT_BB and VBAT_RF two pins for connection with an external power supply. The following table shows the details of VBAT_BB and VBAT_RF pins and ground pins. Table 7: VBAT and GND Pins VBAT_BB 1) 19 VBAT_RF 1) 20 Pin Name Pin No. Description Min. Typ. Max. Unit Power supply for the modules baseband part Power supply for modules RF part the 2.2 3.3 4.35 3.1 3.3 4.2

V V

GND 2225, 27, 28, 30, 31, 47, 5256, 58, 66, 7375, 8486, 88, 89 BG772A-GL_Hardware_Design 30 / 75 LPWA Module Series BG772A-GL Hardware Design NOTE 1) When the module starts up normally, to ensure full-function mode, the minimum power supply voltage should be higher than 3.1 V. 3.5.2. Decrease Voltage Drop The power supply VBAT_BB range of BG772A-GL is from 2.2 V to 4.35 V, the power supply VBAT_RF range of BG772A-GL is from 3.1 V to 4.2 V. When the module starts up normally, to ensure full-function mode, the minimum power supply voltage should be higher than 3.1 V. To decrease voltage drop, a bypass capacitor of about 100 F with low ESR should be used, and a multi-layer ceramic chip capacitor (MLCC) array should also be reserved due to its low ESR. It is recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC array, and place these capacitors close to VBAT pins. The main power supply from an external application has to be a single voltage source and can be expanded to two sub paths with star structure. The width of VBAT trace should be no less than 1 mm. In principle, the longer the VBAT trace is, the wider it will be. In addition, to get a stable power source, it is suggested to use a TVS with low leakage current and suitable reverse stand-off voltage, and also it is recommended to place it as close to the VBAT pins as possible. The following figure shows the star structure of the power supply. Figure 4: Star Structure of the Power Supply BG772A-GL_Hardware_Design 31 / 75 LPWA Module Series BG772A-GL Hardware Design 3.6. Turn on and off Scenarios 3.6.1. Pin Definition of PWRKEY The following table shows the pin definition of PWRKEY. Table 8: Pin Definition of PWRKEY Pin Name Pin No. Description DC Characteristics Comment PWRKEY*

46 Turn on/off the module VILmax = 0.3 V VIHmin = 1.0 V Internally pulled up resistor is 470 k. 3.6.2. Turn on Module Using PWRKEY When the module is in power off mode, it can be turned on by driving PWRKEY low for at least 500 ms. It is recommended to use an open drain/collector driver to control the PWRKEY. A simple reference circuit is illustrated in the following figure. Figure 5: Turn on the Module by Using Driving Circuit Another way to control the PWRKEY is by using a button directly. When pressing the button, electrostatic strike may generate from the finger. Therefore, a TVS component is indispensable to be placed near the button for ESD protection. A reference circuit is shown in the following figure. BG772A-GL_Hardware_Design 32 / 75 LPWA Module Series BG772A-GL Hardware Design Figure 6: Turn on the Module by Using Keystroke The power-up scenario is illustrated in the following figure. Figure 7: Power-up Timing BG772A-GL_Hardware_Design 33 / 75 LPWA Module Series BG772A-GL Hardware Design NOTE Ensure that VBAT is stable before pulling down PWRKEY pin and keep the interval no less than 30 ms. 3.6.3. Turn off Module Either of the following methods can be used to turn off the module normally:

Turn off the module through PWRKEY. Turn off the module through AT+QPOWD. 3.6.3.1.Turn off Module through PWRKEY Drive the PWRKEY pin low for 6501500 ms and then releasing it, the module will execute power-down procedure. The power-down timing is illustrated in the following figure. Figure 8: Power-down Timing 3.6.3.2.Turn off Module through AT Command It is also a safe way to use AT+QPOWD to turn off the module, which is similar to turning off the module with PWRKEY. See document [4] for details about AT+QPOWD. BG772A-GL_Hardware_Design 34 / 75 LPWA Module Series BG772A-GL Hardware Design 3.7. Reset the Module RESET_N is used to reset the module. The module can be reset by driving RESET_N low for minimum assertion time 100 ms. Table 9: Pin Definition of RESET_N Pin Name Pin No. Description DC Characteristics Comment RESET_N 45 Reset the module VILmax = 0.3 V VIHmin = 1.3 V The reset timing is illustrated in the following figure. Figure 9: Reset Timing The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET_N pin. Figure 10: Reference Circuit of RESET_N by Using Driving Circuit BG772A-GL_Hardware_Design 35 / 75 LPWA Module Series BG772A-GL Hardware Design Figure 11: Reference Circuit of RESET_N by Using Button NOTE Ensure that there is no large capacitance on RESET_N pin. 3.8. PON_TRIG*

BG772A-GL provides one PON_TRIG pin which is used to wake up the module from PSM. When the pin detects high level for minimum assertion time 100 s, the module will wake up from PSM. Table 10: Pin Definition of PON_TRIG Pin Name Pin No. I/O Description Comment PON_TRIG 72 DI/NP Wake up the module from PSM 1.8 V power domain. Wakeup active high for minimum assertion time 100 s . No pulled by default. BG772A-GL_Hardware_Design 36 / 75 A reference circuit is shown in the following figure. LPWA Module Series BG772A-GL Hardware Design Figure 12: Reference Circuit of PON_TRIG NOTE VDD_1V8 is provided by an external LDO. 3.9.

(U)SIM Interface BG772A-GL supports 1.8 V (U)SIM card only. The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Table 11: Pin Definition of (U)SIM Interface Pin No. 16 15 Pin Name I/O Description Comment USIM_DET*

44 DI/PD

(U)SIM card hot-plug detect 1.8 V power domain. USIM_VDD PO

(U)SIM card power supply Only 1.8 V (U)SIM card is supported. USIM_RST DO/PD (U)SIM card reset 1.8 V power domain. USIM_DATA 14 DIO/PU (U)SIM card data 1.8 V power domain. USIM_CLK 13 DO/PD (U)SIM card clock 1.8 V power domain. USIM_GND 65 Specified ground for card

(U)SIM BG772A-GL_Hardware_Design 37 / 75 LPWA Module Series BG772A-GL Hardware Design BG772A-GL supports (U)SIM card hot-plug via USIM_DET, and both high- and low- level detections are supported. The function is disabled by default, and see AT+QSIMDET in document [4] for more details. The following figure shows a reference design of (U)SIM interface with an 8-pin (U)SIM card connector. Figure 13: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, keep USIM_DET unconnected. A reference circuit for

(U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure. Figure 14: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector To enhance the reliability and availability of the (U)SIM card in applications, follow the criteria below in

(U)SIM circuit design:

BG772A-GL_Hardware_Design 38 / 75 LPWA Module Series BG772A-GL Hardware Design Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace length as less than 200 mm as possible. Keep (U)SIM card signals away from RF and VBAT traces. Assure the ground between the module and the (U)SIM card connector short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5 mm to maintain the same electric potential. Make sure the bypass capacitor between USIM_VDD and USIM_GND less than 1 F, and place it as close to (U)SIM card connector as possible. If the system ground plane is complete, USIM_GND can be connected to the system ground directly. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with surrounded ground. USIM_RST should also be ground shielded. To offer good ESD protection, it is recommended to add a TVS diode array with parasitic capacitance not exceeding 15 pF. In order to facilitate debugging, it is recommended to reserve series resistors for the (U)SIM signals of the module. The 33 pF capacitors are used for filtering interference of EGSM900. Note that the (U)SIM peripheral circuit should be close to the (U)SIM card connector. The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace and sensitive occasion are applied, and should be placed close to the (U)SIM card connector. 3.10. USB Interface*

BG772A-GL contains one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0 specification and supports operation at full-speed (12 Mbps) mode only. The USB interface is under development, it is not recommended to use at present. The following table shows the pin definition of USB interface. Table 12: Pin Definition of USB Interface Pin Name Pin No. I/O Description Comment USB_VBUS USB_DP USB_DM USBPHY_3P3 12 11 10 42 43 AI DIO DIO PI USB connection detect Input range: 1.192.0 V USB differential data (+) USB differential data (-) Power supply for USB PHY circuit External control for USB LDO enable Require differential impedance of 90 Vnom = 3.3 V USBPHY_3P3_EN 64 DO/PU 1.8 V power domain GND Ground For more details about USB 2.0 specification, visit http://www.usb.org/home. BG772A-GL_Hardware_Design 39 / 75 The following figures illustrate reference designs of USB PHY and USB interface. LPWA Module Series BG772A-GL Hardware Design Figure 15: Reference Design of USB PHY Figure 16: Reference Design of USB Interface To ensure the integrity of USB data trace signal, components R3 and R4 should be placed close to the module, and also these resistors should be placed close to each other. The extra stubs of trace must be as short as possible. To meet USB 2.0 specification, comply with the following principles while designing the USB interface. It is important to route the USB signal traces as differential pairs with ground surrounded. The impedance of USB differential trace is 90 . Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is important to route the USB differential traces in inner-layer of the PCB, and surround the traces with ground on that layer and with ground planes above and below. Junction capacitance of the ESD protection device might cause influences on USB data lines, so pay BG772A-GL_Hardware_Design 40 / 75 LPWA Module Series BG772A-GL Hardware Design attention to the selection of the device. Typically, the stray capacitance should be less than 2 pF. Keep the ESD protection devices as close to the USB connector as possible. NOTES 1. The USB interface is under development, it is not recommended to use at present. 2. The input voltage range of USB_VBUS is 1.192.0 V. 3.11. UART Interfaces The module provides three UART interfaces: the main UART interface, the debug UART interface and the auxiliary UART interface. Features of them are illustrated below:

The main UART interface supports 9600 bps, 19200 bps, 38400 bps, 57600 bps, 115200 bps, 230400 bps, 460800 bps, 921600 bps and 3000000 bps baud rates, and the default is 115200 bps. It is used for data transmission and AT command communication, and supports RTS and CTS hardware flow control. The default frame format is 8N1 (8 data bits, no parity, 1 stop bit). The debug UART interface supports 9600 bps, 19200 bps, 38400 bps, 57600 bps, 115200 bps, 230400 bps, 460800 bps, 921600 bps and 3000000 bps baud rates, and the default is 115200 bps. It is used for firmware upgrade, software debugging and log output, and supports RTS and CTS hardware flow control. The default frame format is 8N1 (8 data bits, no parity, 1 stop bit). The auxiliary UART interface supports 921600 bps baud rate by default, and is used for RF calibration and log output, and supports RTS and CTS hardware flow control. The default frame format is 8N1 (8 data bits, no parity, 1 stop bit). The following tables show the pin definition of three UART interfaces. Table 13: Pin Definition of Main UART Interface Pin Name Pin No. I/O Description Comment MAIN_DTR 62 DI/PU Main UART data terminal ready MAIN_RXD DI/PU Main UART receive MAIN_TXD MAIN_CTS MAIN_RTS 6 7 39 38 90 DO/PU Main UART transmit DO/PU Main UART clear to send DI/PU Main UART request to send 1.8 V power domain MAIN_DCD DO/PU Main UART data carrier detect BG772A-GL_Hardware_Design 41 / 75 LPWA Module Series BG772A-GL Hardware Design MAIN_RI*

76 DO/PU Main UART ring indication NOTE DBG_TXD DBG_RXD DBG_CTS DBG_RTS AUX_TXD AUX_RXD AUX_CTS AUX_RTS 60 61 51 92 93 82 70 59 AT+IPR command can be used to set the baud rate of the main UART interface, and AT+IFC command can be used to set the hardware flow control (the function is disabled by default). See document [4] for more details about these AT commands. Table 14: Pin Definition of Debug UART Interface Pin Name Pin No. I/O Description Comment DO/PU Debug UART transmit DI/PU Debug UART receive DO/PU Debug UART clear to send DI/PD Debug UART request to send 1.8 V power domain Table 15: Pin Definition of Auxiliary UART Interface Pin Name Pin No. I/O Description Comment DO/PU Auxiliary UART transmit DI/PU Auxiliary UART receive DO/PU Auxiliary UART clear to send DI/PU Auxiliary UART request to send 1.8 V power domain The module provides 1.8 V UART interfaces. A voltage-level translator should be used if customers application is equipped with a 3.3 V UART interface. The following figure shows a reference design of the main UART interface:

BG772A-GL_Hardware_Design 42 / 75 LPWA Module Series BG772A-GL Hardware Design Figure 17: Main UART Reference Design (Translator Chip) Visit http://www.ti.com for more information. Another example with transistor translation circuit is shown as below. For the design of circuits in dotted lines, refer to that of circuits in solid lines, but pay attention to the direction of connection. Figure 18: Main UART Reference Design (Transistor Circuit) NOTES chip. 1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps. 2. The main UART of the module shouldnt be asserted high during PSM, otherwise, it will damage the BG772A-GL_Hardware_Design 43 / 75 LPWA Module Series BG772A-GL Hardware Design 3.12. PCM and I2C Interfaces*

interface and one I2C interface for BG772A-GL provides one Pulse Code Modulation (PCM) digital VoLTE only. The following table shows the pin definition of the two interfaces which can be applied on audio codec design. Table 16: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Description Comment PCM_CLK DO/PD PCM clock PCM_SYNC 35 DO/PU PCM data frame sync PCM_DIN DI/PU PCM data input PCM_DOUT 34 DO/PU PCM data output I2C_SCL I2C_SDA OD OD I2C serial clock (for external codec) I2C serial data (for external codec) 3 2 37 5 1.8 V power domain Require external pull-up to 1.8 V Require external pull-up to 1.8 V The following figure shows a reference design of PCM and I2C interfaces with an external codec IC. Figure 19: Reference Circuit of PCM Application with Audio Codec NOTE PCM and I2C interfaces support VoLTE only. BG772A-GL_Hardware_Design 44 / 75 LPWA Module Series BG772A-GL Hardware Design 3.13. Network Status Indication*

BG772A-GL provides one network status indication pin: NET_STATUS. The pin is used to drive a network status indication LED. The following tables describe the pin definition and logic level changes of NET_STATUS in different network activity status. Table 17: Pin Definition of NET_STATUS Pin Name Pin No. I/O Description Comment NET_STATUS 79 DO/PU 1.8 V power domain. Indicate the module's network activity status Table 18: Working State of NET_STATUS Pin Name Logic Level Changes Network Status Flicker slowly (200 ms High/1800 ms Low) Network searching NET_STATUS Flicker slowly (1800 ms High/200 ms Low) Idle Flicker quickly (125 ms High/125 ms Low) Data transfer is ongoing Always high Voice calling A reference circuit is shown in the following figure. Figure 20: Reference Design of NET_STATUS BG772A-GL_Hardware_Design 45 / 75 LPWA Module Series BG772A-GL Hardware Design 3.14. STATUS The STATUS pin is used to indicate the operation status of BG772A-GL. It outputs high level when the module powers on. The following table describes the pin definition of STATUS. Table 19: Pin Definition of STATUS Pin Name Pin No. I/O Description Comment STATUS 78 DO/PD Indicate the module's operation status 1.8 V power domain The following figure shows a reference circuit of STATUS. Figure 21: Reference Design of STATUS 3.15. Behaviors of MAIN_RI*

AT+QCFG="risignaltype","physical" can be used to configure MAIN_RI behavior. No matter on which port URC is presented, URC will trigger the behavior of MAIN_RI pin. The default behaviors of MAIN_RI are shown as below. Table 20: Default Behaviors of MAIN_RI State Idle URC Response MAIN_RI keeps in high level. MAIN_RI outputs 120 ms low pulse when new URC returns. BG772A-GL_Hardware_Design 46 / 75 LPWA Module Series BG772A-GL Hardware Design The default MAIN_RI behaviors can be configured flexibly by AT+QCFG="urc/ri/ring"* command. For more details about AT+QCFG, see document [3]. NOTE A URC can be outputted from UART port, through configuration via AT+QURCCFG. 3.16. ADC Interfaces*

The module provides two analog-to-digital converter (ADC) interfaces. AT+QADC=0 can be used to read the voltage value on ADC0 pin. AT+QADC=1 be used to read the voltage value on ADC1 pin. For more details about the AT command, see document [4]. To improve the accuracy of ADC voltage values, the trace of ADC should be surrounded with ground. Table 21: Pin Definition of ADC Interfaces Pin Name Pin No. I/O Description ADC0 ADC1 17 18 AI AI General-purpose ADC interface General-purpose ADC interface The following table describes the characteristics of ADC interfaces. Table 22: Characteristics of ADC Interfaces Parameter Min. Typ. Max. Unit Voltage Range Resolution Input Resistance 0 6 1.8 12 0.5 V bit k BG772A-GL_Hardware_Design 47 / 75 LPWA Module Series BG772A-GL Hardware Design NOTES 1. ADC input voltage must not exceed 1.8 V. 2. 3. It is prohibited to supply any voltage to ADC pin when VBAT is removed. It is recommended to use resistor divider circuit for ADC application, and the dividers resistor accuracy should be no less than 1 %. 3.17. GPIO Interfaces*

The module provides seven general-purpose input and output (GPIO) interfaces. AT+QCFG="gpio" can the AT command, see be used to configure the status of GPIO pins. For more details about document [3]. Table 23: Pin Definition of GPIO Interfaces Pin Name Pin No. Description GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 1 8 9 33 40 57 63 General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output BG772A-GL_Hardware_Design 48 / 75 LPWA Module Series BG772A-GL Hardware Design 3.18. GRFC Interfaces*

The module provides two generic RF control interfaces for the control of external antenna tuners. Table 24: Pin Definition of GRFC Interfaces Pin Name Pin No. Description Comments GRFC1 GRFC2 83 94 Generic RF controller 1.8 V power domain. Generic RF controller 1.8 V power domain. Table 25: Truth Table of GRFC Interfaces GRFC1 Level GRFC2 Level Frequency Range (MHz) Band Low Low High High Low High Low High TBD TBD TBD TBD TBD TBD TBD TBD BG772A-GL_Hardware_Design 49 / 75 LPWA Module Series BG772A-GL Hardware Design 4 GNSS Receiver*

4.1. General Description BG772A-GL supports GPS and GLONASS satellite systems using dedicated hardware accelerators in a power and cost-efficient manner. The module supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1 Hz data update rate via debug UART interface by default. By default, BG772A-GL GNSS engine is switched off. It has to be switched on via AT command. The module does not support concurrent operation of WWAN and GNSS. For more details about GNSS engine technology and configurations, see document [1]. 4.2. GNSS Performance The following table shows the GNSS performance of BG772A-GL. Table 26: GNSS Performance Parameter Description Conditions Sensitivity

(GNSS) TTFF

(GNSS) Cold start Autonomous Reacquisition Autonomous Tracking Autonomous Cold start

@ open sky Warm start

@ open sky Autonomous XTRA enabled Autonomous XTRA enabled Hot start Autonomous Typ.

-145

-153

-158 TBD TBD TBD TBD TBD Unit dBm dBm dBm s s s s s BG772A-GL_Hardware_Design 50 / 75 LPWA Module Series BG772A-GL Hardware Design

@ open sky CEP-50 XTRA enabled Autonomous

@ open sky TBD 1.41 s m Accuracy

(GNSS) NOTES 1. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep 2. Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock positioning for at least 3 minutes continuously). within 3 minutes after loss of lock. 3. Cold start sensitivity:

the minimum GNSS signal power at which the module can fix position successfully within 3 minutes after executing cold start command. 4.3. Layout Guidelines The following layout guidelines should be taken into account in application designs. Maximize the distance between GNSS antenna and main antenna. Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card should be kept away from antennas. Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar isolation and protection. Keep 50 characteristic impedance for ANT_GNSS trace. Refer to Chapter 5 for GNSS antenna reference design and antenna installation information. BG772A-GL_Hardware_Design 51 / 75 LPWA Module Series BG772A-GL Hardware Design 5 Antenna Interfaces BG772A-GL includes a main antenna interface and a GNSS antenna interface. The impedance of antenna port is 50 . 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of the main antenna interface is shown below. Table 27: Pin Definition of Main Antenna Interface Pin Name Pin No. I/O Description Comment ANT_MAIN 26 AIO Main antenna interface 50 impedance 5.1.2. Operating Frequency Table 28: BG772A-GL Operating Frequency 3GPP Band Transmit LTE-FDD B1 19201980 LTE-FDD B2 18501910 LTE-FDD B3 17101785 LTE-FDD B4 17101755 LTE-FDD B5 LTE-FDD B8 LTE-FDD B12 824849 880915 699716 Receive 21102170 19301990 18051880 21102155 869894 925960 729746 Unit MHz MHz MHz MHz MHz MHz MHz BG772A-GL_Hardware_Design 52 / 75 LPWA Module Series BG772A-GL Hardware Design LTE-FDD B13 LTE-FDD B17 1) LTE-FDD B18 LTE-FDD B19 LTE-FDD B20 LTE-FDD B26 2) LTE-FDD B27 2) LTE-FDD B28 777787 704716 815830 830845 832862 814849 807824 703748 746756 734746 860875 875890 791821 859894 852869 758803 LTE-FDD B25 18501915 19301995 LTE-FDD B66 17101780 21102180 NOTES 1. 2. 1) LTE-FDD B17 is supported by Cat NB2 only. 2) LTE-FDD B26 and B27 are supported by Cat M1 only. MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 5.1.3. Reference Design of Main Antenna Interface A reference design of main antenna interface is shown as below. It is recommended to reserve a -type matching circuit for better RF performance, and the -type matching components (R1/C1/C2) should be placed as close to the antenna as possible. The capacitors are not mounted by default. Figure 22: Reference Design of Main Antenna Interface BG772A-GL_Hardware_Design 53 / 75 LPWA Module Series BG772A-GL Hardware Design 5.2. GNSS Antenna Interface The following tables show the pin definition and frequency specification of GNSS antenna interface. 5.2.1. Pin Definition Table 29: Pin Definition of GNSS Antenna Interface Pin Name Pin No. I/O Description Comment ANT_GNSS 32 AI GNSS antenna interface 50 impedance 5.2.2. GNSS Operating Frequency Table 30: GNSS Operating Frequency Type GPS Frequency 1575.42 1.023 GLONASS 1597.51605.8 Unit MHz MHz 5.2.3. Reference Design of GNSS Antenna Interface A reference design of GNSS antenna interface is shown as below. Figure 23: Reference Circuit of GNSS Antenna Interface BG772A-GL_Hardware_Design 54 / 75 LPWA Module Series BG772A-GL Hardware Design NOTE The module of BG772A-GL is designed with a passive antenna. 5.3. Antenna Installation 5.3.1. Reference Design of RF Layout For users PCB, the characteristic impedance of all RF traces should be controlled to 50 . The impedance of RF traces is usually determined by the trace width (W), the materials dielectric constant, layer (H), and the clearance between RF traces and height from the reference ground to the signal grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB structures. Figure 24: Microstrip Design on a 2-layer PCB Figure 25: Coplanar Waveguide Design on a 2-layer PCB BG772A-GL_Hardware_Design 55 / 75 LPWA Module Series BG772A-GL Hardware Design Figure 26: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 27: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design:

Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully 50 . connected to ground. The distance between the RF pins and the RF connector should be as short as possible, and all the right-angle traces should be changed to curved ones. There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be no less than two times the width of RF signal traces (2 W). Keep RF traces away from interference sources, and avoid intersection and paralleling between traces on adjacent layers. BG772A-GL_Hardware_Design 56 / 75 LPWA Module Series BG772A-GL Hardware Design For more details about RF layout, see document [5]. 5.3.2. Antenna Requirements The following table shows the requirements on main antenna and GNSS antenna. Table 31: Antenna Requirements Antenna Type Requirements Frequency range: 15591609 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0 dBi Active antenna noise figure: < 1.5 dB Active antenna gain: > 0 dBi Active antenna embedded LNA gain: < 17 dB VSWR: 2 Efficiency: > 30 %

Max Input Power (W): 50 Input Impedance (): 50 Cable Insertion Loss: < 1 dB

(LTE B5/B8/B12/B13/B17/B18/B19/B20/B26/B27/B28) Cable Insertion Loss: < 1.5 dB

(LTE B1/B2/B3/B4/B25/B66) GNSS 1) LTE NOTE 1) It is recommended to use a passive GNSS antenna when LTE B13 is supported, as the use of active antenna may generate harmonics which will affect the GNSS performance. BG772A-GL_Hardware_Design 57 / 75 LPWA Module Series BG772A-GL Hardware Design 5.3.3. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use U.FL-R-SMT connectors provided by HIROSE. Figure 28: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 29: Mechanicals of U.FL-LP Connectors BG772A-GL_Hardware_Design 58 / 75 The following figure describes the space factor of mated connector. LPWA Module Series BG772A-GL Hardware Design Figure 30: Space Factor of Mated Connector (Unit: mm) For more details, visit http://www.hirose.com. BG772A-GL_Hardware_Design 59 / 75 LPWA Module Series BG772A-GL Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 32: Absolute Maximum Ratings Parameter VBAT_BB VBAT_RF USB_VBUS Voltage at Digital Pins Min.

-0.2

1.19

-0.3 6.2. Power Supply Ratings Table 33: Power Supply Ratings Max. Unit 4.5 4.6 2.0 2.0 V V V V Parameter Description Conditions Min. Typ. Max. Unit VBAT_BB 1) Power supply for the modules baseband part 2.2 3.3 4.35 V The actual input voltages must be kept between the minimum and maximum values. VBAT_RF 1) Power supply for modules RF part the The actual input voltages must be kept between 3.1 3.3 4.2 V BG772A-GL_Hardware_Design 60 / 75 LPWA Module Series BG772A-GL Hardware Design USBPHY_3P3 Power supply for USB PHY circuit the minimum and maximum values. USB_VBUS USB connection detect 1.19 2.0 3.3 V V NOTE 1) When the module starts up normally, in order to ensure full-function mode, the minimum power supply voltage should be higher than 3.1 V. 6.3. Operating and Storage Temperatures The operating and storage temperatures of the module are listed in the following table. Table 34: Operating and Storage Temperatures Parameter Min. Max. Unit Operating Temperature Range 1)

-35 Extended Temperature Range 2)

-40 Storage Temperature Range

-40 Typ.

+25

+75

+85

+90 C C C NOTES 1. 2. 1) Within the operating temperature range, the module meets 3GPP specifications. 2) Within the extended temperature range, the module remains the ability to establish and maintain functions such as voice*, SMS and data transmission, without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may exceed the specified tolerances of 3GPP. When the temperature returns to the operating temperature range, the module meets 3GPP specifications again. BG772A-GL_Hardware_Design 61 / 75 LPWA Module Series BG772A-GL Hardware Design 6.4. Current Consumption The following table shows current consumption of BG772A-GL. Table 35: BG772A-GL Current Consumption (Power Supply: 3.3 V, Room Temperature) Description Conditions Avg. Max. Unit Leakage Power-off @ USB/UART disconnected PSM PSM @ USB/UART disconnected Rock Bottom AT+CFUN=0 @ Sleep mode Sleep Mode

(USB/UART disconnected) Idle State

(USB/UART disconnected) LTE Cat M1 data transfer

(GNSS OFF) LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE-FDD B1 @ dBm LTE-FDD B2 @ dBm LTE-FDD B3 @ dBm LTE-FDD B4 @ dBm LTE-FDD B5 @ dBm LTE-FDD B8 @ dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

TBD TBD TBD TBD TBD TBD A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA BG772A-GL_Hardware_Design 62 / 75 LTE-FDD B12 @ dBm LTE-FDD B13 @ dBm LTE-FDD B18 @ dBm LTE-FDD B19 @ dBm LTE-FDD B20 @ dBm LTE-FDD B25 @ dBm LTE-FDD B26 @ dBm LTE-FDD B27 @ dBm LTE-FDD B28A @ dBm LTE-FDD B28B @ dBm LTE-FDD B66 @ dBm LTE-FDD B1 @ dBm LTE-FDD B2 @ dBm LTE-FDD B3 @ dBm LTE-FDD B4 @ dBm LTE-FDD B5 @ dBm LTE-FDD B8 @ dBm LTE-FDD B17 @ dBm LTE-FDD B18 @ dBm LTE-FDD B19 @ dBm LTE-FDD B20 @ dBm LTE-FDD B25 @ dBm LTE-FDD B28 @ dBm LTE Cat NB2 data transfer

(GNSS OFF) LTE-FDD B12 @ dBm LTE-FDD B13 @ dBm LPWA Module Series BG772A-GL Hardware Design TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA BG772A-GL_Hardware_Design 63 / 75 LPWA Module Series BG772A-GL Hardware Design LTE-FDD B66 @ dBm TBD TBD mA Table 36: GNSS Current Consumption (Power Supply: 3.3 V, Room Temperature) Description Conditions Searching

(AT+CFUN=0) Cold start @ Instrument Hot start @ Instrument Lost state @ Instrument Instrument environment @ Passive antenna Tracking

(AT+CFUN=0) Half sky @ Real network, Passive antenna Half sky @ Real network, Active antenna Typ. TBD TBD TBD TBD TBD TBD Unit mA mA mA mA mA mA Parameter Description Unit 6.5. Digital I/O Characteristic Table 37: 1.8 V I/O Requirements Input high voltage Input low voltage Output high voltage 1.36 Output low voltage 0 Table 38: (U)SIM 1.8 V I/O Requirements Parameter Description USIM_VDD Power supply Input high voltage Input low voltage Output high voltage Min. 1.2

-0.2 Min. 1.7 1.2

-0.2 1.36 VIH VIL VOH VOL VIH VIL VOH Max. 2.0 0.57 2.0 0.38 Max. 1.9 2.0 0.57 2.0 V V V V V V V V Unit BG772A-GL_Hardware_Design 64 / 75 VOL Output low voltage 0 0.38 V LPWA Module Series BG772A-GL Hardware Design 6.6. RF Output Power The following table shows the RF output power of BG772A-GL. Table 39: BG772A-GL RF Output Power Frequency Bands Max. RF Output Power Min. RF Output Power LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B171)/B18/B19

/B20/B25/B26 2)/B27 2) /B28/B66 23 dBm 2.7 dB

< -39 dBm NOTES 1. 2. 1) LTE-FDD B17 is supported by Cat NB2 only. 2) LTE-FDD B26 and B27 are supported by Cat M1 only. 6.7. RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of BG772A-GL. Table 40: BG772A-GL Conducted RF Receiving Sensitivity Network Frequency Band Primary Diversity LTE LTE-FDD B3 Supported TBD/-99.3 TBD/-107.5 Not Supported LTE-FDD B1 LTE-FDD B2 LTE-FDD B4 LTE-FDD B5 Receiving Sensitivity (dBm) Cat M1/3GPP Cat NB2 1)/3GPP TBD/-102.3 TBD/-107.5 TBD/-100.3 TBD/-107.5 TBD/-102.3 TBD/-107.5 TBD/-100.8 TBD/-107.5 BG772A-GL_Hardware_Design 65 / 75 LTE-FDD B8 LTE-FDD B12 LTE-FDD B13 LTE-FDD B17 2) LTE-FDD B18 LTE-FDD B19 LTE-FDD B20 LTE-FDD B25 LTE-FDD B26 3) LTE-FDD B27 3) LTE-FDD B28 LTE-FDD B66 LPWA Module Series BG772A-GL Hardware Design TBD/-99.8 TBD/-107.5 TBD/-99.3 TBD/-107.5 TBD/-99.3 TBD/-107.5 Not Supported TBD/-107.5 TBD/-102.3 TBD/-107.5 TBD/-102.3 TBD/-107.5 TBD/-99.8 TBD/-107.5 TBD/-100.3 TBD/-107.5 TBD/-100.3 Not Supported TBD/-100.8 Not Supported TBD/-100.8 TBD/-107.5 TBD/-101.8 TBD/-107.5 NOTES 1. 2. 3. 1) LTE Cat NB2 receiving sensitivity without repetitions. 2) LTE-FDD B17 is supported by Cat NB2 only. 3) LTE-FDD B26 and B27 are supported by Cat M1 only. BG772A-GL_Hardware_Design 66 / 75 LPWA Module Series BG772A-GL Hardware Design 6.8. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. The following table shows the electrostatic discharge characteristics of BG772A-GL module. Table 41: Electrostatic Discharge Characteristics (Temperature: 25 C, Relative Humidity: 45 %) Tested Interfaces Contact Discharge Air Discharge Unit VBAT, GND Main/GNSS Antenna Interfaces TBD TBD TBD TBD kV kV BG772A-GL_Hardware_Design 67 / 75 LPWA Module Series BG772A-GL Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of millimeter (mm), and the dimensional tolerances are 0.05 mm unless otherwise specified. the module. All dimensions are measured in 7.1. Top and Side Dimensions Pin 1 Figure 31: Module Top and Side Dimensions BG772A-GL_Hardware_Design 68 / 75 LPWA Module Series BG772A-GL Hardware Design Pin 1 Figure 32: Bottom Dimensions (Bottom View) NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard. BG772A-GL_Hardware_Design 69 / 75 7.2. Recommended Footprint LPWA Module Series BG772A-GL Hardware Design Figure 33: Recommended Footprint (Top View) NOTES 1. For easy maintenance of the module, keep a distance of about 3 mm between the module and other components on the motherboard. 2. All reserved pins must be kept open. 3. For stencil design requirements of the module, see document [6]. BG772A-GL_Hardware_Design 70 / 75 7.3. Top and Bottom Views LPWA Module Series BG772A-GL Hardware Design Figure 34: Top and Bottom View of the Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, refer to the module received from Quectel. BG772A-GL_Hardware_Design 71 / 75 LPWA Module Series BG772A-GL Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 5 C and the relative humidity should be 3560 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition. 3. The floor life of the module is 168 hours 1) in a plant where the temperature is 23 5 C and relative humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g. a drying cabinet). 4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under the following circumstances:

The module is not stored in Recommended Storage Condition;

Violation of the third requirement above occurs;

Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;

Before module repairing. 5. If needed, the pre-baking should follow the requirements below:

The module should be baked for 8 hours at 120 5 C;

All modules must be soldered to PCB within 24 hours after the baking, otherwise they should be put in a dry environment such as in a drying oven. BG772A-GL_Hardware_Design 72 / 75 LPWA Module Series BG772A-GL Hardware Design NOTES 1)This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 1. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. If the temperature and moisture do not conform to IPC/JEDEC J-STD-033 or the relative moisture is over 60 %, it is recommended to start the solder reflow process within 24 hours after the package is removed. And do not remove the packages of tremendous modules if they are not ready for soldering. 3. Take the module out of the packaging and put it on high-temperature resistant fixtures before the baking. If shorter baking time is desired, refer to IPC/JEDEC J-STD-033 for baking procedure. 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the for the module is recommended to be 0.100.12 mm. For more details, see thickness of stencil document [6]. It is suggested that the peak reflow temperature is 238246 C, and the absolute maximum reflow temperature is 246 C. To avoid damage to the module caused by repeated heating, it is strongly recommended that the module should be mounted after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. Figure 35: Recommended Reflow Soldering Thermal Profile BG772A-GL_Hardware_Design 73 / 75 Table 42: Recommended Thermal Profile Parameters LPWA Module Series BG772A-GL Hardware Design Soak time (between A and B: 150 C and 200 C) 70 to 120 s Recommendation 1 to 3 C/s 2 to 3 C/s 45 to 70 s 238 to 246 C

-1.5 to -3 C/s 1 Factor Soak Zone Max slope Reflow Zone Max slope Max temperature Cooling down slope Reflow Cycle Max reflow cycle NOTE Reflow time (D: over 220 C) 8.3. Packaging If a conformal coating is necessary for the module, do NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module. BG772A-GL is packaged in a vacuum-sealed bag which is ESD protected. The bag should not be opened until the devices are ready to be soldered onto the application. The following figures show the packaging details, measured in millimetre (mm). BG772A-GL_Hardware_Design 74 / 75 LPWA Module Series BG772A-GL Hardware Design Figure 36: Tape Dimensions Figure 37: Reel Dimensions Table 43: BG772A-GL Packaging Specifications MOQ for MP Minimum Package: 500 Minimum Package x 4 = 2000 500 Pieces Size: 370 mm 350 mm 56 mm N.W: TBD G.W: TBD Size: 380 mm 250 mm 365 mm N.W: TBD G.W: TBD BG772A-GL_Hardware_Design 75 / 75 LPWA Module Series BG772A-GL Hardware Design 9 Appendix A References Table 44: Related Documents SN Document Name Description

[1]

Quectel_BG772A-GL_GNSS_Application_Note BG772A-GL GNSS Application Note

[2]

Quectel_UMTS&LTE_EVB_User_Guide UMTS&LTE EVB User Guide

[3]

Quectel_BG772A-GL_QCFG_AT_Commands_Manual

[4]

Quectel_BG772A-GL_AT_Commands_Manual AT+QCFG Commands Manual for BG772A-GL Module AT Commands Manual of BG772A-GL Module

[5]

Quectel_RF_Layout_Application_Note RF Layout Application Note

[6]

Quectel_Module_Secondary_SMT_Application_Note Module Secondary SMT User Guide Table 45: Terms and Abbreviations Abbreviation Description ADC Balun bps CHAP CTS DFOTA DL DRX EGSM Analog to Digital Converter Balanced to Unbalanced Bits Per Second Challenge Handshake Authentication Protocol Clear to Send Delta Firmware Upgrade Over the Air Downlink Discontinuous Reception Extended GSM (Global System for Mobile Communications) BG772A-GL_Hardware_Design 76 / 75 e-I-DRX Extended Idle Mode Discontinuous Reception LPWA Module Series BG772A-GL Hardware Design EPC ESD FDD HSS I2C LNA LPF LTE MO MT PAP PCB PDU PPP PSM RF RTS SAW SMS UL UE URC

(U)SIM Password Authentication Protocol Evolved Packet Core Electrostatic Discharge Frequency Division Duplex Home Subscriber Server Inter-Integrated Circuit Low Noise Amplifier Low Pass Filter Long Term Evolution Mobile Originated Mobile Terminated Printed Circuit Board Protocol Data Unit Point-to-Point Protocol Power Saving Mode Radio Frequency Request to Send Surface Acoustic Wave Short Message Service Uplink User Equipment Unsolicited Result Code

(Universal) Subscriber Identity Module RHCP Right Hand Circularly Polarized BG772A-GL_Hardware_Design 77 / 75 LPWA Module Series BG772A-GL Hardware Design Vmax Vnom Vmin VIHmax VIHmin VILmax VSWR WWAN Maximum Voltage Value Nominal Voltage Value Minimum Voltage Value Maximum Input High Level Voltage Value Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Voltage Standing Wave Ratio Wireless Wide Area Network BG772A-GL_Hardware_Design 78 / 75

QUECTEL BG772A-GL AA Q1-AXxxx BG772AGLAA-N06-SGNSA FCC ID:XMR2022BG772AGL IC:10224A-2022BG772A SN:XXXXXXXXXXXXXXX IMEI: XXXXXXXXXXXXXXX Ce

~ eer me N-E1027KO24000020

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Quectel Wireless Solutions Co., Ltd Statement We Quectel Wireless Solutions Co., Ltd declare the following models. Product Name: LTE Module Model Number: BG770A-GL, BG772A-GL Hardware Version: R1.1 BG770A-GL and BG772A-GL both use ALT1250 chip, share the same chipset baseline, the same hardware and software design, and support the same frequency bands. based on 770, 772 is for different market purpose. Your assistance on this matter is highly appreciated. Sincerely, Name: Jean Hu Title: Certification Section

Quectel Wireless Solutions Co., Ltd Statement We Quectel Wireless Solutions Co., Ltd declare the following models. Product Name: LTE Cat M1 & Cat NB2 Module Model Number: BG772A-GL BG772A-GL supports from Cat NB1(3GPP R13) to Cat NB2(3GPP R14) only by FW updating, the hardware remains the same. The key information for the module is as below:

Module BB Chip Category BG772A-GL (Cat NB1) ALT1250 Cat M1 & NB1 BG772-GL (Cat NB2) ALT1250 Cat M1 & NB2 Frequency Bands Cat M1 LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B18/B19/B20/B25/B26

/B27/B28/B66 Cat M1 LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B18/B19/B20/B25/B26

/B27/B28/B66 Cat NB1 LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B17/B18/B19/B20/B25

/B28/B66 Cat NB2 LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B17/B18/B19/B20/B25

/B28/B66 GNSS QuecOpen GPS, GLONASS Yes GPS, GLONASS Yes Your assistance on this matter is highly appreciated. Sincerely, Name: Jean Hu Title: Certification Section Manager

Model Number:BG772A-GL FCC ID:XMR2022BG772AGL Certificate No. :222180245AA00 Date of issue:03/15/ 2022 BG772A-GL supports from Cat NB1(3GPPR13) to Cat NB2(3GPPR14) onlyby FW updating, the hardware remains the same. The report validation information is below:

NB report :

There is only verified RF Power Output, Band Edge Compliance and Spurious Emissions at Antenna Terminals, and did not worsen, so they were not recorded in the report. Powers of new variant are varied due to measurement uncertainty, and sample tolerance of the acceptance range. The detailed product change description please refers to the Difference Declaration Letter (Variant 2). LTE-M report:

There is only verified RF Power Output, Band Edge Compliance and Spurious Emissions at Antenna Terminals, and did not worsen, so they were not recorded in the report. Powers of new variant are varied due to measurement uncertainty, and sample tolerance of the acceptance range. The detailed product change description please refers to the Difference Declaration Letter (Variant 2).

Quectel Wireless Solutions Company Limited Declaration of the Modular Approval Applicant / Grantee FCC ID:

Model:

Quectel Wireless Solutions Company Limited XMR2022BG772AGL BG772A-GL The single module transmitter has been evaluated then tested meeting the requirements under Part 15C Section 212 as below:

Modular approval requirement EUT Condition

(a) The radio elements of the modular transmitter must have their own shielding. The physical crystal and tuning capacitors may be located external to the shielded radio elements. The radio elements of the modular transmitter have their own shielding. Com ply YES

(b) The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with part 15 requirements under conditions of excessive data rates or over-modulation. The modular has buffered data inputs, it is integrated in chip. Please see schematic.pdf YES

(c)The modular transmitter must have its own powersupply regulation. All power lines derived from the host device are regulated before energizing other circuits internal to the BG772A-GL. Please see schematic.pdf YES Quectel Wireless Solutions Company Limited

(d) The modular transmitter must comply with the antenna and transmission system requirements of Sections 15.203, 15.204(b) and 15.204(c). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of Section 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph (b) of this section.

(e)The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing for compliance with part 15 requirements. Unless the transmitter module will be battery powered, it must comply with the AC line conducted requirements found in Section 15.207. AC or DC power lines and data input/output lines connected to the module must not contain ferrites, unless they will be marketed with the module (see Section 15.27(a)). The length of these lines shall be the length typical of actual use or, if that length is unknown, at least 10 centimeters to insure that there is no coupling between the case of the module and supporting equipment. Any accessories, peripherals, or support equipment connected to the module during testing shall be unmodified and commercially available (see Section 15.31(i))mustnotbeinsideanotherdeviceduringtesting.

(f)The modular transmitter must be equipped with either a permanently affixed label or must be capable of electronically displaying its FCC identification number.

(g) The modular transmitter must comply with any specific rules or operating requirements that ordinarily apply to a complete transmitter and the manufacturer must provide adequate instructions along with the module to explain any suchrequirements. A copy of these instructions must be included in the application for equipmentauthorizationrequirements,whicharebasedonthei ntendeduse/configurations. A permanently attached antenna or unique antenna connector is not a requirement for licensed modules. YES The BG772A-GL was tested in a stand alone configuration via a PCMCIA extender. Please see spurious setup YES The label position of BG772A-GL is clearly indicated. If the FCC ID of the module cannot be seen when it is installed, then the host label must include the text:

Contains FCC ID: XMR202005BG95M5. Please see the label.pdf The BG772A-GL is compliant with all applicable FCC rules. Detail instructions are given in the User Manual. YES YES

(h)The modular transmitter must comply with any applicable RF exposure requirements in its final configuration. The BG772A-GL is approved to comply with the applicable RF exposure requirement, please see the MPE YES Quectel Wireless Solutions Company Limited evaluation with 20cm as the distance restriction. Dated By:

2023/07/18 Jean Hu Signature Printed Title: Project Manager

Quectel Wireless Solutions Company Limited POWER OF ATTORNEY DATE: July 18, 2023 To:

Federal Communications Commission, Authorization & Evaluation Division, 7435 Oakland Mills Road, Columbia, MD 21046 We, the undersigned, hereby authorize TA Technology (Shanghai) Co., Ltd.

/Jinnan Han on our behalf, to apply to FCC on our equipment for FCC ID:

XMR2022BG772AGL. Any and all acts carried out by TA Technology

(Shanghai) Co., Ltd. / Jinnan Han on our behalf shall have the same effect as acts of our own. Sincerely, Signature:

Print name: Jean Hu Company: Quectel Wireless Solutions Company Limited

Quectel Wireless Solutions Company Limited Request for Confidentiality Date: _2023/07/18 Subject: Confidentiality Request for: _____ FCC ID: XMR2022BG772AGL ______ Pursuant to FCC 47 CRF 0.457(d) and 0.459 and IC RSP-100, Section 10, the applicant requests that a part of the subject FCC application be held confidential. Type of Confidentiality Requested Permanent*1 Permanent*2 Permanent Short Term Short Term Short Term ______(Insert Explanation as Necessary)______ Exhibit External Photos Internal Photos Tune-Up Procedure

*Note:

______ FCC ID: XMR2022BG772AGL has spent substantial effort in developing this product and it is one of the first of its kind in industry. Having the subject information easily available to "competition" would negate the advantage they have achieved by developing this product. Not protecting the details of the design will result in financial hardship. Permanent Confidentiality:

The applicant requests the exhibits listed above as permanently confidential be permanently withheld from public review due to materials that contain trade secrets and proprietary information not customarily released to the public. Short-Term Confidentiality:

The applicant requests the exhibits selected above as short term confidential be withheld from public view for a period of ______ days from the date of the Grant of Equipment Authorization and prior to marketing. This is to avoid premature release of sensitive information prior to marketing or release of the product to the public. Applicant is also aware that they are responsible to notify TCB in the event information regarding the product or the product is made available to the public. TCB will then release the documents listed above for public disclosure pursuant to FCC Public Notice DA 04-1705. NOTE for Industry Canada Applications:

The applicant understands that until such time that IC distinguishes between Short Term and Permanent Confidentiality, either type of marked exhibit above will simply be marked Confidential when submitted to IC. Sincerely, By:

(Signature/Title3)

(Print name) Jean Hu

Quectel Wireless Solutions Co., Ltd To: Federal Communications Commission 7435 Oakland Mills Road Columbia, MD 21046 USA Date: 2023/07/18 Attestation Section 2.911(d)(5)(i) and Section 2.911(d)(5)(ii)

(KDB 986446 D01 Covered Equipment) Section 2.911(d)(5)(i) Quectel Wireless Solutions Co., Ltd(the applicant) certifies that the equipment for which authorization is sought is not covered equipment prohibited from receiving an equipment authorization pursuant to section 2.903 of the FCC rules. Section 2.911(d)(5)(ii) Quectel Wireless Solutions Co., Ltd(the applicant) certifies that, as of the date of the filing of the application, the applicant is not identified on the Covered List as an entity producing covered equipment. Type of Equipment subject to FCC Certification:

Fleet Management System FCC ID:XMR2022BG772AGL If you have any questions, please feel free to contact me Contact Person:

Position in the Company: Quectel Wireless Solutions Co., Ltd Date of Signature:

2023/07/18 Jean Hu ______________ Signatory

(signature of the applicant)

QIECCTEL Federal Communications Commission 7435 Oakland Mills Road Columbia MD 21046 Subject: Certification designating a U.S. agent for service of process pursuant to Part 2.911(d)(7) To whom it may concern, Quectel Wireless Solutions Company Limited, Grantee Code: XMR (the applicant) certifies that, as of the date of the filing of application, Ikotek USA, Inc., FRN: 0033350331 (the agent) is designated as the U.S. agent for the purpose of accepting service of process on behalf of the applicant. The physical U.S. address and email for the designated agent are:

Physical U.S. address: 9920 Pacific Heights Blvd., Ste. 150, #7025, San Diego, CA 92121 Email: compliance@ikotek.com The applicant accepts to maintain an agent for service of process in the United States for no less than one year after either the grantee has permanently terminated all marketing and importation of the applicable equipment within the U.S., or the conclusion of any Commission-related administrative or judicial proceeding involving the equipment, whichever is later. The agent accepts the designation by (the applicant) as the U.S. agent to accept service of process includes, but is not limited to, delivery of any correspondence, notices, orders, decisions, and requirements of administrative, legal, or judicial process related to Commission proceedings. Signed by the Applicant Signed by the Agent (if different from the Applicant) Name: Jean Hu C Name-dseph M. Peterson Title: Certification Manager Title: President and CEO Email: Jean.hu@quectel.com Email: joe.peterson@ikotek.com Date: 16 February 2023 Date: February 17%, 2023

Quectel Wireless Solutions Company Limited BG770A-GL original date of grant : 07/05/2021, Certificate number :212180712AA00 FCC IDXMR2021BG770AGL Name: LTE Module Parent Model: BG772A-GL Hardware Version:R1.1 The description of the modification is as follows All reports are updated as follows:

BG772A-GL (Report No.: R2112A1193-M1) is a variant model of BG770A-GL (Report No.:

R2104A0331-M1). Test values partial duplicated from Original for variant. There is no test for variant in this report. BG772A-GL (Report No.: R2112A1193-R1) is a variant model of BG770A-GL (Report No.:

R2104A0331-R1). Test values partial duplicated from Original for variant. There is no test for variant in this report. BG772A-GL (Report No.: R2112A1193-R2) is a variant model of BG770A-GL (Report No.:

R2104A0331-R2). Test values partial duplicated from Original for variant. There is only test RF Power Output, please refer to Appendix C for Verify data. BG772A-GL (Report No.: R2112A1193-R3) is a variant model of BG770A-GL (Report No.:

R2104A0331-R3). Test values partial duplicated from Original for variant. There is only test RF Power Output, please refer to Appendix C for Verify data. BG772A-GL (Report No.: R2112A1193-R4) is a variant model of BG770A-GL (Report No.:

R2104A0331-R4). Test values partial duplicated from Original for variant. There is only test RF Power Output, please refer to Appendix C for Verify data. BG772A-GL (Report No.: R2112A1193-R5) is a variant model of BG770A-GL (Report No.:

R2104A0331-R5). Test values partial duplicated from Original for variant. There is no test for variant in this report. BG772A-GL (Report No.: R2112A1193-R6) is a variant model of BG770A-GL (Report No.:

R2104A0331-R6). Test values partial duplicated from Original for variant. There is only test RF Power Output, please refer to Appendix C for Verify data. BG772A-GL (Report No.: R2112A1193-R7) is a variant model of BG770A-GL (Report No.:

R2104A0331-R7). Test values partial duplicated from Original for variant. There is only test R Radiates Spurious Emission (NB-IoT Band 13), please refer to Appendix C for Verify data. BG772A-GL (Report No.: R2112A1193-R8) is a variant model of BG770A-GL (Report No.:

R2104A0331-R8). Test values partial duplicated from Original for variant. There is only test RF Power Output, please refer to Appendix C for Verify data. Your assistance on this matter is highly appreciated. Signature:

Print name: Jean Hu Date: 03/04/2022 Company: Quectel Wireless Solutions Co., Ltd.