FCC ID: XMR2022BG952AGL LTE Cat M1 & Cat NB2 Module

BG952A-GL QuecOpen Hardware Design LPWA Module Series Version: 1.0.0 Date: 2022-04-30 Status: Preliminary www.quectel.com LPWA Module Series Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters:

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit:

http://www.quectel.com/support/sales.htm. For technical support, or to report documentation errors, please visit:

http://www.quectel.com/support/technical.htm Or email to support@quectel.com. General Notes Quectel offers the information as a service to its customers. The information provided is based upon customers requirements. Quectel makes every effort to ensure the quality of the information it makes available. Quectel does not make any warranty as to the information contained herein, and does not accept any liability for any injury, loss or damage of any kind incurred by use of or reliance upon the information. All information supplied herein is subject to change without prior notice. Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors, it is possible that these functions and features could contain errors, inaccuracies and omissions. Unless otherwise provided by valid agreement, Quectel makes no warranties of any kind, implied or express, with respect to the use of features and functions under development. To the maximum extent permitted by law, Quectel excludes all liability for any loss or damage suffered in connection with the use of the functions and features under development, regardless of whether such loss or damage may have been foreseeable. Duty of Confidentiality The Receiving Party shall keep confidential all documentation and information provided by Quectel, except when the specific permission has been granted by Quectel. The Receiving Party shall not access or use Quectels documentation and information for any purpose except as expressly provided herein. Furthermore, the Receiving Party shall not disclose any of the Quectel's documentation and information to any third party without the prior written consent by Quectel. For any noncompliance to the above requirements, unauthorized use, or other illegal or malicious use of the documentation and information, Quectel will reserve the right to take legal action. BG952A-GL_QuecOpen_Hardware_Design 1 / 72 LPWA Module Series Copyright The information contained here is proprietary technical information of Quectel. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design. Copyright Quectel Wireless Solutions Co., Ltd. 2022. All rights reserved. Hereby, [Quectel Wireless Solutions Co., Ltd.] declares that the radio equipment type [BG952A-GL] is in compliance with Directive 2014/53/EU. The full text of the EU declaration of conformity is available at the following internet address:

http://www.quectel.com The device could be used with a separation distance of 20cm to the human body. BG952A-GL_QuecOpen_Hardware_Design 2 / 72 LPWA Module Series Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be paid to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation interference with of wireless appliances in an aircraft communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft. is forbidden to prevent Wireless devices may cause interference on sensitive medical equipment, so the restrictions on the use of wireless devices when in please be aware of hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions, such as when the mobile bill is unpaid or the (U)SIM card is invalid. When emergency help is needed in such conditions, use emergency call if the device supports it. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. In an emergency, the device with emergency call function cannot be used as the only contact method considering network connection cannot be guaranteed under all circumstances. The cellular terminal or mobile contains a transceiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV sets, radios, computers or other electric equipment. In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or BG952A-GL_QuecOpen_Hardware_Design 3 / 72 LPWA Module Series metal powders. BG952A-GL_QuecOpen_Hardware_Design 4 / 72 LPWA Module Series About the Document Revision History Version Date Author Description

2022-04-30 Creation of the document 1.0.0 2022-04-30 Preliminary Arvin WU/

Ben JIANG Arvin WU/

Ben JIANG BG952A-GL_QuecOpen_Hardware_Design 5 / 72 LPWA Module Series Contents Safety Information ........................................................................................................................................ 3 About the Document .................................................................................................................................... 5 Contents .........................................................................................................................................................6 Table Index .................................................................................................................................................... 8 Figure Index .................................................................................................................................................10 1 2 Introduction ..........................................................................................................................................11 Special Mark ..............................................................................................................................11 1.1. Product Concept ................................................................................................................................. 12 General Description .................................................................................................................. 12 12 Key Features .............................................................................................................................13 Functional Diagram ...................................................................................................................15 Evaluation Board .......................................................................................................................16 2.1. 2.2. 2.3. 2.4. 3.5.1. 3.6. 3.7. 3.7.1. 3.7.2. 3.7.3. 3.1. 3.2. 3.3. 3.4. 3.5. 3 Application Interfaces .........................................................................................................................17 General Description .................................................................................................................. 17 Pin Assignment ......................................................................................................................... 18 Pin Description ..........................................................................................................................19 Pins Multiplexing ....................................................................................................................... 25 Operating Modes ...................................................................................................................... 25 Recovery Mode ............................................................................................................... 26 Power Saving Mode* ................................................................................................................ 27 Power Supply ............................................................................................................................28 Power Supply Pins .......................................................................................................... 28 DVoltage Stability Requirements .................................................................................... 28 Power Supply Monitoring ................................................................................................ 29 Turn on ...................................................................................................................................... 29 Turn on Module with PWRKEY .......................................................................................29 Turn off Module ............................................................................................................... 32 Turn off Module with PWRKEY .............................................................................32 Reset the Module ......................................................................................................................33 3.9. 3.10. PON_TRIG Interface ................................................................................................................ 35 3.11.

(U)SIM Interface ........................................................................................................................36 3.12. USB Interface* .......................................................................................................................... 38 3.13. UART Interfaces ........................................................................................................................39 3.14. I2C Interface* ............................................................................................................................ 41 3.15. SPI Interfaces* .......................................................................................................................... 42 3.16. ADC Interfaces* ........................................................................................................................ 42 3.17. Network Status Indication .........................................................................................................43 3.8.1. 3.8.2. 3.8.2.1. 3.8. BG952A-GL_QuecOpen_Hardware_Design 6 / 72 LPWA Module Series 3.18. STATUS .....................................................................................................................................44 3.19. GRFC Interfaces* ......................................................................................................................45 4 GNSS Receiver .................................................................................................................................... 46 General Description .................................................................................................................. 46 GNSS Performance .................................................................................................................. 46 Layout Guidelines ..................................................................................................................... 47 4.1. 4.2. 4.3. 5.2. 5.1. 5 Antenna Interfaces .............................................................................................................................. 48 Main Antenna Interface .............................................................................................................48 Pin Definition ................................................................................................................... 48 5.1.1. 5.1.2. Operating Frequency ...................................................................................................... 48 Reference Design ............................................................................................................49 5.1.3. GNSS Antenna Interface .......................................................................................................... 50 Pin Definition ................................................................................................................... 50 5.2.1. 5.2.2. GNSS Operating Frequency ........................................................................................... 50 Reference Design ............................................................................................................50 5.2.3. Reference Design of RF Layout ............................................................................................... 51 Antenna Installation .................................................................................................................. 53 Antenna Requirements ................................................................................................... 53 Recommended RF Connector for Antenna Installation ..................................................53 5.4.1. 5.4.2. 5.3. 5.4. 6 Reliability, Radio and Electrical Characteristics .............................................................................56 Absolute Maximum Ratings ......................................................................................................56 Power Supply Ratings .............................................................................................................. 56 Operating and Storage Temperatures ......................................................................................57 Power Consumption ................................................................................................................. 57 Tx Power ................................................................................................................................... 60 RF Receiving Sensitivity ........................................................................................................... 60 ESD ........................................................................................................................................... 61 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 7 Mechanical Dimensions ..................................................................................................................... 62 Mechanical Dimensions ............................................................................................................62 Recommended Footprint .......................................................................................................... 64 Top and Bottom Views .............................................................................................................. 65 7.1. 7.2. 7.3. 8 Storage, Manufacturing and Packaging ........................................................................................... 66 Storage ......................................................................................................................................66 8.1. Manufacturing and Soldering ....................................................................................................67 8.2. Packaging ................................................................................................................................. 68 8.3. Carrier Tape .....................................................................................................................68 Plastic Reel ......................................................................................................................69 Packing Process ..............................................................................................................70 8.3.1. 8.3.2. 8.3.3. 9 Appendix A References ......................................................................................................................71 BG952A-GL_QuecOpen_Hardware_Design 7 / 72 LPWA Module Series Table Index Table 1: Special Mark ...................................................................................................................................11 Table 2: Frequency Bands and GNSS Types of BG952A-GL QuecOpen ..................................................12 Table 3: Key Features of BG952A-GL QuecOpen ...................................................................................... 13 Table 4: Definition of I/O Parameters .......................................................................................................... 19 Table 5: Pin Description ............................................................................................................................... 20 Table 6: Overview of MAP Operating Modes .............................................................................................. 25 Table 7: Overview of MCU Operating Modes ..............................................................................................26 Table 8: Maximum Device Sleep Level of MAP-MCU Mode Combinations ...............................................27 Table 9: Power Supply Pin Definition .......................................................................................................... 28 Table 10: PWRKEY Pin Definition ............................................................................................................... 30 Table 11: Pin Definition of RESET_N .......................................................................................................... 33 Table 12: Pin Definition of PON_TRIG Interface .........................................................................................35 Table 13: Pin Definition of (U)SIM Interface ................................................................................................ 36 Table 14: Pin Definition of USB Interface .................................................................................................... 38 Table 15: Pin Definition of Main UART Interface .........................................................................................39 Table 16: Pin Definition of CLI UART Interface ........................................................................................... 40 Table 17: Pin Definition of ADC Interfaces .................................................................................................. 42 Table 18: Characteristics of ADC Interfaces ............................................................................................... 43 Table 19: Pin Definition of NET_STATUS ....................................................................................................43 Table 20: Operating Status of NET_STATUS ..............................................................................................44 Table 21: Pin Definition of STATUS ............................................................................................................. 44 Table 22: Pin Definition of GRFC Interfaces ............................................................................................... 45 Table 23: Truth Table of GRFC Interfaces ...................................................................................................45 Table 24: GNSS Performance ..................................................................................................................... 46 Table 25: Pin Definition of the Main Antenna Interface ...............................................................................48 Table 26: BG952A-GL QuecOpen Operating Frequency ........................................................................... 48 Table 27: Pin Definition of GNSS Antenna Interface ...................................................................................50 Table 28: GNSS Operating Frequency ........................................................................................................50 Table 29: Antenna Requirements ................................................................................................................ 53 Table 30: Absolute Maximum Ratings ......................................................................................................... 56 Table 31: Power Supply Ratings ..................................................................................................................56 Table 32: Operating and Storage Temperatures ......................................................................................... 57 Table 33: Power Consumption (Power Supply: 3.3 V, Room Temperature) ...............................................57 Table 34: GNSS Current Consumption of (3.3 V Power Supply, Room Temperature) .............................. 59 Table 35: Tx Power ...................................................................................................................................... 60 Table 36: Conducted RF Receiving Sensitivity of BG952A-GL QuecOpen ............................................... 60 Table 37: Electrostatic Discharge Characteristics (25 C, 45 % Relative Humidity) .................................. 61 Table 38: Recommended Thermal Profile Parameters ...............................................................................68 Table 39: Carrier Tape Dimension Table (Unit: mm) ................................................................................... 69 Table 40: Plastic Reel Dimension Table (Unit: mm) ....................................................................................69 Table 41: Related Documents ..................................................................................................................... 71 BG952A-GL_QuecOpen_Hardware_Design 8 / 72 Table 42: Terms and Abbreviations ............................................................................................................. 71 LPWA Module Series BG952A-GL_QuecOpen_Hardware_Design 9 / 72 LPWA Module Series Figure Index Figure 1: Functional Diagram of BG952A-GL ............................................................................................. 15 Figure 2: Pin Assignment (Top View) .......................................................................................................... 18 Figure 3: Power Supply Limits during Burst Transmission ......................................................................... 28 Figure 4: Star Structure of the Power Supply ............................................................................................. 29 Figure 5: Auto Power-on Circuit ...................................................................................................................30 Figure 6: Turn on the Module with a Driving Circuit ....................................................................................31 Figure 7: Turn on the Module with a Button ................................................................................................ 31 Figure 8: Power-up Timing ...........................................................................................................................32 Figure 9: Power-down Timing (PWRKEY) .................................................................................................. 33 Figure 10: Reference Circuit of RESET_N with a Driving Circuit ............................................................... 34 Figure 11: Reference Circuit of RESET_N with a Button ............................................................................34 Figure 12: Reset Timing ...............................................................................................................................34 Figure 13: Reference Circuit of PON_TRIG ................................................................................................35 Figure 14: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector ......................... 36 Figure 15: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector ............................37 Figure 16: Reference Design of USB Interface ...........................................................................................38 Figure 17: Main UART Reference Design (Translator Chip) ...................................................................... 40 Figure 18: Main UART Reference Design (Transistor Circuit) ....................................................................41 Figure 19: Reference Design of I2C Interface with an External I2C Interface Sensor .............................. 42 Figure 20: Reference Design of NET_STATUS .......................................................................................... 44 Figure 21: Reference Design of STATUS ....................................................................................................45 Figure 22: Reference Design of Main Antenna Interface ............................................................................49 Figure 23: Reference Design of GNSS Antenna Interface ......................................................................... 50 Figure 24: Microstrip Design on a 2-layer PCB ...........................................................................................51 Figure 25: Coplanar Waveguide Design on a 2-layer PCB ........................................................................ 51 Figure 26: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 52 Figure 27: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 52 Figure 28: Dimensions of the U.FL-R-SMT Connector (Unit: mm) .............................................................54 Figure 29: Mechanicals of U.FL-LP Connectors ......................................................................................... 54 Figure 30: Space Factor of Mated Connectors (Unit: mm) .........................................................................54 Figure 31: Module Top and Side Dimensions ............................................................................................. 62 Figure 32: Bottom Dimensions (Bottom View) ............................................................................................ 63 Figure 33: Recommended Footprint (Top View) ......................................................................................... 64 Figure 34: Top and Bottom Views ................................................................................................................65 Figure 35: Recommended Reflow Soldering Thermal Profile .................................................................... 67 Figure 36: Carrier Tape Dimension Drawing ............................................................................................... 69 Figure 37: Plastic Reel Dimension Drawing ................................................................................................69 Figure 38: Packaging Process .....................................................................................................................70 BG952A-GL_QuecOpen_Hardware_Design 10 / 72 LPWA Module Series 1 Introduction QuecOpen is an application solution where the module acts as a main processor. With the development of communication technology and the ever-changing market demands, more and more customers have realized the advantages of QuecOpen solution, especially the advantage in reducing product cost. With QuecOpen solution, development flow for wireless applications and hardware designs will be simplified. Main features of QuecOpen solution are listed below:

Simplify the development of embedded applications, and shorten the product development cycle Simplify circuit design, and reduce product cost Decrease the size of terminal products Reduce power consumption Support firmware update via DFOTA, and provide a mechanism for APP binary image update Improve cost-performance ratio of products, and enhance product competitiveness BG952A-GL QuecOpen is based on the processor core is ARM Cortex-M4, the maximum frequency is up to 80 MHz, and the RAM size is 128K byte. You can use this module as the basis for developing QuecOpen applications. This document, describing BG952A-GL QuecOpen module and its air interface and hardware interfaces connected to your applications, provides you with the interface specifications, electrical and mechanical details, as well as other related information of the module. With the application notes and user guides provided separately, you can easily use the module to design and set up mobile applications. 1.1. Special Mark Table 1: Special Mark Mark Definition

When an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin name, AT command, or argument is under development and currently not supported, unless otherwise specified. BG952A-GL_QuecOpen_Hardware_Design 11 / 72 LPWA Module Series 2 Product Concept 2.1. General Description As an embedded IoT (LTE Cat M1, LTE Cat NB2 and EGPRS) wireless communication module, it provides data connectivity on LTE-FDD and GPRS/EGPRS networks, and supports half-duplex operation in LTE network. It also provides GNSS function to meet your specific application demands. The module is based on an architecture in which WWAN (LTE) and GNSS Rx chains share certain hardware blocks. However, the module does not support concurrent operation of WWAN and GNSS. The solution adopted in the module is a form of coarse time-division multiplexing (TDM) between WWAN and GNSS Rx chains. Given the relaxed latency requirements of most LPWA applications, time-division sharing of resources can be made largely transparent to applications. For more details, see document

[1]. BG952A-GL QuecOpen is an industrial-grade module for industrial and commercial applications only. The following table shows the frequency bands of BG952A-GL QuecOpen module. Table 2: Frequency Bands and GNSS Types of BG952A-GL QuecOpen Supported Bands Supported Bands LTE Bands Power Class GNSS Cat M1:

LTE HD-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/B20/B25/

B26/B27/B28/B66 Cat NB1/NB2* 1:

LTE HD-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B17/B18/B19/B20/

B25/B28/B66 Power Class 3

(23 dBm 2.7 dB) GPS, GLONASS. BG952A-GL QuecOpen, an SMD type module, can be embedded into applications through its 102 LGA 1 LTE Cat NB2* is backward compatible with LTE Cat NB1. BG952A-GL_QuecOpen_Hardware_Design 12 / 72 LPWA Module Series pins. With a compact profile of 23.6 mm 19.9 mm 2.2 mm, it can meet almost all requirements for M2M applications such as security, smart metering, tracking system, and wireless POS. 2.2. Key Features Table 3: Key Features of BG952A-GL QuecOpen Features Details Power Supply Supply voltage: 2.24.35 1) V Typical supply voltage: 3.3 V Transmitting Power Class 3 (23 dBm 2.7 dB) for LTE HD-FDD bands Supports 3GPP Rel-13/Rel-14*

Supports LTE Cat M1, NB1/NB2*

Supports 1.4 MHz RF bandwidth for LTE Cat M1 Supports 200 kHz RF bandwidth for LTE Cat NB1/NB2*

Rel-13:

Cat M1: 300 kbps (DL)/375 kbps (UL) Cat NB1: 27.2 kbps (DL)/62.5 kbps (UL) Rel-14*:

Cat M1: 588 kbps (DL)/1119 kbps (UL) Cat NB2*: 127 kbps (DL)/158 kbps (UL) PPP/TCP/UDP/SSL/MQTT/FTP(S)/HTTP(S)/LwM2M/IPv4/IPv6/

TLS/DTLS/PING/CoAP/NITZ protocols Supports PAP and CHAP for PPP connections Text and PDU mode Point-to-point MO and MT SMS cell broadcast SMS storage: ME by default LTE Features Internet Protocol Features SMS

(U)SIM Interface Supports 1.8 V external (U)SIM/eSIM card only Compliant with USB 2.0 specifications Supports full speed mode only Used for AT command communication, data transmission, software USB Interface debugging and firmware upgrade*

UART Interfaces Main UART:

Used to connect with external peripherals of the module for customer USB serial driver:

- Windows 7/8/8.1/10 Linux 2.65.15 configuration. BG952A-GL_QuecOpen_Hardware_Design 13 / 72 LPWA Module Series 115200 bps baud rate by default The default frame format bit)115200 bps baud rate by default is 8N1 (8 data bits, no parity, 1 stop CLI UART 2:

Used for firmware upgrade, software debugging, log output, GNSS data and NMEA sentence output Supports RTS and CTS hardware flow control Default frame format: 8N1 (8 data bits, no parity, 1 stop bit) Supports RTS and CTS hardware flow control Supports 3 SPI interfaces, 2 SPI master and 1 SPI slave, which can be multiplexed from GPIOs. SPI Interfaces MCU SPIM0:

Supports master mode only Up to 25 MHz MCU SPIM1:

Supports master mode only Up to 25 MHz MCU SPIS:

Supports slave mode only Up to 25 MHz I2C Interface Supports 2 channels of MCU I2C interfaces GNSS GPS, GLONASS AT Commands 3GPP TS 27.007 and 3GPP TS 27.005 AT commands Quectel enhanced AT commands Network Indication One NET_STATUS pin for network connectivity status indication Antenna Interfaces Physical Characteristics Temperature Range Firmware Upgrade Main antenna interface (ANT_MAIN) GNSS antenna interface (ANT_GNSS) Dimensions: (23.6 0.2) mm (19.9 0.2) mm (2.2 0.2) mm Weight: approx. 2.15 g Operating temperature range: -35 C to +75 C 2) Extended temperature range: -40 C to +85 C 3) Storage temperature range: -40 C to +90 C CLI UART interface USB interface*

DFOTA RoHS All hardware components are fully compliant with EU RoHS directive NOTES 2 BG952A-GL supports two CLI UART interfaces, more precisely, pin 27 (CLI_TXD1) and pin 28 (CLI_RXD1) are connected to pin 95 (CLI_TXD2) and pin 94 (CLI_RXD2) respectively inside the module. BG952A-GL_QuecOpen_Hardware_Design 14 / 72 LPWA Module Series 1. 2. 3. 1) When the module starts up normally, to ensure full functionality, the minimum supply voltage should be higher than 2.2 V. For every VBAT transition/re-insertion from 0 V, VBAT slew rate < 25 mV/s. To ensure normal module startup, pulling down PWRKEY to turn on the module after VBAT remains stable for 100 ms. 2) Within the operating temperature range, the module meets 3GPP specifications. 3) Within the extended temperature range, the module remains the ability to establish and maintain functions such as SMS and data transmission, without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may exceed the specified tolerances of 3GPP. When the temperature returns to the operating temperature range, the module meets 3GPP specifications again. The following figures show the block diagram of the modules and illustrates the major functional parts. 2.3. Functional Diagram Power management Baseband Radio frequency Peripheral interfaces Figure 1: Functional Diagram of BG952A-GL BG952A-GL_QuecOpen_Hardware_Design 15 / 72 LPWA Module Series 2.4. Evaluation Board To facilitate application design with the module conveniently, Quectel supplies the evaluation board (LTE OPEN EVB), a USB to RS-232 converter cable, a micro-USB cable, an earphone, antennas and other peripherals to control or test the module. For more details, see document [2]. BG952A-GL_QuecOpen_Hardware_Design 16 / 72 LPWA Module Series BG952A-GL QuecOpen is equipped with 102 LGA pins. The subsequent chapters provide detailed descriptions of the following interfaces:

3 Application Interfaces 3.1. General Description Power supply PON_TRIG interface

(U)SIM interface USB interface UART interfaces PCM and I2C interfaces*

SPI interfaces*

ADC interfaces*

Status indication interfaces GRFC interfaces BG952A-GL_QuecOpen_Hardware_Design 17 / 72 LPWA Module Series 3.2. Pin Assignment The following figure shows the pin assignment of the module. Figure 2: Pin Assignment (Top View) BG952A-GL_QuecOpen_Hardware_Design 18 / 72 LPWA Module Series NOTES 1. ADC input voltage must not exceed 1.8 V. 2. Keep all RESERVED pins and unused pins unconnected. 3. GND pins should be connected to ground in the design. 4. On BG952A-GL, pin 27 (CLI_TXD1) and pin 28 (CLI_RXD1) are connected to pin 95 (CLI_TXD2) and pin 94 (CLI_RXD2) respectively inside the module. 5. The LNA is integrated inside the module. It is not recommended to use an external LNA. It is strongly recommended to keep GNSS_LNA_EN (pin 51) and VDD_RF (pin 99) unconnected. The following tables show the pin definition, alternate functions and GPIO pull up/down resistance of the module. 3.3. Pin Description Table 4: Definition of I/O Parameters Type AI AO AIO DI DO DIO PI PO PD PU Description Analog Input Analog Output Analog Input/Output Digital Input Digital Output Digital Input/Output Power Input Power Output Pull down Pull up BG952A-GL_QuecOpen_Hardware_Design 19 / 72 LPWA Module Series Table 5: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment VBAT_BB 32 VBAT_RF 33 PI PI Power supply for the modules baseband part Power supply for the modules RF part Vmax = 4.35 V Vmin = 2.2 V Vnom = 3.3 V VDD_EXT 29 PO Provide 1.8 V for external circuits Vnom = 1.8 V IOmax = 50 mA See NOTE 1. See NOTE 1 Power supply for external GPIOs pull-up circuits. If unused, keep these pins open. GND 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 6774, 7982, 8991, 100102 Turn on/off Pin Name Pin No. I/O Description DC Characteristics Comment PWRKEY RESET_N 15 17 DI DI Turn on/off the module Reset the module VILmax = 0.3 V VIHmin = 1.0 V VILmax = 0.3 V VIHmin = 1.3 V Internally pulled up with a 470 k resistor. Status Indication Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment PSM_IND 1 DO STATUS 20 DO NET_ STATUS 21 DO PON_TRIG Interface Indicate the modules power saving mode Indicate the module's operation status Indicate the module's network activity status VOLmax = 0.36 V VOHmin = 1.44 V 1.8 V power domain. If unused, keep these pins open. Can be configured as GPIOs. 1.8 V power domain. If unused, keep these pins open. Pin Name Pin No. I/O Description DC Characteristics Comment BG952A-GL_QuecOpen_Hardware_Design 20 / 72 LPWA Module Series PON_TRIG*

96 DI USB Interface*

Used to wake up the MCU in low power mode VILmin = -0.2 V VILmax = 0.3 V VIHmin = 1 V VIHmax = 1.98 V 1.8 V power domain. If unused, keep these pins open. Pin Name Pin No. I/O Description DC Characteristics Comment Vnom = 5.0 V Typical 5.0 V USB_VBUS USB_DP 8 9 AI AIO USB_DM 10 AIO USB connection detect USB differential data (+) USB differential data (-)

(U)SIM Interface Pin Name Pin No. I/O Description DC Characteristics Comment USIM_DET 42 DI

(U)SIM card hot-plug detect USIM_VDD 43 PO

(U)SIM card power supply Vmax = 1.9 V Vmin = 1.7 V USIM_RST 44 DO

(U)SIM card reset Compliant with USB 2.0 standard specification. Require differential impedance of 90 . 1.8 V power domain. If unused, keep these pins open. Only 1.8 V (U)SIM card is supported. 1.8 V power domain. Vmax = 4.1 V Vmin = -0.2 V VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V VOLmax = 0.36 V VOHmin = 1.44 V VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V VOLmax = 0.36 V VOHmin = 1.44 V VOLmax = 0.36 V VOHmin = 1.44 V USIM_DATA 45 DIO

(U)SIM card data USIM_CLK 46 DO

(U)SIM card clock USIM_GND 47 Main UART Interface Specified ground for (U)SIM card Pin Name Pin No. I/O Description DC Characteristics Comment MAIN_DTR 30 MAIN_RXD 34 DI DI Main UART data terminal ready Main UART receive VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep these pins open. BG952A-GL_QuecOpen_Hardware_Design 21 / 72 LPWA Module Series Can be configured as GPIOs. 1.8 V power domain. It is recommended to reserve one set of test points. MAIN_TXD 35 DO MAIN_CTS 36 DO MAIN_RTS 37 DI MAIN_DCD 38 MAIN_RI 39 DO DO CLI UART Interfaces Main UART transmit DTE clear to send signal from DCE

(Connect to DTEs CTS) DTE request to send signal from DCE (Connect to DTEs RTS) Main UART data carrier detect Main UART ring indication CLI_RXD2 94 DI CLI_TXD2 94 CLI_TXD1 27 DO DO CLI_RXD1 28 DI Debug UART Interfaces CLI UART2 receive CLI UART2 transmit CLI UART1 transmit CLI UART1 receive VOLmax = 0.36 V VOHmin = 1.44 V VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V VOLmax = 0.36 V VOHmin = 1.44 V VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V VOLmax = 0.36 V VOHmin = 1.44 V VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V Pin Name Pin No. I/O Description DC Characteristics Comment Pin Name Pin No. I/O Description DC Characteristics Comment DBG_RXD 22 DI DBG_TXD 23 DO ADC Interfaces Debug UART receive Debug UART transmit VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V VOLmax = 0.36 V VOHmin = 1.44 V 1.8 V power domain. If unused, keep these pins open. Can be configured as GPIOs. Pin Name Pin No. I/O Description DC Characteristics Comment BG952A-GL_QuecOpen_Hardware_Design 22 / 72 LPWA Module Series ADC1 ADC0 2 24 Other Interfaces AI AI General-purpose ADC interface General-purpose ADC interface Voltage range:

0.11.8 V Voltage range:

0.11.8 V If unused, keep these pins open. Can be configured as GPIOs. Pin Name Pin No. I/O Description DC Characteristics Comment W_DISABLE

18 DI Airplane mode control VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V AP_READY*

19 DI Application processor ready Antenna Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment ANT_MAIN 60 AIO ANT_GNSS 49 AI External GNSS LNA Interface 3 Main antenna interface GNSS antenna interface

Pin Name Pin No. I/O Description DC Characteristics Comment GNSS_LNA_ EN 51 DO External GNSS LNA enable VOLmax = 0.38 V VOHmin = 1.36 V VDD_RF 99 PO 3 The LNA is integrated inside the module. It is not recommended to use an external LNA. It is strongly recommended to Can be used for external GNSS Vnom = 1.9 V IOmax = 50 mA keep GNSS_LNA_EN (pin 51) and VDD_RF (pin 99) unconnected. BG952A-GL_QuecOpen_Hardware_Design 23 / 72 1.8 V power domain. Pulled up by default. When this pin is at low level, the module enters airplane mode. If this pin is unused, keep it open. Can be configured as GPIOs. 1.8 V power domain. If this pin is unused, keep it open. Can be configured as GPIOs. 50 impedance. 50 impedance. If unused, keep this pin unconnected. 1.8 V power domain. If unused, keep this pin open. If unused, keep this pin open. LPWA Module Series LNA power supply RESERVED Pins GPIO Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment RESERVED 1114, 16, 52,53, 56,57, 63, 7578, 92,93,97,98 Keep these pins open. Pin Name Pin No. I/O Description DC Characteristics Comment General-purpose input/output VOLmax = 0.36 V VOHmin = 1.44 V VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep these pins open. GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GRFC1 GRFC2 4 5 6 7 25 26 40 41 64 65 66 85 86 87 88 83 84 DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DO DO GRFC Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment Generic RF controller VOLmax = 0.38 V VOHmin = 1.36 V 1.8 V power domain. If unused, keep this pin unconnected. BG952A-GL_QuecOpen_Hardware_Design 24 / 72 LPWA Module Series NOTES 1. 1) When the module starts up normally, to ensure full functionality, the minimum supply voltage should be higher than 2.2 V. For every VBAT transition/re-insertion from 0 V, VBAT slew rate < 25 mV/s. To ensure normal module startup, pulling down PWRKEY to turn on the module after VBAT remains stable for 100 ms. 2. On BG950A-GL/BG951A-GL, PWRKEY is pulled up to an internal voltage of the baseband chipset inside the module, and the minimum high-level output voltage is 1.0 V. 3. Keep all RESERVED pins and unused pins unconnected. 4. Connect GND to ground in the design. 3.4. Pins Multiplexing See document [7] for details about pin multiplexing of the module. 3.5. Operating Modes The operating mode of the module is combined with internal Modem Application Processor (MAP) mode and MCU mode. Table 6: Overview of MAP Operating Modes Mode Details Normal Operation Connected The module remains registered on the network and is ready to send and receive data. In this mode, the software is active. Idle The module is connected to the network. Its current consumption varies with the network setting and data transfer rate. Extended Idle Mode DRX

(e-I-DRX) The module and the network may negotiate over non-access stratum signaling the use of e-I-DRX for reducing power consumption, while being available for mobile terminating data and/or network originated procedures within a certain delay dependent on the DRX cycle value. Airplane Mode In this mode where the RF function is invalid. Minimum Functionality Mode In this mode, both RF function and (U)SIM card are invalid. BG952A-GL_QuecOpen_Hardware_Design 25 / 72 LPWA Module Series Sleep Mode Power OFF Mode The module remains the ability to receive paging message, SMS and TCP/UDP data from the network normally. In this mode, the current consumption is reduced to a low level. The modules power supply is shut down by its power management unit. In this mode, the software is inactive, the serial interfaces are inaccessible, while the operating voltage (connected to VBAT_RF and VBAT_BB) remains applied. Power Saving Mode

(PSM) PSM is similar to power-off, but the module remains registered on the network and there is no need to re-attach or re-establish PDN connections. The current consumption is reduced to a minimized level. Recovery Mode The module can burn firmware with an empty serial flash, or recover from firmware malfunction. For more details, see Chapter 3.5.1. NOTE In e-I-DRX mode, it is recommended to use the main UART interface for data communication, as the use of USB interface will increase power consumption. Table 7: Overview of MCU Operating Modes Mode Details Normal Run MCU performs user tasks. Stop Standby Shutdown Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. The standby mode can achieve the lowest power consumption with some data retention

(up to 128 KB). and I/Os are latched. The shutdown mode can achieve the lowest power consumption. The internal regulator is switched off. The RTC can remain active. SRAM, registers and retention data are lost, except for registers in the RTC domain. 3.5.1. Recovery Mode BG952A-GL QuecOpen provides the recovery mode for firmware upgrade in emergency cases. Recovery mode can force the module to boot via CLI UART interface for firmware upgrade. The following preconditions can set the module into recovery mode. 1. Short-circuit CLI_TXD2 and CLI_RXD2 pins. 2. Drive PWRKEY low to turn on the module. In this case the module will enter recovery mode. 3. After the module enters recovery mode successfully, disconnect the connection between CLI_TXD2 and CLI_RXD2. BG952A-GL_QuecOpen_Hardware_Design 26 / 72 LPWA Module Series 4. Upgrade firmware via CLI UART interface. NOTE 1. In recovery mode, pin 25 functions as CLI_RTS and pin 26 functions as CLI_CTS, while in other modes they are GPIO pins. 2. Since the baud rate of the serial port required to download firmware to the baseband chip is 3 Mbps, the flow control pins of the CLI serial port need to be reserved. Otherwise, you can only download with a 921600 baud rate, which is very slow. It is recommended to reserve the test points of the CLI UART interface, including pin 25, pin 26, pin 94 and pin 95, and keep pin 94 close to pin 95. 3. Ensure that VBAT remains stable for at least 100 ms before pulling down PWRKEY. 3.6. Power Saving Mode*

With different power modes configured in MAP and MCU, power management processor (PMP) selects the proper system modes accordingly. The table below shows the maximum device sleep level per different MAP-MCU power mode combinations. Table 8: Maximum Device Sleep Level of MAP-MCU Mode Combinations

MCU Nomal Stop Standby Shutdown Normal MCU active MAP normal MAP sleep MAP sleep MAP Sleep MCU active MAP normal MAP sleep MAP sleep PSM MCU active MAP normal MAP sleep MAP PSM BG952A-GL_QuecOpen_Hardware_Design 27 / 72 LPWA Module Series 3.7. Power Supply 3.7.1. Power Supply Pins The module provides two VBAT pins for connection with an external power supply. The following table shows the details of VBAT_BB and VBAT_RF pins and ground pins. Table 9: Power Supply Pin Definition Pin Name Pin No. Description Min. Typ. Max. Unit VBAT_BB 32 Power supply for the modules baseband part 2.2 3.3 4.35 VBAT_RF 33 Power supply for the modules RF part 2.2 3.3 4.35 GND 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 6774, 7982, 8991, 100102

V V

NOTE For every VBAT transition/re-insertion from 0 V, VBAT slew rate < 25 mV/s. After the module starts up normally, in order to ensure full functionality, the minimum supply voltage should be higher than 2.2 V. 3.7.2. Voltage Stability Requirements The power supply range of the module is from 2.2 V to 4.35 V. Make sure that the input voltage never drops below 2.2 V. Figure 3: Power Supply Limits during Burst Transmission To decrease voltage drop, a bypass capacitor of about 100 F with low ESR should be used, and a multi-layer ceramic chip capacitor (MLCC) array should also be reserved due to its low ESR. It is BG952A-GL_QuecOpen_Hardware_Design 28 / 72 LPWA Module Series recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC array, and place these capacitors close to VBAT pins. The main power supply from an external application has to be a single voltage source and can be expanded to two sub paths with star structure. The width of VBAT_BB trace should be no less than 0.6 mm, and the width of VBAT_RF trace should be no less than 2 mm. In principle, the longer the VBAT trace is, the wider it should be. In addition, to get a stable power source, it is suggested to use two TVSs with low leakage current and suitable reverse stand-off voltage, and also it is recommended to place them as close to the VBAT pins as possible. The following figure shows the star structure of the power supply. Figure 4: Star Structure of the Power Supply Power design for a module is critical to its performance. The power supply of the module should be able to provide a sufficient current of at least 0.8 A, so it is recommended to select a DC-DC converter chip or an LDO chip with ultra-low leakage current and current output of at least 1.0 A for the power supply design. 3.7.3. Power Supply Monitoring AT+CBC can be used to monitor the VBAT_BB voltage value. For more details, see document [3]. 3.8. Turn on 3.8.1. Turn on Module with PWRKEY The following table shows the pin definition of PWRKEY. BG952A-GL_QuecOpen_Hardware_Design 29 / 72 LPWA Module Series Table 10: PWRKEY Pin Definition Pin Name Pin No. I/O Description Comment PWRKEY 15 DI on/off the Turn module Internally pulled up with a 470 k resistor. When the module is in power-off mode, it can be turned on by driving PWRKEY low for 5001000 ms. It is recommended to use an auto power-on circuit to control PWRKEY, as shown below. Figure 5: Auto Power-on Circuit Visit https://www.torexsemi.com for more information on the XC6119 voltage detector. NOTE With the above circuit, the module automatically powers on when the power supply is switched on, and keeps PWRKEY at a high level after successful power-on. With this design, if you intend to power on the module again after you power it off with an API or AT command, switch off the power supply of the module and remain in switch-off state for at least 200 ms before you switch on the power supply to enable automatic power-on of the module. If the device has an extra MCU, it is recommended to use an open drain/collector driver to control the PWRKEY. A simple reference circuit is illustrated in the following figure. BG952A-GL_QuecOpen_Hardware_Design 30 / 72 LPWA Module Series Figure 6: Turn on the Module with a Driving Circuit Another way to control the PWRKEY is using a button directly. When pressing the button, electrostatic strike may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the button for ESD protection. A reference circuit is shown in the following figure. Figure 7: Turn on the Module with a Button The power-up scenario is illustrated in the following figure. BG952A-GL_QuecOpen_Hardware_Design 31 / 72 LPWA Module Series Figure 8: Power-up Timing Ensure that VBAT is stable before pulling down PWRKEY and keep the interval no less than 100 ms. NOTES 3.8.2. Turn off Module After the module is turned off or enters PSM, do not pull up any I/O pin of the module. Otherwise, the module will have additional power consumption and may have damaged pins. 3.8.2.1. Turn off Module with PWRKEY When the module is powered on, drive PWRKEY low for 6501500 ms before you release it, and then module will execute power-down procedure. The power-down timing is illustrated in the following figure. BG952A-GL_QuecOpen_Hardware_Design 32 / 72 LPWA Module Series Figure 9: Power-down Timing (PWRKEY) 3.9. Reset the Module The module can be reset by driving RESET_N low for at least 100 ms and then releasing it. The RESET_N signal is sensitive to interference, so it is recommended to route the trace as short as possible and surround it with ground. Table 11: Pin Definition of RESET_N Pin Name Pin No. I/O Description RESET_N 45 DI Reset the module. Internally pulled up with a 470 k resistor. The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button can be used to control RESET_N. BG952A-GL_QuecOpen_Hardware_Design 33 / 72 LPWA Module Series Figure 10: Reference Circuit of RESET_N with a Driving Circuit Another way to control the RESET_N is by using a button directly. Figure 11: Reference Circuit of RESET_N with a Button The reset scenario is illustrated in the following figure. Figure 12: Reset Timing BG952A-GL_QuecOpen_Hardware_Design 34 / 72 LPWA Module Series NOTE Make sure that there is no large capacitance on RESET_N. 3.10. PON_TRIG Interface BG952A-GL QuecOpen provides one PON_TRIG pin. Drive PON_TRIG is used to wake up the internal MCU. PON_TRIG is not pulled up/down internally by default. Table 12: Pin Definition of PON_TRIG Interface Pin Name Pin No. I/O Description Comment PON_TRIG 96 DI Used to wake up the MCU in low power mode 1.8 V power domain. Pulled down by default. PON_TRIG is used to wake up the internal MCU. If the low power consumption mode of the MCU is not required, it is strongly recommended to reserve a PON_TRIG test point. A reference design is shown in the following figure. Figure 13: Reference Circuit of PON_TRIG NOTE VDD_1V8 is powered by an external LDO. BG952A-GL_QuecOpen_Hardware_Design 35 / 72 LPWA Module Series 3.11.

(U)SIM Interface The module supports 1.8 V (U)SIM card only. The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Table 13: Pin Definition of (U)SIM Interface Pin No. I/O DI Pin Name Description Comment USIM_DET 42

(U)SIM card hot-plug detect 1.8 V power domain. USIM_VDD 43 PO

(U)SIM card power supply Only 1.8 V (U)SIM card is supported. USIM_RST 44 DO

(U)SIM card reset 1.8 V power domain. USIM_DATA 45 DIO

(U)SIM card data 1.8 V power domain. USIM_CLK 46 DO

(U)SIM card clock 1.8 V power domain. USIM_GND 47 Specified ground for (U)SIM card The module supports (U)SIM card hot-plug via USIM_DET, and both high and low level detections are supported. The function is disabled by default, and see AT+QSIMDET in document [3] for more details. The following figure shows a reference design of (U)SIM interface with an 8-pin (U)SIM card connector. Figure 14: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector BG952A-GL_QuecOpen_Hardware_Design 36 / 72 LPWA Module Series If (U)SIM card detection function is not needed, keep USIM_DET unconnected. A reference circuit for

(U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure. Figure 15: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector To enhance the reliability and availability of the (U)SIM card in applications, follow the criteria below in

(U)SIM circuit design:

Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace length less than 200 mm. Keep (U)SIM card signals away from RF and VBAT traces. Assure the ground trace between the module and the (U)SIM card connector short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5 mm to maintain the same electric potential. Make sure the bypass capacitor between USIM_VDD and USIM_GND is less than 1 F, and place it as close to (U)SIM card connector as possible. If the system ground plane is complete, USIM_GND can be connected to the system ground directly. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with surrounded ground. USIM_RST should also be surrounded with ground. To offer good ESD protection, it is recommended to add a TVS diode array with parasitic capacitance not exceeding 15 pF. to facilitate debugging, it is recommended to reserve series resistors for the

(U)SIM signals of the module. The 33 pF capacitors are used for filtering interference of EGSM900. Note that the (U)SIM peripheral circuit should be close to the (U)SIM card connector. The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace and sensitive occasion are applied, and should be placed close to the (U)SIM card connector. BG952A-GL_QuecOpen_Hardware_Design 37 / 72 LPWA Module Series 3.12. USB Interface*

BG952A-GL QuecOpen provides one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0 specification and supports full speed mode only. The following table shows the pin definition of USB interface. Table 14: Pin Definition of USB Interface Pin Name Pin No. I/O Description Comment USB_VBUS AI USB connection detect Typical 5.0 V 8 9 USB_DP AIO USB differential data (+) USB_DM 10 AIO USB differential data (-) Require differential impedance of 90 For more details about USB 2.0 specification, visit http://www.usb.org/home. It is recommended to reserve test points for debugging and firmware upgrading* in your designs. Figure 16: Reference Design of USB Interface To ensure USB data signal integrity, if possible, reserve a 0 resistor on USB_DP and USB_DM traces, respectively. Resistors R1 and R2 should be placed close to the module and to each other. The extra trace stubs must be as short as possible. To meet USB 2.0 specification, comply with the following principles while designing the USB interface. It is important to route the USB signal traces as differential pairs with ground surrounded. The impedance of USB differential trace is 90 . BG952A-GL_QuecOpen_Hardware_Design 38 / 72 LPWA Module Series Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is important to route the USB differential traces in inner-layer of the PCB, and surround the traces with ground on that layer and with ground planes above and below. Junction capacitance of the ESD protection device might cause influences on USB data lines, so pay attention to the selection of the device. Typically, the stray capacitance should be less than 2 pF. Keep the ESD protection devices as close to the USB connector as possible. 1. After the module is turned off or enters PSM, do not pull up any USB interface pin lest it cause additional power consumption and potentially damage pins on the module. 2. When using the UMTS&LTE EVB board to test the USB interface function of the module, please refer NOTE to document [8]. 3.13. UART Interfaces The module provides two UART interfaces: main UART and CLI UART interfacethe. The following are the features of the UART interfaces. The main UART interface is used to communicate with peripherals, which can be multiplexed as GPIOs. The CLI UART interface supports 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 and 3000000 bps baud rates, and the default is 115200 bps. It is used for firmware upgrade, software debugging, log and GNSS NMEA sentences output, and supports RTS and CTS hardware flow control. The default frame format is 8N1 (8 data bits, no parity, 1 stop bit). The GPIO pins configuration is determined by compilation time and it cannot be changed dynamically. The following tables show the pin definition of the four UART interfaces. Table 15: Pin Definition of Main UART Interface Pin Name Pin No. I/O Description Comment MAIN_DTR MAIN_RXD MAIN_TXD MAIN_CTS MAIN_RTS MAIN_DCD 30 34 35 36 37 38 DI DI DO DO DI DO Main UART data terminal ready Main UART receive Main UART transmit Main UART clear to send Main UART request to send Main UART data carrier detect 1.8 V power domain. If these pins are unused, keep them open. Can be configured as GPIOs. BG952A-GL_QuecOpen_Hardware_Design 39 / 72 LPWA Module Series MAIN_RI*

39 DO Main UART ring indication Table 16: Pin Definition of CLI UART Interface Pin Name Pin No. I/O Description Comment CLI_TXD2 CLI_RXD2 CLI_TXD1 CLI_RXD1 95 94 27 28 DO CLI UART2 transmission DI CLI UART2 reception DO CLI UART1 transmission DI CLI UART1 reception 1.8 V power domain. If unused, keep them open. 1.8 V power domain. If unused, keep them open. The module provides 1.8 V UART interfaces. A voltage-level translator should be used if your application is equipped with a 3.3 V UART interface. It is recommended to use a level conversion chip without internal pull-up. The voltage-level translator TXB0108PWR provided by Texas Instruments is recommended. The following figure shows a reference design of the main UART interface:

Figure 17: Main UART Reference Design (Translator Chip) Visit http://www.ti.com for more information on the translator chip. Another example with transistor circuit is shown as below. For the design of circuits in dotted lines, refer to that of circuits in solid lines, but pay attention to the direction of connection. BG952A-GL_QuecOpen_Hardware_Design 40 / 72 LPWA Module Series Figure 18: Main UART Reference Design (Transistor Circuit) NOTE 1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps. 2. The UART interface should be disconnected in PSM and power off modes. Otherwise, the module 3. will have additional power consumption and may have damaged pins. It is recommended to use a level-shifting chip without internal pull-up, such as TXB0108PWR, for voltage level translation. 3.14. I2C Interface*

The module provides two Inter-Integrated Circuit (I2C) interface for data communication. The interface supports fast-mode plus and master mode only. The pins of I2C interface are open drain and are multiplexed from GPIOs. The pull-up resistors should be provided externally. NOTES The pins of I2C interface are open drain that must be pulled up to 1.8 V. The pull-up resistors should be provided externally. The following figure shows a reference design of I2C interface with an external I2C interface sensor. BG952A-GL_QuecOpen_Hardware_Design 41 / 72 LPWA Module Series Figure 19: Reference Design of I2C Interface with an External I2C Interface Sensor 3.15. SPI Interfaces*

The module provides three SPI interfaces. 2 SPI interfaces for master mode, 1 SPI interface for slave mode. The SPI interfaces function is multiplexed from GPIOs. SPIM0 and SPIM1 interfaces in master mode up to 25 MHz. SPIS interface supports slave mode only, up to 25 MHz. NOTE The power domain of the SPI interface is 1.8 V. A voltage-level translator should be used between the module and the host if your application is equipped with a 3.3 V processor or device interface. 3.16. ADC Interfaces*

The module provides two analog-to-digital converter (ADC) interfaces by default. The other two ADC interfaces can be multiplexed from GPIOs. To improve the accuracy of ADC voltage values, the traces of ADC should be surrounded with ground. Table 17: Pin Definition of ADC Interfaces Pin Name Pin No. I/O Description Comment BG952A-GL_QuecOpen_Hardware_Design 42 / 72 LPWA Module Series ADC0 ADC1 24 2 AI AI General-purpose ADC interface General-purpose ADC interface If unused, keep these pins open. Can be configured as GPIOs. The following table describes characteristics of ADC interfaces. Table 18: Characteristics of ADC Interfaces Parameter Min. Typ. Voltage Range Resolution 0 6

Max. 1.8 12 Unit V bit NOTES 1. ADC input voltage must not exceed 1.8 V. 2. 3. It is prohibited to supply any voltage to ADC pin when VBAT is removed. It is recommended to use resistor divider circuit for ADC application, and the divider resistor accuracy should be no less than 1 %. 4. After the module is turned off or enters PSM, do not pull up any pin of ADC interfaces. Otherwise the module will have additional power consumption and may have damaged pins. 3.17. Network Status Indication The module provides one network status indication pin: NET_STATUS. The pin is used to drive a network status indication LED. The following tables describe the pin definition and logic level changes of NET_STATUS in different network activity status. Table 19: Pin Definition of NET_STATUS Pin Name Pin No. I/O Description Comment NET_STATUS 21 DO Indicate the module's network activity status 1.8 V power domain. If the pin is unused, keep it open. BG952A-GL_QuecOpen_Hardware_Design 43 / 72 LPWA Module Series Table 20: Operating Status of NET_STATUS Pin Name Indicator Status (Logic Level Changes) Network Status Flicker slowly (200 ms High/1800 ms Low) Network searching NET_STATUS Flicker slowly (1800 ms High/200 ms Low) Idle Flicker quickly (125 ms High/125 ms Low) Data transfer is ongoing Always High Voice calling A reference design is shown in the following figure. Figure 20: Reference Design of NET_STATUS 3.18. STATUS The STATUS pin is used to indicate the operation status of the module. It outputs high level when the module powers on. Table 21: Pin Definition of STATUS Pin Name I/O Description Comment STATUS DO Indicate the module's operation status 1.8 V power domain Pin No. 20 The following figure shows a reference circuit of STATUS. BG952A-GL_QuecOpen_Hardware_Design 44 / 72 LPWA Module Series Figure 21: Reference Design of STATUS 3.19. GRFC Interfaces*

The module provides two generic RF control interfaces for the control of external antenna tuners. Table 22: Pin Definition of GRFC Interfaces Pin Name Pin No. Description Comment GRFC1 GRFC2 83 84 Generic RF controller Generic RF controller 1.8 V power domain. If unused, keep these pins open. I/O DO DO Table 23: Truth Table of GRFC Interfaces GRFC1 Level GRFC2 Level Frequency Range (MHz) Band Low Low High Low High Low 8802200 791894 698803 B1, B2, B3, B4, B8, B25, B66 B5, B18, B19, B20, B26, B27 B12, B13, B17, B28 BG952A-GL_QuecOpen_Hardware_Design 45 / 72 LPWA Module Series 4 GNSS Receiver 4.1. General Description BG952A-GL QuecOpen supports GPS and GLONASS satellite systems using dedicated hardware accelerators in a power and cost-efficient manner. The module supports standard NMEA-0183 protocol, and outputs GNSS NMEA sentences at 1 Hz data update rate via CLI UART interface by default. By default, BG772A-GL QuecOpen GNSS engine is switched off. It has to be switched on via AT command. The module does not support concurrent operation of WWAN and GNSS. For more details about GNSS engine technology and configurations, see document [1]. 4.2. GNSS Performance Table 24: GNSS Performance Parameter Description Conditions Cold start Autonomous Sensitivity (GNSS) Reacquisition Autonomous Tracking Cold start @ open sky Autonomous Autonomous XTRA enabled Autonomous XTRA enabled Hot start @ open sky Autonomous TTFF (GNSS) Warm start @ open sky Typ.

-145

-153

-158 29.42 TBD 28.38 TBD 1.07 Unit dBm dBm dBm s s s s s BG952A-GL_QuecOpen_Hardware_Design 46 / 72 LPWA Module Series Accuracy (GNSS) CEP-50 Autonomous @ open sky 1.41 XTRA enabled TBD s m NOTES 1. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep 2. Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock positioning for at least 3 minutes continuously). within 3 minutes after loss of lock. 3. Cold start sensitivity:

the minimum GNSS signal power at which the module can fix position successfully within 3 minutes after executing cold start command. 4.3. Layout Guidelines The following layout guidelines should be taken into account in application designs. Maximize the distance between the GNSS antenna and the main antenna. Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card should be kept away from the antennas. Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar isolation and protection. Keep 50 characteristic impedance for ANT_GNSS trace. See Chapter 5 for GNSS antenna reference design and antenna installation information. BG952A-GL_QuecOpen_Hardware_Design 47 / 72 LPWA Module Series 5 Antenna Interfaces The module includes a main antenna interface and a GNSS antenna interface. The impedance of antenna ports is 50 . 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of the main antenna interface is shown below. Table 25: Pin Definition of the Main Antenna Interface Pin Name Pin No. I/O Description Comment ANT_MAIN 60 AIO Main antenna interface 50 impedance 5.1.2. Operating Frequency Table 26: BG952A-GL QuecOpen Operating Frequency 3GPP Band Transmit LTE HD-FDD B1 19201980 LTE HD-FDD B2 18501910 LTE HD-FDD B3 17101785 LTE HD-FDD B4 17101755 LTE HD-FDD B5 824849 LTE HD-FDD B8 880915 LTE HD-FDD B12 699716 Receive 21102170 19301990 18051880 21102155 869894 925960 729746 Unit MHz MHz MHz MHz MHz MHz MHz BG952A-GL_QuecOpen_Hardware_Design 48 / 72 LPWA Module Series LTE HD-FDD B13 777787 LTE HD-FDD B17 4 704716 LTE HD-FDD B18 815830 LTE HD-FDD B19 830845 LTE HD-FDD B20 832862 LTE HD-FDD B26 5 814849 LTE HD-FDD B27 5 807824 LTE HD-FDD B28 703748 746756 734746 860875 875890 791821 859894 852869 758803 LTE HD-FDD B25 18501915 19301995 LTE HD-FDD B66 17101780 21102180 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 5.1.3. Reference Design A reference design of main antenna interface is shown as below. It is recommended to reserve a -type matching circuit for better RF performance, and the -type matching components (R1/C1/C2) should be placed as close to the antenna as possible. The capacitors are not mounted by default. Figure 22: Reference Design of Main Antenna Interface 4 LTE HD-FDD B17 is supported in Cat NB1/Cat NB2* only. 5 LTE HD-FDD B26 and B27 are supported in Cat M1 only. BG952A-GL_QuecOpen_Hardware_Design 49 / 72 LPWA Module Series 5.2. GNSS Antenna Interface 5.2.1. Pin Definition Table 27: Pin Definition of GNSS Antenna Interface Pin Name Pin No. I/O Description Comment ANT_GNSS 49 AI GNSS antenna interface 50 impedance 5.2.2. GNSS Operating Frequency Table 28: GNSS Operating Frequency Type GPS Frequency 1575.42 1.023 GLONASS 1597.51605.8 Unit MHz MHz 5.2.3. Reference Design A reference design of GNSS antenna interface is shown as below. Figure 23: Reference Design of GNSS Antenna Interface NOTES The module is designed with a built-in LNA, and supports passive GNSS antenna only. Active antenna and external LNA are not supported. BG952A-GL_QuecOpen_Hardware_Design 50 / 72 LPWA Module Series 5.3. Reference Design of RF Layout For users PCB, the characteristic impedance of all RF traces should be controlled to 50 . The impedance of the RF traces is usually determined by the trace width (W), the materials dielectric constant, the height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB structures. Figure 24: Microstrip Design on a 2-layer PCB Figure 25: Coplanar Waveguide Design on a 2-layer PCB BG952A-GL_QuecOpen_Hardware_Design 51 / 72 LPWA Module Series Figure 26: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 27: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design:

Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully 50 . connected to ground. The distance between the RF pins and the RF connector should be as short as possible, and all the right-angle traces should be changed to curved ones. The recommended trace angle is 135. There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be no less than two times the width of RF signal traces (2 W). Keep RF traces away from interference sources, and avoid intersection and paralleling between traces on adjacent layers. BG952A-GL_QuecOpen_Hardware_Design 52 / 72 LPWA Module Series For more details about RF layout, see document [6]. 5.4. Antenna Installation 5.4.1. Antenna Requirements Table 29: Antenna Requirements Antenna Type Requirements GNSS LTE Frequency range: 15591609 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0 dBi VSWR: 2 Efficiency: > 30 %

Max. Input Power: 50 W Input Impedance: 50 Cable Insertion Loss:

< 1 dB: LB (< 1 GHz)

< 1.5 dB: MB (12.3 GHz) 5.4.2. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use U.FL-R-SMT connectors provided by HIROSE. BG952A-GL_QuecOpen_Hardware_Design 53 / 72 LPWA Module Series Figure 28: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 29: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connectors. Figure 30: Space Factor of Mated Connectors (Unit: mm) BG952A-GL_QuecOpen_Hardware_Design 54 / 72 LPWA Module Series For more details, visit http://www.hirose.com. BG952A-GL_QuecOpen_Hardware_Design 55 / 72 LPWA Module Series 6 Reliability, Radio and Electrical Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 30: Absolute Maximum Ratings Parameter VBAT_BB VBAT_RF USB_VBUS Voltage at Digital Pins Min.

-0.2

-0.2 1.19

-0.3 6.2. Power Supply Ratings Table 31: Power Supply Ratings Max. Unit 4.5 4.5 2.0 2.0 V V V V Parameter Description Conditions Min. Typ. Max. Unit VBAT_BB VBAT_RF Power supply for the modules baseband part Power supply for the modules RF part USB connection detection The actual input voltages must be kept between the minimum and the maximum values. BG95-MF USB_VBUS

5.0

V 2.2 3.3 4.35 V BG952A-GL_QuecOpen_Hardware_Design 56 / 72 LPWA Module Series 6.3. Operating and Storage Temperatures Table 32: Operating and Storage Temperatures Parameter Min. Operating Temperature Range 1)

-35 Extended Temperature Range 2)

-40 Storage Temperature Range

-40 Typ.

+ 25 Max.

+ 75

+ 85

+ 90 Unit C C C NOTES 1. 2. 1) Within the operating temperature range, the module meets 3GPP specifications. 2) Within the extended temperature range, the module remains the ability to establish and maintain functions such as SMS and data transmission, without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may exceed the specified tolerances of 3GPP. When the temperature returns to the operating temperature range, the module meets 3GPP specifications again. 6.4. Power Consumption Table 33: Power Consumption (Power Supply: 3.3 V, Room Temperature) Description Conditions Avg. Max. Unit Leakage PSM Power-off @ USB/UART disconnected TBD PSM @ USB/UART disconnected Rock Bottom AT+CFUN=0 @ Sleep mode Sleep Mode

(USB/UART disconnected) LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s

TBD TBD TBD TBD A A A mA mA BG952A-GL_QuecOpen_Hardware_Design 57 / 72 Idle State

(USB/UART disconnected) LTE Cat M1 data transfer

(GNSS OFF) LTE HD-FDD B13 @ 23.16 dBm LTE HD-FDD B18 @ 23.24 dBm LPWA Module Series LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE HD-FDD B1 @ 22.8 dBm LTE HD-FDD B2 @ 23.37 dBm LTE HD-FDD B3 @ 23.22 dBm LTE HD-FDD B4 @ 23.25 dBm LTE HD-FDD B5 @ 23.32 dBm LTE HD-FDD B8 @ 23.56 dBm LTE HD-FDD B12 @ 23.49 dBm LTE HD-FDD B19 @ 23.34 dBm LTE HD-FDD B20 @ 23.37 dBm LTE HD-FDD B25 @ 23.37 dBm LTE HD-FDD B26 @ 23.29 dBm LTE HD-FDD B27 @ 23.16 dBm LTE HD-FDD B28A @ 23.41 dBm LTE HD-FDD B28B @ 23.33 dBm TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA BG952A-GL_QuecOpen_Hardware_Design 58 / 72 LTE HD-FDD B66 @ 23.19 dBm LTE HD-FDD B1 @ 22.7 dBm LTE HD-FDD B2 @ 22.72 dBm LTE HD-FDD B3 @ 23.24 dBm LTE HD-FDD B4 @ 23.19 dBm LTE HD-FDD B5 @ 23.32 dBm LTE HD-FDD B8 @ 22.71 dBm LTE HD-FDD B12 @ 22.8 dBm LTE HD-FDD B13 @ 23.23 dBm LTE HD-FDD B17 @ 22.73 dBm LTE HD-FDD B18 @ 23.28 dBm LTE HD-FDD B19 @ 23.36 dBm LTE HD-FDD B20 @ 23.39 dBm LTE HD-FDD B25 @ 23.4 dBm LTE HD-FDD B28 @ 22.75 dBm LTE HD-FDD B66 @ 23.26 dBm LPWA Module Series TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA LTE Cat NB1 data transfer

(GNSS OFF) Table 34: GNSS Current Consumption of (3.3 V Power Supply, Room Temperature) Description Conditions Searching

(AT+CFUN=0) Tracking

(AT+CFUN=0) Cold start @ Instrument Hot start @ Instrument Lost state @ Instrument Instrument environment @ Passive antenna Half sky @ Real network, Passive antenna Typ. TBD TBD TBD TBD TBD Unit mA mA mA mA mA BG952A-GL_QuecOpen_Hardware_Design 59 / 72 LPWA Module Series 6.5. Tx Power Table 35: Tx Power Frequency Bands Max. Tx Power Min. Tx Power LTE HD-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B17 6/B18/

B19/B20/B25/B26 7/B27 7/B28/B66 23 dBm 2.7 dB

< -39 dBm 6.6. RF Receiving Sensitivity Table 36: Conducted RF Receiving Sensitivity of BG952A-GL QuecOpen Frequency Band Primary Diversity LTE HD-FDD B1 LTE HD-FDD B2 LTE HD-FDD B3 LTE HD-FDD B4 LTE HD-FDD B5 LTE HD-FDD B8 LTE HD-FDD B12 LTE HD-FDD B13 LTE HD-FDD B17 6 LTE HD-FDD B18 Supported

Receiving Sensitivity (dBm) Cat M1/3GPP Cat NB18/3GPP

-106.6/-102.3

-115.3/-107.5

-106.2/-100.3

-114.3/-107.5

-106.2/-99.3

-114/-107.5

-106.6/-102.3

-114/-107.5

-106.8/-100.8

-115/-107.5

-107/-99.8

-115/-107.5

-106.4/-99.3

-114.3/-107.5

-106.4/-99.3

-114.6/-107.5

-114.6/-107.5

-107.2/-102.3

-115.3/-107.5 6 LTE HD-FDD B17 is supported in Cat NB1/Cat NB2* only. 7 LTE HD-FDD B26 and B27 are supported in Cat M1 only. 8 LTE Cat NB1 receiving sensitivity without repetitions. BG952A-GL_QuecOpen_Hardware_Design 60 / 72 LPWA Module Series

-107/-102.3

-115.3/-107.5

-106.6/-99.8

-114.6/-107.5

-106.4/-100.3

-114.3/-107.5

-107/-100.3

-107.2/-100.8

-106.6/-100.8

-114.6/-107.5

-106.8/-101.8

-114.9/-107.5 LTE HD-FDD B19 LTE HD-FDD B20 LTE HD-FDD B25 LTE HD-FDD B26 9 LTE HD-FDD B27 9 LTE HD-FDD B28 LTE HD-FDD B66 6.7. ESD If the static electricity generated by various ways discharges to the module, the module maybe damaged to a certain extent. Thus, please take proper ESD countermeasures and handling methods. For example, wearing anti-static gloves during the development, production, assembly and testing of the module;

adding ESD protective components to the ESD sensitive interfaces and points in the product design. Table 37: Electrostatic Discharge Characteristics (25 C, 45 % Relative Humidity) Tested Interfaces Contact Discharge Air Discharge Unit VBAT, GND Main/GNSS Antenna Interfaces TBD TBD TBD TBD kV kV 9 LTE HD-FDD B26 and B27 are supported in Cat M1 only. BG952A-GL_QuecOpen_Hardware_Design 61 / 72 LPWA Module Series 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are 0.05 mm unless otherwise specified. 7.1. Mechanical Dimensions Figure 31: Module Top and Side Dimensions BG952A-GL_QuecOpen_Hardware_Design 62 / 72 LPWA Module Series 1.00 1.00 0.25 Pin 1 1.90 1.10 0.50 0.25 1.10 19.900.20 0.25 1.10 0.55 1.95 1.10 5.10 1.00 0 5

. 8 0.85 1.70

. 0 2 0 0 6 3 2

. 1.00 1.70 1.00 1.70 0.70 0.25 0.55 40x1.0 62x0.7 40x1.0 62x1.10 Figure 32: Bottom Dimensions (Bottom View) NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard. BG952A-GL_QuecOpen_Hardware_Design 63 / 72 7.2. Recommended Footprint LPWA Module Series 9.95 9.15 7.45 1.10 19.900.20 9.95 9.15 7.15 1.95 0.55 1.10 0.25 1.00 1.00 Pin 1 1.10 1.70 2.50 1.70 1.70 0.85

. 0 2 0 0 6

. 3 2 0.25 1.70 0.15 1.70 0.85 1

. 7 0 2.55 0.85 1.00 1.10 1.00 0.70 1.10 0.25 1.10 2.50 1.10 4.25 5.95 62x0.7 4.25 5.95 40x1.0 62x1.10 40x1.0 0.25 0

. 2 0 1

. 9 0 5

. 9 5 4

. 2 5 4

. 2 5 5

. 9 5 1 1

. 8 0 1 1

. 0 0 9

. 7 0 7

. 6 5 7

. 6 5 9

. 6 0 1 1

. 0 0 1 1

. 8 0 Figure 33: Recommended Footprint (Top View) NOTES 1. Keep at least 3 mm between the module and other components on the motherboard to improve soldering quality and maintenance convenience. 2. All reserved pins must be kept open. 3. For stencil design requirements of the module, see document [6]. BG952A-GL_QuecOpen_Hardware_Design 64 / 72 7.3. Top and Bottom Views LPWA Module Series Figure 34: Top and Bottom Views NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. BG952A-GL_QuecOpen_Hardware_Design 65 / 72 LPWA Module Series 8 Storage, Manufacturing and Packaging 8.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 5 C and the relative humidity should be 3560 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition. 3. The floor life of the module is 168 hours 1) in a plant where the temperature is 23 5 C and relative humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g. a drying cabinet). 4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under the following circumstances:

The module is not stored in Recommended Storage Condition;

Violation of the third requirement above occurs;

Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;

Before module repairing. 5. If needed, the pre-baking should follow the requirements below:

The module should be baked for 8 hours at 120 5 C;

All modules must be soldered to PCB within 24 hours after the baking, otherwise they should be put in a dry environment such as in a drying oven. BG952A-GL_QuecOpen_Hardware_Design 66 / 72 LPWA Module Series NOTES 1) This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 1. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. If the temperature and moisture do not conform to IPC/JEDEC J-STD-033 or the relative moisture is over 60 %, it is recommended to start the solder reflow process within 24 hours after the package is removed. And do not remove the packages of tremendous modules if they are not ready for soldering. 3. Take the module out of the packaging and put it on high-temperature resistant fixtures before baking. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure. 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.130.15 mm. For more details, see document [7]. It is suggested that the peak reflow temperature is 238 C to 246 C, and the absolute maximum reflow temperature is 246 C. To avoid damage to the module caused by repeated heating, it is strongly recommended that the module should be mounted after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. Figure 35: Recommended Reflow Soldering Thermal Profile BG952A-GL_QuecOpen_Hardware_Design 67 / 72 Table 38: Recommended Thermal Profile Parameters LPWA Module Series Soak time (between A and B: 150 C and 200 C) 70120 s Factor Soak Zone Max slope Reflow Zone Max slope Reflow time (D: over 220 C) Max temperature Cooling down slope Reflow Cycle Max reflow cycle Recommendation 13 C/s 13 C/s 4570 s 235246 C

-1.5 to -3 C/s 1 NOTE module. 1. If the module requires conformal coating, DO NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module. 2. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the 3. Due to the SMT process complexity, please contact Quectel Technical Support in advance regarding any situation that you are not sure about, or any process (e.g., selective soldering, ultrasonic soldering) that is not mentioned in document [6]. The module is delivered in a tape carrier packaging and details are as follows:

8.3. Packaging 8.3.1. Carrier Tape Dimension details:

BG952A-GL_QuecOpen_Hardware_Design 68 / 72 LPWA Module Series Figure 36: Carrier Tape Dimension Drawing Table 39: Carrier Tape Dimension Table (Unit: mm) W 44 P 32 B0 24 T A0 K0 K1 F E 0.35 20.2 3.15 6.65 20.2 1.75 8.3.2. Plastic Reel Figure 37: Plastic Reel Dimension Drawing Table 40: Plastic Reel Dimension Table (Unit: mm) D1 D2 W BG952A-GL_QuecOpen_Hardware_Design 69 / 72 LPWA Module Series 330 100 44.5 8.3.3. Packing Process Place the packaged plastic reel, humidity indicator card and desiccant bag inside a vacuum bag, then vacuumize it. Place the module onto the carrier tape and use the cover tape to cover them; then wind the heat-sealed carrier tape on the plastic reel and use the protective tape for protection. One plastic reel can load 250 modules. Place the vacuum-packed plastic reel inside a pizza box. Place 4 pizza boxes inside 1 carton and seal it. One carton can pack 1000 modules. Figure 38: Packaging Process BG952A-GL_QuecOpen_Hardware_Design 70 / 72 LPWA Module Series 9 Appendix A References Table 41: Related Documents SN Document Name Quectel_BG770A-GL&BG95xA-GL_GNSS_Application_Note Quectel_LTE_OPEN_EVB_User_Guide Quectel_BG77xA-GL&BG95xA-GL_AT_Commands_Manual Quectel_BG77xA-GL&BG95xA-GL_QCFG_AT_Commands_Manual Quectel_RF_Layout_Application_Note Quectel_Module_Secondary_SMT_Application_Note Quectel_BG952A-GL_QuecOpen_GPIO_Configuration Quectel_BG950A-GL&BG951A-GL_TE-A_User_Guide Table 42: Terms and Abbreviations Abbreviation Description Analog-to-Digital Converter Bits Per Second Challenge Handshake Authentication Protocol Coding Scheme Downlink Delta Firmware Upgrade Over The Air Extended Idle Mode Discontinuous Reception Enhanced Data Rates for GSM Evolution

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

ADC bps CHAP CS DFOTA DL e-I-DRX EDGE BG952A-GL_QuecOpen_Hardware_Design 71 / 72 LPWA Module Series Enhanced General Packet Radio Service Extended GSM (Global System for Mobile Communications) Evolved Packet Core Electrostatic Discharge Frequency Division Duplex Gaussian Minimum Shift Keying Global System for Mobile Communications EGPRS EGSM EPC ESD FDD GMSK GSM HSS I2C LED LNA LTE MO MS MSL MT PA PAP PCB PDU PPP PSM RF RHCP Rx SAW SMS Home Subscriber Server Inter-Integrated Circuit Light Emitting Diode Low Noise Amplifier Long Term Evolution Mobile Originated Mobile Station Moisture Sensitivity Level Mobile Terminated Power Amplifier Printed Circuit Board Protocol Data Unit Point-to-Point Protocol Power Saving Mode Radio Frequency Right Hand Circularly Polarized Receive Surface Acoustic Wave Short Message Service Password Authentication Protocol BG952A-GL_QuecOpen_Hardware_Design 72 / 72 LPWA Module Series SPI TDM TVS UL UE URC

(U)SIM Vmax Vnom Vmin VIHmax VIHmin VILmax VILmin VOHmin VOLmax VSWR WWAN Wi-Fi Serial Peripheral Interface Time-Division Multiplexing Transient Voltage Suppressor Uplink User Equipment Unsolicited Result Code

(Universal) Subscriber Identity Module Maximum Voltage Value Nominal Voltage Value Minimum Voltage Value Maximum Input High Level Voltage Value Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Minimum Input Low Level Voltage Value Minimum Output High Level Voltage Value Maximum Output Low Level Voltage Value Voltage Standing Wave Ratio Wireless Wide Area Network Wireless Fidelity BG952A-GL_QuecOpen_Hardware_Design 73 / 72 LPWA Module Series CE Statement The minimum distance between the user and/or any bystander and the radiating structure of the transmitter is 20cm. Hereby, We, Quectel Wireless Solutions Co., Ltd. declares that the radio equipment type BG951A-GL is in compliance with the Directive 2014/53/EU. The full text of the EU declaration of conformity is available at the following internet address:

Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China https://www.quectel.com/support/downloadb/TechnicalDocuments.htm The device operates with the following frequency bands and transmitting power:

According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a FCC Certification Requirements. mobile device. And the following conditions must be met:

1. This Modular Approval is limited to OEM installation for mobile and fixed applications only. The antenna installation and operating configurations of this transmitter, including any applicable source-based time-

averaging duty factor, antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements of 2.1091. 2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the users body and must not transmit simultaneously with any other antenna or transmitter. 3.A label with the following statements must be attached to the host end product: This device contains FCC ID: XMR2022BG952AGL. 4.To comply with FCC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed:

Catm LTE Band2/25:11.000dBi Catm LTE Band4/66:8.000dBi Catm LTE Band5/26:12.541dBi Catm LTE Band12:11.798dBi Catm LTE Band13:12.214dBi BG952A-GL_QuecOpen_Hardware_Design 74 / 72 LPWA Module Series NB LTE Band2/25:11.000dBi NB LTE Band4/66:8.000dBi NB LTE Band5:12.541 dBi NB LTE Band12:11.798dBi NB LTE Band13:12.214dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093 If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations. For this device, OEM integrators must be provided with labeling instructions of finished products. Please refer to KDB784748 D01 v07, section 8. Page 6/7 last two paragraphs:

A certified modular has the option to use a permanently affixed label, or an electronic label. For a permanently affixed label, the module must be labeled with an FCC ID - Section 2.926 (see 2.2 Certification (labeling requirements) above). The OEM manual must provide clear instructions explaining to the OEM the labeling requirements, options and OEM user manual instructions that are required (see next paragraph). For a host using a certified modular with a standard fixed label, if (1) the modules FCC ID is not visible when installed in the host, or (2) if the host is marketed so that end users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible;

then an additional permanent label referring to the enclosed module:Contains Transmitter Module FCC ID: XMR2022BG952AGL or Contains FCC ID: XMR2022BG952AGL must be used. The host OEM user manual must also contain clear instructions on how end users can find and/or access the module and the FCC ID. BG952A-GL_QuecOpen_Hardware_Design 75 / 72 LPWA Module Series The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The users manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. In cases where the manual is provided only in a form other than paper, such as on a computer disk or over the Internet, the information required by this section may be included in the manual in that alternative form, provided the user can reasonably be expected to have the capability to access information in that form. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the manufacturer could void the users authority to operate the equipment. IC Statement IRSS-GEN

"This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device." or "Le prsent appareil est conforme aux CNR dIndustrie Canada applicables aux appareils radio exempts de licence. Lexploitation est autorise aux deux conditions suivantes :

1) lappareil ne doit pas produire de brouillage; 2) lutilisateur de lappareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible den compromettre le fonctionnement."

Dclaration sur l'exposition aux rayonnements RF The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the users body BG952A-GL_QuecOpen_Hardware_Design 76 / 72 LPWA Module Series and must not transmit simultaneously with any other antenna or transmitter. L'autre utilis pour l'metteur doit tre install pour fournir une distance de sparation d'au moins 20 cm de toutes les personnes et ne doit pas tre colocalis ou fonctionner conjointement avec une autre antenne ou un autre metteur. To comply with IC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed:

Catm LTE Band2/25:11.000dBi Catm LTE Band4/66:8.000dBi Catm LTE Band5/26:12.541dBi Catm LTE Band12:11.798dBi Catm LTE Band13:12.214dBi Catm LTE Band85:11.798dBi NB LTE Band2/25:11.000dBi NB LTE Band4/66:8.000dBi NB LTE Band5:12.541 dBi NB LTE Band12:11.798dBi NB LTE Band13:12.214dBi The host product shall be properly labelled to identify the modules within the host product. The Innovation, Science and Economic Development Canada certification label of a module shall be clearly visible at all times when installed in the host product; otherwise, the host product must be labeled to display the Innovation, Science and Economic Development Canada certification number for the module, preceded by the word Contains or similar wording expressing the same meaning, as follows:

BG952A-GL_QuecOpen_Hardware_Design 77 / 72 LPWA Module Series Contains IC: 10224A-022BG952AGL or where: 10224A-022BG952AGL is the modules certification number. Le produit hte doit tre correctement tiquet pour identifier les modules dans le produit hte. L'tiquette de certification d'Innovation, Sciences et Dveloppement conomique Canada d'un module doit tre clairement visible en tout temps lorsqu'il est installdans le produit hte; sinon, le produit hte doit porter une tiquette indiquant le numro de certification d'Innovation, Sciences et Dveloppement conomique Canada pour le module, prcd du mot Contient ou d'un libell semblable exprimant la mme signification, comme suit:"Contient IC: 10224A-022BG952AGL " ou "o: 10224A-022BG952AGL est le numro de certification du module. BG952A-GL_QuecOpen_Hardware_Design 78 / 72 LPWA Module Series BG952A-GL_QuecOpen_Hardware_Design 79 / 72

QUuECcTree BG952A-GL Q1-AXXXX BG952AGLXXXXX-XXXXX SN:XXXXXXXXXXXXXXX IMEI: XXXXXXXXXXXXXXX FCC ID: XMR2022BG952AGL IC: 10224A-022BG952AGL Be 3 2

QIECCTEL Federal Communications Commission 7435 Oakland Mills Road Columbia MD 21046 Subject: Certification designating a U.S. agent for service of process pursuant to Part 2.911(d)(7) To whom it may concern, Quectel Wireless Solutions Company Limited, Grantee Code: XMR (the applicant) certifies that, as of the date of the filing of application, Ikotek USA, Inc., FRN: 0033350331 (the agent) is designated as the U.S. agent for the purpose of accepting service of process on behalf of the applicant. The physical U.S. address and email for the designated agent are:

Physical U.S. address: 9920 Pacific Heights Blvd., Ste. 150, #7025, San Diego, CA 92121 Email: compliance@ikotek.com The applicant accepts to maintain an agent for service of process in the United States for no less than one year after either the grantee has permanently terminated all marketing and importation of the applicable equipment within the U.S., or the conclusion of any Commission-related administrative or judicial proceeding involving the equipment, whichever is later. The agent accepts the designation by (the applicant) as the U.S. agent to accept service of process includes, but is not limited to, delivery of any correspondence, notices, orders, decisions, and requirements of administrative, legal, or judicial process related to Commission proceedings. Signed by the Applicant Signed by the Agent (if different from the Applicant) Name: Jean Hu C Name-dseph M. Peterson Title: Certification Manager Title: President and CEO Email: Jean.hu@quectel.com Email: joe.peterson@ikotek.com Date: 16 February 2023 Date: February 17%, 2023

(Quectel Wireless Solutions Co., Ltd) To: Federal Communications Commission Date: 2023/07/19 7435 Oakland Mills Road Columbia, MD 21046 USA Attestation Section 2.911(d)(5)(i) and Section 2.911(d)(5)(ii)

(KDB 986446 D01 Covered Equipment) Section 2.911(d)(5)(i)

[Quectel Wireless Solutions Co., Ltd] (the applicant) certifies that the equipment for which authorization is sought is not covered equipment prohibited from receiving an equipment authorization pursuant to section 2.903 of the FCC rules. Section 2.911(d)(5)(ii)

[Quectel Wireless Solutions Co., Ltd] (the applicant) certifies that, as of the date of the filing of the application, the applicant [is not] identified on the Covered List (as a specifically named entity or any of its subsidiaries or affiliates) as an entity producing covered equipment. Type of Equipment subject to FCC Certification:

FCC ID:XMR 2022BG952AGL If you have any questions, please feel free to contact me Jean Hu Contact Person:

Position in the Company: Quectel Wireless Solutions Co., Ltd Date of Signature:

2023/07/17 ___________________________ Signatory

(signature of the applicant)

Quectel Wireless Solutions Company Limited Declaration of the Modular Approval Applicant / Grantee FCC ID:

Model:

Quectel Wireless Solutions Co., Ltd. XMR2022BG952AGL BG952A-GL The single module transmitter has been evaluated then tested meeting the requirements under Part 15C Section 212 as below:

Modular approval requirement EUT Condition

(a) The radio elements of the modular transmitter must have their own shielding. The physical crystal and tuning capacitors may be located external to the shielded radio elements. The radio elements of the modular transmitter have their own shielding. Com ply YES

(b) The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with part 15 requirements under conditions of excessive data rates or over-modulation. The modular has buffered data inputs, it is integrated in chip. Please see schematic.pdf YES

(c)The modular transmitter must have its own powersupply regulation.

(d) The modular transmitter must comply with the antenna and transmission system requirements of Sections 15.203, 15.204(b) and 15.204(c). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of Section 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph (b) of this section.

(e)The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing for compliance with part 15 requirements. Unless the transmitter module will be battery powered, it must comply with the AC line conducted requirements found in Section 15.207. AC or DC power lines and data input/output lines connected to the module must not contain ferrites, unless they will be marketed with these the module (see Section 15.27(a)). The length of All power lines derived from the host device are regulated before energizing other circuits internal to the BG952A-GL. Please see schematic.pdf A permanently attached antenna or unique antenna connector is not a requirement for licensed modules. YES YES The BG952A-GLwas tested in a stand alone configuration via a PCMCIA extender. Please see spurious setup YES Quectel Wireless Solutions Company Limited lines shall be the length typical of actual use or, if that length is unknown, at least 10 centimeters to insure that there is no coupling between the case of the module and supporting equipment. Any accessories, peripherals, or support equipment connected to the module during testing shall be unmodified and commercially available (see Section 15.31(i))mustnotbeinsideanotherdeviceduringtesting.

(f)The modular transmitter must be equipped with either a permanently affixed label or must be capable of electronically displaying its FCC identification number.

(g) The modular transmitter must comply with any specific rules or operating requirements that ordinarily apply to a complete transmitter and the manufacturer must provide adequate instructions along with the module to explain any suchrequirements. A copy of these instructions must be included in the application for equipmentauthorizationrequirements,whicharebasedonthei ntendeduse/configurations.

(h)The modular transmitter must comply with any applicable RF exposure requirements in its final configuration. The label position of BG952A-GLis clearly indicated. If the FCC ID of the module cannot be seen when it is installed, then the host label must include the text:

Contains FCC ID: XMR2022BG952AGLL. Please see the label.pdf The BG952A-GL is compliant with all applicable FCC rules. Detail instructions are given in the User Manual. YES YES The BG952A-GL is approved to comply with the applicable RF exposure requirement, please see the MPE evaluation with 20cm as the distance restriction. YES Dated By:

2023/07/17 Jean Hu Signature Printed Title: Project Manager

Quectel Wireless Solutions Co., Ltd POWER OF ATTORNEY DATE:July 17, 2023 To:

Federal Communications Commission, Authorization & Evaluation Division, 7435 Oakland Mills Road, Columbia, MD 21046 We, the undersigned, hereby authorize TA Technology (Shanghai) Co., Ltd.

/Sun Yue on our behalf, to apply to FCC on our equipment for FCC ID:

XMR2022BG952AGL. Any and all acts carried out by TA Technology

(Shanghai) Co., Ltd. / Sun Yue on our behalf shall have the same effect as acts of our own. Sincerely, Signature:

Print name: Jean Hu Company: Quectel Wireless Solutions Co., Ltd

Quectel Wireless Solutions Co., Ltd Statement We Quectel Wireless Solutions Co., Ltd declare the following models. Product Name: LTE Cat M1 & Cat NB1 Module Model Number: BG950A-GL, BG952A-GL BG950A-GL and BG952A-GL share the same chipset baseline, the same hardware and software design, and also support the same frequency bands. The only difference is that BG952A-GL supports QuecOpen for secondary development while BG950A-GL do not support. Module QuecOpen BG950A-GL N/A BG952A-GL Supported QuecOpen is a software SDK for our customer to develop their own application and running in BG952A-GL module. Applications based on QuecOpen will run independently and do not have any interface to affect modem. Thus, all the performance of module will be the same as BG950A-GL. BG950A-GL and BG952A-GL share the same firmware baseline, and secondary developed firmware based on QuecOpen will be flashed on customer side. Your assistance on this matter is highly appreciated. Sincerely, Name: Jean Hu Title: Certification Section Manager

Quectel Wireless Solutions Co., Ltd Statement We Quectel Wireless Solutions Co., Ltd declare the following models. Product Name: LTE Cat M1 & Cat NB2 Module Model Number: BG952A-GL BG952A-GL supports from Cat NB1(3GPP R13) to Cat NB2(3GPP R14) only by FW updating, the hardware remains the same. The key information for the module is as below:

Module BG952A-GL (Cat NB1) BG952-GL (Cat NB2) BB Chip ALT1250 ALT1250 Category Cat M1 & NB1 Cat M1 & NB2 Cat M1 Cat M1 LTE-HD-FDD: B1/B2/B3/B4/B5/B8 | LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B18/B19/B20/B25/B26 | /B12/B13/B18/B19/B20/B25/B26

/B27/B28/B66 /B27/B28/B66 Frequency Sends | cat cat Nea LTE-HD-FDD: B1/B2/B3/B4/B5/B8 | LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B17/B18/B19/B20/B25 | /B12/B13/B17/B18/B19/B20/B25

/B28/B66 /B28/B66 GNSS GPS, GLONASS GPS, GLONASS QuecOpen N/A N/A Your assistance on this matter is highly appreciated. Sincerely;

7 AIL Name: Jean Hu Title: Certification Section Manager UY

Model Number:BG952A-GL FCC ID:XMR2022BG952AGL Date of issue:2022-07-27 BG952A-GL supports from Cat NB1(3GPPR13) to Cat NB2(3GPPR14) only by FW updating, the hardware remains the same. The report validation information is below:

NB report :

There is only verified RF Power Output, Band Edge Compliance and Spurious Emissions at Antenna Terminals, and did not worsen, so they were not recorded in the report. Powers of new variant are varied due to measurement uncertainty, and sample tolerance of the acceptance range. The detailed product change description please refers to the Difference Declaration Letter (Variant 2). LTE-M report:

There is only verified RF Power Output, Band Edge Compliance and Spurious Emissions at Antenna Terminals, and did not worsen, so they were not recorded in the report. Powers of new variant are varied due to measurement uncertainty, and sample tolerance of the acceptance range. The detailed product change description please refers to the Difference Declaration Letter (Variant 2).

Quectel Wireless Solutions Co., Ltd Office of Engineering Technology Federal Communications Commission 7435 Oakland Mills Road Columbia, MD21046 Subject; Request for Long Term Confidentiality FCC ID:XMR2022BG952AGL To Whom It May Concern, Pursuant to the provisions of the Commissions rules Title 47 Sections 0.457 and 0.459, we are requesting the Commission to withhold the following attachment(s) as confidential documents from public disclosure indefinitely. These documents contain detailed system and equipment descriptions and are considered as proprietary information in operation of the equipment. The public disclosure of these documents might be harmful to our company and would give competitors an unfair advantage in the market. Tune up procedure It is our understanding that all measurement test reports, FCC ID label format and correspondence during the certification review process cannot be granted as confidential documents and this information will be available for public review once the grant of equipment authorization is issued. Signature :

Print name:

Jean Hu Date:2023/07/17 Company: Quectel Wireless Solutions Co., Ltd

Quectel Wireless Solutions Co., Ltd Office of Engineering Technology Federal Communications Commission 7435 Oakland Mills Road Columbia, MD21046 Subject; Request for Long Term Confidentiality FCC ID:XMR2022BG952AGL To Whom It May Concern, Pursuant to the provisions of the Commissions rules Title 47 Sections 0.457 and 0.459, we are requesting the Commission to withhold the following attachment(s) as confidential documents from public disclosure indefinitely. These documents contain detailed system and equipment descriptions and are considered as proprietary information in operation of the equipment. The public disclosure of these documents might be harmful to our company and would give competitors an unfair advantage in the market. Schematic Diagram Block Diagram Parts List Operational Description Tune up procedure It is our understanding that all measurement test reports, FCC ID label format and correspondence during the certification review process cannot be granted as confidential documents and this information will be available for public review once the grant of equipment authorization is issued. Signature :

Print name:

Jean Hu Company: Quectel Wireless Solutions Co., Ltd

Quectel Wireless Solutions Company Limited Declaration of the Modular Approval Applicant / Grantee FCC ID:

Model:

Quectel Wireless Solutions Co., Ltd. XMR2022BG952AGL BG952A-GL The single module transmitter has been evaluated then tested meeting the requirements under Part 15C Section 212 as below:

Modular approval requirement EUT Condition

(a) The radio elements of the modular transmitter must have their own shielding. The physical crystal and tuning capacitors may be located external to the shielded radio elements. The radio elements of the modular transmitter have their own shielding. Com ply YES

(b) The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with part 15 requirements under conditions of excessive data rates or over-modulation. The modular has buffered data inputs, it is integrated in chip. Please see schematic.pdf YES

(c)The modular transmitter must have its own powersupply regulation.

(d) The modular transmitter must comply with the antenna and transmission system requirements of Sections 15.203, 15.204(b) and 15.204(c). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of Section 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph (b) of this section.

(e)The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing for compliance with part 15 requirements. Unless the transmitter module will be battery powered, it must comply with the AC line conducted requirements found in Section 15.207. AC or DC power lines and data input/output lines connected to the module must not contain ferrites, unless they will be marketed with these the module (see Section 15.27(a)). The length of All power lines derived from the host device are regulated before energizing other circuits internal to the BG951A-GL. Please see schematic.pdf A permanently attached antenna or unique antenna connector is not a requirement for licensed modules. YES YES The BG951A-GLwas tested in a stand alone configuration via a PCMCIA extender. Please see spurious setup YES Quectel Wireless Solutions Company Limited lines shall be the length typical of actual use or, if that length is unknown, at least 10 centimeters to insure that there is no coupling between the case of the module and supporting equipment. Any accessories, peripherals, or support equipment connected to the module during testing shall be unmodified and commercially available (see Section 15.31(i))mustnotbeinsideanotherdeviceduringtesting.

(f)The modular transmitter must be equipped with either a permanently affixed label or must be capable of electronically displaying its FCC identification number.

(g) The modular transmitter must comply with any specific rules or operating requirements that ordinarily apply to a complete transmitter and the manufacturer must provide adequate instructions along with the module to explain any suchrequirements. A copy of these instructions must be included in the application for equipmentauthorizationrequirements,whicharebasedonthei ntendeduse/configurations.

(h)The modular transmitter must comply with any applicable RF exposure requirements in its final configuration. The label position of BG951A-GLis clearly indicated. If the FCC ID of the module cannot be seen when it is installed, then the host label must include the text:

Contains FCC ID: XMR2021BG951AGL. Please see the label.pdf The BG951A-GL is compliant with all applicable FCC rules. Detail instructions are given in the User Manual. The BG951A-GL is approved to comply with the applicable RF exposure requirement, please see the MPE evaluation with 20cm as the distance restriction. YES YES YES Dated By:

2022/07/08 Jean Hu Signature Printed Title: Project Manager