FCC ID: XMR2020BG95M1 LTE Cat M1 Module

LPWA Module Series BG95 Hardware Design BG95-M1 Design Hardware LPWA Module Series Rev. BG95_Hardware_Design_V1.0 Date: 2019-05-15 Status: Preliminary BG95_Hardware_Design 1 / 80 LPWA Module Series BG95 Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters:

Quectel Wireless Solutions Co., Ltd. 7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit:

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http://www.quectel.com/support/technical.htm Or email to: support@quectel.com GENERAL NOTES QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION PROVIDED IS BASED UPON CUSTOMERS REQUIREMENTS. QUECTEL MAKES EVERY EFFORT TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR RELIANCE UPON THE INFORMATION. ALL INFORMATION SUPPLIED HEREIN IS SUBJECT TO CHANGE WITHOUT PRIOR NOTICE. COPYRIGHT THE INFORMATION CONTAINED HERE IS PROPRIETARY TECHNICAL INFORMATION OF QUECTEL WIRELESS SOLUTIONS CO., LTD. TRANSMITTING, REPRODUCTION, DISSEMINATION AND EDITING OF THIS DOCUMENT AS WELL AS UTILIZATION OF THE CONTENT ARE FORBIDDEN WITHOUT PERMISSION. OFFENDERS WILL BE HELD LIABLE FOR PAYMENT OF DAMAGES. ALL RIGHTS ARE RESERVED IN THE EVENT OF A PATENT GRANT OR REGISTRATION OF A UTILITY MODEL OR DESIGN. Copyright Quectel Wireless Solutions Co., Ltd. 2019. All rights reserved. BG95_Hardware_Design 2 / 80 LPWA Module Series BG95 Hardware Design About the Document History Revision Date Author Description 1.0 2019-05-15 Initial Lim PENG/

Garey XIE BG95_Hardware_Design 3 / 80 LPWA Module Series BG95 Hardware Design Contents About the Document ................................................................................................................................ 3 Contents .................................................................................................................................................... 4 Table Index ............................................................................................................................................... 6 Figure Index .............................................................................................................................................. 8 1 Introduction ....................................................................................................................................... 9 1.1. Safety Information .................................................................................................................. 10 2 Product Concept ............................................................................................................................. 14 2.1. General Description ................................................................................................................ 14 2.2. Key Features .......................................................................................................................... 16 2.3. Functional Diagram ................................................................................................................ 19 2.4. Evaluation Board .................................................................................................................... 20 3 Application Interfaces ..................................................................................................................... 22 3.1. Pin Assignment ...................................................................................................................... 23 3.2. Pin Description ....................................................................................................................... 24 3.3. Operating Modes .................................................................................................................... 31 3.4. Power Saving ......................................................................................................................... 32 3.4.1. Airplane Mode .............................................................................................................. 32 3.4.2. Power Saving Mode (PSM).......................................................................................... 33 3.4.3. Extended Idle Mode DRX (e-I-DRX) ............................................................................ 34 3.4.4. Sleep Mode* ................................................................................................................ 34 3.4.4.1. UART Application .............................................................................................. 34 3.5. Power Supply ......................................................................................................................... 35 3.5.1. Power Supply Pins ....................................................................................................... 35 3.5.2. Decrease Voltage Drop ............................................................................................... 36 3.5.3. Monitor the Power Supply ............................................................................................ 37 3.6. Turn on and off Scenarios ...................................................................................................... 37 3.6.1. Turn on Module Using the PWRKEY Pin ..................................................................... 37 3.6.2. Turn off Module ............................................................................................................ 39 3.6.2.1. Turn off Module Using the PWRKEY Pin ........................................................... 39 3.6.2.2. Turn off Module Using AT Command ................................................................ 40 3.7. Reset the Module ................................................................................................................... 40 3.8.

(U)SIM Interface ..................................................................................................................... 42 3.9. USB Interface ......................................................................................................................... 44 3.10. UART Interfaces ..................................................................................................................... 46 3.11. PCM* and I2C* Interfaces ...................................................................................................... 49 3.12. Network Status Indication ....................................................................................................... 50 3.13. STATUS ................................................................................................................................. 51 3.14. Behaviors of RI* ..................................................................................................................... 51 3.15. USB_BOOT Interface ............................................................................................................. 52 3.16. ADC Interfaces ....................................................................................................................... 53 BG95_Hardware_Design 4 / 80 LPWA Module Series BG95 Hardware Design 3.17. GPIO Interfaces ...................................................................................................................... 54 4 GNSS Receiver ................................................................................................................................ 56 4.1. General Description ................................................................................................................ 56 4.2. GNSS Performance ................................................................................................................ 56 4.3. Layout Guidelines ................................................................................................................... 57 5 Antenna Interfaces .......................................................................................................................... 58 5.1. Main Antenna Interface .......................................................................................................... 58 5.1.1. Pin Definition ................................................................................................................ 58 5.1.2. Operating Frequency ................................................................................................... 58 5.1.3. Reference Design of RF Antenna Interface ................................................................. 59 5.1.4. Reference Design of RF Layout ................................................................................... 60 5.2. GNSS Antenna Interface ........................................................................................................ 62 5.3. Antenna Installation ................................................................................................................ 63 5.3.1. Antenna Requirements ................................................................................................ 63 5.3.2. Recommended RF Connector for Antenna Installation ................................................ 64 6 Electrical, Reliability and Radio Characteristics .......................................................................... 66 6.1. Absolute Maximum Ratings .................................................................................................... 66 6.2. Power Supply Ratings ............................................................................................................ 66 6.3. Operation and Storage Temperatures .................................................................................... 67 6.4. RF Output Power .................................................................................................................... 67 6.5. RF Receiving Sensitivity ......................................................................................................... 68 6.6. Electrostatic Discharge ........................................................................................................... 69 7 Mechanical Dimensions.................................................................................................................. 71 7.1. Mechanical Dimensions of the Module ................................................................................... 71 7.2. Recommended Footprint ........................................................................................................ 73 7.3. Design Effect Drawings of the Module .................................................................................... 74 8 Storage, Manufacturing and Packaging ........................................................................................ 75 8.1. Storage ................................................................................................................................... 75 8.2. Manufacturing and Soldering .................................................................................................. 76 8.3. Packaging ............................................................................................................................... 77 9 Appendix A References .................................................................................................................. 79 10 Appendix B GPRS Coding Schemes ............................................................................................. 82 11 Appendix C GPRS Multi-slot Classes ............................................................................................ 83 12 Appendix D EDGE Modulation and Coding Schemes .................................................................. 85 BG95_Hardware_Design 5 / 80 LPWA Module Series BG95 Hardware Design Table Index TABLE 1: VERSION SELECTION FOR BG95 SERIES MODULE ................................................................... 14 TABLE 2: FREQUENCY BANDS AND GNSS TYPES OF BG95 SERIES MODULE ...................................... 14 TABLE 3: KEY FEATURES OF BG95 SERIES MODULES ............................................................................. 17 TABLE 4: DEFINITION OF I/O PARAMETERS ................................................................................................ 24 TABLE 5: PIN DESCRIPTION ........................................................................................................................... 25 TABLE 6: OVERVIEW OF OPERATING MODES ............................................................................................ 32 TABLE 7: VBAT AND GND PINS ...................................................................................................................... 36 TABLE 8: PIN DEFINITION OF PWRKEY ........................................................................................................ 38 TABLE 9: PIN DEFINITION OF RESET_N ....................................................................................................... 40 TABLE 10: PIN DEFINITION OF (U)SIM INTERFACE ..................................................................................... 42 TABLE 11: PIN DEFINITION OF USB INTERFACE ......................................................................................... 44 TABLE 12: PIN DEFINITION OF MAIN UART INTERFACE ............................................................................ 46 TABLE 13: PIN DEFINITION OF DEBUG UART INTERFACE......................................................................... 47 TABLE 14: PIN DEFINITION OF GNSS UART INTERFACE ........................................................................... 47 TABLE 15: LOGIC LEVELS OF DIGITAL I/O ................................................................................................... 47 TABLE 16: PIN DEFINITION OF PCM AND I2C INTERFACES ...................................................................... 49 TABLE 17: PIN DEFINITION OF NETLIGHT .................................................................................................... 50 TABLE 18: WORKING STATE OF NETLIGHT ................................................................................................. 50 TABLE 19: PIN DEFINITION OF STATUS ....................................................................................................... 51 TABLE 20: DEFAULT BEHAVIORS OF RI ....................................................................................................... 52 TABLE 21: PIN DEFINITION OF USB_BOOT INTERFACE............................................................................. 52 TABLE 22: PIN DEFINITION OF ADC INTERFACE ......................................................................................... 53 TABLE 23: CHARACTERISTICS OF ADC INTERFACES ................................................................................ 54 TABLE 24: PIN DEFINITION OF GPIO INTERFACES ..................................................................................... 54 TABLE 25: LOGIC LEVELS OF GPIO INTERFACES ...................................................................................... 55 TABLE 26: GNSS PERFORMANCE ................................................................................................................. 56 TABLE 27: PIN DEFINITION OF MAIN ANTENNA INTERFACE ..................................................................... 58 TABLE 28: BG95 OPERATING FREQUENCY ................................................................................................. 58 TABLE 29: PIN DEFINITION OF GNSS ANTENNA INTERFACE .................................................................... 62 TABLE 30: GNSS FREQUENCY ...................................................................................................................... 62 TABLE 31: ANTENNA REQUIREMENTS ......................................................................................................... 63 TABLE 32: ABSOLUTE MAXIMUM RATINGS ................................................................................................. 66 TABLE 33: POWER SUPPLY RATINGS .......................................................................................................... 66 TABLE 34: OPERATION AND STORAGE TEMPERATURES ......................................................................... 67 TABLE 35: BG95 RF OUTPUT POWER ........................................................................................................... 68 TABLE 36: BG95 CONDUCTED RF RECEIVING SENSITIVITY ..................................................................... 68 TABLE 37: ELECTROSTATIC DISCHARGE CHARACTERISTICS (25C, 45% RELATIVE HUMIDITY) ....... 70 TABLE 38: RECOMMENDED THERMAL PROFILE PARAMETERS .............................................................. 76 TABLE 39: REEL PACKAGING ........................................................................................................................ 78 TABLE 40: RELATED DOCUMENTS ............................................................................................................... 79 TABLE 41: TERMS AND ABBREVIATIONS ..................................................................................................... 79 BG95_Hardware_Design 6 / 80 LPWA Module Series BG95 Hardware Design TABLE 42: DESCRIPTION OF DIFFERENT CODING SCHEMES .................................................................. 82 TABLE 43: GPRS MULTI-SLOT CLASSES ...................................................................................................... 83 TABLE 44: EDGE MODULATION AND CODING SCHEMES .......................................................................... 85 BG95_Hardware_Design 7 / 80 LPWA Module Series BG95 Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 20 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 23 FIGURE 3: SLEEP MODE APPLICATION VIA UART ...................................................................................... 35 FIGURE 4: POWER SUPPLY LIMITS DURING BURST TRANSMISSION ..................................................... 36 FIGURE 5: STAR STRUCTURE OF THE POWER SUPPLY ........................................................................... 37 FIGURE 6: TURN ON THE MODULE USING DRIVING CIRCUIT ................................................................... 38 FIGURE 7: TURN ON THE MODULE USING KEYSTROKE ........................................................................... 38 FIGURE 8: TIMING OF TURNING ON MODULE ............................................................................................. 39 FIGURE 9: TIMING OF TURNING OFF MODULE ........................................................................................... 40 FIGURE 10: TIMING OF RESET MODULE ...................................................................................................... 41 FIGURE 11: REFERENCE CIRCUIT OF RESET_N BY USING DRIVING CIRCUIT ...................................... 41 FIGURE 12: REFERENCE CIRCUIT OF RESET_N BY USING BUTTON ...................................................... 41 FIGURE 13: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH AN 8-PIN (U)SIM CARD CONNECTOR

................................................................................................................................................................... 43 FIGURE 14: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH A 6-PIN (U)SIM CARD CONNECTOR 43 FIGURE 15: REFERENCE CIRCUIT OF USB INTERFACE ............................................................................ 45 FIGURE 16: REFERENCE CIRCUIT WITH TRANSLATOR CHIP ................................................................... 48 FIGURE 17: REFERENCE CIRCUIT WITH TRANSISTOR CIRCUIT .............................................................. 48 FIGURE 18: REFERENCE CIRCUIT OF PCM APPLICATION WITH AUDIO CODEC ................................... 49 FIGURE 19: REFERENCE CIRCUIT OF THE NETWORK STATUS INDICATOR .......................................... 50 FIGURE 20: REFERENCE CIRCUIT OF STATUS ........................................................................................... 51 FIGURE 21: REFERENCE CIRCUIT OF USB_BOOT INTERFACE ................................................................ 53 FIGURE 22: REFERENCE CIRCUIT OF RF ANTENNA INTERFACE ............................................................ 60 FIGURE 23: MICROSTRIP LINE DESIGN ON A 2-LAYER PCB ..................................................................... 60 FIGURE 24: COPLANAR WAVEGUIDE LINE DESIGN ON A 2-LAYER PCB ................................................. 61 FIGURE 25: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE GROUND) .................................................................................................................................................. 61 FIGURE 26: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE GROUND) .................................................................................................................................................. 61 FIGURE 27: REFERENCE CIRCUIT OF GNSS ANTENNA INTERFACE ....................................................... 63 FIGURE 28: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) ............................................... 64 FIGURE 29: MECHANICALS OF U.FL-LP CONNECTORS ............................................................................. 65 FIGURE 30: SPACE FACTOR OF MATED CONNECTOR (UNIT: MM) .......................................................... 65 FIGURE 31: MODULE TOP AND SIDE DIMENSIONS .................................................................................... 71 FIGURE 32: MODULE BOTTOM DIMENSIONS (BOTTOM VIEW) ................................................................. 72 FIGURE 33: RECOMMENDED FOOTPRINT (TOP VIEW) .............................................................................. 73 FIGURE 34: TOP VIEW OF THE MODULE ...................................................................................................... 74 FIGURE 35: BOTTOM VIEW OF THE MODULE .............................................................................................. 74 FIGURE 36: RECOMMENDED REFLOW SOLDERING THERMAL PROFILE ............................................... 76 FIGURE 37: TAPE DIMENSIONS ..................................................................................................................... 77 FIGURE 38: REEL DIMENSIONS ..................................................................................................................... 78 BG95_Hardware_Design 8 / 80 LPWA Module Series BG95 Hardware Design 1 Introduction This document defines BG95 module and describes its air interface and hardware interfaces which are connected with customers applications. This document can help customers quickly understand the interface specifications, electrical and mechanical details, as well as other related information of BG95. To facilitate its application in different fields, reference design is also provided for customers reference. Associated with application notes and user guides, customers can use the module to design and set up mobile applications easily. BG95_Hardware_Design 9 / 80 LPWA Module Series BG95 Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating BG95. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product. If not so, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be given to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If the device offers an Airplane Mode, then it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on boarding the aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signals and cellular network cannot be guaranteed to connect in all possible conditions (for example, with unpaid bills or with an invalid (U)SIM card). When emergent help is needed in such conditions, please remember using emergency call. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV set, radio, computer or other electric equipment. In locations with potentially explosive atmospheres, obey all posted signs to turn off wireless devices such as your phone or other cellular terminals. Areas with potentially explosive atmospheres include fueling areas, below decks on boats, fuel or chemical transfer or storage facilities, areas where the air contains chemicals or particles such as grain, dust or metal powders, etc. BG95_Hardware_Design 10 / 80 LPWA Module Series BG95 Hardware Design According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a 1.2. FCC Certification Requirements. mobile device. And the following conditions must be met:

1. This Modular Approval is limited to OEM installation for mobile and fixed applications only. The antenna installation and operating configurations of this transmitter, including any applicable source-based time-

averaging duty factor, antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements of 2.1091. 2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the users body and must not transmit simultaneously with any other antenna or transmitter. 3.A label with the following statements must be attached to the host end product: This device contains FCC ID: XMR2020BG95M1. 4.To comply with FCC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed:

Catm LTE Band2/25:11.000dBi Catm LTE Band4/66:8.000dBi Catm LTE Band5/26:12.541dBi Catm LTE Band12/85:11.798dBi Catm LTE Band13:12.214dBi Catm LTE Band14:12.272 dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093 BG95_Hardware_Design 11 / 80 LPWA Module Series BG95 Hardware Design configurations. If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna For this device, OEM integrators must be provided with labeling instructions of finished products. Please refer to KDB784748 D01 v07, section 8. Page 6/7 last two paragraphs:

A certified modular has the option to use a permanently affixed label, or an electronic label. For a permanently affixed label, the module must be labeled with an FCC ID - Section 2.926 (see 2.2 Certification (labeling requirements) above). The OEM manual must provide clear instructions explaining to the OEM the labeling requirements, options and OEM user manual instructions that are required (see next paragraph). For a host using a certified modular with a standard fixed label, if (1) the modules FCC ID is not visible when installed in the host, or (2) if the host is marketed so that end users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible;

then an additional permanent label referring to the enclosed module:Contains Transmitter Module FCC ID: XMR2020BG95M1 or Contains FCC ID: XMR2020BG95M1 must be used. The host OEM user manual must also contain clear instructions on how end users can find and/or access the module and the FCC ID. The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The users manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. In cases where the manual is provided only in a form other than paper, such as on a computer disk or over the Internet, the information required by this section may be included in the manual in that alternative form, provided the user can reasonably be expected to have the capability to access information in that form. BG95_Hardware_Design 12 / 80 LPWA Module Series BG95 Hardware Design This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the manufacturer could void the users authority to operate the equipment. BG95_Hardware_Design 13 / 80 LPWA Module Series BG95 Hardware Design 2 Product Concept 2.1. General Description BG95 is a series of embedded IoT (LTE Cat M1, LTE Cat NB2 and EGPRS) wireless communication module. It provides data connectivity on LTE-FDD/GPRS/EGPRS networks, and supports half-duplex operation in LTE networks. It also provides GNSS 1) and voice 2) functionality to meet customers specific application demands. Table 1: Version Selection for BG95 Series Module Version Cat M1 VoLTE GSM Cat NB2 3)/

NB1 Wi-Fi GNSS Positioning

(Optional) BG95-M1 BG95-M2*

BG95-M3*

BG95-N1*

BG95-M4 4) BG95-M5 4) BG95-MF 4) Y Y Y N Y Y Y Y Y Y N Y Y Y N Y Y Y Y Y Y N N Y N N N N N N N N N N Y Y Y Y Y Y Y Y Table 2: Frequency Bands and GNSS Types of BG95 Series Module Module Supported Bands LTE Bands Power Class GNSS (Optional) BG95-M1 Power Class 5 (20dBm) Cat M1 Only:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B14/B18/B19/B20/B25/B26*/B27/

B28/B66/B85 GPS, GLONASS, BeiDou, Galileo BG95_Hardware_Design 14 / 80 LPWA Module Series BG95 Hardware Design BG95-M2*

Power Class 5 (20dBm) GPS, GLONASS, BeiDou, Galileo Cat M1:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B14/B18/B19/B20/B25/B26*/

B27/B28/B66/B85 Cat NB2:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B18/B19/B20/B25/B26*/B28/B66/

B71/B85 Cat M1:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B14/B18/B19/B20/B25/B26*/B27/

B28/B66/B85 Cat NB2:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B18/B19/B20/B25/B26*/

B28/B66/B71/B85 EGPRS:

850/900/1800/1900MHz Cat NB2 Only:

LTE FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B18/B19/B20/B25/B26*/

B28/B66/B71/B85 Cat M1:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B14/B18/B19/B20/B25/B26/B27/

B28/B31/B66/B72/B73/B85 Cat NB2:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B18/B19/B20/B25/B26/B28/B31/

B66/B72/B73/B85 Cat M1:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B14/B18/B19/B20/B25/B26/B27/

B28/B66/B85 Cat NB2:

LTE-FDD:

BG95-M3*

Power Class 5 (20dBm) BG95-N1*

Power Class 5 (20dBm) BG95-M4 4) Power Class 5 (20dBm) GPS, GLONASS, BeiDou, Galileo GPS, GLONASS, BeiDou, Galileo GPS, GLONASS, BeiDou, Galileo GPS, GLONASS, BeiDou, Galileo BG95-M5 4) Power Class 3 (23dBm) BG95_Hardware_Design 15 / 80 LPWA Module Series BG95 Hardware Design B1/B2/B3/B4/B5/B8/B12/B13/

B18/B19/B20/B25/B26/B28/B66/

B71/B85 Cat M1:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B14/B18/B19/B20/B25/B26/B27/

B28/B66/B85 Cat NB2:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B18/B19/B20/B25/B26/

B28/B66/B71/B85 Wi-Fi (For Positioning Only):

2.4GHz/5GHz BG95-MF 4) Power Class 5 (20dBm) GPS, GLONASS, BeiDou, Galileo NOTES 1. 2. 3. 4. 5. 1) GNSS function is optional. 2) BG95 series module supports VoLTE (Voice over LTE) under LTE Cat M1 and CS voice under GSM. 3) LTE Cat NB2 is backward compatible with LTE Cat NB1. 4) BG95-M4/-M5/-MF are still under planning. Therefore, details of them are currently not included and will be added in a future release of this document.

* means under development. With a compact profile of 23.6mm 19.9mm 2.2mm, BG95 can meet almost all requirements for M2M applications such as smart metering, tracking system, security, wireless POS, etc. BG95 is an SMD type module which can be embedded into applications through its 102 LGA pads. It supports internet service protocols like TCP, UDP and PPP. Extended AT commands have been developed for customers to use these internet service protocols easily. 2.2. Key Features The following table describes the detailed features of BG95 series modules. BG95_Hardware_Design 16 / 80 LPWA Module Series BG95 Hardware Design Table 3: Key Features of BG95 Series Modules Features Details Power Supply Transmitting Power LTE Features BG95-M1/-M2/-N1:

Supply voltage: 2.4V~4.8V Typical supply voltage: 3.3V BG95-M3:

Supply voltage: 3.3V~4.3V Typical supply voltage: 3.8V Class 5 (20dBm2dB) for LTE-FDD bands Class 4 (33dBm2dB) for GSM850 Class 4 (33dBm2dB) for EGSM900 Class 1 (30dBm2dB) for DCS1800 Class 1 (30dBm2dB) for PCS1900 Class E2 (27dBm3dB) for GSM850 8-PSK Class E2 (27dBm3dB) for EGSM900 8-PSK Class E2 (26dBm3dB) for DCS1800 8-PSK Class E2 (26dBm3dB) for PCS1900 8-PSK Support LTE Cat M1 and LTE Cat NB2 Support 1.4MHz RF bandwidth for LTE Cat M1 Support 200KHz RF bandwidth for LTE Cat NB2 Support SISO in DL direction Cat M1: Max. 589Kbps (DL)/1.12Mbps (UL) Cat NB2: Max. 136Kbps (DL)/150Kbps (UL) GPRS:

Support GPRS multi-slot class 33 (33 by default) Coding scheme: CS-1, CS-2, CS-3 and CS-4 Max. 107Kbps (DL), Max. 85.6Kbps (UL) GSM Features EDGE:

Support EDGE multi-slot class 33 (33 by default) Support GMSK and 8-PSK for different MCS (Modulation and Coding Scheme) Downlink coding schemes: CS 1-4 and MCS 1-9 Uplink coding schemes: CS 1-4 and MCS 1-9 Max. 296Kbps (DL), Max. 236.8Kbps (UL) Support PPP/TCP/UDP/SSL/TLS/FTP(S)/HTTP(S)/NITZ/PING/MQTT/

CoAP protocols Support PAP (Password Authentication Protocol) and CHAP (Challenge Handshake Authentication Protocol) protocols which are usually used for PPP connections Text and PDU mode Point to point MO and MT SMS cell broadcast Internet Protocol Features*

SMS BG95_Hardware_Design 17 / 80 LPWA Module Series BG95 Hardware Design SMS storage: ME by default

(U)SIM Interface Support 1.8V USIM/SIM card Audio Feature*

Support one digital audio interface: PCM interface USB Interface UART Interfaces Compliant with USB 2.0 specification (slave only) Support operations at low-speed and full-speed Used for AT command communication, data transmission, GNSS NMEA output, software debugging and firmware upgrade Support USB serial drivers for Windows 7/8/8.1/10, Linux 2.6/3.x (3.4 or later)/4.1~4.15, Android 4.x/5.x/6.x/7.x/8.x/9.x Main UART:

Used for data transmission and AT command communication 115200bps baud rate by default The default frame format is 8N1 (8 data bits, no parity, 1 stop bit) Support RTS and CTS hardware flow control Debug UART:

Used for software debugging and log output Support 115200bps baud rate GNSS UART:

Used for GNSS data and NMEA sentences output 115200bps baud rate by default AT Commands 3GPP TS 27.007 and 3GPP TS 27.005 AT commands, as well as Quectel enhanced AT commands Network Indication One NETLIGHT pin for network connectivity status indication Antenna Interfaces Including main antenna (ANT_MAIN) and GNSS antenna (ANT_GNSS) interfaces Physical Characteristics Temperature Range Size: (23.60.15)mm (19.90.15)mm (2.20.2)mm Weight: approx. 2.15g Operation temperature range: -35C ~ +75C 1) Extended temperature range: -40C ~ +85C 2) Storage temperature range: -40C ~ +90C Firmware Upgrade USB interface, DFOTA*

All hardware components are fully compliant with EU RoHS directive RoHS NOTES BG95_Hardware_Design 18 / 80 LPWA Module Series BG95 Hardware Design 1. * means under development. 2. 1) Within operation temperature range, the module is 3GPP compliant. 3. 2) Within extended temperature range, the module remains the ability to establish and maintain a voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances. When the temperature returns to the normal operating temperature levels, the module will meet 3GPP specifications again. 2.3. Functional Diagram The following figure shows a block diagram of BG95 and illustrates the major functional parts. Power management Baseband Radio frequency Peripheral interfaces BG95_Hardware_Design 19 / 80 VBAT_RF VBAT_BB PWRKEY RESET_N ADC1 ADC0 LPWA Module Series BG95 Hardware Design ANT_MAIN ANT_GNSS SAW LNA GNSS PA

(GSM) Tx

(ASM) Rx Transceiver/PA/switch IQ Control PMIC Control Baseband 19.2M XO eSIM VDD_EXT USB

(U)SIM PCM*

UARTs I2C*

GPIOs STATUS NETLIGHT Figure 1: Functional Diagram NOTES simultaneously. 1. eSIM function is optional. If eSIM is selected, then the external (U)SIM cannot be used 2. RESET_N will be supported in the next hardware design version. 3. ADC0 and ADC1 cannot be used simultaneously. BG95 supports using of only one ADC interface at a time: either ADC0 or ADC1. Currently only ADC0 is enabled, and ADC1 will be enabled in the next hardware design version. 4. * means under development. 2.4. Evaluation Board In order to help customers to develop applications conveniently with BG95, Quectel supplies the evaluation board (EVB), USB to RS-232 converter cable, USB data cable, earphone, antenna and other BG95_Hardware_Design 20 / 80 LPWA Module Series BG95 Hardware Design peripherals to control or test the module. For more details, please refer to document [1]. BG95_Hardware_Design 21 / 80 LPWA Module Series BG95 Hardware Design 3 Application Interfaces

(U)SIM interface BG95 is equipped with 102 LGA pads that can be connected to customers cellular application platforms. The following sub-chapters will provide detailed description of interfaces listed below:

Power supply USB interface UART interfaces PCM* and I2C* interfaces Status indication USB_BOOT interface ADC interfaces GPIO interfaces NOTE

* means under development. BG95_Hardware_Design 22 / 80 LPWA Module Series BG95 Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of BG95. PSM_IND*

ADC1 1) GND PCM_CLK*

PCM_SYNC*

PCM_IN*

PCM_OUT*

USB_VBUS USB_DP USB_DM RESERVED RESERVED RESERVED RESERVED PWRKEY 2) GPIO16 RESET_N 3) W_DISABLE# *

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 I N A M _ T N A D N G D N G D N G D N G D E V R E S E R D E V R E S E R F R _ T A B V F R _ T A B V D E V R E S E R D N G D N G D N G 2 6 1 6 0 6 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 82 81 80 79 102 101 100 99 63 83 GPIO64 64 84 GPIO65 65 65 85 67 87 68 88 98 78 97 77 96 76 94 74 93 73 GPIO66 66 86 95 75 USB_BOOT 89 90 91 92 69 70 71 72 9 1 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 0 3 1 3 S U T A T S I T H G L T E N D X R _ G B D D X T _ G B D

) 1 0 C D A

Y D A E R _ P A R T D D N G T X E _ D D V 5 2 O P G I 6 2 O P G I D X T _ T R A U _ S S N G D X R _ T R A U _ S S N G 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 USIM_PRESENCE*

ANT_GNSS GND USIM_GND USIM_CLK USIM_DATA USIM_RST USIM_VDD I2C_SDA*

I2C_SCL*

RI DCD RTS CTS TXD RXD VBAT_BB VBAT_BB POWER USB UART

(U)SIM PCM ANT GND RESERVED OTHERS Figure 2: Pin Assignment (Top View) BG95_Hardware_Design 23 / 80 LPWA Module Series BG95 Hardware Design 1) ADC0 and ADC1 cannot be used simultaneously. BG95 supports using of only one ADC interface at a time: either ADC0 or ADC1. Currently only ADC0 is enabled, and ADC1 will be enabled in the next hardware design version. 2) PWRKEY output voltage is 1.5V because of the diode drop in the Qualcomm chipset. PWRKEY should never be pulled down to GND permanently. 3) RESET_N will be supported in the next hardware design version. 3. 4. Keep all RESERVED pins and unused pins unconnected. 5. GND pins should be connected to ground in the design. 6.

* means under development. 3.2. Pin Description The following tables show the pin definition and description of BG95. Table 4: Definition of I/O Parameters NOTES 1. 2. Type AI AO DI DO IO OD PI PO Description Analog Input Analog Output Digital Input Digital Output Bidirectional Open Drain Power Input Power Output BG95_Hardware_Design 24 / 80 LPWA Module Series BG95 Hardware Design Table 5: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment BG95-M1/-M2/-N1:

Vmax=4.8V Vmin=2.4V Vnorm=3.3V BG95-M3:

Vmax=4.3V Vmin=3.3V Vnorm=3.8V BG95-M1/-M2/-N1:

Vmax=4.8V Vmin=2.4V Vnorm=3.3V BG95-M3:

Vmax=4.3V Vmin=3.3V Vnorm=3.8V Vnorm=1.8V IOmax=50mA VBAT_BB 32, 33 PI Power supply for the modules baseband part VBAT_RF 52, 53 PI VDD_EXT 29 PO Power supply for the modules RF part 1.8V output power supply for external circuit GND Ground 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 67~74, 79~82, 89~91, 100~102 Turn on/off Pin Name Pin No. I/O Description DC Characteristics Comment PWRKEY 1) 15 DI Turn on/off the module Vnorm=1.5V VILmax=0.45V Power supply for external GPIOs pull-up circuits. If unused, keep this pin open. The output voltage is 1.5V because of the diode drop in the Qualcomm chipset. PWRKEY should BG95_Hardware_Design 25 / 80 LPWA Module Series BG95 Hardware Design Pin Name Pin No. I/O Description DC Characteristics Comment RESET_N 2) 17 DI VILmax=0.45V Reset the module Reset Status Indication never be pulled down to GND permanently. RESET_N will be supported in the next hardware design version. Pin Name Pin No. I/O Description DC Characteristics Comment STATUS 20 DO NETLIGHT 21 DO USB Interface Indicate the modules operation status Indicate the modules network activity status VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. Pin Name Pin No. I/O Description DC Characteristics Comment USB_VBUS 8 PI USB detection Vmax=5.25V Vmin=3.0V Vnorm=5.0V USB_DP 9 USB_DM 10

(U)SIM Interface IO IO USB differential data bus (+) USB differential data bus (-) Compliant with USB 2.0 standard specification. Require differential impedance of 90. Pin Name Pin No. I/O Description DC Characteristics Comment USIM_ PRESENCE*

42 DI

(U)SIM card insertion detection VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open. USIM_VDD 43 PO Power supply for (U)SIM card Vmax=1.9V Vmin=1.7V Only 1.8V (U)SIM card is supported. USIM_RST 44 DO Reset signal of VOLmax=0.45V BG95_Hardware_Design 26 / 80 LPWA Module Series BG95 Hardware Design

(U)SIM card VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V USIM_DATA 45 IO Data signal of

(U)SIM card USIM_CLK 46 DO Clock signal of

(U)SIM card VOLmax=0.45V VOHmin=1.35V USIM_GND 47 Main UART Interface Specified ground for

(U)SIM card Pin Name Pin No. I/O Description DC Characteristics Comment DTR 30 DI Data terminal ready (sleep mode control) RXD 34 DI Receive data TXD 35 DO Transmit data CTS 36 DO Clear to send RTS 37 DI Request to send DCD 38 DO Data carrier detection VOLmax=0.45V VOHmin=1.35V RI 39 DO Ring indication signal VOLmax=0.45V VOHmin=1.35V Debug UART Interface 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. BG95_Hardware_Design 27 / 80 LPWA Module Series BG95 Hardware Design Pin Name Pin No. I/O Description DC Characteristics Comment Pin Name Pin No. I/O Description DC Characteristics Comment DBG_RXD 22 DI Receive data DBG_TXD 23 DO Transmit data GNSS UART Interface 27 DO Transmit data 28 DI Receive data GNSS_UART_ TXD GNSS_UART_ RXD PCM Interface*

VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V PCM_CLK*

4 DO PCM_SYNC*

5 DO PCM clock output VOLmax=0.45V VOHmin=1.35V PCM frame synchronization output VOLmax=0.45V VOHmin=1.35V PCM_IN*

6 DI PCM data input VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V PCM_OUT*

7 DO PCM data output VOLmax=0.45V VOHmin=1.35V I2C Interface*

Pin Name Pin No. I/O Description DC Characteristics Comment 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. External pull-up resistor is required. 1.8V only. If unused, keep this Pin Name Pin No. I/O Description DC Characteristics Comment I2C_SCL*

40 OD I2C serial clock. Used for external codec. BG95_Hardware_Design 28 / 80 LPWA Module Series BG95 Hardware Design Pin Name Pin No. I/O Description DC Characteristics Comment Pin Name Pin No. I/O Description DC Characteristics Comment I2C_SDA*

41 OD I2C serial data. Used for external codec. IO AI Main antenna interface GNSS antenna interface Antenna Interfaces ANT_MAIN 60 ANT_GNSS 49 GPIO Interfaces GPIO16 16 IO GPIO25 25 IO GPIO26 26 IO GPIO64 64 IO General-

purpose input/

output interface General-

purpose input/

output interface General-

purpose input/

output interface General-

purpose input/

output interface VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V pin open. External pull-up resistor is required. 1.8V only. If unused, keep this pin open. 50 impedance 50 impedance. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. BG95_Hardware_Design 29 / 80 LPWA Module Series BG95 Hardware Design General-

purpose input/

output interface General-

purpose input/

output interface VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V GPIO65 65 DO GPIO66 66 DO ADC Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment ADC0 3) 24 AI Voltage range:

0.3V to 1.8V General purpose analog to digital converter interface General purpose analog to digital converter interface ADC1 3) 2 AI Voltage range:

0.3V to 1.8V Other Interface Pins Pin Name Pin No. I/O Description DC Characteristics Comment PSM_IND* 4) 1 DO Power saving mode indicator VOLmax=0.45V VOHmin=1.35V W_DISABLE#* 18 DI Airplane mode control VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. ADC0 and ADC1 cannot be used simultaneously. BG95 supports using of only one ADC interface at a time:

either ADC0 or ADC1. Currently only ADC0 is enabled, and ADC1 will be enabled in the next hardware design version 1.8V power domain. If unused, keep this pin open. 1.8V power domain. Pulled up by default. When it is in low voltage level, the module can enter into airplane mode. If unused, keep this pin open. BG95_Hardware_Design 30 / 80 LPWA Module Series BG95 Hardware Design AP_READY*

19 DI USB_BOOT 75 DI RESERVED Pins Application processor sleep state detection Force the module to enter into emergency download mode VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open. 1.8V power domain. If unused, keep this pin open. Pin Name Pin No. I/O Description DC Characteristics Comment RESERVED Reserved Keep these pins open. 11~14, 51, 56, 57, 63, 76~78, 83~88, 92~99 NOTES 1. 1) The output voltage of PWRKEY is 1.5V because of the diode drop in the Qualcomm chipset, and PWRKEY should never be pulled down to GND permanently. 2. 2) RESET_N will be supported in the next hardware design version. 3. 3) ADC0 and ADC1 cannot be used simultaneously. BG95 supports using of only one ADC interface at a time: either ADC0 or ADC1. Currently only ADC0 is enabled, and ADC1 will be enabled in the next hardware design version. 4. 4) When PSM is enabled, the function of PSM_IND* pin will be activated after the module is rebooted. When PSM_IND* is in high voltage level, the module is in normal operation state, when it is in low voltage level, the module is in PSM. 5. Keep all RESERVED pins and unused pins unconnected. 6. * means under development. 3.3. Operating Modes The table below briefly summarizes the various operating modes of BG95. BG95_Hardware_Design 31 / 80 LPWA Module Series BG95 Hardware Design Table 6: Overview of Operating Modes Mode Details Normal Operation Connected Network has been connected. In this mode, the power consumption may vary with the network setting and data transfer rate. Idle Software is active. The module remains registered on network, and it is ready to send and receive data. Extended Idle Mode DRX

(e-I-DRX) BG95 module and the network may negotiate over non-access stratum signaling the use of e-I-DRX for reducing power consumption, while being available for mobile terminating data and/or network originated procedures within a certain delay dependent on the DRX cycle value. Airplane Mode AT+CFUN=4 or W_DISABLE#* pin can set the module into airplane mode. In this case, RF function will be invalid. Minimum Functionality Mode Sleep Mode*

AT+CFUN=0 can set the module into a minimum functionality mode without removing the power supply. In this case, both RF function and (U)SIM card will be invalid. In this mode, the current consumption of the module will be reduced to a lower level. During this mode, the module can still receive paging message, SMS and TCP/UDP data from the network normally. Power Saving Mode

(PSM) BG95 module may enter into Power Saving Mode to further reduce its power consumption. PSM is similar to power-off, but the module remains registered on the network and there is no need to re-attach or re-establish PDN connections. Power OFF Mode In this mode, the power management unit shuts down the power supply. Software is not active. The serial interfaces are not accessible. But the operating voltage

(connected to VBAT_RF and VBAT_BB) remains applied. 1. During e-I-DRX, it is recommended to use UART interface for data communication, as the use of USB interface will increase power consumption. 2. * means under development. NOTES 3.4. Power Saving 3.4.1. Airplane Mode When the module enters into airplane mode, the RF function does not work, and all AT commands correlative with RF function will be inaccessible. This mode can be set via the following ways. BG95_Hardware_Design 32 / 80 LPWA Module Series BG95 Hardware Design W_DISABLE#* is pulled up by default. Driving it to low level will let the module enter into airplane mode. AT+CFUN=<fun> provides choice of the functionality level, through setting <fun> into 0, 1 or 4. AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled. AT+CFUN=1: Full functionality mode (by default). AT+CFUN=4: Airplane mode. RF function is disabled. Hardware:

Software:

NOTES 1. Airplane mode control via W_DISABLE#* is disabled in firmware by default. It can be enabled by AT+QCFG="airplanecontrol" command which is still under development. Details about the command will be provided in document [2]. 2. The execution of AT+CFUN command will not affect GNSS function. 3.

* means under development. 3.4.2. Power Saving Mode (PSM) BG95 module can enter into PSM for reducing its power consumption. The mode is similar to power-off, but the module remains registered on the network and there is no need to re-attach or re-establish PDN connections. So BG95 in PSM cannot immediately respond users requests. When the module wants to use the PSM it shall request an Active Time value during every Attach and TAU procedures. If the network supports PSM and accepts that the module uses PSM, the network confirms usage of PSM by allocating an Active Time value to the module. If the module wants to change the Active Time value, e.g. when the conditions are changed in the module, the module consequently requests the value it wants in the TAU procedure. If PSM is supported by the network, then it can be enabled via AT+CPSMS command. Either of the following methods will wake up the module from PSM:

Drive PWRKEY pin to low level will wake up the module. When the T3412_Ext timer expires, the module will be woken up automatically. The Main UART data will wake up the module and the function is under development. NOTE Please refer to document [2] for details about AT+CPSMS command. BG95_Hardware_Design 33 / 80 LPWA Module Series BG95 Hardware Design 3.4.3. Extended Idle Mode DRX (e-I-DRX) The module (UE) and the network may negotiate over non-access stratum signalling the use of e-I-DRX for reducing its power consumption, while being available for mobile terminating data and/or network originated procedures within a certain delay dependent on the DRX cycle value. Applications that want to use e-I-DRX need to consider specific handling of mobile terminating services or data transfers, and in particular they need to consider the delay tolerance of mobile terminated data. In order to negotiate the use of e-I-DRX, the UE requests e-I-DRX parameters during attach procedure and RAU/TAU procedure. The EPC may reject or accept the UE request for enabling e-I-DRX. In case the EPC accepts e-I-DRX, the EPC based on operator policies and, if available, the e-I-DRX cycle length value in the subscription data from the HSS, may also provide different values of the e-I-DRX parameters than what was requested by the UE. If the EPC accepts the use of e-I-DRX, the UE applies e-I-DRX based on the received e-I-DRX parameters. If the UE does not receive e-I-DRX parameters in the relevant accept message because the EPC rejected its request or because the request was received by EPC not supporting e-I-DRX, the UE shall apply its regular discontinuous reception. If e-I-DRX is supported by the network, then it can be enabled by AT+CEDRXS=1 command. Please refer to document [2] for details about AT+CEDRXS command. NOTE 3.4.4. Sleep Mode*

3.4.4.1. UART Application BG95 is able to reduce its current consumption to a lower value during the sleep mode. The following sub-chapters describe the power saving procedure of BG95 module. If the host communicates with module via UART interface, the following preconditions can let the module enter into sleep mode. Execute AT+QSCLK=1 command to enable sleep mode. Drive DTR to high level. The following figure shows the connection between the module and the host. BG95_Hardware_Design 34 / 80 LPWA Module Series BG95 Hardware Design Figure 3: Sleep Mode Application via UART When BG95 has URC to report, RI signal will wake up the host. Please refer to Chapter 3.14 for details about RI behavior. Driving the host DTR to low level will wake up the module. AP_READY* will detect the sleep state of the host (can be configured to high level or low level detection). Please refer to AT+QCFG="apready" command in document [2] for details. NOTE

* means under development. 3.5. Power Supply 3.5.1. Power Supply Pins BG95 provides the following four VBAT pins for connection with an external power supply. There are two separate voltage domains for VBAT. Two VBAT_RF pins for modules RF part. Two VBAT_BB pins for modules baseband part. The following table shows the details of VBAT pins and ground pins. BG95_Hardware_Design 35 / 80 LPWA Module Series BG95 Hardware Design Table 7: VBAT and GND Pins Pin Name Pin No. Description Module Min. Typ. Max. Unit VBAT_RF 52, 53 VBAT_BB 32, 33 Power supply for the modules RF part Power supply for the modules baseband part BG95-M1/-M2/-N1 2.4 3.3 4.8 BG95-M3 3.3 3.8 4.3 BG95-M1/-M2/-N1 2.4 3.3 4.8 BG95-M3 3.3 3.8 4.3 V V V V GND Ground

3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 67~74, 79~82, 89~91, 100~102 3.5.2. Decrease Voltage Drop BG95-M1/-M2/-N1: The power supply range of BG95-M1/-M2/-N1 is from 2.4V to 4.8V. Please make sure that the input voltage will never drop below 2.4V. BG95-M3: The power supply range of the BG95-M3 is from 3.3V to 4.3V. Please make sure that the input voltage will never drop below 3.3V. The following figure shows the voltage drop during burst transmission in 2G network of BG95-M3 module. The voltage drop will be less in LTE Cat M1 and/or LTE Cat NB2 networks. Burst Transmission Burst Transmission VBAT Min.3.3V Drop Ripple Figure 4: Power Supply Limits during Burst Transmission To decrease voltage drop, a bypass capacitor of about 100F with low ESR should be used, and a multi-layer ceramic chip capacitor (MLCC) array should also be reserved due to its low ESR. It is recommended to use three ceramic capacitors (100nF, 33pF, 10pF) for composing the MLCC array, and place these capacitors close to VBAT pins. The main power supply from an external application has to be BG95_Hardware_Design 36 / 80

LPWA Module Series BG95 Hardware Design a single voltage source and can be expanded to two sub paths with star structure. The width of VBAT_BB trace should be no less than 0.5mm, and the width of VBAT_RF trace should be no less than 2mm. In principle, the longer the VBAT trace is, the wider it will be. In addition, in order to get a stable power source, it is suggested to use a TVS with low leakage current and suitable reverse stand-off voltage, and also it is recommended to place it as close to the VBAT pins as possible. The following figure shows the star structure of the power supply. VBAT

C 1 D1 TVS C2 C3 C4 C5 C6 C7 C8 100uF 100nF 33pF 10pF 100uF 100nF 33pF 10pF VBAT_RF VBAT_BB Module Figure 5: Star Structure of the Power Supply 3.5.3. Monitor the Power Supply AT+CBC* command can be used to monitor the VBAT_BB voltage value. For more details, please refer to document [2]. NOTE

* means under development. 3.6. Turn on and off Scenarios 3.6.1. Turn on Module Using the PWRKEY Pin The following table shows the pin definition of PWRKEY. BG95_Hardware_Design 37 / 80 LPWA Module Series BG95 Hardware Design Table 8: Pin Definition of PWRKEY Pin Name Pin No. Description DC Characteristics Comment PWRKEY 15 Turn on/off the module Vnorm=1.5V VILmax=0.45V The output voltage is 1.5V because of the diode drop in the Qualcomm chipset. When BG95 is in power off mode, it can be turned on to normal mode by driving the PWRKEY pin to a low level for a duration between 500ms and 1000ms. It is recommended to use an open drain/collector driver to control the PWRKEY. A simple reference circuit is illustrated in the following figure. 500ms~1000ms Turn on pulse 4.7K PWRKEY 10nF 47K Figure 6: Turn on the Module Using Driving Circuit Another way to control the PWRKEY is using a button directly. When pressing the key, electrostatic strike may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the button for ESD protection. A reference circuit is shown in the following figure. Figure 7: Turn on the Module Using Keystroke The turn on scenario is illustrated in the following figure. BG95_Hardware_Design 38 / 80 LPWA Module Series BG95 Hardware Design NOTE VBA T 500ms~1000ms PWRKEY VIL0.45V RESET_N STATUS

(DO) TBD Typ. 2s Typ. 2s USB Inactive Active UART Inactive Active Figure 8: Timing of Turning on Module NOTES than 30ms. 1. Make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no less 2. PWRKEY is internally pulled up to an internal voltage in the Qualcomm chipset, and its output voltage is the internal voltage minus a diode drop in the chipset. Therefore, the expected output voltage of PWRKEY is 1.5V. 3. PWRKEY should never be pulled down to GND permanently. 3.6.2. Turn off Module Either of the following methods can be used to turn off the module:

Normal power down procedure: Turn off the module using the PWRKEY pin. Normal power down procedure: Turn off the module using AT+QPOWD command. 3.6.2.1. Turn off Module Using the PWRKEY Pin Driving the PWRKEY pin to a low level voltage for a duration between 650ms and 1500ms, the module will execute power-down procedure after the PWRKEY is released. BG95_Hardware_Design 39 / 80 LPWA Module Series BG95 Hardware Design The power-down scenario is illustrated in the following figure. 650ms~150 0ms TBD VIL0.45V VBA T PWRKEY STATUS Module Status RUNNING Power-down procedure OFF Figure 9: Timing of Turning off Module 3.6.2.2. Turn off Module Using AT Command It is also a safe way to use AT+QPOWD command to turn off the module, which is similar to turning off the module via PWRKEY pin. Please refer to document [2] for details about AT+QPOWD command. 3.7. Reset the Module RESET_N is used to reset the module and will be supported in the next hardware design version. The module can be reset by driving RESET_N to a low level voltage for a duration between 2s and 3.8s. Table 9: Pin Definition of RESET_N Pin Name Pin No. Description DC Characteristics Comment RESET_N 17 Reset the module VILmax=0.45V The reset scenario is illustrated in the following figure. RESET_N will be supported in the next hardware design version. BG95_Hardware_Design 40 / 80 LPWA Module Series BG95 Hardware Design 3.8s VIL0.45V VBA T RESET_N 2s Module Status Running Resetting Restart Figure 10: Timing of Reset Module The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET_N pin. RESET_N 2s~3.8s Reset pulse 4.7K 47K Figure 11: Reference Circuit of RESET_N by Using Driving Circuit S2 TVS RESET_N Close to S2 Figure 12: Reference Circuit of RESET_N by Using Button BG95_Hardware_Design 41 / 80 LPWA Module Series BG95 Hardware Design NOTE Please assure that there is no large capacitance on RESET_N pin. 3.8. (U)SIM Interface The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. BG95 supports 1.8V (U)SIM card only. Table 10: Pin Definition of (U)SIM Interface Pin Name Pin No. I/O Description Comment USIM_ PRESENCE*

42 DI

(U)SIM card insertion detection USIM_VDD 43 PO Power supply for (U)SIM card USIM_RST 44 DO Reset signal of (U)SIM card USIM_DATA 45 IO Data signal of (U)SIM card USIM_CLK 46 DO Clock signal of (U)SIM card USIM_GND 47 Specified ground for (U)SIM card Only 1.8V (U)SIM card is supported. BG95 supports (U)SIM card hot-plug via the USIM_PRESENCE* pin. The function supports low level and high level detections, and is disabled by default. Please refer to document [2] about AT+QSIMDET*

command for details. The following figure shows a reference design of (U)SIM interface with an 8-pin (U)SIM card connector. BG95_Hardware_Design 42 / 80 LPWA Module Series BG95 Hardware Design Figure 13: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_PRESENCE* unconnected. A reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure. Figure 14: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector In order to enhance the reliability and availability of the (U)SIM card in applications, please follow the criteria below in (U)SIM circuit design:

Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace length as less than 200mm as possible. Keep (U)SIM card signals away from RF and VBAT traces. BG95_Hardware_Design 43 / 80 LPWA Module Series BG95 Hardware Design Assure the ground between the module and the (U)SIM card connector short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5mm to maintain the same electric potential. Make sure the bypass capacitor between USIM_VDD and USIM_GND less than 1uF, and place it as close to (U)SIM card connector as possible. If the system ground plane is complete, USIM_GND can be connected to the system ground directly. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with surrounded ground. USIM_RST should also be ground shielded. In order to offer good ESD protection, it is recommended to add a TVS diode array with parasitic capacitance not exceeding 15pF. In order to facilitate debugging, it is recommended to reserve series resistors for the (U)SIM signals of the module. The 33pF capacitors are used for filtering interference of GSM 900MHz. Please note that the (U)SIM peripheral circuit should be close to the

(U)SIM card connector. The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace and sensitive occasion are applied, and should be placed close to the (U)SIM card connector. NOTE

* means under development. 3.9. USB Interface BG95 contains one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0 specification and supports low-speed (1.5Mbps) and full-speed (12Mbps) modes. The USB interface is used for AT command communication, data transmission, software debugging and firmware upgrade. The following table shows the pin definition of USB interface. Table 11: Pin Definition of USB Interface Pin Name Pin No. I/O Description Comment USB_VBUS PI USB connection detection Typically 5.0V IO USB differential data bus (+) IO USB differential data bus (-) Require differential impedance of 90 8 9 10 3 USB_DP USB_DM GND Ground For more details about USB 2.0 specification, please visit http://www.usb.org/home. BG95_Hardware_Design 44 / 80 LPWA Module Series BG95 Hardware Design The USB interface is recommended to be reserved for firmware upgrade in customers designs. The following figure shows a reference circuit of USB interface. Figure 15: Reference Circuit of USB Interface A common mode choke L1 is recommended to be added in series between the module and customers MCU in order to suppress EMI spurious transmission. Meanwhile, the 0 resistors (R3 and R4) should be added in series between the module and the test points so as to facilitate debugging, and the resistors are not mounted by default. In order to ensure the integrity of USB data line signal, L1/R3/R4 components must be placed close to the module, and also these resistors should be placed close to each other. The extra stubs of trace must be as short as possible. The following principles should be complied with when design the USB interface, so as to meet USB 2.0 specification. It is important to route the USB signal traces as differential pairs with total grounding. The impedance of USB differential trace is 90. Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is important to route the USB differential traces in inner-layer with ground shielding on not only upper and lower layers but also right and left sides. Pay attention to the influence of junction capacitance of ESD protection components on USB data lines. Typically, the capacitance value should be less than 2pF. Keep the ESD protection components as close to the USB connector as possible. NOTE BG95 module can only be used as a slave device. BG95_Hardware_Design 45 / 80 LPWA Module Series BG95 Hardware Design 3.10. UART Interfaces The module provides three UART interfaces: Main UART, Debug UART and GNSS UART interfaces. Features of them are illustrated below:

The Main UART interface supports 9600bps, 19200bps, 38400bps, 57600bps, 115200bps, 230400bps, 460800bps and 921600bps baud rates, and the default is 115200bps. It is used for data transmission and AT command communication, and supports RTS and CTS hardware flow control. The default frame format is 8N1 (8 data bits, no parity, 1 stop bit). The Debug UART interface supports a fixed baud rate of 115200bps, and is used for software The GNSS UART interface supports 115200bps baud rate by default, and is used for GNSS data and debugging and log output. NMEA sentences output. The following tables show the pin definition of the three UART interfaces. Table 12: Pin Definition of Main UART Interface Pin Name Pin No. I/O Description Comment 30 34 35 36 37 38 39 DI DI DO DO DI DO DO Data terminal ready. Sleep mode control 1.8V power domain Receive data 1.8V power domain Transmit data 1.8V power domain Clear to send 1.8V power domain Request to send 1.8V power domain Data carrier detection 1.8V power domain Ring indication signal 1.8V power domain AT+IPR command can be used to set the baud rate of the Main UART interface, and AT+IFC command can be used to set the hardware flow control (hardware flow control is disabled by default). Please refer to document [2] for more details about these AT commands. DTR RXD TXD CTS RTS DCD RI NOTE BG95_Hardware_Design 46 / 80 LPWA Module Series BG95 Hardware Design Table 13: Pin Definition of Debug UART Interface Pin Name Pin No. I/O Description Comment DBG_RXD DBG_TXD 22 23 DI DO Receive data 1.8V power domain Transmit data 1.8V power domain Table 14: Pin Definition of GNSS UART Interface Pin Name Pin No. I/O Description Comment GNSS_UART_TXD 27 DO Transmit data 1.8V power domain GNSS_UART_RXD 28 DI Receive data 1.8V power domain The logic levels of UART interfaces are described in the following table. Table 15: Logic Levels of Digital I/O Parameter VIL VIH VOL VOH Min.

-0.3 1.2 0 1.35 Max. 0.6 2.0 0.45 1.8 Unit V V V V The module provides 1.8V UART interface. A level translator should be used if customers application is equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments is recommended. The following figure shows a reference design of the Main UART interface:

BG95_Hardware_Design 47 / 80 LPWA Module Series BG95 Hardware Design VDD_EXT VCCA VCCB 0.1uF VDD_MCU 0.1uF 1 0 K 120K RI DCD CTS RTS DTR TXD RXD OE A1 A2 A3 A4 A5 A6 A7 A8 Translator GND B1 B2 B3 B4 B5 B6 B7 B8 51K 51K RI_MCU DCD_MCU CTS_MCU RTS_MCU DTR_MCU TXD_MCU RXD_MCU Figure 16: Reference Circuit with Translator Chip Please visit http://www.ti.com for more information. Another example with transistor translation circuit is shown as below. The circuit design of dotted line section can refer to that of solid line section, in terms of both module input and output circuit designs, but please pay attention to the direction of connection. Figure 17: Reference Circuit with Transistor Circuit NOTE Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps. BG95_Hardware_Design 48 / 80 LPWA Module Series BG95 Hardware Design 3.11. PCM* and I2C* Interfaces BG95 provides one Pulse Code Modulation (PCM) digital interface and one I2C interface. The following table shows the pin definition of the two interfaces which can be applied on audio codec design. Table 16: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Description Comment PCM_CLK*

4 DO PCM clock output 1.8V power domain PCM_SYNC*

5 DO 1.8V power domain PCM frame synchronization output PCM_IN*

DI PCM data input 1.8V power domain PCM_OUT*

DO PCM data output 1.8V power domain I2C_SCL*

OD I2C serial clock Require external pull-up to 1.8V I2C_SDA*

OD I2C serial data Require external pull-up to 1.8V The following figure shows a reference design of PCM and I2C interfaces with an external codec IC. 6 7 40 41 Figure 18: Reference Circuit of PCM Application with Audio Codec NOTE

* means under development. BG95_Hardware_Design 49 / 80 LPWA Module Series BG95 Hardware Design 3.12. Network Status Indication BG95 provides one network status indication pin: NETLIGHT. The pin is used to drive a network status indication LED. The following tables describe the pin definition and logic level changes of NETLIGHT in different network activity status. Table 17: Pin Definition of NETLIGHT Pin Name Pin No. I/O Description Comment NETLIGHT 21 DO Indicate the modules network activity status 1.8V power domain Table 18: Working State of NETLIGHT Pin Name Logic Level Changes Network Status Flicker slowly (200ms High/1800ms Low) Network searching NETLIGHT Flicker slowly (1800ms High/200ms Low) Idle Flicker quickly (125ms High/125ms Low) Data transfer is ongoing Always high Voice calling A reference circuit is shown in the following figure. Figure 19: Reference Circuit of the Network Status Indicator BG95_Hardware_Design 50 / 80 LPWA Module Series BG95 Hardware Design 3.13. STATUS The STATUS pin is used to indicate the operation status of BG95 module. It will output high level when the module is powered on. The following table describes the pin definition of STATUS. Table 19: Pin Definition of STATUS Pin Name Pin No. I/O Description Comment STATUS 20 DO Indicate the modules operation status 1.8V power domain The following figure shows a reference circuit of STATUS. Figure 20: Reference Circuit of STATUS 3.14. Behaviors of RI*

AT+QCFG="risignaltype","physical" command can be used to configure RI behavior. No matter on which port URC is presented, URC will trigger the behavior of RI pin. The default behaviors of RI are shown as below. BG95_Hardware_Design 51 / 80 LPWA Module Series BG95 Hardware Design Table 20: Default Behaviors of RI Response RI keeps in high level. State Idle URC NOTES RI outputs 120ms low pulse when new URC returns. The default RI behaviors can be configured flexibly by AT+QCFG=urc/ri/ring command. For more details about AT+QCFG*, please refer to document [2]. 1. URC can be outputted from UART port, USB AT port and USB modem port, through configuration via AT+QURCCFG command. The default port is USB AT port. 2. * means under development. 3.15. USB_BOOT Interface BG95 provides a USB_BOOT pin. During development or factory production, USB_BOOT can force the module to boot from USB port for firmware upgrade. Table 21: Pin Definition of USB_BOOT Interface Pin Name Pin No. I/O Description Comment USB_BOOT 75 DI Force the module to enter into emergency download mode The following figure shows a reference circuit of USB_BOOT interface. 1.8V power domain. Active high. If unused, keep it open. BG95_Hardware_Design 52 / 80 LPWA Module Series BG95 Hardware Design Figure 21: Reference Circuit of USB_BOOT Interface NOTE It is recommended to reserve the above circuit design during application design. 3.16. ADC Interfaces The module provides two analog-to-digital converter (ADC) interfaces but only one ADC interface can be used for each time. AT+QADC=0 command can be used to read the voltage value on the ADC being used. For more details about the AT command, please refer to document [2]. In order to improve the accuracy of ADC voltage values, the trace of ADC should be surrounded by ground. Table 22: Pin Definition of ADC Interface Pin Name Pin No. Description ADC0 ADC1 24 2 ADC0 and ADC1 cannot be used simultaneously. Currently only ADC0 is enabled, and ADC1 will be enabled in the next hardware design version. The following table describes the characteristics of ADC interfaces. BG95_Hardware_Design 53 / 80 LPWA Module Series BG95 Hardware Design Table 23: Characteristics of ADC Interfaces Parameter Min. Typ. Max. ADC0/ADC1 Voltage Range 0.3 ADC0/ADC1 Resolution ADC0/ADC1 Sampling Rate 1.8 64.979 4.8 Unit V uV MHz NOTES 1. ADC0 and ADC1 cannot be used simultaneously. BG95 supports using of only one ADC interface at a time: either ADC0 or ADC1. Currently only ADC0 is enabled, and ADC1 will be enabled in the next hardware design version. 2. ADC input voltage must not exceed 1.8V. 3. 4. It is prohibited to supply any voltage to ADC pin when VBAT is removed. It is recommended to use resistor divider circuit for ADC application, and the divider resistor accuracy should be no less than 1%. 3.17. GPIO Interfaces The module provides six general-purpose input and output (GPIO) interfaces. AT+QCFG="gpio"*

command can be used to configure corresponding GPIO pins status. For more details about the AT command, please refer to document [2]. Table 24: Pin Definition of GPIO Interfaces Pin Name Pin No. Description GPIO16 GPIO25 GPIO26 GPIO64 GPIO65 GPIO66 16 25 26 64 65 66 General-purpose input and output interface General-purpose input and output interface General purpose input and output interface General purpose input and output interface General purpose input and output interface General purpose input and output interface BG95_Hardware_Design 54 / 80 LPWA Module Series BG95 Hardware Design The following table describes the characteristics of GPIO interfaces. Table 25: Logic Levels of GPIO Interfaces Parameter Min.

-0.3 1.2 0 1.35 Max. 0.6 2.0 0.45 1.8 Unit V V V V VIL VIH VOL VOH NOTE

* means under development. BG95_Hardware_Design 55 / 80 LPWA Module Series BG95 Hardware Design 4 GNSS Receiver 4.1. General Description BG95 includes a fully integrated global navigation satellite system solution that supports Gen9 VT of Qualcomm (GPS, GLONASS, BeiDou and Galileo). BG95 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via USB interface by default. By default, BG95 GNSS engine is switched off. It has to be switched on via AT command. For more details about GNSS engine technology and configurations, please refer to document [3]. 4.2. GNSS Performance The following table shows the GNSS performance of BG95. Table 26: GNSS Performance Parameter Description Conditions Sensitivity

(GNSS) TTFF

(GNSS) Cold start Autonomous Reacquisition Autonomous Tracking Autonomous Cold start

@open sky Warm start

@open sky Autonomous XTRA enabled Autonomous XTRA enabled Typ. TBD TBD TBD TBD TBD TBD TBD Unit dBm dBm dBm s s s s BG95_Hardware_Design 56 / 80 LPWA Module Series BG95 Hardware Design Hot start

@open sky CEP-50 Autonomous XTRA enabled Autonomous

@open sky TBD TBD TBD s s m Accuracy

(GNSS) NOTES 1. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes. 2. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can fix position again within 3 minutes after loss of lock. 3. Cold start sensitivity: the lowest GNSS signal value at the antenna port on which the module fixes position within 3 minutes after executing cold start command. 4.3. Layout Guidelines The following layout guidelines should be taken into account in customers designs. Maximize the distance between GNSS antenna and main antenna. Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar should be kept away from the antennas. isolation and protection. Keep 50 characteristic impedance for the ANT_GNSS trace. Please refer to Chapter 5 for GNSS antenna reference design and antenna installation information. BG95_Hardware_Design 57 / 80 LPWA Module Series BG95 Hardware Design 5 Antenna Interfaces BG95 includes a main antenna interface and a GNSS antenna interface. The antenna ports have an impedance of 50. 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of main antenna interface is shown below. Table 27: Pin Definition of Main Antenna Interface 5.1.2. Operating Frequency Table 28: BG95 Operating Frequency Pin Name Pin No. I/O Description Comment ANT_MAIN 60 IO Main antenna interface 50 characteristic impedance 3GPP Band Transmit Receive LTE-FDD B1 1920~1980 2110~2170 LTE-FDD B2, PCS1900 1850~1910 1930~1990 LTE-FDD B3, DCS1800 1710~1785 1805~1880 LTE-FDD B4 1710~1755 2110~2155 LTE-FDD B5, GSM850 824~849 LTE-FDD B8, EGSM900 880~915 LTE-FDD B12 699~716 869~894 925~960 729~746 Unit MHz MHz MHz MHz MHz MHz MHz BG95_Hardware_Design 58 / 80 LPWA Module Series BG95 Hardware Design MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 777~787 788~798 815~830 830~845 832~862 807~824 703~748 663~698 698~716 746~756 758~768 860~875 875~890 791~821 859~894 852~869 758~803 617~652 728~746 LTE-FDD B25 1850~1915 1930~1995 LTE-FDD B26*

814~849 LTE-TDD B66 1710~1780 2110~2200 LTE-FDD B13 LTE-FDD B14 1) LTE-FDD B18 LTE-FDD B19 LTE-FDD B20 LTE-FDD B27 1) LTE-FDD B28 LTE-TDD B71 2) LTE-TDD B85 NOTES 1. 1) LTE-FDD B14 and B27 are supported by Cat M1 only. 2. 2) LTE-FDD B71 is supported by Cat NB2 only. 3. * means under development. 5.1.3. Reference Design of RF Antenna Interface A reference design of main antenna pad is shown as below. A -type matching circuit should be reserved for better RF performance, and the -type matching components (R1/C1/C2) should be placed as close to the antenna as possible. The capacitors are not mounted by default. BG95_Hardware_Design 59 / 80 LPWA Module Series BG95 Hardware Design Figure 22: Reference Circuit of RF Antenna Interface 5.1.4. Reference Design of RF Layout For users PCB, the characteristic impedance of all RF traces should be controlled as 50. The impedance of the RF traces is usually determined by the trace width (W), the materials dielectric constant, the distance between signal layer and reference ground (H), and the clearance between RF trace and ground (S). Microstrip line or coplanar waveguide line is typically used in RF layout for characteristic impedance control. The following are reference designs of microstrip line or coplanar waveguide line with different PCB structures. Figure 23: Microstrip Line Design on a 2-layer PCB BG95_Hardware_Design 60 / 80 LPWA Module Series BG95 Hardware Design Figure 24: Coplanar Waveguide Line Design on a 2-layer PCB Figure 25: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 26: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground) BG95_Hardware_Design 61 / 80 LPWA Module Series BG95 Hardware Design In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:

Use impedance simulation tool to control the characteristic impedance of RF traces as 50. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground. The distance between the RF pins and the RF connector should be as short as possible, and all the right angle traces should be changed to curved ones. There should be clearance area under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be no less than two times the width of RF signal traces (2*W). For more details about RF layout, please refer to document [4]. 5.2. GNSS Antenna Interface The following tables show the pin definition and frequency specification of GNSS antenna interface. Table 29: Pin Definition of GNSS Antenna Interface Pin Name Pin No. I/O Description Comment ANT_GNSS 49 AI GNSS antenna interface 50 impedance Type GPS Galileo BeiDou Table 30: GNSS Frequency GLONASS 1597.5~1605.8 Frequency 1575.421.023 1575.422.046 1561.0982.046 Unit MHz MHz MHz MHz A reference design of GNSS antenna interface is shown as below. BG95_Hardware_Design 62 / 80 LPWA Module Series BG95 Hardware Design 1. An external LDO can be selected to supply power according to the active antenna requirement. 2. If the module is designed with a passive antenna, then the VDD circuit is not needed. Figure 27: Reference Circuit of GNSS Antenna Interface NOTES GNSS 1) LTE/GSM 5.3. Antenna Installation 5.3.1. Antenna Requirements The following table shows the requirements on main antenna and GNSS antenna. Table 31: Antenna Requirements Antenna Type Requirements Frequency range: 1559MHz ~1609MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0dBi Active antenna noise figure: < 1.5dB Active antenna gain: > 0dBi Active antenna embedded LNA gain: < 17dB VSWR: 2 Efficiency: > 30%

Max Input Power (W): 50 Input Impedance (): 50 BG95_Hardware_Design 63 / 80 LPWA Module Series BG95 Hardware Design Cable Insertion Loss: < 1dB

(LTE B5/B8/B12/B13/B14 2)/B18/B19/B20/B26*/B27 2)/B28/B71 3)/ B85, GSM850/EGSM900) Cable Insertion Loss: < 1.5dB

(LTE B1/B2/B3/B4/B25/B66, DCS1800/PCS1900) NOTES 1. 1) It is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use of active antenna may generate harmonics which will affect the GNSS performance. 2. 2) LTE-FDD B14 and B27 are supported by Cat M1 only. 3. 3) LTE-FDD B71 is supported by Cat NB2 only. 4. * means under development. 5.3.2. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector provided by HIROSE. Figure 28: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. BG95_Hardware_Design 64 / 80 LPWA Module Series BG95 Hardware Design Figure 29: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector. Figure 30: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com. BG95_Hardware_Design 65 / 80 LPWA Module Series BG95 Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 32: Absolute Maximum Ratings Parameter VBAT_BB VBAT_RF USB_VBUS Voltage at Digital Pins Min.

-0.5

-0.3

-0.3

-0.3 6.2. Power Supply Ratings Table 33: Power Supply Ratings Max. Unit 6.0 6.0 5.5 2.3 V V V V Parameter Description Conditions Module Min. Typ. Max. Unit VBAT VBAT_BB/

VBAT_RF The actual input voltages must stay between the minimum and maximum values. BG95-M1/

BG95-M2/

BG95-N1 BG95-M3 3.3 3.8 4.3 2.4 3.3 4.8 V IVBAT Peak supply Maximum power BG95-M3 1.8 2.0 V A BG95_Hardware_Design 66 / 80 LPWA Module Series BG95 Hardware Design current (during transmission slot) control level on EGSM900 USB_VBUS USB detection 3.0 5.0 5.25 V BG95-M1/

BG95-M2/

BG95-N1/

BG95-M3 6.3. Operation and Storage Temperatures The operation and storage temperatures of the module are listed in the following table. Table 34: Operation and Storage Temperatures Parameter Min. Max. Unit Operation Temperature Range 1)

-35 Extended Temperature Range 2)

-40 Storage Temperature Range

-40 Typ.

+25

+75

+85

+90 C C C NOTES 1. 2. 1) Within operation temperature range, the module is 3GPP compliant. 2) Within extended temperature range, the module remains the ability to establish and maintain a voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances. When the temperature returns to the normal operating temperature levels, the module will meet 3GPP specifications again. 6.4. RF Output Power The following table shows the RF output power of BG95. BG95_Hardware_Design 67 / 80 LPWA Module Series BG95 Hardware Design Table 35: BG95 RF Output Power Frequency Max. Min. LTE-FDD B1/B2/B3/B4/B5/B8/B12/B13/B14 1)/B18/B19/B20/B25/

B26*/B27 1)/B28/B66/B71 2)/B85 20dBm2dB

<-39dBm GSM850/EGSM900 DCS1800/PCS1900 33dBm2dB 5dBm5dB 30dBm2dB 0dBm5dB GSM850/EGSM900 (8-PSK) 27dBm3dB 5dBm5dB DCS1800/PCS1900 (8-PSK) 26dBm3dB 0dBm5dB NOTES 1. 2. 3. 1) LTE-FDD B14 and B27 are supported by Cat M1 only. 2) LTE-FDD B71 is supported by Cat NB2 only.

* means under development. 6.5. RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of BG95. Table 36: BG95 Conducted RF Receiving Sensitivity Network Band Primary Diversity LTE-FDD B1 LTE-FDD B2 LTE-FDD B3 LTE-FDD B5 LTE-FDD B8 LTE-FDD B12 Sensitivity (dBm) Cat M1/3GPP Cat NB2 1)/3GPP TBD/-102.7 TBD/-107.5 TBD /-100.3 TBD/-107.5 TBD /-99.3 TBD/-107.5 TBD /-100.8 TBD/-107.5 TBD /-99.8 TBD/-107.5 TBD /-99.3 TBD/-107.5 LTE LTE-FDD B4 Supported TBD /-102.3 TBD/-107.5 Not Supported BG95_Hardware_Design 68 / 80 LPWA Module Series BG95 Hardware Design LTE-FDD B13 LTE-FDD B14 LTE-FDD B18 LTE-FDD B19 LTE-FDD B20 LTE-FDD B25 LTE-FDD B26*

LTE-FDD B27 LTE-FDD B28 LTE-FDD B66 LTE-FDD B71 LTE-FDD B85 TBD /-99.3 TBD/-107.5 TBD /-99.3

TBD /-102.3 TBD/-107.5 TBD /-102.3 TBD/-107.5 TBD /-99.8 TBD/-107.5 TBD /-100.3 TBD/-107.5 TBD /-100.3 TBD/-107.5 TBD /-100.8

TBD /-100.8 TBD/-107.5 TBD

TBD TBD/-107.5 TBD/-107.5 TBD/-107.5 Sensitivity (dBm) GSM/3GPP TBD/-102 TBD/-102 Network Band Primary Diversity GSM GSM850/EGSM900 DCS1800/PCS1900 Supported Not Supported NOTES 1. 1) LTE Cat NB2 receiving sensitivity without repetitions. 2. * means under development. 6.6. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. The following table shows the electrostatic discharge characteristics of BG95 module. BG95_Hardware_Design 69 / 80 LPWA Module Series BG95 Hardware Design Table 37: Electrostatic Discharge Characteristics (25C, 45% Relative Humidity) Tested Points Contact Discharge Air Discharge Unit VBAT, GND Main/GNSS Antenna Interfaces TBD TBD TBD TBD kV kV BG95_Hardware_Design 70 / 80 LPWA Module Series BG95 Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm, and the tolerances for dimensions without tolerance values are 0.05mm. 7.1. Mechanical Dimensions of the Module 19.900.15 2.20.2 Pin 1 5 1

. 0 0 6

. 3 2 Figure 31: Module Top and Side Dimensions BG95_Hardware_Design 71 / 80 LPWA Module Series BG95 Hardware Design 19.900.15 7.15 7.45 0.20 1.10 0.55 1.95 1.10 5.10 1.00 0 5

. 8 0.85 1.70 5 1

. 0 0 6

. 3 2 1.00 1.00 0.20 Pin 1 1.90 1.10 1.00 1.70 1.00 1.70 0.70 0.50 0.20 0.55 1.15 0.20 40x1.0 62x0.7 40x1.0 62x1.15 Figure 32: Module Bottom Dimensions (Bottom View) BG95_Hardware_Design 72 / 80 LPWA Module Series BG95 Hardware Design 7.2. Recommended Footprint 19.900.15 9.18 7.45 9.18 7.15 1.00 1.00 Pin 1 1.10 1.95 0.55 1.10 0.20 2.55 2.55 5.10 0.20 5 1

. 0 0 6

. 3 2 0.15 1.90 1.10 1.00 1.70 0.85 0 5

. 8 0.85 0.85 0.85 1.00 0 7 1

. 5 2

. 4 5 2 4

. 5 6 7

. 5 9 5

. 5 9

. 5 5 6 7

. 3 0 1 1

. 0 7 9

. 0 6

. 9 3 0

. 1 1 0.50 0.70 1.70 1.00 0.20 1.15 0.55 0.20 4.25 5.95 4.25 5.95 62x0.7 40x1.0 62x1.15 40x1.0 Figure 33: Recommended Footprint (Top View) NOTES 1. For easy maintenance of the module, please keep about 3mm between the module and other components on the host PCB. 2. All reserved pins must be kept open. 3. For stencil design requirements of the module, please refer to document [5]. BG95_Hardware_Design 73 / 80 LPWA Module Series BG95 Hardware Design 7.3. Design Effect Drawings of the Module Figure 34: Top View of the Module Figure 35: Bottom View of the Module NOTE These are renderings of BG95 module. For authentic appearance, please refer to the module that you receive from Quectel. BG95_Hardware_Design 74 / 80 LPWA Module Series BG95 Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage BG95 is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are listed below. 1. Shelf life in the vacuum-sealed bag: 12 months at <40C/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be:

Mounted within 168 hours at the factory environment of 30C/60%RH. Stored at <10%RH. 3. Devices require baking before mounting, if any circumstance below occurs. When the ambient temperature is 23C5C and the humidity indication card shows the humidity is >10% before opening the vacuum-sealed bag. Device mounting cannot be finished within 168 hours at factory conditions of 30C/60% RH. If baking is required, devices may be baked for 8 hours at 120C5C. As the plastic package cannot be subjected to high temperature, it should be removed from devices before high temperature (120C) baking. to IPC/JEDECJ-STD-033 for baking procedure. is desired, please refer If shorter baking time 4. NOTE BG95_Hardware_Design 75 / 80 LPWA Module Series BG95 Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.13mm~0.15mm. For more details, please refer to document [5]. It is suggested that the peak reflow temperature is 238~245C, and the absolute maximum reflow temperature is 245C. To avoid damage to the module caused by repeated heating, it is strongly recommended that the module should be mounted after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. Temp. (C) 245 238 220 200 150 100 Soak Zone A Max slope: 1~3C/sec Reflow Zone Max slope:

2~3C/sec C Cooling down slope: 1~4C/sec B D Figure 36: Recommended Reflow Soldering Thermal Profile Factor Soak Zone Max slope Table 38: Recommended Thermal Profile Parameters Recommendation 1 to 3C/sec Soak time (between A and B: 150C and 200C) 60 to 120 sec BG95_Hardware_Design 76 / 80 LPWA Module Series BG95 Hardware Design Reflow Zone Max slope Reflow time (D: over 220C) Max temperature Cooling down slope Reflow Cycle Max reflow cycle 8.3. Packaging 2 to 3C/sec 40 to 60 sec 238C ~ 245C 1 to 4C/sec 1 BG95 is packaged in a vacuum-sealed bag which is ESD protected. The bag should not be opened until the devices are ready to be soldered onto the application. The reel is 330mm in diameter and each reel contains 250 modules. The following figures show the packaging details, measured in mm. Figure 37: Tape Dimensions BG95_Hardware_Design 77 / 80 LPWA Module Series BG95 Hardware Design DETAIL:A 6 PS DETAIL:A Figure 38: Reel Dimensions Table 39: Reel Packaging Model Name MOQ for MP Minimum Package: 250pcs Minimum Package x 4=1000pcs BG95 250pcs Size: 370mm 350mm 56mm N.W: 0.61kg G.W: 1.35kg Size: 380mm 250mm 365mm N.W: 2.45kg G.W: 6.28kg BG95_Hardware_Design 78 / 80 LPWA Module Series BG95 Hardware Design 9 Appendix A References Table 40: Related Documents SN Document Name Remark

[1] Quectel_UMTS&LTE_EVB_User_Guide UMTS&LTE EVB User Guide

[2] Quectel_BG95_AT_Commands_Manual BG95 AT Commands Manual

[3] Quectel_BG95_GNSS_AT_Commands_Manual BG95 GNSS AT Commands Manual

[4] Quectel_RF_Layout_Application_Note RF Layout Application Note

[5] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide Table 41: Terms and Abbreviations Abbreviation Description Adaptive Multi-rate Bits Per Second Coding Scheme Clear To Send Challenge Handshake Authentication Protocol Delta Firmware Upgrade Over The Air Downlink Data Terminal Ready Discontinuous Transmission Extended Idle Mode Discontinuous Reception Evolved Packet Core AMR bps CHAP CS CTS DFOTA DL DTR DTX e-I-DRX EPC BG95_Hardware_Design 79 / 80 LPWA Module Series BG95 Hardware Design ESD FDD FR GMSK GSM HSS I/O Inorm LED LNA LTE MO MS MT PAP PCB PDU PPP PSM RF RHCP Rx SISO SMS TDD Electrostatic Discharge Frequency Division Duplex Full Rate Gaussian Minimum Shift Keying Global System for Mobile Communications Home Subscriber Server Input/Output Normal Current Light Emitting Diode Low Noise Amplifier Long Term Evolution Mobile Originated Mobile Station (GSM engine) Mobile Terminated Password Authentication Protocol Printed Circuit Board Protocol Data Unit Point-to-Point Protocol Power Saving Mode Radio Frequency Right Hand Circularly Polarized Receive Single Input Single Output Short Message Service Time Division Duplexing BG95_Hardware_Design 80 / 80 LPWA Module Series BG95 Hardware Design Transmitting Direction Uplink User Equipment Unsolicited Result Code Maximum Voltage Value Normal Voltage Value Minimum Voltage Value

(Universal) Subscriber Identity Module Maximum Input High Level Voltage Value Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Minimum Input Low Level Voltage Value Absolute Maximum Input Voltage Value Absolute Minimum Input Voltage Value Maximum Output High Level Voltage Value Minimum Output High Level Voltage Value Maximum Output Low Level Voltage Value Minimum Output Low Level Voltage Value Voltage Standing Wave Ratio TX UL UE URC

(U)SIM Vmax Vnorm Vmin VIHmax VIHmin VILmax VILmin VImax VImin VOHmax VOHmin VOLmax VOLmin VSWR BG95_Hardware_Design 81 / 80 LPWA Module Series BG95 Hardware Design 10 Appendix B GPRS Coding Schemes Table 42: Description of Different Coding Schemes Scheme Code Rate USF Pre-coded USF BCS Tail Coded Bits Punctured Bits Data Rate Kb/s Radio Block excl.USF and BCS 181 268 CS-1 CS-2 CS-3 CS-4 2/3 3/4 1/2 3 3 40 4 456 0 3 6 16 4 588 132 9.05 13.4 1 3 12 428 16

456 21.4 3 6 312 16 4 676 220 15.6 BG95_Hardware_Design 82 / 80 LPWA Module Series BG95 Hardware Design 11 Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots. The active slots determine the total number of slots the GPRS device can use simultaneously for both uplink and downlink communications. The description of different multi-slot classes is shown in the following table. Table 43: GPRS Multi-slot Classes Multislot Class Downlink Slots Uplink Slots Active Slots 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 2 3 2 3 3 4 3 4 4 4 3 4 2 3 3 4 4 4 4 5 5 5 5 5 NA NA 1 1 2 1 2 2 3 1 2 2 3 4 3 4 BG95_Hardware_Design 83 / 80 LPWA Module Series BG95 Hardware Design 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 5 6 7 8 6 6 6 6 6 8 8 8 8 8 8 5 5 5 5 5 6 7 8 2 3 4 4 6 2 3 4 4 6 8 1 2 3 4 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 6 6 6 6 BG95_Hardware_Design 84 / 80 LPWA Module Series BG95 Hardware Design 12 Appendix D EDGE Modulation and Coding Schemes Table 44: EDGE Modulation and Coding Schemes Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot GMSK GMSK GMSK GMSK GMSK GMSK GMSK GMSK 8-PSK 8-PSK 8-PSK 8-PSK 8-PSK

C B A C B A B A A 9.05kbps 18.1kbps 36.2kbps 13.4kbps 26.8kbps 53.6kbps 15.6kbps 31.2kbps 62.4kbps 21.4kbps 42.8kbps 85.6kbps 8.80kbps 17.60kbps 35.20kbps 11.2kbps 22.4kbps 44.8kbps 14.8kbps 29.6kbps 59.2kbps 17.6kbps 35.2kbps 70.4kbps 22.4kbps 44.8kbps 89.6kbps 29.6kbps 59.2kbps 118.4kbps 44.8kbps 89.6kbps 179.2kbps 54.4kbps 108.8kbps 217.6kbps 59.2kbps 118.4kbps 236.8kbps Coding Schemes CS-1 CS-2 CS-3 CS-4 MCS-1 MCS-2 MCS-3 MCS-4 MCS-5 MCS-6 MCS-7 MCS-8 MCS-9 BG95_Hardware_Design 85 / 80

QuecTreu BG95-M1 ai-avox LA

| BG9SM1LA-64-SGNS

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Cat M1. Quect tel Wire eless S Solution 95M1coverl BG9 s Com etter pany L imited al FCC ID: X XMR2020BG G95M1 BG9 Cert 5M1 origina tifitcate num mber: 202180 0143AA00 , date of gran nt :03/26/20 020 Acc ording to the e market's re equirement,

, we will clos se CatM1 Ba and 14 thro ugh softwa are, thei r hardware a are the sam e as before

. The chang ge will not im mpact RF pe rformance o of All r reports of So oftware Vers sion have be een updated d from BG95 5M1LAR02A A02 to BG9 95M1LAR02 2A04 withou t any modifi cation of the e data. Sign nature:

Prin nt name: Jea an Hu Date e: 05/11/202 20 Com mpany: Quec ctel Wireles s Solutions Co., Ltd. dress: Buildin hang Distric ail: jean.hu ng 5, Shang ct, Shanghai u@quectel.c ghai Busines

, China 200 com ss Park Pha 233 Add Min Ema se III (Area B), No.1016 6 Tianlin Roa ad,

Quectel Wireless Solutions Company Limited POWER OF ATTORNEY DATE: July 13, 2020 To:

Federal Communications Commission, Authorization & Evaluation Division, 7435 Oakland Mills Road, Columbia, MD 21046 We, the undersigned, hereby authorize TA Technology (Shanghai) Co., Ltd.

/Han jinnan on our behalf, to apply to FCC on our equipment for FCC ID:

XMR2020BG95M1. Any and all acts carried out by TA Technology (Shanghai) Co., Ltd. / Han jinnan on our behalf shall have the same effect as acts of our Signature:

Print name: Jen Hu Company: Quectel Wireless Solutions Company Limited own. Sincerely, 7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, ChinaEmail: info@quectel.comWebsite: www.quectel.compage 1

Quectel Wireless Solutions Co., Ltd Statement We Quectel Wireless Solutions Co., Ltd declare the following models. Product Name: Cat M1 Module Model Number: BG95-M3, BG95-M1 Hardware Version: R2.1 Module Category SupportedBand CatM1/NBIoT/

BG95-M3 GSM/GPRS/EGPR S Cat NB2:

Cat M1:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B14/B18/B19/B20/B25/B26/B27/ B28/B66/B85 LTE-FDD:B1/B2/B3/B4/B5/B8/B12/B13/

B18/B19/B20/B25/B26/ B28/B66/B71/B85 GSM/GPRS/ EGPRS: 850/900/1800/1900MHz Cat M1:

LTE-FDD:B1/B2/B3/B4/B5/B8/B12/B13/

B14/B18/B19/B20/B25/B26/ B27/B28/B66/B85 BG95-M1 CatM1 BG95-M1 and BG95-M3 share the same HW design, BG95-M1 only do removal of the component for GSM/GPRS/EGPRS on the hardware network according to the model requirement of the product definition, and BG95-M1 disable NB by SW on the basis of BG95-M3. Q Quectel Wire eless Solut tions Co., L td BG95-

M3 BG G95-M1 signator 3 scription) BG95-M3

(Part Des NA BG95-M

(Part D IC RF Coupler 1.0x0.5m M1 escription)

) M Directiona THIN-FILM 450M MHz-3800MH mm H0.3mm R RO al Hz Des U60 02 U60 03 U50 02 U50 04 The Sinc cerely, IC RF SW Qualband 5 WITCH SP1 5.3x5.5mm H 10T + GSM M H0.905mm RO O LOW PAS Hz 1.0x0.5m SS FILTER R mm H0.4mm m IC RF 698-960MH RO NA NA IC RF T 1.0x0.5mm TX LPF 16 695-2180MH O m H0.5mm RO z NA e change wil ll not impac ct RF perfor rmance of C Cat M1 . You ur assistance e on this ma atter is high ly appreciat ted. Nam me:Jean Hu u Titl le:Certificat tion Section n

Quec ctel Wirel ess Solu utions Co ompany Limited aration of the Modu lar Approv val antee cant / Gra ID:

el:

Quectel W XMR2020B BG95M1 ireless Solut G95M1 tions Compa any Limited Decla Appli FCC I Mode The s requi single mod rements u dule trans under Part smitter has t 15C Sect s been eva tion 212 a aluated th s below:

hen tested meeting t the Mo odular app proval req quirement EUT C Condition The radio e transmitter h elements of t have their ow the modular wn shielding. Co om p ply YE ES The modula integrated in schematic.p ar has buffere n chip. Pleas pdf ed data inpu se see ts, it is YE ES The radio e their own capacitors m elements. elements of t shielding. T may be loca the modular The physica ated external transmitter m al crystal a l to the shie must have nd tuning lded radio The modular transmitte inputs ata t the module conditions o have must er in nputs are

(if such y with part e will comply data rates f excessive buffered m provided) to 15 requirem or over-mod modulation/da o ensure tha ments under dulation.

(a)

(b)

(c)Th own he modular t npowersupp transmitter m must have its plyregulation n. All power lin device are r other circuit Please see nes derived f regulated bef ts internal to schematic.p pdf t from the host fore energizi ing M1. the BG95-M YE ES 7th Floor, Ho ngye Building, No.1 1801 Hongmei Roa ad, Xuhui District, S Shanghai 200233, C ChinaEmail: info@q quectel.comWebsite e: www.quectel.com mpage 1 Quec ctel Wirel ess Solu utions Co ompany Limited

(d) The w with the ante S Sections 15. m must either b a antenna cou a and the ante in nstallation p m modules but p paragraph (b must modular enna and tra 203, 15.204 be permanen pler (at all enna, includ provision of S can apply to

) of this sect r transmitter ansmission sy ystem requir 5.204(c). The 4(b) and 15 d or employ a ntly attached between th connections ing the cab ble). The pr 03 is not ap Section 15.2 o limited mo odular approv ion. comply rements of e antenna a unique he module rofessional plicable to vals under modu

(e)T he i in a stand-al in nside anothe p part 15 requi b battery powe re equirements li ines and dat m must not con th he module li ines shall b le ength is unk th here is no c s supporting e s support equip s shall be un S Section 1 15.31(i))must ular trans one configur er device d rements. Un red, it must c s found in S ta input/outp ntain ferrites,

(see Section e the length known, at le coupling betw equipment. A pment conne nmodified a m be smitter must he module m ration, i.e., th uring testing g for compli nsmitter mod nless the tran the AC line c comply with 07. AC or D Section 15.2 put lines con nnected to th y will be mar unless they The length n 15.27(a)). h typical of actual use timeters to in east 10 cent ase of the m ween the ca Any access ories, perip ected to the module duri nd commer rcially availa tested must not be iance with dule will be conducted DC power he module rketed with h of these or, if that nsure that odule and herals, or ing testing able (see tnotbeinsidea anotherdevic ceduringtesti ng. he mo equipped w be capable identification odular with either a p e of elect n number. transmitter permanently tronically d be must l or must affixed labe it ts FCC displaying

(f)Th

(g) The modula with any sp ordinarily ap manufacture with the mod of these inst equipmenta ntendeduse/

ar transmitter ecific rules o pply to a com er must provi dule to expla tructions mus uthorizationr

/configuratio r must compl or operating r mplete transm ide adequate ain any suchr st be include requirements ons. y requirements s that e mitter and the s along e instructions requirements s. A copy lication for ed in the app s,whichareba asedonthei A permanen antenna con licensed mo ntly attached nnector is no odules. antenna or ot a requirem unique ment for YE ES The BG95-M alone config extender. P M1was teste guration via a lease see sp d in a stand a PCMCIA purious set up YE ES early ule then 1. The label po indicated. If cannot be s the host lab Contains FC Please see The BG95-M applicable F are given in G95-M1 is cle osition of BG of the modu f the FCC ID is installed, t seen when it ude the text:

bel must inclu CC ID: XMR2 2020BG95M f the label.pdf M1 is complia ant with all Detail instruct FCC rules. D the User Ma anual. tions YE ES YE ES

(h)T he modular t w with any appl transmitter m licable RF ex must comply xposure requ uirements in its final The BG95-M the applicab M1 is approv ble RF expos ved to comply sure requirem y with ment, ES YE 7th Floor, Ho ngye Building, No.1 1801 Hongmei Roa ad, Xuhui District, S Shanghai 200233, C ChinaEmail: info@q quectel.comWebsite e: www.quectel.com mpage 2 Quec ctel Wirel ess Solu utions Co ompany Limited please see as the dista the MPE eva nce restrictio aluation with on. 20cm c configuration

. Dated By:

2020/3 3/9 Sign nature Jean n Hu Pri rinted Title:

Project M Manager Limited) On beh half of :

(Quectel l Wireless S Solutions Teleph one:

+862 2151086236 6ext6511 7th Floor, Ho ngye Building, No.1 1801 Hongmei Roa ad, Xuhui District, S Shanghai 200233, C ChinaEmail: info@q quectel.comWebsite e: www.quectel.com mpage 3

Quectel Wireless Solutions Company Limited Request for Confidentiality Date: _2020/3/9_ Subject: Confidentiality Request for: _____ FCC ID: XMR2020BG95M1 ______ Pursuant to FCC 47 CRF 0.457(d) and 0.459 and IC RSP-100, Section 10, the applicant requests that a part of the subject FCC application be held confidential. Type of Confidentiality Requested Short Term Short Term Short Term Short Term Short Term Short Term Short Term Short Term Short Term Permanent Permanent*1 Permanent Permanent Permanent Permanent Permanent*

Exhibit Block Diagrams External Photos Internal Photos Operation Description/Theory of Operation Parts List & Placement/BOM Tune-Up Procedure Schematics Test Setup Photos Users Manual

*Note: ______(Insert Explanation as Necessary)______ ______ FCC ID: XMR2020BG95M1 _____ has spent substantial effort in developing this product and it is one of the first of its kind in industry. Having the subject information easily available to "competition" would negate the advantage they have achieved by developing this product. Not protecting the details of the design will result in financial hardship. Permanent Confidentiality:

The applicant requests the exhibits listed above as permanently confidential be permanently withheld from public review due to materials that contain trade secrets and proprietary information not customarily released to the public. Short-Term Confidentiality:

The applicant requests the exhibits selected above as short term confidential be withheld from public view for a period of ______ days from the date of the Grant of Equipment Authorization and prior to marketing. This is to avoid premature release of sensitive information prior to marketing or release of the product to the public. Applicant is also aware that they are responsible to notify TCB in the event information regarding the product or the product is made available to the public. TCB will then release the documents listed above for public disclosure pursuant to FCC Public Notice DA 04-1705. NOTE for Industry Canada Applications:

The applicant understands that until such time that IC distinguishes between Short Term and Permanent Confidentiality, either type of marked exhibit above will simply be marked Confidential when submitted to IC. Sincerely, By:

(Signature/Title2) Jean Hu

(Print name) 7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, ChinaEmail: info@quectel.comWebsite: www.quectel.compage 1

Quectel Wireless Solutions Company Limited XMR201910BG95M3coverletter WeQuectelWirelessSolutionsCo.,Ltddeclarethefollowingmodels. ProductName:CatM1Module ModelNumber:BG95M3,BG95M1 HardwareVersion:R2.1 BG95M3FCCID:XMR201910BG95M3,dateofgrant:10/17/2019 Orginalmodel:BG95M3 Module Category SupportedBand CatM1:

LTE-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/

B14/B18/B19/B20/B25/B26/B27/

B28/B66/B85 CatNB2:

LTE-FDD:B1/B2/B3/B4/B5/B8/B12/B13/

B18/B19/B20/B25/B26/ B28/B66/B71/B85 GSM/GPRS/EGPRS:850/900/1800/1900MHz CatM1:

LTE-FDD:B1/B2/B3/B4/B5/B8/B12/B13/

B14/B18/B19/B20/B25/B26/

B27/B28/B66/B85 FCCrule parts 22H/24E/

27/90 22H/24E/

27/90 BG95M3 CatM1/NBIoT/

GSM/GPRS/EGPRS BG95M1 CatM1 BG95M1 and BG95M3 share the same HW design, BG95M1 only do removal of the component for GSM/GPRS/EGPRS on the hardware network according to the model requirement of the product definition, and BG95M1 disable NB by SW on the basis of BG95M3. Designator U602 U603 U502 U504 BG95M3 BG95M1 BG95-M3

(Part Description) NA BG95-M1

(Part Description) IC RF THIN-FILM Directional Coupler 450MHz-3800MHz 1.0x0.5mm H0.3mm RO IC RF SWITCH SP10T + GSM Qualband 5.3x5.5mm H0.905mm RO IC RF LOW PASS FILTER 698-960MHz 1.0x0.5mm H0.4mm RO NA NA IC RF TX LPF 1695-2180MHz 1.0x0.5mm H0.5mm RO NA ThechangewillnotimpactRFperformanceofCatM1. Pleaseseeallreportupdatesbelow:

BG95M1(ReportNo.:R1907A0450R1V2)isavariantmodelofBG95M3(ReportNo.:

R1907A0446R1V1).TestvaluespartialduplicatedfromOriginalforvariant.Thereisonlytested RFPowerOutput,EffectiveRadiatedPower,OccupiedBandwidthandRadiatesSpurious Emissionforvariantinthisreport. BG95M1(ReportNo.:R1907A0450R2V2)isavariantmodelofBG95M3(ReportNo.:

R1907A0446R2).TestvaluespartialduplicatedfromOriginalforvariant.Thereisonlytested RFPowerOutput,EffectiveIsotropicRadiatedPower,OccupiedBandwidthandRadiates SpuriousEmissionforvariantinthisreport. 2)isavariant uplicatedfrom atedPower, rt. 2)isavariant icatedfromO wer,Occupied tmodelofBG mOriginalfo OccupiedBa G95M3(Rep orvariant.Th andwidthand ortNo.:

ereisonlyte dRadiates ested tmodelofBG Originalforv dBandwidth G95M3(Rep variant.There andRadiate ortNo.:

eisonlyteste esSpurious ed 2)isavariant icatedfromO wer,Occupied tmodelofBG Originalforv dBandwidtha G95M3(Rep variant.There andRadiates ortNo.:

eisonlyteste sSpurious ed 2)isavariant plicatedfrom wer,Occupied tmodelofBG Originalfor dBandwidtha G95M3(Rep variant.Ther andRadiates ortNo.:

reisonlytest sSpurious ted 95M1(Repor 07A0446R3V PowerOutput riousEmissio 95M1(Repor 07A0446R7) PowerOutput ssionforvari 95M1(Repor 07A0446R8) PowerOutput ssionforvari 95M1(Repor 07A0446R11 PowerOutput ssionforvari rtNo.:R1907 V1).Testvalu t,EffectiveIs onforvariant rtNo.:R1907

).Testvalues t,EffectiveR iantinthisre rtNo.:R1907

).Testvalues t,EffectiveR iantinthisre rtNo.:R1907 1).Testvalue t,EffectiveR iantinthisre 7A0450R3V2 uespartialdu sotropicRadi tinthisrepo 7A0450R4V2 partialdupli RadiatedPow eport. 7A0450R5V2 partialdupli RadiatedPow eport. 7A0450R6V2 espartialdup RadiatedPow eport. BG9 R190 RFP Spur BG9 R190 RFP Emis BG9 R190 RFP Emis BG9 R190 RFP Emis Dat 202 20/3/10 ted By:

Jean Hu Title e: Projec On behalf of :

S Signature ct Manager

(Que Limite ectel ed) Printed W Wireless Solutions Tele ephone:

+8 862151086 1 236ext6511