FCC ID: XMR2023BG953AGL LTE Cat M1/NB Module

BG95xA-GL Hardware Design LPWA Module Series Version: 1.1.1 Date: 2022-06-10 Status: Preliminary LPWA Module Series At Quectel, our aim is to provide timely and comprehensive services to our customers. If you require any assistance, please contact our headquarters:

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local offices. For more information, please visit:

http://www.quectel.com/support/sales.htm. For technical support, or to report documentation errors, please visit:

http://www.quectel.com/support/technical.htm. Or email us at: support@quectel.com. Legal Notices We offer information as a service to you. The provided information is based on your requirements and we make every effort to ensure its quality. You agree that you are responsible for using independent analysis and evaluation in designing intended products, and we provide reference designs for illustrative purposes only. Before using any hardware, software or service guided by this document, please read this notice carefully. Even though we employ commercially reasonable efforts to provide the best possible experience, you hereby acknowledge and agree that this document and related services hereunder are provided to you on an as available basis. We may revise or restate this document from time to time at our sole discretion without any prior notice to you. Use and Disclosure Restrictions License Agreements Documents and information provided by us shall be kept confidential, unless specific permission is granted. They shall not be accessed or used for any purpose except as expressly provided herein. Copyright Our and third-party products hereunder may contain copyrighted material. Such copyrighted material shall not be copied, reproduced, distributed, merged, published, translated, or modified without prior written consent. We and the third party have exclusive rights over copyrighted material. No license shall be granted or conveyed under any patents, copyrights, trademarks, or service mark rights. To avoid ambiguities, purchasing in any form cannot be deemed as granting a license other than the normal non-exclusive, royalty-free license to use the material. We reserve the right to take legal action for noncompliance with abovementioned requirements, unauthorized use, or other illegal or malicious use of the material. BG95xA-GL_Hardware_Design 1 / 102 LPWA Module Series Trademarks Except as otherwise set forth herein, nothing in this document shall be construed as conferring any rights to use any trademark, trade name or name, abbreviation, or counterfeit product thereof owned by Quectel or any third party in advertising, publicity, or other aspects. Third-Party Rights This document may refer to hardware, software and/or documentation owned by one or more third parties

(third-party materials). Use of such third-party materials shall be governed by all restrictions and obligations applicable thereto. We make no warranty or representation, either express or implied, regarding the third-party materials, including but not limited to any implied or statutory, warranties of merchantability or fitness for a particular purpose, quiet enjoyment, system integration, information accuracy, and non-infringement of any third-party intellectual property rights with regard to the licensed technology or use thereof. Nothing herein constitutes a representation or warranty by us to either develop, enhance, modify, distribute, market, sell, offer for sale, or otherwise maintain production of any our products or any other hardware, software, device, tool, information, or product. We moreover disclaim any and all warranties arising from the course of dealing or usage of trade. Privacy Policy To implement module functionality, certain device data are uploaded to Quectels or third-partys servers, including carriers, chipset suppliers or customer-designated servers. Quectel, strictly abiding by the relevant laws and regulations, shall retain, use, disclose or otherwise process relevant data for the purpose of performing the service only or as permitted by applicable laws. Before data interaction with third parties, please be informed of their privacy and data security policy. Disclaimer a) We acknowledge no liability for any injury or damage arising from the reliance upon the information. b) We shall bear no liability resulting from any inaccuracies or omissions, or from the use of the information contained herein. c) While we have made every effort to ensure that the functions and features under development are free from errors, it is possible that they could contain errors, inaccuracies, and omissions. Unless otherwise provided by valid agreement, we make no warranties of any kind, either implied or express, and exclude all liability for any loss or damage suffered in connection with the use of features and functions under development, to the maximum extent permitted by law, regardless of whether such loss or damage may have been foreseeable. d) We are not responsible for the accessibility, safety, accuracy, availability, legality, or completeness of information, advertising, commercial offers, products, services, and materials on third-party websites and third-party resources. Copyright Quectel Wireless Solutions Co., Ltd. 2022. All rights reserved BG95xA-GL_Hardware_Design 2 / 102 LPWA Module Series Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be paid to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation interference with of wireless appliances in an aircraft communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft. is forbidden to prevent Wireless devices may cause interference on sensitive medical equipment, so the restrictions on the use of wireless devices when in please be aware of hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions, such as when the mobile bill is unpaid or the (U)SIM card is invalid. When emergent help is needed in such conditions, use emergency call if the device supports it. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. In an emergency, the device with emergency call function cannot be used as the only contact method considering network connection cannot be guaranteed under all circumstances. The cellular terminal or mobile contains a transceiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV sets, radios, computers or other electric equipment. In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fueling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or metal powders. BG95xA-GL_Hardware_Design 3 / 102 LPWA Module Series About the Document Revision History Version Date Author Description

2021-07-07 1.0 2022-04-22 1.1.0 2022-05-30 1.1.1 2022-06-10 Lex LI/

Ben JIANG Lex LI/

Ben JIANG Lex LI/

Ben JIANG Lex LI/

Ben JIANG Creation of the document First official release Preliminary:

Added the applicable modules of BG953A-GL and BG955A-GL. Preliminary:

Updated the functional diagram of BG955A-GL

(Figure 4) BG95xA-GL_Hardware_Design 4 / 102 LPWA Module Series Contents Safety Information ........................................................................................................................................ 3 About the Document .................................................................................................................................... 4 Contents .........................................................................................................................................................5 Table Index .................................................................................................................................................... 8 Figure Index .................................................................................................................................................10 1 2 Introduction ..........................................................................................................................................12 Special Mark ............................................................................................................................. 12 1.1. Product Overview ................................................................................................................................13 Frequency Bands and Functions ............................................................................................. 14 2.1. Key Features ............................................................................................................................ 15 2.2. Functional Diagram .................................................................................................................. 17 2.3. Pin Assignment .........................................................................................................................22 2.4. Pin Description ......................................................................................................................... 25 2.5. EVB Kit ......................................................................................................................................31 2.6. 3.5. 3.5.1. 3.6. 3.7. 3.4.1. 3.4.2. 3.1. 3.2. 3.3. 3.4. 3 Operating Characteristics .................................................................................................................. 32 Operating Modes ...................................................................................................................... 32 Airplane Mode ...........................................................................................................................33 Power Saving Mode (PSM) ......................................................................................................33 Extended Idle Mode DRX (e-I-DRX) ........................................................................................34 e-I-DRX Sleep Mode ....................................................................................................... 35 e-I-DRX Idle Mode ...........................................................................................................35 Sleep Mode ...............................................................................................................................35 UART Application Scenario .............................................................................................35 Recovery Mode ........................................................................................................................ 37 Power Supply ............................................................................................................................37 Power Supply Pins .......................................................................................................... 37 Voltage Stability Requirements .......................................................................................38 Power Supply Monitoring ................................................................................................ 39 Turn On ..................................................................................................................................... 40 Turn On with PWRKEY ................................................................................................... 40 Turn Off ..................................................................................................................................... 43 Turn Off with PWRKEY and PON_TRIG ........................................................................ 43 Turn Off with AT Command and PON_TRIG .................................................................. 44 3.10. Reset .........................................................................................................................................45 PON_TRIG ............................................................................................................................... 47 3.11. 3.7.1. 3.7.2. 3.7.3. 3.9.1. 3.9.2. 3.8.1. 3.9. 3.8. 4 Application Interfaces .........................................................................................................................49

(U)SIM Interface ....................................................................................................................... 49 4.1. USB Interface ........................................................................................................................... 51 4.2. UART Interfaces ....................................................................................................................... 53 4.3. BG95xA-GL_Hardware_Design 5 / 102 LPWA Module Series 4.4. 4.5. 4.6. 4.7. 4.8. ADC Interfaces ......................................................................................................................... 56 Indication Signals ..................................................................................................................... 57 PSM Status Indication .....................................................................................................57 4.5.1. Network Status Indication ............................................................................................... 58 4.5.2. 4.5.3. STATUS ........................................................................................................................... 59 4.5.4. MAIN_RI .......................................................................................................................... 60 GRFC Interfaces .......................................................................................................................60 GPIO Interface ..........................................................................................................................61 GNSS Control and Indication Interfaces ..................................................................................62 5.2. 5.1.1. 5.1.2. 5.1.3. 5.1.4. RF Specifications ................................................................................................................................ 63 Cellular Network ....................................................................................................................... 63 5.1. Antenna Interface & Frequency Bands ...........................................................................63 Tx Power ......................................................................................................................... 64 Rx Sensitivity ................................................................................................................... 65 Reference Design ............................................................................................................68 GNSS ........................................................................................................................................70 5.2.1. Antenna Interface & Frequency Bands ...........................................................................70 5.2.2. GNSS Performance ........................................................................................................ 71 Reference Design ............................................................................................................73 5.2.3. Layout Guidelines .....................................................................................................................74 RF Routing Guidelines ............................................................................................................. 74 Antenna Design Requirements ................................................................................................ 77 RF Connector Recommendation ............................................................................................. 80 5.3. 5.4. 5.5. 5.6. Reliability and Electrical Characteristics ......................................................................................... 89 Absolute Maximum Ratings ..................................................................................................... 89 6.1. Power Supply Ratings .............................................................................................................. 90 6.2. Power Consumption ................................................................................................................. 90 6.3. BG950A-GL Power Consumption ................................................................................... 90 6.3.1. BG951A-GL Power Consumption ................................................................................... 92 6.3.2. BG953A-GL Power Consumption ................................................................................... 95 6.3.3. 6.3.4. BG955A-GL Power Consumption ................................................................................... 97 6.3.5. GNSS Power Consumption .......................................................................................... 101 Digital I/O Characteristic ........................................................................................................ 104 ESD Protection ....................................................................................................................... 105 Operating and Storage Temperatures ................................................................................... 105 6.4. 6.5. 6.6. 5 6 7 Mechanical Information .................................................................................................................... 107 Top and Side View Dimensions ............................................................................................. 107 Recommended Footprint ........................................................................................................109 Top and Bottom Views ............................................................................................................110 7.1. 7.2. 7.3. 8 Storage, Manufacturing & Packaging .............................................................................................111 Storage Conditions ................................................................................................................. 111 8.1. Manufacturing and Soldering ................................................................................................. 112 8.2. BG95xA-GL_Hardware_Design 6 / 102 LPWA Module Series 8.3. Packaging Specifications ........................................................................................................113 Carrier Tape ................................................................................................................... 113 Plastic Reel ....................................................................................................................114 Packing Process ............................................................................................................115 8.3.1. 8.3.2. 8.3.3. 9 Appendix References ....................................................................................................................... 116 BG95xA-GL_Hardware_Design 7 / 102 LPWA Module Series Table Index Table 1: Special Mark ...................................................................................................................................12 Table 2: Brief Introduction of the Module .....................................................................................................13 Table 3: Wireless Network Types ................................................................................................................ 14 Table 4: Key Features .................................................................................................................................. 15 Table 5: I/O Parameters Definition .............................................................................................................. 25 Table 6: Pin Definition Pins with Same Functions on BG95xA-GL ..........................................................25 Table 7: Pin Definition Pins with Different Functions on BG95xA-GL ..................................................... 30 Table 8: Operating Mode Overview ............................................................................................................. 32 Table 9: Power Supply Pin Definition of BG950A-GL/BG951A-GL/BG953A-GL ....................................... 37 Table 10: Power Supply Pin Definition of BG955A-GL ............................................................................... 38 Table 11: PWRKEY Pin Definition ............................................................................................................... 40 Table 12: RESET_N Pin Definition .............................................................................................................. 45 Table 13: Pin Definition of PON_TRIG ........................................................................................................ 47 Table 14: (U)SIM Interface Pin Definition .................................................................................................... 49 Table 15: USB Interface Pin Definition ........................................................................................................ 51 Table 16: Main UART Interface Pin Definition .............................................................................................53 Table 17: Debug UART Interface Pin Definition .......................................................................................... 54 Table 18: BG950A-GL & BG953A-GL & BG955A-GL CLI UART Interface Pin Definition ......................... 54 Table 19: BG951A-GL CLI UART Interface Pin Definition .......................................................................... 54 Table 20: BG951A-GL GNSS UART Interface Pin Definition ..................................................................... 54 Table 21: Pin Definition of ADC Interfaces .................................................................................................. 56 Table 22: Characteristics of ADC Interfaces ............................................................................................... 57 Table 23: PSM_IND Pin Definition ...............................................................................................................57 Table 24: Pin Definition of NET_STATUS ....................................................................................................58 Table 25: Working State of Network Connection Status Indication ............................................................ 58 Table 26: STATUS Pin Definition ................................................................................................................. 59 Table 27: MAIN_RI Pin Definition ................................................................................................................ 60 Table 28: MAIN_RI Default Behaviors .........................................................................................................60 Table 29: GRFC Interface Pin Definitions ................................................................................................... 60 Table 30: GRFC Interface Truth Table .........................................................................................................61 Table 31: GPIO Interface Pin Definitions .....................................................................................................61 Table 32: Pin Definition of GNSS Control and Indication Interfaces .......................................................... 62 Table 33: Pin Definition of Cellular Network Interface .................................................................................63 Table 34: Operating Frequency ................................................................................................................... 63 Table 35: RF Output Power ......................................................................................................................... 64 Table 36: Conducted RF Receiving Sensitivity of BG950A-GL/BG951A-GL ............................................. 66 Table 37: Conducted RF Receiving Sensitivity of BG955A-GL .................................................................. 67 Table 38: Pin Definition of GNSS Antenna Interface ...................................................................................71 Table 39: BG950A-GL & BG953A-GL & BG955A-GL GNSS Frequency ................................................... 71 Table 40: BG951A-GL GNSS Frequency .................................................................................................... 71 Table 41: BG950A-GL & BG953A-GL GNSS Performance ........................................................................71 BG95xA-GL_Hardware_Design 8 / 102 LPWA Module Series Table 42: BG951A-GL GNSS Performance ................................................................................................ 72 Table 43: BG955A-GL GNSS Performance ................................................................................................ 72 Table 44: Antenna Design Requirements ....................................................................................................77 Table 45: Absolute Maximum Ratings ......................................................................................................... 89 Table 46: BG950A-GL & BG951A-GL & BG953A-GL Power Supply Ratings ............................................90 Table 47: BG955A-GL Power Supply Ratings .............................................................................................90 Table 48: BG950A-GL Power Consumption (Power Supply: 3.3 V, Room Temperature) ..........................90 Table 49: BG951A-GL Power Consumption (Power Supply: 3.3 V, Room Temperature) ..........................93 Table 50: BG953A-GL Power Consumption (Power Supply: 3.3 V, Room Temperature) ..........................95 Table 51: BG955A-GL Power Consumption (Power Supply: 3.8 V, Room Temperature) ..........................97 Table 52: BG950A-GL GNSS Power Consumption .................................................................................. 102 Table 53: BG951A-GL GNSS Power Consumption .................................................................................. 103 Table 54: BG953A-GL GNSS Power Consumption .................................................................................. 103 Table 55: BG955A-GL GNSS Power Consumption .................................................................................. 104 Table 56: 1.8 V Digital I/O Requirements (U)SIM .................................................................................. 104 Table 57: 1.8 V Digital I/O Requirements Others ...................................................................................104 Table 58: Electrostatics Discharge Characteristics (Temperature: 25 C, Humidity: 45 %) .....................105 Table 59: Operating and Storage Temperatures ....................................................................................... 105 Table 60: Recommended Thermal Profile Parameters ............................................................................. 113 Table 61: Carrier Tape Dimension Table (Unit: mm) ................................................................................. 114 Table 62: Plastic Reel Dimension Table (Unit: mm) .................................................................................. 114 Table 63: Related Documents ....................................................................................................................116 Table 64: Terms and Abbreviations ............................................................................................................116 BG95xA-GL_Hardware_Design 9 / 102 LPWA Module Series Figure Index Figure 1: Functional Diagram of BG950A-GL ............................................................................................. 18 Figure 2: Functional Diagram of BG951A-GL ............................................................................................. 19 Figure 3: Functional Diagram of BG953A-GL ............................................................................................. 20 Figure 4: Functional Diagram of BG955A-GL ............................................................................................. 21 Figure 5: Pin Assignment of BG950A-GL & BG953A-GL (Top View) ......................................................... 22 Figure 6: Pin Assignment of BG951A-GL (Top View) ................................................................................. 23 Figure 7: Pin Assignment of BG955A-GL (Top View) ................................................................................. 24 Figure 8: Sleep Mode Application via UART Interface ................................................................................36 Figure 9: Power Supply Limits During Burst Transmission .........................................................................38 Figure 10: Star Structure of Power Supply ..................................................................................................39 Figure 11: Turn On Module With a Driving Circuit .......................................................................................40 Figure 12: Turn On Module With a Button ...................................................................................................40 Figure 13: Power-up Timing (After VBAT is Stable for 100200 ms) ......................................................... 41 Figure 14: Power-up Timing (After VBAT is Stable for more than 250 ms) ................................................42 Figure 15: Restart Timing ............................................................................................................................ 43 Figure 16: Power-down Timing (PWRKEY & PON_TRIG) ......................................................................... 44 Figure 17: Power-down Timing (AT Command & PON_TRIG) ...................................................................44 Figure 18: Reference Circuit of RESET_N with a Driving Circuit ............................................................... 45 Figure 19: Reference Circuit of RESET_N with a Button ........................................................................... 46 Figure 20: Reset Timing ...............................................................................................................................46 Figure 21: PON_TRIG Reference Circuit 1 .................................................................................................47 Figure 22: PON_TRIG Reference Circuit 2 .................................................................................................48 Figure 23: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector ......................... 50 Figure 24: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector ............................50 Figure 25: Reference Circuit of USB Application ........................................................................................ 52 Figure 26: Main UART Reference Design (Translator Chip) ...................................................................... 55 Figure 27: Main UART Reference Design (Transistor Circuit) ....................................................................56 Figure 28: Reference Circuit of PSM Status Indication .............................................................................. 58 Figure 29: Reference Circuit of Network Status Indication .........................................................................59 Figure 30: Reference Circuit of STATUS .....................................................................................................59 Figure 31: Reference Circuit of Main Antenna Interface .............................................................................70 Figure 32: Reference Design of GNSS Antenna Interface ......................................................................... 74 Figure 33: Microstrip Design on a 2-Layer PCB ......................................................................................... 75 Figure 34: Coplanar Waveguide Design on a 2-Layer PCB ....................................................................... 75 Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 75 Figure 36: Coplanar Waveguide Design on a 4-Layer PCB (Layer 4 as Reference Ground) ................... 76 Figure 37: Dimensions of the Receptacle (Unit: mm) ................................................................................. 83 Figure 38: Specifications of Mated Plugs ....................................................................................................85 Figure 39: Space Factor of Mated Connectors (Unit: mm) .........................................................................88 Figure 40: Module Top and Side Dimensions (Unit: mm) ......................................................................... 107 Figure 41: Module Bottom Dimensions (Bottom View, Unit: mm) ............................................................ 108 BG95xA-GL_Hardware_Design 10 / 102 LPWA Module Series Figure 42: Recommended Footprint (Top View, Unit: mm) .......................................................................109 Figure 43: Top & Bottom Views of BG95xA-GL .........................................................................................110 Figure 44: Recommended Reflow Soldering Thermal Profile ...................................................................112 Figure 45: Carrier Tape Dimension Drawing ............................................................................................. 114 Figure 46: Plastic Reel Dimension Drawing .............................................................................................. 114 Figure 47: Packaging Process ...................................................................................................................115 BG95xA-GL_Hardware_Design 11 / 102 LPWA Module Series 1 Introduction This document helps you gain a quick insight into BG95xA-GL modules, their air and hardware interfaces, electrical and mechanical specifications, and other related information, as well. In addition, it includes some reference designs that, coupled with application notes and user guides, facilitate the development and deployment of your LPWA module applications. NOTE For conciseness purposes, BG95xA-GL modules will hereinafter be referred to collectively as ''the in parts hereof applicable to four modules, and individually as ''BG950A-GL'', module/modules''

"BG951A-GL", "BG953A-GL" and "BG955A-GL" in parts hereof referring to the differences between them. 1.1. Special Mark Table 1: Special Mark Mark Definition

Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin, AT command, or argument is under development and currently not supported; and the asterisk (*) after a model indicates that the sample of the model is currently unavailable. BG95xA-GL_Hardware_Design 12 / 102 LPWA Module Series 2 Product Overview The module is an embedded IoT (LTE Cat M1, NB1/NB2*) wireless communication module. It supports data connectivity on LTE HD-FDD network, and features GNSS functionality to meet your specific application demands. Additionally, BG955A-GL also supports GPRS network. It is an SMD type module that can be engineered into M2M applications, such as smart metering, tracking system, security, wireless POS, and other wearable devices. The module is an industrial-grade module for industrial and commercial applications only. Related information and details are listed in the table below. Table 2: Brief Introduction of the Module Categories Packaging and pins number LGA; 102 pieces Dimensions Weight

(23.6 0.2) mm (19.9 0.2) mm (2.2 0.2) mm Approx. 2.15 g Wireless technologies LTE, GNSS and GPRS Variants BG950A-GL, BG951A-GL, BG953A-GL, BG955A-GL BG95xA-GL_Hardware_Design 13 / 102 LPWA Module Series 2.1. Frequency Bands and Functions Table 3: Wireless Network Types Module Supported Bands LTE Bands Power Class GNSS BG950A-GL BG951A-GL BG953A-GL BG955A-GL Cat M1:

LTE HD-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/B2 0/B25/B26/B27/B28/B66 Cat NB1/NB2* 1:

LTE HD-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B17/B18/B1 9/B20/B25/B28/B66 Cat M1:

LTE HD-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/B2 0/B25/B26/B27/B28/B66 Cat NB1/NB2* 1:

LTE HD-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B17/B18/B1 9/B20/B25/B28/B66 Cat M1:

LTE HD-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/B2 0/B25/B26/B27/B28/B66 Cat NB1/NB2* 1:

LTE HD-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B17/B18/B1 9/B20/B25/B28/B66 Cat M1:

LTE HD-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/B2 0/B25/B26/B27/B28/B66 Cat NB1/NB2* 1:

LTE HD-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B17/B18/B1 9/B20/B25/B28/B66 GPRS:

GSM850/EGSM900/DCS1800/PCS1900 Power Class 3

(23 dBm 2.7 dB) GPS, GLONASS. Power Class 3

(23 dBm 2.7 dB) GPS, GLONASS, BDS, Galileo, QZSS. Power Class 3

(23 dBm 2.7 dB) GPS, GLONASS. Power Class 3

(23 dBm 2.7 dB) GPS, GLONASS. 1 LTE Cat NB2* is backward compatible with LTE Cat NB1. BG95xA-GL_Hardware_Design 14 / 102 LPWA Module Series NOTE The baseband chip of BG950A-GL, BG953A-GL and BG955A-GL integrates the GNSS function, whereas the internal baseband chip and GNSS chip are separated on BG951A-GL. Therefore, BG951A-GL supports concurrent operation of LTE and GNSS, whereas BG950A-GL, BG953A-GL and BG955A-GL does not. 2.2. Key Features Table 4: Key Features Features Details Power Supply SMS

(U)SIM Interface BG950A-GL/BG951A-GL/BG953A-GL:

Supply voltage: 2.24.35 V Typical supply voltage: 3.3 V BG955A-GL:

Supply voltage: 3.34.3 V Typical supply voltage: 3.8 V Text and PDU mode Point-to-point MO and MT SMS cell broadcast SMS storage: ME by default BG950A-GL/BG951A-GL/BG955A-GL:

Supports 1.8 V external (U)SIM/eSIM card only BG953A-GL:

Built-in iSIM. If iSIM function is used, an external (U)SIM card is required. Compliant with USB 2.0 specifications Supports full speed mode only Used for AT command communication, data transmission, software USB Interface debugging and firmware upgrade*

USB serial driver:

- Windows 7/8/8.1/10 Linux 2.65.15

UART Interfaces Main UART:

Used for AT command communication and data transmission Baud rate: 115200 bps by default Default frame format: 8N1 (8 data bits, no parity, 1 stop bit) Supports RTS and CTS hardware flow control CLI UART 2:

2 BG951A-GL only supports one CLI UART interface, while BG950A-GL, BG953A-GL and BG955A-GL support two CLI BG95xA-GL_Hardware_Design 15 / 102 LPWA Module Series Used for firmware upgrade, software debugging, log output, GNSS data and NMEA sentence output Baud rate: 115200 bps by default Default frame format: 8N1 (8 data bits, no parity, 1 stop bit) Supports RTS and CTS hardware flow control Debug UART:

Used for RF calibration and log output Baud rate: 961200 bps by default Default frame format: 8N1 (8 data bits, no parity, 1 stop bit) Supports RTS and CTS hardware flow control GNSS UART:

Only BG951A-GL module: used for GNSS data and GNSS NMEA sentence output, and GNSS firmware upgrade Baud rate: 115200 bps by default Network Indication Pin NET_STATUS to indicate network connectivity status AT Commands Antenna Interface Transmitting Power LTE Features GSM Features 3GPP TS 27.007 and 3GPP TS 27.005 AT commands Quectel enhanced AT commands Main antenna interface (ANT_MAIN), 50 impedance GNSS antenna interface (ANT_GNSS), 50 impedance Class 3 (23 dBm 2.7 dB) for LTE bands Class 4 (33 dBm 2 dB) for GSM850 Class 4 (33 dBm 2 dB) for EGSM900 Class 1 (30 dBm 2 dB) for DCS1800 Class 1 (30 dBm 2 dB) for PCS1900 Supports 3GPP Rel-13/Rel-14*

Supports LTE Cat M1, NB1/NB2*

Supports 1.4 MHz RF bandwidth for LTE Cat M1 Supports 200 kHz RF bandwidth for LTE Cat NB1/NB2*

Rel-13:

Cat M1: 300 kbps (DL)/375 kbps (UL) Cat NB1: 27.2 kbps (DL)/62.5 kbps (UL) Rel-14*:

Cat M1: 588 kbps (DL)/1119 kbps (UL) Cat NB2*: 127 kbps (DL)/158 kbps (UL) GPRS:

Support GPRS multi-slot class 10 Coding scheme: CS-1, CS-2, CS-3 and CS-4 Max. 85.6 kbps (DL)/42.8 kbps (UL) UART interfaces, more precisely, pin 27 (CLI_TXD1) and pin 28 (CLI_RXD1) are connected to pin 95 (CLI_TXD2) and pin 94 (CLI_RXD2) respectively inside the module. BG95xA-GL_Hardware_Design 16 / 102 Internet Protocol Features GNSS Features Temperature Range Firmware Upgrade Supports PPP/TCP/UDP/SSL/MQTT/FTP(S)/HTTP(S)/LwM2M/IPv4/IPv6/

LPWA Module Series TLS/DTLS/PING/CoAP/NITZ protocols Supports PAP and CHAP for PPP connections BG950A-GL/BG953A-GL/BG955A-GL:

GPS, GLONASS BG951A-GL:

GPS, GLONASS, BDS, Galileo, QZSS Operating temperature range 3: -35 to +75 C Extended temperature range 4: -40 to +85 C Storage temperature range: -40 to +90 C CLI UART interface 2 USB 2.0 interface DFOTA RoHS All hardware components are fully compliant with EU RoHS directive. 2.3. Functional Diagram The block diagrams and major functional parts of BG95xA-GL modules are illustrated in the following figures. Power management Baseband Radio frequency Peripheral interfaces 3 Within the operating temperature range, the module meets 3GPP specifications. 4 Within the extended temperature range, the module retains the ability to establish and maintain functions such as SMS and data transmission, without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may exceed the specified 3GPP tolerances. When the temperature returns to the operating temperature range, the module meets 3GPP specifications again. BG95xA-GL_Hardware_Design 17 / 102 LPWA Module Series Figure 1: Functional Diagram of BG950A-GL BG95xA-GL_Hardware_Design 18 / 102 LPWA Module Series Figure 2: Functional Diagram of BG951A-GL BG95xA-GL_Hardware_Design 19 / 102 LPWA Module Series Figure 3: Functional Diagram of BG953A-GL BG95xA-GL_Hardware_Design 20 / 102 LPWA Module Series Figure 4: Functional Diagram of BG955A-GL BG95xA-GL_Hardware_Design 21 / 102 LPWA Module Series 2.4. Pin Assignment The following figure illustrates the pin assignment of BG950A-GL and BG953A-GL. Figure 5: Pin Assignment of BG950A-GL & BG953A-GL (Top View) BG95xA-GL_Hardware_Design 22 / 102 The following figure illustrates the pin assignment of BG951A-GL. LPWA Module Series Figure 6: Pin Assignment of BG951A-GL (Top View) BG95xA-GL_Hardware_Design 23 / 102 The following figure illustrates the pin assignment of BG955A-GL. LPWA Module Series Figure 7: Pin Assignment of BG955A-GL (Top View) NOTE 1. ADC input voltage must not exceed 1.8 V. 2. Keep all RESERVED pins and unused pins unconnected. 3. GND pins should be connected to ground in the design. 4. Only BG951A-GL supports GNSS_BOOT (pin 75), GNSS_NRST (pin 76), GNSS_EN (pin 97) and BG95xA-GL_Hardware_Design 24 / 102 LPWA Module Series SFNIND_1PPS (pin 98). 5. On BG950A-GL, BG953A-GL and BG955A-GL, pin 27 (CLI_TXD1) and pin 28 (CLI_RXD1) are connected to pin 95 (CLI_TXD2) and pin 94 (CLI_RXD2) respectively inside the module. 6. The LNA is integrated inside the module. It is not recommended to use an external LNA. It is strongly recommended to keep GNSS_LNA_EN (pin 51) and VDD_RF (pin 99) unconnected. 2.5. Pin Description The following table shows the DC characteristics and pin descriptions. Table 5: I/O Parameters Definition Type AI AIO DI DO DIO OD PI PO Description Analog Input Analog Input/Output Digital Input Digital Output Digital Input/Output Open Drain Power Input Power Output Table 6: Pin Definition Pins with Same Functions on BG95xA-GL Power Supply Output Pin Name Pin No. I/O Description DC Characteristics Comment VDD_EXT 29 PO Provide 1.8 V for external circuits Vnom = 1.8 V IOmax = 50 mA Turn On/Off Pin Name Pin No. I/O Description DC Characteristics Comment BG95xA-GL_Hardware_Design 25 / 102 PWRKEY 15 DI Turn on/off the module LPWA Module Series VILmax = 0.3 V VIHmin = 1.0 V Internally pulled up with a 470 k resistor. Reset Pin Name Pin No. I/O Description DC Characteristics Comment RESET_N 17 DI Reset the module VILmax = 0.3 V VIHmin = 1.3 V Internally pulled up with a 470 k resistor. Status Indication Pin Name Pin No. I/O Description DC Characteristics Comment PSM_IND 1 DO STATUS 20 DO NET_STATUS 21 DO Indicate the modules power saving mode Indicate the modules operation status Indicate the modules network activity status VOLmax = 0.36 V VOHmin = 1.44 V 1.8 V power domain. If unused, keep these pins open. USB Interface Pin Name USB_VBUS USB_DP Pin No. 8 9 I/O Description DC Characteristics Comment AI USB connection detect Vnom = 5.0 V Typical 5.0 V AIO USB differential data (+) Vmax = 4.1 V Vmin = -0.2 V Compliant with the standard USB 2.0 specification. Requires differential impedance of 90 . USB_DM 10 AIO USB differential data (-)

(U)SIM Interface Pin Name Pin No. I/O Description DC Characteristics Comment USIM_DET 42 DI

(U)SIM card hot-plug detect USIM_VDD USIM_RST USIM_DATA 43 44 45 PO

(U)SIM card power supply DO

(U)SIM card reset DIO

(U)SIM card data VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V Vmax = 1.9 V Vmin = 1.7 V VOLmax = 0.36 V VOHmin = 1.44 V VILmin = -0.2 V VILmax = 0.54 V 1.8 V power domain. If unused, keep this pin open. Only 1.8 V (U)SIM card is supported. 1.8 V power domain. BG95xA-GL_Hardware_Design 26 / 102 LPWA Module Series VIHmin = 1.26 V VIHmax = 2.0 V VOLmax = 0.36 V VOHmin = 1.44 V VOLmax = 0.36 V VOHmin = 1.44 V DO

(U)SIM card clock

Specified ground for

(U)SIM card

I/O Description DC Characteristics Comment DI DI Main UART data terminal ready Main UART receive VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V DO Main UART transmit USIM_CLK USIM_GND 46 47 Main UART Interface Pin Name MAIN_DTR MAIN_RXD MAIN_TXD Pin No. 30 34 35 MAIN_CTS 36 DO MAIN_RTS 37 DI MAIN_DCD MAIN_RI 38 39 DO DO DTE clear to send signal from DCE (Connect to DTEs CTS) DTE request to send signal from DCE

(Connect to DTEs RTS) Main UART data carrier detect Main UART ring indication VOLmax = 0.36 V VOHmin = 1.44 V VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V VOLmax = 0.36 V VOHmin = 1.44 V 1.8 V power domain. If unused, keep these pins open. Debug UART Interface Pin Name Pin No. I/O Description DC Characteristics Comment DBG_RXD 22 DI Debug UART receive DBG_TXD 23 DO Debug UART transmit VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V VOLmax = 0.36 V VOHmin = 1.44 V 1.8 V power domain. If unused, keep these pins open. Antenna Interfaces Pin Name ANT_MAIN Pin No. 60 I/O Description DC Characteristics Comment AIO Main antenna interface

50 impedance BG95xA-GL_Hardware_Design 27 / 102 ANT_GNSS 49 AI GNSS antenna interface LPWA Module Series 50 impedance. If unused, keep this pin open. GPIO Interfaces Pin Name GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 ADC Interfaces Pin Name ADC0 ADC1 Other Interfaces Pin Name Pin No. 25 26 64 65 66 85 86 87 88 Pin No. 24 2 Pin No. I/O Description DC Characteristics Comment DIO DIO DIO DIO DIO DIO DIO DIO DIO General-purpose input/output VOLmax = 0.36 V VOHmin = 1.44 V VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep these pins open. I/O Description DC Characteristics Comment AI AI General-purpose ADC interface General-purpose ADC interface 01.8 V 01.8 V If unused, keep these pins open. I/O Description DC Characteristics Comment W_DISABLE#

18 DI Airplane mode control VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V 1.8 V power domain. Pulled up by default. When this pin is at a low level, the module can enter airplane mode. If unused, keep this pin open. BG95xA-GL_Hardware_Design 28 / 102 AP_READY 19 DI Application processor sleep state detect PON_TRIG 96 DI Used for main UART function control and for entering/exiting e-l-DRX, PSM, sleep or power off modes LPWA Module Series VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V VILmin = -0.2 V VILmax = 0.3 V VIHmin = 1 V VIHmax = 1.98 V 1.8 V power domain. If unused, keep this pin open. 1.8 V power domain. Pulled down by default. GRFC Interface Pin Name GRFC1 Pin No. 83 I/O Description DC Characteristics Comment DO Generic RF controller GRFC2 84 DO Generic RF controller External GNSS LNA Interface 5 VOLmax = 0.36 V VOHmin = 1.44 V VOHmax = 2.0 V 1.8 V power domain. If unused, keep these pins open. Pin Name Pin No. I/O Description DC Characteristics Comment GNSS_LNA_ EN 51 DO External GNSS LNA enable VOLmax = 0.38 V VOHmin = 1.36 V VDD_RF 99 PO Can be used for external GNSS LNA power supply Vnom = 1.9 V IOmax = 50 mA RESERVED Pins Pin Name Pin No. RESERVED 47, 1114, 16, 40, 41, 56, 57, 63, 77, 78, 92, 93 GND Pins Pin Name Pin No. GND 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 6774, 7982, 8991, 100102 1.8 V power domain. If unused, keep this pin open. If unused, keep this pin open. Comment Keep these pins open. Comment 5 The LNA is integrated inside the module. It is not recommended to use an external LNA. It is strongly recommended to keep GNSS_LNA_EN (pin 51) and VDD_RF (pin 99) unconnected. BG95xA-GL_Hardware_Design 29 / 102 Table 7: Pin Definition Pins with Different Functions on BG95xA-GL Pin No. 32 33 52 BG950A-GL/BG953A-GL BG951A-GL BG955A-GL Pin Name Pin Description Pin Name Pin Description Pin Name Pin Description VBAT_BB VBAT_RF Power supply for the modules baseband part Power supply for the modules RF part VBAT_BB VBAT_RF Power supply for the modules baseband part Power supply for the modules RF part RESERVED Reserved RESERVED Reserved 53 RESERVED Reserved RESERVED Reserved VBAT_BB Power supply for the modules baseband part VBAT_RF Power supply for the modules RF part 94 CLI_RXD2 CLI UART2 receive CLI_RXD CLI UART receive CLI_RXD2 CLI UART2 receive DI 95 27 28 75 76 97 CLI_TXD2 CLI UART2 transmit CLI_TXD CLI UART transmit CLI_TXD2 CLI UART2 transmit CLI_TXD1 CLI UART1 transmit GNSS_TXD GNSS UART transmit CLI_TXD1 CLI UART1 transmit CLI_RXD1 CLI UART1 receive GNSS_RXD GNSS UART receive CLI_RXD1 CLI UART1 receive RESERVED Reserved GNSS_BOOT RESERVED Reserved GNSS_NRST Force the GNSS chip of the module into emergency download mode RESERVED Reserved Reset the GNSS chip;

Active high RESERVED Reserved RESERVED Reserved GNSS_EN Enable internal GNSS chip RESERVED Reserved DO DO DI DI DI DI LPWA Module Series I/O DC Characteristics Comment BG950A-GL/BG953A-GL:

Vmax = 4.35 V Vmin = 2.2 V Vnom = 3.3 V PI BG955A-GL:

Vmax = 4.3 V Vmin = 3.3 V Vnom = 3.8 V VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V VOLmax = 0.36 V VOHmin = 1.44 V VILmin = -0.2 V VILmax = 0.54 V VIHmin = 1.26 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep these pins open. 98 RESERVED Reserved SFNIND_1PPS One pulse per second RESERVED Reserved DO VOLmax = 0.36 V VOHmin = 1.44 V Synchronized at the rising edge. Pulse width: 100 ms. If unused, keep it open. BG95xA-GL_Hardware_Design 30 / 102 LPWA Module Series NOTE 1. For BG950A-GL/BG951A-GL/BG953A-GL, when the module starts up normally, to ensure full functionality, the minimum supply voltage should be higher than 2.2 V. While for BG955A-GL, the minimum supply voltage should be higher than 3.3 V. For every VBAT transition/re-insertion from 0 V, VBAT slew rate < 25 mV/s. To ensure normal module startup, pulling down PWRKEY to turn on the module after VBAT remains stable for 100 ms. 2. After entering PSM or power off mode, it is prohibited to provide any external voltage to the module's I/O ports that are not defined as a wake-up source. 3. Keep all RESERVED pins and unused pins unconnected. 2.6. EVB Kit To help you develop applications with the module, Quectel supplies an evaluation board (UMTS&LTE EVB) with accessories to control or test the module. For more details, see document [1]. BG95xA-GL_Hardware_Design 31 / 102 LPWA Module Series 3 Operating Characteristics 3.1. Operating Modes The table below outlines operating modes of the module. Table 8: Operating Mode Overview Mode Details Normal Operation Extended Idle Mode DRX (e-I-DRX) Idle The module remains registered on the network and is ready to send and receive data. In this mode, the software is active. Connected The module is connected to the network. Its current consumption varies with the network setting and data transfer rate. The module and network may negotiate over non-access stratum signaling the use of e-I-DRX for reducing power consumption while being available for mobile terminated data and/or network originated procedures within a certain delay dependent on the DRX cycle value. Airplane Mode AT+CFUN=4 or W_DISABLE# pin can set the module to airplane mode where the RF function is invalid. Minimum Functionality AT+CFUN=0 can set the module to minimum functionality without removing the power supply. In this mode, both RF function and (U)SIM card are invalid. Sleep Mode Power OFF Mode The module retains the ability to receive paging messages, SMS and TCP/UDP data from the network normally. In this mode, the current consumption is reduced to a low level. The modules power supply is shut down by its power management unit. The software is inactive, the serial interfaces are inaccessible, while the operating voltage of VBAT_BB/RF is still maintained. Power Saving Mode

(PSM) PSM is similar to power-off, but the module remains registered on the network and there is no need to re-attach or re-establish PDN connections. The current consumption is minimized. Recovery Mode The module can burn firmware with an empty serial firmware malfunction. For more details, see Chapter 3.6. flash, or recover from BG95xA-GL_Hardware_Design 32 / 102 LPWA Module Series NOTE In e-I-DRX mode, it is recommended to use the main UART interface for data communication, as the use of USB interface will increase power consumption. 3.2. Airplane Mode When the module enters airplane mode, correlative with RF function will be inaccessible. This mode can be set as follows:

the RF function will be disabled, and all AT commands Hardware:

W_DISABLE# is pulled up by default. Driving it low will make the module enter airplane mode. Software:

AT+CFUN=<fun> provides functionality level choices by setting <fun> to 0, 1 or 4. AT+CFUN=0: Minimum functionality. Both RF and (U)SIM functions are disabled. AT+CFUN=1: Full functionality (default). AT+CFUN=4: Airplane mode (RF function is disabled). NOTE 1. Airplane mode control via W_DISABLE# is disabled in firmware by default. It can be enabled with 2. On BG950A-GL/BG953A-GL/BG955A-GL, AT+QCFG="airplanecontrol". For more details of the command, see document [2]. the execution of AT+CFUN will affect the GNSS function. Since the module does not support concurrent operation of LTE and GNSS, the GNSS function can be used when <fun>=0 or 4, but cannot be used when <fun>=1. 3. On BG951A-GL, the execution of AT+CFUN will not affect the GNSS function. 3.3. Power Saving Mode (PSM) The module minimizes its power consumption by entering PSM. The mode is similar to power-off, but the module remains registered on the network and there is no need to re-attach or re-establish PDN connections. Therefore, in PSM the module cannot immediately respond to user requests. When the module wants to use PSM, it shall request an Active Time value during every Attach and TAU procedure. If the network supports PSM use, it will allocate an Active Time value to the module to confirm BG95xA-GL_Hardware_Design 33 / 102 LPWA Module Series PSM use. If the module wants to change the Active Time value, the module consequently requests the value it wants in the TAU procedure. If PSM is supported by the network, then it can be enabled via AT+QPSMS. In this case, driving PON_TRIG low will set the module to PSM. Any of the following methods can wake up the module from PSM:

Driving PON_TRIG high and keeping it high, will wake up the module from PSM. When the TAU timer expires, the module wakes up from PSM automatically. In this case, the main UART interface is inaccessible until PON_TRIG is pulled up. Driving PWRKEY low to wake up the module from PSM. In this case, the main UART interface is inaccessible until PON_TRIG is pulled up. NOTE 1. PON_TRIG is pulled down by default. 2. PON_TRIG must be pulled up after executing any PSM wake-up event, otherwise the main UART will be inaccessible. In any case, the main UART interface is inaccessible until PON_TRIG is pulled up. 3. See document [3] for details about AT+QPSMS. 3.4. Extended Idle Mode DRX (e-I-DRX) The module (UE) and the network may negotiate over non-access stratum signalling the use of e-I-DRX for reducing its power consumption, while being available for mobile terminating data and/or network originated procedures within a certain delay dependent on the DRX cycle value. Applications that want to use e-I-DRX need to consider specific handling of mobile terminating services or data transfers, and in particular, they need to consider the delay tolerance of mobile terminated data. In order to negotiate the use of e-I-DRX, the UE requests e-I-DRX parameters during attach procedure and RAU/TAU procedure. The EPC may reject or accept the UE request for enabling e-I-DRX. In case the EPC accepts e-I-DRX, the EPC based on operator policies and, if available, the e-I-DRX cycle length value in the subscription data from the HSS, may also provide different values of the e-I-DRX parameters than what was requested by the UE. If the EPC accepts the use of e-I-DRX, the UE applies e-I-DRX based on the received e-I-DRX parameters. If the UE does not receive e-I-DRX parameters in the relevant accept message because the EPC rejected its request or because the request was received by EPC not supporting e-I-DRX, the UE shall apply its regular discontinuous reception. BG95xA-GL_Hardware_Design 34 / 102 LPWA Module Series 3.4.1. e-I-DRX Sleep Mode If e-I-DRX is supported by the network, perform the steps below in sequence to make the module enter e-l-DRX sleep mode, in which case the main UART interface is inaccessible. 1. Send AT+QPSMS=0 to disable the use of PSM. 2. Send AT+CEDRXS=1 to enable the use of e-l-DRX. 3. Send AT+QSCLK=2 to enable sleep mode. 4. Drive MAIN_DTR high. 5. Drive PON_TRIG low. To make the module exit e-l-DRX sleep mode, perform the steps below in sequence. 1. Drive PON_TRIG high. 2. Drive MAIN_DTR low. 3. Send AT+QSCLK=0 to disable sleep mode. 4. Send AT+CEDRXS=0 to disable the use of e-l-DRX mode. 5. Send AT+QPSMS=0 to enable the use of PSM (optional). 3.4.2. e-I-DRX Idle Mode If e-I-DRX is supported by the network, just send AT+CEDRXS=1 to make the module enter e-l-DRX idle mode, or send AT+CEDRXS=0 to make the module exit e-l-DRX idle mode. NOTE See document [3] for details about the above AT commands. 3.5. Sleep Mode The module can reduce its power consumption during the sleep mode. Power saving procedures and sleep mode are outlined in the following sub-sections. 3.5.1. UART Application Scenario If the host communicates with the module via the main UART interface, perform the steps below in sequence to make the module enter the sleep mode, in which case the main UART interface is not accessible. BG95xA-GL_Hardware_Design 35 / 102 LPWA Module Series 1. Send AT+CFUN=0 to set the module to minimum functionality 6. 2. Drive MAIN_DTR low. 3. Execute AT+QSCLK=2 to enable sleep mode. 4. Drive MAIN_DTR high. 5. Drive PON_TRIG low. When the module is in sleep mode, perform the steps below in sequence to make the module exit sleep mode. 1. Drive PON_TRIG high. 2. Drive MAIN_DTR low. 3. Execute AT+QSCLK=0 to disable sleep mode. 4. Send AT+CFUN=1 to set the module to full functionality 6. 5. Drive MAIN_DTR high. The figure illustrates the connection between the module and the host. Figure 8: Sleep Mode Application via UART Interface When the module has a URC to report, MAIN_RI will wake up the host. See Chapter 4.5.4 for details about MAIN_RI behavior. After the module is turned on, MAIN_DTR is internally pulled up by default. AP_READY will detect the sleep state of the host (it can be configured to detect high or low voltage level). See AT+QCFG="apready" in document [2] for details. 6 After setting the module to minimum functionality with AT+CFUN=0, you can test the lowest power consumption of the module after the module enters sleep mode. If you need to keep the RF function on after the module enters sleep mode, there is no need to send any AT+CFUN. BG95xA-GL_Hardware_Design 36 / 102 LPWA Module Series 3.6. Recovery Mode The module features the recovery mode for firmware upgrade in emergency cases. Recovery mode can force the baseband chip of the module to upgrade firmware via the CLI UART interface(s) 7. The following preconditions can set the module to recovery mode. 1. Short-circuit CLI_TXD & CLI_RXD on BG951A-GL, or CLI_TXD2 & CLI_RXD2 on BG950A-GL/

BG953A-GL/BG955A-GL. 2. Drive PWRKEY low to turn on the module. In this case the module will enter recovery mode. 3. After the module enters recovery mode, disconnect CLI_TXD & CLI_RXD, or CLI_TXD2 &

CLI_RXD2. 4. Upgrade firmware via the CLI UART interface(s) 7. NOTE 1. In recovery mode, pin 25 functions as CLI_RTS and pin 26 functions as CLI_CTS, while in other modes they are GPIO pins. 2. Since the baud rate of the UART interface required to download firmware to the baseband chip is 3 Mbps, the flow control pins of the CLI UART interface need to be reserved. Otherwise, you can only download with a 921600 baud rate, which is very slow. It is recommended to reserve the test points of the CLI UART interface, including pin 25, pin 26, pin 94 and pin 95, and keep pin 94 close to pin 95. 3. Ensure that VBAT remains stable for at least 100 ms before pulling down PWRKEY. 3.7. Power Supply 3.7.1. Power Supply Pins The module has two VBAT pins for connection with an external power supply. One VBAT_RF pin for RF part. One VBAT_BB pin for baseband part. Table 9: Power Supply Pin Definition of BG950A-GL/BG951A-GL/BG953A-GL Pin Name Pin No. Description Min. Typ. Max. Unit 7 On BG950A-GL, BG953A-GL and BG955A-GL, it is recommended to use CLI UART2 for firmware upgrade in recovery mode. CLI UART1 is not recommended to be used in this case. BG95xA-GL_Hardware_Design 37 / 102 LPWA Module Series VBAT_BB 32 Power supply for the modules baseband part 2.2 3.3 4.35 VBAT_RF 33 Power supply for the modules RF part 2.2 3.3 4.35 GND 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 6774, 7982, 8991, 100102

V V

Table 10: Power Supply Pin Definition of BG955A-GL Pin Name Pin No. Description Min. Typ. Max. Unit VBAT_BB VBAT_RF 32 33 52 53 Power supply for the modules baseband part 3.3 3.8 4.3 Power supply for the modules RF part 3.3 3.8 4.3 GND 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 6774, 7982, 8991, 100102

V V

NOTE For BG950A-GL/BG951A-GL/BG953A-GL, when the module starts up normally, to ensure full functionality, the minimum supply voltage should be higher than 2.2 V. While for BG955A-GL, the minimum supply voltage should be higher than 3.3 V. For every VBAT transition/re-insertion from 0 V, VBAT slew rate < 25 mV/s. 3.7.2. Voltage Stability Requirements The power supply range of the BG950A-GL/BG951A-GL/BG953A-GL module is from 2.2 V to 4.35 V. Make sure that the input voltage never drops below 2.2 V. The power supply range of the BG955A-GL module is from 3.3 V to 4.3 V. Make sure that the input voltage never drops below 3.3 V. Figure 9: Power Supply Limits During Burst Transmission BG95xA-GL_Hardware_Design 38 / 102 LPWA Module Series To decrease voltage drop, one bypass capacitor of about 100 F with low ESR and one multi-layer ceramic chip (MLCC) capacitor array for its ultra-low ESR should be used for VBAT_BB & RF respectively. It is recommended to use three ceramic capacitors for composing the MLCC array (100 nF, 33 pF, 10 pF), and place these capacitors close to VBAT pins. The main power supply from an external application must be a single voltage source that can supply power along two star-structured sub paths. The width of VBAT_BB or VBAT_RF trace should be at least 1 mm. In principle, the longer the VBAT trace is, the wider it should be. In addition, to ensure power supply stability, it is necessary to add two high-power TVS components near VBAT_BB and VBAT_RF. The reference circuit of the power supply is shown below. Figure 10: Star Structure of Power Supply Power design for the module is critical to its performance. For BG950A-GL/BG951A-GL/BG953A-GL, the power supply of the module should be able to provide a sufficient current of at least 0.8 A, so it is recommended to select a DC-DC converter chip or an LDO chip with ultra-low leakage current and current output of at least 1.0 A for the power supply design. For BG955A-GL, the power supply design is to be confirmed. 3.7.3. Power Supply Monitoring AT+CBC can be used to monitor the VBAT_BB voltage value. For more details, see document [3]. BG95xA-GL_Hardware_Design 39 / 102 LPWA Module Series 3.8. Turn On 3.8.1. Turn On with PWRKEY Table 11: PWRKEY Pin Definition Pin Name Pin No. I/O Description Comment PWRKEY 15 DI Turn on/off the module Internally pulled up with a 470 k resistor. When the module is in power off mode, driving PWRKEY low for 5001000 ms and then releasing it will turn on the module. It is recommended to use an open drain/collector driver to control PWRKEY. A simple reference design is illustrated in the following figure. Figure 11: Turn On Module With a Driving Circuit Another way to control PWRKEY is with a button. Pressing the button may result in a discharge of static electricity from a finger. Therefore, it is vital to place a TVS component near the button for ESD protection. Figure 12: Turn On Module With a Button BG95xA-GL_Hardware_Design 40 / 102 Drive PON_TRIG high and then drive PWRKEY low after VBAT is stable for 100200 ms, the module will be turned on immediately. The power-up timing is shown below. LPWA Module Series Figure 13: Power-up Timing (After VBAT is Stable for 100200 ms)

. NOTE 1. Ensure that VBAT is stable for 100200 ms before pulling down PWRKEY. 2. Before you turn on the module by driving PWRKEY low for 5001000 ms, drive PON_TRIG high, otherwise, the main UART interface will be inaccessible. Drive PON_TRIG high and then drive PWRKEY low after VBAT is stable for more than 250 ms, the module will be turned on immediately. The power-up timing is shown below. BG95xA-GL_Hardware_Design 41 / 102 LPWA Module Series Figure 14: Power-up Timing (After VBAT is Stable for more than 250 ms) NOTE 1. After VBAT is powered on, it will take about 250 ms for the module to load the internal program. 2. Before the module is turned on by driving PWRKEY low for 5001000 ms, drive PON_TRIG high, otherwise, the main UART interface will be inaccessible. After the module is turned off with the PWRKEY and PON_TRIG solution (see Chapter 3.9.1) or the AT command and PON_TRIG solution (see Chapter 3.9.2), VBAT will keep powered on all the time until the main power supply is disconnected. In this case, driving PON_TRIG high and then driving PWRKEY low will restart the module, and the restart timing is shown below. BG95xA-GL_Hardware_Design 42 / 102 LPWA Module Series Figure 15: Restart Timing 3.9. Turn Off After the module is turned off or enters PSM, do not pull up any I/O pin lest it cause additional power consumption and possibly damage pins on the module. Either of the following methods can be used to turn off the module normally:

Turn off the module via PWRKEY and PON_TRIG. Turn off the module via AT+QPOWD and PON_TRIG. 3.9.1. Turn Off with PWRKEY and PON_TRIG When the module is powered on, drive PWRKEY low for 6501500 ms before releasing it, and then pull down PON_TRIG within 200 ms, after which the module will execute the power-down procedure. The power-down timing is illustrated in the following figure. BG95xA-GL_Hardware_Design 43 / 102 LPWA Module Series Figure 16: Power-down Timing (PWRKEY & PON_TRIG) 3.9.2. Turn Off with AT Command and PON_TRIG Similar to PWRKEY, the module can be turned off safely with AT+QPOWD. After AT+QPOWD is sent, pull down PON_TRIG within 200 ms, and the module will execute the power-down procedure. See document [3] for details about AT+QPOWD. Figure 17: Power-down Timing (AT Command & PON_TRIG) BG95xA-GL_Hardware_Design 44 / 102 LPWA Module Series

. NOTE 1. To avoid internal flash data damage, do not switch off the power supply while the module is working normally. The power supply can be cut off only after the module is shut down with PWRKEY &

PON_TRIG or AT command & PON_TRIG. 2. When turning off the module with AT command, keep PWRKEY at a high level after executing the power-off command. Otherwise, the module will be turned on again after turn-off. 3.10. Reset The module can be reset by driving RESET_N low for at least 100 ms and then releasing it. The RESET_N signal is sensitive to interference, so it is recommended to route the trace as short as possible and surround it with ground. Table 12: RESET_N Pin Definition Pin Name Pin No. RESET_N 17 I/O DI Description Reset the module. Internally pulled up with a 470 k resistor. The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or a button can be used to control RESET_N. Figure 18: Reference Circuit of RESET_N with a Driving Circuit BG95xA-GL_Hardware_Design 45 / 102 LPWA Module Series Figure 19: Reference Circuit of RESET_N with a Button The reset timing is illustrated in the following figure. Figure 20: Reset Timing NOTE 1. Ensure that there is no large capacitance on RESET_N pin. 2. Because PWRKEY and RESET traces are sensitive signal traces, its necessary to surround the traces with ground on that layer and with ground planes above and below, and keep their traces away from each other, so as to reduce interference. BG95xA-GL_Hardware_Design 46 / 102 LPWA Module Series 3.11. PON_TRIG The module provides one PON_TRIG pin. Drive PON_TRIG high and keep it high to wake up the module from PSM. PON_TRIG is pulled down by default. Table 13: Pin Definition of PON_TRIG Pin Name Pin No. I/O Description Comment PON_TRIG 96 DI Used for main UART function control and for entering/exiting e-l-DRX, PSM, sleep or power off mode. 1.8 V power domain. Pulled down by default. PON_TRIG has the following functions:

Makes the module enter or exit e-l-DRX, PSM, sleep or power off mode. Enables/disables the main UART interface communication function. Turns on/off the module. PON_TRIG must be designed to allow for external control. A reference circuit is shown in the following figure. Figure 21: PON_TRIG Reference Circuit 1 In addition, a voltage divider circuit can be used to control PON_RIG. The voltage domain of the external host and the voltage divider resistor should be selected with care. A voltage divider circuit in the 3.3 V host voltage domain is shown in the following figure. BG95xA-GL_Hardware_Design 47 / 102 LPWA Module Series Figure 22: PON_TRIG Reference Circuit 2 NOTE 1. VDD_1V8 is provided by an external LDO. 2. 3. If the hosts voltage domain is not 3.3 V, the value of the voltage divider resistors should be tested according to your actual application. Inside the module, PON_TRIG is connected in series with a diode and connected in parallel with a 10 k pull-down resistor to the ground. Therefore, the actual voltage divider value needs to be measured. The following is a brief description of PON_TRIG use. PON_TRIG is pulled down by default. Before the module is turned on, PON_TRIG must be pulled up. Otherwise, the main UART interface will be inaccessible. When the module is powered on, pull down PON_TRIG within 200 ms after sending AT+QPOWED or driving PWRKEY low, after which the module will execute the power-down procedure. For more details, see Chapter 3.9. After sending AT+QPSMS to enable PSM, driving PON_TRIG low will set the module to PSM. Drive PON_TRIG high and keep it high, the module will wake up from PSM. In this case, PON_TRIG must remain high, otherwise the module will re-enter PSM. Pull down PON_TRIG and keep it low in e-l-DRX, PSM, sleep or power off mode. In other cases, pull up PON_TRIG and keep it high to make sure the main UART is accessible. For details about PON_TRIG use in e-l-DRX and sleep modes, see Chapter 3.4 and Chapter 3.5 respectively. BG95xA-GL_Hardware_Design 48 / 102 LPWA Module Series 4 Application Interfaces 4.1. (U)SIM Interface BG95xA-GL module supports 1.8 V (U)SIM card only. The circuitry of (U)SIM interfaces meet ETSI and IMT-2000 requirements. BG953A-GL supports integrated iSIM. After enabling this function, you do not need to design the (U)SIM interface, which helps to improve the security of the device and reduce the PCB area. For more details about iSIM function, please contact with local network service providers. Table 14: (U)SIM Interface Pin Definition Pin Name Pin No. I/O Description Comment USIM_DET 42 DI

(U)SIM card hot-plug detect USIM_VDD USIM_RST USIM_DATA USIM_CLK USIM_GND 43 44 45 46 47 PO

(U)SIM card power supply DO

(U)SIM card reset DIO

(U)SIM card data 1.8 V power domain. DO

(U)SIM card clock

Specified ground for (U)SIM card

1.8 V power domain. If unused, keep this pin open. Only 1.8 V (U)SIM card is supported. BG95xA-GL module supports (U)SIM card hot-plug via USIM_DET, and both high-level and low-level detections are supported. The function is disabled by default. See AT+QSIMDET in document [3] for more details. The following figure illustrates a reference design of (U)SIM interface with an 8-pin (U)SIM card connector. BG95xA-GL_Hardware_Design 49 / 102 LPWA Module Series Figure 23: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, keep USIM_DET unconnected. A reference circuit for

(U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure. Figure 24: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector To enhance the reliability and availability of the (U)SIM card in applications, follow the criteria below in the

(U)SIM circuit design:

Place the (U)SIM card connector as close as possible to the module with a trace shorter than 200 mm. Keep (U)SIM card signals away from RF and power supply traces. BG95xA-GL_Hardware_Design 50 / 102 LPWA Module Series Ensure a short and wide ground trace between the module and the (U)SIM card connector. Keep the ground and USIM_VDD traces at least 0.5 mm wide to maintain the same electric potential. Make sure the bypass capacitor between USIM_VDD and USIM_GND is less than 1 F, and place it as close to the (U)SIM card connector as possible. If the system ground plane is complete, USIM_GND can be directly connected to the system ground. To avoid cross-talk between USIM_DATA and USIM_CLK, keep their traces away from each other and shield them with ground. USIM_RST should also be shielded with ground. To offer good ESD protection, is recommended to add a TVS diode array with parasitic capacitance not exceeding 15 pF. It is recommended to reserve 0 series resistors for the (U)SIM signals of the module to facilitate debugging. The 33 pF capacitors are used for filtering interference of EGSM900. Note that the (U)SIM peripheral circuit should be close to the (U)SIM card connector. it The pull-up resistor on USIM_DATA trace can improve anti-jamming capability, and should be placed close to the (U)SIM card connector. 4.2. USB Interface The module features one integrated USB (Universal Serial Bus) interface that complies with the USB 2.0 specification and supports full speed mode only. This USB interface is used for AT command communication, data transmission, software debugging and firmware upgrade*. The USB interface pin definition is presented in the following table. Table 15: USB Interface Pin Definition Pin Name Pin No. I/O Description Comment USB_VBUS USB_DP 8 9 AI USB connection detect Typ. 5.0 V AIO USB differential data (+) USB_DM 10 AIO USB differential data (-) Compliant with the USB 2.0 standard specification. Requires differential impedance of 90 . It is recommended to reserve test points for debugging and firmware upgrading* in your designs. BG95xA-GL_Hardware_Design 51 / 102 LPWA Module Series Figure 25: Reference Circuit of USB Application To ensure USB data signal integrity, if possible, reserve a 0 resistor on USB_DP and USB_DM traces, respectively. Resistors R1 and R2 should be placed close to the module and to each other. The extra trace stubs must be as short as possible. To meet USB 2.0 specification, comply with the following principles in USB interface designing. It is important to route the USB signal traces as a differential pair with ground. The impedance of the USB differential trace is 90 . Do not route signal traces under crystals, oscillators, magnetic devices, and RF signal traces. It is important to route the USB differential traces in inner layers of the PCB, and surround the traces with ground on that layer and with ground planes above and below. Junction capacitance of the ESD protection components might influence USB data traces, so pay attention to device selection. Typically, the stray capacitance should be less than 2 pF. Keep the ESD protection components as close to the USB connector as possible. If possible, reserve a 0 resistor on USB_DP and USB_DM traces, respectively. For more details about the USB specifications, visit http://www.usb.org/home. NOTE 1. After the module is turned off or enters PSM, do not pull up any USB interface pin lest it cause additional power consumption and potentially damage pins on the module. 2. For more details about using the UMTS&LTE EVB board to test the USB interface function of the module, see document [7]. BG95xA-GL_Hardware_Design 52 / 102 LPWA Module Series 4.3. UART Interfaces BG950A-GL, BG953A-GL and BG955A-GL module provides four UART interfaces: one main UART interface, one debug UART interface and two CLI UART interfaces. BG951A-GL module provides four UART interfaces: one main UART, one debug UART, one CLI UART and one GNSS UART interface. Main UART:

It supports 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 and 3000000 bps baud rates. The default baud rate is 115200 bps. It is used for AT command communication and data transmission, and supports RTS and CTS hardware flow control. The default frame format is 8N1 (8 data bits, no parity, 1 stop bit). Debug UART:

It supports 921600 bps baud rate by default, and is used for RF calibration and log output, and supports RTS and CTS hardware flow control. The default frame format is 8N1 (8 data bits, no parity, 1 stop bit). CLI UART 8:

It supports 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 and 3000000 bps baud rates. The default baud rate is 115200 bps. It is used for firmware upgrade, software debugging, log output, GNSS data and NMEA sentence output, and supports RTS and CTS hardware flow control. The default frame format is 8N1 (8 data bits, no parity, 1 stop bit). GNSS UART (Only Supported by BG951A-GL):

The GNSS UART interface supports 115200 bps baud rate by default, and it is used for GNSS data, GNSS NMEA sentence output and GNSS firmware upgrade. The following tables show the pin definition of four UART interfaces. Table 16: Main UART Interface Pin Definition Pin Name Pin No. I/O Description Comment MAIN_DTR MAIN_RXD MAIN_TXD 30 34 35 DI DI Main UART data terminal ready Main UART reception DO Main UART transmission 1.8 V power domain. If unused, keep these pins open. 8 BG951A-GL only supports one CLI UART interface, while BG950A-GL, BG953A-GL and BG955A-GL supports two CLI UART interfaces, more precisely, pin 27 (CLI_TXD1) and pin 28 (CLI_RXD1) are connected to pin 95 (CLI_TXD2) and pin 94 (CLI_RXD2) respectively inside the module. BG95xA-GL_Hardware_Design 53 / 102 LPWA Module Series MAIN_CTS MAIN_RTS MAIN_DCD MAIN_RI 36 37 38 39 DO DI DO DO DTE clear to send signal from DCE

(Connect to DTEs CTS) DTE request to send signal from DCE (Connect to DTEs RTS) Main UART data carrier detection Main UART ring indication Table 17: Debug UART Interface Pin Definition Pin Name Pin No. I/O Description Comment DBG_TXD DBG_RXD 23 22 DO Debug UART transmission DI Debug UART reception 1.8 V power domain. If unused, keep them open. Table 18: BG950A-GL & BG953A-GL & BG955A-GL CLI UART Interface Pin Definition Pin Name Pin No. I/O Description Comment CLI_TXD2 CLI_RXD2 CLI_TXD1 CLI_RXD1 95 94 27 28 DO CLI UART2 transmission DI CLI UART2 reception DO CLI UART1 transmission DI CLI UART1 reception 1.8 V power domain. If unused, keep them open. 1.8 V power domain. If unused, keep them open. Table 19: BG951A-GL CLI UART Interface Pin Definition Pin Name Pin No. I/O Description Comment CLI_TXD CLI_RXD 95 94 DO CLI UART transmission DI CLI UART reception 1.8 V power domain. If unused, keep them open. Table 20: BG951A-GL GNSS UART Interface Pin Definition Pin Name Pin No. I/O Description Comment GNSS_TXD 27 DO GNSS UART transmission 1.8 V power domain. BG95xA-GL_Hardware_Design 54 / 102 GNSS_RXD 28 DI GNSS UART reception If unused, keep them open. LPWA Module Series NOTE AT+IPR can be used to set the baud rate of the main UART interface, and AT+IFC can be used to enable/disable the hardware flow control (the function is disabled by default). See document [3] for more details about these AT commands. The module features 1.8 V UART interfaces. A level-shifting circuit should be used if your application has a 3.3 V UART interface. It is recommended to use a level-shifting chip without internal pull-up. The voltage-level translator TXB0108PWR manufactured by Texas Instruments is recommended. The following figure shows a reference design of the main UART interface:

Figure 26: Main UART Reference Design (Translator Chip) Visit http://www.ti.com for more information. Another example with a transistor circuit is shown below. For the design of circuits shown in dotted lines, see that of circuits in solid lines, but pay attention to the direction of connection. BG95xA-GL_Hardware_Design 55 / 102 LPWA Module Series Figure 27: Main UART Reference Design (Transistor Circuit) NOTE 1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps. 2. The main UART interface should be disconnected in PSM and power off modes lest it cause 3. additional power consumption and potentially damage pins on the module. It is recommended to use a level-shifting chip without internal pull-up, such as TXB0108PWR, for level shifting. 4. Please note that the modules CTS is connected to the hosts CTS, and the modules RTS is connected to the hosts RTS. 4.4. ADC Interfaces The module provides two ADC (Analog-to-Digital Converter) interfaces. To improve the accuracy of ADC voltage values, the ADC traces should be surrounded with ground. Table 21: Pin Definition of ADC Interfaces Pin Name Pin No. I/O Description Comment ADC0 ADC1 24 2 AI AI General-purpose ADC interface General-purpose ADC interface Voltage range: 01.8 V BG95xA-GL_Hardware_Design 56 / 102 LPWA Module Series The voltage value on ADC pins can be read via AT+QADC=<port>:

AT+QADC=0: read the voltage value on ADC0. AT+QADC=1: read the voltage value on ADC1. For more details about the AT command, see document [3]. The resolution of the ADC interfaces is up to 12 bits. The following table describes the characteristic of the ADC interfaces. Table 22: Characteristics of ADC Interfaces Name Min. Typ. Voltage Range Resolution 0 6

Max. 1.8 12 Unit V bit NOTE 1. ADC input voltage must not exceed 1.8 V. 2. 3. It is prohibited to supply any voltage to the ADC pin when VBAT is removed. It is recommended to use a resistor divider circuit for ADC application, and the dividers resistor accuracy should be no less than 1 %. 4. After the module is turned off or enters PSM, do not pull up any pin of ADC interfaces lest it cause additional power consumption and potentially damage pins on the module. 4.5. Indication Signals 4.5.1. PSM Status Indication Table 23: PSM_IND Pin Definition Pin Name Pin No. I/O Description Comment PSM_IND 1 DO Indicate the modules power saving mode 1.8 V power domain. If unused, keep this pin open. When PSM is enabled, the function of PSM_IND will be activated after the module is rebooted. When PSM_IND is at a high level, the module is in a normal operation mode. When it is at a low level, the module is in PSM. BG95xA-GL_Hardware_Design 57 / 102 LPWA Module Series Figure 28: Reference Circuit of PSM Status Indication 4.5.2. Network Status Indication Table 24: Pin Definition of NET_STATUS Pin Name Pin No. I/O Description Comment NET_STATUS 21 DO Indicate the module's network activity status 1.8 V power domain. If unused, keep this pin open. The network indication pin can be used to drive network status indication LEDs. The module features one network indication pin: NET_STATUS. The pin definition and logic level changes in different network status are outlined in the following table. Table 25: Working State of Network Connection Status Indication Pin Name Status Description Flicker slowly (200 ms High/1800 ms Low) Network searching NET_STATUS Flicker slowly (1800 ms High/200 ms Low) Idle Flicker quickly (125 ms High/125 ms Low) Data transfer is ongoing A reference circuit is shown in the following figure. BG95xA-GL_Hardware_Design 58 / 102 LPWA Module Series Figure 29: Reference Circuit of Network Status Indication 4.5.3. STATUS The STATUS pin is an open-drain output for indicating the modules operation status. It will output a high level once the module is powered on successfully. Table 26: STATUS Pin Definition Pin Name Pin No. I/O Description Comment STATUS 20 DO Indicate the modules operation status 1.8 V power domain A reference circuit is shown below. Figure 30: Reference Circuit of STATUS BG95xA-GL_Hardware_Design 59 / 102 LPWA Module Series 4.5.4. MAIN_RI AT+QCFG= "risignaltype","physical" can be used to configure MAIN_RI behavior. No matter on which port a URC is presented, the URC will trigger the behavior of MAIN_RI. Table 27: MAIN_RI Pin Definition Pin Name Pin No. I/O Description Comment MAIN_RI 39 DO Main UART ring indication 1.8 V power domain. If unused, keep this pin open. The default MAIN_RI behaviors can be configured flexibly with AT+QCFG="urc/ri/ring". See document [2] for details. The default behavior of the MAIN_RI is shown below. Table 28: MAIN_RI Default Behaviors Response MAIN_RI remains at a high level. MAIN_RI outputs a 120 ms low pulse when a new URC is returned. State Idle URC NOTE A URC can be outputted from the main UART interface (default), the debug UART or EMUX ports by configuring URC indication option with AT+QURCCFG. See document for details about AT+QURCCFG.

[3]

4.6. GRFC Interfaces The module has two generic RF control interfaces for the control of external antenna tuners. Table 29: GRFC Interface Pin Definitions Pin Name Pin No. I/O Description Comment GRFC1 GRFC2 83 84 DO DO Generic RF controller Generic RF controller 1.8 V power domain. If unused, keep them open. BG95xA-GL_Hardware_Design 60 / 102 LPWA Module Series Table 30: GRFC Interface Truth Table GRFC1 Level GRFC2 Level Frequency Range (MHz) Low Low High Low High Low 8802200 791879.9 698790.9 4.7. GPIO Interface The module has nine general-purpose input and output (GPIO) interfaces. AT+QCFG="gpio" can be used to configure the status of GPIO pins. For more details about the AT command, see document [2]. Table 31: GPIO Interface Pin Definitions Pin Name Pin No. I/O Description Comment GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 25 26 64 65 66 85 86 87 88 DIO DIO DIO DIO DIO DIO DIO DIO DIO General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output 1.8 V power domain. General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output BG95xA-GL_Hardware_Design 61 / 102 LPWA Module Series 4.8. GNSS Control and Indication Interfaces On BG951A-GL module, the GNSS chip is independent of the baseband chip, therefore BG951A-GL module supports the following additional GNSS control and indication pins compared with BG950A-GL/BG953A-GL/BG955A-GL. Table 32: Pin Definition of GNSS Control and Indication Interfaces Pin Name Pin No. I/O Description Comment GNSS_BOOT 75 GNSS_NRST GNSS_EN 76 97 Force the GNSS chip of the module into emergency download mode Reset the GNSS chip;

Active high Enable internal GNSS chip DI DI DI SFNIND_1PPS 98 DO One pulse per second 1.8 V power domain. If unused, keep these pins open. Synchronized with the NMEA sentences output time at the rising edge. Pulse width: 100 ms. If unused, keep it open. GNSS_EN is used to enable the LDO that powers the GNSS chip internally. In addition, this LDO can be enabled via the GPIO pins of the internal baseband chip. Pulling up GNSS_EN will power on the GNSS chip. After the module is turned on, the external host can send AT+QGPS=1 to the GNSS chip via the GNSS UART interface to enable the GNSS function, and then the GNSS chip will output the NEMA sentences from the GNSS UART interface. GNSS_BOOT is used to upgrade the firmware of the GNSS chip. First, pull up GNSS_BOOT, and then pull up GNSS_EN to supply power for the GNSS chip. After the module is turned on, the GNSS chip will enter the boot mode. At this time, you can use the QFlash tool to update the GNSS firmware. After the update is completed, pull down GNSS_BOOT. 1PPS output via SFNIND_1PPS is disabled by default. You can enable it with AT+QGPSPPS=1. BG95xA-GL_Hardware_Design 62 / 102 LPWA Module Series 5 RF Specifications 5.1. Cellular Network 5.1.1. Antenna Interface & Frequency Bands The pin definition is shown below:

Table 33: Pin Definition of Cellular Network Interface Pin Name Pin No. I/O Description Comment ANT_MAIN 60 AIO Main antenna interface 50 impedance Table 34: Operating Frequency Operating Frequency Transmit (MHz) Receive (MHz) LTE HD-FDD B1 19201980 LTE HD-FDD B2 18501910 LTE HD-FDD B3 17101785 LTE HD-FDD B4 17101755 LTE HD-FDD B5 LTE HD-FDD B8 LTE HD-FDD B12 LTE HD-FDD B13 LTE HD-FDD B17 9 LTE HD-FDD B18 824849 880915 699716 777787 704716 815830 9 LTE HD-FDD B17 is supported by Cat NB2* only. 21102170 19301990 18051880 21102155 869894 925960 729746 746756 734746 860875 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz BG95xA-GL_Hardware_Design 63 / 102 LPWA Module Series LTE HD-FDD B19 LTE HD-FDD B20 830845 832862 875890 791821 LTE HD-FDD B25 18501915 19301995 LTE HD-FDD B26 10 LTE HD-FDD B27 10 LTE HD-FDD B28 814849 807824 703748 859894 852869 758803 LTE HD-FDD B66 17101780 21102180 MHz MHz MHz MHz MHz MHz MHz 5.1.2. Tx Power The Tx power of the module is presented in the following table. Table 35: RF Output Power Frequency Bands Max. Tx Power Min. Tx Power LTE HD-FDD:

B1/B2/B3/B4/B5/B8/B12/B13/B17 9/B18/B19/

B20/B25/B26 10/B27 10/B28/B66 GSM850/EGSM900 DCS1800/PCS1900 23 dBm 2.7 dB

< -39 dBm 33 dBm 2 dB 5 dBm 5 dB 30 dBm 2 dB 0 dBm 5 dB 5.1.3. Rx Sensitivity 10 LTE HD-FDD B26 and B27 are supported by Cat M1 only. BG95xA-GL_Hardware_Design 64 / 102 LPWA Module Series The conducted Rx sensitivity of the module is presented in the following table. Table 36: Conducted RF Receiving Sensitivity of BG950A-GL/BG951A-GL Frequency Band Primary Diversity Sensitivity (dBm) Cat M1/3GPP Cat NB1 11/3GPP LTE HD-FDD B1 LTE HD-FDD B2 LTE HD-FDD B3 LTE HD-FDD B4 LTE HD-FDD B5 LTE HD-FDD B8 LTE HD-FDD B12 LTE HD-FDD B13

-105.3/-102.3

-114/-107.5

-105.3/-100.3

-114/-107.5

-104.3/-99.3

-113/-107.5

-105.3/-102.3

-114/-107.5

-105.8/-100.8

-115/-107.5

-105.8/-99.8

-115/-107.5

-105.3/-99.3

-114/-107.5

-105.3/-99.3

-114/-107.5 LTE HD-FDD B17 12 Supported

-114/-107.5 LTE HD-FDD B18 LTE HD-FDD B19 LTE HD-FDD B20 LTE HD-FDD B25 LTE HD-FDD B26 13 LTE HD-FDD B27 13 LTE HD-FDD B28 LTE HD-FDD B66

-106.3/-102.3

-115/-107.5

-106.3/-102.3

-115/-107.5

-105.8/-99.8

-114/-107.5

-104.8/-100.3

-114/-107.5

-106.3/-100.3

-106.3/-100.8

-105.8/-100.8

-114/-107.5

-104.8/-101.8

-114/-107.5 11 LTE Cat NB1 receiving sensitivity without repetitions. 12 LTE HD-FDD B17 is supported by Cat NB2* only. 13 LTE HD-FDD B26 and B27 are supported by Cat M1 only. BG95xA-GL_Hardware_Design 65 / 102 Table 37: Conducted RF Receiving Sensitivity of BG955A-GL LPWA Module Series Frequency Band Primary Diversity GSM850/EGSM900 Supported DCS1800/PCS1900 Supported

Frequency Band Primary Diversity LTE HD-FDD B1 LTE HD-FDD B2 LTE HD-FDD B3 LTE HD-FDD B4 LTE HD-FDD B5 LTE HD-FDD B8 LTE HD-FDD B12 LTE HD-FDD B13 GSM/3GPP Sensitivity (dBm) TBD/-102 TBD/-102 Cat M1/3GPP Sensitivity (dBm) Cat NB1 14/3GPP Sensitivity (dBm) TBD/-102.3 TBD/-107.5 TBD/-100.3 TBD/-107.5 TBD/-99.3 TBD/-107.5 TBD/-102.3 TBD/-107.5 TBD/-100.8 TBD/-107.5 TBD/-99.8 TBD /-107.5 TBD/-99.3 TBD/-107.5 TBD/-99.3 TBD/-107.5 LTE HD-FDD B17 15 Supported

TBD/-107.5 LTE HD-FDD B18 LTE HD-FDD B19 LTE HD-FDD B20 LTE HD-FDD B25 LTE HD-FDD B26 16 LTE HD-FDD B27 13 LTE HD-FDD B28 LTE HD-FDD B66 TBD/-102.3 TBD/-107.5 TBD/-102.3 TBD/-107.5 TBD/-99.8 TBD/-107.5 TBD/-100.3 TBD/-107.5 TBD/-100.3 TBD/-100.8

TBD/-100.8 TBD/-107.5 TBD/-101.8 TBD/-107.5 14 LTE Cat NB1 receiving sensitivity without repetitions. 15 LTE HD-FDD B17 is supported by Cat NB2* only. 16 LTE HD-FDD B26 and B27 are supported by Cat M1 only. BG95xA-GL_Hardware_Design 66 / 102 LPWA Module Series 5.1.4. Reference Design It is recommended to reserve a -type matching circuit for better RF performance, and the -type matching components (R1, C1 and C2) should be placed as close to the antenna as possible. The capacitors are not mounted by default. Figure 31: Reference Circuit of Main Antenna Interface 5.2. GNSS BG950A-GL, BG953A-GL and BG955A-GL module features a fully integrated GNSS solution that supports GPS and GLONASS. BG951A-GL module has an independent GNSS solution that supports GPS, GLONASS, BDS, Galileo and QZSS. The modules support standard NMEA 0183 protocol. BG950A-GL, BG953A-GL and BG955A-GL outputs GNSS NMEA sentences via the CLI UART interfaces. BG951A-GL outputs NMEA sentences via the GNSS UART interface. Data update rate for both modules: 110 Hz; 1 Hz by default. GNSS engine is switched off by default. It must be switched on via AT command. BG950A-GL, BG953A-GL and BG955A-GL does not support concurrent operation of LTE and GNSS, while BG951A-GL does. For more details about GNSS engine technology and configurations, see document [4]. 5.2.1. Antenna Interface & Frequency Bands The pin definition, frequency bands, and performance of GNSS antenna interface are presented in the following table shows. BG95xA-GL_Hardware_Design 67 / 102 LPWA Module Series Table 38: Pin Definition of GNSS Antenna Interface Pin Name Pin No. ANT_GNSS 49 I/O AI Description Comment GNSS antenna interface 50 impedance Table 39: BG950A-GL & BG953A-GL & BG955A-GL GNSS Frequency Type GPS Frequency 1575.42 1.023 GLONASS 1597.51605.8 Table 40: BG951A-GL GNSS Frequency Type GPS Frequency 1575.42 1.023 GLONASS 1597.51605.8 BDS Galileo QZSS 1561.098 2.046 1575.42 2.046 1575.42 1.023 Unit MHz MHz Unit MHz MHz MHz MHz MHz 5.2.2. GNSS Performance Table 41: BG950A-GL & BG953A-GL GNSS Performance Parameter Description Conditions Cold start Autonomous Sensitivity Reacquisition Autonomous Tracking TTFF Cold start @ open sky Autonomous Autonomous XTRA enabled Typ.

-145

-154

-159 29.42 TBD Unit dBm s BG95xA-GL_Hardware_Design 68 / 102 LPWA Module Series Warm start @ open sky Hot start @ open sky Autonomous XTRA enabled Autonomous XTRA enabled Accuracy CEP-50 Autonomous @ open sky Table 42: BG951A-GL GNSS Performance Parameter Description Conditions Acquisition Autonomous Sensitivity Reacquisition Autonomous Tracking Cold start @ open sky TTFF Warm start @ open sky Hot start @ open sky Autonomous Autonomous XTRA enabled Autonomous XTRA enabled Autonomous XTRA enabled 28.38 TBD 1.07 TBD 2.0 Typ.

-145

-145

-160 34 TBD 36 TBD 1 TBD m Unit dBm s Accuracy CEP-50 Autonomous @ open sky 0.76 m Table 43: BG955A-GL GNSS Performance Parameter Description Conditions Acquisition Autonomous Sensitivity Reacquisition Autonomous Tracking TTFF Cold start @ open sky Autonomous Autonomous XTRA enabled Typ. TBD TBD TBD TBD TBD Unit dBm s BG95xA-GL_Hardware_Design 69 / 102 LPWA Module Series Warm start @ open sky Hot start @ open sky Autonomous XTRA enabled Autonomous XTRA enabled TBD TBD TBD TBD Accuracy CEP-50 Autonomous @ open sky TBD m NOTE 1. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain a lock

(keep positioning for at least 3 minutes continuously). 2. Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain a lock within 3 minutes after loss of lock. 3. Acquisition sensitivity: the minimum GNSS signal power at which the module can fix a position successfully within 3 minutes after executing cold start command. 5.2.3. Reference Design The following is the reference design of GNSS antenna. Figure 32: Reference Design of GNSS Antenna Interface

. NOTE The module is designed with a built-in LNA, and supports passive GNSS antennas only. Active antennas and external LNAs are not supported. BG95xA-GL_Hardware_Design 70 / 102 LPWA Module Series 5.3. Layout Guidelines The following layout guidelines should be taken into account in application designs. Maximize the distance between the GNSS antenna and the main antenna. Digital circuits such as (U)SIM card, USB interface, camera module, display connector, and SD card should be kept away from antennas. Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar isolation and protection. Keep 50 characteristic impedance for the ANT_GNSS trace. Refer to Chapter 5.2 for GNSS antenna reference design and antenna installation information. 5.4. RF Routing Guidelines For users PCB, the characteristic impedance of all RF traces should be 50 . The impedance of the RF traces is usually determined by trace width (W), the materials dielectric constant, the height from the reference ground to the signal layer (H), and the space between RF traces and grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance. The following are reference designs of microstrip or coplanar waveguides with different PCB structures. Figure 33: Microstrip Design on a 2-Layer PCB BG95xA-GL_Hardware_Design 71 / 102 LPWA Module Series Figure 34: Coplanar Waveguide Design on a 2-Layer PCB Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 36: Coplanar Waveguide Design on a 4-Layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, follow the principles below in RF layout design:

BG95xA-GL_Hardware_Design 72 / 102 LPWA Module Series Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 . The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground. The distance between the RF pins and the RF connector should be as short as possible and all the right-angle traces should be changed to curved ones. The recommended trace angle is 135. There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be at least two times the width of RF signal traces (2 W). Keep RF traces away from interference sources, and avoid intersection and paralleling between traces on adjacent layers. For more details about RF layout, see document [5]. 5.5. Antenna Design Requirements Table 44: Antenna Design Requirements Antenna Type Requirements GNSS LTE Must be a passive antenna Frequency range: 15591609 MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0 dBi VSWR: 2 Efficiency: > 30 %

Gain: 1 dBi Max input power: 50 W Input impedance: 50 Polarization: vertical Cable insertion loss:

< 1 dB: LB (< 1 GHz)

< 1.5 dB: MB (12.3 GHz) BG95xA-GL_Hardware_Design 73 / 102 LPWA Module Series 5.6. RF Connector Recommendation If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector provided by Hirose. Figure 37: Dimensions of the Receptacle (Unit: mm) The mated plugs listed in the following figure can be used to match the U.FL-R-SMT connector. Figure 38: Specifications of Mated Plugs The following figure describes the space factor of the mated connectors. BG95xA-GL_Hardware_Design 74 / 102 LPWA Module Series Figure 39: Space Factor of Mated Connectors (Unit: mm) For more details, visit http://www.hirose.com. BG95xA-GL_Hardware_Design 75 / 102 LPWA Module Series 6 Reliability and Electrical 7 Characteristics 7.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 45: Absolute Maximum Ratings Parameter VBAT_RF/VBAT_BB USB_VBUS Voltage at Digital Pins Min.

-0.2

-0.3

-0.3 Max. 4.5 5.5 2.0 Unit V V V 7.2. Power Supply Ratings Table 46: BG950A-GL & BG951A-GL & BG953A-GL Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT_BB/

VBAT_RF USB_VBUS Power supply for the modules baseband part/RF part The actual input voltages must stay between the minimum and maximum values. USB connection detect

2.2 3.3 4.35 V

5.0

V BG95xA-GL_Hardware_Design 76 / 102 LPWA Module Series Table 47: BG955A-GL Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT_BB/

VBAT_RF USB_VBUS Power supply for the modules baseband part/RF part The actual input voltages must stay between the minimum and maximum values. USB connection detect

3.3 3.8 4.3

5.0

V V 7.3. Power Consumption 7.3.1. BG950A-GL Power Consumption Table 48: BG950A-GL Power Consumption (Power Supply: 3.3 V, Room Temperature) Description Conditions Avg. Max. Unit Leakage PSM Power-off @ USB/UART disconnected PSM @ USB/UART disconnected Rock bottom AT+CFUN=0 @ Sleep mode Sleep mode

(USB disconnected) LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s LTE Cat M1 e-I-DRX = 40.96 s

@ PTW = 1.28 s, DRX = 1.28 s LTE Cat M1 e-I-DRX = 40.96 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 1.28 s, DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 40.96 s 1.5 1.5 39 1.1 2.2 0.09 0.12 0.07 0.09 0.19

A A A mA mA mA mA mA mA mA BG95xA-GL_Hardware_Design 77 / 102 Idle state

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE HD-FDD B1 @ 23.01 dBm LTE HD-FDD B2 @ 23.04 dBm LTE HD-FDD B3 @ 23.03 dBm LTE HD-FDD B4 @ 23.03 dBm LTE HD-FDD B5 @ 23.08 dBm LTE HD-FDD B8 @ 23.02 dBm LTE HD-FDD B12 @ 23.01 dBm LTE Cat M1 data transfer (GNSS OFF) LTE HD-FDD B13 @ 23.03 dBm LTE HD-FDD B18 @ 23.04 dBm LTE HD-FDD B19 @ 23.16 dBm LTE HD-FDD B20 @ 23.02 dBm LTE HD-FDD B25 @ 23.06 dBm LTE HD-FDD B26 @ 23.07 dBm LTE HD-FDD B27 @ 23.09 dBm LTE HD-FDD B28 @ 22.99 dBm LTE HD-FDD B66 @ 22.78 dBm LTE Cat NB1 data transfer (GNSS OFF) LTE HD-FDD B1 @ 23.19 dBm LTE HD-FDD B2 @ 23.01 dBm LPWA Module Series 0.15 15.0 16.0 15.0 15.0 242 224 207 208 208 220 204 199 201 209 211 236 209 201 200 209 247 222

657 596 535 533 544 607 521 514 528 548 555 628 544 519 504 536 700 588 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA BG95xA-GL_Hardware_Design 78 / 102 LTE HD-FDD B3 @ 23.10 dBm LTE HD-FDD B4 @ 23.09 dBm LTE HD-FDD B5 @ 23.03 dBm LTE HD-FDD B8 @ 23.10 dBm LTE HD-FDD B12 @ 23.09 dBm LTE HD-FDD B13 @ 23.20 dBm LTE HD-FDD B17 @ 23.06 dBm LTE HD-FDD B18 @ 23.19 dBm LTE HD-FDD B19 @ 23.20 dBm LTE HD-FDD B20 @ 23.15 dBm LTE HD-FDD B25 @ 23.17 dBm LTE HD-FDD B28 @ 23.12 dBm LTE HD-FDD B66 @ 22.82 dBm LPWA Module Series 208 203 204 223 194 185 191 197 200 209 220 187 205 548 541 532 608 529 499 515 530 541 570 585 506 554 mA mA mA mA mA mA mA mA mA mA mA mA mA 7.3.2. BG951A-GL Power Consumption Table 49: BG951A-GL Power Consumption (Power Supply: 3.3 V, Room Temperature) Description Conditions Avg. Max. Unit Leakage PSM Power-off @ USB/UART disconnected PSM @ USB/UART disconnected Rock bottom AT+CFUN=0 @ Sleep mode Sleep mode

(USB disconnected) LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s LTE Cat M1 e-I-DRX = 40.96 s

@ PTW = 1.28 s, DRX = 1.28 s LTE Cat M1 e-I-DRX = 40.96 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat M1 1.5 1.5 42 1.1 2.2 0.09 0.12 0.08

A A A mA mA mA mA mA BG95xA-GL_Hardware_Design 79 / 102 e-I-DRX = 81.92 s

@ PTW = 1.28 s, DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 40.96 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE HD-FDD B1 @ 23.01 dBm LTE HD-FDD B2 @ 23.04 dBm LTE HD-FDD B3 @ 23.03 dBm LTE HD-FDD B4 @ 23.03 dBm LTE HD-FDD B5 @ 23.08 dBm LTE HD-FDD B8 @ 23.02 dBm LTE HD-FDD B12 @ 23.01 dBm LTE HD-FDD B13 @ 23.03 dBm LTE HD-FDD B18 @ 23.04 dBm LTE HD-FDD B19 @ 23.16 dBm LTE HD-FDD B20 @ 23.02dBm LTE HD-FDD B25 @ 23.06 dBm LTE HD-FDD B26 @ 23.07 dBm LTE HD-FDD B27 @ 23.09 dBm LPWA Module Series 0.10 0.18 0.14 17.0 17.0 16.0 16.0 242 224 207 208 208 220 204 199 201 209 211 236 209 201 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA

657 596 535 533 544 607 521 514 528 548 555 628 544 519 Idle state LTE Cat M1 data transfer

(GNSS OFF) BG95xA-GL_Hardware_Design 80 / 102 LTE HD-FDD B28 @ 22.99 dBm LTE HD-FDD B66 @ 22.78 dBm LTE HD-FDD B1 @ 23.19 dBm LTE HD-FDD B2 @ 23.01 dBm LTE HD-FDD B3 @ 23.10 dBm LTE HD-FDD B4 @ 23.09 dBm LTE HD-FDD B5 @ 23.03 dBm LTE HD-FDD B8 @ 23.10 dBm LTE HD-FDD B12 @ 23.09 dBm LTE HD-FDD B13 @ 23.20 dBm LTE HD-FDD B17 @ 23.06 dBm LTE HD-FDD B18 @ 23.19 dBm LTE HD-FDD B19 @ 23.20 dBm LTE HD-FDD B20 @ 23.15 dBm LTE HD-FDD B25 @ 23.17 dBm LTE HD-FDD B28 @ 23.12 dBm LTE HD-FDD B66 @ 22.82 dBm LPWA Module Series 200 209 247 222 208 203 204 223 194 185 191 197 200 209 220 187 205 504 536 700 588 548 541 532 608 529 499 515 530 541 570 585 506 554 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA LTE Cat NB1 data transfer

(GNSS OFF) 7.3.3. BG953A-GL Power Consumption Table 50: BG953A-GL Power Consumption (Power Supply: 3.3 V, Room Temperature) Description Conditions Avg. Max. Unit Leakage PSM Power-off @ USB/UART disconnected PSM @ USB/UART disconnected Rock bottom AT+CFUN=0 @ Sleep mode Sleep mode

(USB disconnected) LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s 1.5 1.5 TBD TBD TBD

A A A mA mA BG95xA-GL_Hardware_Design 81 / 102 LTE Cat M1 e-I-DRX = 40.96 s

@ PTW = 1.28 s, DRX = 1.28 s LTE Cat M1 e-I-DRX = 40.96 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 1.28 s, DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 40.96 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE HD-FDD B1 @ 23.01 dBm LTE HD-FDD B2 @ 23.04 dBm LTE HD-FDD B3 @ 23.03 dBm LTE HD-FDD B4 @ 23.03 dBm Idle state LTE Cat M1 data transfer (GNSS OFF) LTE HD-FDD B5 @ 23.08 dBm LTE HD-FDD B8 @ 23.02 dBm LTE HD-FDD B12 @ 23.01 dBm LTE HD-FDD B13 @ 23.03 dBm LTE HD-FDD B18 @ 23.04 dBm LTE HD-FDD B19 @ 23.16 dBm LPWA Module Series TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA BG95xA-GL_Hardware_Design 82 / 102 LTE HD-FDD B20 @ 23.02 dBm LTE HD-FDD B25 @ 23.06 dBm LTE HD-FDD B26 @ 23.07 dBm LTE HD-FDD B27 @ 23.09 dBm LTE HD-FDD B28 @ 22.99 dBm LTE HD-FDD B66 @ 22.78 dBm LTE HD-FDD B1 @ 23.19 dBm LTE HD-FDD B2 @ 23.01 dBm LTE HD-FDD B3 @ 23.10 dBm LTE HD-FDD B4 @ 23.09 dBm LTE HD-FDD B5 @ 23.03 dBm LTE HD-FDD B8 @ 23.10 dBm LTE HD-FDD B12 @ 23.09 dBm LTE HD-FDD B13 @ 23.20 dBm LTE HD-FDD B17 @ 23.06 dBm LTE HD-FDD B18 @ 23.19 dBm LTE HD-FDD B19 @ 23.20 dBm LTE HD-FDD B20 @ 23.15 dBm LTE HD-FDD B25 @ 23.17 dBm LTE HD-FDD B28 @ 23.12 dBm LTE HD-FDD B66 @ 22.82 dBm LPWA Module Series TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA LTE Cat NB1 data transfer (GNSS OFF) 7.3.4. BG955A-GL Power Consumption BG95xA-GL_Hardware_Design 83 / 102 Table 51: BG955A-GL Power Consumption (Power Supply: 3.8 V, Room Temperature) Description Conditions Avg. Max. Unit LPWA Module Series Leakage PSM Power-off @ USB/UART disconnected PSM @ USB/UART disconnected Rock bottom AT+CFUN=0 @ Sleep mode LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s LTE Cat M1 e-I-DRX = 40.96 s

@ PTW = 1.28 s, DRX = 1.28 s LTE Cat M1 e-I-DRX = 40.96 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 1.28 s, DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 40.96 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat M1 DRX = 1.28 s LTE Cat NB1 DRX = 1.28 s LTE Cat M1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE Cat NB1 e-I-DRX = 81.92 s

@ PTW = 2.56 s, DRX = 1.28 s LTE HD-FDD B1 @ 23.01 dBm LTE HD-FDD B2 @ 23.04 dBm LTE HD-FDD B3 @ 23.03 dBm Sleep mode

(USB disconnected) Idle state LTE Cat M1 data transfer (GNSS OFF) 1.5 1.5 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

TBD TBD TBD A A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA BG95xA-GL_Hardware_Design 84 / 102 LTE HD-FDD B4 @ 23.03 dBm LTE HD-FDD B5 @ 23.08 dBm LTE HD-FDD B8 @ 23.02 dBm LTE HD-FDD B12 @ 23.01 dBm LTE HD-FDD B13 @ 23.03 dBm LTE HD-FDD B18 @ 23.04 dBm LTE HD-FDD B19 @ 23.16 dBm LTE HD-FDD B20 @ 23.02 dBm LTE HD-FDD B25 @ 23.06 dBm LTE HD-FDD B26 @ 23.07 dBm LTE HD-FDD B27 @ 23.09 dBm LTE HD-FDD B28 @ 22.99 dBm LTE HD-FDD B66 @ 22.78 dBm LTE HD-FDD B1 @ 23.19 dBm LTE HD-FDD B2 @ 23.01 dBm LTE HD-FDD B3 @ 23.10 dBm LTE HD-FDD B4 @ 23.09 dBm LTE HD-FDD B5 @ 23.03 dBm LTE HD-FDD B8 @ 23.10 dBm LTE HD-FDD B12 @ 23.09 dBm LTE HD-FDD B13 @ 23.20 dBm LTE HD-FDD B17 @ 23.06 dBm LTE HD-FDD B18 @ 23.19 dBm LTE HD-FDD B19 @ 23.20 dBm LTE HD-FDD B20 @ 23.15 dBm LTE HD-FDD B25 @ 23.17 dBm LPWA Module Series TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA LTE Cat NB1 data transfer (GNSS OFF) BG95xA-GL_Hardware_Design 85 / 102 LPWA Module Series LTE HD-FDD B28 @ 23.12 dBm LTE HD-FDD B66 @ 22.82 dBm TBD TBD TBD TBD mA mA 7.3.5. GNSS Power Consumption Table 52: BG950A-GL GNSS Power Consumption Description Conditions Searching

(AT+CFUN=0) Tracking

(AT+CFUN=0) Cold start @ Passive antenna Hot start @ Passive antenna Lost state @ Passive antenna Instrument environment @ Passive antenna 48.44 Open sky @ Real network, Passive antenna TBD Typ. 48.19 48.63 47.97 Unit mA mA mA mA mA Table 53: BG951A-GL GNSS Power Consumption Description Conditions Typ. Unit GNSS startup non-positioning

(AT+CFUN=0 & AT+QSCLK=2) Instrument environment @ Passive antenna 3.62 Cold start @ Passive antenna Searching (AT+CFUN=0) Hot start @ Passive antenna Lost state @ Passive antenna 21.51 20.07 20.99 Tracking (AT+CFUN=0) Instrument environment @ Passive antenna 15.51 Open sky @ Real network, Passive antenna 16.50 mA mA mA mA mA mA Table 54: BG953A-GL GNSS Power Consumption Description Conditions Searching Cold start @ Passive antenna Typ. TBD Unit mA BG95xA-GL_Hardware_Design 86 / 102 LPWA Module Series

(AT+CFUN=0) Hot start @ Passive antenna Tracking

(AT+CFUN=0) Lost state @ Passive antenna Instrument environment @ Passive antenna Open sky @ Real network, Passive antenna TBD Table 55: BG955A-GL GNSS Power Consumption Description Conditions Searching

(AT+CFUN=0) Tracking

(AT+CFUN=0) Cold start @ Passive antenna Hot start @ Passive antenna Lost state @ Passive antenna Instrument environment @ Passive antenna Open sky @ Real network, Passive antenna TBD TBD TBD TBD Typ. TBD TBD TBD TBD 7.4. Digital I/O Characteristic Table 56: 1.8 V Digital I/O Requirements (U)SIM Parameter Description USIM_VDD Power supply VIH VIL VOH VOL Input high voltage Input low voltage Output high voltage Output low voltage Min. 1.7 1.26

-0.2 1.44

-0.2 Table 57: 1.8 V Digital I/O Requirements Others Parameter Description VIH Input high voltage Min. 1.26 Max. 1.9 2.0 0.54 2.0 0.36 Max. 2.0 mA mA mA mA Unit mA mA mA mA mA Unit V V V V V Unit V BG95xA-GL_Hardware_Design 87 / 102 LPWA Module Series VIL VOH VOL Input low voltage Output high voltage Output low voltage

-0.2 1.44

-0.2 0.54 2.0 0.36 V V V 7.5. ESD Protection Static electricity occurs naturally and it may damage the module. Therefore, applying proper ESD countermeasures and handling methods is imperative. For example, wear anti-static gloves during the development, production, assembly, and testing of the module; add ESD protection components to the ESD sensitive interfaces and points in the product design. Table 58: Electrostatics Discharge Characteristics (Temperature: 25 C, Humidity: 45 %) Tested Interfaces Contact Discharge Air Discharge Unit VBAT, GND Main Antenna Interfaces GNSS Antenna Interfaces 8 5 5 12 10 8 kV kV kV 7.6. Operating and Storage Temperatures BG95xA-GL_Hardware_Design 88 / 102 LPWA Module Series Table 59: Operating and Storage Temperatures Parameter Operating Temperature Range 17 Extended Temperature Range 18 Storage Temperature Range Min.

-35

-40

-40 Typ.

+25

Max. Unit

+75

+85

+90 C C C 17 Within the operating temperature range, the module meets 3GPP specifications. 18 Within the extended temperature range, the module retains the ability to establish and maintain functions such as SMS, data transmission, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may exceed the specified 3GPP tolerances. When the temperature returns to the operating temperature range, the module meets 3GPP specifications again. BG95xA-GL_Hardware_Design 89 / 102 LPWA Module Series 8 Mechanical Information This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeters (mm). The dimensional tolerances are 0.2 mm, unless otherwise specified. 8.1. Top and Side View Dimensions Figure 40: Module Top and Side Dimensions (Unit: mm) BG95xA-GL_Hardware_Design 90 / 102 LPWA Module Series 1.00 1.00 Pin1 0.25 1.90 1.10 0.50 0.25 1.10 19.900.20 0.25 1.10 0.55 1.95 1.10 5.10 1.00 0 5

. 8 0.85 1.70

. 0 2 0 0 6 3 2

. 1.00 1.70 1.00 1.70 0.70 0.25 0.55 40x1.0 62x0.7 40x1.0 62x1.10 Figure 41: Module Bottom Dimensions (Bottom View, Unit: mm) NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard. BG95xA-GL_Hardware_Design 91 / 102 8.2. Recommended Footprint LPWA Module Series 1.00 1.00 Pin1 9.95 9.15 7.45 1.10 19.900.20 9.95 9.15 7.15 1.95 0.55 1.10 0.25 1.10 1.70 2.50 1.70 1.70 0.85

. 0 2 0 0 6

. 3 2 0.15 1.70 0.85 0.25 1.70 1

. 7 0 2.55 0.85 1.00 1.10 1.00 0.70 1.10 0.25 1.10 2.50 1.10 4.25 5.95 62x0.7 4.25 5.95 40x1.0 62x1.10 40x1.0 0.25 0

. 2 0 1

. 9 0 5

. 9 5 4

. 2 5 4

. 2 5 5

. 9 5 1 1

. 8 0 1 1

. 0 0 9

. 7 0 7

. 6 5 7

. 6 5 9

. 6 0 1 1

. 0 0 1 1

. 8 0 Figure 42: Recommended Footprint (Top View, Unit: mm)

. NOTE 1. Keep at least 3 mm between the module and other components on the motherboard to improve soldering quality and maintenance convenience. 2. All reserved pins must be kept open. 3. For stencil design requirements of the module, see document [6]. BG95xA-GL_Hardware_Design 92 / 102 8.3. Top and Bottom Views LPWA Module Series Figure 43: Top & Bottom Views of BG95xA-GL NOTE Images above are for illustrative purposes only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. BG95xA-GL_Hardware_Design 93 / 102 LPWA Module Series 9 Storage, Manufacturing & Packaging 9.1. Storage Conditions The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: the temperature should be 23 5 C and the relative humidity should be 3560 %. 2. Shelf life (in a vacuum-sealed packaging): 12 months in Recommended Storage Condition. 3. Floor life: 168 hours 19 in a factory where the temperature is 23 5 C and relative humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g., a dry cabinet). 4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under the following circumstances:

The module is not stored in Recommended Storage Condition;

Violation of the third requirement mentioned above;

Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;

Before module repairing. 5. If needed, the pre-baking should follow the requirements below:

The module should be baked for 8 hours at 120 5 C;

The module must be soldered to PCB within 24 hours after the baking, otherwise it should be put in a dry environment such as in a dry cabinet. 19 This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to, or are not sure to conform to IPC/JEDEC J-STD-033. And do not remove the packages of tremendous modules if they are not ready for soldering. BG95xA-GL_Hardware_Design 94 / 102 LPWA Module Series NOTE 1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to the air is forbidden. 2. Take out the module from the package and put it on high-temperature-resistant fixtures before baking. All modules must be soldered to PCB within 24 hours of the baking, otherwise put them in the drying oven. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure. 3. Pay attention to ESD protection, such as wearing anti-static gloves, when touching the modules. 9.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the stencil surface, thus making the paste fill the stencil openings and then penetrate the PCB. Apply proper force on the squeegee to produce a clean stencil surface on a single pass. To guarantee module soldering quality, 0.130.15 mm stencil thickness for the module is recommended. For more details, see document [6]. The peak reflow temperature should be 235246 C, with 246 C as the absolute maximum reflow temperature. To avoid module damage caused by repeated heating, it is strongly recommended that the module should be mounted only after reflow soldering of the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. Figure 44: Recommended Reflow Soldering Thermal Profile BG95xA-GL_Hardware_Design 95 / 102 LPWA Module Series Table 60: Recommended Thermal Profile Parameters Factor Soak Zone Max slope Recommendation 13 C/s Soak time (between A and B: 150 C and 200 C) 70120 s Reflow Zone Max slope Reflow time (D: over 217 C) Max temperature Cooling down slope Reflow Cycle Max reflow cycle NOTE 13 C/s 4070 s 235246 C

-1.5 to 3 C/s 1 1. If the module requires conformal coating, DO NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module. 2. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the module. 3. Due to the SMT process complexity, please contact Quectel Technical Support in advance regarding any situation that you are not sure about, or any process (e.g., selective soldering, ultrasonic soldering) that is not mentioned in document [6]. 9.3. Packaging Specifications The module is delivered in a tape carrier packaging and details are as follows:

9.3.1. Carrier Tape Dimension details:

BG95xA-GL_Hardware_Design 96 / 102 LPWA Module Series Figure 45: Carrier Tape Dimension Drawing Table 61: Carrier Tape Dimension Table (Unit: mm) W 44 P 32 T A0 0.35 20.2 B0 24 K0 K1 F E 3.15 6.65 20.2 1.75 9.3.2. Plastic Reel Figure 46: Plastic Reel Dimension Drawing Table 62: Plastic Reel Dimension Table (Unit: mm) D1 330 D2 100 W 44.5 BG95xA-GL_Hardware_Design 97 / 102 9.3.3. Packing Process Place the packaged plastic reel, humidity indicator card and desiccant bag inside a vacuum bag, then vacuumize it. LPWA Module Series Place the module onto the carrier tape and use the cover tape to cover them; then wind the heat-sealed carrier tape on the plastic reel and use the protective tape for protection. One plastic reel can load 250 modules. Place the vacuum-packed plastic reel inside a pizza box. Place 4 pizza boxes inside 1 carton and seal it. One carton can pack 1000 modules. Figure 47: Packaging Process BG95xA-GL_Hardware_Design 98 / 102 LPWA Module Series 10 Appendix References Table 63: Related Documents Document Name

[1] Quectel_UMTS&LTE_EVB_User_Guide

[2] Quectel_BG77xA-GL&BG95xA-GL_QCFG_AT_Commands_Manual

[3] Quectel_BG77xA-GL&BG95xA-GL_AT_Commands_Manual

[4] Quectel_BG770A-GL&BG95xA-GL_GNSS_Application_Note

[5] Quectel_RF_Layout_Application_Note

[6] Quectel_Module_Secondary_SMT_Application_Note

[7] Quectel_BG950A-GL&BG951A-GL_TE-A_User_Guide Table 64: Terms and Abbreviations Abbreviation Description ADC BDS Balun bps CHAP CoAP CTS DFOTA DL Analog to Digital Converter BeiDou Navigation Satellite System Balanced to Unbalanced bit(s) per second Challenge Handshake Authentication Protocol Constrained Application Protocol Clear to Send Delta Firmware Upgrade Over-the-Air Downlink BG95xA-GL_Hardware_Design 99 / 102 LPWA Module Series Discontinuous Reception Extended GSM (Global System for Mobile Communications) Extended Idle Mode Discontinuous Reception Evolved Packet Core Electrostatic Discharge Evaluation Board Frequency Division Duplex FTP over SSL Global Navigation Satellite System DRX EGSM e-I-DRX EPC ESD EVB FDD FTP(S) GNSS GLONASS Global Navigation Satellite System (Russia) GPIO GPS GRFC HD HSS I/O I2C Inom LDO LED LGA LNA LPF LPWA LTE General-Purpose Input/Output Global Positioning System Generic RF Controller Half Duplex Home Subscriber Server Input/Output Inter-Integrated Circuit Nominal Current Low-Dropout Regulator Light Emitting Diode Land Grid Array Low Noise Amplifier Low Pass Filter Low-Power Wide-Area (Network) Long Term Evolution BG95xA-GL_Hardware_Design 100 / 102 LwM2M Lightweight M2M LPWA Module Series ME MO MQTT MSL MT NITZ NMEA PA PAP PCB PDU PING PMU POS PPP PSM RAU RF RFIC RHCP RoHS RTS SAW SMD Mobile Equipment Mobile Originated Message Queuing Telemetry Transport Moisture Sensitivity Levels Mobile Terminated Network Identity and Time Zone NMEA (National Marine Electronics Association) 0183 Interface Standard Power Amplifier Password Authentication Protocol Printed Circuit Board Protocol Data Unit Packet Internet Groper Power Management Unit Point of Sale Point-to-Point Protocol Power Saving Mode Routing Area Update Radio Frequency Radio Frequency Integrated Circuit Right Hand Circularly Polarized Restriction of Hazardous Substances Request to Send Surface Acoustic Wave Surface Mount Device BG95xA-GL_Hardware_Design 101 / 102 LPWA Module Series SMS SSL TAU TCP TCXO TLS TTFF Tx UART UDP UL UE URC

(U)SIM Vmax Vnom Vmin VIHmax VIHmin VILmax VILmin VOHmax VOHmin VOLmax VSWR Short Message Service Secure Sockets Layer Tracking Area Update Transmission Control Protocol Temperature Complementary Crystal Oscillator Transport Layer Security Time to First Fix Transmit Universal Asynchronous Receiver/Transmitter User Datagram Protocol Uplink User Equipment Unsolicited Result Code

(Universal) Subscriber Identity Module Maximum Voltage Nominal Voltage Minimum Voltage Maximum High-level Input Voltage Minimum High-level Input Voltage Maximum Low-level Input Voltage Minimum Low-level Input Voltage Maximum High-level Output Voltage Minimum High-level Output Voltage Maximum Low-level Output Voltage Voltage Standing Wave Ratio BG95xA-GL_Hardware_Design 102 / 102 LPWA Module Series CE Statement The minimum distance between the user and/or any bystander and the radiating structure of the transmitter is 20cm. Hereby, We, Quectel Wireless Solutions Co., Ltd. declares that the radio equipment type BG953A-GL is in compliance with the Directive 2014/53/EU. The full text of the EU declaration of conformity is available at the following internet address:

Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China https://www.quectel.com/support/downloadb/TechnicalDocuments.htm Legal InformationThis device may be operated in all member states of the EU.Observe national and local regulations where the device is used. FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met:

1. This Modular Approval is limited to OEM installation for mobile and fixed applications only. The antenna installation and operating configurations of this transmitter, including any applicable source-based time-

averaging duty factor, antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements of 2.1091. 2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the users body and must not transmit simultaneously with any other antenna or transmitter. 3.A label with the following statements must be attached to the host end product: This device contains FCC ID: XMR2023BG953AGL. 4.To comply with FCC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed:

Catm LTE Band2/25:11.000dBi Catm LTE Band4/66:8.000dBi Catm LTE Band5/26:12.541dBi BG95xA-GL_Hardware_Design 103 / 102 LPWA Module Series Catm LTE Band12:11.798dBi Catm LTE Band13:12.214dBi NB LTE Band2/25:11.000dBi NB LTE Band4/66:8.000dBi NB LTE Band5:12.541 dBi NB LTE Band12:11.798dBi NB LTE Band13:12.214dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093 If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations. For this device, OEM integrators must be provided with labeling instructions of finished products. Please refer to KDB784748 D01 v07, section 8. Page 6/7 last two paragraphs:

A certified modular has the option to use a permanently affixed label, or an electronic label. For a permanently affixed label, the module must be labeled with an FCC ID - Section 2.926 (see 2.2 Certification (labeling requirements) above). The OEM manual must provide clear instructions explaining to the OEM the labeling requirements, options and OEM user manual instructions that are required (see next paragraph). For a host using a certified modular with a standard fixed label, if (1) the modules FCC ID is not visible when installed in the host, or (2) if the host is marketed so that end users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible;

then an additional permanent label referring to the enclosed module:Contains Transmitter Module FCC ID: XMR2023BG953AGL or Contains FCC ID: XMR2023BG953AGL must be used. The host OEM BG95xA-GL_Hardware_Design 104 / 102 LPWA Module Series user manual must also contain clear instructions on how end users can find and/or access the module and the FCC ID. The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The users manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. In cases where the manual is provided only in a form other than paper, such as on a computer disk or over the Internet, the information required by this section may be included in the manual in that alternative form, provided the user can reasonably be expected to have the capability to access information in that form. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the manufacturer could void the users authority to operate the equipment. IC Statement IRSS-GEN

"This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device." or "Le prsent appareil est conforme aux CNR dIndustrie Canada applicables aux appareils radio exempts de licence. Lexploitation est autorise aux deux conditions suivantes :

1) lappareil ne doit pas produire de brouillage; 2) lutilisateur de lappareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible den compromettre le fonctionnement."

BG95xA-GL_Hardware_Design 105 / 102 LPWA Module Series Dclaration sur l'exposition aux rayonnements RF The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the users body and must not transmit simultaneously with any other antenna or transmitter. L'autre utilis pour l'metteur doit tre install pour fournir une distance de sparation d'au moins 20 cm de toutes les personnes et ne doit pas tre colocalis ou fonctionner conjointement avec une autre antenne ou un autre metteur. To comply with IC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed:

Catm LTE Band2/25:11.000dBi Catm LTE Band4/66:8.000dBi Catm LTE Band5/26:12.541dBi Catm LTE Band12:11.798dBi Catm LTE Band13:12.214dBi Catm LTE Band85:11.798dBi NB LTE Band2/25:11.000dBi NB LTE Band4/66:8.000dBi NB LTE Band5:12.541 dBi NB LTE Band12:11.798dBi NB LTE Band13:12.214dBi The host product shall be properly labelled to identify the modules within the host product. The Innovation, Science and Economic Development Canada certification label of a module shall be clearly visible at all times when installed in the host product; otherwise, the host product must be BG95xA-GL_Hardware_Design 106 / 102 LPWA Module Series labeled to display the Innovation, Science and Economic Development Canada certification number for the module, preceded by the word Contains or similar wording expressing the same meaning, as follows:

Contains IC: 10224A-023BG953AGL or where: 10224A-023BG953AGL is the modules certification number. Le produit hte doit tre correctement tiquet pour identifier les modules dans le produit hte. L'tiquette de certification d'Innovation, Sciences et Dveloppement conomique Canada d'un module doit tre clairement visible en tout temps lorsqu'il est installdans le produit hte; sinon, le produit hte doit porter une tiquette indiquant le numro de certification d'Innovation, Sciences et Dveloppement conomique Canada pour le module, prcd du mot Contient ou d'un libell semblable exprimant la mme signification, comme suit:"Contient IC: 10224A-023BG953AGL " ou "o: 10224A-023BG953AGL est le numro de certification du module. BG95xA-GL_Hardware_Design 107 / 102 LPWA Module Series BG95xA-GL_Hardware_Design 108 / 102

RUECTEL BG953A-GL ai-anx AA BG953AGLAA-NO6-SGNSA SNEXXXXXXXXXXXXXXX IMEI:XXXXXXXXXXXXXXX FCC ID: XMR2023BG953AGL IC: 10224A-023BG953AGL C BR

} SN: Dt Q22aR1 -O000067 y IMEI: 866907060001 871 Engineering Sample soften py at

Quectel Wireless Solutions Co., Ltd February 20, 2023 Eurofins Electrical and Electronic Testing NA, Inc. 914 West Patapsco Avenue Baltimore, MD 21230 RE: Attestation Statements Part 2.911(d)(5)(i) request for FCC IDXMR2023BG953AGL

[Quectel Wireless Solutions Co., Ltd] (the applicant) certifies that the equipment for which authorization is sought is not covered equipment prohibited from receiving an equipment authorization pursuant to section 2.903 of the FCC rules. Sincerely, Applicant signature Applicant printed nameJean Hu Quectel Wireless Solutions Co., Ltd February 20, 2023 Eurofins Electrical and Electronic Testing NA, Inc. 914 West Patapsco Avenue Baltimore, MD 21230 RE: Attestation Statements Part 2.911(d)(5)(ii) request for FCC IDXMR2023BG953AGL

[Quectel Wireless Solutions Co., Ltd] (the applicant) certifies that, as of the date of the filing of the application, the applicant is not identified on the Covered List as an entity producing covered equipment. Sincerely, Applicant signature Applicant printed nameJean Hu

QIECCTEL Federal Communications Commission 7435 Oakland Mills Road Columbia MD 21046 Subject: Certification designating a U.S. agent for service of process pursuant to Part 2.911(d)(7) To whom it may concern, Quectel Wireless Solutions Company Limited, Grantee Code: XMR (the applicant) certifies that, as of the date of the filing of application, Ikotek USA, Inc., FRN: 0033350331 (the agent) is designated as the U.S. agent for the purpose of accepting service of process on behalf of the applicant. The physical U.S. address and email for the designated agent are:

Physical U.S. address: 9920 Pacific Heights Blvd., Ste. 150, #7025, San Diego, CA 92121 Email: compliance@ikotek.com The applicant accepts to maintain an agent for service of process in the United States for no less than one year after either the grantee has permanently terminated all marketing and importation of the applicable equipment within the U.S., or the conclusion of any Commission-related administrative or judicial proceeding involving the equipment, whichever is later. The agent accepts the designation by (the applicant) as the U.S. agent to accept service of process includes, but is not limited to, delivery of any correspondence, notices, orders, decisions, and requirements of administrative, legal, or judicial process related to Commission proceedings. Signed by the Applicant Signed by the Agent (if different from the Applicant) Name: Jean Hu C Name-dseph M. Peterson Title: Certification Manager Title: President and CEO Email: Jean.hu@quectel.com Email: joe.peterson@ikotek.com Date: 16 February 2023 Date: February 17%, 2023

Quectel Wireless Solutions Co., Ltd Office of Engineering Technology Federal Communications Commission 7435 Oakland Mills Road Columbia, MD21046 Subject; Request for Long Term Confidentiality FCC ID:XMR2023BG953AGL To Whom It May Concern, Pursuant to the provisions of the Commissions rules Title 47 Sections 0.457 and 0.459, we are requesting the Commission to withhold the following attachment(s) as confidential documents from public disclosure indefinitely. These documents contain detailed system and equipment descriptions and are considered as proprietary information in operation of the equipment. The public disclosure of these documents might be harmful to our company and would give competitors an unfair advantage in the market. Schematic Diagram Block Diagram Parts List Operational Description Tune up procedure It is our understanding that all measurement test reports, FCC ID label format and correspondence during the certification review process cannot be granted as confidential documents and this information will be available for public review once the grant of equipment authorization is issued. Signature :

Print name:

Jean Hu Company: Quectel Wireless Solutions Co., Ltd

Quectel Wireless Solutions Company Limited Declaration of the Modular Approval Applicant / Grantee FCC ID:

Model:

Quectel Wireless Solutions Co., Ltd. XMR2023BG953AGL BG953A-GL The single module transmitter has been evaluated then tested meeting the requirements under Part 15C Section 212 as below:

Modular approval requirement EUT Condition

(a) The radio elements of the modular transmitter must have their own shielding. The physical crystal and tuning capacitors may be located external to the shielded radio elements. The radio elements of the modular transmitter have their own shielding. Com ply YES

(b) The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with part 15 requirements under conditions of excessive data rates or over-modulation. The modular has buffered data inputs, it is integrated in chip. Please see schematic.pdf YES

(c)The modular transmitter must have its own powersupply regulation.

(d) The modular transmitter must comply with the antenna and transmission system requirements of Sections 15.203, 15.204(b) and 15.204(c). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of Section 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph (b) of this section.

(e)The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing for compliance with part 15 requirements. Unless the transmitter module will be battery powered, it must comply with the AC line conducted requirements found in Section 15.207. AC or DC power lines and data input/output lines connected to the module must not contain ferrites, unless they will be marketed with these the module (see Section 15.27(a)). The length of All power lines derived from the host device are regulated before energizing other circuits internal to the BG953A-GL. Please see schematic.pdf A permanently attached antenna or unique antenna connector is not a requirement for licensed modules. YES YES The BG953A-GL was tested in a stand alone configuration via a PCMCIA extender. Please see spurious setup YES Quectel Wireless Solutions Company Limited lines shall be the length typical of actual use or, if that length is unknown, at least 10 centimeters to insure that there is no coupling between the case of the module and supporting equipment. Any accessories, peripherals, or support equipment connected to the module during testing shall be unmodified and commercially available (see Section 15.31(i))mustnotbeinsideanotherdeviceduringtesting.

(f)The modular transmitter must be equipped with either a permanently affixed label or must be capable of electronically displaying its FCC identification number.

(g) The modular transmitter must comply with any specific rules or operating requirements that ordinarily apply to a complete transmitter and the manufacturer must provide adequate instructions along with the module to explain any suchrequirements. A copy of these instructions must be included in the application for equipmentauthorizationrequirements,whicharebasedonthei ntendeduse/configurations.

(h)The modular transmitter must comply with any applicable RF exposure requirements in its final configuration. The label position of BG953A-GL is clearly indicated. If the FCC ID of the module cannot be seen when it is installed, then the host label must include the text: Contains FCC ID:

XMR2023BG953AGL. Please see the label.pdf The BG953A-GL is compliant with all applicable FCC rules. Detail instructions are given in the User Manual. The BG953A-GL is approved to comply with the applicable RF exposure requirement, please see the MPE evaluation with 20cm as the distance restriction. YES YES YES Dated By:

2023/02/01 Jean Hu Signature Printed Title: Project Manager

Quectel Wireless Solutions Co., Ltd POWER OF ATTORNEY DATE:February 1, 2023 To:

Federal Communications Commission, Authorization & Evaluation Division, 7435 Oakland Mills Road, Columbia, MD 21046 We, the undersigned, hereby authorize TA Technology (Shanghai) Co., Ltd.

/Sun Yue on our behalf, to apply to FCC on our equipment for FCC ID:

XMR2023BG953AGL. Any and all acts carried out by TA Technology

(Shanghai) Co., Ltd. / Sun Yue on our behalf shall have the same effect as acts of our own. Sincerely, Signature:

Print name: Jean Hu Company: Quectel Wireless Solutions Co., Ltd

WARNING:pdfminer.pdfpage:The PDF <_io.BufferedReader name='/Volumes/Scratch/Incoming/eg-scratch/6373205.pdf'> contains a metadata field indicating that it should not allow text extraction. Ignoring this field and proceeding. Use the check_extractable if you want to raise an error in this case Product Change Description Report No.: R2211A1103 Product Change Description Statement We Quectel Wireless Solutions Co., Ltd declare the following models. Product Name: LTE Cat M & Cat NB Module Model Name: BG950A-GL, BG953A-GL BG950A-GL and BG953A-GL both use ALT1250 chip, share the same chipset baseline, the same hardware and software design, and also support the same frequency bands. The only differences are:

BG953A-GL supports iSIM while BG950A-GL do not support it. BG950A-GL and BG953A-GL share the same firmware baseline. BG953A-GL supports 3GPP Release 14 (Cat NB2 ) while BG950A-GL 3GPP Release 13(Cat NB1). Integrated SIM (iSIM) is a new SIM form-factor, integrated within ALT1250 and providing security and functionality equivalent to traditional SIM or eSIM. This feature is enabled by software configuration. 3GPP Release 14 upgrade from Release 13 is a software upgrade, there is no hardware change for it. The key information for two modules is as below:

Module BB Chip Category Frequency Bands BG950A-GL ALT1250 BG953A-GL ALT1250 Cat M1 /NB1/GNSS Cat M1 /NB2/GNSS Cat M LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B18/B19/B20/B25/B26

/B27/B28/B66 Cat NB LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B17/B18/B19/B20/B25

/B28/B66 Cat M LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B18/B19/B20/B25/B26

/B27/B28/B66 Cat NB LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B17/B18/B19/B20/B25

/B28/B66 GNSS iSIM GPS, GLONASS N/A GPS, GLONASS Supported Your assistance on this matter is highly appreciated. Sincerely, Name: Jean Hu Title: Certification Section Manager TA Technology (Shanghai) Co., Ltd. TA-MB-01-035E Page 1 of 1 This report shall not be reproduced except in full, without the written approval of TA Technology (Shanghai) Co., Ltd.

Quectel Wireless Solutions Co., Ltd Statement We Quectel Wireless Solutions Co., Ltd declare the following models. Product Name: LTE Cat M1/NB Module Model Name: BG950A-GL, BG953A-GL BG950A-GL and BG953A-GL both use ALT1250 chip, share the same chipset baseline, the same hardware and software design, and also support the same frequency bands. The only differences are:

BG953A-GL supports iSIM while BG950A-GL do not support it. BG953A-GL supports 3GPP Release 14 (Cat NB2) while BG950A-GL 3GPP Release 13(Cat NB1). Integrated SIM (iSIM) is a new SIM form-factor, integrated within ALT1250 and providing security and functionality equivalent to traditional SIM or eSIM. This feature is enabled by software configuration. 3GPP Release 14 upgrade from Release 13 is a software upgrade, there is no hardware change for it. The key information for two modules is as below:

Module BB Chip Category BG950A-GL ALT1250 Cat M1 /NB1/GNSS BG953A-GL ALT1250 Cat M1 /NB2/GNSS Frequency Bands Cat M LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B18/B19/B20/B25/B26

/B27/B28/B66 Cat NB LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B17/B18/B19/B20/B25

/B28/B66 Cat M LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B18/B19/B20/B25/B26

/B27/B28/B66 Cat NB LTE-HD-FDD: B1/B2/B3/B4/B5/B8

/B12/B13/B17/B18/B19/B20/B25

/B28/B66 GNSS iSIM GPS, GLONASS N/A GPS, GLONASS Supported Your assistance on this matter is highly appreciated. Sincerely, Name: Jean Hu Title: Certification Section Manager