SC650T Hardware Design Smart LTE Module Series Rev: SC650T_Hardware_Design_V1.1 Date: 2019-03-01 Status: Preliminary www.quectel.com Smart LTE Module Series SC650T Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters:
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SC650T_Hardware_Design 1 / 131 Smart LTE Module Series SC650T Hardware Design About the Document History Revision Date Author Description 1.0 2019-02-26 Arsene Initial SC650T_Hardware_Design 2 / 131 Smart LTE Module Series SC650T Hardware Design Contents About the Document ................................................................................................................................ 2 Contents .................................................................................................................................................... 3 Table Index ............................................................................................................................................... 6 Figure Index .............................................................................................................................................. 8 1 Introduction ..................................................................................................................................... 13 1.1. Safety Information .................................................................................................................. 14 2 Product Concept ............................................................................................................................. 15 2.1. General Description ................................................................................................................ 15 2.2. Key Features .......................................................................................................................... 16 2.3. Evaluation Board .................................................................................................................... 19 3.5.1. 3.5.2. 3 Application Interfaces ..................................................................................................................... 20 3.1. General Description ................................................................................................................ 20 3.2. Pin Assignment ....................................................................................................................... 21 3.3. Pin Description ....................................................................................................................... 22 3.4. Power Supply ......................................................................................................................... 39 3.4.1. Power Supply Pins ....................................................................................................... 39 3.4.2. Decrease Voltage Drop ................................................................................................ 39 3.4.3. Reference Design for Power Supply ............................................................................ 40 3.5. Turn on and off Scenarios ...................................................................................................... 41 Turn on Module Using the PWRKEY ........................................................................... 41 Turn off Module ............................................................................................................ 43 3.6. VRTC Interface ....................................................................................................................... 43 3.7. Power Output ......................................................................................................................... 44 3.8. Battery Charge and Management .......................................................................................... 45 3.9. USB Interface ......................................................................................................................... 47 3.10. UART Interfaces ..................................................................................................................... 49 3.11. (U)SIM Interfaces ................................................................................................................... 51 3.12. SD Card Interface ................................................................................................................... 53 3.13. GPIO Interfaces ...................................................................................................................... 55 3.14. I2C Interfaces ......................................................................................................................... 59 3.15. I2S Interface ........................................................................................................................... 59 3.16. SPI Interfaces ......................................................................................................................... 60 3.17. ADC Interfaces ....................................................................................................................... 61 3.18. Vibrator Drive Interface ........................................................................................................... 61 3.19. LCM Interfaces ....................................................................................................................... 62 3.20. Touch Panel Interfaces ........................................................................................................... 66 3.21. Camera Interfaces .................................................................................................................. 67 3.21.1. Design Considerations ................................................................................................. 71 SC650T_Hardware_Design 3 / 131 Smart LTE Module Series SC650T Hardware Design 3.21.2. Flashlight Interfaces ..................................................................................................... 73 3.22. Sensor Interfaces ................................................................................................................... 74 3.23. Audio Interfaces ..................................................................................................................... 74 3.23.1. Reference Circuit Design for Microphone Interfaces ................................................... 76 3.23.2. Reference Circuit Design for Earpiece Interface .......................................................... 77 3.23.3. Reference Circuit Design for Headphone Interface ..................................................... 78 3.23.4. Reference Circuit Design for Loudspeaker Interface ................................................... 78 3.23.5. Audio Interfaces Design Considerations ...................................................................... 78 3.24. Emergency Download Interface ............................................................................................. 79 3.25. LED Driver Interfaces ............................................................................................................. 79 4 Wi-Fi and BT .................................................................................................................................... 81 4.1. Wi-Fi Overview ....................................................................................................................... 81 4.1.1. Wi-Fi Performance ....................................................................................................... 81 4.2. BT Overview ........................................................................................................................... 83 4.2.1. BT Performance ........................................................................................................... 84 5 GNSS ................................................................................................................................................ 85 5.1. GNSS Performance ................................................................................................................ 85 5.2. GNSS RF Design Guidelines ................................................................................................. 86 6 Antenna Interfaces .......................................................................................................................... 87 6.1. Main/Rx-diversity Antenna Interfaces ..................................................................................... 87 6.1.1. Main and Rx-diversity Antenna Interfaces Reference Design ...................................... 88 6.1.2. Reference Design of RF Layout ................................................................................... 89 6.2. Wi-Fi/BT Antenna Interface .................................................................................................... 91 6.3. GNSS Antenna Interface ........................................................................................................ 91 6.3.1. Recommended Circuit for Passive Antenna ................................................................ 92 6.3.2. Recommended Circuit for Active Antenna ................................................................... 92 6.4. Antenna Installation ................................................................................................................ 93 6.4.1. Antenna Requirements ................................................................................................ 93 6.4.2. Recommended RF Connector for Antenna Installation ................................................ 94 7 Electrical, Reliability and Radio Characteristics .......................................................................... 96 7.1. Absolute Maximum Ratings .................................................................................................... 96 7.2. Power Supply Ratings ............................................................................................................ 96 7.3. Operation and Storage Temperatures ..................................................................................... 97 7.4. Current Consumption ............................................................................................................. 97 7.5. RF Output Power .................................................................................................................... 99 7.6. RF Receiving Sensitivity ....................................................................................................... 100 7.7. Electrostatic Discharge ......................................................................................................... 101 8 Mechanical Dimensions................................................................................................................ 102 8.1. Mechanical Dimensions of the Module ................................................................................. 102 8.2. Recommended Footprint ...................................................................................................... 104 8.3. Top and Bottom View of the Module ..................................................................................... 105 SC650T_Hardware_Design 4 / 131 Smart LTE Module Series SC650T Hardware Design 9 Storage, Manufacturing and Packaging ...................................................................................... 106 9.1. Storage ................................................................................................................................. 106 9.2. Manufacturing and Soldering ................................................................................................ 107 9.3. Packaging ............................................................................................................................. 108 10 Appendix A References ................................................................................................................ 110 SC650T_Hardware_Design 5 / 131 Smart LTE Module Series SC650T Hardware Design Table Index TABLE 1: SC650T-NA FREQUENCY BANDS .................................................................................................. 15 TABLE 2: SC650T-EM FREQUENCY BANDS .................................................................................................. 15 TABLE 3: SC650T KEY FEATURES ................................................................................................................. 16 TABLE 4: I/O PARAMETERS DEFINITION ....................................................................................................... 22 TABLE 5: PIN DESCRIPTION ........................................................................................................................... 22 TABLE 6: POWER DESCRIPTION ................................................................................................................... 44 TABLE 7: PIN DEFINITION OF CHARGING INTERFACE ............................................................................... 45 TABLE 8: PIN DEFINITION OF USB INTERFACE ........................................................................................... 47 TABLE 9: USB TRACE LENGTH INSIDE THE MODULE ................................................................................. 49 TABLE 10: PIN DEFINITION OF UART INTERFACES ..................................................................................... 49 TABLE 11: PIN DEFINITION OF (U)SIM INTERFACES ................................................................................... 51 TABLE 12: PIN DEFINITION OF SD CARD INTERFACE ................................................................................ 54 TABLE 13: SD CARD SIGNAL TRACE LENGTH INSIDE THE MODULE ........................................................ 55 TABLE 14: PIN DEFINITION OF GPIO INTERFACES ..................................................................................... 55 TABLE 15: PIN DEFINITION OF I2C INTERFACES ......................................................................................... 59 TABLE 16: PIN DEFINITION OF I2S INTERFACE ........................................................................................... 60 TABLE 17: PIN DEFINITION OF SPI INTERFACES ........................................................................................ 60 TABLE 18: PIN DEFINITION OF ADC INTERFACES ....................................................................................... 61 TABLE 19: PIN DEFINITION OF VIBRATOR DRIVE INTERFACE .................................................................. 61 TABLE 20: PIN DEFINITION OF LCM INTERFACES ....................................................................................... 62 TABLE 21: PIN DEFINITION OF TOUCH PANEL INTERFACES ..................................................................... 66 TABLE 22: PIN DEFINITION OF CAMERA INTERFACES ............................................................................... 67 TABLE 23: MIPI TRACE LENGTH INSIDE THE MODULE............................................................................... 71 TABLE 24: PIN DEFINITION OF FLASHLIGHT INTERFACES ........................................................................ 73 TABLE 25: PIN DEFINITION OF SENSOR INTERFACES ............................................................................... 74 TABLE 26: PIN DEFINITION OF AUDIO INTERFACES ................................................................................... 74 TABLE 27: PIN DEFINITION OF LED DRIVER INTERFACES ......................................................................... 80 TABLE 28: WI-FI TRANSMITTING PERFORMANCE ....................................................................................... 81 TABLE 29: WI-FI RECEIVING PERFORMANCE .............................................................................................. 82 TABLE 30: BT DATA RATE AND VERSIONS .................................................................................................... 84 TABLE 31: BT TRANSMITTING AND RECEIVING PERFORMANCE ............................................................. 84 TABLE 32: GNSS PERFORMANCE ................................................................................................................. 85 TABLE 33: PIN DEFINITION OF MAIN/RX-DIVERSITY ANTENNA INTERFACES ......................................... 87 TABLE 34: SC650T-NA MODULE OPERATING FREQUENCIES .................................................................... 87 TABLE 35: SC650T-EM MODULE OPERATING FREQUENCIES ................................................................... 88 TABLE 36: PIN DEFINITION OF WI-FI/BT ANTENNA INTERFACE ................................................................ 91 TABLE 37: WI-FI/BT FREQUENCY ................................................................................................................... 91 TABLE 38: PIN DEFINITION OF GNSS ANTENNA .......................................................................................... 92 TABLE 39: GNSS FREQUENCY ....................................................................................................................... 92 TABLE 40: ANTENNA REQUIREMENTS .......................................................................................................... 93 TABLE 41: ABSOLUTE MAXIMUM RATINGS .................................................................................................. 96 SC650T_Hardware_Design 6 / 131 Smart LTE Module Series SC650T Hardware Design TABLE 42: SC650T MODULE POWER SUPPLY RATINGS ............................................................................ 96 TABLE 43: OPERATION AND STORAGE TEMPERATURES .......................................................................... 97 TABLE 44: SC650T-NA CURRENT CONSUMPTION ....................................................................................... 98 TABLE 45: SC650T-EM CURRENT CONSUMPTION ...................................................................................... 98 TABLE 46: SC650T-NA RF OUTPUT POWER ................................................................................................. 99 TABLE 47: SC650T-EM RF OUTPUT POWER ................................................................................................. 99 TABLE 48: SC650T-NA RF RECEIVING SENSITIVITY X` ............................................................................. 100 TABLE 49: SC650T-EM RF RECEIVING SENSITIVITY ................................................................................. 100 TABLE 50: ESD CHARACTERISTICS (TEMPERATURE: 25C, HUMIDITY: 45%) ....................................... 101 TABLE 51: RECOMMENDED THERMAL PROFILE PARAMETERS ............................................................. 107 TABLE 52: REEL PACKAGING ....................................................................................................................... 109 TABLE 53: RELATED DOCUMENTS ............................................................................................................... 110 TABLE 54: TERMS AND ABBREVIATIONS ..................................................................................................... 110 SC650T_Hardware_Design 7 / 131 Smart LTE Module Series SC650T Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 18 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 21 FIGURE 3: VOLTAGE DROP SAMPLE ............................................................................................................. 39 FIGURE 4: STAR STRUCTURE OF POWER SUPPLY .................................................................................... 40 FIGURE 5: REFERENCE CIRCUIT OF POWER SUPPLY .............................................................................. 40 FIGURE 6: TURN ON THE MODULE USING DRIVING CIRCUIT ................................................................... 41 FIGURE 7: TURN ON THE MODULE USING KEYSTROKE ........................................................................... 42 FIGURE 8: TIMING OF TURNING ON MODULE ............................................................................................. 42 FIGURE 9: TIMING OF TURNING OFF MODULE ........................................................................................... 43 FIGURE 10: RTC POWERED BY COIN CELL ................................................................................................. 43 FIGURE 11: REFERENCE DESIGN FOR BATTERY CHARGING CIRCUIT ................................................... 46 FIGURE 12: USB 2.0 INTERFACE REFERENCE DESIGN ............................................................................. 48 FIGURE 13: USB TYPE-C INTERFACE REFERENCE DESIGN ..................................................................... 48 FIGURE 14: REFERENCE CIRCUIT WITH LEVEL TRANSLATOR CHIP (FOR UART5) ............................... 50 FIGURE 15: RS232 LEVEL MATCH CIRCUIT (FOR UART5) .......................................................................... 51 FIGURE 16: REFERENCE CIRCUIT FOR (U)SIM INTERFACE WITH AN 8-PIN (U)SIM CARD CONNECTOR
................................................................................................................................................................... 52 FIGURE 17: REFERENCE CIRCUIT FOR (U)SIM INTERFACE WITH A 6-PIN (U)SIM CARD CONNECTOR
................................................................................................................................................................... 53 FIGURE 18: REFERENCE CIRCUIT FOR SD CARD INTERFACE ................................................................. 54 FIGURE 19: REFERENCE CIRCUIT FOR VIBRATOR CONNECTION ........................................................... 62 FIGURE 20: REFERENCE CIRCUIT DESIGN FOR LCM0 INTERFACE ......................................................... 64 FIGURE 21: REFERENCE CIRCUIT DESIGN FOR LCM1 INTERFACE ......................................................... 65 FIGURE 22: REFERENCE DESIGN OF LCM EXTERNAL BACKLIGHT DRIVING CIRCUIT ......................... 65 FIGURE 23: REFERENCE CIRCUIT DESIGN FOR TOUCH PANEL INTERFACES ....................................... 67 FIGURE 24: REFERENCE CIRCUIT DESIGN FOR TWO-CAMERA APPLICATIONS .................................... 70 FIGURE 25: REFERENCE CIRCUIT DESIGN FOR FLASHLIGHT INTERFACES .......................................... 73 FIGURE 26: REFERENCE CIRCUIT DESIGN FOR ANALOG ECM-TYPE MICROPHONE ........................... 76 FIGURE 27: REFERENCE CIRCUIT DESIGN FOR MEMS-TYPE MICROPHONE ........................................ 76 FIGURE 28:REFERENCE CIRCUIT DESIGN FOR DIGITAL MICROPHONE ................................................. 77 FIGURE 29: REFERENCE CIRCUIT DESIGN FOR EARPIECE INTERFACE ................................................ 77 FIGURE 30: REFERENCE CIRCUIT DESIGN FOR HEADPHONE INTERFACE ........................................... 78 FIGURE 31: REFERENCE CIRCUIT DESIGN FOR LOUDSPEAKER INTERFACE ....................................... 78 FIGURE 32: REFERENCE CIRCUIT DESIGN FOR EMERGENCY DOWNLOAD INTERFACE ..................... 79 FIGURE 33: REFERENCE CIRCUIT DESIGN FOR LED INTERFACES ......................................................... 80 FIGURE 34: REFERENCE CIRCUIT DESIGN FOR MAIN AND RX-DIVERSITY ANTENNA INTERFACES .. 89 FIGURE 35: MICROSTRIP LINE DESIGN ON A 2-LAYER PCB ...................................................................... 89 FIGURE 36: COPLANAR WAVEGUIDE LINE DESIGN ON A 2-LAYER PCB .................................................. 89 FIGURE 37: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE GROUND) .................................................................................................................................................. 90 FIGURE 38: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE SC650T_Hardware_Design 8 / 131 Smart LTE Module Series SC650T Hardware Design GROUND) .................................................................................................................................................. 90 FIGURE 39: REFERENCE CIRCUIT DESIGN FOR WI-FI/BT ANTENNA INTERFACE .................................. 91 FIGURE 40: REFERENCE CIRCUIT DESIGN FOR GNSS PASSIVE ANTENNA ........................................... 92 FIGURE 41: REFERENCE CIRCUIT DESIGN FOR GNSS ACTIVE ANTENNA ............................................. 93 FIGURE 42: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) ................................................ 94 FIGURE 43: MECHANICALS OF U.FL-LP CONNECTORS ............................................................................. 95 FIGURE 44: SPACE FACTOR OF MATED CONNECTOR (UNIT: MM) ........................................................... 95 FIGURE 45: MODULE TOP AND SIDE DIMENSIONS ................................................................................... 102 FIGURE 46: MODULE BOTTOM DIMENSIONS (TOP VIEW) ....................................................................... 103 FIGURE 47: RECOMMENDED FOOTPRINT (TOP VIEW) ............................................................................ 104 FIGURE 48: TOP VIEW OF THE MODULE .................................................................................................... 105 FIGURE 49: BOTTOM VIEW OF THE MODULE ............................................................................................ 105 FIGURE 50: RECOMMENDED REFLOW SOLDERING THERMAL PROFILE .............................................. 107 FIGURE 51: TAPE DIMENSIONS ................................................................................................................... 108 FIGURE 52: REEL DIMENSIONS ................................................................................................................... 109 SC650T_Hardware_Design 9 / 131 Smart LTE Module Series SC650T Hardware Design OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.31 (h) and (k): The host manufacturer is responsible for additional testing to verify compliance as a composite system. When testing the host device for compliance with Part 15 Subpart B, the host manufacturer is required to show compliance with Part 15 Subpart B while the transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation should confirm that the module's intentional emissions are compliant (i.e. fundamental and out of band emissions). The host manufacturer must verify that there are no additional unintentional emissions other than what is permitted in Part 15 Subpart B or emissions are complaint with the transmitter(s) rule(s). The Grantee will provide guidance to the host manufacturer for Part 15 B requirements if needed. End Product Labeling When the module is installed in the host device, the FCC/IC ID label must be visible through a window on the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a second label must be placed on the outside of the final device that contains the following text:
Contains FCC ID: XMR2019SC650TNA Contains IC: 10224A-19SC650TNA The FCC ID/IC ID can be used only when all FCC/IC compliance requirements are met. In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC/IC authorization. Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can SC650T_Hardware_Design 10 / 131 Smart LTE Module Series SC650T Hardware Design be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:
- Reorient or relocate the receiving antenna.
- Increase the separation between the equipment and receiver.
- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
- Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. Industry Canada Statement This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions:
(1) This device may not cause interference; and
(2) This device must accept any interference, including interference that may cause undesired operation of the device. Le prsent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorise aux deux conditions suivantes:
(1) l'appareil ne doit pas produire de brouillage, et
(2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement."
The device could automatically discontinue transmission in case of absence of information to transmit, or operational failure. Note that this is not intended to prohibit transmission of control or signaling information or the use of repetitive codes where required by the technology. The device for operation in the band 51505250 MHz is only for indoor use to reduce the potential for harmful interference to co-channel mobile satellite systems; The maximum antenna gain permitted for devices in the bands 52505350 MHz and 54705725 MHz shall comply with the e.i.r.p. limit; and The maximum antenna gain permitted for devices in the band 57255825 MHz shall comply with the e.i.r.p. limits specified for point-to-point and non point-to-point operation as appropriate. L'appareil peut interrompre automatiquement la transmission en cas d'absence d'informations transmettre ou de panne oprationnelle. Notez que ceci n'est pas destin interdire la transmission d'informations de contrle ou de signalisation ou l'utilisation de codes rptitifs lorsque cela est requis par la technologie. Le dispositif utilis dans la bande 5150-5250 MHz est rserv une utilisation en intrieur afin de rduire le risque de brouillage prjudiciable aux systmes mobiles par satellite dans le mme canal; Le gain d'antenne maximal autoris pour les dispositifs dans les bandes 5250-5350 MHz et 5470-5725 MHz doit tre conforme la norme e.r.p. limite; et Le gain d'antenne maximal autoris pour les appareils de la bande 5725-5825 MHz doit tre conforme la norme e.i.r.p. les limites spcifies pour un fonctionnement SC650T_Hardware_Design 11 / 131 Smart LTE Module Series SC650T Hardware Design point point et non point point, selon le cas CAN ICES-3(B)/ NMB-3(B) Radiation Exposure Statement This equipment complies with FCC/IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator &
your body. This radio transmitter [10224A-19SC650TNA] has been approved by Innovation, Science and Economic Development Canada to operate with the antenna types listed below, with the maximum permissible gain indicated. Antenna types not included in this list that have a gain greater than the maximum gain indicated for any type listed are strictly prohibited for use with this device. Frequency Bands Antenna type Maximun GaindBi 2.4G WIFI/BT 5G WIFI LTE B5 LTE B26 LTE B2/25 LTE B14 LTE B4/66 LTE B7 LTE B12 LTE B13 Dipole Dipole Dipole Dipole Dipole Dipole Dipole Dipole Dipole Dipole 5.38 5.05 2.53 3.19 1.59 4.45 2 3 3.95 4.45 SC650T_Hardware_Design 12 / 131 Smart LTE Module Series SC650T Hardware Design 1 Introduction This document defines the SC650T module and describes its air interface and hardware interface which are connected with customers applications. This document can help customers quickly understand module interface specifications, electrical and mechanical details as well as other related information of SC650T module. Associated with application note and user guide, customers can use SC650T module to design and set up mobile applications easily. SC650T_Hardware_Design 13 / 131 Smart LTE Module Series SC650T Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating SC650T module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product. If not so, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be given to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If the device offers an Airplane Mode, then it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on boarding the aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signals and cellular network cannot be guaranteed to connect in all possible conditions (for example, with unpaid bills or with an invalid (U)SIM card). When emergent help is needed in such conditions, please remember using emergency call. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV set, radio, computer or other electric equipment. In locations with potentially explosive atmospheres, obey all posted signs to turn off wireless devices such as your phone or other cellular terminals. Areas with potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, areas where the air contains chemicals or particles such as grain, dust or metal powders, etc. SC650T_Hardware_Design 14 / 131 Smart LTE Module Series SC650T Hardware Design 2 Product Concept 2.1. General Description Integrate GPS/GLONASS/BeiDou satellite positioning systems SC650T is a series of Smart LTE module based on Qualcomm platform and Android operating system, and provides industrial grade performance. Its general features are listed below:
Support worldwide LTE-FDD Support short-range wireless communication via Wi-Fi 802.11a/b/g/n/ac and BT4.2 LE standards Support multiple audio and video codecs Built-in high performance AdrenoTM 506 graphics processing unit Provide multiple audio and video input/output interfaces as well as abundant GPIO interfaces SC650T includes models such as SC650T-NA and SC650T-EM. The following table shows the supported frequency bands of SC650T. Table 1: SC650T-NA Frequency Bands Wi-Fi 802.11a/b/g/n/ac 2402MHz~2482MHz; 5180MHz~5825MHz Frequency Bands B2/B4/B5/B7/B12/B13/B14/B25/B26/B66 2402MHz~2480MHz GPS: 1575.42MHz1.023MHz GLONASS: 1597.5MHz~1605.8MHz BeiDou: 1561.098MHz2.046MHz Type LTE-FDD BT4.2 LE GNSS Table 2: SC650T-EM Frequency Bands Type Frequency Bands SC650T_Hardware_Design 15 / 131 Smart LTE Module Series SC650T Hardware Design LTE-FDD B1/B3/B7/B20/B28 Wi-Fi 802.11a/b/g/n/ac 2402MHz~2482MHz; 5180MHz~5825MHz BT4.2 LE GNSS 2402MHz~2480MHz GPS: 1575.42MHz1.023MHz GLONASS: 1597.5MHz~1605.8MHz BeiDou: 1561.098MHz2.046MHz SC650T is an SMD type module which can be embedded into applications through its 323 pins (including 152 LCC pads and 171 LGA pads). With a compact profile of 43.0mm 44.0mm 2.85mm, SC650T can meet almost all requirements for M2M applications such as smart metering, smart home, security, routers, wireless POS, mobile computing devices, PDA phone, tablet PC, etc. 2.2. Key Features The following table describes the detailed features of SC650T module. Table 3: SC650T Key Features Features Details Application Processor SC650T Octa-core ARM Cortex-A53 64-bit CPU @2.0GHz (high performance) One quad-core with 1MB L2 cache One quad-core with 512KB L2 cache Modem system Hexagon DSP v56 core up to 850MHz 768KB L2 cache GPU Memory SC650T AdrenoTM 506 with 64-bit addressing, designed for 650MHz 16GB eMMC + 2GB LPDDR3 (default) 32GB eMMC + 4GB LPDDR3 (optional) Operating System Android OS 9.0 Power Supply VBAT Supply Voltage: 3.55V~4.4V Typical 3.8V Transmitting Power Class 3 (23dBm2dB) for LTE-FDD bands LTE Features Support 3GPP R8 Cat 4 Support 1.4 to 20MHz RF bandwidth Support Multiuser MIMO in DL direction SC650T_Hardware_Design 16 / 131 Smart LTE Module Series SC650T Hardware Design Cat 4 FDD: Max 150Mbps (DL)/Max 50Mbps (UL) WLAN Features 2.4GHz/5GHz, support 802.11a/b/g/n/ac, maximally up to 433Mbps Support AP and STA mode Bluetooth Features BT4.2 LE GNSS Features GPS/GLONASS/BeiDou SMS LCM Interfaces Camera Interfaces Video Codec Audio Interfaces Audio Codec USB Interface Text and PDU mode Point-to-point MO and MT SMS cell broadcast Support two groups of 4-lane MIPI_DSI Support dual LCDs Support WUXGA up to (19201200) at 60fps Support two groups of 4-lane MIPI_CSI, up to 2.1Gbps per lane Support 2 cameras (4-lane + 4-lane) or 3 cameras (4-lane + 4-lane + 2-lane ) up to 24MP with dual ISP SC650T Video encoding and decoding: up to 4K @30fps, up to 1080P @60fps Wi-Fi Video: encoding up to 1080P @30fps; decoding up to 1080P @60fps Audio Input:
Two analog microphone inputs, two digital microphone inputs, integrating internal bias voltage Audio Output:
Class AB stereo headphone output Class AB earpiece differential output G711, QCELP, EVRC, EVRC-B, EVRC-WB, AMR-NB, AMR-WB, GSM-EFR, GSM-FR, GSM-HR Compliant with USB 3.0 and 2.0 specifications, with transmission rates up to 5Gbps on USB 3.0 and 480Mbps on USB 2.0. Support USB OTG Used for AT command communication, data transmission, software debugging and firmware upgrade 4 UART Interfaces: UART5, UART6, UART4 and UART2 UART5 & UART6: 4-wire UART interface with RTS/CTS hardware flow UART Interfaces control, baud rate up to 4Mbps UART4: 2-wire UART interface UART2: 2-wire UART interface used for debugging Vibrator drive interface Drive ERM vibrator SD Card Interface
(U)SIM Interfaces Support SD 3.0 Support SD card hot-plug 2 (U)SIM interfaces Support USIM/SIM card: 1.8V/2.95V SC650T_Hardware_Design 17 / 131 Smart LTE Module Series SC650T Hardware Design Support Dual SIM Dual Standby (supported by default) I2C Interfaces Five I2C interfaces, used for peripherals such as TP, camera, sensor, etc. I2S Interface Support for I2S peripherals Flashlight Interface 2 high current Flash and torch LED driver 1A for Flash mode and 300mA for torch mode by default 1.5A for Flash mode and 300mA for torch mode maximally ADC Interfaces SPI Interfaces 2 general purpose ADC interfaces Support up to 15-bit sampling accuracy 2 SPI interfaces, only support master mode One SPI interface used for peripheral device Charging Interface Used for battery voltage detection, fuel gauge, battery temperature detection One SPI interface used for sensor application, such as fingerprint sensors Real Time Clock Supported Antenna Interfaces Main antenna, Rx-diversity antenna, GNSS antenna and Wi-Fi/BT antenna interfaces Physical Characteristics Temperature Range Size: (43.00.15)mm (44.00.15)mm (2.850.2)mm Package: LCC + LGA Weight: approx. 13.0g Operating temperature range: -35C ~ +65C 1) Extended temperature range: -40C ~ +75C 2) Storage temperature range: -40C ~ +90C Firmware Upgrade Over USB interface RoHS All hardware components are fully compliant with EU RoHS directive 1. 1) Within operation temperature range, the module is 3GPP compliant. 2. 2) Within extended temperature range, the module remains the ability to establish and maintain a voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances. When the temperature returns to the normal operating temperature levels, the module will meet 3GPP specifications again. NOTES SC650T_Hardware_Design 18 / 131 Smart LTE Module Series SC650T Hardware Design 2.3. Evaluation Board In order to help customers develop applications with SC650T conveniently, Quectel supplies the evaluation board, USB to RS232 converter cable, USB Type-C data cable, power adapter, earphone, antenna and other peripherals to control or test the module. For more details, please refer to document
[1]. SC650T_Hardware_Design 19 / 131 Smart LTE Module Series SC650T Hardware Design 3 Application Interfaces 3.1. General Description SC650T is equipped with 323-pin 1.0mm pitch SMT pads that can be embedded into cellular application platform. The following chapters provide the detailed description of pins/interfaces listed below. Power supply VRTC interface Charging interface USB interface UART interfaces
(U)SIM interfaces SD card interface GPIO interfaces I2C interfaces I2S interfaces SPI interfaces ADC interfaces Vibrator drive interface LCM interfaces TP (touch panel) interfaces Camera interfaces Flashlight interfaces Sensor interfaces Audio interfaces Emergency download interface LED sink driver interfaces SC650T_Hardware_Design 20 / 131 Smart LTE Module Series SC650T Hardware Design 3.2. Pin Assignment The following figure shows the pin assignment of SC650T module. Figure 1: Pin Assignment (Top View) SC650T_Hardware_Design 21 / 131 Smart LTE Module Series SC650T Hardware Design 3.3. Pin Description Table 4: I/O Parameters Definition Type IO DI DO PI PO AI AO OD Description Bidirectional Digital input Digital output Power input Power output Analog input Analog output Open drain The following tables show the SC650Ts pin definition and electrical characteristics. Table 5: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment VBAT 363738 PI/PO Power supply for the battery. Vmax=4.4V Vmin=3.55V Vnorm=3.8V It must be able to provide sufficient current up to 3.0A. It is suggested to use a TVS to increase voltage surge withstand capability. VDD_RF 12 PO Connect to external bypass capacitors to eliminate voltage fluctuation of RF part. Vmax=4.4V Vmin=3.55V Vnorm=3.8V Do not load externally. VPH_PWR 220,221 PO Power supply for the Vmax=4.4V Peripheral power SC650T_Hardware_Design 22 / 131 Smart LTE Module Series SC650T Hardware Design VRTC 16 PI/PO module. Vmin=3.55V Vnorm=3.8V interface Power supply for internal RTC circuit VOmax=3.2V VI=2.0V~3.25V LDO5_1P8 9 PO 1.8V output power supply Vnorm=1.8V IOmax=20mA LDO10_2P8 11 PO 2.8V output power supply Vnorm=2.8V IOmax=150mA LDO6_1P8 10 PO 1.8V output power supply Vnorm=1.8V IOmax=300mA LDO17_2P85 12 PO 2.85V output power supply Vnorm=2.85V IOmax=300mA LDO13_3P07 5 157 PO 13.125V output power supply Vnorm=3.125V IOmax=150mA LDO23_1P2 15 PO 1.2V output power supply Vnorm=1.2V IOmax=600mA Power supply for external GPIOs pull up circuits and level shift circuit. Power supply for VDD of sensors and TPs. Add a 1.0uF~4.7uF bypass capacitor if used. If unused, keep this pin open. Power supply for I/O VDD of cameras, LCDs and sensors. Add a 1.0uF~2.2uF bypass capacitor if used. If unused, keep this pin open. Power supply for cameras and LCDs. Add a 1.0uF~4.7uF bypass capacitor if used. If unused, keep this pin open. Power supply for USB Add a 1.0uF~4.7uF bypass capacitor if used. If unused, keep this pin open. Power supply for DVDD of front cameras. Add a 1.0uF~2.2uF bypass capacitor if SC650T_Hardware_Design 23 / 131 Smart LTE Module Series SC650T Hardware Design used. If unused, keep this pin open. Power supply for DVDD of rear cameras. Add a 1.0uF~2.2uF bypass capacitor if used. If unused, keep this pin open. Power supply for AVDD of cameras. Add a 1.0uF~4.7uF bypass capacitor if used. If unused, keep this pin open. LDO2_1P1 13 PO 1.1V output power supply Vnorm=1.1V IOmax=1200mA LDO22_2P8 14 PO 2.8V output power supply Vnorm=2.8V IOmax=150mA 3,4,18,20,3 1,34,35,40, 43,47,56,6 2,87,98,10 1,112,125, 128,130,13 3,135,148, 150,159,16 0,163,170, 173,176,18 2,193,195, 219,243,25 7--323 GND Ground Audio Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment DMIC1_DATA 45 DMIC1_CLK 46 DI DO DMIC2_DATA 168 DI DMIC2_CLK 169 DO Digital microphone1 data Digital microphone1 clock Digital microphone2 data Digital microphone2 clock SC650T_Hardware_Design 24 / 131 Smart LTE Module Series SC650T Hardware Design MIC_BIAS1 44 MIC_BIAS2 233 MIC_BIAS3 167 AO AO AO Microphone bias voltage Microphone bias voltage Microphone bias voltage VO=1.6V~2.85V VO=1.6V~2.85V VO=1.6V~2.85V Dias voltage for DMIC1 Dias voltage for AMIC2 Dias voltage for DMIC2 LINE_OUT_3 228 AO Audio output LINE_OUT_R EF 227 AI Audio output reference ground LINE_OUT_4 226 AO Audio output Analog microphone positive input for channel 1 Analog microphone negative input for channel 1 Analog microphone positive input for headset Analog microphone negative input for headset Earpiece positive output Earpiece positive output External audio power amplifier clock interface External audio power amplifier data interface External audio power amplifier enable signal Headphone right channel output Headphone reference ground Headphone left channel output AMIC1_P 218 AI AMIC1_M 217 AI AMIC2_P 216 AI AMIC2_M 215 AI EAR_P EAR_N 53 52 AO AO PDM_CLK 55 AO PDM_DATA 54 AO WSA_EN 230 DO HPH_R 51 HPH_REF 50 HPH_L 49 AO AI AO SC650T_Hardware_Design 25 / 131 Smart LTE Module Series SC650T Hardware Design HS_DET 48 AI Pulled up internally. Headset insertion detection USB Interface Pin Name Pin No. I/O Description DC Characteristics Comment USB_VBUS 4142 PI/PO USB_DM USB_DP USB_SS_RX _P USB_SS_RX _M USB_SS_TX_ P USB_SS_TX_ M 33 32 171 172 174 175 IO IO AI AI AO AO USBC_CC2 223 AI/AO USBC_CC1 224 AI/AO CC_OUT 225 AO
(U)SIM Interface Charging power input. Power supply output for OTG device. USB/charger insertion detection. USB 2.0 differential data bus (minus) USB 2.0 differential data bus (plus) USB 3.0 differential receive (plus) USB 3.0 differential receive (minus) USB 3.0 differential transmit (plus) USB 3.0 differential transmit (minus) USB Type-C control configuration channel 2 USB Type-C control configuration channel 1 USB Type-C switch control Vmax=10V Vmin=4V Vnorm=5.0V USB 2.0 standard compliant 90 differential impedance. USB 3.0 standard compliant 90 differential impedance. 90 differential impedance. Pin Name Pin No. I/O Description DC Characteristics Comment USIM1_DET 145 DI
(U)SIM1 card hot-plug detection VILmax=0.63V VIHmin=1.17V Active Low. Require external pull-up to 1.8V. If unused, keep this pin open. Disabled by default, and can be enabled SC650T_Hardware_Design 26 / 131 Smart LTE Module Series SC650T Hardware Design through software configuration. USIM1_RST 144 DO USIM1_CLK 143 DO
(U)SIM1 card reset signal
(U)SIM1 card clock signal USIM1_DATA 142 IO
(U)SIM1 card data signal USIM1_VDD 141 PO
(U)SIM1 card power supply VOLmax=0.4V VOHmin=
0.8 USIM1_VDD VOLmax=0.4V VOHmin=
0.8 USIM1_VDD VILmax=
0.2 USIM1_VDD VIHmin=
0.7 USIM1_VDD VOLmax=0.4V VOHmin=
0.8 USIM1_VDD 1.8V (U)SIM Vmax=1.85V Vmin=1.75V 2.95V (U)SIM Vmax=3.1V Vmin=2.8V USIM2_DET 256 DI
(U)SIM2 card detection VILmax=0.63V VIHmin=1.17V USIM2_RST 207 DO USIM2_CLK 208 DO
(U)SIM2 card reset signal
(U)SIM2 card clock signal USIM2_DATA 209 IO
(U)SIM2 card data signal VOLmax=0.4V VOHmin=
0.8 USIM2_VDD VOLmax=0.4V VOHmin=
0.8 USIM2_VDD VILmax=
0.2 USIM2_VDD VIHmin=
0.7 USIM2_VDD VOLmax=0.4V VOHmin=
Either 1.8V or 2.95V
(U)SIM card is supported. Active Low. Need external pull-up to 1.8V. If unused, keep this pin open. Disabled by default, and can be enabled through software configuration. SC650T_Hardware_Design 27 / 131 0.8 USIM2_VDD 1.8V (U)SIM Vmax=1.85V Vmin=1.75V 2.95V (U)SIM Vmax=3.1V Vmin=2.8V VOLmax=0.45V VOHmin=1.35V VILmax=0.63V VIHmin=1.17V VOLmax=0.45V VOHmin=1.35V VILmax=0.63V VIHmin=1.17V VILmax=0.63V VIHmin=1.17V VOLmax=0.45V VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V VILmax=0.63V VIHmin=1.17V VILmax=0.63V VIHmin=1.17V VOLmax=0.45V VOHmin=1.35V Smart LTE Module Series SC650T Hardware Design USIM2_VDD 210 PO
(U)SIM2 card power supply Either 1.8V or 2.95V
(U)SIM card is supported. UART Interface Pin Name Pin No. I/O Description DC Characteristics Comment UART2_TXD 5 DO UART2_RXD 6 DI UART4_TXD 7 DO UART5_TXD 199 UART5_RTS 245 UART5_CTS 246 UART2 transmit data. Debug port by default. UART2 receive data. Debug port by default. UART4 transmit data UART5 transmit data UART5 request to send UART5 clear to send DI DI DO DO DI DI UART4_RXD 8 UART4 receive data UART5_RXD 198 UART5 receive data 1.8V power domain. If unused, keep these pins open. UART6_RXD 61 UART6 receive data UART6_TXD 60 DO UART6 transmit data SD Card Interface Pin Name Pin No. I/O Description Comment SD_CLK 70 DO High speed digital clock signal of SD card DC Characteristics 1.8V SD card VOLmax=0.45V VOHmin=1.4V SC650T_Hardware_Design 28 / 131 Smart LTE Module Series SC650T Hardware Design SD_CMD 69 IO Command signal of SD card SD_DATA0 68 SD_DATA1 67 SD_DATA2 66 IO IO IO SD_DATA3 65 IO High speed bidirectional digital signal lines of SD card 2.95V SD card VOLmax=0.37V VOHmin=2.2V 1.8V SD card VILmax=0.58V VIHmin=1.27V VOLmax=0.45V VOHmin=1.4V 2.95V SD card VILmax=0.73V VIHmin=1.84V VOLmax=0.37V VOHmin=2.2V 1.8V SD card VILmax=0.58V VIHmin=1.27V VOLmax=0.45V VOHmin=1.4V 2.95V SD card VILmax=0.73V VIHmin=1.84V VOLmax=0.37V VOHmin=2.2V SD_DET 64 SD_LDO11 63 DI PO SD card insertion detection VILmax=0.63V VIHmin=1.17V Power supply for SD card Vnorm=2.95V IOmax=800mA Active low. SD_LDO12 179 PO 1.8V/2.95V output TP (Touch Panel) Interfaces Vnorm=1.8V/2.95 V IOmax=50mA Power supply for SD cards pull-up circuit. Pin Name Pin No. I/O Description DC Characteristics Comment TP0_RST 138 DO Reset signal of touch panel (TP0) VOLmax=0.45V VOHmin=1.35V 1.8V power domain. Active low. TP0_INT 139 DI Interrupt signal of touch panel (TP0) VILmax=0.63V VIHmin=1.17V TP0_I2C_ SCL 140 OD I2C clock signal of touch panel (TP0) 1.8V power domain. 1.8V power domain. SC650T_Hardware_Design 29 / 131 Smart LTE Module Series SC650T Hardware Design I2C data signal of touch panel (TP0) 1.8V power domain. Reset signal of touch panel (TP1) VOLmax=0.45V VOHmin=1.35V 1.8V power domain. Active low. TP1_INT 137 DI Interrupt signal of touch panel (TP1) VILmax=0.63V VIHmin=1.17V 1.8V power domain. 1.8V power domain. 1.8V power domain. TP0_I2C_ SDA 206 TP1_RST 136 TP1_I2C_ SDA TP1_I2C_ SCL 204 205 LCM Interfaces LCD_BIAS_P 21 LCD_BIAS_N 22 OD DO OD OD PO AI Pin Name Pin No. I/O Description DC Characteristics Comment I2C data signal of touch panel (TP1) I2C clock signal of touch panel (TP1) LCD positive bias voltage. LCD negative bias voltage. LCD enable for backlight. WLED_EN 158 DO WLED_PWM 30 DO PWM signal output LCD0_RST 127 DO LCD0 reset signal VOLmax=0.45V VOHmin=1.35V 1.8V power domain. Active low. LCD0_TE 126 DI LCD0 tearing effect signal VILmax=0.63V VIHmin=1.17V 1.8V power domain. LCD1_RST 113 DO LCD1 reset signal VOLmax=0.45V VOHmin=1.35V 1.8V power domain. Active low. LCD1 tearing effect signal VILmax=0.63V VIHmin=1.17V 1.8V power domain. LCD0 MIPI clock signal (negative) LCD1_TE 114 DSI0_CLK_N 116 DSI0_CLK_P 115 DI AO AO DSI0_LN0_N 118 AO DSI0_LN0_P 117 AO DSI0_LN1_N 120 AO LCD0 MIPI clock signal (positive) LCD0 MIPI lane 0 data signal
(negative) LCD0 MIPI lane 0 data signal
(positive) LCD0 MIPI lane 1 data signal
(negative) SC650T_Hardware_Design 30 / 131 Smart LTE Module Series SC650T Hardware Design DSI0_LN1_P 119 AO DSI0_LN2_N 122 AO DSI0_LN2_P 121 AO DSI0_LN3_N 124 AO DSI0_LN3_P 123 AO DSI1_CLK_N 103 DSI1_CLK_P 102 AO AO DSI1_LN0_N 105 AO DSI1_LN0_P 104 AO DSI1_LN1_N 107 AO DSI1_LN1_P 106 AO DSI1_LN2_N 109 AO DSI1_LN2_P 108 AO DSI1_LN3_N 111 AO DSI1_LN3_P 110 AO LCD0 MIPI lane 1 data signal
(positive) LCD0 MIPI lane 2 data signal
(negative) LCD0 MIPI lane 2 data signal
(positive) LCD0 MIPI lane 3 data signal
(negative) LCD0 MIPI lane 3 data signal
(positive) LCD1 MIPI clock signal (negative) LCD1 MIPI clock signal (positive) LCD1 MIPI lane 0 data signal
(negative) LCD1 MIPI lane 0 data signal
(positive) LCD1 MIPI lane 1 data signal
(negative) LCD1 MIPI lane 1 data signal
(positive) LCD1 MIPI lane 2 data signal
(negative) LCD1 MIPI lane 2 data signal
(positive) LCD1 MIPI lane 3 data signal
(negative) LCD1 MIPI lane 3 data signal
(positive) SC650T_Hardware_Design 31 / 131 Smart LTE Module Series SC650T Hardware Design Pin Name Pin No. I/O Description DC Characteristics Comment Camera Interfaces CSI0_CLK_N 89 CSI0_CLK_P 88 CSI0_LN0_N 91 CSI0_LN0_P 90 CSI0_LN1_N 93 CSI0_LN1_P 92 CSI0_LN2_N 95 CSI0_LN2_P 94 CSI0_LN3_N 97 CSI0_LN3_P 96 CSI2_CLK_N 78 CSI2_CLK_P 77 CSI2_LN0_N 80 AI AI AI AI AI AI AI AI AI AI AI AI AI MIPI clock signal of rear camera
(negative) MIPI clock signal of rear camera
(positive) MIPI lane 0 data signal of rear camera (negative) MIPI lane 0 data signal of rear camera (positive) MIPI lane 1 data signal of rear camera (negative) MIPI lane 1 data signal of rear camera (positive) MIPI lane 2 data signal of rear camera (negative) MIPI lane 2 data signal of rear camera (positive) MIPI lane 3 data signal of rear camera (negative) MIPI lane 3 data signal of rear camera (positive) MIPI clock signal of front camera
(negative) MIPI clock signal of front camera
(positive) MIPI lane 0 data signal of front camera (negative) SC650T_Hardware_Design 32 / 131 Smart LTE Module Series SC650T Hardware Design MIPI lane 0 data signal of front camera (positive) MIPI lane 1 data signal of front camera (negative) MIPI lane 1 data signal of front camera (positive) MIPI lane 2 data signal of front camera (negative) MIPI lane 2 data signal of front camera (positive) MIPI lane 3 data signal of front camera (negative) MIPI lane 3 data signal of front camera (positive) CSI2_LN0_P 79 CSI2_LN1_N 82 CSI2_LN1_P 81 CSI2_LN2_N 84 CSI2_LN2_P 83 CSI2_LN3_N 86 CSI2_LN3_P 85 MCAM_MCLK 99 SCAM_MCLK 100 MCAM_RST 74 SCAM_RST 72 MCAM_ PWDN SCAM_ PWDN CAM_I2C_ SCL CAM_I2C_ SDA 73 71 75 76 DCAM_MCLK 194 CAM4_MCLK 236 AI AI AI AI AI AI AI DO DO DO DO DO DO OD OD DO DO Master clock signal of rear camera VOLmax=0.45V VOHmin=1.35V Master clock signal of front camera VOLmax=0.45V VOHmin=1.35V Reset signal of rear camera VOLmax=0.45V VOHmin=1.35V Power down signal of rear camera VOLmax=0.45V VOHmin=1.35V Reset signal of front camera VOLmax=0.45V VOHmin=1.35V Power down signal of front camera VOLmax=0.45V VOHmin=1.35V I2C clock signal of camera I2C data signal of camera Master clock signal of depth camera VOLmax=0.45V VOHmin=1.35V Master clock signal of fourth camera VOLmax=0.45V VOHmin=1.35V 1.8V power domain. 1.8V power domain. 1.8V power domain. 1.8V power domain. 1.8V power domain. 1.8V power domain. 1.8V power domain. 1.8V power domain. DCAM_RST 180 DO Reset signal of VOLmax=0.45V SC650T_Hardware_Design 33 / 131 Smart LTE Module Series SC650T Hardware Design depth camera VOHmin=1.35V Power down signal of depth camera VOLmax=0.45V VOHmin=1.35V I2C data signal of depth camera I2C clock signal of depth camera 1.8V power domain. 1.8V power domain. DCAM_ PWDN DCAM_I2C_ SDA DCAM_I2C_ SCL 181 197 196 Keypad Interfaces PWRKEY 39 DO OD OD DI DI DI Pin Name Pin No. I/O Description DC Characteristics Comment Turn on/off the module VILmax=0.63V VIHmin=1.17V Pull-up to 1.8V internally. Active low. VILmax=0.63V VIHmin=1.17V VILmax=0.63V VIHmin=1.17V If unused, keep this pin open. If unused, keep this pin open. VOL_UP 146 Volume up VOL_DOWN 147 Volume down SENSOR_I2C Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment SENSOR_I2C _SCL SENSOR_I2C _SDA 131 132 ADC Interfaces OD OD I2C clock signal of external sensors I2C data signal of external sensors Pin Name Pin No. I/O Description PMU_MPP2 151 PMU_MPP4 152 AI AI General purpose ADC interface General purpose ADC interface BAT_THERM 29 AI Battery temperature detection BAT_ID 17 AI Battery type detection DC Characteristics Comment 1.8V power domain. 1.8V power domain. Maximum input voltage: 1.7V. Maximum input voltage: 1.7V. Internally pulled up. Externally connected to GND via a 47K NTC resistor. Maximum input voltage: 1.875V. Maximum input voltage: 1.875V.If unused, keep this pin SC650T_Hardware_Design 34 / 131 Smart LTE Module Series SC650T Hardware Design Charging Interface Pin Name Pin No. I/O Description DC Characteristics Comment open. BAT_PLUS 27 AI Must be connected. BAT_MINUS 28 AI Must be connected. Pin Name Pin No. I/O Description DC Characteristics Comment 50 impedance Differential input signal of battery voltage detection
(plus) Differential input signal of battery voltage detection
(minus) Main antenna interface Diversity antenna interface GNSS antenna interface Wi-Fi/BT antenna interface FM antenna interface IO AI AI IO AI IO IO IO IO IO IO IO GPIO GPIO GPIO GPIO GPIO GPIO GPIO VILmax=0.63V VIHmin=1.17V Antenna Interfaces ANT_MAIN 19 ANT_DRX 149 ANT_GNSS 134 ANT_WIFI/BT 129 ANT_FM 244 GPIO Interfaces GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_22 GPIO_23 248 247 201 200 58 59 GPIO_33 238 Pin Name Pin No. I/O Description DC Characteristics Comment SC650T_Hardware_Design 35 / 131 Smart LTE Module Series SC650T Hardware Design VOLmax=0.45V VOHmin=1.4V Suggest as ACCL_INT Suggest as ALSP_INT Suggest as GYRO_INT Suggest as MAG_INT GPIO_36 237 GPIO_42 252 GPIO_43 253 GPIO_44 254 GPIO_45 255 GPIO_46 153 GPIO_48 240 GPIO_59 234 GPIO_60 232 GPIO_90 231 GPIO_97 229 GPIO_98 177 GPIO_99 178 GPIO_105 242 GPIO_107 241 SPI Interfaces IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GRFC1 GRFC2 GRFC is only used for RF Tuner control. Pin Name Pin No. I/O Description DC Characteristics Comment FP_SPI_CS0 203 DO FP_SPI_CS1 232 DO FP_SPI_CLK 250 FP_SPI_MOSI 249 DO DO FP_SPI_MISO 251 DI Chip selection signal of SPI interface Chip selection signal of SPI interface Clock signal of SPI interface Master out slave in of SPI interface Master in salve out of SPI interface SC650T_Hardware_Design 36 / 131 Smart LTE Module Series SC650T Hardware Design Pin Name Pin No. I/O Description DC Characteristics Comment I2S_1_WS 156 DO I2S Interface I2S_MCLK 234 I2S_1_SCK 212 I2S_1_D0 154 I2S_1_D1 155 I2S_1_D2 213 I2S_1_D3 214 Vibrator Drive Interface DO DO IO IO IO IO Master clock signal of I2S interface Clock signal of I2S interface Channel selection signal of I2S interface Data0 signal of I2S interface Data1 signal of I2S interface Data2 signal of I2S interface Data3 signal of I2S interface Pin Name Pin No. I/O Description DC Characteristics Comment VIB_DRV 161 AO Vibrator drive LED Driver Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment LED_RED 23 PO Red LED light LED_GRN 24 PO Green LED light LED_BLU 25 PO Blue LED light Flashlight Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment SC650T_Hardware_Design 37 / 131 Connected to the positive terminal of vibrator. The output current does not exceed 12mA The output current does not exceed 12mA The output current does not exceed 12mA Smart LTE Module Series SC650T Hardware Design FLASH_LED1 26 FLASH_LED2 162 AO AO Flash/torch current driver output Flash/torch current driver output Emergency Download Interface USB_BOOT 57 DI Force the module to enter into emergency download mode Pin Name Pin No. I/O Description DC Characteristics Comment Support flash and torch modes. Pulled up to LDO5_1P8 during power-up will force the module to enter into emergency download mode. Other Interfaces Pin Name Pin No. I/O Description GNSS_LNA_ EN 202 DO LNA enable signal OPTION 211 DI Choose different charging modes DC Characteristics Comment If unused, keep this pin open. Choose Micro USB or TYPE-C Pin Name Pin No. I/O Description DC Characteristics Comment JTAG Interfaces JTAG_PS_HO LD JTAG_TRST_ N 183 184 DO Power hold signal JTAG reset DI DI DI DI DI JTAG_TCLK 188 JTAG clock input JTAG_TMS 185 JTAG mode-select input JTAG_TDO 186 DO JTAG data output JTAG_TDI 187 JTAG data input JTAG_SRST_ N 189 Reserved Interface JTAG reset for debug Pin Name Pin No. I/O Description DC Characteristics Comment SC650T_Hardware_Design 38 / 131 Smart LTE Module Series SC650T Hardware Design RESERVED Reserved pins Keep these pins open. 164,165,16 6,190,191, 192222 3.4. Power Supply 3.4.1. Power Supply Pins SC650T provides 3 VBAT pins,2 VDD_RF pins and 2 VPH_PWR pins. VBAT pins are dedicated for connection with an external power supply. VDD_RF pins are designed for modules RF part, and are used to connect bypass capacitors so as to eliminate voltage fluctuation of RF part. VPH_PWR pins are designed for peripherals. 3.4.2. Decrease Voltage Drop The power supply range of the module is from 3.55V to 4.4V, and the recommended value is 3.8V. The power supply performance, such as load capacity, voltage ripple, etc. directly influences the modules performance and stability. Under ultimate conditions, the module may have a transient peak current up to 3A. If the power supply capability is not sufficient, there will be voltage drops, and if the voltage drops below 3.1V, the module will be powered off automatically. Therefore, please make sure the input voltage will never drop below 3.1V. Figure 2: Voltage Drop Sample To decrease voltage drop, a bypass capacitor of about 100F with low ESR (ESR=0.7) should be used, and a multi-layer ceramic chip capacitor (MLCC) array should also be reserved due to its ultra-low ESR. It is recommended to use three ceramic capacitors (100nF, 33pF, 10pF) for composing the MLCC array, and place these capacitors close to VBAT/VDD_RF pins. The width of VBAT trace should be no less than 3mm. In principle, the longer the VBAT trace is, the wider it will be. In addition, in order to get a stable power source, it is suggested to use a 0.5W TVS and place it as close to the VBAT pins as possible to increase voltage surge withstand capability. The following figure shows SC650T_Hardware_Design 39 / 131 3A Input current Voltage 3.8V 3.1V Smart LTE Module Series SC650T Hardware Design the structure of the power supply. Figure 3: Star Structure of Power Supply 3.4.3. Reference Design for Power Supply The power design for the module is very important, as the performance of module largely depends on the power source. The power supply of SC650T should be able to provide sufficient current up to 3A at least. By default, it is recommended to use a battery to supply power for SC650T. But if battery is not intended to be used, it is recommended to use a regulator for SC650T. If the voltage difference between the input and output is not too high, it is suggested to use an LDO to supply power for the module. If there is a big voltage difference between the input source and the desired output (VBAT), a buck converter is preferred to be used as the power supply. The following figure shows a reference design for +5V input power source which adopts an LDO
(MIC29502WU) from MICROCHIP. The typical output voltage is 3.8V and the maximum rated current is 5.0A. Figure 4: Reference Circuit of Power Supply SC650T_Hardware_Design 40 / 131 VBAT
C5 D1 C1 C2 C3 C4 C6 C7 C8 100uF 100nF 33pF 10pF NM 100nF 33pF 10pF VDD_RF VBAT Module DC_IN VBAT MIC29502WU U1 2 IN N E OUT 4 J D A D N G 1 3 5 C1 470uF C2 R1 100nF 51K R2 100K 1%
R3 47K 1%
R4 470R C3 C4 470uF 100nF Smart LTE Module Series SC650T Hardware Design NOTES 1. It is recommended to switch off the power supply for module in abnormal state, and then switch on the power to restart the module. 2. The module supports battery charging function by default. If the above power supply design is adopted, please make sure the charging function is disabled by software, or connect VBAT to Schottky diode in series to avoid the reverse current to the power supply chip. 3. When the battery power is reduced to 0%, the system will trigger automatic shutdown, so the design of power supply should be consistent with the configuration of fuel gauge driver. 3.5. Turn on and off Scenarios 3.5.1. Turn on Module Using the PWRKEY The module can be turned on by driving PWRKEY pin to a low level for at least 1.6s. PWRKEY pin is pulled to 1.8V internally. It is recommended to use an open drain/collector driver to control the PWRKEY. A simple reference circuit is illustrated in the following figure. Figure 5: Turn on the Module Using Driving Circuit Another way to control the PWRKEY is using a button directly. A TVS component is indispensable to be placed nearby the button for ESD protection. A reference circuit is shown in the following figure. SC650T_Hardware_Design 41 / 131
>1.6s Turn on pulse R1 4.7K PWRKEY R3 1K Q1 R2 47K Smart LTE Module Series SC650T Hardware Design Figure 6: Turn on the Module Using Keystroke The turning on scenario is illustrated in the following figure. Figure 7: Timing of Turning on Module NOTES SC650T_Hardware_Design 42 / 131 S1 PWRKEY 1K TVS Close to S1 VBA T (Typ e:3.8V) Note2 PWRKEY
>1.6s LDO5_1P8 LDO6_1P8 LDO10_2P8 LDO17_2P85 Others 61.2ms Software controlled Software controlled 38s Acti ve Smart LTE Module Series SC650T Hardware Design 1. The turn-on timing might be different from the above figure when the module powers on for the first time. 2. Make sure that VBAT is stable before pulling down PWRKEY pin. The recommended time between them is no less than 30ms. PWRKEY cannot be pulled down all the time. 3.5.2. Turn off Module Pull down PWRKEY for at least 1s, and then choose to turn off the module when the prompt window comes up. Another way to turn off the module is to drive PWRKEY to a low level for at least 8s. The module will execute forced shutdown. The forced power-down scenario is illustrated in the following figure. Figure 8: Timing of Turning off Module 3.6. VRTC Interface The RTC (Real Time Clock) can be powered by an external power source through VRTC when the module is powered down and there is no power supply for the VBAT. The external power source can be rechargeable battery (such as coil cells) according to application demands. The following reference circuit design when an external battery is utilized for powering RTC. Figure 9: RTC Powered by Coin Cell SC650T_Hardware_Design 43 / 131 VBAT PWRKEY Others
> 8s Power down Coin Cell VRTC RTC Core Module Smart LTE Module Series SC650T Hardware Design If RTC is ineffective, it can be synchronized through network after the module is powered on. 2.0V~3.25V input voltage range and 3.0V typical value for VRTC, when VBAT is disconnected. When powered by VBAT, the RTC error is 50ppm. When powered by VRTC, the RTC error is about 200ppm. If the rechargeable battery is used, the ESR of battery should be less than 2K, and it is recommended to use the MS621FE FL11E of SEIKO. 3.7. Power Output SC650T supports output of regulated voltages for peripheral circuits. During application, it is recommended to use parallel capacitors (33pF and 10pF) in the circuit to suppress high frequency noise. Table 6: Power Description Pin Name Default Voltage (V) Drive Current (mA) Idle LDO5_1P8 LDO6_1P8 LDO10_2P8 LDO2_1P1 LDO22_2P8 LDO23_1P2 1.8 1.8 2.8 1.1 2.8 1.2 LDO17_2P85 2.85 LDO13_3P075 3.125 SD_LDO12 1.8/2.95 SD_LDO11 2.95 USIM1_VDD 1.8/2.95 USIM2_VDD 1.8/2.95 1200 20 300 150 300 150 150 600 50 800 50 50 Keep
SC650T_Hardware_Design 44 / 131 Smart LTE Module Series SC650T Hardware Design 3.8. Battery Charge and Management SC650T module supports a fully programmable switch-mode Li-ion battery charge function. It can charge single-cell Li-ion and Li-polymer battery. The battery charger of SC650T module supports trickle charging, pre-charge, constant current charging and constant voltage charging modes, which optimize the charging procedure for Li-ion batteries. Trickle charging: When the battery voltage is below 2.1V, a 45mA trickle charging current is applied to the battery. Pre-charge: When the battery voltage is charged up and is between 2.1V and 3.0V (the maximum pre-charge voltage is 2.4V~3.0V programmable, 3.0V by default), the system will enter into pre-charge mode. The charging current is 250mA (100mA~250mA programmable, 250mA by default). Constant current mode (CC mode): When the battery voltage is increased to between the maximum pre-charge voltage and 4.2V (3.6V~4.5V programmable, 4.2V by default), the system will switch to CC mode. The charging current is programmable from 300mA~3000mA. The default charging current is 500mA for USB charging and 2A for adapter. Constant voltage mode (CV mode): When the battery voltage reaches the final value 4.2V, the system will switch to CV mode and the charging current will decrease gradually. When the charging current reduces to about 100mA, the charging is completed. Table 7: Pin Definition of Charging Interface Pin Name Pin No. I/O Description Comment USB_VBUS 41, 42 PI/PO Charging power input. Power supply output for OTG device. USB/charger insertion detection. VBAT PI/PO Power supply for the module 36,37, 38 BAT_ID 17 Battery type detection BAT_PLUS 27 BAT_MINUS 28 AI AI AI Differential input signal of battery voltage detection (plus) Differential input signal of battery voltage detection (minus) BAT_THERM 29 AI Battery temperature detection Vmax=10V Vmin=4.0V Vnorm=5.0V Vmax=4.4V Vmin=3.55V Vnorm=3.8V If unused, keep this pin open. Must be connected. Must be connected. Internally pulled up. Externally connected to GND via a 47K NTC resistor. SC650T module supports battery temperature detection in the condition that the battery integrates a SC650T_Hardware_Design 45 / 131 Smart LTE Module Series SC650T Hardware Design thermistor (47K 1% NTC thermistor with B-constant of 4050K by default; SDNT1608X473F4050FTF of SUNLORD is recommended) and the thermistor is connected to VBAT_THERM pin. If VBAT_THERM pin is not connected, there will be malfunctions such as boot error, battery charging failure, battery level display error, etc. A reference design for battery charging circuit is shown as below. Figure 10: Reference Design for Battery Charging Circuit SC650T offers a fuel gauge algorithm that is able to accurately estimate the batterys state by current and voltage monitor techniques. Using precise measurements of battery voltage, current, and temperature, the fuel gauge provides a dependable state of charge estimate throughout the entire life of the battery and across a broad range of operating conditions. It effectively protects the battery from over-discharging, and also allows users to estimate the battery life based on the battery level so as to timely save important data before completely power-down. Mobile devices such as mobile phones and handheld POS systems are powered by batteries. When different batteries are utilized, the charging and discharging curve has to be modified correspondingly so as to achieve the best effect. If thermistor is not available in the battery, or adapter is utilized for powering the module, then there is only a need for VBAT and GND connection. In this case, the system may be unable to detect the battery, which will cause power-on failure. In order to avoid this, VBAT_THERM should be connected to GND with a 47K resistor. VBAT_SNS, BAT_PLUS and BAT_MINUS must be connected, otherwise there may be abnormalities in use of the module. Among them, BAT_PLUS and BAT_MINUS are used for battery level detection, and they should be routed as differential pair to ensure accuracy. SC650T_Hardware_Design 46 / 131 Adapter or USB R2 NC R3 NC R1 0R 0805 VBAT NTC GND Battery D1 D2 C1 C2 C3 ESD ESD 100uF 1 uF 33 pF USB _VBUS CS _PLUS CS _MINUS VBAT BAT_PLUS VBAT_SNS BAT_THERM BAT _ MINUS GND Module Smart LTE Module Series SC650T Hardware Design 3.9. USB Interface SC650T provides one integrated Universal Serial Bus (USB) interface which complies with the USB 3.0/2.0 specifications and supports super speed (5Gbps) on USB 3.0, high speed (480Mbps) on USB 2.0 and full speed (12Mbps) modes. The USB interface supports USB OTG function, and is used for AT command communication, data transmission, software debugging and firmware upgrade. The following table shows the pin definition of USB interface. Table 8: Pin Definition of USB Interface Pin Name Pin No. I/O Description USB_VBUS 41, 42 PI/PO USB_DM USB_DP 33 32 USB_SS_RX_P 171 USB_SS_RX_M 172 IO IO AI AI USB_SS_TX_P 174 AO USB_SS_TX_M 175 AO USBC_CC2 223 AI/AO Vmax=10V Vmin=4V Vnorm=5.0V Require differential impedance of 90 Require differential impedance of 90 Charging power input;
Power supply output for OTG device;
USB/charger insertion detection. USB 2.0 USB differential data bus (minus) USB 2.0 USB differential data bus (plus) USB 3.0 differential receive
(plus) USB 3.0 differential receive
(minus) USB 3.0 differential transmit
(plus) USB 3.0 differential transmit
(minus) USB Type-C control configuration channel 2 USB Type-C control configuration channel 1 USBC_CC1 224 AI/AO Micro USB mode is USB_ID CC_OUT 225 DO USB Type-C switch control USB_VBUS can be powered by USB power or adapter. It is used for USB connection detection and power supply input for battery charging. Its input voltage ranges from 4.0V to 10.0V, and the typical value is 5.0V. SC650T module supports charging management for a single cell Li-ion battery, but varied charging parameters should be set for batteries with varied models or capacities. The maximum charging current is up to 3.0A. The module also supports USB On-The-Go (OTG) function, through using USB_ID pin to detect whether SC650T_Hardware_Design 47 / 131 Smart LTE Module Series SC650T Hardware Design the OTG device is attached: when USB_ID is kept open (high level by default), SC650T is in USB slave mode; if USB_ID is connected to ground, it is in OTG mode and USB_VBUS is used to supply power for peripherals with maximum output of 5V/1A. The following is a reference design for USB interface:
Figure 11: USB 2.0 Interface Reference Design Figure 12: USB Type-C Interface Reference Design In order to ensure USB performance, please follow the following principles while designing USB interface. It is important to route the USB signal traces as differential pairs with total grounding. The impedance of USB differential trace is 90. Pay attention to the influence of junction capacitance of ESD protection devices on USB data lines. Typically, the capacitance value should be less than 2pF for USB 2.0 and less than 0.5pF for USB 3.0. Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is SC650T_Hardware_Design 48 / 131 USB_VUSB USB_DM USB_DP USB_ID Module C1 D1 D2 D3 100nF ESD ESD ESD 89 D N G D N G 1 2 3 4 5 VUSB USB_DM USB_DP USB_ID GND D N G D N G 6 7 Module USB_ VBUS USB_DM USB_DP CC1 CC2 USB_SS_TX_P USB_SS_TX_M USB_SS_RX_P USB_SS_RX_M CC_OUT VDD_3V C2 C3 C4 C5 A0+
A0-
A1+
A0-
SEL VDD PD B0+
B0-
B1+
B1-
C6 C7 C8 C9 C0+
C10 C0-
C11 C1+
C12 C1-
C13 C1 C14 R1 4.7uF 100nF Switch USB 3.0 VBUS_ VBUS D-
D+
CC1 CC2 TX1+
TX1-
RX1+
RX1-
TX2+
TX2-
RX2+
RX2-
33 32 171 172 174 175 Smart LTE Module Series SC650T Hardware Design important to route the USB differential traces in inner-layer with ground shielding on not only upper and lower layers but also right and left sides. Keep the ESD protection devices as close as possible to the USB connector. Make sure the trace length difference between USB 2.0 DM/DP differential pair and that between USB 3.0 RX/TX differential pairs both do not exceed 0.7mm. Table 9: USB Trace Length Inside the Module Pin No. Signal Length (mm) Length Difference (DP-DM) USB_DM USB_DP USB_SS_RX_P USB_SS_RX_M USB_SS_TX_P USB_SS_TX_M 40.02 39.99 27.89 27.90 21.51 22.42
-0.04 0.01 0.91 3.10. UART Interfaces The module provides the following four UART interfaces:
UART5: 4-wire UART interface, hardware flow control supported, 1.8V power domain UART6: 2-wire UART interface, UART2: 2-wire UART interface, used for debugging UART4: 2-wire UART interface The following table shows the pin definition of UART interfaces. Table 10: Pin Definition of UART Interfaces Pin Name Pin No. I/O Description Comment UART2_TXD 5 UART2_RXD 6 DO DI UART2 transmit data. Debug port by default. UART2 receive data. Debug port by default. 1.8V power domain. If unused, keep these pins open. SC650T_Hardware_Design 49 / 131 Smart LTE Module Series SC650T Hardware Design UART4_TXD DO UART4 transmit data 7 8 UART4_RXD UART4 receive data UART5_RXD 198 UART5 receive data UART5_TXD 199 UART5 transmit data UART5_CTS 246 UART5 clear to send UART5_RTS 245 UART5 request to send UART6_RXD 61 UART6 receive data UART6_TXD 60 UART6 transmit data DI DI DO DI DO DI DO UART5 is a 4-wire UART interface with 1.8V power domain. A level translator chip should be used if customers application is equipped with a 3.3V UART interface. A level translator chip TXS0104EPWR provided by Texas Instruments is recommended. The following figure shows a reference design. Figure 13: Reference Circuit with Level Translator Chip (for UART5) The following figure is an example of connection between SC650T and PC. A voltage level translator and a RS-232 level translator chip are recommended to be added between the module and PC, as shown below:
SC650T_Hardware_Design 50 / 131 LDO5_1P8 VCCA VCCB VDD_3.3V C1 100 pF U1 GND C2 100pF UART5_ CTS UART 5_ RTS UART5_ TXD UART5_ RXD OE A1 A2 A3 A4 TXS0104 EPWR B1 B2 B3 B4 CTS_3.3V RTS_3.3V TXD_3.3V RXD_3.3V Smart LTE Module Series SC650T Hardware Design Figure 14: RS232 Level Match Circuit (for UART5) NOTE UART2, UART4 and UART6 are similar to UART5. Please refer to UART5 reference circuit design for UART2, UART4 and UART6s. 3.11. (U)SIM Interfaces SC650T provides two (U)SIM interfaces which both meet ETSI and IMT-2000 requirements. Dual SIM Dual Standby is supported by default. Both 1.8V and 2.95V (U)SIM cards are supported, and the (U)SIM interfaces are powered by the dedicated low dropout regulators from SC650T module. Table 11: Pin Definition of (U)SIM Interfaces Pin Name Pin No. I/O Description Comment USIM1_DET 145 DI
(U)SIM1 card detection USIM1_RST 144 DO
(U)SIM1 card reset signal USIM1_CLK 143 DO
(U)SIM1 card clock signal Active Low. Need external pull-up to 1.8V. If unused, keep this pin open. Disabled by default, and can be enabled through software configuration. SC650T_Hardware_Design 51 / 131 1.8V 3.3V OE VCCA TXD_1.8V RTS_1.8V VCCB TXD_3.3V RTS_3.3V UART5_TXD UART5_RTS VCC DIN 1 DIN 2 DIN 3 DIN 4 DIN 5 R1OUTB ROUT1 ROUT 2 ROUT3 GND DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 RIN1 RIN2 RIN3 GND RXD CTS TXD RTS UART5_RXD UART5_CTS RXD_1.8V CTS_1.8V RXD_3.3V CTS_3.3V GND GND Module TXS0104 EPWR SN65C 3238 DB-9 3.3V FORCEON
/FORCEOFF
/INVALID Smart LTE Module Series SC650T Hardware Design USIM1_DATA 142 IO
(U)SIM1 card data signal USIM1_VDD 141 PO
(U)SIM1 card power supply USIM2_DET 256 DI
(U)SIM2 card insertion detection USIM2_RST 207 DO
(U)SIM2 card reset signal USIM2_CLK 208 DO
(U)SIM2 card clock signal USIM2_DATA 209 IO
(U)SIM2 card data signal USIM2_VDD 210 PO
(U)SIM2 card power supply Pull up to USIM1_VDD with a 10K resistor. Either 1.8V or 2.95V (U)SIM card is supported. Active low. Need external pull-up to 1.8V. If unused, keep this pin open. Disabled by default, and can be enabled through software configuration. Pull-up to USIM2_VDD with a 10K resistor. Either 1.8V or 2.95V (U)SIM card is supported. SC650T supports (U)SIM card hot-plug via the USIM_DET pin, which is disabled by default and can be enabled through software configuration. A reference circuit for (U)SIM interface with an 8-pin (U)SIM card connector is shown as below. Figure 15: Reference Circuit for (U)SIM Interface with an 8-pin (U)SIM Card Connector If there is no need to use USIM_DET, please keep it open. The following is a reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector. SC650T_Hardware_Design 52 / 131 LD05_1P8 USIM_ VDD R1 100K R2 10K Module USIM_ VDD USIM_ RST USIM_ CLK USIM_ DET R3 R4 22R 22R USIM_ DATA R5 22R C1 100nF
(U)SIM Card Connector VCC RST CLK GND VPP IO C2 C3 C4 22pF 22pF 22pF D1 ESD Smart LTE Module Series SC650T Hardware Design Figure 16: Reference Circuit for (U)SIM Interface with a 6-pin (U)SIM Card Connector In order to ensure good performance and avoid damage of (U)SIM cards, please follow the criteria below in (U)SIM circuit design:
Keep placement of (U)SIM card connector as close to the module as possible. Keep the trace length of (U)SIM card signals as less than 200mm as possible. Keep (U)SIM card signals away from RF and VBAT traces. A filter capacitor shall be reserved for USIM_VDD, and its maximum capacitance should not exceed 1uF. The capacitor should be placed near to (U)SIM card. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with ground. USIM_RST also needs ground protection. In order to offer good ESD protection, it is recommended to add a TVS diode array with parasitic capacitance not exceeding 50pF. The 22 resistors should be added in series between the module and (U)SIM card so as to suppress EMI spurious transmission and enhance ESD protection. Please note that the (U)SIM peripheral circuit should be close to the (U)SIM card connector. The 22pF capacitors should be added in parallel on USIM_DATA, USIM_VDD, USIM_CLK and USIM_RST signal lines so as to filter RF interference, and they should be placed as close to the
(U)SIM card connector as possible. 3.12. SD Card Interface SC650T module supports SD 3.0 specifications. The pin definition of the SD card interface is shown below. SC650T_Hardware_Design 53 / 131 USIM _VDD R1 10K Module USIM_ VDD USIM_ RST USIM_ CLK USIM_ DET USIM_ DATA R4 22R R2 R3 22R 22R C1 100nF
(U)SIM Card Connector VCC RST CLK GND VPP IO C2 C3 C4 22pF 22pF 22pF D1 ESD Smart LTE Module Series SC650T Hardware Design Table 12: Pin Definition of SD Card Interface Pin Name Pin No. I/O Description Comment SD_LDO11 63 PO Power supply for SD card Vnorm=2.95V IOmax=800mA SD_LDO12 179 PO SD card pull-up power supply Support 1.8V or 2.95V power supply. The maximum drive current is 50mA. SD_CLK 70 DO High speed digital clock signal of SD card SD_CMD 69 I/O Command signal of SD card SD_DATA0 68 SD_DATA1 67 SD_DATA2 66 SD_DATA3 65 I/O I/O I/O I/O High speed bidirectional digital signal lines of SD card SD_DET 64 DI SD card insertion detection Active low. A reference circuit for SD card interface is shown as below. Control characteristic impedance as 50. Figure 17: Reference Circuit for SD Card Interface SD_LDO11 is a peripheral driver power supply for SD card. The maximum drive current is approx. 800mA. Because of the high drive current, it is recommended that the trace width is 0.5mm or above. In order to ensure the stability of drive power, a 4.7uF and a 33pF capacitor should be added in parallel near the SD card connector. SC650T_Hardware_Design 54 / 131 LDO5_1P8 SD_LDO12 SD_LDO11 R1 R2 R3 R4 R5 R6 NM_51K NM_51K NM_10K NM_51K NM_51K SD_DATA2 SD_DATA3 SD_CMD SD_CLK SD_DATA0 SD_DATA1 SD_DET 120K 33R 33R 33R R7 R8 R9 R10 33R R11 R12 R13 33R 33R 1K Module D1 D2 D3 D4 D5 D6 D7 C1 C2 D8 4.7uF 33pF 1 2 3 4 5 6 7 8 9 P1-DAT2 P2-CD/DAT3 P3-CMD P4-VDD P5-CLK P6-VSS P7-DAT0 P8-DAT1 DETECTIVE 10 11 12 13 GND GND GND GND SD Card Connector Smart LTE Module Series SC650T Hardware Design CMD, CLK, DATA0, DATA1, DATA2 and DATA3 are all high speed signal lines. In PCB design, please control the characteristic impedance of them as 50, and do not cross them with other traces. It is recommended to route the trace on the inner layer of PCB, and keep the same trace length for CLK, CMD, DATA0, DATA1, DATA2 and DATA3. CLK additionally needs ground shielding. Layout guidelines:
Control impedance as 5010%, and ground shielding is required. The total trace length difference between CLK and other signal line traces should not exceed 1mm. Table 13: SD Card Signal Trace Length Inside the Module Pin No. Signal Length (mm) Comment 70 69 68 67 66 65 SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 30.44 31.60 31.50 30.96 32.70 31.62 3.13. GPIO Interfaces SC650T has abundant GPIO interfaces with power domain of 1.8V. The pin definition is listed below. Table 14: Pin Definition of GPIO Interfaces Pin Name Pin No. GPIO Default Status Comment GPIO_0 GPIO_1 GPIO_2 GPIO_3 248 247 201 200 GPIO_0 B-PD:nppukp 1) GPIO_1 B-PD:nppukp Wakeup 2) GPIO_2 B-PD:nppukp GPIO_3 B-PD:nppukp SC650T_Hardware_Design 55 / 131 Smart LTE Module Series SC650T Hardware Design GPIO_4 B-PD:nppukp GPIO_5 B-PD:nppukp Wakeup TP1_I2C_SDA GPIO_6 B-PD:nppukp TP1_I2C_SCL GPIO_7 B-PD:nppukp GPIO_8 B-PD:nppukp GPIO_9 B-PD:nppukp Wakeup TP0_I2C_SDA GPIO_10 B-PD:nppukp TP0_I2C_SCL GPIO_11 B-PD:nppukp UART4_TXD UART4_RXD GPIO_12 B-PD:nppukp Wakeup GPIO_13 B-PD:nppukp Wakeup SENSOR_I2C_SDA 132 GPIO_14 B-PD:nppukp SENSOR_I2C_SCL 131 GPIO_15 B-PD:nppukp GPIO_16 B-PD:nppukp GPIO_17 B-PD:nppukp Wakeup UART2_TXD UART2_RXD TP1_RST TP1_INT UART5_TXD UART5_RXD UART5_CTS UART5_RTS UART6_TXD UART6_RXD GPIO_22 GPIO_23 LCD0_TE LCD1_TE MCAM_MCLK SCAM_MCLK DCAM_MCLK 5 6 204 205 136 137 206 140 7 8 199 198 246 245 60 61 58 59 126 114 99 100 194 GPIO_21 B-PD:nppukp Wakeup GPIO_18 B-PD:nppukp GPIO_19 B-PD:nppukp GPIO_20 B-PD:nppukp GPIO_22 B-PD:nppukp GPIO_23 B-PD:nppukp GPIO_24 B-PD:nppukp GPIO_26 B-PD:nppukp GPIO_27 B-PD:nppukp GPIO_25 B-PD:nppukp Wakeup GPIO_28 B-PD:nppukp Wakeup SC650T_Hardware_Design 56 / 131 Smart LTE Module Series SC650T Hardware Design CAM_I2C_SDA GPIO_29 B-PD:nppukp CAM_I2C_SCL GPIO_30 B-PD:nppukp DCAM_I2C_SDA 197 GPIO_31 B-PD:nppukp Wakeup DCAM_I2C_SCL 196 GPIO_32 B-PD:nppukp GPIO_33 B-PD:nppukp GPIO_36 B-PD:nppukp Wakeup MCAM_PWDN GPIO_39 B-PD:nppukp MCAM_RST GPIO_40 B-PD:nppukp 76 75 238 237 73 74 252 253 254 255 153 240 235 239 127 138 139 234 146 113 155 232 231 GPIO_33 GPIO_36 GPIO_42 GPIO_43 GPIO_44 GPIO_45 GPIO_46 GPIO_48 GPIO_59 GPIO_60 LCD0_RST TP0_RST TP0_INT I2S_MCLK VOL_UP LCD1_RST I2S_1_D1 GPIO_42 B-PD:nppukp Wakeup GPIO_43 B-PD:nppukp Wakeup GPIO_44 B-PD:nppukp Wakeup GPIO_45 B-PD:nppukp Wakeup GPIO_46 B-PD:nppukp Wakeup GPIO_48 B-PD:nppukp Wakeup GPIO_59 B-PD:nppukp Wakeup GPIO_60 B-PD:nppukp Wakeup GPIO_61 B-PD:nppukp Wakeup GPIO_64 B-PD:nppukp GPIO_65 B-PD:nppukp Wakeup GPIO_69 B-PD:nppukp GPIO_85 B-PD:nppukp Wakeup GPIO_87 B-PD:nppukp Wakeup GPIO_88 B-PD:nppukp FP_SPI_CS1 GPIO_89 B-PD:nppukp GPIO_90 GPIO_90 B-PD:nppukp Wakeup SC650T_Hardware_Design 57 / 131 212 156 154 213 214 230 229 177 178 242 241 236 72 71 180 181 64 250 203 249 251 I2S_1_SCK I2S_1_WS I2S_1_D0 I2S_1_D2 I2S_1_D3 WSA_EN GPIO_97 GPIO_98 GPIO_99 GPIO_105 GPIO_107 CAM4_MCLK SCAM_RST SD_DET FP_SPI_CLK FP_SPI_CS0 NOTES Smart LTE Module Series SC650T Hardware Design GPIO_91 B-PD:nppukp Wakeup GPIO_92 B-PD:nppukp GPIO_93 B-PD:nppukp Wakeup GPIO_97 B-PD:nppukp Wakeup GPIO_94 B-PD:nppukp GPIO_95 B-PD:nppukp GPIO_96 B-PD:nppukp GPIO_98 B-PD:nppukp GPIO_99 B-PD:nppukp GPIO_105 B-PD:nppukp GPIO_107 B-PD:nppukp GPIO_128 B-PD:nppukp GPIO_129 B-PD:nppukp is only for RF GRFC used Tuner control SCAM_PWDN 3) GPIO_130 B-PD:nppukp DCAM_RST GPIO_131 B-PD:nppukp Wakeup DCAM_PWDN 3) GPIO_132 B-PD:nppukp Wakeup GPIO_133 B-PD:nppukp Wakeup GPIO_135 B-PD:nppukp GPIO_136 B-PD:nppukp FP_SPI_MOSI GPIO_137 B-PD:nppukp Wakeup FP_SPI_MISO GPIO_138 B-PD:nppukp 1. 2. 3. 1) B: Bidirectional digital with CMOS input; PD: nppukp = default pulldown with programmable options following the colon (:). 2) Wakeup: interrupt pins that can wake up the system. 3) SCAM_PWDN and DCAM_PWDN cannot be pulled up when the module starts up. SC650T_Hardware_Design 58 / 131 Smart LTE Module Series SC650T Hardware Design 4. More details about GPIO configuration, please refer to document [2]. 3.14. I2C Interfaces SC650T provides five I2C interfaces. As an open drain output, each I2C interface should be pulled up to 1.8V voltage. The SENSOR_I2C the aDSP architecture. CAM/DCAM_I2C bus is controlled by Linux Kernel code and supports connection to video output related devices. interface supports only sensors of Table 15: Pin Definition of I2C Interfaces Pin Name Pin No I/O Description Comment TP0_I2C_SCL TP0_I2C_SDA TP1_I2C_SCL TP1_I2C_SDA CAM_I2C_SCL CAM_I2C_SDA DCAM_I2C_SCL DCAM_I2C_SDA 140 206 205 204 75 76 196 197 SENSOR_I2C_SCL 131 OD OD OD OD OD OD OD OD OD I2C clock signal of touch panel I2C data signal of touch panel Used for TP0 I2C clock signal of touch panel I2C data signal of touch panel Used for TP1 I2C clock signal of main camera I2C data signal of main camera I2C clock signal of front camera I2C data signal of front camera I2C clock signal for external sensor Used for main cameras Used for front cameras Used for external sensors SENSOR_I2C_SDA 132 OD I2C data signal for external sensor 3.15. I2S Interface SC650T provides one I2S interface, with power domain of 1.8V . SC650T_Hardware_Design 59 / 131 Smart LTE Module Series SC650T Hardware Design Table 16: Pin Definition of I2S Interface Pin Name Pin No I/O Description Comment I2S_MCLK 234 I2S_1_SCK 212 I2S_1_WS 156 I2S_1_D0 154 I2S_1_D1 155 I2S_1_D2 213 I2S_1_D3 214 DO DO DO IO IO IO IO Master clock signal of I2S interface Clock signal of I2S interface I2S_MCLK I2S_1_SCK Channel selection signal of I2S interface I2S_1_WS Data0 signal of I2S interface Data1 signal of I2S interface Data2 signal of I2S interface Data3 signal of I2S interface I2S_1_D0 I2S_1_D1 I2S_1_D2 I2S_1_D3 3.16. SPI Interfaces SC650T provides two SPI interfaces which only support master mode. The two interfaces are typically applied for fingerprint identification. Table 17: Pin Definition of SPI Interfaces Pin Name Pin No I/O Description Comment 58 59 GPIO_22 DO Chip selection signal of SPI interface GPIO_23 DO Clock signal of SPI interface UART6_TXD 60 DO Master out slave in of SPI interface UART6_RXD 61 DI Master in salve out of SPI interface FP_SPI_CS0 203 DO Chip selection signal of SPI interface Used for fingerprint FP_SPI_CS1 232 DO Chip selection signal of SPI interface Can be multiplexed into SPI_CS. Can be multiplexed into SPI_CLK. Can be multiplexed into SPI_MOSI. Can be multiplexed into SPI_MISO. identification by default. Can be SC650T_Hardware_Design 60 / 131 Smart LTE Module Series SC650T Hardware Design FP_SPI_CLK 250 DO Clock signal of SPI interface FP_SPI_MOSI 249 DO Master out slave in of SPI interface FP_SPI_MISO 251 DI Master in salve out of SPI interface multiplexed into I2S interface. 3.17. ADC Interfaces SC650T provides two analog-to-digital converter (ADC) interfaces, and the pin definition is shown below. Table 18: Pin Definition of ADC Interfaces Pin Name Pin No. I/O Description Comment PMU_MPP4 152 Maximum input voltage: 1.7V. PMU_MPP2 151 Maximum input voltage: 1.7V. AI AI General purpose ADC interface General purpose ADC interface The resolution of the ADC is up to 15 bits. 3.18. Vibrator Drive Interface The pin definition of vibrator drive interface is listed below. Table 19: Pin Definition of Vibrator Drive Interface Pin Name Pin No I/O Description Comment VIB_DRV 161 AO Vibrator drive (positive) Connected to the positive terminal of vibrator. The Vibrator is driven by an exclusive circuit, and a reference circuit design is shown below. SC650T_Hardware_Design 61 / 131 Smart LTE Module Series SC650T Hardware Design Figure 18: Reference Circuit for Vibrator Connection 3.19. LCM Interfaces SC650T module provides two LCM interfaces, and supports dual LCDs with WUXGA (19001200) display. The interfaces support high speed differential data transmission, with up to eight lanes. Table 20: Pin Definition of LCM Interfaces Pin Name Pin No. I/O Description Comment PO PO 1.8V output power supply for LCM logic circuit and DSI 2.85V output power supply for LCM analog circuits WLED_PWM DO PWM signal output WLED_EN 158 DO LCD enable for backlight. LDO6_1P8 LDO17_2P85 LCD_BIAS_P LCD_BIAS_N LCD0_RST LCD0_TE LCD1_RST LCD1_TE 10 12 30 21 22 127 126 113 114 PO LCD positive bias voltage. PO LCD negative bias voltage. DO LCD0 reset signal Active low. DI LCD0 tearing effect signal DO LCD1 reset signal Active low. DI LCD1 tearing effect signal SC650T_Hardware_Design 62 / 131 VIB_DRV Module VIB_DRV GND Motor 33pF C1 PESD5V0H1BSF Smart LTE Module Series SC650T Hardware Design DSI0_CLK_N 116 AO DSI0_CLK_P 115 AO DSI0_LN0_N 118 AO DSI0_LN0_P 117 AO DSI0_LN1_N 120 AO DSI0_LN1_P 119 AO DSI0_LN2_N 122 AO DSI0_LN2_P 121 AO DSI0_LN3_N 124 AO DSI0_LN3_P 123 AO DSI1_CLK_N 103 AO DSI1_CLK_P 102 AO DSI1_LN0_N 105 AO DSI1_LN0_P 104 AO DSI1_LN1_N 107 AO DSI1_LN1_P 106 AO DSI1_LN2_N 109 AO DSI1_LN2_P 108 AO DSI1_LN3_N 111 AO DSI1_LN3_P 110 AO LCD0 MIPI clock signal
(negative) LCD0 MIPI clock signal
(positive) LCD0 MIPI lane 0 data signal
(negative) LCD0 MIPI lane 0 data signal
(positive) LCD0 MIPI lane 1 data signal
(negative) LCD0 MIPI lane 1 data signal
(positive) LCD0 MIPI lane 2 data signal
(negative) LCD0 MIPI lane 2 data signal
(positive) LCD0 MIPI lane 3 data signal
(negative) LCD0 MIPI lane 3 data signal
(positive) LCD1 MIPI clock signal
(negative) LCD1 MIPI clock signal
(positive) LCD1 MIPI lane 0 data signal
(negative) LCD1 MIPI lane 0 data signal
(positive) LCD1 MIPI lane 1 data signal
(negative) LCD1 MIPI lane 1 data signal
(positive) LCD1 MIPI lane 2 data signal
(negative) LCD1 MIPI lane 2 data signal
(positive) LCD1 MIPI lane 3 data signal
(negative) LCD1 MIPI lane 3 data signal
(positive) The following are the reference designs for LCM interfaces. SC650T_Hardware_Design 63 / 131 Smart LTE Module Series SC650T Hardware Design Figure 19: Reference Circuit Design for LCM0 Interface SC650T_Hardware_Design 64 / 131 LDO 6_1P8 LCD_BIAS_P LCD_BIAS_N C1 1uF C2 1uF C3 1uF 10V 10V LCD0_TE LCD0_ RST PMU_MPP2 DSI0_LN3_P DSI0_LN3_N DSI0_LN2_P DSI0_LN2_N DSI0_LN1_P DSI0_LN1_N DSI0_LN0_P DSI0_LN0_N DSI0_ CLK_P DSI0_ CLK_N LCM _LED+
LCM _LED-
Module 1 2 1 2 1 2 1 2 1 2 FL1 3 FL2 FL3 FL4 FL5 4 3 4 3 4 3 4 3 4 5 6 5 6 5 6 5 6 5 6 EMI filter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 LCD_BIAS_P NC LCD_BIAS_N NC LPTE RESET LCD_ID NC (SDA-TP) NC (SCL-TP) NC (RST-TP) NC (EINT-TP) GND VIO18 VCC28 NC (VTP-TP) GND MIPI_TDP3 MIPI_TDN3 GND MIPI_TDP2 MIPI_TDN2 GND MIPI_TDP1 MIPI_TDN1 GND MIPI_TDP0 MIPI_TDN0 GND MIPI_TCP MIPI_TCN GND LCM_LED+
GND LCM_LED-
LCM Smart LTE Module Series SC650T Hardware Design Figure 20: Reference Circuit Design for LCM1 Interface MIPI are high speed signal lines. It is recommended that common-mode filters should be added in series near the LCM connector, so as to improve protection against electromagnetic radiation interference. When compatible design with other displays is required, please connect the LCD_ID pin of LCM to the modules ADC pin, and please note that the output voltage of LCD_ID cannot exceed the voltage range of ADC pin. The SC650T does not have an integrated backlight driver, and LCM requires an external backlight driver.The reference circuit of external backlight drive is shown below, where the pin WLED_PWM supports PWM output and can be used for backlight brightness adjustment. Figure 21: Reference Design of LCM External Backlight Driving Circuit SC650T_Hardware_Design 65 / 131 LDO6_1P8 LCD_BIAS_P LCD_BIAS_N C1 1uF C2 1uF C3 1 uF 10V 10V LCD1_TE LCD1_RST DSI1_LN3_P DSI1_LN3_N DSI1_LN2_P DSI1_LN2_N DSI1_LN1_P DSI1_LN1_N DSI1_LN0_P DSI1_LN0_N DSI1_CLK_P DSI1_CLK_N LCM _LED+
LCM _LED-
Module 1 2 1 2 1 2 1 2 1 2 5 6 5 6 5 6 5 6 5 6 FL1 FL2 FL3 FL4 FL5 3 4 3 4 3 4 3 4 3 4 EMI filter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 LEDA NC LEDK NC LPTE RESET LCD_ID NC (SDA-TP) NC (SCL-TP) NC (RST-TP) NC (EINT-TP) GND VIO18 VCC28 NC (VTP-TP) GND MIPI_TDP3 MIPI_TDN3 GND MIPI_TDP2 MIPI_TDN2 GND MIPI_TDP1 MIPI_TDN1 GND MIPI_TDP0 MIPI_TDN0 GND MIPI_TCP MIPI_TCN GND LCM_LED+
GND LCM_LED-
LCM VBAT WLED_PWM 152 Module C1 2.2uF Backlight Driver LCM_LED+
LCM_LED-
Smart LTE Module Series SC650T Hardware Design 3.20. Touch Panel Interfaces SC650T provides two I2C interfaces for connection with Touch Panel (TP), and also provides the corresponding power supply and interrupt pins. The pin definition of touch panel interfaces is illustrated below. Table 21: Pin Definition of Touch Panel Interfaces Pin Name Pin No I/O Description Comment LDO10_2P8 11 PO 2.8V output power supply for TP VDD power Vnorm=2.8V IOmax=150mA LDO6_1P8 10 PO 1.8V output power supply Pull-up power supply of I2C Vnorm=1.8V IOmax=300mA TP0_INT 139 DI Interrupt signal of touch panel (TP0) TP0_RST 138 DO Reset signal of touch panel (TP0) Active low TP0_I2C_ SCL TP0_I2C_ SDA TP1_I2C_ SCL TP1_I2C_ SDA 140 OD I2C clock signal of touch panel
(TP0) 206 OD I2C data signal of touch panel (TP0) TP1_INT 137 DI Interrupt signal of touch panel (TP1) TP1_RST 136 DO Reset signal of touch panel (TP1) Active low 205 OD I2C clock signal of touch panel
(TP1) 204 OD I2C data signal of touch panel (TP1) A reference design for touch panel interfaces is shown below. SC650T_Hardware_Design 66 / 131 Smart LTE Module Series SC650T Hardware Design Figure 22: Reference Circuit Design for Touch Panel Interfaces NOTE TP is powered by LDO10_2P8 by default and LDO10_2P8 can output 150mA current. It is recommended to use an external LDO power supply if dual-TP or other applications need to be supported. 3.21. Camera Interfaces Based on standard MIPI CSI input interface, SC650T module supports 2 cameras (4-lane + 4-lane ), with maximum pixels up to 24MP. The video and photo quality are determined by various factors such as camera sensor, camera lens quality, etc. Table 22: Pin Definition of Camera Interfaces Pin Name Pin No. I/O Description Comment LDO2_1P1 13 PO LDO6_1P8 LDO17_2P85 LDO22_2P8 PO PO PO 10 12 14 15 1.1V output power supply for digital core circuit of rear camera 1.8V output power supply for digital I/O circuit of camera Vnorm=1.1V IOmax=1200mA Vnorm=1.8V IOmax=300mA 2.85V output power supply auto focus circuit Vnorm=2.85V IOmax=300mA 2.8V output power supply for AVDD of cameras Vnorm=2.8V IOmax=150mA LDO23_1P2 PO 1.2V output power supply Vnorm=1.2V SC650T_Hardware_Design 67 / 131 LDO 6_1P8 LDO10_2P8 R1 2.2K R2 2.2K TP_I2C_SDA TP_I2C_SCL TP_RST TP_INT Module 1 2 3 4 5 6 SDA 1.8V SCL 1.8V RESET 1.8V INT 1.8V GND VDD 2.8V TP D1 D2 D3 D4 C1 C2 D5 4.7uF 100nF Smart LTE Module Series SC650T Hardware Design IOmax=600mA CSI0_CLK_N CSI0_CLK_P CSI0_LN0_N CSI0_LN0_P CSI0_LN1_N CSI0_LN1_P CSI0_LN2_N CSI0_LN2_P CSI0_LN3_N CSI0_LN3_P CSI2_CLK_N CSI2_CLK_P CSI2_LN0_N CSI2_LN0_P CSI2_LN1_N CSI2_LN1_P CSI2_LN2_N CSI2_LN2_P CSI2_LN3_N CSI2_LN3_P 89 88 91 90 93 92 95 94 97 96 78 77 80 79 82 81 84 83 86 85 for digital core circuit of front camera MIPI clock signal of rear camera (negative) MIPI clock signal of rear camera (positive) MIPI lane 0 data signal of rear camera (negative) MIPI lane 0 data signal of rear camera (positive) MIPI lane 1 data signal of rear camera (negative) MIPI lane 1 data signal of rear camera (positive) MIPI lane 2 data signal of rear camera (negative) MIPI lane 2 data signal of rear camera (positive) MIPI lane 3 data signal of rear camera (negative) MIPI lane 3 data signal of rear camera (positive) MIPI clock signal of front camera (negative) MIPI clock signal of front camera (positive) MIPI lane 0 data signal of front camera (negative) MIPI lane 0 data signal of front camera (positive) MIPI lane 1 data signal of front camera (negative) MIPI lane 1 data signal of front camera (positive) MIPI lane 2 data signal of front camera (negative) MIPI lane 2 data signal of front camera (positive) MIPI lane 3 data signal of front camera (negative) MIPI lane 3 data signal of front camera (positive) AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI SC650T_Hardware_Design 68 / 131 Smart LTE Module Series SC650T Hardware Design MCAM_MCLK 99 DO SCAM_MCLK 100 DO MCAM_RST 74 MCAM_PWDN 73 SCAM_RST SCAM_PWDN CAM_I2C_SCL CAM_I2C_SDA 72 71 75 76 DCAM_MCLK 194 CAM4_MCLK 236 DO DCAM_RST 180 DO DCAM_PWDN 181 Master clock signal of rear camera Master clock signal of front camera Reset signal of rear camera Power down signal of rear camera Reset signal of front camera Power down signal of front camera I2C clock signal of camera I2C data signal of camera Clock signal of depth camera Master clock signal of fourth camera Reset signal of depth camera Power down signal of depth camera DO DO DO DO OD OD DO DO OD OD DCAM_I2C_SDA 197 I2C data of depth camera DCAM_I2C_SCL 196 I2C clock of depth camera SC650T_Hardware_Design 69 / 131 Smart LTE Module Series SC650T Hardware Design The following is a reference circuit design for two-camera applications. Figure 23: Reference Circuit Design for Two-Camera Applications NOTE SC650T_Hardware_Design 70 / 131 1 u F 1 u F
. 4 7 u F
. 4 7 u F AVDD DVDD DOVDD AF_VDD LDO17_2P85 LDO22_2P8 LDO2_1P1 LDO 6_1P8 2.2K 2.2K r o t c e n n o c a r e m a c r a e R r o t c e n n o c a r e m a c t n o r F 4.7uF 1uF 1uF AVDD DOVDD DVDD LDO23_1P2 EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI MCAM_ RST MCAM_PWDN MCAM_MCLK CAM_I2C_ SDA CAM_I2C_ SCL CSI0_LN3_P CSI0_LN3_N CSI0_LN2_P CSI0_LN2_N CSI0_LN1_P CSI0_LN1_N CSI0_LN0_P CSI0_LN0_N CSI0_ CLK_P CSI0_ CLK_N SCAM_RST SCAM_PWDN SCAM_MCLK CSI2_LN3_P CSI2_LN3_N CSI2_LN2_P CSI2_LN2_N CSI2_LN1_P CSI2_LN1_N CSI2_LN0_P CSI2_LN0_N CSI2_ CLK_P CSI2_ CLK_N Smart LTE Module Series SC650T Hardware Design CSI0 is used for rear camera, and CSI2 is used for front camera. 3.21.1. 3.21.1. Design Considerations Special attention should be paid to the pin definition of LCM/camera connectors. Assure the SC650T and the connectors are correctly connected. MIPI are high speed signal lines, supporting maximum data rate up to 2.1Gbps. The differential impedance should be controlled as 100. Additionally, it is recommended to route the trace on the inner layer of PCB, and do not cross it with other traces. For the same group of DSI or CSI signals, all the MIPI traces should keep the same length. In order to avoid crosstalk, it is recommended to maintain the intra-lane spacing as trace width and the inter-lane spacing as two times of the trace width. Any cut or hole on GND reference plane under MIPI signals should be avoided. It is recommended to select a low capacitance TVS for ESD protection and the recommended parasitic capacitance is below 1pF. Pin No. Pin Name Length (mm) Length Difference (P-N) Route MIPI traces according to the following rules:
a) The total trace length should not exceed 305mm;
b) Control the differential impedance as 8510%;
c) Control intra-lane length difference within 0.67mm;
d) Control inter-lane length difference within 1.3mm. Table 23: MIPI Trace Length Inside the Module 116 115 118 117 120 119 122 121 124 123 DSI0_CLK_N DSI0_CLK_P DSI0_LN0_N DSI0_LN0_P DSI0_LN1_N DSI0_LN1_P DSI0_LN2_N DSI0_LN2_P DSI0_LN3_N DSI0_LN3_P 21.32 21.44 24.43 24.53 24.42 24.78 24.56 24.60 28.38 28.44 0.12 0.10 0.36 0.04 0.06 SC650T_Hardware_Design 71 / 131 Smart LTE Module Series SC650T Hardware Design 103 102 105 104 107 106 109 108 111 110 89 88 91 90 93 92 95 94 97 96 78 77 80 79 82 81 DSI1_CLK_N DSI1_CLK_P DSI1_LN0_N DSI1_LN0_P DSI1_LN1_N DSI1_LN1_P DSI1_LN2_N DSI1_LN2_P DSI1_LN3_N DSI1_LN3_P CSI0_CLK_N CSI0_CLK_P CSI0_LN0_N CSI0_LN0_P CSI0_LN1_N CSI0_LN1_P CSI0_LN2_N CSI0_LN2_P CSI0_LN3_N CSI0_LN3_P CSI2_CLK_N CSI2_CLK_P CSI2_LN0_N CSI2_LN0_P CSI2_LN1_N CSI2_LN1_P 11.69 11.71 11.46 11.56 15.26 15.27 15.12 14.47 16.15 16.14 17.80 17.86 17.73 17.73 12.98 12.95 11.28 10.96 10.02 9.98 22.70 22.95 22.14 22.40 22.96 22.54 0.02 0.09 0.01
-0.65
-0.01 0.06
-0.01
-0.03
-0.31
-0.04 0.25 0.26
-0.42 SC650T_Hardware_Design 72 / 131 84 83 86 85 Smart LTE Module Series SC650T Hardware Design CSI2_LN2_N CSI2_LN2_P CSI2_LN3_N CSI2_LN3_P 22.96 22.95 22.77 22.41
-0.01
-0.36 3.21.2. Flashlight Interfaces SC650T module supports 2 flash LED drivers, with maximal output current up to 1.5A in flash mode and 300mA in torch mode. The default output current is 1A in flash mode and 300mA in torch mode. Table 24: Pin Definition of Flashlight Interfaces Pin Name Pin No. I/O Description Comment FLASH_LED1 26 AO Flash/torch drive signal output FLASH_LED2 162 AO Flash/torch drive signal output A reference circuit design is shown below. Figure 24: Reference Circuit Design for Flashlight Interfaces SC650T_Hardware_Design 73 / 131 D1 D2 FLASH_LED1 FLASH_LED2 Module Smart LTE Module Series SC650T Hardware Design 3.22. Sensor Interfaces SC650T module supports communication with sensors via I2C interface, and it supports various sensors such as acceleration sensor, gyroscopic sensor, compass, optical sensor, temperature sensor. Table 25: Pin Definition of Sensor Interfaces Pin Name Pin No. I/O Description Comment SENSOR_I2C_SCL 131 OD I2C clock signal of external sensor SENSOR_I2C_SDA 132 OD I2C data signal of external sensor GPIO_43 GPIO_44 GPIO_42 GPIO_45 253 254 252 255 DI DI DI DI Interrupt signal of optical sensor Interrupt signal of direction sensor
(compass) Interrupt signal of acceleration sensor Interrupt signal of gyroscopic sensor 3.23. Audio Interfaces SC650T module provides two analog input channels, two analog output channels and two digital input channels. The following table shows the pin definition. Table 26: Pin Definition of Audio Interfaces Pin Name Pin No. I/O Description Comment DMIC1_DATA DMIC1_CLK 45 46 Digital microphone1 data Digital microphone1 clock DMIC2_DATA 168 Digital microphone2 data DMIC2_CLK 169 Digital microphone2 clock DI DO DI DO AO MIC_BIAS1 44 Microphone bias voltage MIC_BIAS2 233 AO Microphone bias voltage Dias voltage for DMIC1 Dias voltage for AMIC2 SC650T_Hardware_Design 74 / 131 Smart LTE Module Series SC650T Hardware Design MIC_BIAS3 167 Microphone bias voltage Dias voltage for DMIC2 LINE_OUT_3 228 Audio output LINE_OUT_REF 227 Audio output reference ground LINE_OUT_4 226 Audio output AO AO AI AO AI AI AI AI AO AO AO AO AO AI AO AI AMIC1_P 218 AMIC1_M 217 AMIC2_P 216 AMIC2_M 215 53 52 55 54 51 50 49 48 EAR_P EAR_N PDM_CLK PDM_DATA HPH_R HPH_REF HPH_L HS_DET pair . WSA_EN 230 DO Analog microphone positive input for channel 1 Analog microphone negative input for channel 1 Analog microphone positive input for headset Analog microphone negative input for headset Earpiece positive output Earpiece positive output External audio power amplifier enable signal Headphone right channel output Headphone reference ground Headphone left channel output External audio power amplifier clock interface External connect to WSA8810/WSA8815 External audio power amplifier data interface External connect to WSA8810/WSA8815 The module offers four audio input channels, including two digital input pair and two analog input Headset insertion detection Pulled up internally. Three MIC_BIAS output. These output voltage range of MIC_BIAS is programmable between 1.6V and 2.85V, and the maximum output current is 3mA. The earpiece interface uses differential output. The headphone interface features stereo left and right channel output, and headphone insertion detection function is supported. SC650T_Hardware_Design 75 / 131 Smart LTE Module Series SC650T Hardware Design 3.23.1. Reference Circuit Design for Microphone Interfaces Figure 25: Reference Circuit Design for Analog ECM-type Microphone Figure 26: Reference Circuit Design for MEMS-type Microphone SC650T_Hardware_Design 76 / 131 MIC_BIASn AMICx_P AMICx_M Module R4 1.1K R1 0R R2 0R C1 0.1uF R3 1.1K ECM-MIC MIC_BIASn AMICx_M AMICx_P Module R1 0R R2 0R C4 100nF R3 0R 2 3 1 VDD GND GND OUT 4 MEMS-MIC Smart LTE Module Series SC650T Hardware Design Figure 27:Reference Circuit Design for Digital Microphone 3.23.2. Reference Circuit Design for Earpiece Interface Figure 28: Reference Circuit Design for Earpiece Interface SC650T_Hardware_Design 77 / 131 R2 NC R1 NC GND L/R VDD NC Digital MIC DMIC_CLK DMIC_CLK DMIC_DATA MIC_ BIAS DMIC_DATA Module C2 100nF C3 10uF C4 C2 NM_8.2pF NM_33pF R1 0R R2 0R C1 C3 NM_8.2pF NM_33pF D1 D2 EAR_P EAR_N Module Smart LTE Module Series SC650T Hardware Design 3.23.3. Reference Circuit Design for Headphone Interface Figure 29: Reference Circuit Design for Headphone Interface 3.23.4. Reference Circuit Design for Loudspeaker Interface Figure 30: Reference Circuit Design for Loudspeaker Interface 3.23.5. Audio Interfaces Design Considerations It is recommended to use the electret microphone with dual built-in capacitors (e.g. 10pF and 33pF) for filtering out RF interference, thus reducing TDD noise. The 33pF capacitor is applied for filtering out RF interference when the module is transmitting at EGSM900. Without placing this capacitor, TDD noise could be heard. The 10pF capacitor here is used for filtering out RF interference at DCS1800. Please note SC650T_Hardware_Design 78 / 131 MIC_BIAS2 AMIC2_M AMIC2_P HPH_L HS_DET HPH_R HPH_REF Module C2 33pF C2 33pF R 6 2
. 2 K
1 R 1 0 R C2 100pF F1 R4 NC R2 0R R5 NC F2 F3 F4 1 5 4 6 3 2 C3 C4 R7 680pF 680pF 0R D1 D2 D3 D4 D5 ESD LDO5_1P8 VPH_PWR EARP EA RN WSA_EN PDM_CLK PDM_DATA GND LDO5_1P8 VPH_PWR EARP EA RN SPK_P SPK_N F1 F2 WSA_EN PDM_CLK PDM_DATA GND Module WSA8810&WSA8815 C1 C2 8.2pF 8.2pF D1 D2 12V 12V Smart LTE Module Series SC650T Hardware Design that the resonant frequency point of a capacitor largely depends on the material and production technique. Therefore, customers would have to discuss with their capacitor vendors to choose the most suitable capacitor for filtering out high-frequency noises. The severity degree of the RF interference in the voice channel during GSM transmitting largely depends on the application design. In some cases, EGSM900 TDD noise is more severe; while in other cases, DCS1800 TDD noise is more obvious. Therefore, a suitable capacitor can be selected based on the test results. Sometimes, even no RF filtering capacitor is required. In order to decrease radio or other signal interference, RF antennas should be placed away from audio interfaces and audio traces. Power traces cannot be parallel with and also should be far away from the audio traces. The differential audio traces must be routed according to the differential signal layout rule. 3.24. Emergency Download Interface USB_BOOT is an emergency download interface. Pull up to LDO5_1P8 during power-up will force the module enter into emergency download mode. This is an emergency option when there are failures such as abnormal startup or operation. For convenient firmware upgrade and debugging in the future, please reverse the reference circuit design shown as below. Figure 31: Reference Circuit Design for Emergency Download Interface 3.25. LED Driver Interfaces The following is the pin definition of LED driver interfaces. SC650T_Hardware_Design 79 / 131 S1 USB_BOOT Module LDO5_1P8 R1 10K Smart LTE Module Series SC650T Hardware Design Table 27: Pin Definition of LED Driver Interfaces Pin Name Pin No. I/O Description Comment LED_RED LED_GRN LED_BLU 23 24 25 PO PO PO Red LED light Green LED light Blue LED light A reference circuit design for LED interfaces is shown below. The output current does not exceed 12mA The output current does not exceed 12mA The output current does not exceed 12mA Figure 32: Reference Circuit Design for LED Interfaces SC650T_Hardware_Design 80 / 131 GRN RED BLU R1 0R R2 0R R3 0R VPH_PWR VPH_PWR VPH_PWR C1 C2 C3 1nF 1nF 1nF Smart LTE Module Series SC650T Hardware Design 4 Wi-Fi and BT SC650T module provides a shared antenna interface ANT_WIFI/BT for Wi-Fi and Bluetooth (BT) functions. The interface impedance is 50. External antennas such as PCB antenna, sucker antenna and ceramic antenna can be connected to the module via the interface, so as to achieve Wi-Fi and BT functions. 4.1. Wi-Fi Overview SC650T module supports 2.4GHz and 5GHz dual-band WLAN wireless communication based on IEEE 802.11a/b/g/n/ac standard protocols. The maximum data rate is up to 433Mbps. The features are as below:
Support Wake-on-WLAN (WoWLAN) Support ad hoc mode Support WAPI SMS4 hardware encryption Support AP mode Support Wi-Fi Direct Support MCS 0-7 for HT20 and HT40 Support MCS 0-8 for VHT20 Support MCS 0-9 for VHT40 and VHT80 4.1.1. Wi-Fi Performance The following table lists the Wi-Fi transmitting and receiving performance of SC650T module. Table 28: Wi-Fi Transmitting Performance Standard 802.11b Rate 1Mbps Output Power 16dBm2.5dB 2.4GHz 802.11b 11Mbps 16dBm2.5dB 802.11g 6Mbps 16dBm2.5dB SC650T_Hardware_Design 81 / 131 Smart LTE Module Series SC650T Hardware Design 802.11g 54Mbps 14dBm2.5dB 802.11n HT20 802.11n HT20 802.11n HT40 802.11n HT40 802.11a 802.11a 802.11n HT20 802.11n HT20 802.11n HT40 802.11n HT40 MCS0 MCS7 MCS0 MCS7 6Mbps 54Mbps MCS0 MCS7 MCS0 MCS7 802.11ac VHT20 MCS0 802.11ac VHT20 MCS8 802.11ac VHT40 MCS0 802.11ac VHT40 MCS9 802.11ac VHT80 MCS0 802.11ac VHT80 MCS9 Table 29: Wi-Fi Receiving Performance Standard 802.11b 802.11b 802.11g 2.4GHz 802.11g Rate 1Mbps 11Mbps 6Mbps 54Mbps 802.11n HT20 MCS0 5GHz 15dBm2.5dB 13dBm2.5dB 15dBm2.5dB 13dBm2.5dB 17dBm2.5dB 16dBm2.5dB 17dBm2.5dB 16dBm2.5dB 17dBm2.5dB 16dBm2.5dB 16dBm2.5dB 15dBm2.5dB 15dBm2.5dB 14dBm2.5dB 15dBm2.5dB 14dBm2.5dB Sensitivity
-97dBm
-89dBm
-91dBm
-74dBm
-91dBm SC650T_Hardware_Design 82 / 131 Smart LTE Module Series SC650T Hardware Design 802.11n HT20 802.11n HT40 802.11n HT40 802.11a 802.11a MCS7 MCS0 MCS7 6Mbps 54Mbps 802.11n HT20 MCS0 802.11n HT20 MCS7 802.11n HT40 MCS7 802.11ac VHT20 MCS8 802.11ac VHT40 MCS9 802.11ac VHT80 MCS9 5GHz 802.11n HT40 MCS0
-72dBm
-89dBm
-70dBm
-92dBm
-74dBm
-91dBm
-73dBm
-88dBm
-70dBm
-68dBm
-63dBm
-59dBm Reference specifications are listed below:
IEEE 802.11n WLAN MAC and PHY, October 2009 + IEEE 802.11-2007 WLAN MAC and PHY, June 2007 IEEE Std 802.11b, IEEE Std 802.11d, IEEE Std 802.11e, IEEE Std 802.11g, IEEE Std 802.11i: IEEE 802.11-2007 WLAN MAC and PHY, June 2007 4.2. BT Overview SC650T module supports BT4.2 (BR/EDR+BLE) specifications, as well as GFSK, 8-DPSK, /4-DQPSK modulation modes. Maximally support up to 7 wireless connections Maximally support up to 3.5 piconets at the same time Support one SCO or eSCO (Extended Synchronous Connection Oriented) connection The BR/EDR channel bandwidth is 1MHz, and can accommodate 79 channels. The BLE channel bandwidth is 2MHz, and can accommodate 40 channels. SC650T_Hardware_Design 83 / 131 Smart LTE Module Series SC650T Hardware Design Table 30: BT Data Rate and Versions Version Data rate Maximum Application Throughput Comment 1.2 1Mbit/s
> 80Kbit/s 2.0+EDR 3Mbit/s
> 80Kbit/s 3.0+HS 24Mbit/s Reference to 3.0+HS 4.0 24Mbit/s Reference to 4.0 LE Reference specifications are listed below:
Bluetooth Radio Frequency TSS and TP Specification 1.2/2.0/2.0 + EDR/2.1/2.1+ EDR/3.0/3.0 + HS, August 6, 2009 Bluetooth Low Energy RF PHY Test Specification, RF-PHY.TS/4.0.0, December 15, 2009 4.2.1. BT Performance The following table lists the BT transmitting and receiving performance of SC650T module. Table 31: BT Transmitting and Receiving Performance Transmitter Performance Packet Types DH5 2-DH5 3-DH5 Transmitting Power 8dBm2.5dB 8dBm2.5dB 8dBm2.5dB Receiver Performance Packet Types DH5 Receiving Sensitivity
-93dBm 2-DH5
-92dBm 3-DH5
-92dBm SC650T_Hardware_Design 84 / 131 Smart LTE Module Series SC650T Hardware Design 5 GNSS SC650T module integrates a Qualcomm IZat GNSS engine (Gen 8C) which supports multiple positioning and navigation systems including GPS, GLONASS and BeiDou. With an embedded LNA, the module provides greatly improved positioning accuracy. 5.1. GNSS Performance The following table lists the GNSS performance of SC650T module in conduction mode. Table 32: GNSS Performance Parameter Description Sensitivity (GNSS) Reacquisition Cold start Tracking Cold start Hot start TTFF (GNSS) Warm start Static Drift (GNSS) CEP-50 Typ.
-146
-157
-158 51 30 6 8 Unit dBm dBm dBm s s s m SC650T_Hardware_Design 85 / 131 Smart LTE Module Series SC650T Hardware Design 5.2. GNSS RF Design Guidelines Bad design of antenna and layout may cause reduced GNSS receiving sensitivity, longer GNSS positioning time, or reduced positioning accuracy. In order to avoid these, please follow the design rules listed below:
Maximize the distance between the GNSS RF part and the GPRS RF part (including trace routing and antenna layout) to avoid mutual interference. In user systems, GNSS RF signal lines and RF components should be placed far away from high speed circuits, switched-mode power supplies, power inductors, the clock circuit of single-chip microcomputers, etc. For applications with harsh electromagnetic environment or high ESD-protection requirements, it is recommended to add ESD protective diodes for the antenna interface. Only diodes with ultra-low junction capacitance such as 0.5pF can be selected. Otherwise, there will be effects on the impedance characteristic of RF circuit loop, or attenuation of bypass RF signal may be caused. Control the impedance of either feeder line or PCB trace as 50, and keep the trace length as short as possible. Refer to Chapter 6.3 for GNSS antenna reference circuit designs. SC650T_Hardware_Design 86 / 131 Smart LTE Module Series SC650T Hardware Design 6 Antenna Interfaces SC650T provides four antenna interfaces for main antenna, Rx-diversity/MIMO antenna, GNSS antenna, and Wi-Fi/BT antenna, respectively. The antenna ports have an impedance of 50. 6.1. Main/Rx-diversity Antenna Interfaces The pin definition of main/Rx-diversity antenna interfaces is shown below. Table 33: Pin Definition of Main/Rx-diversity Antenna Interfaces I/O IO AI Pin Name Pin No. Description Comment ANT_MAIN 19 Main antenna interface 50 impedance ANT_DRX 149 Diversity and MIMO antenna interface 50 impedance The operating frequencies of SC650T module are listed in the following table. Table 34: SC650T-NA Module Operating Frequencies 3GPP Band Receive Transmit LTE-FDD B2 1930~1990 1850~1910 LTE-FDD B4 2110~2155 1710~1755 LTE-FDD B5 869~894 824~849 LTE-FDD B7 2620~2690 2500~2570 LTE-FDD B12 LTE-FDD B13 LTE-FDD B14 729~746 746~756 758~768 699~716 777~787 788~798 Unit MHz MHz MHz MHz MHz MHz MHz SC650T_Hardware_Design 87 / 131 Smart LTE Module Series SC650T Hardware Design LTE-FDD B25 1930~1995 1850~1915 LTE-FDD B26 859~894 814~849 LTE-FDD B66 2110~2200 1710~1780 Table 35: SC650T-EM Module Operating Frequencies 3GPP Band Receive Transmit LTE-FDD B1 2110~2170 1920~1980 LTE-FDD B3 1805~1880 1710~1785 LTE-FDD B7 2620~2690 2500~2570 LTE-FDD B20 LTE-FDD B28 6.1.1. 6.1.1. 791~821 758~803 832~862 703~748 MHz MHz MHz Unit MHz MHz MHz MHz MHz 6.1.1. Main and Rx-diversity Antenna Interfaces Reference Design A reference circuit design for main and Rx-diversity antenna interfaces is shown as below. A -type matching circuit should be reserved for better RF performance, and the -type matching components
(R1/C1/C2, R2/C3/C4) should be placed as close to the antennas as possible. The capacitors are not mounted by default and resistors are 0. SC650T_Hardware_Design 88 / 131 Main antenna Diversity antenna ANT_MAIN R1 0R C1 NM C3 NM C2 NM C4 NM ANT_DRX R2 0R Module Smart LTE Module Series SC650T Hardware Design Figure 33: Reference Circuit Design for Main and Rx-diversity Antenna Interfaces 6.1.2. Reference Design of RF Layout For users PCB, the characteristic impedance of all RF traces should be controlled as 50. The impedance of the RF traces is usually determined by the trace width (W), the materials dielectric constant, the distance between signal layer and reference ground (H), and the clearance between RF trace and ground (S). Microstrip line or coplanar waveguide line is typically used in RF layout for characteristic impedance control. The following are reference designs of microstrip line or coplanar waveguide line with different PCB structures. Figure 34: Microstrip Line Design on a 2-layer PCB Figure 35: Coplanar Waveguide Line Design on a 2-layer PCB SC650T_Hardware_Design 89 / 131 Smart LTE Module Series SC650T Hardware Design Figure 36: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 37: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:
Use impedance simulation tool to control the characteristic impedance of RF traces as 50. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground. The distance between the RF pins and the RF connector should be as short as possible, and all the right-angle traces should be changed to curved ones. There should be clearance area under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between the ground vias and RF traces should be no less than two times the width of RF signal traces (2*W). For more details about RF layout, please refer to document [3]. SC650T_Hardware_Design 90 / 131 Smart LTE Module Series SC650T Hardware Design 6.2. Wi-Fi/BT Antenna Interface Table 36: Pin Definition of Wi-Fi/BT Antenna Interface Pin Name Pin No. I/O Description Comment ANT_WIFI/BT 129 IO Wi-Fi/BT antenna interface 50 impedance Table 37: Wi-Fi/BT Frequency Type 802.11a/b/g/n/ac BT4.2 LE Frequency 2402~2482 5180~5825 2402~2480 Unit MHz MHz A reference circuit design for Wi-Fi/BT antenna interface is shown as below. A -type matching circuit is recommended to be reserved for better RF performance. The capacitors are not mounted by default and resistors are 0. Figure 38: Reference Circuit Design for Wi-Fi/BT Antenna Interface 6.3. GNSS Antenna Interface SC650T_Hardware_Design 91 / 131 ANT_WIFI/BT R1 0R C1 NM C2 NM Module Smart LTE Module Series SC650T Hardware Design Table 38: Pin Definition of GNSS Antenna Pin Name Pin No. I/O Description Comment ANT_GNSS 134 AI GNSS antenna Interface 50 impedance GNSS_LNA_EN 202 DO LNA enable control For test purpose only. If unused, keep it open. Table 39: GNSS Frequency Type GPS Frequency 1575.421.023 GLONASS 1597.5~1605.8 BeiDou 1561.0982.046 6.3.1. Recommended Circuit for Passive Antenna GNSS antenna interface supports passive ceramic antennas and other types of passive antennas. A reference circuit design is given below. Unit MHz MHz MHz Figure 39: Reference Circuit Design for GNSS Passive Antenna NOTE When the passive antenna is placed far away from the module (that is, the antenna trace is long), it is recommended to add an external LNA circuit for better GNSS receiving performance, and the LNA should be placed close to the antenna. 6.3.2. Recommended Circuit for Active Antenna The active antenna is powered by a 56nH inductor through the antenna's signal path. The common power supply voltage ranges from 3.3V to 5.0V. Although featuring low power consumption, the active antenna SC650T_Hardware_Design 92 / 131 Passive Antenna C1 R1 C4 0R NM C2 NM ANT_GNSS Module Smart LTE Module Series SC650T Hardware Design still requires stable and clean power supplies. It is recommended to use high performance LDO as the power supply. A reference design of GNSS active antenna is shown below. Figure 40: Reference Circuit Design for GNSS Active Antenna 6.4. Antenna Installation 6.4.1. Antenna Requirements The following table shows the requirements on main antenna, Rx-diversity, Wi-Fi/BT antenna and GNSS antenna. Table 40: Antenna Requirements Antenna Type Requirements LTE Wi-Fi/BT VSWR: 2 Gain (dBi): 1 Max Input Power (W): 50 Input Impedance (): 50 Polarization Type: Vertical Cable Insertion Loss: < 1dB
(LTE B5/B12/B13/B14/B20/B26/B28) Cable Insertion Loss: < 1.5dB
(LTE B1/B2/B3/B4/B25/B66) Cable Insertion Loss: < 2dB (LTE B7) VSWR: 2 Gain (dBi): 1 Max Input Power (W): 50 Input Impedance (): 50 Polarization Type: Vertical Cable Insertion Loss: < 1dB SC650T_Hardware_Design 93 / 131 3V3 Active Antenna R1 C1 1uF C2 100pF 10R L1 56nH ANT_GNSS Module R2 0R C4 NM C3 100pF C5 NM Smart LTE Module Series SC650T Hardware Design Frequency range: 1559MHz~1609MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive Antenna Gain: > 0dBi Active Antenna Noise Figure: < 1.5dB (Typ.) Active Antenna Gain: > -2dBi Active Antenna Embedded LNA Gain: < 17dB (Typ.) Active Antenna Total Gain: < 17dBi (Typ.) 1) It is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use of active antenna may generate harmonics which will affect the GNSS performance. 6.4.2. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector provided by HIROSE. GNSS 1) NOTE Figure 41: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. SC650T_Hardware_Design 94 / 131 Smart LTE Module Series SC650T Hardware Design Figure 42: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector. Figure 43: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com. SC650T_Hardware_Design 95 / 131 Smart LTE Module Series SC650T Hardware Design 7 Electrical, Reliability and Radio Characteristics 7.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 41: Absolute Maximum Ratings Parameter VBAT USB_VBUS Current on VBAT Voltage on Digital Pins Min
-0.5
-0.5 0
-0.3 Max Unit 6 20 3 2.3 V V A V 7.2. Power Supply Ratings Table 42: SC650T Module Power Supply Ratings Parameter Description Conditions Min Typ. Max Unit VBAT VBAT 3.55 3.8 4.4 V The actual input voltages must stay between the minimum and maximum values. USB_VBUS VRTC Power supply voltage of backup 4.0 5.0 10 2.0 3.0 3.25 V V SC650T_Hardware_Design 96 / 131 Smart LTE Module Series SC650T Hardware Design Parameter Description Conditions Min Typ. Max Unit battery. 7.3. Operation and Storage Temperatures The operation and storage temperatures are listed in the following table. Table 43: Operation and Storage Temperatures Parameter Min Operating temperature range 1)
-35 Extended temperature range 2)
-40 Storage temperature range
-40 Typ.
+25 Max
+65
+75
+90 Unit C C C NOTES 1. 2. 1) Within operation temperature range, the module is 3GPP compliant. 2) Within extended temperature range, the module remains the ability to establish and maintain a voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances. When the temperature returns to the normal operating temperature levels, the module will meet 3GPP specifications again. 7.4. Current Consumption SC650T_Hardware_Design 97 / 131 Smart LTE Module Series SC650T Hardware Design Table 44: SC650T-NA Current Consumption Parameter Description Conditions Min Typ. Max Unit OFF state Power down LTE-FDD supply current Sleep (USB disconnected)
@DRX=6 Sleep (USB disconnected)
@DRX=8 Sleep (USB disconnected)
@DRX=9 LTE-FDD B2 @max power LTE-FDD B4 @max power LTE-FDD B5 @max power LTE-FDD B7 @max power LTE-FDD B12 @max power LTE-FDD B13 @max power LTE-FDD B14 @max power LTE-FDD B25 @max power LTE-FDD B26 @max power LTE-FDD B66 @max power IVBAT LTE data transfer Table 45: SC650T-EM Current Consumption Parameter Description Conditions Min Typ. Max Unit OFF state Power down IVBAT LTE-FDD supply current Sleep (USB disconnected)
@DRX=6 Sleep (USB disconnected)
@DRX=8 Sleep (USB disconnected)
@DRX=9 LTE data transfer LTE-FDD B1 @max power SC650T_Hardware_Design 98 / 131 73 5.3 3.5 3.2 591 566 540 654 541 561 532 588 571 631 80 5 3.2 2.9 650 uA mA mA mA mA mA mA mA mA mA mA mA mA mA uA mA mA mA mA Smart LTE Module Series SC650T Hardware Design LTE-FDD B3 @max power LTE-FDD B7 @max power LTE-FDD B20 @max power LTE-TDD B28 @max power 721 702 571 607 mA mA mA mA 7.5. RF Output Power The following table shows the RF output power of SC650T module. Table 46: SC650T-NA RF Output Power Max 23dBm2dB 23dBm2dB 23dBm2dB 23dBm2dB 23dBm2dB 23dBm2dB 23dBm2dB 23dBm2dB 23dBm2dB 23dBm2dB Max 23dBm2dB 23dBm2dB Min
<-39dBm
<-39dBm
<-39dBm
<-39dBm
<-39dBm
<-39dBm
<-39dBm
<-39dBm
<-39dBm
<-39dBm Min
<-39dBm
<-39dBm Table 47: SC650T-EM RF Output Power SC650T_Hardware_Design 99 / 131 7.5. Frequency LTE-FDD B2 LTE-FDD B4 LTE-FDD B5 LTE-FDD B7 LTE-FDD B12 LTE-FDD B13 LTE-FDD B14 LTE-FDD B25 LTE-FDD B26 LTE-FDD B66 Frequency LTE-FDD B1 LTE-FDD B3 Smart LTE Module Series SC650T Hardware Design LTE-FDD B7 LTE-FDD B20 LTE-FDD B28 23dBm2dB 23dBm2dB 23dBm2dB
<-39dBm
<-39dBm
<-39dBm 7.6. RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of SC650T module. Table 48: SC650T-NA RF Receiving Sensitivity x`
Frequency Receive Sensitivity (Typ.) Primary Diversity SIMO 3GPP (SIMO) LTE-FDD B2 (10M)
-99.5dBm
-100.4dBm
-102.9dBm
-94.3dBm LTE-FDD B4 (10M)
-98.7dBm
-99.6dBm
-102.3dBm
-96.3dBm LTE-FDD B5 (10M)
-100.3dBm
-99.7dBm
-103.6dBm
-94.3dBm LTE-FDD B7 (10M)
-96dBm
-99.2dBm
-100dBm
-94.3dBm LTE-FDD B12 (10M)
-100dBm
-100.1dBm
-103.2dBm
-93.3dBm LTE-FDD B13 (10M)
-98.5dBm
-100.3dBm
-102.6dBm
-93.3dBm LTE-FDD B14 (10M)
-98.9dBm
-101dBm
-102.9dBm
-93.3dBm LTE-FDD B25 (10M)
-99.4dBm
-100.4dBm
-102.8dBm
-92.8dBm LTE-FDD B26 (10M)
-100.5dBm
-99.5dBm
-103.9dBm
-93.8dBm LTE-FDD B66 (10M)
-98.3dBm
-99.4dBm
-102dBm
-95.8dBm Table 49: SC650T-EM RF Receiving Sensitivity Frequency Receive Sensitivity (Typ.) Primary Diversity SIMO 3GPP (SIMO) SC650T_Hardware_Design 100 / 131 Smart LTE Module Series SC650T Hardware Design LTE-FDD B1 (10M)
-99.1dBm
-99dBm
-102.3dBm
-96.3dBm LTE-FDD B3 (10M)
-98.9dBm
-99.5dBm
-102.1dBm
-93.3dBm LTE-FDD B7 (10M)
-98.5dBm
-98.8dBm
-101.9dBm
-94.3dBm LTE-FDD B20 (10M)
-99.7dBm
-99.6dBm
-102.4dBm
-93.3dBm LTE-TDD B28 (10M)
-99.8dBm
-99.4dBm
-102.2dBm
-94.8dBm 7.7. 7.7. Electrostatic Discharge The module is not protected against electrostatic discharge (ESD) in general. Consequently, it should be subject to ESD handling precautions that are typically applied to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. The following table shows the electrostatic discharge characteristics of SC650T module. Table 50: ESD Characteristics (Temperature: 25C, Humidity: 45%) Test Points Contact Discharge Air Discharge Unit VBAT, GND
+/-5 All Antenna Interfaces
+/-5 Other Interfaces
+/-0.5
+/-10
+/-10
+/-1 KV KV KV SC650T_Hardware_Design 101 / 131 Smart LTE Module Series SC650T Hardware Design 8 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the tolerances for dimensions without tolerance values are 0.05mm. 8.1. Mechanical Dimensions of the Module Figure 44: Module Top and Side Dimensions SC650T_Hardware_Design 102 / 131 Pin1 Top view Side view Smart LTE Module Series SC650T Hardware Design Figure 45: Module Bottom Dimensions (Top View) SC650T_Hardware_Design 103 / 131 Smart LTE Module Series SC650T Hardware Design 8.2. Recommended Footprint Figure 46: Recommended Footprint (Top View) NOTES on host PCB. 1. For easy maintenance of the module, keep about 3mm between the module and other components 2. All RESERVED pins should be kept open and MUST NOT be connected to ground. SC650T_Hardware_Design 104 / 131 Smart LTE Module Series SC650T Hardware Design 8.3. Top and Bottom View of the Module Figure 47: Top View of the Module Figure 48: Bottom View of the Module NOTE These are renderings of SC650T module. For authentic dimension and appearance, please refer to the module that you receive from Quectel. SC650T_Hardware_Design 105 / 131 Smart LTE Module Series SC650T Hardware Design 9 Storage, Manufacturing and Packaging 9.1. Storage SC650T is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are shown as below. 1. Shelf life in the vacuum-sealed bag: 12 months at <40C/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be:
Mounted within 168 hours at the factory environment of 30C/60%RH. Stored at <10%RH. 3. Devices require baking before mounting, if any circumstance below occurs. When the ambient temperature is 23C5C and the humidity indication card shows the humidity is >10% before opening the vacuum-sealed bag. Device mounting cannot be finished within 168 hours at factory conditions of 30C/60%. If baking is required, devices may be baked for 8 hours at 120C5C. As the plastic package cannot be subjected to high temperature, it should be removed from devic es before high temperature (120C) baking. If shorter baking time is desired, please refer to IPC/J EDECJ-STD-033 for baking procedure. 4. NOTE SC650T_Hardware_Design 106 / 131 Smart LTE Module Series SC650T Hardware Design 9.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.18mm~0.20mm. It is recommended to slightly reduce the amount of solder paste for LGA pads, thus avoiding short-circuit. For more details, please refer to document [4]. It is suggested that the peak reflow temperature is 240~245C, and the absolute maximum reflow temperature is 245C. To avoid damage to the module caused by repeated heating, it is strongly recommended that the module should be mounted after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. Figure 49: Recommended Reflow Soldering Thermal Profile Table 51: Recommended Thermal Profile Parameters Factor Soak Zone Max slope Recommendation 1 to 3C/sec Soak time (between A and B: 150C and 200C) 60 to 120 sec SC650T_Hardware_Design 107 / 131 Temp. (C) 245 240 220 200 150 100 Soak Zone A Max slope: 1~3C/sec Reflow Zone Max slope:
2~3C/sec C Cooling down slope: 1~4C/sec B D Smart LTE Module Series SC650T Hardware Design Reflow Zone Max slope Reflow time (D: over 220C) Max temperature Cooling down slope Reflow Cycle Max reflow cycle 9.3. Packaging 2 to 3C/sec 40 to 60 sec 240C ~ 245C 1 to 4C/sec 1 SC650T is packaged in tape and reel carriers. Each reel is 330mm in diameter and contains 200 modules. The following figures show the package details, measured in mm. Figure 50: Tape Dimensions SC650T_Hardware_Design 108 / 131 Smart LTE Module Series SC650T Hardware Design Figure 51: Reel Dimensions Table 52: Reel Packaging Model Name MOQ for MP Minimum Package: 200pcs Minimum Package4=800pcs SC650T 200 Size: 398mm 383mm 83mm N.W: 1.92kg G.W: 3.67kg Size: 420mm 350mm 405mm N.W: 8.18kg G.W: 15.18kg SC650T_Hardware_Design 109 / 131 Smart LTE Module Series SC650T Hardware Design 10 Appendix A References Table 53: Related Documents SN Document Name Remark
[1]
Quectel_Smart_EVB-G2_User_Guide EVB User Guide for SC650T
[2]
Quectel_SC650T_GPIO_Configuration GPIO Configuration of SC650T
[3]
Quectel_RF_Layout_Application_Note RF Layout Application Note
[4]
Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide
[5]
Quectel_SC650T_Reference_Design Reference Design for SC650T Table 54: Terms and Abbreviations Abbreviation Description ADC AMR bps CS CSD CTS DRX EFR ESD FR Analog-to-Digital Converter Adaptive Multi-rate Bits per Second Coding Scheme Circuit Switched Data Clear to Send Discontinuous Reception Enhanced Full Rate Electrostatic Discharge Full Rate GMSK Gaussian Minimum Shift Keying SC650T_Hardware_Design 110 / 131 Smart LTE Module Series SC650T Hardware Design GPS GPU HR HSDPA HSPA I/O IQ LCD LCM LED LNA LRA MIPI PCB PDU PMI PMU PSK QAM QPSK RF RH RHCP RTC Rx High Speed Down Link Packet Access Global Positioning System Graphics Processing Unit Half Rate High Speed Packet Access Input/Output Inphase and Quadrature Liquid Crystal Display LCD Module Light Emitting Diode Low Noise Amplifier Linear Resonant Actuator Mobile Industry Processor Interface Printed Circuit Board Protocol Data Unit Power Management Interface Power Management Unit Phase Shift Keying Quadrature Amplitude Modulation Quadrature Phase Shift Keying Radio Frequency Relative Humidity Real Time Clock Receive Right Hand Circularly Polarized SC650T_Hardware_Design 111 / 131 Smart LTE Module Series SC650T Hardware Design Short Message Service Terminal Equipment Transmitting Direction Universal Asynchronous Receiver & Transmitter Universal Mobile Telecommunications System
(Universal) Subscriber Identity Module Maximum Voltage Value Normal Voltage Value Minimum Voltage Value Voltage Input Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Voltage Output Minimum Output High Level Voltage Value Maximum Output Low Level Voltage Value Voltage Standing Wave Ratio SMS TE TX UART UMTS
(U)SIM Vmax Vnorm Vmin VI VIHmin VILmax VO VOHmin VOLmax VSWR SC650T_Hardware_Design 112 / 131