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1 2 3 | Attestation Statements | July 16 2023 | ||||||
1 2 3 | BOM | Parts List/Tune Up Info | July 16 2023 | confidential | ||||
1 2 3 | Block Diagram | Block Diagram | July 16 2023 | confidential | ||||
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1 2 3 | Cover Letter(s) | July 16 2023 | ||||||
1 2 3 | RF Exposure Info | July 16 2023 | ||||||
1 2 3 | Schematics | Schematics | July 16 2023 | confidential | ||||
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1 2 3 | Tune up | Parts List/Tune Up Info | July 16 2023 | confidential |
1 2 3 | Users Manual | Users Manual | 1.93 MiB | July 16 2023 / January 13 2024 | delayed release |
SG368Z Series Hardware Design Smart Module Series Version: 1.0.0 Date: 2023-04-28 Status: Preliminary Smart Module Series At Quectel, our aim is to provide timely and comprehensive services to our customers. If you require any assistance, please contact our headquarters:
Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local offices. For more information, please visit:
http://www.quectel.com/support/sales.htm. For technical support, or to report documentation errors, please visit:
http://www.quectel.com/support/technical.htm. Or email us at: support@quectel.com. Legal Notices We offer information as a service to you. The provided information is based on your requirements and we make every effort to ensure its quality. You agree that you are responsible for using independent analysis and evaluation in designing intended products, and we provide reference designs for illustrative purposes only. Before using any hardware, software or service guided by this document, please read this notice carefully. Even though we employ commercially reasonable efforts to provide the best possible experience, you hereby acknowledge and agree that this document and related services hereunder are provided to you on an as available basis. We may revise or restate this document from time to time at our sole discretion without any prior notice to you. Copyright Our and third-party products hereunder may contain copyrighted material. Such copyrighted material shall not be copied, reproduced, distributed, merged, published, translated, or modified without prior written consent. We and the third party have exclusive rights over copyrighted material. No license shall be granted or conveyed under any patents, copyrights, trademarks, or service mark rights. To avoid ambiguities, purchasing in any form cannot be deemed as granting a license other than the normal non-exclusive, royalty-free license to use the material. We reserve the right to take legal action for noncompliance with abovementioned requirements, unauthorized use, or other illegal or malicious use of the material. Trademarks Except as otherwise set forth herein, nothing in this document shall be construed as conferring any rights to use any trademark, trade name or name, abbreviation, or counterfeit product thereof owned by Quectel or any third party in advertising, publicity, or other aspects. Third-Party Rights SG368Z_Series_Hardware_Design 1 / 113 Smart Module Series This document may refer to hardware, software and/or documentation owned by one or more third parties
(third-party materials). Use of such third-party materials shall be governed by all restrictions and obligations applicable thereto. We make no warranty or representation, either express or implied, regarding the third-party materials, including but not limited to any implied or statutory, warranties of merchantability or fitness for a particular purpose, quiet enjoyment, system integration, information accuracy, and non-infringement of any third-party intellectual property rights with regard to the licensed technology or use thereof. Nothing herein constitutes a representation or warranty by us to either develop, enhance, modify, distribute, market, sell, offer for sale, or otherwise maintain production of any our products or any other hardware, software, device, tool, information, or product. We moreover disclaim any and all warranties arising from the course of dealing or usage of trade. Privacy Policy To implement module functionality, certain device data are uploaded to Quectels or third-partys servers, including carriers, chipset suppliers or customer-designated servers. Quectel, strictly abiding by the relevant laws and regulations, shall retain, use, disclose or otherwise process relevant data for the purpose of performing the service only or as permitted by applicable laws. Before data interaction with third parties, please be informed of their privacy and data security policy. Disclaimer a) We acknowledge no liability for any injury or damage arising from the reliance upon the information. b) We shall bear no liability resulting from any inaccuracies or omissions, or from the use of the information contained herein. c) While we have made every effort to ensure that the functions and features under development are free from errors, it is possible that they could contain errors, inaccuracies, and omissions. Unless otherwise provided by valid agreement, we make no warranties of any kind, either implied or express, and exclude all liability for any loss or damage suffered in connection with the use of features and functions under development, to the maximum extent permitted by law, regardless of whether such loss or damage may have been foreseeable. d) We are not responsible for the accessibility, safety, accuracy, availability, legality, or completeness of information, advertising, commercial offers, products, services, and materials on third-party websites and third-party resources. Copyright Quectel Wireless Solutions Co., Ltd. 2023. All rights reserved. SG368Z_Series_Hardware_Design 2 / 113 Smart Module Series Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be paid to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions, such as when the mobile bill is unpaid or the (U)SIM card is invalid. When emergency help is needed in such conditions, use emergency call if the device supports it. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. In an emergency, the device with emergency call function cannot be used as the only contact method considering network connection cannot be guaranteed under all circumstances. The cellular terminal or mobile contains a transceiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV sets, radios, computers or other electric equipment. In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or metal powders. SG368Z_Series_Hardware_Design 3 / 113 Smart Module Series About the Document Revision History Version Date Author Description
2023-04-28 1.0.0 2023-04-28 Glenn GE/Jace ZHANG/
Szymon YU Glenn GE/Jace ZHANG/
Szymon YU Creation of the document Preliminary SG368Z_Series_Hardware_Design 4 / 113 Smart Module Series Contents Safety Information .................................................................................................................................... 3 About the Document ................................................................................................................................ 4 Contents .................................................................................................................................................... 5 Table Index ............................................................................................................................................... 7 Figure Index .............................................................................................................................................. 9 1 Introduction ..................................................................................................................................... 11 Special Marks ........................................................................................................................11 1.1. 2 Product Overview ............................................................................................................................ 12 Frequency Bands and Functions .......................................................................................... 12 Key Features ........................................................................................................................ 13 Functional Diagram ............................................................................................................... 15 Pins Assignment ................................................................................................................... 17 Pins Description .................................................................................................................... 18 EVB Kit ................................................................................................................................. 33 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 3.1. 3 Operating Characteristics .............................................................................................................. 34 Power Supply ....................................................................................................................... 34 3.1.1. Power Supply Interface ................................................................................................ 34 3.1.2. Reference Design for Power Supply ............................................................................ 34 3.1.3. Requirements for Voltage Stability ............................................................................... 35 Turn On ................................................................................................................................. 36 3.2.1. Turn On with PWRKEY ................................................................................................ 36 3.2.2. Turn On with PON_1 .................................................................................................... 37 Turn Off/Restart .................................................................................................................... 38 Standby ................................................................................................................................ 38 Power Output ........................................................................................................................ 38 3.3. 3.4. 3.5. 3.2. 4.1. 4 Application Interfaces ..................................................................................................................... 40 USB Interfaces ..................................................................................................................... 40 4.1.1. Micro USB Interface ..................................................................................................... 41 4.1.2. USB Type-A Interface .................................................................................................. 43 4.1.3. USB Interface Design Considerations ......................................................................... 44 VOL_UP/BOOT .................................................................................................................... 45 SD Card Interface ................................................................................................................. 46 UART .................................................................................................................................... 48 I2C Interfaces ....................................................................................................................... 49 I2S Interfaces ....................................................................................................................... 50 PDM Interface ....................................................................................................................... 51 Analog Audio Interfaces ........................................................................................................ 51 4.8.1. Microphone Interface Reference Design ..................................................................... 52 4.8.2. Headset Interface Reference Design ........................................................................... 53 Loudspeaker Interface Reference Design ................................................................... 54 4.8.3. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. SG368Z_Series_Hardware_Design 5 / 113 Smart Module Series 4.10.1. 4.10.2. 4.10.3. 4.8.4. Audio Interfaces Design Considerations ...................................................................... 54 4.9. ADC Interfaces ..................................................................................................................... 55 4.10. Video Output Interfaces ........................................................................................................ 55 eDP Interface ........................................................................................................ 56 HDMI Interface ..................................................................................................... 58 LCM Interfaces ..................................................................................................... 61 4.11. Camera Interface .................................................................................................................. 63 4.11.1. MIPI Design Considerations ........................................................................................ 67 4.12. Touch Panel Interface ........................................................................................................... 69 4.13. PCIe Interfaces ..................................................................................................................... 69 4.14. RGMII Interfaces .................................................................................................................. 74 4.15. GPIO ..................................................................................................................................... 80 5 RF Specifications ............................................................................................................................ 83 5.1. Wi-Fi & Bluetooth .................................................................................................................. 83 5.1.1. Wi-Fi Overview ............................................................................................................ 83 5.1.2. Bluetooth Overview ...................................................................................................... 86 5.1.3. Reference Design ........................................................................................................ 87 RF Routing Guidelines .......................................................................................................... 87 Requirements for Antenna Design ........................................................................................ 89 RF Connector Recommendation .......................................................................................... 90 5.2. 5.3. 5.4. 6 Electrical Characteristics and Reliability ...................................................................................... 92 Absolute Maximum Ratings .................................................................................................. 92 Power Supply Ratings .......................................................................................................... 92 Power Consumption ............................................................................................................. 93 Digital I/O Characteristics ..................................................................................................... 94 ESD Protection ..................................................................................................................... 96 Operating and Storage Temperatures ................................................................................... 97 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 7 Mechanical Information .................................................................................................................. 98 7.1. Mechanical Dimensions ........................................................................................................ 98 Recommended Footprint .................................................................................................... 100 7.2. Top and Bottom Views ........................................................................................................ 101 7.3. 8 Storage, Manufacturing & Packaging .......................................................................................... 102 8.1. Storage Conditions ............................................................................................................. 102 8.2. Manufacturing and Soldering .............................................................................................. 103 Packaging Specification ...................................................................................................... 105 8.3. 8.3.1. Carrier Tape ............................................................................................................... 105 8.3.2. Plastic Reel ................................................................................................................ 106 8.3.3. Mounting Direction ..................................................................................................... 106 8.3.4. Packaging Process .................................................................................................... 107 9 Appendix References ................................................................................................................... 108 SG368Z_Series_Hardware_Design 6 / 113 Smart Module Series Table Index Table 1: Special Marks ............................................................................................................................. 11 Table 2: Basic Information ....................................................................................................................... 12 Table 3: Frequency Bands and Functions ............................................................................................... 12 Table 4: Key Features ............................................................................................................................. 13 Table 5: Parameters Definition ................................................................................................................ 18 Table 6: Pins Description ......................................................................................................................... 18 Table 7: VBAT and GND Pins .................................................................................................................. 34 Table 8: Pins Description of PWRKEY .................................................................................................... 36 Table 9: Pins Description of PON_1 ........................................................................................................ 37 Table 10: Power Information .................................................................................................................... 38 Table 11: Pins Description of USB Interfaces .......................................................................................... 40 Table 12: USB Interface Trace Length Inside the Module (Unit: mm) ...................................................... 44 Table 13: Pins Description of VOL_UP/BOOT ......................................................................................... 45 Table 14: Pins Description of SD Card Interface ..................................................................................... 46 Table 15: SD Card Interface Trace Length Inside the Module (Unit: mm) ............................................... 48 Table 16: Pins Description of UART ........................................................................................................ 48 Table 17: Pins Description of I2C Interfaces ............................................................................................ 50 Table 18: Pins Description of I2S Interfaces ............................................................................................ 51 Table 19: Pins Description of PDM Interface ........................................................................................... 51 Table 20: Pins Description of Analog Audio Interfaces ............................................................................ 51 Table 21: Pins Description of ADC Interfaces .......................................................................................... 55 Table 22: Pins Description of eDP Interface ............................................................................................ 56 Table 23: eDP Interface Trace Length Inside the Module (Unit: mm) ...................................................... 58 Table 24: Pins Description of HDMI Interface .......................................................................................... 59 Table 25: HDMI Interface Trace Length Inside the Module (Unit: mm) .................................................... 60 Table 26: Pins Description of LCM Interfaces .......................................................................................... 61 Table 27: Pins Description of Camera Interface ...................................................................................... 63 Table 28: MIPI Trace Length Inside the Module (Unit: mm) ..................................................................... 67 Table 29: Pins Description of Touch Panel Interface ............................................................................... 69 Table 30: Pins Description of PCIe Interfaces ......................................................................................... 70 Table 31: PCIe Interface Trace Length Inside the Module (Unit: mm) ..................................................... 73 Table 32: Pins Description of RGMII Interfaces ....................................................................................... 75 Table 33: RGMII Interface Trace Length Inside the Module (Unit: mm) ................................................... 79 Table 34: Pins Description of GPIO ......................................................................................................... 80 Table 35: Pins Description of Wi-Fi & Bluetooth Antenna Interface ......................................................... 83 Table 36: Wi-Fi & Bluetooth Frequency (Unit: MHz) ................................................................................ 83 Table 37: Wi-Fi Transmitting Performance .............................................................................................. 84 Table 38: Wi-Fi Receiving Performance .................................................................................................. 85 Table 39: Bluetooth Data Rates and Versions ......................................................................................... 86 Table 40: Bluetooth Transmitting and Receiving Performance (Unit: dBm) ............................................. 87 Table 41: Requirements for Antenna Design ........................................................................................... 89 SG368Z_Series_Hardware_Design 7 / 113 Smart Module Series Table 42: Absolute Maximum Ratings ..................................................................................................... 92 Table 43: Modules Power Supply Ratings .............................................................................................. 92 Table 44: SG368Z-WF Power Consumption ........................................................................................... 93 Table 45: SG368Z-AP Power Consumption ............................................................................................ 94 Table 46: 1.8 V VCCIO I/O Characteristics (Unit: V) ................................................................................ 94 Table 47: PMUIO0 I/O Characteristics (Unit: V)....................................................................................... 95 Table 48: PMUIO1 I/O Characteristics (Unit: V)....................................................................................... 95 Table 49: PMUIO2 I/O Characteristics (Unit: V)....................................................................................... 95 Table 50: SD Card High-voltage I/O Characteristics (Unit: V) ................................................................. 95 Table 51: SD Card Low-voltage I/O Characteristics (Unit: V) .................................................................. 96 Table 52: ESD Characteristics (Temperature: 2530 C, Humidity: 40 5 %, Unit: kV) ........................... 96 Table 53: Operating and Storage Temperatures (Unit: C) ...................................................................... 97 Table 54: Recommended Thermal Profile Parameters .......................................................................... 104 Table 55: Carrier Tape Dimension Table (Unit: mm) .............................................................................. 105 Table 56: Plastic Reel Dimension Table (Unit: mm) ............................................................................... 106 Table 57: Related Documents ............................................................................................................... 108 Table 58: Terms and Abbreviations ........................................................................................................ 108 SG368Z_Series_Hardware_Design 8 / 113 Smart Module Series Figure Index Figure 1: Functional Diagram ..................................................................... Error! Bookmark not defined. Figure 2: Pins Assignment (Top View) ..................................................................................................... 17 Figure 3: Reference Design of Power Input ............................................................................................ 34 Figure 4: Reference Design of Power Supply ......................................................................................... 35 Figure 5: Reference Design of Turn On with Driving Circuit .................................................................... 36 Figure 6: Reference Design of Turn On with Keystroke .......................................................................... 36 Figure 7: Timing of Turn On with PWRKEY ............................................................................................. 37 Figure 8: Timing of Turn Off ..................................................................................................................... 38 Figure 9: Reference Design of Micro USB Interface ................................................................................ 42 Figure 10: Reference Design of USB Type-A Interface ........................................................................... 43 Figure 11: Reference Design of VOL_UP/BOOT ..................................................................................... 46 Figure 12: Reference Design of SD Card Interface ................................................................................. 47 Figure 13: Reference Design of UART with Level-shifting Chip .............................................................. 49 Figure 14: Reference Design of Differential Microphone Interface .......................................................... 52 Figure 15: Reference Design of Single-ended Microphone Interface ...................................................... 53 Figure 16: Reference Design of Headset Interface ................................................................................. 53 Figure 17: Reference Design of Loudspeaker Interface .......................................................................... 54 Figure 18: Reference Design of eDP Interface ........................................................................................ 57 Figure 19: Reference Design of HDMI Interface...................................................................................... 59 Figure 20: Reference Design of LCM Interface ....................................................................................... 62 Figure 21: Reference Design of LCM Interface External Backlight Drive ................................................ 63 Figure 22: Reference Design of One-Camera Application ....................................................................... 65 Figure 23: Reference Design of Dual-Camera Application ...................................................................... 66 Figure 24: Reference Design of Touch Panel Interface ........................................................................... 69 Figure 25: Schematic Diagram of PCIe1 Interface .................................................................................. 72 Figure 26: Schematic Diagram of 2 Lane RC Mode of PCIe2 Interface .................................................. 72 Figure 27: Schematic Diagram of 2 Lane EP Mode of PCIe2 Interface ................................................... 72 Figure 28: Schematic Diagram of 1 Lane RC + 1 Lane RC Mode of PCIe2 Interface ............................. 73 Figure 29: Reference Design of RGMII Interface PHY with External Crystal........................................... 77 Figure 30: Reference Design of RGMII Interface PHY with Modules 25 MHz Clock .............................. 78 Figure 31: Reference Design of Wi-Fi & Bluetooth Antenna .................................................................... 87 Figure 32: Microstrip Design on a 2-layer PCB ....................................................................................... 88 Figure 33: Coplanar Waveguide Design on a 2-layer PCB ...................................................................... 88 Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) ................... 88 Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) ................... 89 Figure 36: Dimensions of the Receptacle (Unit: mm) .............................................................................. 90 Figure 37: Specifications of Mated Plugs (Unit: mm) ............................................................................... 90 Figure 38: Space Factor of the Mated Connectors (Unit: mm) ................................................................ 91 Figure 39: Top and Side Dimensions ....................................................................................................... 98 Figure 40: Bottom Dimensions ................................................................................................................ 99 Figure 41: Recommended Footprint ...................................................................................................... 100 SG368Z_Series_Hardware_Design 9 / 113 Smart Module Series Figure 42: Top & Bottom Views of the Module ....................................................................................... 101 Figure 43: Recommended Reflow Soldering Thermal Profile ................................................................ 103 Figure 44: Carrier Tape Dimension Drawing .......................................................................................... 105 Figure 45: Plastic Reel Dimension Drawing .......................................................................................... 106 Figure 46: Mounting Direction ............................................................................................................... 106 Figure 47: Packaging Process............................................................................................................... 107 SG368Z_Series_Hardware_Design 10 / 113 Smart Module Series 1 Introduction This document describes the SG368Z series modules features, performance, and air interfaces and hardware interfaces connected to your applications. The document provides a quick insight into interface specifications, RF performance, electrical and mechanical specifications, and other module information, as well. NOTE For conciseness purposes, SG368Z-WF and SG368Z-AP will hereinafter be referred to collectively as
''the module'' in parts hereof applicable to both models, and individually as ''SG368Z-WF'' and
"SG368Z-AP" in parts hereof referring to the differences between them. 1.1. Special Marks Table 1: Special Marks Marks Definitions
Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin, AT command, or argument is under development and currently not supported; and the asterisk (*) after a model indicates that the sample of the model is currently unavailable. Brackets ([]) used after a pin enclosing a range of numbers indicate all pins of the same type. For example, SDIO_DATA[0:3] refers to all four SDIO_DATA pins, SDIO_DATA0, SDIO_DATA1, SDIO_DATA2 and SDIO_DATA3. SG368Z_Series_Hardware_Design 11 / 113 Smart Module Series 2 Product Overview SG368Z series is Quectels new generation of Linux/Android smart module. It is an SMD module with compact packaging and it supports built-in high performance ARM Mali G52 GPU, multiple audio and video codecs, and multiple audio and video input/output interfaces as well as abundant GPIO interfaces. With these, the module is engineered to meet most of the demands of M2M applications, for instance:
IoT gateways smart commercial displays AI industrial automation security surveillance NAS NVR/DVR Table 2: Basic Information SG368Z Series Packaging type Pin counts Dimensions Weight Models LGA 453 46.0 42.0 3.15 mm SG368Z-WF: approx. 13.1 g SG368Z-AP: approx. 12.8 g SG368Z-WF, SG368Z-AP 2.1. Frequency Bands and Functions Table 3: Frequency Bands and Functions Wireless Network Type SG368Z-WF SG368Z-AP Wi-Fi 802.11a/b/g/n/ac 24022482 MHz
SG368Z_Series_Hardware_Design 12 / 113 Smart Module Series 51805825 MHz Bluetooth 4.2 24022480 MHz
2.2. Key Features Table 4: Key Features Categories Descriptions Application Processor Quad-core 64-bit ARM Cortex-A55 CPU Up to 2 GHz 32 KB L1 I-cache, 32 KB L1 D-cache, 512 KB L3 cache GPU ARM Mali G52 GPU Memory Industrial grade:
8 GB eMMC + 1 GB LPDDR4X (default) 16 GB eMMC + 2 GB LPDDR4X (optional) Commercial grade:
32 GB eMMC + 2 GB LPDDR4X (default) 32 GB eMMC + 4 GB LPDDR4X (optional) Operating System Android 11*/12*/13, Linux (Kernel 4.19/5.10*) Supply Voltage 3.33.5 V Typ.: 3.4 V USB Interfaces 1 USB 3.0 and 2.0 OTG interface (USB0):
Supports Host and Device modes Supports AT command communication, data transmission, software debugging, firmware upgrade (only supports firmware upgrade through USB 2.0) SS channel can be multiplexed into SATA0* interface 1 USB 3.0 and 2.0 Host interface (USB1):
Only supports Host mode SS channel can be multiplexed into SATA1 or QSGMII/SGMII*
interface 2 USB 2.0 Host interfaces (USB2 and USB3):
SD Card Interface Only support Host mode Complies with SD 3.0 protocol 1.8/3.3 V SD card SD card hot-plug SG368Z_Series_Hardware_Design 13 / 113 Smart Module Series UART SG368Z-AP Up to 8 groups of UART for SG368Z-WF; Up to 10 groups of UART for I2C Interfaces I2S Interfaces Analog Audio Interfaces PDM Interface Speed rate up to 4 Mbps Up to 5 groups of I2C interfaces Only support master mode Up to 2 groups of I2S interfaces for SG368Z-AP Up to 1 group of I2S interface for SG368Z-WF Audio input:
1 analog microphone input Audio outputs:
Class AB stereo headphone output Class D loudspeaker differential amplifier output 1 group of PDM interface Supports up to 6-lane PDM audio input Audio Codec MP3, AAC, AAC+ and PCM ADC Interfaces 5 generic ADC interfaces Resolution: up to 10-bit eDP Interface HDMI Interface LCM Interfaces Video Codec Camera Interface 1 group of 4-lane eDP interface Data rate: up to 2.7 Gbps/lane Supports 1-lane or 2-lane or 4-lane mode Supports AUX channel Supports up to 2560 1600 @ 60 fps HDMI 2.0 Supports hot-plug Supports up to 4096 2160 @ 60 fps 2 groups of MIPI DSI: 4-lane MIPI DSI0 and 4-lane MIPI DSI1 Data rate: up to 2.5 Gbps/lane 1 group of MIPI DSI (4-lane) supports up to 1920 1080 @ 60 fps 2 groups of MIPI DSI (8-lane) supports up to 2048 1536 @ 60 fps MIPI DSI0 can be multiplexed into LVDS, supports up to 1280 800 @
60 fps Encoding: 1080p @ 60 fps Decoding: 4K @ 60 fps Supports 1 group of 4-lane MIPI CSI or 2 groups of 2-lane MIPI CSI Data rate: up to 2.5 Gbps/lane Up to 8 MP Touch Panel Interface Supports I2C TP interface 1 group of 1-lane PCIe 2.0 interface, only supports RC mode, can be PCIe Interfaces multiplexed into SATA2 or QSGMII/SGMII* interface RGMII Interfaces 1 group of 2-lane PCIe 3.0 interface Up to 1 group of RGMII interface for SG368Z-WF Up to 2 groups of RGMII interfaces for SG368Z-AP SG368Z_Series_Hardware_Design 14 / 113 Smart Module Series Antenna Interface Wi-Fi & Bluetooth antenna interface (ANT_RF) 50 characteristic impedance WLAN Features Operating modes: AP and STA Operating frequency: 2.4 GHz, 5 GHz Protocol features: IEEE 802.11a/b/g/n/ac Data rate: up to 433.3 Mbps Bluetooth Features Bluetooth Core Specification Version 4.2 Bluetooth Classic & Bluetooth Low Energy (BLE) Real Time Clock The module supports RTC function Temperature Ranges Normal operating temperature 1:
- Commercial grade: -10 C to +75 C Industrial grade: -40 C to +85 C
Storage temperature: -40 to +90 C Firmware Upgrade USB 2.0 interface OTA RoHS All hardware components are fully Complies with EU RoHS directive 2.3. Functional Diagram The main components of the block diagram are explained below:
Power management Baseband part eMMC + LPDDR4X flash Radio frequency part Peripheral interfaces 1 Within the operating temperature range, the module meets IEEE specifications. SG368Z_Series_Hardware_Design 15 / 113 Smart Module Series NOTE 1. SG368Z-AP does not support WLAN and Bluetooth function. 2. SG368Z-WF only supports 1 group of RGMII interface. SG368Z_Series_Hardware_Design 16 / 113 Smart Module Series 2.4. Pins Assignment Figure 1: Pins Assignment (Top View) NOTE 1. Keep all RESERVED pins and unused pins unconnected unless otherwise specified. 2. All GND pins should be connected to ground. SG368Z_Series_Hardware_Design 17 / 113 7CSI_LN0_N11CSI_LN3_N16CSI_LN2_N21GND26DSI0_LN3_P31DSI0_LN2_P36DSI0_CLK_P41DSI0_LN1_P46DSI0_LN0_P51GND56HDMI_CLK_M61HDMI_TX0_M66HDMI_TX1_M71HDMI_TX2_M76GND81PCIE1_REFCLK_P86PCIE1_RX_P90PCIE1_TX_P94GND97MIC_M100HPH_L102HPH_R104SPK_P105GND5CSI_LN1_P8CSI_LN0_P12CSI_LN3_P17CSI_LN2_P22GND27DSI0_LN3_N32DSI0_LN2_N37DSI0_CLK_N42DSI0_LN1_N47DSI0_LN0_N52GND57HDMI_CLK_P62HDMI_TX0_P67HDMI_TX1_P72HDMI_TX2_P77GND82PCIE1_REFCLK_M87PCIE1_RX_M91PCIE1_TX_M95GND98MIC_P101HPH_GND103SPK_M6CSI_CLK1_N9CSI_CLK1_P13GND18GND23DSI1_LN3_N28DSI1_LN2_N33DSI1_CLK_N38DSI1_LN1_N43DSI1_LN0_N48GND53PCIE2_REFCLK_P58PCIE2_TX0_P63PCIE2_TX1_P68PCIE2_RX0_P73PCIE2_RX1_P78GND83USB1_DM88USB1_SS_TX_M92USB1_SS_RX_M96GND99GND10GPIO0_D614GND19DSI1_LN3_P24DSI1_LN2_P29DSI1_CLK_P34DSI1_LN1_P39DSI1_LN0_P44GND49PCIE2_REFCLK_M54PCIE2_TX0_M59PCIE2_TX1_M64PCIE2_RX0_M69PCIE2_RX1_M74GND79USB1_DP84USB1_SS_TX_P89USB1_SS_RX_P93GND15RESERVED20RESERVED25GPIO0_C430TP_RST35TP_INT40TP_I2C1_SDA45TP_I2C1_SCL50GPIO0_C155PWM460GPIO0_D465GND70EDP_DET75CAM1_MCLK80GPIO0_D585HOST_PWR_EN280GND275RESERVED270RESERVED265RESERVED260RESERVED255RESERVED250RESERVED245RESERVED240RESERVED235GND230RESERVED225GPIO0_B0220GPIO0_B7215GPIO0_C0210GPIO0_C5288RGMII1_REFCLKOUT284I2C2_SDA279CAM0_MCLK274GND269RESERVED264RESERVED259GND254RESERVED249RESERVED244RESERVED239RESERVED234RESERVED229RESERVED224GND219RESERVED214RESERVED209GPIO0_C7205RESERVED294RGMII1_RX1291GPIO4_B2287I2C2_SCL283GND278RGMII1_MCLK273I2C3_SCL268I2C3_SDA263GND258PDM_CLK1253PDM_DIN1248PDM_DIN2243PDM_DIN3238GND233ADC4228ADC5223ADC6218ADC2213ADC7208RESERVED204RESERVED201RESERVED298RGMII1_TX_CTL296RGMII1_RX0293RGMII1_RX_CTL290RGMII1_MDC286RGMII1_MDIO282VCCIO1277GPIO1_D4272GPIO1_D2267GPIO1_D1262SD_VDD257SD_DATA3252SD_CLK247SD_CMD242SD_PU_VDD237GND232VOL_DOWN227ESC222MENU217EXT_EN212GND207GND203GND200GND198RESERVED300GND299RESERVED297USB3_DM295USB3_DP292USB2_DM289USB2_DP285GND281GPIO1_D3276GPIO1_D0271VCCIO2266GND261SD_DET256SD_DATA2251SD_DATA1246SD_DATA0241GND236VOL_UP/BOOT231RESET_N226PWRKEY221PON_1216GND211GND206ANT_RF202GND199GND197RESERVED196GND301GND302VCCIO6304RGMII1_RX_CLK307RGMII1_RX3311GND316CAM0_PWDN321GPIO3_C6326GND331UART5_RXD336GPIO3_B5341GND346GPIO3_A6351GPIO3_A5356GND361UART8_TXD366PCIE1_CLKREQ_N371VCCIO5375GND379HDMI_DET382HDMI_CEC385HDMI_SDA387HDMI_SCL389VCCIO7390GND303RGMII1_TX1305RGMII1_TX0308RGMII1_RX2312RGMII1_TX2317CAM0_RST322LCD1_RST327UART7_TXD332UART5_TXD337GPIO3_B6342GPIO3_B4347GPIO3_A7352GPIO3_A4357UART8_RXD362PCIE2_RST0_N367PCIE1_WAKE_N372GND376I2S3_MCLK380I2S3_DOUT383I2S3_DIN386I2S3_SCLK388I2S3_LRCK306RGMII1_TX_CLK309GND313CAM1_PWDN318GPIO3_D0323GND328UART7_RXD333PCIE1_RST_N338GND343GPIO3_B3348GPIO3_B0353GND358PCIE2_RST1_N363PCIE2_WAKE0_N368PCIE2_CLKREQ1_N373GND377RESERVED381RESERVED384GPIO4_D2310RGMII1_TX3314CAM1_RST319GPIO3_D1324GND329RESERVED334UART3_RXD339UART3_TXD344UART4_TXD349UART4_RXD354GPIO3_A3359GPIO3_A2364PCIE2_CLKREQ0_N369PCIE2_WAKE1_N374DBG_TXD378DBG_RXD315RESERVED320RESERVED325GND330RESERVED335RESERVED340RESERVED345RESERVED350GND355VCC_PMUIO2360RESERVED365RESERVED370GPIO0_C6175RGMII0_RX_CTL170GPIO2_C516532K_CLK160RGMII0_REFCLKOUT155I2C4_SDA150PMU_32K_CLK145GND140RESERVED135RESERVED130RESERVED125GPIO0_D3120GND183RGMII0_RX0179RGMII0_RX1174RGMII0_RX2169RGMII0_RX3164RGMII0_RX_CLK159I2C4_SCL154GND149GND144GND139BUCK5_1V8134VCC_SWOUT1129LDO6_3V3124LDO9_1V8119GND115GND189GND186GND182RGMII0_TX3178RGMII0_TX2173RGMII0_TX1168RGMII0_TX0163RGMII0_TX_CLK158GND153VBAT148VBAT143GND138GND133GND128GND123GPIO0_A5118USB0_ID114GND111USB0_VBUS193GND191GND188GND185RGMII0_MDIO181RGMII0_MDC177RGMII0_MCLK172RGMII0_TX_CTL167GND162GND157VBAT152VBAT147VBAT142GND137EDP_AUX_N132EDP_ML0_N127EDP_ML1_N122EDP_ML2_N117EDP_ML3_N113USB0_DM110USB0_SS_RX_M108USB0_SS_TX_M195GND194GND192RESERVED190GND187GND184GND180VCCIO4176VCC_SPK_HP171VRTC166GND161VBAT156VBAT151VBAT146GND141EDP_AUX_P136EDP_ML0_P131EDP_ML1_P126EDP_ML2_P121EDP_ML3_P116GND112USB0_DP109USB0_SS_RX_P107USB0_SS_TX_P106GND1GND2CSI_CLK0_N3CSI_CLK0_P4CSI_LN1_N391GND392GND393GND394GND395GND396GND397GND398GND399GND400GND401GND402GND403GND404GND405GND406GND407GND408GND409GND410GND411GND412GND413GND414GND415GND416GND417GND418GND419GND420GND421GND422GND423GND424GND425GND426GND427GND428GND429GND430GND431GND432GND433GND434GND435GND436GND437GND438GND439GND440GND441GND442GND443GND444GND445GND446GND447GND448GND449GND450GND451GND452GND453GNDPowerGPIOSDCameraTPUARTRGMIILCMHDMIUSBPCIEEDPAnalog AudioADCOthersRF AntennaRESERVEDGNDDigital AudioI2CKeypad Smart Module Series 2.5. Pins Description Table 5: Parameters Definition Parameters AI AO AIO DI DO DIO OD PI PO Descriptions Analog Input Analog Output Analog Input/Output Digital Input Digital Output Digital Input/Output Open Drain Power Input Power Output DC characteristics include power domain and rate current in the table below. Table 6: Pins Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment VBAT 147, 148, 151, 152, 153, 156, 157, 161 PI Power supply for the module VCCIO1 282 PO VCCIO2 271 PO 1.8 V output power, reference voltage for VCCIO1 power domain 1.8 V output power, reference voltage for VCCIO2 power domain Vmax = 3.5 V Vmin = 3.3 V Vnom = 3.4 V Vnom = 1.8 V Vnom = 1.8 V SG368Z_Series_Hardware_Design 18 / 113 Smart Module Series VCCIO4 180 PO VCCIO5 371 PO VCCIO6 302 PO VCCIO7 389 PO VCC_PMUIO2 355 PO LDO6_3V3 129 PO 1.8 V output power, reference voltage for VCCIO4 power domain 1.8 V output power, reference voltage for VCCIO5 power domain 1.8 V output power, reference voltage for VCCIO6 power domain 1.8 V output power, reference voltage for VCCIO7 power domain 1.8 V output power, reference voltage for PMUIO2 and PMUIO0 power domain 3.3 V output power, reference voltage for PMUIO1 power domain Vnom = 1.8 V Vnom = 1.8 V Vnom = 1.8 V Vnom = 1.8 V Vnom = 1.8 V Vnom = 3.3 V LDO9_1V8 BUCK5_1V8 124 139 PO 1.8 V output power for MIPI LCM VIO Vnom = 1.8 V PO 1.8 V output power Vnom = 1.8 V VCC_SWOUT1 134 PO VRTC*
171 PI VBAT output power 1 Power supply for RTC Vnom = VBAT Keep this pin unconnected. GND 1, 13, 14, 18, 21, 22, 44, 48, 51, 52, 65, 74, 7678, 9396, 99, 105, 106, 114116, 119, 120, 128, 133, 138, 142146, 149, 154, 158, 162, 166, 167, 184, 186191, 193196, 199, 200, 202, 203, 207, 211, 212, 216, 224, 235, 237, 238, 241, 259, 263, 266, 274, 280, 283, 285, 300, 301, 309, 311, 323, 324, 325, 326, 338, 341, 350, 353, 356, 372, 373, 375, 390453 Analog Audio Interfaces Pin Name Pin No. I/O Description HPH_L 100 AO Headphone left channel output DC Characteristics Comment SG368Z_Series_Hardware_Design 19 / 113 Smart Module Series HPH_R 102 AO HPH_GND 101 AI SPK_P 104 AO SPK_M 103 AO MIC_P MIC_M 98 97 AI AI Headphone right channel output Headphone reference ground Loudspeaker output
(+) Loudspeaker output
(-) Microphone input (+) Microphone input (-) VCC_SPK_HP 176 PI Analog audio power supply Vmax = 5.5 V Vmin = 2.7 V Vnom = 5 V If unused, connect this pin to ground. If the analog audio function is not used, this pin needs to be connected to VBAT. USB Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment HOST_PWR_EN 85 DO Host USB VBUS power enable PMUIO1 Can not supply power for peripherals. A test point must be reserved. Internally pull up to 1.8 V. A test point must be reserved. A test point must be reserved. USB0_VBUS 111 DI USB0 insertion detection VIHmax = 2.7 V VIHmin = 3.3 V USB0_ID 118 DI USB0 ID detect VILmax = 0.3 V USB0_DP 112 AIO USB0_DM 113 AIO USB0_SS_TX_P 107 AO USB0_SS_TX_M 108 AO USB0_SS_RX_P 109 USB0_SS_RX_M 110 AI AI USB1_DP 79 AIO USB0 2.0 differential data (+) USB0 2.0 differential data (-) USB0 3.0 transmit
(+) USB0 3.0 transmit
(-) USB0 3.0 receive (+) USB0 3.0 receive (-) USB1 2.0 differential data (+) SG368Z_Series_Hardware_Design 20 / 113 Smart Module Series USB1_DM 83 AIO USB1_SS_TX_P 84 USB1_SS_TX_M 88 USB1_SS_RX_P 89 USB1_SS_RX_M 92 AO AO AI AI USB2_DP 289 AIO USB2_DM 292 AIO USB3_DP 295 AIO USB3_DM 297 AIO PCIe Interfaces USB1 2.0 differential data (-) USB1 3.0 transmit
(+) USB1 3.0 transmit
(-) USB1 3.0 receive (+) USB1 3.0 receive (-) USB2 2.0 differential data (+) USB2 2.0 differential data (-) USB3 2.0 differential data (+) USB3 2.0 differential data (-) Pin Name Pin No. I/O Description DC Characteristics Comment PCIE1_TX_P PCIE1_TX_M PCIE1_RX_P PCIE1_RX_M 90 91 86 87 PCIE1_REFCLK_P 81 PCIE1_REFCLK_M 82 PCIE1_CLKREQ_N 366 PCIE1_WAKE_N 367 AO PCIe1 transmit (+) AO PCIe1 transmit (-) AI AI AO AO DI DI PCIe1 receive (+) PCIe1 receive (-) PCIe1 reference clock (+) PCIe1 reference clock (-) PCIe1 clock request VCCIO5 PCIe1 wake up VCCIO5 PCIE1_RST_N 333 DO PCIe1 reset VCCIO5 PCIE2_TX0_P PCIE2_TX0_M PCIE2_TX1_P PCIE2_TX1_M 58 54 63 59 AO PCIe2 transmit 0 (+) AO PCIe2 transmit 0 (-) AO PCIe2 transmit 1 (+) AO PCIe2 transmit 1 (-) SG368Z_Series_Hardware_Design 21 / 113 Smart Module Series PCIE2_RX0_P PCIE2_RX0_M PCIE2_RX1_P PCIE2_RX1_M 68 64 73 69 PCIE2_REFCLK_P 53 PCIE2_REFCLK_M 49 AI AI AI AI AI AI PCIe2 receive 0 (+) PCIe2 receive 0 (-) PCIe2 receive 1 (+) PCIe2 receive 1 (-) PCIe2 reference clock (+) PCIe2 reference clock (-) PCIE2_CLKREQ0_ N 364 DIO PCIe2 channel 0 clock request VCCIO5 PCIE2_WAKE0_N 363 DIO PCIe2 channel 0 wake up VCCIO5 PCIE2_RST0_N 362 DIO PCIe2 channel 0 reset VCCIO5 PCIE2_CLKREQ1_ N 368 PCIE2_WAKE1_N 369 DI DI PCIE2_RST1_N 358 DO PCIe2 channel 1 clock request PCIe2 channel 1 wake up PCIe2 channel 1 reset VCCIO5 VCCIO5 VCCIO5 SD Card Interface If unused, connect this pin to ground. If unused, connect this pin to ground. When PCIe2 is configured in PCIe 2 lane mode, this pin is used for clock request function. When PCIe2 is configured in PCIe 2 lane mode, this pin is used for wake up function. When PCIe2 is configured in PCIe 2 lane mode, this pin is used for reset function. Pin Name Pin No. I/O Description DC Characteristics Comment SD_VDD 262 PO SD card power supply Vnom = VBAT Dedicated for SD card power supply. SD_CLK SD_CMD SD_DATA0 252 247 246 DO SD card clock VCCIO3 DIO SD card command VCCIO3 DIO SDIO data bit 0 VCCIO3 SG368Z_Series_Hardware_Design 22 / 113 Smart Module Series SD_DATA1 SD_DATA2 SD_DATA3 SD_DET 251 256 257 261 SD_PU_VDD 242 PO Touch Panel Interface DIO SDIO data bit 1 VCCIO3 DIO SDIO data bit 2 VCCIO3 DIO SDIO data bit 3 VCCIO3 DI SD card hot-plug detect 1.8/3.3 V output power for SD card pull-up circuits PMUIO1 Vnom =
1.8/3.3 V Pin Name Pin No. I/O Description DC Characteristics Comment TP_RST TP_INT TP_I2C1_SCL TP_I2C1_SDA LCM Interfaces 30 35 45 40 DO TP reset PMUIO2 DI TP interrupt PMUIO2 OD TP I2C clock PMUIO2 OD TP I2C data PMUIO2 Pin Name Pin No. I/O Description DC Characteristics Comment LCD1_RST 322 DO LCD1 reset VCCIO6 DSI0_CLK_N DSI0_CLK_P DSI0_LN0_N DSI0_LN0_P DSI0_LN1_N DSI0_LN1_P DSI0_LN2_N DSI0_LN2_P DSI0_LN3_N 37 36 47 46 42 41 32 31 27 AO LCD0 MIPI clock (-) AO LCD0 MIPI clock (+) AO AO AO AO AO AO AO LCD0 MIPI lane 0 data (-) LCD0 MIPI lane 0 data (+) LCD0 MIPI lane 1 data (-) LCD0 MIPI lane 1 data (+) LCD0 MIPI lane 2 data (-) LCD0 MIPI lane 2 data (+) LCD0 MIPI lane 3 data (-) SG368Z_Series_Hardware_Design 23 / 113 Smart Module Series DSI0_LN3_P DSI1_CLK_N DSI1_CLK_P DSI1_LN0_N DSI1_LN0_P DSI1_LN1_N DSI1_LN1_P DSI1_LN2_N DSI1_LN2_P DSI1_LN3_N DSI1_LN3_P eDP Interface 26 33 29 43 39 38 34 28 24 23 19 AO LCD0 MIPI lane 3 data (+) AO LCD1 MIPI clock (-) AO LCD1 MIPI clock (+) AO AO AO AO AO AO AO AO LCD1 MIPI lane 0 data (-) LCD1 MIPI lane 0 data (+) LCD1 MIPI lane 1 data (-) LCD1 MIPI lane 1 data (+) LCD1 MIPI lane 2 data (-) LCD1 MIPI lane 2 data (+) LCD1 MIPI lane 3 data (-) LCD1 MIPI lane 3 data (+) Pin Name Pin No. I/O Description DC Characteristics Comment EDP_ML0_P EDP_ML0_N EDP_ML1_P EDP_ML1_N EDP_ML2_P EDP_ML2_N EDP_ML3_P EDP_ML3_N EDP_AUX_P 136 132 131 127 126 122 121 117 141 AO eDP data 0 (+) AO eDP data 0 (-) AO eDP data 1 (+) AO eDP data 1 (-) AO eDP data 2 (+) AO eDP data 2 (-) AO eDP data 3 (+) AO eDP data 3 (-) AIO eDP auxiliary channel (+) eDP auxiliary channel (-) EDP_AUX_N 137 AIO EDP_DET 70 DI eDP hot-plug detect PMUIO2 SG368Z_Series_Hardware_Design 24 / 113 Smart Module Series HDMI Interface Pin Name Pin No. I/O Description DC Characteristics Comment HDMI_TX2_P HDMI_TX2_M HDMI_TX1_P HDMI_TX1_M HDMI_TX0_P HDMI_TX0_M HDMI_CLK_P HDMI_CLK_M HDMI_DET HDMI_SCL HDMI_SDA HDMI_CEC Camera Interfaces 72 71 67 66 62 61 57 56 379 387 385 382 AO HDMI data 2 (+) AO HDMI data 2 (-) AO HDMI data 1 (+) AO HDMI data 1 (-) AO HDMI data 0 (+) AO HDMI data 0 (-) AO HDMI clock (+) AO HDMI clock (-) DI HDMI hot-plug detect VIHmax = 5.3 V VIHmin = 2.4 V Active high. OD HDMI I2C clock VCCIO7 OD HDMI I2C data VCCIO7 DIO HDMI CEC signal VCCIO7 Pin Name Pin No. I/O Description DC Characteristics Comment CSI_CLK0_N CSI_CLK0_P CSI_CLK1_N CSI_CLK1_P CSI_LN0_N CSI_LN0_P CSI_LN1_N CSI_LN1_P 2 3 6 9 7 8 4 5 CSI_LN2_N 16 AI AI AI AI AI AI AI AI AI MIPI CSI clock 0 (-) MIPI CSI clock 0 (+) MIPI CSI clock 1 (-) MIPI CSI clock 1 (+) MIPI CSI lane 0 data
(-) MIPI CSI lane 0 data
(+) MIPI CSI lane 1 data
(-) MIPI CSI lane 1 data
(+) MIPI CSI lane 2 data
(-) SG368Z_Series_Hardware_Design 25 / 113 Smart Module Series CSI_LN2_P CSI_LN3_N CSI_LN3_P CAM0_MCLK CAM0_RST 17 11 12 279 317 AI AI AI MIPI CSI lane 2 data
(+) MIPI CSI lane 3 data
(-) MIPI CSI lane 3 data
(+) DO Master clock of camera 0 VCCIO6 DO Reset of camera 0 VCCIO6 CAM0_PWDN 316 DO CAM1_MCLK 75 DO Power down of camera 0 Master clock of camera 1 VCCIO6 PMUIO1 CAM1_RST 314 DO Reset of camera 1 VCCIO6 CAM1_PWDN 313 DO Power down of camera 1 VCCIO6 RGMII Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment RGMII0_RX0 183 RGMII0_RX1 179 RGMII0_RX2 174 RGMII0_RX3 169 RGMII0_RX_CTL 175 RGMII0_RX_CLK 164 DI DI DI DI DI DI RGMII0_TX0 168 DO RGMII0_TX1 173 DO RGMII0_TX2 178 DO RGMII0_TX3 182 DO RGMII0_TX_CTL 172 DO RGMII0 receive data bit 0 RGMII0 receive data bit 1 RGMII0 receive data bit 2 RGMII0 receive data bit 3 RGMII0 receive control RGMII0 receive clock RGMII0 transmit data bit 0 RGMII0 transmit data bit 1 RGMII0 transmit data bit 2 RGMII0 transmit data bit 3 RGMII0 transmit control VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. SG368Z_Series_Hardware_Design 26 / 113 Smart Module Series Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. The output frequency of reference clock is 25 MHz. The output frequency of reference clock is 125 MHz;
Only SG368Z-AP supports this pin. RGMII0_TX_CLK 163 DO RGMII0_MDC 181 DO RGMII0_MDIO 185 OD RGMII0 transmit clock RGMII0 management data clock RGMII0 management data input/output VCCIO4 VCCIO4 VCCIO4 RGMII0_ REFCLKOUT 160 DO RGMII0 reference clock output VCCIO4 RGMII0_MCLK 177 DI RGMII0 clock input VCCIO4 RGMII1_RX0 296 RGMII1_RX1 294 RGMII1_RX2 308 RGMII1_RX3 307 RGMII1_RX_CTL 293 RGMII1_RX_CLK 304 DI DI DI DI DI DI RGMII1_TX0 305 DO RGMII1_TX1 303 DO RGMII1_TX2 312 DO RGMII1_TX3 310 DO RGMII1_TX_CTL 298 DO RGMII1_TX_CLK 306 DO RGMII1_MDC 290 DO RGMII1 receive data bit 0 RGMII1 receive data bit 1 RGMII1 receive data bit 2 RGMII1 receive data bit 3 RGMII1 receive control RGMII1 receive clock RGMII1 transmit data bit 0 RGMII1 transmit data bit 1 RGMII1 transmit data bit 2 RGMII1 transmit data bit 3 RGMII1 transmit control RGMII1 transmit clock RGMII1 management data VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 SG368Z_Series_Hardware_Design 27 / 113 Smart Module Series RGMII1_MDIO 286 OD clock RGMII1 management data input/output VCCIO6 RGMII1_ REFCLKOUT 288 DO RGMII1 reference clock output VCCIO6 RGMII1_MCLK 278 DI RGMII1 clock input VCCIO6 The output frequency of reference clock is 25 MHz. The output frequency of reference clock is 125 MHz. Keypad Interfaces Pin Name Pin No. I/O Description PWRKEY 226 DI VOL_UP/BOOT 236 AI Turn on/off the module Volume up;
Control the module into firmware upgrade mode DC Characteristics Comment VBAT Active low. 1.8 V Active low. A test point is recommended to be reserved. VOL_DOWN 232 AI Volume down 1.8 V Active low. RESET_N 231 DI Reset the module 1.8 V PON_1 221 DI LOW to HIGH indicates power on VIHmax = 1.4 V VIHmin = 0.8 V Active low. A test point is recommended to be reserved if unused. Under normal VBAT power supply conditions, if this pin is detected as high level, the turning-on process will be triggered. After turning-on, PON_1 can be pulled down or kept high, which does not affect the turning-on status. SG368Z_Series_Hardware_Design 28 / 113 Smart Module Series ESC MENU UART 227 222 AI Esc keypad AI Menu keypad 1.8 V 1.8 V Active low. Active low. Pin Name Pin No. I/O Description DC Characteristics Comment DBG_TXD 374 DO DBG_RXD 378 DI Debug UART transmit Debug UART receive PMUIO2 PMUIO2 The default baud rate is 115200 bps. Test points must be reserved. UART3_TXD UART3_RXD UART4_TXD UART4_RXD UART5_TXD UART5_RXD UART7_TXD UART7_RXD UART8_TXD UART8_RXD I2C Interfaces 339 334 344 349 332 331 327 328 361 357 DO UART3 transmit VCCIO5 DI UART3 receive VCCIO5 DO UART4 transmit VCCIO5 DI UART4 receive VCCIO5 DO UART5 transmit VCCIO5 DI UART5 receive VCCIO5 DO UART7 transmit VCCIO5 DI UART7 receive VCCIO5 DO UART8 transmit VCCIO5 DI UART8 receive VCCIO5 Pin Name Pin No. I/O Description DC Characteristics Comment I2C2_SDA I2C2_SCL I2C3_SDA I2C3_SCL I2C4_SDA I2C4_SCL 284 287 268 273 155 159 OD I2C2 serial data VCCIO6 OD I2C2 serial clock VCCIO6 OD I2C3 serial data VCCIO1 OD I2C3 serial clock VCCIO1 OD I2C4 serial data VCCIO4 OD I2C4 serial clock VCCIO4 I2S and PDM Interfaces SG368Z_Series_Hardware_Design 29 / 113 Smart Module Series Pin Name Pin No. I/O Description DC Characteristics Comment I2S3_SCLK I2S3_LRCK I2S3_DOUT I2S3_DIN I2S3_MCLK PDM_CLK1 PDM_DIN1 PDM_DIN2 PDM_DIN3 386 388 380 383 376 258 253 248 243 DO I2S3 bit clock VCCIO7 DO I2S3 channel select VCCIO7 DO I2S3 data output VCCIO7 DI I2S3 data input VCCIO7 DO I2S3 master clock VCCIO7 DO PDM clock 1 VCCIO1 DI DI DI PDM data input 1 VCCIO1 PDM data input 2 VCCIO1 PDM data input 3 VCCIO1 RF Antenna Interface Pin Name Pin No. I/O Description ANT_RF 206 AIO Wi-Fi/Bluetooth antenna interface ADC Interfaces DC Characteristics Comment Pin Name Pin No. I/O Description DC Characteristics Comment ADC2 ADC4 ADC5 ADC6 ADC7 218 233 228 223 213 AI AI AI AI AI General-purpose ADC interface General-purpose ADC interface General-purpose ADC interface General-purpose ADC interface General-purpose ADC interface Input voltage range: 0~1.8 V Other Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment EXT_EN 217 DO External device enable signal Vnom = VBAT After the module is turned on, this pin outputs a high level. SG368Z_Series_Hardware_Design 30 / 113 Smart Module Series PMU_32K_CLK 150 OD PMU 32 kHz clock output 32K_CLK 165 DO 32 kHz clock output VCCIO4 Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. PWM4 GPIO 55 DO PWM output 4 PMUIO2 Pin Name Pin No. I/O Description DC Characteristics Comment GPIO0_D3 125 DIO GPIO0_D4 GPIO0_D5 GPIO0_D6 60 80 10 DIO DIO DIO GPIO0_A5 123 DIO GPIO0_B0 225 DIO GPIO0_B7 220 DIO GPIO0_C0 215 DIO GPIO0_C1 GPIO0_C4 50 25 DIO DIO GPIO0_C5 210 DIO GPIO0_C6 370 DIO GPIO0_C7 209 DIO GPIO1_D0 276 DIO GPIO1_D1 267 DIO GPIO1_D2 272 DIO GPIO1_D3 281 DIO General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output PMUIO0 PMUIO0 PMUIO0 PMUIO0 PMUIO1 PMUIO2 PMUIO2 PMUIO2 PMUIO2 PMUIO2 PMUIO2 PMUIO2 PMUIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. SG368Z_Series_Hardware_Design 31 / 113 Smart Module Series Only SG368Z-AP supports this pin. GPIO1_D4 277 DIO GPIO2_C5 170 DIO GPIO3_A2 359 DIO GPIO3_A3 354 DIO GPIO3_A4 352 DIO GPIO3_A5 351 DIO GPIO3_A6 346 DIO GPIO3_A7 347 DIO GPIO3_B0 348 DIO GPIO3_B3 343 DIO GPIO3_B4 342 DIO GPIO3_B5 336 DIO GPIO3_B6 337 DIO GPIO3_C6 321 DIO GPIO3_D0 318 DIO GPIO3_D1 319 DIO GPIO4_B2 291 DIO GPIO4_D2 384 DIO RESERVED Pins Pin Name Pin No. General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output VCCIO2 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 RESERVED 15, 20, 130, 135, 140, 192, 197, 198, 201, 204, 205, 208, 214, 219, 229, 230, 234, 239, 240, 244, 245, 249, 250, 254, 255, 260, 264, 265, 269, 270, 275, 299, 315, 320, 329, 330, 335, 340, 345, 360, 365, 377, 381 SG368Z_Series_Hardware_Design 32 / 113 Smart Module Series 2.6. EVB Kit To help you develop applications with the module, Quectel supplies an evaluation board (SG368Z Series EVB) with accessories to control or test the module. For more details, see document [1]. SG368Z_Series_Hardware_Design 33 / 113 Smart Module Series 3 Operating Characteristics 3.1. Power Supply 3.1.1. Power Supply Interface The module provides 8 VBAT pins dedicate to connecting with the external power supply. The power supply range of the module is 3.33.5 V, and the recommended value is 3.4 V. Table 7: VBAT and GND Pins Pin Name Pin No. I/O Description Comment VBAT 147, 148, 151, 152, 153, 156, 157, 161 PI Power supply for the module GND 142, 143, 144, 146, 149, 154, 158, 162, 166 Ground 3.1.2. Reference Design for Power Supply Power design for the module is essential. The power supply of the module should be able to provide sufficient current of 3 A* at least. If the voltage difference between input voltage and the supply voltage is small, it is suggested to use an LDO; if the voltage difference is big, a buck converter is recommended. The following figure shows a reference design for LDO power supply:
Figure 2: Reference Design of Power Input SG368Z_Series_Hardware_Design 34 / 113 DC_INC1C2U1INOUTENGNDADJ24135VBAT 100 nFC3470 FC4100 nFR2220K100KR3470 F470R51KR4R11 %1 %
Smart Module Series NOTE To avoid corrupting the data in the internal flash, do not turn off the power supply to turn off the module when the module works normally. Only after turning off the module with PWRKEY, then you can cut off the power supply. 3.1.3. Requirements for Voltage Stability The recommended power supply voltage of the module is 3.4 V. The power supply performance, such as load capacity, voltage ripple, etc. will directly influence the modules performance and stability. Under ultimate conditions, the module may have a transient peak current up to 3 A*. If the power supply capability is not sufficient, there will be voltage drops, and if the voltage drops below 3.3 V, the module will turn off automatically. Therefore, ensure the input voltage never drops below 3.3 V. To prevent the voltage from dropping below 3.3 V, it is recommended to connect a 100 F bypass capacitor with low ESR as well as 4.7 F, 100 nF, 33 pF and 10 pF filter capacitors in parallel near the VBAT pins of the module. It is also recommended that the PCB traces of VBAT should be as short as possible and wide enough to reduce the equivalent impedance of the VBAT traces and ensure that there will be no large voltage drop under high current at the maximum transmission power. The width of VBAT trace should be at least 3 mm*. As per design rules, the longer the VBAT trace is, the wider it should be. Additionally, the ground plane of the power supply part should be as complete as possible. To suppress the impact of power fluctuations and ensure the stability of the output power supply, it is suggested to add a TVS component of at least 2000 W and place it as close to the VBAT pins as possible to enhance surge protection. The following figure shows a reference circuit:
Figure 3: Reference Design of Power Supply SG368Z_Series_Hardware_Design 35 / 113 ModuleVBATVBATC1100 F +C2100 nF C333 pF C410 pF D1C54.7 FGND Smart Module Series 3.2. Turn On 3.2.1. Turn On with PWRKEY Table 8: Pins Description of PWRKEY Pin Name Pin No. PWRKEY 226 I/O DI Description Comment Turn on/off the module Active low. When powering up the VBAT, the module can be turned on by driving PWRKEY low for at least 200 ms. It is recommended to use an open drain/collector driver to control the PWRKEY. PWRKEY is pulled up to VBAT internally. Figure 4: Reference Design of Turn On with Driving Circuit Another way to control the PWRKEY is using a keystroke directly. When pressing the keystroke, an electrostatic strike may be generated from finger. Therefore, you should place a TVS near the keystroke for ESD protection. Additionally, a 1 k resistor is connected in series to PWRKEY for ESD protection. Figure 5: Reference Design of Turn On with Keystroke SG368Z_Series_Hardware_Design 36 / 113 PWRKEY 200 msMCUGPIOModuleTurn on pulse4.7K47KQ1PWRKEYModuleS1Close to S1TVS1KTurn-on pulseR1 Smart Module Series Figure 6: Timing of Turn On with PWRKEY
. NOTE 1. When the module is powered up for the first time, its turn on timing may be different from that shown in the figure above. 2. Ensure the voltage of VBAT is stable before driving the PWRKEY low. It is recommended to drive PWRKEY low after VBAT reaches 3.4 V and remains stable. PWRKEY cannot be driven low all the time. 3.2.2. Turn On with PON_1 Table 9: Pins Description of PON_1 Pin Name Pin No. I/O Description Comment PON_1 221 DI LOW to HIGH indicates power on High level voltage range:
0.81.4 V Recommended value:
1.2 V Under normal VBAT power supply conditions, pull up PON_1, and then the turning-on process will be triggered. After the module is turned on, PON_1 can be pulled down or kept high, which does not affect the turning-on status. SG368Z_Series_Hardware_Design 37 / 113 VBAT 3.4 VPWRKEYOthers~100 msStartEXT_EN~4050 msVCC_PMUIO/VCCIO/LDO/BUCK~25 msRESET_N> 200 ms Smart Module Series 3.3. Turn Off/Restart The module can be turned off by driving the PWRKEY low for at least 6 seconds. It can be restarted by driving RESET_N low (for at least 100 ms). Figure 7: Timing of Turn Off 3.4. Standby Under normal conditions, driving PWRKEY low for 0.51 s can make the module enter standby state. Then driving PWRKEY low for 0.51 s again can wake up the module. 3.5. Power Output The module supports multiple regulated voltage output for peripheral circuits. In practical application, it is recommended to use a 10-pF and a 33-pF capacitor in parallel to suppress high-frequency noise. Table 10: Power Information Pin Name Default Voltage (V) Drive Current (mA) Standby VCCIO1 VCCIO2 VCCIO4 VCCIO5 1.8 1.8 1.8 1.8 50 50 50 50 OFF OFF ON OFF SG368Z_Series_Hardware_Design 38 / 113 VBATPWRKEYOthers>6 sPower off Smart Module Series 1.8 1.8 1.8 3.3 1.8 1.8 1.8 VCCIO6 VCCIO7 VCC_PMUIO2 LDO6_3V3 LDO9_1V8 BUCK5_1V8 VCC_SWOUT1
. NOTE 50 50 50 50 50 100 100 OFF OFF ON ON OFF OFF OFF IO of VCCIO4 power domain will power down in standby state. SG368Z_Series_Hardware_Design 39 / 113 Smart Module Series 4 Application Interfaces 4.1. USB Interfaces The module provides 4 USB interfaces which complies with USB 3.0 and USB 2.0 specifications. USB 3.0 supports SuperSpeed mode and the data rate is up to 5 Gbps; USB 2.0 supports high-speed mode and the data rate is up to 480 Mbps. USB0 interface:
Supports USB 3.0 and USB 2.0 specifications Supports USB OTG function Supports Host mode and Device mode Supports AT command communication, data transmission, software debugging, firmware upgrade
(only supports firmware upgrade through USB 2.0) USB 3.0 SS channel can be multiplexed into SATA0* interface. For the multiplexing relationship, see document [2]
USB1 interface:
Supports USB 3.0 and USB 2.0 specifications Only supports Host mode USB3.0 SS channel can be multiplexed into SATA1 or QSGMII/SGMII* interface. For the multiplexing relationship, see document [2]
USB2 and USB3 interfaces:
Support USB 2.0 specifications Only support Host mode Table 11: Pins Description of USB Interfaces Pin Name Pin No. I/O Description Comment HOST_PWR_EN 85 DO Host USB VBUS power enable SG368Z_Series_Hardware_Design 40 / 113 Smart Module Series USB0_VBUS 111 DI USB0 insertion detection Can not supply power for peripherals. A test point must be reserved. USB0_ID 118 DI USB0 ID detect Internally pull up to 1.8 V. USB0_DP 112 AIO USB0 2.0 differential data (+) USB0_DM 113 AIO USB0 2.0 differential data (-) A test point must be reserved. A test point must be reserved. USB0_SS_TX_P 107 USB0_SS_TX_M 108 USB0_SS_RX_P 109 USB0_SS_RX_M 110 USB1_DP USB1_DM 79 83 USB1_SS_TX_P 84 USB1_SS_TX_M 88 USB1_SS_RX_P 89 USB1_SS_RX_M 92 AO AO AI AI USB0 3.0 transmit (+) USB0 3.0 transmit (-) USB0 3.0 receive (+) USB0 3.0 receive (-) AIO USB1 2.0 differential data (+) AIO USB1 2.0 differential data (-) AO AO AI AI USB1 3.0 transmit (+) USB1 3.0 transmit (-) USB1 3.0 receive (+) USB1 3.0 receive (-) USB2_DP USB2_DM USB3_DP USB3_DM 289 292 295 297 AIO USB2 2.0 differential data (+) AIO USB2 2.0 differential data (-) AIO USB3 2.0 differential data (+) AIO USB3 2.0 differential data (-) 4.1.1. Micro USB Interface Only USB0_DP and USB0_DM are the system firmware burning interface. If you do not use this interface, please be sure to reserve this interface and test points during the debugging and production process, otherwise you will not be able to debug and produce burning firmware. USB0_ID is internally pulled up to 1.8 V with an about 200 k resistor. USB0_VBUS is used to detect OTG mode and Device mode. It is active at high level. Its voltage range is 2.73.3 V, and the typical value is 3.0 V. It is recommended to place a 100 nF capacitor near SG368Z_Series_Hardware_Design 41 / 113 Smart Module Series USB0_VBUS. USB0 can be configured in the following three modes:
OTG mode (default): USB0 can switch automatically between Device mode and Host mode according to the state of USB0_ID. If USB0_ID is at high level, USB0 is in Device mode, and if USB0_ID is at low level, USB0 is in Host mode. In Device mode, the module can judge whether the USB0_VBUS pin is at high level. If it is, USB0_DP will be pulled up to start enumeration. Device mode: When USB0 is configured to this mode, there is no need to pay attention to the state of USB0_ID. The module only needs to judge whether the USB0_VBUS pin is at high level. If it is, USB0_DP will be pulled up to start enumeration. Host mode: When USB0 is configured to this mode, there is no need to pay attention to the states of USB0_ID and USB0_VBUS. (If you only need Host mode, but you also need to use USB0_DP/USB0_DM for system firmware burning during debugging and production, then you need to configure USB0 to Device mode during burning and ABD debugging. Under this condition, USB0_VBUS signal must be connected.) Before Uboot starts, USB0 is in Device mode by default; after Uboot starts, USB0 can be configured to the above three modes according to demand. The reference design of Micro USB interface realized by USB0 is shown below:
Figure 8: Reference Design of Micro USB Interface
. NOTE 1. To suppress electromagnetic radiation, common-mode chokes (common-mode choke coil) can be added on the USB0_DP/USB0_DM signals, and other USB 2.0 interfaces can also refer to this SG368Z_Series_Hardware_Design 42 / 113 ENVIN5V_OUTGND10K USB0_DPUSB0_DMUSB0_VBUSUSB0_ID12345USB_DPUSB_DMVBUSUSB_IDGNDGNDGNDGNDGND678915KModuleGPIOVINC1C2POWER ICR1Schottky10KR2R3ESDESDESDESD100 nFC3R2100 Smart Module Series design. 2. The Schottky diode in the above figure is used for anti-backflow, which will affect the VBUS output power supply capability. If there is a high requirement for power supply capability, it is recommended to choose a power chip that supports anti-backflow. 4.1.2. USB Type-A Interface The reference design of USB Type-A interface realized by USB0 is shown below:
Figure 9: Reference Design of USB Type-A Interface
. NOTE 1. USB Type-C design requires an external CC logic chip and an SS channel switch. For details, see document [3]. 2. The Type-A design of USB1, USB2, and USB3 interfaces can refer to the above figure. It should be noted that the module does not have corresponding VBUS and USB_ID. For external VBUS 5 V output enable control pin, you can choose HOST_PWR_EN, or choose other GPIO. SG368Z_Series_Hardware_Design 43 / 113 ENVIN5V_OUTGND10K USB0_DPUSB0_DMUSB0_VBUS12398USB_DPUSB_DMVBUSGNDGNDGNDGND471015KModuleHOST_PWR_ENVINC1C2POWER ICR1Schottky10KR2R3100 nFC3USB0_SS_TX_PUSB0_SS_TX_MUSB0_SS_RX_PUSB0_SS_RX_MSS_TX_PSS_TX_MSS_RX_PSS_RX_MType-AC4C5100 nF100 nF0R0RR4R56511 Smart Module Series 4.1.3. USB Interface Design Considerations Table 12: USB Interface Trace Length Inside the Module (Unit: mm) Pin Name Pin No. Length Length Matching (P-M) USB0_DP USB0_DM 112 113 USB0_SS_TX_P 107 USB0_SS_TX_M 108 USB0_SS_RX_P 109 USB0_SS_RX_M 110 USB1_DP USB1_DM 79 83 USB1_SS_TX_P 84 USB1_SS_TX_M 88 USB1_SS_RX_P 89 USB1_SS_RX_M 92 USB2_DP USB2_DM USB3_DP USB3_DM 289 292 295 297 31.89 31.80 34.35 34.38 31.63 31.55 21.90 21.81 22.27 22.45 26.00 26.12 43.18 43.00 42.56 42.31 0.09
-0.03 0.08 0.09
-0.18
-0.12 0.18 0.25 To ensure performance, you should follow the following principles when designing USB interfaces:
Route USB signal traces as differential pairs with surrounded ground. The impedance of USB differential trace is 90 . Route USB differential traces at the inner-layer of the PCB, and surround the traces with ground on that layer and ground planes above and below. For signal traces, provide clearance from power supply traces, crystal-oscillators, magnetic devices, sensitive signals like RF signals, analog signals, and noise signals generated by clock, DC-DC, etc. The reference ground plane under the USB signal traces must be continuous without any cuts or vias SG368Z_Series_Hardware_Design 44 / 113 Smart Module Series to ensure impedance continuity. Pay attention to the impact caused by stray capacitance of the ESD protection component on USB data traces. Typically, stray capacitance should be less than 3 pF for USB 2.0, and less than 0.4 pF for USB 3.0. Do not route USB 3.0 signal traces under RF signal traces. Crossing or being parallel with RF signal traces is forbidden. For USB 3.0 signal traces, length matching of each differential data pair (Tx/Rx) should be less than 0.3 mm. For USB 3.0, the clearance between Rx and Tx signal traces should be 4 times the signal trace width. The clearance between USB 3.0 signal traces and other signal traces should be 4 times the signal trace width. For USB 2.0 signal traces, the differential data pair matching (P/M) should be less than 0.5 mm. For USB 2.0, the clearance between DP-DM signal traces and other signal traces should be 3 times the signal trace width. 4.2. VOL_UP/BOOT VOL_UP/BOOT is used to control the module to enter firmware upgrade mode. It is at high level by default. On the premise that VOL_UP/BOOT is not pressed and the module has been burned with firmware, VOL_UP/BOOT is used for the volume up function by default after the module is turned on. If VOL_UP/BOOT button is pressed when the module is turned on, that is, VOL_UP/BOOT is kept at low level, the module enters the Loader burning mode. When the PC recognizes the USB device, release the button to restore the VOL_UP/BOOT to high level and then you can upgrade the firmware. Table 13: Pins Description of VOL_UP/BOOT Pin Name Pin No. I/O Description Comment VOL_UP/BOOT 236 AI Volume up;
Control the module into firmware upgrade mode Active low. A test point is recommended to be reserved. SG368Z_Series_Hardware_Design 45 / 113 Smart Module Series Figure 10: Reference Design of VOL_UP/BOOT
. NOTE The VOL_UP/BOOT grounded circuit cannot be connected in series with resistors to prevent affecting the internal voltage division. 4.3. SD Card Interface SD card interface of the module complies with SD 3.0 specifications:
Table 14: Pins Description of SD Card Interface Pin Name Pin No. I/O Description Comment SD_VDD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 SD_DET 262 252 247 246 251 256 257 261 PO SD card power supply Dedicated for SD card power supply. DO SD card clock DIO SD card command DIO SDIO data bit 0 DIO SDIO data bit 1 DIO SDIO data bit 2 DIO SDIO data bit 3 DI SD card hot-plug detect SG368Z_Series_Hardware_Design 46 / 113 S1 ModuleVOL_UP/BOOT Smart Module Series SD_PU_VDD 242 PO 1.8/3.3 V output power for SD card pull-up circuits Figure 11: Reference Design of SD Card Interface SD_VDD is a peripheral driver power supply for SD card. The maximum drive current is 600 mA. Because of the high drive current, it is recommended to keep the trace width as at least 0.6 mm. To ensure the stability of drive power, you should add a 4.7-F and a 33-pF capacitor in parallel near the SD card connector. SD_CMD, SD_CLK and SD_DATA[0:3] are all high-speed signal traces. In PCB design, control the characteristic impedance of these traces as 50 , shield them and do not cross them with other traces. It is recommended to route these traces on the inner layer of PCB and keep their lengths the same. Additionally, SD_CLK needs separate ground shielding. Layout guidelines:
Control impedance to 50 10 %, and add ground shielding. Trace length matching between SD_CLK and SD_CMD/SD_DATA should be less than 3 mm. Trace length requirements: less than 150 mm when SD_CLK frequency is less than or equal to 50 MHz; less than 100 mm when SD_CLK frequency is greater than 50 MHz. Clearance between SD card signal traces should be greater than or equal to 2 times the trace width and the clearance between SD card signal traces and other signal traces should be greater than or equal to 3 times the trace width. The load capacitance requirements of SD_DATA[0:3], SD_CLK and SD_CMD traces: less than 9 pF for SD 2.0; less than 1 pF for SD 3.0. SG368Z_Series_Hardware_Design 47 / 113 SD_CMDNM_100KNM_51KSD_DATA3SD_DATA2SD_CLKSD_DATA0SD_DETSD_DATA1P1-DAT2P2-CD/DAT3P3-CMDP4-VDDP5-CLKP8-DAT1GNDP6-VSSP7-DAT0DETECTIVEGNDGNDGND1234567891011121333R33R33R33R33R33R100R33 pF4.7 FModuleR1R2R3R4R5R6NM_51KNM_10KNM_51KNM_51KR7R8R9R10R11R12R13D1D2D3D4D5D6D7D8C1C2SD Card ConnectorLDO6_3V3SD_VDDSD_PU_VDD Smart Module Series Table 15: SD Card Interface Trace Length Inside the Module (Unit: mm) Pin Name Pin No. Length Length Matching with SD_CLK 43.60 42.92 41.08 41.44 41.73 41.83
0.68 2.52 2.16 1.87 1.77 SD_CLK 252 SD_CMD 247 SD_DATA0 246 SD_DATA1 251 SD_DATA2 256 SD_DATA3 257 4.4. UART SG368Z-WF supports up to 8 groups of UART and SG368Z-AP supports up to 10 groups of UART. 6 of them are configured by default, and the rest of them are multiplexed from other interfaces. For detailed multiplexing relationship, see document [2]. UART features:
Each UART contains two 64-byte FIFOs for data reception and transmission Support 115.2 kbps, 460.8 kbps, 921.6 kbps, 1.5 Mbps, 3 Mbps and 4 Mbps Support programmable baud rate and non-integer clock divider Support 58 bit width transmission Table 16: Pins Description of UART Pin Name Pin No. I/O Description Comment DBG_TXD DBG_RXD UART3_TXD UART3_RXD UART4_TXD 374 378 339 334 344 DO Debug UART transmit DI Debug UART receive The default baud rate is 115200 bps. Test points must be reserved. DO UART3 transmit DI UART3 receive DO UART4 transmit SG368Z_Series_Hardware_Design 48 / 113 Smart Module Series UART4_RXD UART5_TXD UART5_RXD UART7_TXD UART7_RXD UART8_TXD UART8_RXD 349 332 331 327 328 361 357 DI UART4 receive DO UART5 transmit DI UART5 receive DO UART7 transmit DI UART7 receive DO UART8 transmit DI UART8 receive The power domain of UART is 1.8 V. You can use a level-shifting chip between the module and hosts UART if the power domains are not matching:
Figure 12: Reference Design of UART with Level-shifting Chip NOTE Debug UART is similar to UARTx and for the reference design, refer to Figure 12. For debug UART, VCC_PMUIO2 is used as power supply pin for VCCA. 4.5. I2C Interfaces The module supports up to 5 groups of I2C interfaces. 4 of them are configured by default, and 1 of them is multiplexed from other interfaces. For detailed multiplexing relationship, see document [2]. All I2C interfaces are open drain signals and therefore you must pull them up externally. The reference power domain is 1.8 V. SG368Z_Series_Hardware_Design 49 / 113 VCCAVCCBOEA1A2GNDB1B2VCCIOxUARTx_RXDTXD_3.3 VVDD_3.3 VC1100pFC2U1100pFRXD_3.3 V10K120KUARTx_TXD Smart Module Series I2C features:
Support I2C bus master mode Support programmable clock frequency by software and the data rate is up to 400 kbps Support 7-bit and 10-bit addressing modes Table 17: Pins Description of I2C Interfaces Pin Name I2C2_SDA I2C2_SCL I2C3_SDA I2C3_SCL I2C4_SDA I2C4_SCL TP_I2C1_SCL TP_I2C1_SDA Pin No. 284 287 268 273 155 159 45 40 I/O OD OD OD OD OD OD OD OD Description I2C2 serial data I2C2 serial clock I2C3 serial data I2C3 serial clock I2C4 serial data I2C4 serial clock TP I2C clock TP I2C data 4.6. I2S Interfaces SG368Z-WF supports up to 1 group of I2S interface; SG368Z-AP supports up to 2 groups of I2S interfaces. 1 of them is configured by default and 1 of them is multiplexed from other interface, see document [2]. I2S features:
Bit rate is from 16 bits to 32 bits Sampling rate is up to 192 kHz Support master or slave mode Support I2S, PCM, TDM modes Support PCM formats: early, late1, late2, late3 Support up to TDM 16 channels I2S, PCM, TDM modes can not be used simultaneously SG368Z_Series_Hardware_Design 50 / 113 Smart Module Series Table 18: Pins Description of I2S Interfaces Pin Name Pin No. I2S3_SCLK I2S3_LRCK I2S3_DOUT I2S3_DIN I2S3_MCLK 386 388 380 383 376 4.7. PDM Interface I/O DO DO DO DI DO Description I2S3 bit clock I2S3 channel select I2S3 data output I2S3 data input I2S3 master clock The module supports 1 group of digital audio interface. The interface supports up to 6-lane PDM audio input. The sampling rate is up to 192 kHz and the bit rate is from 16 bits to 32 bits. Table 19: Pins Description of PDM Interface Pin Name Pin No. PDM_CLK1 PDM_DIN1 PDM_DIN2 PDM_DIN3 258 253 248 243 I/O DO DI DI DI Description PDM clock 1 PDM data input 1 PDM data input 2 PDM data input 3 4.8. Analog Audio Interfaces The module provides 1 analog input channels and 2 analog output channels:
Table 20: Pins Description of Analog Audio Interfaces Pin Name Pin No. I/O Description Comment HPH_L 100 AO Headphone left channel output SG368Z_Series_Hardware_Design 51 / 113 Smart Module Series HPH_R 102 AO Headphone right channel output HPH_GND 101 AI Headphone reference ground If unused, connect this pin to ground. SPK_P SPK_M MIC_P MIC_M 104 103 98 97 AO AO AI AI Loudspeaker output (+) Loudspeaker output (-) Microphone input (+) Microphone input (-) VCC_SPK_HP 176 PI Analog audio power supply If the analog audio function is not used, this pin needs to be connected to VBAT. The module offers 1 differential MIC input pair, which can also be used as 2 single-ended MIC input channels. VCCIO1 can be used as MIC_BIAS and the output voltage is 1.8 V by default. The loudspeaker interface uses the differential output. The output channel is available with a Class D amplifier whose maximum output power is 1.3 W when the load is 8 . The headset interface features stereo left and right channel output, and headset insert detection function is supported. 4.8.1. Microphone Interface Reference Design Figure 13: Reference Design of Differential Microphone Interface SG368Z_Series_Hardware_Design 52 / 113 MIC_MECM MICModuleMIC_P12D2MIC_PMIC_MD1GNDC1100pF100RR11.1KR21.1KR3VCCIO1C21 F Smart Module Series Figure 14: Reference Design of Single-ended Microphone Interface 4.8.2. Headset Interface Reference Design Figure 15: Reference Design of Headset Interface NOTE 1. ADC2 can be used for headset HOOK function, which is under development. 2. GPIO is used for headset insert detection function. VCCIOx indicates the reference voltage of GPIO. If it is required to support headset insert detection function in a low power consumption state, the GPIO of PMUIO power domain should be selected. 3. HPH_GND needs to be routed separately to the headset socket and connected to GND to reduce the SG368Z_Series_Hardware_Design 53 / 113 ECM MICModuleMIC1_P12MIC_PMIC_MD1GNDC1200 pF100RR12.2KR2VCCIO1C21 FTVS ArrayHPH_LGPIOHPH_RHPH_GNDModuleR1265314D1D2D3VCCIO1C21 FR90RMIC_M2.2KADC21 KR7D4MICR_AUDIOL_AUDIOGNDDETECTGND100RVCCIOxC1100 nFR2100KR3100KR4R50RR60RR8100KC3100 nFC4C5NMNM Smart Module Series level difference between the headset GND. Route HPH_GND trace between HPH_R and HPH_L to avoid interference from other signals. 4. HPH_R/HPH_L can be used for LINEOUT function to connect to an external power amplifier. In this scenario, HPH_GND can be connected to ground at the module end. 4.8.3. Loudspeaker Interface Reference Design Figure 16: Reference Design of Loudspeaker Interface NOTE 1. The headset and loudspeaker functions require an external 5 V power supply input, and the power supply input pin is VCC_SPK_HP. 2. The module can provide a maximum driving capacity of 1.3 W @ 8 (5 V power supply). If you need to drive a higher-power speaker, it is recommended to add an power amplifier chip. 4.8.4. Audio Interfaces Design Considerations The filter capacitor on the PCB should be placed near the audio device or audio interface as close as possible, and the trace should be as short as possible. The filter capacitor should be passed before reaching other connection points. To decrease signal interferences, RF antennas should be placed away from audio interfaces and audio traces. Power traces and audio traces should not be parallel, and they should be far away from each other. The differential audio traces must be routed according to the differential signal layout rule. SG368Z_Series_Hardware_Design 54 / 113 EARPEARNSPK_PSPK_MNMModuleD1D2NMC1C2GND Smart Module Series 4.9. ADC Interfaces The module provides 5 ADC interfaces which support up to 10-bit resolution. Table 21: Pins Description of ADC Interfaces Pin Name Pin No. I/O Description Comment ADC2 ADC4 ADC5 ADC6 ADC7 218 233 228 223 213 AI AI AI AI AI General-purpose ADC interface General-purpose ADC interface General-purpose ADC interface Input voltage range: 0~1.8 V General-purpose ADC interface General-purpose ADC interface 4.10. Video Output Interfaces The module has a built-in VOP controller and it has three output ports:
Port 1: Supports HDMI, MIPI DSI0, MIPI DSI1 and eDP video output Port 2: Supports HDMI, MIPI DSI0, MIPI DSI1, eDP and LVDS video output Port 3: Supports LVDS, RGB*, BT1120*, BT656* video output Each port only supports one kind of video signal. The module supports triple-screen display and the three screens can support different video signal. The module supports multiple video display interfaces:
1 group of HDMI interface: supports HDMI 2.0, with the maximum output resolution up to 4096 2160 @ 60 fps 1 group of MIPI DSI0 interface: supports MIPI 1.2, with the maximum output resolution up to 1920 1080 @ 60 fps; it can be multiplexed into LVDS interface, with the maximum output resolution up to 1280 800 @ 60 fps 1 group of MIPI DSI1 interface: supports MIPI 1.2, with the maximum output resolution up to 1920 1080 @ 60 fps. MIPI DSI0 and MIPI DIS1 can be combined to support Dual-MIPI, with the maximum output resolution up to 2048 1536 @ 60 fps 1 group of eDP interface: supports eDP V1.3, with the maximum output resolution up to 2560 1600
@ 60 fps SG368Z_Series_Hardware_Design 55 / 113 Smart Module Series 1 group of RGB* interface: supports parallel 24 bits RGB output, with the maximum output resolution up to 1920 1080 @ 60 fps 1 group of BT1120* interface: supports 16 bits BT1120 output, with the maximum output resolution up to 1920 1080 @ 60 fps 1 group of BT656* interface: supports 8 bits BT656 output 4.10.1. eDP Interface The module supports eDP V1.3 and supports 1 group of 4-lane eDP interface, with the maximum output resolution up to 2560 1600 @ 60 fps. Supports data rate: up to 2.7 Gbps/lane Supports 1-lane or 2-lane or 4-lane mode Supports AUX channel Supports data rate up to 1 Mbps Table 22: Pins Description of eDP Interface Pin Name Pin No. EDP_ML0_P EDP_ML0_N EDP_ML1_P EDP_ML1_N EDP_ML2_P EDP_ML2_N EDP_ML3_P EDP_ML3_N EDP_AUX_P EDP_AUX_N EDP_DET 136 132 131 127 126 122 121 117 141 137 70 I/O AO AO AO AO AO AO AO AO AIO AIO DI Description eDP data 0 (+) eDP data 0 (-) eDP data 1 (+) eDP data 1 (-) eDP data 2 (+) eDP data 2 (-) eDP data 3 (+) eDP data 3 (-) eDP auxiliary channel (+) eDP auxiliary channel (-) eDP hot-plug detect SG368Z_Series_Hardware_Design 56 / 113 Smart Module Series Figure 17: Reference Design of eDP Interface NOTE 1. Confirm that whether level-shift is needed for PWM, BL_EN, HPD and other signals according to the selected module pins and eDP LCD specifications. 4. 2. For LCDs that support eDP V1.2a and above protocols, R1 and R2 are not mounted. 3. If the eDP LCD has requirements on the power-up timing, the modules GPIO can be selected for timing control. If the application scenario involves frequent plugging and unplugging of the eDP connector or has high requirements for ESD protection, it is recommended to reserve a TVS near the connector, and the TVS junction capacitance should not exceed 0.4 pF. 5. EDP_DET is optional and can be configured as required. SG368Z_Series_Hardware_Design 57 / 113 VDDINVDDINVDDINGNDPWMGND EDP_ML0_PNCNCNCBL_ENHPDGNDDAUXPDRX0PDRX0NGNDGNDGND1234567891012131415161718192021222324252627GNDVLED29283011100 nF4.7 FModuleeDP LCDC1NCNCNCGNDEDP_ML0_NEDP_ML1_PEDP_ML1_NEDP_ML2_PEDP_ML2_NEDP_ML3_PEDP_ML3_NEDP_AUX_PEDP_AUX_NDAUXNDRX1PDRX1NDRX2PDRX2NDRX3PDRX3NC2VCC_3V3Level shiftLevel shiftLevel shiftVCC_12V100 nF4.7 FC3C4100 nFC5100 nFC6100 nFC7100 nFC8100 nFC9100 nFC10100 nFC11100 nFC12100 nFC13100 nFC14R1100KR2100KGPIOPWMEDP_DET Smart Module Series Table 23: eDP Interface Trace Length Inside the Module (Unit: mm) Pin Name Pin No. Length Length Matching (N-P) EDP_ML0_P 136 EDP_ML0_N 132 EDP_ML1_P 131 EDP_ML1_N 127 EDP_ML2_P 126 EDP_ML2_N 122 EDP_ML3_P 121 EDP_ML3_N 117 EDP_AUX_P 141 EDP_AUX_N 137 33.18 33.34 31.89 31.92 34.51 34.66 31.55 31.78 30.86 30.94
-0.16
-0.03
-0.15
-0.23
-0.08 To ensure performance, the following principles should be complied with when designing eDP interface:
Special attention should be paid to the pin description of eDP interface. Different eDP device will have varied definitions for their corresponding connectors. Ensure that the devices and the connectors are correctly connected. eDP are high-speed signal traces, supporting maximum data rate up to 2.7 Gbps. The differential impedance should be controlled to 100 . Additionally, it is recommended to route the traces on the inner layer of PCB and do not cross it with other traces. To avoid crosstalk, a clearance of 4 times the trace width is recommended among eDP signal traces. During impedance matching, do not connect eDP signal traces to GND on different planes to ensure impedance consistency. It is recommended to select a TVS of low capacitance for ESD protection and the recommended parasitic capacitance should be lower than 0.4 pF. Route eDP traces according to the following requirements:
a) The total trace length should not exceed 150 mm;
b) Control the differential impedance to 100 10 %;
c) Control intra-lane length matching within 0.3 mm. 4.10.2. HDMI Interface The module supports HDMI 2.0 and supports 1 group of 3-lane HDMI interface, with the maximum output resolution up to 4096 2160 @ 60 fps. SG368Z_Series_Hardware_Design 58 / 113 Smart Module Series Table 24: Pins Description of HDMI Interface Pin Name Pin No. HDMI_TX2_P HDMI_TX2_M HDMI_TX1_P HDMI_TX1_M HDMI_TX0_P HDMI_TX0_M HDMI_CLK_P HDMI_CLK_M HDMI_DET HDMI_SCL HDMI_SDA HDMI_CEC 72 71 67 66 62 61 57 56 379 387 385 382 I/O AO AO AO AO AO AO AO AO DI OD OD Description Comment HDMI data 2 (+) HDMI data 2 (-) HDMI data 1 (+) HDMI data 1 (-) HDMI data 0 (+) HDMI data 0 (-) HDMI clock (+) HDMI clock (-) HDMI hot-plug detect Active high. HDMI I2C clock HDMI I2C data DIO HDMI CEC signal Figure 18: Reference Design of HDMI Interface SG368Z_Series_Hardware_Design 59 / 113 D2- HDMI_TX1_PD2_SHIELDD1+D1-D0-CLK-123456789101112131415SCLSDA171618ModuleHDMICEC_GNDVCC_5VGNDHDMI_TX1_MHDMI_TX0_PHDMI_TX0_MHDMI_CLK_PHDMI_SCLHDMI_SDAHDMI_TX2_MHDMI_TX2_PD2+D0+D0_SHIELDCLK+CLK_SHIELDCECNCESD1 FC12.2RR127KD1_SHIELDDETECTGNDGNDGNDGND1920212223HDMI_CLK_M2.2R2.2R2.2R2.2R2.2R2.2R2.2RVCC_3V31.8K1.8KVCC_5VHDMI_CECVCCIO7ESDESDESDR2R3R4R5R6R7R8R8R9R10R1127K10K10KD1D2D3D4R12R13R14R151KR16100KD5D6D7ESDESDESDESDQ1Q2Q3 Smart Module Series NOTE 1. The junction capacitance of D1, D2, D3 and D4 should not exceed 0.4 pF, and that of other ESD protection components should not exceed 1 pF. 2. VCC_3V3 and VCC_5V are provided by the terminal board. 3. D5, D6, and D7 use Schottky diodes. 4. For Q1, Q2, Q3, it is recommended to use 2SK3018. Table 25: HDMI Interface Trace Length Inside the Module (Unit: mm) Pin Name Pin No. Length Length Matching (P-M) HDMI_TX2_P HDMI_TX2_M HDMI_TX1_P HDMI_TX1_M HDMI_TX0_P HDMI_TX0_M HDMI_CLK_P HDMI_CLK_M 72 71 67 66 62 61 57 56 20.84 20.64 19.89 19.64 18.77 18.55 18.06 17.79 0.2 0.25 0.22 0.27 To ensure performance, the following principles should be complied with when designing HDMI interface:
Special attention should be paid to the pin description of HDMI interface. Different HDMI device will have varied definitions for their corresponding connectors. Ensure that the devices and the connectors are correctly connected. HDMI are high-speed signal traces, supporting maximum data rate up to 6 Gbps. The differential impedance should be controlled to 100 . Additionally, it is recommended to route the traces on the inner layer of PCB and do not cross it with other traces. To avoid crosstalk, a clearance of 4 times the trace width among HDMI data signal traces and a clearance of 5 times the trace width between HDMI data signal traces and clock signal traces are recommended. During impedance matching, do not connect HDMI signal traces to GND on different planes to ensure impedance consistency. It is recommended to select a TVS of low capacitance for ESD protection and the recommended parasitic capacitance on HDMI data and clock signals should be lower than 0.4 pF and lower than 1 pF on other HDMI signals. Route HDMI traces according to the following requirements:
a) The total trace length should not exceed 150 mm;
SG368Z_Series_Hardware_Design 60 / 113 Smart Module Series b) Control the differential impedance to 100 10 %;
c) Control intra-lane length matching within 0.3 mm. d) Control the length matching between clock signal traces and data signals traces within 12 mm. 4.10.3. LCM Interfaces Table 26: Pins Description of LCM Interfaces Pin Name Pin No. LCD1_RST 322 DSI0_CLK_N DSI0_CLK_P DSI0_LN0_N DSI0_LN0_P DSI0_LN1_N DSI0_LN1_P DSI0_LN2_N DSI0_LN2_P DSI0_LN3_N DSI0_LN3_P DSI1_CLK_N DSI1_CLK_P DSI1_LN0_N DSI1_LN0_P DSI1_LN1_N DSI1_LN1_P DSI1_LN2_N DSI1_LN2_P 37 36 47 46 42 41 32 31 27 26 33 29 43 39 38 34 28 24 I/O DO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO AO Description LCD1 reset LCD0 MIPI clock (-) LCD0 MIPI clock (+) LCD0 MIPI lane 0 data (-) LCD0 MIPI lane 0 data (+) LCD0 MIPI lane 1 data (-) LCD0 MIPI lane 1 data (+) LCD0 MIPI lane 2 data (-) LCD0 MIPI lane 2 data (+) LCD0 MIPI lane 3 data (-) LCD0 MIPI lane 3 data (+) LCD1 MIPI clock (-) LCD1 MIPI clock (+) LCD1 MIPI lane 0 data (-) LCD1 MIPI lane 0 data (+) LCD1 MIPI lane 1 data (-) LCD1 MIPI lane 1 data (+) LCD1 MIPI lane 2 data (-) LCD1 MIPI lane 2 data (+) SG368Z_Series_Hardware_Design 61 / 113 Smart Module Series DSI1_LN3_N DSI1_LN3_P 23 19 AO AO LCD1 MIPI lane 3 data (-) LCD1 MIPI lane 3 data (+) NOTE LVDS is multiplexed from DSI0. For the detailed multiplexing relationship, see document [2]. Figure 19: Reference Design of LCM Interface NOTE The power supply of VIO18 can be either external ELDO1_1V8 or LDO9_1V8 of the module. SG368Z_Series_Hardware_Design 62 / 113 DSI_CLK_PLEDANCLEDKLPTENC (SDA-TP) VIO18NC (VTP-TP) DSI_LN3_PLCD1_RST (GPIO)DSI_LN3_NDSI_LN2_PDSI_CLK_NDSI_LN2_NRESETLCD_IDNC (SCL-TP) NC (RST-TP) NC (EINT-TP) GNDVCC28GNDMIPI_TDP3MIPI_TDN3GNDMIPI_TDP2MIPI_TDN2GNDMIPI_TDP1MIPI_TDN1GNDELDO2_2V8ELDO1_1V8LCM_LED+LCM_LED-1234567891012131415161718192021222324252627MIPI_TDP0MIPI_TDN0GNDMIPI_TCPMIPI_TCN2928303456345634563456DSI_LN1_NDSI_LN1_PDSI_LN0_NDSI_LN0_P1234561112121212100nF1F1FModuleLCMFL1FL2FL3FL4FL5EMI filterC3C2C1NCGNDGNDGNDGNDADCx31323334GND Smart Module Series MIPI are high-speed signal traces. It is recommended to add common-mode chokes in series near the LCM connector to reduce electromagnetic radiation interference. It is recommended to read the LCM ID register through MIPI when compatible design with other displays is required. If several LCMs share the same IC, it is recommended that LCM factory burn an OTP register to distinguish different screens. You can also connect the LCD_ID of LCM to the ADC of the module to distinguish different screens by level detection. But note that the output voltage of LCD_ID should not exceed the voltage range of the ADC. You can design an external backlight drive circuit for LCM according to actual requirement. PWM can be used for backlight brightness adjustment. Figure 20: Reference Design of LCM Interface External Backlight Drive For more details about the principles when designing LCM interfaces, see Chapter 4.11.1. 4.11. Camera Interface Based on MIPI CSI standard, the module supports 1 camera (4-lane) or 2 cameras (2-lane + 2-lane). The maximum pixel of the camera is up to 8 MP. The video and photo quality are determined by various factors such as the camera sensor, camera lens specifications, etc. Table 27: Pins Description of Camera Interface Pin Name Pin No. CSI_CLK0_N CSI_CLK0_P 2 3 I/O AI AI Description MIPI CSI clock 0 (-) MIPI CSI clock 0 (+) SG368Z_Series_Hardware_Design 63 / 113 LCM_LED+Module4.7 FBacklight DriveLCM_LED-VDDC1PWMGNDGND10KR1 Smart Module Series CSI_CLK1_N CSI_CLK1_P CSI_LN0_N CSI_LN0_P CSI_LN1_N CSI_LN1_P CSI_LN2_N CSI_LN2_P CSI_LN3_N CSI_LN3_P CAM0_MCLK CAM0_RST CAM0_PWDN CAM1_MCLK CAM1_RST CAM1_PWDN 6 9 7 8 4 5 16 17 11 12 279 317 316 75 314 313 AI AI AI AI AI AI AI AI AI AI DO DO DO DO DO DO MIPI CSI clock 1 (-) MIPI CSI clock 1 (+) MIPI CSI lane 0 data (-) MIPI CSI lane 0 data (+) MIPI CSI lane 1 data (-) MIPI CSI lane 1 data (+) MIPI CSI lane 2 data (-) MIPI CSI lane 2 data (+) MIPI CSI lane 3 data (-) MIPI CSI lane 3 data (+) Master clock of camera 0 Reset of camera 0 Power down of camera 0 Master clock of camera 1 Reset of camera 1 Power down of camera 1 SG368Z_Series_Hardware_Design 64 / 113 Smart Module Series The following is a reference design of one-camera application:
Figure 21: Reference Design of One-Camera Application SG368Z_Series_Hardware_Design 65 / 113 CAM0_PWDNCAM0_MCLKCAM0_RSTAVDDAF_VDDDVDDDOVDD1 F1 F4.7 F4.7 FAF_VDD_2V8AVDD_2V8DVDD_1V1DOVDD_1V8 I2Cx_SDAI2Cx_SCLCSI_LN0_PCSI_LN0_NCSI_LN1_PCSI_LN1_NCSI_CLK0_PCSI_CLK0_NCSI_LN2_PCSI_LN2_NCSI_LN3_PCSI_LN3_NCAMModuleEMIEMIEMIEMIEMI Smart Module Series The following is a reference design of dual-camera application:
Figure 22: Reference Design of Dual-Camera Application NOTE 1. When the I2C addresses of the two cameras are different, they can be connected to the same I2C interface. 2. The module's ISP supports up to 8 MP camera input. 3. EMI devices should be placed near the camera. SG368Z_Series_Hardware_Design 66 / 113 CAM0_PWDNCAM0_MCLKCAM1_RSTCAM1_PWDNCAM1_MCLK4.7 F1 FCAM0_RSTEMIEMIEMIEMIAVDDAF_VDDDVDDDOVDD1 F1 F4.7 F4.7 FAF_VDD_2V8AVDD_2V8DVDD_1V1DOVDD_1V8 AVDDAF_VDDDVDDDOVDD14.7 F FI2Cx_SDAI2Cx_SCLCSI_LN0_PCSI_LN0_NCSI_LN1_PCSI_LN1_NCSI_CLK0_PCSI_CLK0_NI2Cx_SDAI2Cx_SCLCSI_LN2_PCSI_LN2_NCSI_LN3_PCSI_LN3_NCSI_CLK1_PCSI_CLK1_NEMIEMICAM1CAM0Module Smart Module Series 4. AVDD, AF_VDD, DVDD, and DOVDD must be provided by the terminal board. If the camera has power supply timing requirements, the timing control can be performed through the modules GPIO. 5. The power domain of CAM1_MCLK is 3.3 V. If it does not match with the cameras power domain, the level-shift is required. 4.11.1. MIPI Design Considerations To ensure performance, the following principles should be complied with when designing LCM and camera interfaces:
Special attention should be paid to the pin description of LCM and camera interfaces. Different video devices will have varied definitions for their corresponding connectors. Ensure that the devices and the connectors are correctly connected. MIPI are high-speed signal traces, supporting maximum data rate up to 2.5 Gbps. The differential impedance should be controlled to 100 . Additionally, it is recommended to route the traces on the inner layer of PCB and do not cross it with other traces. For the same video device, keep all the MIPI traces be of the same length. To avoid crosstalk, a clearance of 3 times the trace width is recommended among MIPI signal traces. During impedance matching, do not connect MIPI signal traces to GND on different planes to ensure impedance consistency. It is recommended to select a TVS of low capacitance for ESD protection and the recommended parasitic capacitance should be lower than 1 pF. Route MIPI traces according to the following requirements:
a) The total trace length should not exceed 150 mm;
b) Control the differential impedance to 100 10 %;
c) Control intra-lane length matching within 0.3 mm;
d) Control inter-lane length matching within 0.9 mm. Table 28: MIPI Trace Length Inside the Module (Unit: mm) Pin Name Pin No. Length Length Matching (N-P) CSI_CLK0_N CSI_CLK0_P CSI_CLK1_N CSI_CLK1_P CSI_LN0_N CSI_LN0_P CSI_LN1_N 2 3 6 9 7 8 4 19.59 19.62 14.00 14.07 17.27 17.07 18.30
-0.03
-0.07 0.2 0 SG368Z_Series_Hardware_Design 67 / 113 Smart Module Series CSI_LN1_P 5 CSI_LN2_N CSI_LN2_P 16 17 CSI_LN3_N 11 CSI_LN3_P 12 DSI0_CLK_N 37 DSI0_CLK_P 36 DSI0_LN0_N 47 DSI0_LN0_P 46 DSI0_LN1_N 42 DSI0_LN1_P 41 DSI0_LN2_N 32 DSI0_LN2_P 31 DSI0_LN3_N 27 DSI0_LN3_P 26 DSI1_CLK_N 33 DSI1_CLK_P 29 DSI1_LN0_N 43 DSI1_LN0_P 39 DSI1_LN1_N 38 DSI1_LN1_P 34 DSI1_LN2_N 28 DSI1_LN2_P 24 DSI1_LN3_N 23 DSI1_LN3_P 19 18.30 15.42 15.36 15.74 15.47 13.68 13.54 14.91 14.68 13.99 13.98 14.15 13.92 14.69 14.50 9.24 9.24 11.08 10.93 10.46 10.40 9.33 9.09 9.79 9.66 0.06 0.27 0.14 0.23 0.01 0.23 0.19 0 0.15 0.06 0.24 0.13 SG368Z_Series_Hardware_Design 68 / 113 Smart Module Series 4.12. Touch Panel Interface The module provides 1 I2C interface for connection with Touch Panel (TP) by default, and provides the corresponding power supply and interrupt pins. Table 29: Pins Description of Touch Panel Interface Pin Name Pin No. TP_RST TP_INT TP_I2C1_SCL TP_I2C1_SDA 30 35 45 40 I/O DO DI OD OD Description TP reset TP interrupt TP I2C clock TP I2C data Figure 23: Reference Design of Touch Panel Interface 4.13. PCIe Interfaces The module provides 2 PCIe interfaces. PCIe1 interface:
SG368Z_Series_Hardware_Design 69 / 113 TP_RSTTP_I2C_SCLTP_I2C_SDATP_INT1234562.2K2.2K1.0 F100 nFModuleRESET 1.8 V SCL 1.8 VSDA 1.8 V INT 1.8 V GNDVDD 2.8 V TPR2R1C1C2D1D2D3D4D5VDD_2V8VCC_PMUIO2GND Smart Module Series 1 group of 1-lane PCIe 2.0 interface Only supports RC mode PCIE1_REFCLK_P/M can support both output and input, but they output clock signals for EP device by default. PCIe1 data channel can be multiplexed into SATA2 or QSGMII/SGMII* interface. For detailed multiplexing relationship, see document [2]. PCIe2 Interface:
1 group of 2-lane PCIe 3.0 interface Supports PCIe 3.0 2 lane RC mode, compatible with PCIe 3.0 1 lane RC mode;
PCIe 3.0 1 lane RC mode uses PCIE2_TX0_P/M, PCIE2_RX0_P/M channel Supports PCIe 3.0 2 lane EP mode, compatible with PCIe 3.0 1 lane EP mode;
PCIe 3.0 1 lane EP mode uses PCIE2_TX0_P/M, PCIE2_RX0_P/M channel Supports PCIe 3.0 1 lane RC mode + PCIe 3.0 1 lane RC mode PCIE2_REFCLK_P/M only support input:
Need to provide HCSL level clock input;
Must meet the requirements for PCIe 3.0 clock. Table 30: Pins Description of PCIe Interfaces Pin Name Pin No. I/O Description Comment PCIE1_TX_P PCIE1_TX_M PCIE1_RX_P PCIE1_RX_M 90 91 86 87 AO PCIe1 transmit (+) AO PCIe1 transmit (-) AI AI PCIe1 receive (+) PCIe1 receive (-) PCIE1_REFCLK_P 81 AO PCIe1 reference clock (+) PCIE1_REFCLK_M 82 AO PCIe1 reference clock (-) PCIE1_CLKREQ_N 366 PCIE1_WAKE_N 367 DI DI PCIe1 clock request PCIe1 wake up PCIE1_RST_N 333 DO PCIe1 reset PCIE2_TX0_P PCIE2_TX0_M PCIE2_TX1_P 58 54 63 AO PCIe2 transmit 0 (+) AO PCIe2 transmit 0 (-) AO PCIe2 transmit 1 (+) SG368Z_Series_Hardware_Design 70 / 113 Smart Module Series PCIE2_TX1_M PCIE2_RX0_P PCIE2_RX0_M PCIE2_RX1_P PCIE2_RX1_M 59 68 64 73 69 AO PCIe2 transmit 1 (-) AI AI AI AI PCIe2 receive 0 (+) PCIe2 receive 0 (-) PCIe2 receive 1 (+) PCIe2 receive 1 (-) PCIE2_REFCLK_P 53 AI PCIe2 reference clock (+) PCIE2_REFCLK_M 49 AI PCIe2 reference clock (-) PCIE2_CLKREQ0_N 364 DIO PCIe2 channel 0 clock request PCIE2_WAKE0_N 363 DIO PCIe2 channel 0 wake up PCIE2_RST0_N 362 DIO PCIe2 channel 0 reset PCIE2_CLKREQ1_N 368 PCIE2_WAKE1_N 369 DI DI PCIe2 channel 1 clock request PCIe2 channel 1 wake up PCIE2_RST1_N 358 DO PCIe2 channel 1 reset If unused, connect this pin to ground. If unused, connect this pin to ground. When PCIe2 is configured in PCIe 2 lane mode, this pin is used for clock request function. When PCIe2 is configured in PCIe 2 lane mode, this pin is used for wake up function. When PCIe2 is configured in PCIe 2 lane mode, this pin is used for reset function. SG368Z_Series_Hardware_Design 71 / 113 ModuleEP1 Lane RC1 Lane EPPCIe 2.0 REFCLK Smart Module Series Figure 24: Schematic Diagram of PCIe1 Interface Figure 25: Schematic Diagram of 2 Lane RC Mode of PCIe2 Interface Figure 26: Schematic Diagram of 2 Lane EP Mode of PCIe2 Interface SG368Z_Series_Hardware_Design 72 / 113 ModulePCIe 3.0 Clock ICEP 2 Lane RC 2 Lane EP ModuleRC 2 Lane EP 2 Lane RCPCIe 3.0 REFCLK ModulePCIe 3.0 Clock IC 1 Lane RC 1 Lane EP 1 Lane EP 1 Lane RC Smart Module Series Figure 27: Schematic Diagram of 1 Lane RC + 1 Lane RC Mode of PCIe2 Interface NOTE 1. 100 nF AC coupling capacitors are connected in series on the PCIe 2.0 data traces, and 220 nF AC coupling capacitors are connected in series on the PCIe 3.0 data traces. 2. When PCIe2 uses 2 lane mode or 1 lane mode, control signals are PCIE2_CLKREQ0_N, PCIE2_WAKE0_N and PCIE2_RST0_N. 3. When PCIe2 uses 1 lane mode, channel 0 control signals are PCIE2_CLKREQ0_N, PCIE2_WAKE0_N and PCIE2_RST0_N; channel 1 control signals are PCIE2_CLKREQ1_N, PCIE2_WAKE1_N and PCIE2_RST1_N. lane mode + 1 4. The impedance of the PCIe 2.0 data traces is controlled to 90 , and the impedance of the PCIe 3.0 data traces is controlled to 85 . 5. The impedance of the PCIe reference clock traces is controlled to 100 . 6. For detailed signal connection, refer to document [3]. To ensure performance, the following principles should be complied with when designing PCIe interfaces:
PCIe are high-speed signal traces, supporting maximum data rate up to 2.5 Gbps for PCIe 2.0 and the differential impedance should be controlled to 90 . The maximum data rate is up to 4 Gbps for PCIe 3.0 and the differential impedance should be controlled to 85 . Additionally, it is recommended to route the traces on the inner layer of PCB and do not cross it with other traces. To avoid crosstalk, a clearance of 4 times the trace width among PCIe 2.0 signal traces and a clearance of 5 times the trace width among PCIe 3.0 signal traces are recommended. During impedance matching, do not connect PCIe signal traces to GND on different planes to ensure impedance consistency. Route PCIe traces according to the following requirements:
a) The total trace length should not exceed 150 mm;
b) Control the differential impedance of data traces and reference clock traces according to requirements and the deviation is at most 10 %;
c) Control intra-lane length matching within 0.3 mm. Table 31: PCIe Interface Trace Length Inside the Module (Unit: mm) Pin Name Pin No. Length Length Matching (P-M) PCIE1_TX_P PCIE1_TX_M PCIE1_RX_P PCIE1_RX_M 90 91 86 87 PCIE1_REFCLK_P 81 25.20 25.27 22.63 22.58 23.13
-0.07 0.05
-0.18 SG368Z_Series_Hardware_Design 73 / 113 Smart Module Series PCIE1_REFCLK_M 82 PCIE2_TX0_P PCIE2_TX0_M PCIE2_TX1_P PCIE2_TX1_M PCIE2_RX0_P PCIE2_RX0_M PCIE2_RX1_P PCIE2_RX1_M 58 54 63 59 68 64 73 69 PCIE2_REFCLK_P 53 PCIE2_REFCLK_M 49 4.14. RGMII Interfaces 23.31 14.43 14.62 13.07 12.87 15.30 15.51 18.28 18.13 13.41 13.24
-0.19 0.20
-0.21 0.15 0.17 The module has two built-in Gigabit MAC (GMAC0 + GMAC1) controllers, and supports up to two external 10/100/1000 Mbps network ports. The dual network port solution of the SG368Z-AP module:
RGMII0 (GMAC0) + RGMII1 (GMAC1) respectively connected to an Ethernet PHY RGMII0 (GMAC0) externally connected to an Ethernet PHY + multiplexed SGMII (GMAC1) externally connected to an Ethernet PHY RGMII1 (GMAC1) externally connected to an Ethernet PHY + multiplexed SGMII (GMAC0) externally connected to an Ethernet PHY Multiplexed QSGMII (GMAC0 + GMAC1) externally connected a 4-port Ethernet PHY (the module only supports 2 ports) The dual network port solution of the SG368Z-WF module:
Multiplexed QSGMII (GMAC0 + GMAC1) externally connected a 4-port Ethernet PHY (the module only supports 2 ports) SG368Z_Series_Hardware_Design 74 / 113 Smart Module Series Table 32: Pins Description of RGMII Interfaces Pin Name Pin No. I/O Description Comment RGMII0_RX0 RGMII0_RX1 RGMII0_RX2 183 179 174 RGMII0_RX3 169 RGMII0_RX_CTL 175 RGMII0_RX_CLK 164 DI DI DI DI DI DI RGMII0 receive data bit 0 RGMII0 receive data bit 1 RGMII0 receive data bit 2 RGMII0 receive data bit 3 RGMII0 receive control RGMII0 receive clock RGMII0_TX0 168 DO RGMII0 transmit data bit 0 RGMII0_TX1 173 DO RGMII0 transmit data bit 1 RGMII0_TX2 178 DO RGMII0 transmit data bit 2 RGMII0_TX3 182 DO RGMII0 transmit data bit 3 RGMII0_TX_CTL 172 DO RGMII0 transmit control RGMII0_TX_CLK 163 DO RGMII0 transmit clock Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. Only SG368Z-AP supports this pin. RGMII0_MDC 181 DO RGMII0_MDIO 185 OD RGMII0_ REFCLKOUT 160 DO RGMII0 management data clock Only SG368Z-AP supports this pin. RGMII0 management data input/output Only SG368Z-AP supports this pin. RGMII0 reference clock output The output frequency of reference clock is 25 MHz. RGMII0_MCLK 177 DI RGMII0 clock input RGMII1_RX0 RGMII1_RX1 RGMII1_RX2 296 294 308 DI DI DI RGMII1 receive data bit 0 RGMII1 receive data bit 1 RGMII1 receive data bit 2 The output frequency of reference clock is 125 MHz;
Only SG368Z-AP supports this pin. SG368Z_Series_Hardware_Design 75 / 113 Smart Module Series RGMII1_RX3 307 RGMII1_RX_CTL 293 RGMII1_RX_CLK 304 DI DI DI RGMII1 receive data bit 3 RGMII1 receive control RGMII1 receive clock RGMII1_TX0 305 DO RGMII1 transmit data bit 0 RGMII1_TX1 303 DO RGMII1 transmit data bit 1 RGMII1_TX2 312 DO RGMII1 transmit data bit 2 RGMII1_TX3 310 DO RGMII1 transmit data bit 3 RGMII1_TX_CTL 298 DO RGMII1 transmit control RGMII1_TX_CLK 306 DO RGMII1 transmit clock RGMII1_MDC 290 DO RGMII1_MDIO 286 OD RGMII1 management data clock RGMII1 management data input/output RGMII1_ REFCLKOUT 288 DO RGMII1 reference clock output The output frequency of reference clock is 25 MHz. RGMII1_MCLK 278 DI RGMII1 clock input The output frequency of reference clock is 125 MHz. SG368Z_Series_Hardware_Design 76 / 113 Smart Module Series Figure 28: Reference Design of RGMII Interface PHY with External Crystal SG368Z_Series_Hardware_Design 77 / 113 ModuleRGMIIx_TX0RGMIIx_TX1RGMIIx_TX2RGMIIx_TX3RGMIIx_TX_CTLRGMIIx_TX_CLKRGMIIx_RX0RGMIIx_RX1RGMIIx_RX2RGMIIx_RX3RGMIIx_RX_CTLRGMIIx_RX_CLKPHY_TX0PHY_TX1PHY_TX2PHY_TX3PHY_TX_CTLPHY_TX_CLKPHY_RX0PHY_RX1PHY_RX2PHY_RX3PHY_RX_CTLPHY_RX_CLKVCCIOxVCCIO_PHYR122RR222RR322RR422RR522RR622RR722RR822RR922RR1022RR1122RR1222RRGMIIx_MDCRGMIIx_MDIORGMIIx_MCLKRGMII0_REFCLKOUTR1422RPHY_MDCPHY_MDIO1.5KCLK_OUTR15XTAL_INXTAL_OUT/EX_CLKINTPHYRSTGPIOGPIOPHYR13R16(Option) Smart Module Series Figure 29: Reference Design of RGMII Interface PHY with Modules 25 MHz Clock NOTE 1. SG368Z-AP supports RGMII0 and RGMII1 interfaces, while SG368Z-WF only supports RGMII1 interface. RGMII0 uses GMAC0 controller and RGMII1 uses GMAC1 controller. 2. The power domain of RGMII interface is 1.8 V. Please pay attention to level matching with the voltage of the PHY. 3. RGMII_MCLK is an optional function and can be left unconnected. 4. For the design of PHY end, please refer to the reference design of the PHY chip. The designs above 5. 6. are for reference only. If you choose the multiplexed SGMII interface, the used MDC/MDIO needs to match the GMACx used, that is, if SGMII uses GMAC0, select RGMII0_MDC/RGMII0_MDIO, and if SGMII uses GMAC1, select RGMII1_MDC/RGMII1_MDIO. If you choose the multiplexed QSGMII interface, you can choose RGMII0_MDC/RGMII0_MDIO or RGMII1_MDC/RGMII1_MDIO for MDC/MDIO functions. SG368Z_Series_Hardware_Design 78 / 113 ModuleRGMIIx_TX0RGMIIx_TX1RGMIIx_TX2RGMIIx_TX3RGMIIx_TX_CTLRGMIIx_TX_CLKRGMIIx_RX0RGMIIx_RX1RGMIIx_RX2RGMIIx_RX3RGMIIx_RX_CTLRGMIIx_RX_CLKPHY_TX0PHY_TX1PHY_TX2PHY_TX3PHY_TX_CTLPHY_TX_CLKPHY_RX0PHY_RX1PHY_RX2PHY_RX3PHY_RX_CTLPHY_RX_CLKVCCIOxVCCIO_PHYR122RR222RR322RR422RR522RR622RR722RR822RR922RR1022RR1122RR1222RRGMIIx_MDCRGMIIx_MDIORGMIIx_MCLKRGMII0_REFCLKOUTR1422RPHY_MDCPHY_MDIO1.5KCLK_OUTR15XTAL_INXTAL_OUT/EX_CLKINTPHYRSTGPIOGPIOPHYR13R16(Option)R1722R Smart Module Series RGMII_TX and RGMII_RX are all high-speed signal traces. In PCB design, control the characteristic impedance of these traces as 50 , shield them and do not cross them with other traces. It is recommended to route these traces on the inner layer of PCB and keep their lengths the same. Additionally, RGMII_RX_CLK, RGMII_TX_CLK, RGMII_MCLK and RGMII_REFCLKOUT need separate ground shielding. Layout guidelines:
Control the differential impedance to 50 10 % and shield them. The trace length difference among RGMII_TX0, RGMII_TX1, RGMII_TX2, RGMII_TX3, RGMII_TX_CTL and RGMII_TX_CLK should not exceed 3 mm. The trace length difference among RGMII_RX0, RGMII_RX1, RGMII_RX2, RGMII_RX3, RGMII_RX_CTL and RGMII_RX_CLK should not exceed 3 mm. The total trace length of each RGMII signal should not exceed 125 mm. Clearance between RGMII signal traces should be greater than or equal to 2 times the trace width and the clearance between RGMII signal traces and other signal traces should be greater than or equal to 3 times the trace width. Table 33: RGMII Interface Trace Length Inside the Module (Unit: mm) Pin Name Pin No. Length (mm) RGMII0_RX0 RGMII0_RX1 RGMII0_RX2 RGMII0_RX3 RGMII0_RX_CTL RGMII0_RX_CLK RGMII0_TX0 RGMII0_TX1 RGMII0_TX2 RGMII0_TX3 RGMII0_TX_CTL RGMII0_TX_CLK 183 179 174 169 175 164 168 173 178 182 172 163 36.09 35.98 33.79 30.34 32.16 29.21 34.48 33.93 35.60 35.37 54.48 29.78 SG368Z_Series_Hardware_Design 79 / 113 Smart Module Series 296 294 308 307 293 304 305 303 312 310 298 306 RGMII1_RX0 RGMII1_RX1 RGMII1_RX2 RGMII1_RX3 RGMII1_RX_CTL RGMII1_RX_CLK RGMII1_TX0 RGMII1_TX1 RGMII1_TX2 RGMII1_TX3 RGMII1_TX_CTL RGMII1_TX_CLK 4.15. GPIO 56.84 56.26 56.87 57.30 56.84 56.02 43.33 43.90 42.52 42.21 45.08 43.29 SG368Z-WF supports up to 107 GPIOs and SG368Z-AP supports up to 128 GPIOs. The reference voltages of these GPIOs refer to the corresponding power domain. For the multiplexed GPIO, see document [2]. Table 34: Pins Description of GPIO Pin Name Pin No. I/O Description Comment GPIO0_D3 125 DIO General-purpose input/output GPIO0_D4 60 DIO General-purpose input/output GPIO0_D5 80 DIO General-purpose input/output GPIO0_D6 10 DIO General-purpose input/output GPIO0_A5 123 DIO General-purpose input/output SG368Z_Series_Hardware_Design 80 / 113 Smart Module Series GPIO0_B0 225 DIO General-purpose input/output Only SG368Z-AP supports this pin. GPIO0_B7 220 DIO General-purpose input/output Only SG368Z-AP supports this pin. GPIO0_C0 215 DIO General-purpose input/output Only SG368Z-AP supports this pin. GPIO0_C1 50 DIO General-purpose input/output Only SG368Z-AP supports this pin. GPIO0_C4 25 DIO General-purpose input/output GPIO0_C5 210 DIO General-purpose input/output Only SG368Z-AP supports this pin. GPIO0_C6 370 DIO General-purpose input/output GPIO0_C7 209 DIO General-purpose input/output Only SG368Z-AP supports this pin. GPIO1_D0 276 DIO General-purpose input/output GPIO1_D1 267 DIO General-purpose input/output GPIO1_D2 272 DIO General-purpose input/output GPIO1_D3 281 DIO General-purpose input/output GPIO1_D4 277 DIO General-purpose input/output GPIO2_C5 170 DIO General-purpose input/output Only SG368Z-AP supports this pin. GPIO3_A2 359 DIO General-purpose input/output GPIO3_A3 354 DIO General-purpose input/output GPIO3_A4 352 DIO General-purpose input/output GPIO3_A5 351 DIO General-purpose input/output GPIO3_A6 346 DIO General-purpose input/output GPIO3_A7 347 DIO General-purpose input/output GPIO3_B0 348 DIO General-purpose input/output GPIO3_B3 343 DIO General-purpose input/output GPIO3_B4 342 DIO General-purpose input/output GPIO3_B5 336 DIO General-purpose input/output GPIO3_B6 337 DIO General-purpose input/output SG368Z_Series_Hardware_Design 81 / 113 Smart Module Series GPIO3_C6 321 DIO General-purpose input/output GPIO3_D0 318 DIO General-purpose input/output GPIO3_D1 319 DIO General-purpose input/output GPIO4_B2 291 DIO General-purpose input/output GPIO4_D2 384 DIO General-purpose input/output SG368Z_Series_Hardware_Design 82 / 113 Smart Module Series 5 RF Specifications Appropriate antenna type and design should be used with matched antenna parameters according to specific application. It is required to conduct a comprehensive functional test for the RF design before mass production of terminal products. The entire content of this chapter is provided for illustration only. Analysis, evaluation and determination are still necessary when designing target products. 5.1. Wi-Fi & Bluetooth The module provides a shared antenna interface: ANT_RF for Wi-Fi and Bluetooth functions. The impedance shall be kept as 50 . You can connect external antennas such as PCB antenna, sucker antenna or ceramic antenna to the module via these interfaces to achieve Wi-Fi and Bluetooth functions. Table 35: Pins Description of Wi-Fi & Bluetooth Antenna Interface Pin Name Pin No. I/O Description Comment ANT_RF 206 AIO Wi-Fi/Bluetooth antenna interface 50 characteristic impedance Table 36: Wi-Fi & Bluetooth Frequency (Unit: MHz) Types Wi-Fi 802.11a/b/g/n/ac Bluetooth 4.2 5.1.1. Wi-Fi Overview Frequency 24022482 51805825 24022480 The module supports 2.4 GHz and 5 GHz dual-band WLAN wireless communication based on Wi-Fi 802.11a/b/g/n/ac standard protocols. The maximum data rate is up to 433.3 Mbps. The supported features are as below:
Wake-on-WLAN (WoWLAN) SG368Z_Series_Hardware_Design 83 / 113 Smart Module Series CCA on secondary through RTS/CTS handshake TCP/UDP/IP checksum offload Transmit Beamforming WPA, WPA2 AP and STA modes Wi-Fi Direct MCS 0MCS 7: HT20 and HT40 MCS 0MCS 8: VHT20 MCS 0MCS 9: VHT40 and VHT80 Table 37: Wi-Fi Transmitting Performance Bands Standards Speed Rates Output Power 802.11b 802.11b 802.11g 802.11g 1 Mbps 17 dBm 3 dB 11 Mbps 17 dBm 3 dB 6 Mbps 17 dBm 3 dB 54 Mbps 15 dBm 3 dB 2.4 GHz 802.11n @ HT20 MCS 0 17 dBm 3 dB 802.11n @ HT20 MCS 7 13.5 dBm 3 dB 802.11n @ HT40 MCS 0 17 dBm 3 dB 802.11n @ HT40 MCS 7 13.5 dBm 3 dB 802.11a 802.11a 6 Mbps 15.5 dBm 3 dB 54 Mbps 14 dBm 3 dB 802.11n @ HT20 MCS 0 15 dBm 3 dB 802.11n @ HT20 MCS 7 13 dBm 3 dB 5 GHz 802.11n @ HT40 MCS 0 15 dBm 3 dB 802.11n @ HT40 MCS 7 13 dBm 3 dB 802.11ac @ VHT20 MCS 0 15 dBm 3 dB 802.11ac @ VHT20 MCS 8 13 dBm 3 dB 802.11ac @ VHT40 MCS 0 15 dBm 3 dB SG368Z_Series_Hardware_Design 84 / 113 Smart Module Series 802.11ac @ VHT40 MCS 9 12 dBm 3 dB 802.11ac @ VHT80 MCS 0 15 dBm 3 dB 802.11ac @ VHT80 MCS 9 12 dBm 3 dB Table 38: Wi-Fi Receiving Performance Bands Standards Speed Rates Sensitivity (dBm) 802.11b 802.11b 802.11g 802.11g 2.4 GHz 1 Mbps 11 Mbps 6 Mbps 54 Mbps 802.11n @ HT20 MCS 0 802.11n @ HT20 MCS 7 802.11n @ HT40 MCS 0 802.11n @ HT40 MCS 7 802.11a 802.11a 6 Mbps 54 Mbps 802.11n @ HT20 MCS 0 802.11n @ HT20 MCS 7 802.11n @ HT40 MCS 0 5 GHz 802.11n @ HT40 MCS 7 802.11ac @ VHT20 MCS 0 802.11ac @ VHT20 MCS 8 802.11ac @ VHT40 MCS 0 802.11ac @ VHT40 MCS 9 802.11ac @ VHT80 MCS 0
-96
-86
-90
-73
-88
-69
-85
-67
-90
-73
-89
-70
-86
-67
-90
-68
--87
-63
-83 SG368Z_Series_Hardware_Design 85 / 113 Smart Module Series 802.11ac @ VHT80 MCS 9
-60
. NOTE The product complies with the IEEE specifications. 5.1.2. Bluetooth Overview The model with built-in Bluetooth function provides Bluetooth antenna interface. The module supports Bluetooth 4.2 (BR/EDR + BLE) specification, as well as GFSK, 8-DPSK, /4-DQPSK modulations. Supported characteristics include:
Enhanced Bluetooth/WLAN coexistence control to improve transmission quality in different profiles Secure Simple Pairing SCO or eSCO connection The BR/EDR channel bandwidth is 1 MHz, and can accommodate 79 channels. The BLE channel bandwidth is 2 MHz, and can accommodate 40 channels. Table 39: Bluetooth Data Rates and Versions Versions Data Rates (Mbit/s) Maximum Application Throughput 1.2 2.0 + EDR 3.0 + HS 4.0 4.2 1 3 24 24 24
> 80 kbit/s
> 80 kbit/s Refer to 3.0 + HS Refer to 4.0 LE Refer to 4.2 LE Referenced specifications are listed below:
Bluetooth Radio Frequency TSS and TP Specification 1.2/2.0/2.0 + EDR/2.1/2.1 + EDR/3.0/3.0 + HS, August 6, 2009 Bluetooth Low Energy RF PHY Test Specification, RF-PHY.TS/4.0.0, December 15, 2009 Bluetooth Low Energy RF PHY Test Specifications, Core_v4.2, December 12, 2014 SG368Z_Series_Hardware_Design 86 / 113 Smart Module Series Table 40: Bluetooth Transmitting and Receiving Performance (Unit: dBm) Transmitting Performance Packet types DH5 Transmitting power 6 3 Receiving Performance Packet types DH5 Receiving sensitivity
-89 5.1.3. Reference Design 2-DH5 4.5 3 2-DH5
-89 3-DH5 4.5 3 3-DH5
-83 A reference design of Wi-Fi & Bluetooth antenna interface is shown as below. C1 and C2 are not mounted by default. Only a 0 resistor is mounted on R1. Figure 30: Reference Design of Wi-Fi & Bluetooth Antenna 5.2. RF Routing Guidelines When designing PCB, characteristic impedance of all RF traces should be controlled to 50 . Generally, the impedance of RF traces is determined by materials dielectric constant, trace width (W), space between RF traces and grounds (S) and height from the reference ground to the signal layer (H). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB structures when characteristic impedance of RF traces is controlled to 50 . SG368Z_Series_Hardware_Design 87 / 113 ANT_RFR1 0RC1ModuleNMC2NM Smart Module Series Figure 31: Microstrip Design on a 2-layer PCB Figure 32: Coplanar Waveguide Design on a 2-layer PCB Figure 33: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) SG368Z_Series_Hardware_Design 88 / 113 Smart Module Series Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure better RF performance and reliability, the following conditions should be complied with in RF layout design:
Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 . GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground. Clearance between RF pins and RF connector should be as short as possible, and all right-angle
(90) traces should be changed to the ones with the angle of 135. There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, ground vias around RF traces and the reference ground can improve RF performance. The clearance between ground vias and RF traces should be at least twice the width of RF signal traces (2 W). Keep RF traces away from interference sources, and avoid intersection and paralleling between any traces on adjacent layers. For more details about RF layout, see document [4]. 5.3. Requirements for Antenna Design Table 41: Requirements for Antenna Design Antenna Types Wi-Fi & Bluetooth Requirements VSWR: 2 Gain: 1 dBi Max input power: 50 W Input impedance: 50 Vertical polarization SG368Z_Series_Hardware_Design 89 / 113 Smart Module Series Cable insertion loss: < 1 dB 5.4. RF Connector Recommendation If the RF connector is used for antenna connection, it is recommended to use U.FL-R-SMT receptacle provided by Hirose. Figure 35: Dimensions of the Receptacle (Unit: mm) U.FL-LP series mated plugs listed in the following figure can be used to match the U.FL-R-SMT. Figure 36: Specifications of Mated Plugs (Unit: mm) SG368Z_Series_Hardware_Design 90 / 113 Smart Module Series The following figure describes the space factor of the mated connector. Figure 37: Space Factor of the Mated Connectors (Unit: mm) For more details, visit http://www.hirose.com. SG368Z_Series_Hardware_Design 91 / 113 Smart Module Series 6 Electrical Characteristics and Reliability 6.1. Absolute Maximum Ratings Table 42: Absolute Maximum Ratings Parameters Voltage at VBAT Voltage at USB_VBUS Voltage at digital pins Min.
-0.3
-0.3
-0.3 6.2. Power Supply Ratings Table 43: Modules Power Supply Ratings Max. 3.55 3.3 VCCIOx + 0.3 Units V V V Parameters Descriptions Conditions Min. Typ. Max. Units VBAT Power supply for the module The actual input voltage must be within this range 3.3 3.4 3.5 V IVBAT Peak supply current TBD
TBD A SG368Z_Series_Hardware_Design 92 / 113 Smart Module Series 6.3. Power Consumption Table 44: SG368Z-WF Power Consumption Modes OFF state Conditions Power off Standby state Screen off Wi-Fi 11a Tx Wi-Fi 11b Tx Wi-Fi 11g Tx Wi-Fi 11n Tx Wi-Fi 11n Tx Wi-Fi 11ac Tx
@ 6 Mbps
@ 54 Mbps
@ 1 Mbps
@ 11 Mbps
@ 6 Mbps
@ 54 Mbps
@ 7.2 Mbps 20 MHz
@ 72.2 Mbps 20 MHz
@ 15 Mbps 40 MHz
@ 150 Mbps 40 MHz
@ 7.2 Mbps 20 MHz
@ 86.7 Mbps 20 MHz
@ 15 Mbps 40 MHz
@ 200 Mbps 40 MHz
@ 32.5 Mbps 80 MHz
@ 433.3 Mbps 80 MHz Wi-Fi 11a Rx
@ 54 Mbps Wi-Fi 11b Rx
@ 11 Mbps Wi-Fi 11g Rx
@ 54 Mbps Wi-Fi 11n Rx
@ 200 Mbps 40 MHz Typ. Units 100 5.5 380 370 445 380 443 369 375 355 373 364 395 438 391 429 392 432 TBD TBD TBD TBD A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA SG368Z_Series_Hardware_Design 93 / 113 Smart Module Series Wi-Fi 11ac Rx
@ 433.3 Mbps 80 MHz Bluetooth Tx Channel 0 Bluetooth Tx Channel 38 Bluetooth Tx Channel 78 Bluetooth Rx Channel 38
Table 45: SG368Z-AP Power Consumption Modes OFF state Conditions Power off Standby state Screen off NOTE TBD 322 324 326 TBD Typ. 100 5.5 mA mA mA mA mA Units A mA The power consumption data above is for reference only, which may vary among different modules. For detailed information, contact Quectel Technical Support for the power consumption test report of the specific module. 6.4. Digital I/O Characteristics Table 46: 1.8 V VCCIO I/O Characteristics (Unit: V) Parameters Descriptions Min. Max. VIH VIL VOH VOL High-level input voltage 0.65 VCCIO VCCIO + 0.3 Low-level input voltage
-0.3 0.35 VCCIO High-level output voltage 1.4 VCCIO + 0.3 Low-level output voltage
-0.3 0.4 SG368Z_Series_Hardware_Design 94 / 113 Smart Module Series Table 47: PMUIO0 I/O Characteristics (Unit: V) Parameter Description Min. Max. VIH VIL VOH VOL High-level input voltage 0.65 PMUIO0 PMUIO0 + 0.3 Low-level input voltage
-0.3 0.35 PMUIO0 High-level output voltage 1.4 PMUIO0 + 0.3 Low-level output voltage
-0.3 0.4 Table 48: PMUIO1 I/O Characteristics (Unit: V) Parameter Description VIH VIL VOH VOL High-level input voltage Low-level input voltage Min. 2.0
-0.3 Max. PMUIO1 + 0.3 0.8 High-level output voltage 2.4 PMUIO1 + 0.3 Low-level output voltage
-0.3 0.4 Table 49: PMUIO2 I/O Characteristics (Unit: V) Parameter Description Min. Max. VIH VIL VOH VOL High-level input voltage 0.65 PMUIO2 PMUIO2 + 0.3 Low-level input voltage
-0.3 0.35 PMUIO2 High-level output voltage 1.4 PMUIO2 + 0.3 Low-level output voltage
-0.3 0.4 Table 50: SD Card High-voltage I/O Characteristics (Unit: V) Parameter Description VIH VIL High-level input voltage Low-level input voltage Min. 2.0
-0.3 Max. VCCIO3 + 0.3 0.8 SG368Z_Series_Hardware_Design 95 / 113 Smart Module Series VOH VOL High-level output voltage 2.4 VCCIO3 + 0.3 Low-level output voltage
-0.3 0.4 Table 51: SD Card Low-voltage I/O Characteristics (Unit: V) Parameter Description Min. Max. VIH VIL VOH VOL High-level input voltage 0.65 VCCIO3 VCCIO3 + 0.3 Low-level input voltage
-0.3 0.35 VCCIO3 High-level output voltage 1.4 VCCIO3 + 0.3 Low-level output voltage
-0.3 0.4 6.5. ESD Protection Static electricity occurs naturally and it may damage the module. Therefore, applying proper ESD countermeasures and handling methods is imperative. For example, wear anti-static gloves during the development, production, assembly and testing of the module; add ESD protection components to the ESD sensitive interfaces and points in the product design. Table 52: ESD Characteristics (Temperature: 2530 C, Humidity: 40 5 %, Unit: kV) Test Points Contact Discharge Air Discharge VBAT and GND Antenna interface Other interfaces TBD 4 TBD TBD 8 TBD SG368Z_Series_Hardware_Design 96 / 113 Smart Module Series 6.6. Operating and Storage Temperatures Table 53: Operating and Storage Temperatures (Unit: C) Parameters Min. Industrial grade Operating Temperature 2
-40 Commercial grade Operating Temperature 2
-10 Storage Temperature
-40 Typ.
+25
+25
Max.
+85
+75
+90 2 Within the operating temperature range, the module meets IEEE specifications. SG368Z_Series_Hardware_Design 97 / 113 Smart Module Series 7 Mechanical Information This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are 0.2 mm unless otherwise specified. 7.1. Mechanical Dimensions Figure 38: Top and Side Dimensions SG368Z_Series_Hardware_Design 98 / 113 Smart Module Series Figure 39: Bottom Dimensions NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard. SG368Z_Series_Hardware_Design 99 / 113 Smart Module Series 7.2. Recommended Footprint Figure 40: Recommended Footprint
. NOTE Keep at least 3 mm between the module and other components on the motherboard to improve soldering quality and maintenance convenience. SG368Z_Series_Hardware_Design 100 / 113 Smart Module Series 7.3. Top and Bottom Views Figure 41: Top & Bottom Views of the Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. SG368Z_Series_Hardware_Design 101 / 113 Smart Module Series 8 Storage, Manufacturing & Packaging 8.1. Storage Conditions The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended storage condition: the temperature should be 23 5 C and the relative humidity should be 3560 %. 2. Shelf life (in a vacuum-sealed packaging): 12 months in recommended storage condition. 3. Floor life: 168 hours 3 in a factory where the temperature is 23 5 C and relative humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g., a dry cabinet). 4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under the following circumstances:
The module is not stored in recommended storage condition;
Violation of the third requirement mentioned above;
Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;
Before module repairing. 5. If needed, the pre-baking should follow the requirements below:
The module should be baked for 8 hours at 120 5 C;
The module must be soldered to PCB within 24 hours after the baking, otherwise it should be put in a dry environment such as in a dry cabinet. 3 This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to, or are not sure to conform to IPC/JEDEC J-STD-033. Do not unpack the modules in large quantities until they are ready for soldering. SG368Z_Series_Hardware_Design 102 / 113 Smart Module Series NOTE 1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to the air is forbidden. 2. Take out the module from the package and put it on high-temperature-resistant fixtures before baking. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure. 3. Pay attention to ESD protection, such as wearing anti-static gloves, when touching the modules. 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. Apply proper force on the squeegee to produce a clean stencil surface on a single pass. To guarantee module soldering quality, the thickness of stencil for the module is recommended to be TBD mm. For more details, see document [5]. The recommended peak reflow temperature should be 235246 C, with 246 C as the absolute maximum reflow temperature. To avoid damage to the module caused by repeated heating, it is recommended that the module should be mounted only after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. Figure 42: Recommended Reflow Soldering Thermal Profile SG368Z_Series_Hardware_Design 103 / 113 Temp. (C)Reflow ZoneSoak Zone246200217235CDBA150100 Ramp-to-soak slope:02 C/s Cool-down slope:-10 C/s Ramp-up slope:01 C/s Smart Module Series Table 54: Recommended Thermal Profile Parameters Factor Soak Zone Recommended Value Ramp-to-soak slope 02 C/s Soak time (between A and B: 150 C and 200 C) 70120 s Reflow Zone 217235 C ramp-up slope Reflow time (D: over 217C) Max temperature 235217 C cool-down slope Reflow Cycle Max reflow cycle NOTE 01 C/s 4065 s 235246 C
-10 C/s 1 1. The above profile parameter requirements are for the measured temperature of the solder joints. Both the hottest and coldest spots of solder joints on the PCB should meet the above requirements. 2. Due to the large-size form factor, to avoid excessive temperature change, which may cause excessive thermal deformation of the metal shielding frame and cover, it is recommended to reduce the ramp-up and cool-down slopes in the liquid phase of the solder paste. If possible, please choose a reflow oven with more than 10 temperature zones during production so that there are more temperature zones to set up to meet the optimal temperature curve. If a conformal coating is necessary for the module, do NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module. 3. 4. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the module. 5. Due to the complexity of the SMT process, please contact Quectel Technical Support in advance for any situation that you are not sure about, or any process (e.g. selective soldering, ultrasonic soldering) that is not mentioned in document [5]. SG368Z_Series_Hardware_Design 104 / 113 Smart Module Series 8.3. Packaging Specification This chapter describes only the key parameters and process of packaging. All figures below are for reference only. The appearance and structure of the packaging materials are subject to the actual delivery. The module adopts carrier tape packaging and details are as follow:
8.3.1. Carrier Tape Dimension details are as follow:
Figure 43: Carrier Tape Dimension Drawing Table 55: Carrier Tape Dimension Table (Unit: mm) W 72 P 56 T A0 B0 K0 K1 F E 0.4 42.6 46.6 4.25 5.25 34.2 1.75 SG368Z_Series_Hardware_Design 105 / 113 Smart Module Series 8.3.2. Plastic Reel Figure 44: Plastic Reel Dimension Drawing Table 56: Plastic Reel Dimension Table (Unit: mm) D1 380 D2 180 W 72.5 8.3.3. Mounting Direction Figure 45: Mounting Direction SG368Z_Series_Hardware_Design 106 / 113 Smart Module Series 8.3.4. Packaging Process Place the packaged plastic reel, 1 humidity indicator card and 1 desiccant bag into a vacuum bag, vacuumize it. Place the module into the carrier tape and use the cover tape to cover it; then wind the heat-sealed carrier tape to the plastic reel and use the protective tape for protection. 1 plastic reel can load 200 modules. Place the vacuum-packed plastic reel into the pizza box. Put 4 packaged pizza boxes into 1 carton box and seal it. 1 carton box can pack 800 modules. Figure 46: Packaging Process SG368Z_Series_Hardware_Design 107 / 113 Smart Module Series 9 Appendix References Table 57: Related Documents Document Name
[1] Quectel_SG368Z_Series_EVB_User_Guide
[2] Quectel_SG368Z_Series_GPIO_Configuration
[3] Quectel_SG368Z_Series_Reference_Design
[4] Quectel_RF_Layout_Application_Note
[5] Quectel_Module_SMT_Application_Note Table 58: Terms and Abbreviations Abbreviation Description AAC ABD AC AP ARM BLE bps BR CC CEC CSI Advanced Audio Coding Android Debug Bridge Alternating Current Application Processor Advanced RISC Machine Bluetooth Low Energy Bytes per second Basic Rate Configuration Channel Consumer Electronic Control Camera Serial Interface SG368Z_Series_Hardware_Design 108 / 113 Smart Module Series CTS DFOTA DPSK DQPSK DSI DVR eDP EDR EFR EMI eMMC EP eSCO ESD ESR EVB FIFO FR GFSK GMAC GND GPU HCSL HDMI HR Clear To Send Delta Firmware Upgrade Over-The-Air Differential Phase Shift Keying Differential Quadrature Phase Shift Keying Display Serial Interface Digital Video Recorder Embedded DisplayPort Enhanced Data Rate Enhanced Full Rate Electromagnetic Interference Embedded Multimedia Card End Point Extended Synchronous Connection Oriented Electrostatic Discharge Equivalent Series Resistance Evaluation Board First In First Out Full Rate Gaussian Frequency Shift Keying Gigabit Media Access Controller Ground Graphics Processing Unit High-speed Current Steering Logic High Definition Multimedia Interface Half Rate SG368Z_Series_Hardware_Design 109 / 113 Smart Module Series HS HT I2C I2S IEEE IP ISP LCM LDO LGA High Speed High Throughput Inter-Integrated Circuit Inter-IC Sound Institute of Electrical and Electronics Engineers Internet Protocol Image Signal Processor Liquid Crystal Monitor Low Dropout Regulator Land Grid Array LPDDR LVDS Low-Power Double Data Rate Low-Voltage Differential Signaling M2M MAC MCS MIPI MP MP3 MSL NAS NVR OTG OTP PC PCB Machine to Machine Media Access Control Modulation and Coding Scheme Mobile Industry Processor Interface Megapixel Moving Picture Experts Group Audio Layer III Moisture Sensitivity Levels Non-Access Stratum Network Video Recorder On-The-Go One Time Programmable Personal Computer Printed Circuit Board SG368Z_Series_Hardware_Design 110 / 113 Smart Module Series Peripheral Component Interconnect Express Pulse Code Modulation Pulse Density Modulation Physical Layer Root Complex Radio Frequency Red Green Blue Reduced Gigabit Media Independent Interface Restriction of Hazardous Substances Request To Send Serial Advanced Technology Attachment Synchronous Connection Oriented Secure Digital Secure Digital Input and Output Card Serial Gigabit Media Independent Interface Surface Mount Technology Station Transmission Control Protocol Time-Division Multiplexing Touch Panel Transient Voltage Suppressor Universal Asynchronous Receiver/Transmitter User Datagram Protocol Universal Serial Bus
(Universal) Subscriber Identity Module PCIe PCM PDM PHY RC RF RGB RGMII RoHS RTS SATA SCO SD SDIO SGMII SMT STA TCP TDM TP TVS UART UDP USB
(U)SIM SG368Z_Series_Hardware_Design 111 / 113 Smart Module Series VBAT VHT Vmax Vmin Vnom VSWR WLAN WPA TRX Tx UART UHB UL UMTS URC USB Voltage at Battery (Pin) Very High Throughput Maximum Voltage Minimum Voltage Nominal Voltage Voltage Standing Wave Ratio Wireless Local Area Network Wi-Fi Protected Access Transmit & Receive Transmit Universal Asynchronous Receiver/Transmitter Ultra High Band Uplink Universal Mobile Telecommunications System Unsolicited Result Code Universal Serial Bus
(U)SIM Universal Subscriber Identity Module VBAT Vmax Vnom Vmin VIHmax VIHmin VILmax VILmin Voltage at Battery (Pin) Maximum Voltage Nominal Voltage Minimum Voltage Maximum High-level Input Voltage Minimum High-level Input Voltage Maximum Low-level Input Voltage Minimum Low-level Input Voltage SG368Z_Series_Hardware_Design 112 / 113 Smart Module Series VImax VImin VOHmax VOHmin VOLmax VOLmin VSWR Absolute Maximum Input Voltage Absolute Minimum Input Voltage Maximum High-level Output Voltage Minimum High-level Output Voltage Maximum Low-level Output Voltage Minimum Low-level Output Voltage Voltage Standing Wave Ratio WCDMA Wideband Code Division Multiple Access WLAN WWAN Wireless Local Area Network Wireless Wide Area Network Modifications:
Any changes or modifications not expressly approved by Quectel or the party responsible for compliance could void the users authority to operate the equipment and invalidate the regulatory approval. Host manufacturer must follow KDB Publication 996369 D04 Modulen Integration Guide. Host manufacturer is responsible for regression tests to show compliance to the applicable standards due to the following actions:
1.any modification done to the module. 2.Integration of the module into a host device Host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. Final host product is required to show compliance to Part 15 Subpart B with the modular transmitter installed Product Marketing NameQuectel SG368Z-WF FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met:
1. This Modular Approval is limited to OEM installation for mobile and fixed applications only. The antenna installation and operating configurations of this transmitter, including any applicable source-based timeaveraging duty factor, antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements of 2.1091. 2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the users body and must not transmit simultaneously with any other antenna or transmitter. SG368Z_Series_Hardware_Design 113 / 113 Smart Module Series 3. A label with the following statements must be attached to the host end product:
This device contains FCC ID: XMR2023SG368ZWF FCC/ISED Regulations restrict operation of this device to Indoor Use Only 4. Antenna Requirements:
The following antennae were approved with the modules:
Operating Band Frequency Antenna Type Antenna P/N Antenna Gain (dBi)
(MHz) Bluetooth 2400~2483.5 2.4G WiFi 5G WiFi 5150~5850 Dipole YE0038BA
-0.5 dBi
-0.5 dBi 5150~5250 MHz:2.0 dBi 5250~5350 MHz:2.0 dBi 5470~5725 MHz:3.2 dBi 5725~5850 MHz:3.3 dBi The product is provided with an approved antenna. Use only supplied or approved antenna by Quectel. Any changes or modifications to the Antenna may void the regulatory approvals obtained for the product. Host device must comply with FCC Part 15 antenna requirements The OEM must design the host so that the antenna will be installed as an integrated antenna for the host containing the SG368Z-WF and the end user shall not be able to access, remove or replace the antenna. 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093 If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations. For this device, OEM integrators must be provided with labeling instructions of finished products. Please refer to KDB784748 D01 v07, section 8. Page 6/7 last two paragraphs:
A certified modular has the option to use a permanently affixed label, or an electronic label. For a permanently affixed label, the module must be labeled with an FCC ID - Section 2.926 (see 2.2 Certification (labeling requirements) above). The OEM manual must provide clear instructions explaining to the OEM the labeling requirements, options and OEM user manual instructions that are required (see next paragraph). For a host using a certified modular with a standard fixed label, if (1) the modules FCC ID is not visible when installed in the host, or (2) if the host is marketed so that end users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible;
then an additional permanent label referring to the enclosed module: Contains Transmitter Module FCC ID: XMR2023SG368ZWF or Contains FCC ID: XMR2023SG368ZWF must be used. The host OEM user manual must also contain clear instructions on how end users can find and/or access the module SG368Z_Series_Hardware_Design 114 / 113 Smart Module Series and the FCC ID. The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The users manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. In cases where the manual is provided only in a form other than paper, such as on a computer disk or over the Internet, the information required by this section may be included in the manual in that alternative form, provided the user can reasonably be expected to have the capability to access information in that form. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the manufacturer could void the users authority to operate the equipment. To ensure compliance with all non-transmitter functions the host manufacturer is responsible for ensuring compliance with the module(s) installed and fully operational. For example, if a host was previously authorized as an unintentional radiator under the Suppliers Declaration of Conformity procedure without a transmitter certified module and a module is added, the host manufacturer is responsible for ensuring that the after the module is installed and operational the host continues to be compliant with the Part 15B unintentional radiator requirements. Manual Information To the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. IC Statement IRSS-GEN
"This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device." or "Le prsent appareil est conforme aux CNR dIndustrie Canada applicables aux appareils radio exempts de licence. Lexploitation est autorise aux deux conditions suivantes :
1) lappareil ne doit pas produire de brouillage; 2) lutilisateur de lappareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible den compromettre le fonctionnement."
Dclaration sur l'exposition aux rayonnements RF L'autre utilis pour l'metteur doit tre install pour fournir une distance de sparation d'au moins 20 cm de toutes les personnes et ne doit pas tre colocalis ou fonctionner conjointement avec une autre antenne ou un autre metteur. The host product shall be properly labeled to identify the modules within the host product. The Innovation, Science and Economic Development Canada certification label of a module shall be clearly visible at all times when installed in the host product; otherwise, the host product must be labeled to display the Innovation, Science and Economic Development Canada certification number for the module, preceded by the word Contains or similar wording expressing the same meaning, as follows:
Contains IC: 10224A-23SG368ZWF or where: 10224A-23SG368ZWF is the modules certification SG368Z_Series_Hardware_Design 115 / 113 Smart Module Series number. Le produit hte doit tre correctement tiquet pour identifier les modules dans le produit hte. L'tiquette de certification d'Innovation, Sciences et Dveloppement conomique Canada d'un module doit tre clairement visible en tout temps lorsqu'il est installdans le produit hte; sinon, le produit hte doit porter une tiquette indiquant le numro de certification d'Innovation, Sciences et Dveloppement conomique Canada pour le module, prcd du mot Contient ou d'un libell semblable exprimant la mme signification, comme suit:
"Contient IC: 10224A-23SG368ZWF" ou "o: 10224A-23SG368ZWF est le numro de certification du module". i. the device for operation in the band 51505250 MHz is only for indoor use to reduce the potential for harmful interference to co-channel mobile satellite systems;
ii. for devices with detachable antenna(s), the maximum antenna gain permitted for devices in the bands 5250-5350 MHz and 5470-5725 MHz shall be such that the equipment still complies with the e.i.r.p. limit;
iii. for devices with detachable antenna(s), the maximum antenna gain permitted for devices in the band 5725-5850 MHz shall be such that the equipment still complies with the e.i.r.p. limits as appropriate;
iv. Omnidirectional antenna is recommended SG368Z_Series_Hardware_Design 116 / 113
1 2 3 | Internal Photos | Internal Photos | 441.38 KiB | July 16 2023 / January 13 2024 | delayed release |
1 2 3 | External Photo | External Photos | 639.77 KiB | July 16 2023 / January 13 2024 | delayed release |
1 2 3 | Test Setup Photos | Test Setup Photos | 4.67 MiB | July 16 2023 / January 13 2024 | delayed release |
frequency | equipment class | purpose | ||
---|---|---|---|---|
1 | 2023-07-16 | 5745 ~ 5825 | NII - Unlicensed National Information Infrastructure TX | Original Equipment |
2 | 2412 ~ 2462 | DTS - Digital Transmission System | ||
3 | 2402 ~ 2480 | DSS - Part 15 Spread Spectrum Transmitter |
app s | Applicant Information | |||||
---|---|---|---|---|---|---|
1 2 3 | Effective |
2023-07-16
|
||||
1 2 3 | Applicant's complete, legal business name |
Quectel Wireless Solutions Company Limited
|
||||
1 2 3 | FCC Registration Number (FRN) |
0018988279
|
||||
1 2 3 | Physical Address |
Building 5, Shanghai Business Park PhaseIII
|
||||
1 2 3 |
Shanghai, N/A 200233
|
|||||
1 2 3 |
China
|
|||||
app s | TCB Information | |||||
1 2 3 | TCB Application Email Address |
T******@timcoengr.com
|
||||
1 2 3 | TCB Scope |
A4: UNII devices & low power transmitters using spread spectrum techniques
|
||||
app s | FCC ID | |||||
1 2 3 | Grantee Code |
XMR
|
||||
1 2 3 | Equipment Product Code |
2023SG368ZWF
|
||||
app s | Person at the applicant's address to receive grant or for contact | |||||
1 2 3 | Name |
J******** H********
|
||||
1 2 3 | Telephone Number |
+8602******** Extension:
|
||||
1 2 3 | Fax Number |
+8621********
|
||||
1 2 3 |
j******@quectel.com
|
|||||
app s | Technical Contact | |||||
n/a | ||||||
app s | Non Technical Contact | |||||
n/a | ||||||
app s | Confidentiality (long or short term) | |||||
1 2 3 | Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 2 3 | Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?: | Yes | ||||
1 2 3 | If so, specify the short-term confidentiality release date (MM/DD/YYYY format) | 01/13/2024 | ||||
if no date is supplied, the release date will be set to 45 calendar days past the date of grant. | ||||||
app s | Cognitive Radio & Software Defined Radio, Class, etc | |||||
1 2 3 | Is this application for software defined/cognitive radio authorization? | No | ||||
1 2 3 | Equipment Class | NII - Unlicensed National Information Infrastructure TX | ||||
1 2 3 | DTS - Digital Transmission System | |||||
1 2 3 | DSS - Part 15 Spread Spectrum Transmitter | |||||
1 2 3 | Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant) | Smart Module | ||||
1 2 3 | Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application? | No | ||||
1 2 3 | Modular Equipment Type | Single Modular Approval | ||||
1 2 3 | Purpose / Application is for | Original Equipment | ||||
1 2 3 | Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization? | Yes | ||||
1 2 3 | Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization? | No | ||||
1 2 3 | Grant Comments | Output power listed is conducted. Single Modular Approval for mobile RF Exposure condition. The module antenna(s) must be installed to meet the RF exposure compliance separation distance of 20 cm and any additional testing and authorization process as required. Co-location of this module with other transmitters that operate simultaneously are required to be evaluated using the FCC multi-transmitter procedures. Approved for OEM integration only. The grantee must provide OEM integrators, or end-users if marketed directly to end-users, with installation and operating instructions for satisfying FCC multi-transmitter product guidelines. This grant is valid only when the device is sold to OEM integrators and the OEM integrators are instructed to ensure that the end-user has no manual instructions to remove or install the device. This device supports 20, 40 and 80 MHz modes. This module can only be used with a host antenna circuit trace layout design in strict compliance with the OEM instructions provided. | ||||
1 2 3 | Output power listed is conducted. Single Modular Approval for mobile RF Exposure condition. The module antenna(s) must be installed to meet the RF exposure compliance separation distance of 20 cm and any additional testing and authorization process as required. Co-location of this module with other transmitters that operate simultaneously are required to be evaluated using the FCC multi-transmitter procedures. Approved for OEM integration only. The grantee must provide OEM integrators, or end-users if marketed directly to end-users, with installation and operating instructions for satisfying FCC multi-transmitter product guidelines. This grant is valid only when the device is sold to OEM integrators and the OEM integrators are instructed to ensure that the end-user has no manual instructions to remove or install the device. This device supports 20 and 40 MHz modes. This module can only be used with a host antenna circuit trace layout design in strict compliance with the OEM instructions provided. | |||||
1 2 3 | Output power listed is conducted. Single Modular Approval for mobile RF Exposure condition. The module antenna(s) must be installed to meet the RF exposure compliance separation distance of 20 cm and any additional testing and authorization process as required. Co-location of this module with other transmitters that operate simultaneously are required to be evaluated using the FCC multi-transmitter procedures. Approved for OEM integration only. The grantee must provide OEM integrators, or end-users if marketed directly to end-users, with installation and operating instructions for satisfying FCC multi-transmitter product guidelines. This grant is valid only when the device is sold to OEM integrators and the OEM integrators are instructed to ensure that the end-user has no manual instructions to remove or install the device. This module can only be used with a host antenna circuit trace layout design in strict compliance with the OEM instructions provided. | |||||
1 2 3 | Is there an equipment authorization waiver associated with this application? | No | ||||
1 2 3 | If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded? | No | ||||
app s | Test Firm Name and Contact Information | |||||
1 2 3 | Firm Name |
SGS-CSTC Standards Technical Services Co., Ltd. Sh
|
||||
1 2 3 | Name |
K****** X****
|
||||
1 2 3 | Telephone Number |
+86 (********
|
||||
1 2 3 |
K******@sgs.com
|
|||||
Equipment Specifications | |||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
1 | 1 | 15E | CC | 5180 | 5240 | 0.039 | |||||||||||||||||||||||||||||||||||
1 | 2 | 15E | CC | 5260 | 5320 | 0.048 | |||||||||||||||||||||||||||||||||||
1 | 3 | 15E | CC | 5500 | 5700 | 0.042 | |||||||||||||||||||||||||||||||||||
1 | 4 | 15E | CC | 5745 | 5825 | 0.033 | |||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
2 | 1 | 15C | CC | 2402 | 2480 | 0.001 | |||||||||||||||||||||||||||||||||||
2 | 2 | 15C | CC | 2412 | 2462 | 0.24 | |||||||||||||||||||||||||||||||||||
Line | Rule Parts | Grant Notes | Lower Frequency | Upper Frequency | Power Output | Tolerance | Emission Designator | Microprocessor Number | |||||||||||||||||||||||||||||||||
3 | 1 | 15C | CC | 2402.00000000 | 2480.00000000 | 0.0050000 |
some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details
This product uses the FCC Data API but is not endorsed or certified by the FCC