FCC ID: XMR2023SG560DWF Smart Module

 

SG560D Series Hardware Design Smart Module Series Version: 1.1 Date: 2023-02-10 Status: Released Smart Module Series At Quectel, our aim is to provide timely and comprehensive services to our customers. If you require any assistance, please contact our headquarters:

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local offices. For more information, please visit:

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http://www.quectel.com/support/technical.htm. Or email us at: support@quectel.com. Legal Notices We offer information as a service to you. The provided information is based on your requirements and we make every effort to ensure its quality. You agree that you are responsible for using independent analysis and evaluation in designing intended products, and we provide reference designs for illustrative purposes only. Before using any hardware, software or service guided by this document, please read this notice carefully. Even though we employ commercially reasonable efforts to provide the best possible experience, you hereby acknowledge and agree that this document and related services hereunder are provided to you on an as available basis. We may revise or restate this document from time to time at our sole discretion without any prior notice to you. Use and Disclosure Restrictions License Agreements Documents and information provided by us shall be kept confidential, unless specific permission is granted. They shall not be accessed or used for any purpose except as expressly provided herein. Copyright Our and third-party products hereunder may contain copyrighted material. Such copyrighted material shall not be copied, reproduced, distributed, merged, published, translated, or modified without prior written consent. We and the third party have exclusive rights over copyrighted material. No license shall be granted or conveyed under any patents, copyrights, trademarks, or service mark rights. To avoid ambiguities, purchasing in any form cannot be deemed as granting a license other than the normal non-exclusive, royalty-free license to use the material. We reserve the right to take legal action for noncompliance with abovementioned requirements, unauthorized use, or other illegal or malicious use of the material. SG560D_Series_Hardware_Design 1 / 133 Smart Module Series Trademarks Except as otherwise set forth herein, nothing in this document shall be construed as conferring any rights to use any trademark, trade name or name, abbreviation, or counterfeit product thereof owned by Quectel or any third party in advertising, publicity, or other aspects. Third-Party Rights This document may refer to hardware, software and/or documentation owned by one or more third parties

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Privacy Policy To implement module functionality, certain device data are uploaded to Quectels or third-partys servers, including carriers, chipset suppliers or customer-designated servers. Quectel, strictly abiding by the relevant laws and regulations, shall retain, use, disclose or otherwise process relevant data for the purpose of performing the service only or as permitted by applicable laws. Before data interaction with third parties, please be informed of their privacy and data security policy. Disclaimer a) We acknowledge no liability for any injury or damage arising from the reliance upon the information. b) We shall bear no liability resulting from any inaccuracies or omissions, or from the use of the information contained herein. c) While we have made every effort to ensure that the functions and features under development are free from errors, it is possible that they could contain errors, inaccuracies, and omissions. Unless otherwise provided by valid agreement, we make no warranties of any kind, either implied or express, and exclude all liability for any loss or damage suffered in connection with the use of features and functions under development, to the maximum extent permitted by law, regardless of whether such loss or damage may have been foreseeable. d) We are not responsible for the accessibility, safety, accuracy, availability, legality, or completeness of information, advertising, commercial offers, products, services, and materials on third-party websites and third-party resources. Copyright Quectel Wireless Solutions Co., Ltd. 2023. All rights reserved. SG560D_Series_Hardware_Design 2 / 133 Smart Module Series Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be paid to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions, such as when the mobile bill is unpaid or the (U)SIM card is invalid. When emergency help is needed in such conditions, use emergency call if the device supports it. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. In an emergency, the device with emergency call function cannot be used as the only contact method considering network connection cannot be guaranteed under all circumstances. The cellular terminal or mobile contains a transceiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV sets, radios, computers or other electric equipment. In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or metal powders. SG560D_Series_Hardware_Design 3 / 133 Smart Module Series About the Document Revision History Version Date Author Description

2022-05-13 1.0 2022-06-22 Xiaomeng GUO/

Chris ZHANG Xiaomeng GUO/

Chris ZHANG Creation of the document First official release 1.1 2023-02-10 Waller GUO/

Jamie SHI Xiaomeng GUO 1. Added n3, n5, and n8 for SG560D-CN

(Table 3, Table 6, Table 36, Table38, Table 42 and Table 56). 2. Updated the video decode speed (Table 4). 3. Updated the NSA and SA maximum transmission rate of the 5G NR features

(Table 4) 4. Updated the TBD data of the Rx sensitivity

(Table 41 and Table 42). 5. Updated the TBD data of GNSS performance

(Table 46). 6. Updated GNSS antenna design requirement:

changed from VSWR: < 2 to VSWR: 2

(Table 52). 7. Updated the TBD data of the power consumption (Table 55 and Table 56). 8. Updated the recommended reflow soldering thermal profile, the recommended thermal profile parameters and related notes

(Chapter 8.2). 9. Updated UART multiplexing relationship

(Chapter 4.5 & 4.9). SG560D_Series_Hardware_Design 4 / 133 Smart Module Series Contents Safety Information .................................................................................................................................... 3 About the Document ................................................................................................................................ 4 Contents .................................................................................................................................................... 5 Table Index ............................................................................................................................................... 8 Figure Index ............................................................................................................................................ 10 1 Introduction ..................................................................................................................................... 12 Special Mark ......................................................................................................................... 16 1.1. 2 Product Overview ............................................................................................................................ 17 Frequency Bands and Functions .......................................................................................... 17 Key Features ........................................................................................................................ 18 Functional Diagram ............................................................................................................... 22 Pin Assignment ..................................................................................................................... 24 Pin Description ..................................................................................................................... 25 EVB Kit ................................................................................................................................. 43 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 3.1. 3 Operating Characteristics .............................................................................................................. 44 Power Supply ....................................................................................................................... 44 3.1.1. Power Supply Pins ....................................................................................................... 44 3.1.2. Battery Charge and Management ................................................................................ 44 3.1.3. Reference Design for Power Supply ............................................................................ 46 3.1.4. Requirements for Voltage Stability ............................................................................... 47 Turn On ................................................................................................................................. 48 Turn Off/Restart .................................................................................................................... 50 VRTC .................................................................................................................................... 50 Power Output ........................................................................................................................ 51 3.2. 3.3. 3.4. 3.5. 4.1. 4.1.1.1. 4.1.1.2. 4.1.1.3. 4 Application Interfaces ..................................................................................................................... 54 USB Interfaces ..................................................................................................................... 54 4.1.1. USB0 Interface ............................................................................................................ 54 USB Type-C Mode ........................................................................................ 56 Micro USB Mode .......................................................................................... 56 DisplayPort Mode ......................................................................................... 57 4.1.2. USB1 Interface ............................................................................................................ 58 4.1.3. Design Principles for USB Interfaces ........................................................................... 59

(U)SIM Interfaces.................................................................................................................. 60 SD Card Interface ................................................................................................................. 63 GPIO Interfaces .................................................................................................................... 65 UART Interfaces ................................................................................................................... 67 I2C Interfaces ....................................................................................................................... 68 SPI Interface ......................................................................................................................... 69 I2S Interfaces ....................................................................................................................... 70 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. SG560D_Series_Hardware_Design 5 / 133 Smart Module Series UART/SPI/I2C/I2S Multiplexing Relationship ........................................................................ 71 4.9. 4.10. ADC Interfaces ..................................................................................................................... 74 4.11. LCM Interface ....................................................................................................................... 75 4.12. Touch Panel Interface ........................................................................................................... 77 4.13. Camera Interfaces ................................................................................................................ 78 MIPI Design Considerations ................................................................................. 83 4.14. Sensor Interfaces ................................................................................................................. 87 4.15. Emergency Download Interface ............................................................................................ 87 4.16. PCIe Interface ....................................................................................................................... 88 4.17. NFC Interface* ...................................................................................................................... 89 4.13.1. 5.2. 5.1. 5 RF Specifications ............................................................................................................................ 90 Cellular Network ................................................................................................................... 90 5.1.1. Antenna Interfaces & Frequency Bands ...................................................................... 90 5.1.2. Transmitting Power ...................................................................................................... 92 5.1.3. Rx Sensitivity ............................................................................................................... 93 5.1.4. Reference Design of Cellular Antenna Interfaces ........................................................ 96 GNSS ................................................................................................................................... 96 5.2.1. Antenna Interface & Frequency Bands ........................................................................ 96 5.2.2. GNSS Performance ..................................................................................................... 97 5.2.3. Reference Design ........................................................................................................ 98 Reference Design for GNSS Passive Antenna ............................................. 98 Reference Design for GNSS Active Antenna ................................................ 98 GNSS RF Design Guidelines ....................................................................... 99 5.3. Wi-Fi/Bluetooth ..................................................................................................................... 99 5.3.1. Antenna Interface & Frequency Bands ...................................................................... 100 5.3.2. Wi-Fi Overview .......................................................................................................... 100 5.3.3. Bluetooth Overview .................................................................................................... 107 5.3.4. Reference Design ...................................................................................................... 108 Reference Design of RF Routing ........................................................................................ 109 Antenna Installation ............................................................................................................. 111 5.5.1. Antenna Design Requirement ..................................................................................... 111 5.5.2. RF Connector Recommendation ................................................................................ 112 5.2.3.1. 5.2.3.2. 5.2.3.3. 5.4. 5.5. 6 Electrical Characteristics and Reliability .................................................................................... 114 Absolute Maximum Ratings ................................................................................................. 114 Power Supply Ratings ......................................................................................................... 114 Power Consumption ............................................................................................................ 115 Digital I/O Characteristic ..................................................................................................... 121 ESD Protection ................................................................................................................... 123 Operating and Storage Temperatures ................................................................................. 123 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 7 Mechanical Information ................................................................................................................ 124 7.1. Mechanical Dimensions ...................................................................................................... 124 Recommended Footprint .................................................................................................... 126 7.2. Top and Bottom Views ........................................................................................................ 127 7.3. SG560D_Series_Hardware_Design 6 / 133 Smart Module Series 8 Storage, Manufacturing and Packaging ...................................................................................... 128 8.1. Storage Conditions ............................................................................................................. 128 8.2. Manufacturing and Soldering .............................................................................................. 129 Packaging Specification ...................................................................................................... 131 8.3. 8.3.1. Injection Tray ............................................................................................................. 131 8.3.2. Packaging Process .................................................................................................... 132 9 Appendix References ................................................................................................................... 133 SG560D_Series_Hardware_Design 7 / 133 Smart Module Series Table Index Table 1: Special Marks ............................................................................................................................ 16 Table 2: Brief Introduction of the Module ................................................................................................. 17 Table 3: Wireless Network Type .............................................................................................................. 17 Table 4: Key Features ............................................................................................................................. 18 Table 5: I/O Parameters Definition ........................................................................................................... 25 Table 6: Pin Description ........................................................................................................................... 25 Table 7: VBAT Pins .................................................................................................................................. 44 Table 8: Pin Definition of Charging Interface ........................................................................................... 45 Table 9: Pin Definition of PWRKEY ......................................................................................................... 48 Table 10: Pin Definition of Power Suppy Interface ................................................................................... 51 Table 11: Pin Definition of USB0 .............................................................................................................. 54 Table 12: USB Type-C Mode and DisplayPort Mode Pin Mapping .......................................................... 57 Table 13: Pin Description of USB1 Interface ........................................................................................... 58 Table 14: USB Trace Length Inside the Module ...................................................................................... 59 Table 15: Pin Definition of (U)SIM Interfaces ........................................................................................... 60 Table 16: Pin Definition of SD Card Interface .......................................................................................... 63 Table 17: SD Card Signal Trace Length Inside the Module ..................................................................... 64 Table 18: Pin Definition of GPIO Interfaces ............................................................................................. 65 Table 19: Pin Definition of UART Interfaces ............................................................................................ 67 Table 20: Pin Definition of I2C Interfaces ................................................................................................ 68 Table 21: Pin Definition of SPI Interface .................................................................................................. 69 Table 22: Pin Definition of I2S Interfaces ................................................................................................. 70 Table 23: UART/SPI/I2C Multiplex Relationship ...................................................................................... 71 Table 24: I2S Multiplex Relationship Table .............................................................................................. 73 Table 25: Pin Definition of ADC Interfaces ............................................................................................... 74 Table 26: Pin Definition of LCM Interface ................................................................................................ 75 Table 27: Pin Definition of Touch Panel Interface .................................................................................... 77 Table 28: Pin Definition of Camera Interfaces ......................................................................................... 78 Table 29: Relationship Between CSI Rate and Line Length (D-PHY) ...................................................... 83 Table 30: Relationship Between DSI Rate and Line Length (D-PHY) ...................................................... 84 Table 31: Trace Length of MIPI Differential Pairs Inside the Module ....................................................... 84 Table 32: Pin Definition of Sensor Interfaces ........................................................................................... 87 Table 33: Pin Definition of PCIe Interface ................................................................................................ 88 Table 34: Trace Length of Differential Pairs Inside the Module................................................................ 88 Table 35: Pin Definition of NFC Interface ................................................................................................ 89 Table 36: Pin Definition of Cellular Network Interfaces of SG560D-CN ................................................... 90 Table 37: Pin Definition of Cellular Network Interfaces of SG560D-EU ................................................... 90 Table 38: Operating Frequency of SG560D-CN ...................................................................................... 91 Table 39: Operating Frequency of SG560D-EU ...................................................................................... 92 Table 40: Tx Power of SG560D-CN ......................................................................................................... 92 Table 41: Tx Power of SG560D-EU ......................................................................................................... 93 SG560D_Series_Hardware_Design 8 / 133 Smart Module Series Table 42: Conducted RF Rx Sensitivity of SG560D-CN .......................................................................... 93 Table 43: Conducted RF Rx Sensitivity of SG560D-EU (Unit:dBm) ........................................................ 94 Table 44: Pin Definition of GNSS Antenna Interface ................................................................................ 97 Table 45: Operating Frequency ............................................................................................................... 97 Table 46: GNSS Performance ................................................................................................................. 97 Table 47: Pin Definition of Wi-Fi/Bluetooth Interfaces ............................................................................ 100 Table 48: Wi-Fi/Bluetooth Frequency .................................................................................................... 100 Table 49: Wi-Fi Transmitting Performance ............................................................................................ 101 Table 50: Wi-Fi Receiving Performance ................................................................................................ 104 Table 51: Bluetooth Data Rate and Version ........................................................................................... 107 Table 52: Bluetooth Transmitting and Receiving Performance .............................................................. 108 Table 53: Antenna Design Requiremets ................................................................................................. 111 Table 54: Absolute Maximum Ratings .................................................................................................... 114 Table 55: Power Supply Ratings ............................................................................................................. 114 Table 56: Power Consumption of SG560D-CN ...................................................................................... 115 Table 57: Power Consumption of SG560D-EU ....................................................................................... 117 Table 58: 1.8 V I/O Requirements ......................................................................................................... 121 Table 59: (U)SIM 1.8 V I/O Requirements ............................................................................................. 121 Table 60: (U)SIM 2.95 V I/O Requirements ........................................................................................... 122 Table 61: SD card 1.8 V I/O Requirements ........................................................................................... 122 Table 62: SD card 2.95 V I/O Requirements ......................................................................................... 122 Table 63: Electrostatics Discharge Characteristics (Temperature: 2530 C, Humidity: 40 5 % ) ........ 123 Table 64: Operating and Storage Temperatures .................................................................................... 123 Table 65: Recommended Thermal Profile Parameters .......................................................................... 130 Table 66: Related Documents ............................................................................................................... 133 Table 67: Terms and Abbreviations ........................................................................................................ 133 SG560D_Series_Hardware_Design 9 / 133 Smart Module Series Figure Index Figure 1: Functional Diagram .................................................................................................................. 18 Figure 2: Application Block Diagram ........................................................................................................ 18 Figure 3: Pin Assignment ........................................................................................................................ 24 Figure 4: Reference Circuit for Battery Charging Circuit ......................................................................... 46 Figure 5: Reference Circuit of Power Supply .......................................................................................... 47 Figure 6: Power Supply Limits During Burst Transmission ...................................................................... 47 Figure 7: Structure of Power Supply ........................................................................................................ 48 Figure 8: Turn On the Module Using Driving Circuit ................................................................................ 48 Figure 9: Turn On the Module Using Button ............................................................................................ 49 Figure 10: Turn-on Timing ....................................................................................................................... 49 Figure 11: Restart Timing ........................................................................................................................ 50 Figure 12: RTC Powered by a Rechargeable Cell Battery ...................................................................... 50 Figure 13: RTC Powered by Capacitor .................................................................................................... 51 Figure 14: USB Type-C Reference Circuit of USB0 ................................................................................ 56 Figure 15: Micro USB Reference Circuit of USB0 ................................................................................... 56 Figure 16: DisplayPort Mode Reference Circuit ...................................................................................... 58 Figure 17: Reference Circuit of (U)SIM Interface with 8-Pin (U)SIM Card Connector ............................. 62 Figure 18: Reference Circuit of (U)SIM Interface with 6-Pin (U)SIM Card Connector ............................. 62 Figure 19: Reference Circuit for SD Card Interface ................................................................................. 64 Figure 20: Reference Circuit with Level-Shifting Chip (for UART) ........................................................... 67 Figure 21: Reference Circuit with RS232 Level-Shifting Chip (for UART) ............................................... 68 Figure 22: Reference Circuit for LCM Interface ....................................................................................... 76 Figure 23: LCM External Backlight Driver Reference Circuit ................................................................... 77 Figure 24: Reference Circuit for TP Interface .......................................................................................... 78 Figure 25: Reference Circuit for Dual-Camera Applications .................................................................... 81 Figure 26: Reference Circuit for Three-Camera Applications .................................................................. 82 Figure 27: Reference Circuit for Emergency Download Interface ........................................................... 87 Figure 28: Reference Circuit for RF Antenna Interfaces .......................................................................... 96 Figure 29: Reference Circuit for GNSS Passive Antenna ........................................................................ 98 Figure 30: Reference Circuit for GNSS Active Antenna ........................................................................... 99 Figure 31: Reference Circuit for Wi-Fi/Bluetooth Antenna ..................................................................... 108 Figure 32: Reference Circuit for Wi-Fi MIMO Antenna .......................................................................... 108 Figure 33: Microstrip Design on a 2-layer PCB ..................................................................................... 109 Figure 34: Coplanar Waveguide Design on a 2-layer PCB .................................................................... 109 Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) ................. 109 Figure 36: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................. 110 Figure 37: Dimensions of the Receptacle (Unit: mm) ............................................................................. 112 Figure 38: Specifications of Mated Plugs (Unit: mm) .............................................................................. 112 Figure 39: Space Factor of Mated Connectors (Unit: mm) ..................................................................... 113 Figure 40: Module Top and Side Dimensions ........................................................................................ 124 Figure 41: Module Bottom Dimensions (Bottom View) .......................................................................... 125 SG560D_Series_Hardware_Design 10 / 133 Smart Module Series Figure 42: Recommended Footprint ...................................................................................................... 126 Figure 43: Top & Bottom Views of the Module ....................................................................................... 127 Figure 44: Recommended Reflow Soldering Thermal Profile ................................................................ 129 Figure 45: Injection Tray Dimension Drawing ........................................................................................ 131 Figure 46: Packaging Process............................................................................................................... 132 SG560D_Series_Hardware_Design 11 / 133 Smart Module Series 1 Introduction This document defines the SG560D series module and describes its air interfaces and hardware interfaces which are connected to your applications. With this document, you can quickly understand module interface specifications, electrical and mechanical details, as well as other related information of the module. The document, coupled with application notes and user guides, makes it easy to design and set up mobile applications with the module. Modifications:

Any changes or modifications not expressly approved by Quectel or the party responsible for compliance could void the users authority to operate the equipment and invalidate the regulatory approval. Host manufacturer must follow KDB Publication 996369 D04 Modulen Integration Guide. Host manufacturer is responsible for regression tests to show compliance to the applicable standards due to the following actions:

1.any modification done to the module. 2.Integration of the module into a host device Host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. Final host product is required to show compliance to Part 15 Subpart B with the modular transmitter installed Product Marketing NameQuectel SG560D-WF FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met:

1. This Modular Approval is limited to OEM installation for mobile and fixed applications only. The antenna installation and operating configurations of this transmitter, including any applicable source-based timeaveraging duty factor, antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements of 2.1091. 2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the users body and must not transmit simultaneously with any other antenna or transmitter. 3. A label with the following statements must be attached to the host end product:

This device contains FCC ID: XMR2023SG560DWF FCC/ISED Regulations restrict operation of this device to Indoor Use Only 4. Antenna Requirements:

SG560D_Series_Hardware_Design 12 / 133 Smart Module Series The following antennae were approved with the modules:

Operating Frequency Antenna Type Antenna P/N Antenna Gain (dBi) Band

(MHz) Bluetooth 2400~2483.5 2.4G WiFi 5G WiFi 5150~5850 6E WiFi 5925~7125 Dipole SAA31578A 0.47 dBi 0.47 dBi 5150~5250 MHz: -0.67 dBi 5250~5350 MHz: -0.19 dBi 5470~5725 MHz: 1.28 dBi 5725~5850 MHz1.10 dBi 5925~6425 MHz: 3.76dBi 6425~6525 MHz: 3.62dBi 6525~6875 MHz: 3.62dBi 6875~7125 MHz: 2.20dBi The product is provided with an approved antenna. Use only supplied or approved antenna by Quectel. Any changes or modifications to the Antenna may void the regulatory approvals obtained for the product. Host device must comply with FCC Part 15 antenna requirements The OEM must design the host so that the antenna will be installed as an integrated antenna for the host containing the SG560D-WF and the end user shall not be able to access, remove or replace the antenna. 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093 If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations. For this device, OEM integrators must be provided with labeling instructions of finished products. Please refer to KDB784748 D01 v07, section 8. Page 6/7 last two paragraphs:

A certified modular has the option to use a permanently affixed label, or an electronic label. For a permanently affixed label, the module must be labeled with an FCC ID - Section 2.926 (see 2.2 Certification (labeling requirements) above). The OEM manual must provide clear instructions explaining to the OEM the labeling requirements, options and OEM user manual instructions that are required (see next paragraph). For a host using a certified modular with a standard fixed label, if (1) the modules FCC ID is not visible when installed in the host, or (2) if the host is marketed so that end users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible;

then an additional permanent label referring to the enclosed module: Contains Transmitter Module FCC ID: XMR2023SG560DWF or Contains FCC ID: XMR2023SG560DWF must be used. The host OEM user manual must also contain clear instructions on how end users can find and/or access the module SG560D_Series_Hardware_Design 13 / 133 Smart Module Series and the FCC ID. The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The users manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. In cases where the manual is provided only in a form other than paper, such as on a computer disk or over the Internet, the information required by this section may be included in the manual in that alternative form, provided the user can reasonably be expected to have the capability to access information in that form. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the manufacturer could void the users authority to operate the equipment. To ensure compliance with all non-transmitter functions the host manufacturer is responsible for ensuring compliance with the module(s) installed and fully operational. For example, if a host was previously authorized as an unintentional radiator under the Suppliers Declaration of Conformity procedure without a transmitter certified module and a module is added, the host manufacturer is responsible for ensuring that the after the module is installed and operational the host continues to be compliant with the Part 15B unintentional radiator requirements. Manual Information To the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. 5.925-7.125 GHz Radio Transmitters General Refer to KDB publication 987594 D01, Operation of these devices in the 5.925-7.125 GHz band is prohibited on oil platforms, cars, trains, boats, and aircraft, except that operation of this device is permitted in large aircraft while flying above 10,000 feet. 1. Operation of these devices in the 5.925-7.125 GHz band is prohibited for control of or communications with unmanned aircraft systems. 2. Any changes or modifications not expressly approved by the party responsible for compliance could void the users authority to operate the equipment. 3. In the 5.925-7.125 GHz band, devices containing client device must operate under the control of a device containing the SG560D-WF which is an indoor access point. In all cases, an exception exists for transmitting brief messages to an access point when attempting to join its network after detecting a signal that confirms that an access point is operating on a particular channel. Access points may connect to other access points. Client devices are prohibited from connecting directly to another client device. IC Statement IRSS-GEN

"This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following SG560D_Series_Hardware_Design 14 / 133 Smart Module Series two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device." or "Le prsent appareil est conforme aux CNR dIndustrie Canada applicables aux appareils radio exempts de licence. Lexploitation est autorise aux deux conditions suivantes :

1) lappareil ne doit pas produire de brouillage; 2) lutilisateur de lappareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible den compromettre le fonctionnement."

Dclaration sur l'exposi tion aux rayonnements RF L'autre utilis pour l'metteur doit tre i nstall pour fournir une distance de sparation d'au moins 20 cm de toutes les personnes et ne doit pas tre colocalis ou fonctionner conjointement avec une autre antenne ou un autre me tteur. The host product shall be properly labeled to identify the modules within the host product. The Innovation, Science and Economic Development Canada certification label of a module shall be clearly visible at all times when installed in the host product; otherwise, the host product must be labeled to display the Innovation, Science and Economic Development Canada certification number for the module, preceded by the word Contains or similar wording expressing the same meaning, as follows:

Contains IC: 10224A-23SG560DWF or where: 10224A-23SG560DWF is the modules certification number. Le produit hte doit tre correctement tiquet pour identifier les modules dans le produit hte. L'tiquette de certification d'Innovation, Sciences et Dvelopp ement c onomique Canada d'un module doit tre clairement visible en tout temps lorsqu'il est installdans le produit hte; sinon, le produit hte doit porter une tiquette indiquant le numro de certification d'Innovation, Sciences et Dveloppement conomi que Canada pour le module, prc d du mot Contient ou d'un libe ll semblable exprim ant la mme signification, comme suit:

"Contient IC: 10224A-23SG560DWF" ou "o: 10224A-23SG560DWF est le numro de certification du module". i. the device for operation in the band 51505250 MHz is only for indoor use to reduce the potential for harmful interference to co-channel mobile satellite systems;

ii. for devices with detachable antenna(s), the maximum antenna gain permitted for devices in the bands 5250-5350 MHz and 5470-5725 MHz shall be such that the equipment still complies with the e.i.r.p. limit;

iii. for devices with detachable antenna(s), the maximum antenna gain permitted for devices in the band 5725-5850 MHz shall be such that the equipment still complies with the e.i.r.p. limits as appropriate;

iv. Omnidirectional antenna is recommended This device complies with RSS-248 of the Industry Canada Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation of the device. Ce dispositif est conforme la norme CNR -248 d'Industrie Canada applicable aux appareils radio exempts de licence. L'exploitation est autorise aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement. Caution:

Operation shall be limited to indoor use only;

Operation on oil platforms, cars, trains, boats and aircraft shall be prohibited except for on large aircraft SG560D_Series_Hardware_Design 15 / 133 Smart Module Series flying above 10,000 ft. Avertissement:

Utilisation limite lintrieur seulement;

Utilisation interdite bord de plateformes de forage ptrolier, de voitures, de trains, de bateaux et daronefs, sauf bord dun gros aronef volant plus de 10 000 pieds daltitude Enclosure Requirements: Host devices containing the SG560D-WF module and operating in the 5.925-7.125 GHz is prohibited from having a weatherized enclosure. Usage Requirements:

Host devices containing the SG560D-WF module and operating in the 5.925-7.125 GHz must be powered by wired connection such as AC adapter (battery use is not allowed). SG560D-WF do not have a battery backup. If host devices containing SG560D-WF module are designed to have a battery backup, the use of the backup battery should only be allowed during power outages and for indoor use. Host devices containing SG560D-WF are prohibited from direct connection to the internet. 1.1. Special Mark Table 1: Special Marks Mark Definition

Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface, pin name, AT command, or argument, it indicates that the function, feature, interface, pin, AT command, or argument is under development and currently not supported; and the asterisk (*) after a model indicates that the sample of such model is currently unavailable. Brackets ([]) used after a pin enclosing a range of numbers indicate all pins of the same type. For example, SDIO_DATA[0:3] refers to all four SDIO pins: SDIO_DATA0, SDIO_DATA1, SDIO_DATA2, and SDIO_DATA3. SG560D_Series_Hardware_Design 16 / 133 Smart Module Series 2 Product Overview SG560D is a series of smart 5G modules based on Android operating system, and provides industrial grade performance. It supports up to 4K video encoding/decoding, DMIC, built-in high performance Adreno 643 GPU, abundant GPIO interfaces as well as external audio codec. With these, the module is engineered to meet the demanding requirements in M2M applications, such as smart gateway, CPE, MiFi, MID, PND, POS, router, multimedia terminal, smart phone, digital signage, industrial PDA. Related information and details are listed in the table below:

Table 2: Brief Introduction of the Module SG560D Series Packaging Pin Number Dimensions Weight LGA 636

(42.5 0.2) mm (56.5 0.2) mm (2.95 0.2) mm Approx. 17.5 g Wireless Network Functions 1 5G NR, LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA, WCDMA, GSM, EDGE Variants SG560D-CN, SG560D-EU,SG560D-WF 2.1. Frequency Bands and Functions Table 3: Wireless Network Type Wireless Network Type SG560D-CN SG560D-EU SG560D-WF 5G NR NSA 5G NR SA n41/n78/n79 n1/n3/n5/n7/n8/n20/n28/n38/n40/

n41/n77/n78 n1/n3/n5/n8/n28/n41/n78/n79 n1/n3/n5/n7/n8/n20/n28/n38/n40/

1 GSM/EDGE bands are supported only on SG560D-EU. SG560D_Series_Hardware_Design 17 / 134 LTE-FDD LTE-TDD WCDMA GSM/EDGE GNSS Wi-Fi Bluetooth Smart Module Series n41/n77/n78 B1/B3/B5/B8 B1/B3/B5/B7/B8/B20/B28/B32 B34/B38/B39/B40/B41 B38/B39/B40/B41/B42 B1/B5/B8

B1/B5/B8 EGSM900/DCS1800 GPS/GLONASS/BDS/Galileo/Nav IC/SBAS/QZSS; L1 + L5 GPS/GLONASS/BDS/Galileo/NavI C/SBAS/QZSS; L1 + L5 802.11a/b/g/n/ac/ax 802.11a/b/g/n/ac/ax 802.11a/b/g/n/ac/ax Bluetooth 5.2 (BR/EDR + BLE) Bluetooth 5.2 (BR/EDR + BLE) Bluetooth 5.2

(BR/EDR + BLE) 2.2. Key Features Table 4: Key Features Parameter Details Customized octa-core 64-bit ARMv8-compliant Kryo 670 CPU with 2 MB L3 cache 1 Kryo Gold Plus (high performance) core @ 2.7 GHz with 256 KB Application Processor L2 cache 3 Kryo Gold (high performance) cores @ 2.4 GHz with 256 KB L2 cache 4 Kryo Silver (low power) cores @ 1.9 GHz with 128 KB L2 cache Modem system 5G NR: 3GPP Rel-15 LTE: 3GPP Rel-15 GPU Adreno 643, up to 812 MHz Memory 4 GB LPDDR4X + 64 GB UFS (default) SG560D-CN 6 GB LPDDR4X + 128 GB UFS (Optional) 8 GB LPDDR4X + 128 GB UFS (Optional) 8 GB LPDDR4X + 256 GB UFS (Optional) SG560D-WF 6 GB LPDDR4X + 128 GB UFS(Optional) 8 GB LPDDR4X + 128 GB UFS(Optional) SG560D_Series_Hardware_Design 18 / 134 Smart Module Series Operating System Android 12 Power Supply SMS LCM Interface Camera Interfaces Video Codec 2 Audio Codec 2 Supply voltage: 3.554.4 V Typical supply voltage: 4.0 V Text and PDU mode Point-to-point MO and MT SMS cell broadcast SMS storage: ME by default Supports one group of 4-lane MIPI_DSI, up to 2.5 Gbps/lane FHD + (1200 2520 ) @144 fps based on MIPI standard Supports Wi-Fi miracast 4K @ 60 fps Supports four groups of 4-lane MIPI_CSI, up to 2.5 Gbps/lane Supports up to 4 cameras 3 ISP : up to 3 27 MP @ 24 fps or 3 22 MP @ 30 fps; 36 MP +

27 MP @ 24 fps or 36 MP + 22 MP @ 30 fps; 36 MP @ 30 fps Video decode: up to 4K @ 60 fps for H.264/H.265/VP9 Video encode: up to 4K @ 30 fps for H.264/H.265 Video decode and encode: 1080P @ 60 fps decode +

1080P @ 60 fps encode or 4K @ 30 fps decode + 1080P @ 30 fps encode EVRC, EVRC-B, EVRC-WB, G.711, G.729, PCM, EVS GSM-FR, GSM-EFR, GSM-HR AMR-NB, AMR-WB, QCELP Audio Interfaces 3 Three digital microphone inputs

(U)SIM Interfaces ADC Interfaces Two (U)SIM interfaces Supports 1.8/2.95 V (U)SIM card Supports Dual SIM Dual Standby by default Four general-purpose ADC interfaces Supports up to 15-bit resolution Real Time Clock Supported USB Interfaces Supports two USB interfaces: USB0 and USB1 USB0 function:

Compliant with USB 3.1 Gen 1 and USB 2.0 specifications, with transmission rates up to 5 Gbps on USB 3.1 and 480 Mbps on USB 2.0 Supports USB OTG Used for AT command communication, data transmission, software debugging, firmware upgrade and voice over USB USB1 function:

Compliant with USB 2.0 specifications, with transmission rate up to 2 Audio codec and video codec listed in this table are dedicated for codec inside the CPU. 3 An external codec should be added via I2S interface when audio output function is needed. SG560D_Series_Hardware_Design 19 / 134 Smart Module Series DisplayPort Interface 480 Mbps Only support host mode (external VBUS power supply is needed) Supports DisplayPort 1.4 function through USB0_SS1 and USB0_SS2 Supports up to 4K (3840 2160) @ 60 fps USB 3.1 and DisplayPort 1.4 can work concurrently PCIe Interface Supports 2-lane PCIe Gen 3, up to 8 Gbps SD Card Interface Supports SD 3.0 protocol Supports 1.8/2.95 V SD card Supports SD card hot-swap Supports up to eleven groups of UART interfaces, two of them are default configurations and nine of them can be multiplexed from other interfaces Default UART interfaces: UART and DBG_UART UART Interfaces 4 UART: 4-wire UART interface, supports RTS and CTS hardware SPI Interfaces 4 flow control, up to 4 Mbps DBG_UART: 2-wire UART interface, dedicated for debugging For details about nine UART interfaces that can be multiplexed from other interfaces, see Table 23 Supports up to ten groups of SPI interfaces, one of them is default configuration and nine of them can be multiplexed from other interfaces The default SPI supports master mode only For details about nine SPI interfaces that can be multiplexed from other interfaces, see Table 23 Supports up to sixteen groups of I2C interfaces Five of them are dedicated I2C interfaces used for camera and sensor peripherals I2C Interfaces 4 Three of them are generic I2C interfaces that can be used for TP I2S Interfaces and NFC peripherals For details about eight I2C interfaces that can be multiplexed from other interfaces, see Table 23 Supports up to five groups of I2S interfaces Two I2S interfaces are default configurations For details about three I2S interfaces that can be multiplexed from other interfaces, see Table 24 Bluetooth Features Supports Bluetooth Core Specification Version 5.2 Supports Bluetooth Classic & BLE GNSS Features GPS/GLONASS/BDS/Galileo/NavIC/SBAS/QZSS, L1 + L5 Antenna Interface ANT0, ANT1, ANT2, ANT3 ANT_GNSS 4 For details about the multiplexing and conflict relationships of UART, I2C and SPI interfaces, see Table 23. SG560D_Series_Hardware_Design 20 / 134 Transmitting Power Smart Module Series ANT_WIFI/BT, ANT_WIFI_MIMO(SG560D-WF) Class 4 (33 dBm 2 dB) for EGSM900 Class 1 (30 dBm 2 dB) for DCS1800 Class E2 (27 dBm 3 dB) for EGSM900 8 -PSK Class E2 (26 dBm 3 dB) for DCS1800 8 -PSK WCDMA bands: Class 3 (23 dBm 2 dB) LTE HPUE 5 band (B41): Class 2 (26 dBm 2 dB) Other LTE bands: Class 3 (23 dBm 2 dB) 5G NR HPUE 5 bands (n41/n77/n78/n79): Class 2 (26 dBm +2/-3 dB) Other 5G NR bands: Class 3 (23 dBm 2 dB) Supports 3GPP Rel-15 FDD and TDD Supported modulation types:

Uplink: /2-BPSK, QPSK, 16QAM, 64QAM and 256QAM Downlink: QPSK, 16QAM, 64QAM and 256QAM Supports Multi-User MIMO Uplink: 2 2 MIMO 6:

SG560D-CN: n41/n78/n79 SG560D-EU: n41/n77/n78 5G NR Features Downlink: 4 4 MIMO :

SG560D-CN: n1/n41/n78/n79 SG560D-EU: n1/n3/n7/n38/n40/n41/n77/n78 Supports SCS 15 kHz and 30 kHz 7 Supports SA and NSA operation modes Supports Option 3x, Option 3a, Option 3 and Option 2 Maximum transmission rate:

NSA: 2.5 Gbps (DL)/ 550 Mbps (UL) SA: 2.1 Gbps (DL)/ 900 Mbps (UL) Support 3GPP Rel-15 FDD and TDD Supports 1.4/3/5/10/15/20 MHz RF bandwidth Supports Multi-User MIMO Downlink: 4 4 MIMO :

SG560D-CN: B1/B41 SG560D-EU: B1/B3/B7/B38/B40/B41/B42 Supports modulation types:

Uplink QPSK, 16QAM, 64QAM and 256QAM Downlink QPSK, 16QAM, 64QAM and 256QAM Maximum transmission rate: 1.2 Gbps (DL)/ 200 Mbps (UL) Supports 3GPP Rel-9 Supports QPSK, 16QAM and 64QAM modulation LTE Features UMTS Features 5 HPUE only supports single carrier. 6 Uplink 2 2 MIMO is support ed only in 5G TDD SA mode. 7 5G NR FDD bands only support 15 kHz SCS. 5G NR TDD bands only support 30 kHz SCS. SG560D_Series_Hardware_Design 21 / 134 Smart Module Series DC-HSDPA: Max. 42 Mbps (DL) HSUPA: Max. 5.76 Mbps (UL) WCDMA: Max. 384 kbps (DL)/ 384 kbps (UL) Class 4 (33 dBm 2 dB) for EGSM 900 Class 1 (30 dBm 2 dB) for DCS1800 Class E2 (27 dBm 3 dB) for EGSM900 8 -PSK Class E2 (26 dBm 3 dB) for DCS1800 8 -PSK EDGE: Max. 296 kbps (DL)/ 236.8 kbps (UL) GPRS: Max. 107 kbps (DL)/ 85.6 kbps (UL) Supports Wi-Fi 6E Supports AP and STA modes 2.4GHz; 5 GHz; 6 GHz, supports 802.11a/b/g/n/ac/ax, up to 3.6 Gbps GSM Features 8 WLAN Features

(SG560D-WF) Temperature Range Operating Temperature Range 9: -35 C to +75 C Storage Temperature Range: -40 C to +90 C Firmware Upgrade Upgrade via USB or OTA RoHS All hardware components are fully compliant with EU RoHS directive 2.3. Functional Diagram The main functional components of the module diagram are explained below Power Management Battery Charge and Management Radio Frequency Baseband Memory (LPDDR4X + UFS flash) Peripheral Interface

- USB Interfaces

- (U)SIM Interfaces

- SD Card Interface

- GPIO Interfaces

- UART Interfaces

- I2C Interfaces

- SPI Interface

- I2S Interfaces

- ADC Interfaces

- LCM (MIPI) Interface 8 GSM/EDGE bands are supported only on SG560D-EU. 9 Within operating temperature range, the module is 3GPP compliant. SG560D_Series_Hardware_Design 22 / 134 Smart Module Series

- Touch Panel Interface

- Camera (MIPI) Interfaces

- Sensor Interfaces

- Emergency Download Interface

- PCIe Interface

- NFC Interface*

NOTE For SG560D-EU, the I/O directions of ANT1 and ANT2 are analog input/output. For SG560D-CN, the I/O directions of ANT1 and ANT2 are analog input. SG560D_Series_Hardware_Design 23 / 134 Smart Module Series 2.4. Pin Assignment The following figure illustrates the pin assignment of the module. Figure 1: Pin Assignment NOTE Keep all RESERVED pins unconnected. SG560D_Series_Hardware_Design 24 / 134 381GND434GND2VBAT82GND70CCI_I2C_SCL272CSI3_LN3_P64CSI3_LN2_P68CSI3_LN1_P69CSI3_LN1_N56GND48CSI1_LN2_P44CSI1_LN1_P40CSI1_LN0_P52CSI1_LN3_P32GND28CSI0_LN3_P24CSI0_LN2_P60CSI3_LN0_P20CSI0_LN1_P13GND37GND125GND73CSI3_LN3_N65CSI3_LN2_N57GND54CAM1_MCLK53CSI1_LN3_N49CSI1_LN2_N45CSI1_LN1_N41CSI1_LN0_N34GND29CSI0_LN3_N25CSI0_LN2_N21CSI0_LN1_N61CSI3_LN0_N4VBAT9GND78GND67CAM3_RST71CCI_I2C_SDA266CSI3_CLK_N42CSI1_CLK_N38CSI1_CLK_P33CCI_I2C_SDA062CSI3_CLK_P36CCI_I2C_SCL026CAM0_RST10GND18CSI0_CLK_N50CAM1_RST5VBAT302ANT_GNSS280RESERVED268RESERVED256ANT2292ANT3244ANT1232RESERVED220RESERVED262RESERVED258RESERVED254RESERVED286RESERVED242GRFC_0238GRFC_1226RESERVED222RESERVED417GND420VPH_PWR421VPH_PWR424VPH_PWR402CCI_I2C_SCL1392CSI2_LN0_P388CSI2_LN1_P396CSI2_LN2_P380DSI_LN0_P384CAM2_RST376DSI_LN1_P372DSI_LN2_P368DSI_LN3_P364GND357USB0_SS1_TX_M354USB0_DP350GND400CSI2_LN3_P375USB_VCONN359GND353USB0_SS1_RX_M431USB_VBUS344GND336LDO18B_1V8325TP_I2C_SDA416GND407BAT_THERM389CSI2_LN0_N385CSI2_LN1_N393CSI2_LN2_N377DSI_LN0_N373DSI_LN1_N369DSI_LN2_N365DSI_LN3_N361GND358USB0_DM339USB0_CC1349USB0_SS2_RX_M397CSI2_LN3_N345USB0_SS2_TX_M346RESERVED343RESERVED425GND316GND340PWM1418BAT_P413GND426GND390CSI2_CLK_P386CSI2_CLK_N370DSI_CLK_N366DSI_CLK_P378LCD_RST374LCD_TE362GND360USB0_SS1_TX_P356USB0_SS1_RX_P352USB0_SS2_RX_P348USB0_SS2_TX_P398CAM2_MCLK342USB0_CC2338USB_PHY_PS337USB_OPTION399ADC0169USIM2_DATA205GND181SD_DATA3177SD_DATA2185SD_DATA1184SD_DATA0165USIM1_DATA164USIM1_CLK162USIM1_RST159USIM1_DET160USIM1_VDD139LPI_MI2S_WS134LPI_MI2S_DATA1130LPI_MI2S_DATA2105GND109LDO12C_1V8112LDO8C_1V8107NFC_I2C_SCL100GND92ANT_WIFI/BT176SD_LDO9C174SD_DET180SD_CMD188SD_CLK173SD_LDO6C168USIM2_CLK166USIM2_RST163USIM2_DET170GPIO_33172USIM2_VDD152LPI_SENSOR_I2C1_SDA135LPI_MI2S_DATA0138LPI_MI2S_SCLK131LPI_MI2S_DATA3101GND116VREG_L1P_1P05121VREG_L2P_1P1113VREG_L3P_2P8132GND97GND203GPIO_45200USB_BOOT193SPI_CS189I2C0_SDA192I2C0_SCL136MI2S_DATA1133MI2S_DATA0137MI2S_WS140MI2S_SCLK149LPI_SENSOR_I2C1_SCL182GND124VREG_L4P_2P9128VREG_L5P_2P8117VREG_L6P_1P8120VREG_L7P_2P8108GND443GND442GND441GND440GND439GND438GND437GND452GND451GND450GND449GND448GND447GND446GND461GND460GND459GND458GND457GND456GND455GND470GND469GND468GND467GND466GND465GND464GND479GND478GND477GND476GND475GND474GND473GND488GND487GND486GND485GND484GND483GND482GND497GND496GND495GND494GND493GND492GND491GND506GND505GND504GND503GND502GND501GND500GND514GND513GND512GND511GND510GND509GND435GND436GND433GNDPower PinsRESERVED PinsCamera Pins(U)SIM PinsGPIO PinsUSB pinsSPI PinsSD PinsBattery InterfacesANTThermal Pins328TP_I2C_SCL178GPIO_3514CSI0_CLK_P16CSI0_LN0_P74CAM3_MCLK17CSI0_LN0_N1VBAT432USB_VBUS96GND430USB_VBUS427GND313GND429USB_VBUS93GND89GND94GPIO_6404GND401CCI_I2C_SDA1410BAT_ID86ANT_WIFI_MIMO88GND83GND85GND87GND84GND90GND81GNDLCM Pins27VIB_DRV_P39GND11ADC177GND58GND80RESERVED51GPIO_6155RGB_GRN63RGB_RED79PWM219GPIO_715ADC259RGB_BLU35GND47GND308UART_TXD394GND324TP_RST332PWRKEY329VOL_ UP333VOL_DOWN379GND406GND414GND382GND367GND363GND309UART_RXD321TP_INT312VRTC314RESERVED186MAG_INT145LPI_DMIC2_CLK141LPI_DMIC1_DATA171GND144LPI_DMIC1_CLK148LPI_DMIC2_DATA106NFC_I2C_SDA102NFC_CLK_REQ99NFC_INT98NFC_EN95NFC_CLK12GND7FLASH_LED130CAM0_MCLK43GPIO_24103NFC_DWL_REQ179GND123GPIO_68129GND155GPIO_43119GPIO_19196SPI_MISO197SPI_CLK204GND206GND202GPIO_44408LDO17B_1V8409LDO13C_2V8412LDO7C_3V0419BAT_M150GPIO_165111GPIO_16175GPIO_105194SPI_MOSI208GND209GND213GND212GND76GND411GND22GND405GND351GPIO_32387GND110GPIO_17143GND3VBAT8GND6GND23GND46GND91GND104RESERVED114GND115GND118GND126CODEC_RST_N127GND142MI2S_MCLK146GND147GPIO_93151GPIO_158153LPI_SENSOR_I2C2_SDA154GPIO_166156LPI_SENSOR_I2C2_SCL157ALPS_INT158ACCEL_GYRO_INT2161ACCEL_GYRO_INT1190HALL_INT191GPIO_13198GPIO_12210GPIO_107211ANT0214GND215GND216GND305UART_RTS306UART_CTS311GPIO_12315GPIO_34317DBG_TXD320DBG_RXD319GPIO_47334GND335GND341SS_DIR_OUT371GND403ADC3428GND445GND444GND454GND453GND463GND462GND472GND471GND481GND480GND490GND489GND499GND498GND508GND507GND516GND515GND517GND521GND520GND519GND518GND523GND522GND524GND525GND526GND530GND529GND528GND527GND532GND531GND533GND534GND535GND539GND538GND537GND536GND541GND540GND542GND543GND544GND546GND545GND547GND548GND549GND551GND550GND552GND553GND555GND554GND556GND557GND558GND559GND560GND561GND562GND563GND564GND565GND566GND567GND568GND569GND570GND571GND572GND573GND574GND575GND576GND577GND578GND579GND580GNDGND PinsUART PinsI2C PinsOther PinsRF CTRLTP PinsI2S Pins217GND221GND291RESERVED287RESERVED267RESERVED263RESERVED259RESERVED251RESERVED283RESERVED231RESERVED219RESERVED218GND224GND225GND228GND229GND230GND233GND234GND235GND236GND237GND239GND240GND241GND243GND245GND246GND247RESERVED248GND249GND250GND252GND253GND255GND257GND260GND261GND264GND265GND266GND269GND270GND271GND272GND273GND275GND276GND277GND279GND281GND282GND284GND285GND288GND289GND290GND293GND295GND296GND297GND299GND300GND301GND303GND304GNDGRFC31RESERVED75RESERVED122GPIO_18167GPIO_106183GPIO_14187GPIO_15195RESERVED199RESERVED201RESERVED207GPIO_46223RESERVED227RESERVED274RESERVED278RESERVED294RESERVED298RESERVED307GPIO_9310GPIO_108318GPIO_42322GPIO_62323RESERVED326GPIO_63327RESERVED330RESERVED331RESERVED347RESERVED355RESERVED383RESERVED391RESERVED395RESERVED415RESERVED422RESERVED423RESERVED311GPIO_8621USB1_DM626LDO2C_1V8634RESERVED620USB0_DP_AUX_P627RESERVED628RESERVED610RESERVED618RESERVED636RESERVED635RESERVED616RESERVED630RESERVED622USB1_DP631RESERVED633RESERVED617RESERVED625RESERVED632RESERVED629RESERVED624LDO3C_3V0623GND613RESERVED619USB0_DP_AUX_M615RESERVED614RESERVED612LPI_DMIC3_CLK611LPI_DMIC3_DATA609RESERVED597PCIE1_RX0_P593PCIE1_REFCLK_M605PCIE1_RST_N588RESERVED589RESERVED603PCIE1_TX1_P598PCIE1_RX1_M595GND594PCIE1_REFCLK_P608RESERVED606PCIE1_CLKREQ_N591RESERVED600PCIE1_TX0_M311GPIO_12582RESERVED583RESERVED587RESERVED596PCIE1_RX0_M604GND584RESERVED585RESERVED586RESERVED590RESERVED592GND599PCIE1_RX1_P601PCIE1_TX0_P602PCIE1_TX1_M607PCIE1_WAKE_N581RESERVEDPCIe Pins Smart Module Series 2.5. Pin Description The following table shows the DC characteristics and pin descriptions. Table 5: I/O Parameters Definition Type AI AIO AO DI DIO DO OD PI PIO PO Description Analog Input Analog Input/Output Analog Output Digital Input Digital Input/Output Digital Output Open Drain Power Input Power Input/Output Power Output Table 6: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment VBAT 15 PIO Power supply for the module Vmin = 3.55 V Vnom = 4.0 V Vmax = 4.4 V It must be able to provide sufficient current up to 5.0 A. It is suggested to add a TVS diode for surge protection. VPH_PWR 420, 421, 424 PO Power supply for Vnom = VBAT Keep on. peripherals IOmax = 1500 mA 1.5 A in total. SG560D_Series_Hardware_Design 25 / 134 Smart Module Series When using it, it is recommended to add 14.7 F bypass capacitors with a total capacitance not exceeding 18.8 F. When using it, it is recommended to with a total capacitance not exceeding 14.1 F. When using it, it is recommended to add 14.7 F bypass capacitors with a total capacitance not exceeding 18.8 F. When using it, it is recommended to LDO7C_3V0 412 PO

(3.0 V output for sensors and TP) 3.0 V output Vnom = 3.0 V IOmax = 600 mA LDO13C_2V8 409 PO

(2.8 V output for 2.8 V output LCM) LDO18B_1V8 336 PO

(1.8 V output for I/O 1.8 V output pull-up) Vnom = 2.8 V add 14 F bypass IOmax = 150 mA capacitors with a total capacitance not exceeding 4 F. Keep on. When using it, it is recommended to Vnom = 1.8 V add 14.7 F IOmax = 20 mA bypass capacitors LDO17B_1V8 408 PO

(1.8 V output for I/O 1.8 V output power supply) 1.8 V output Vnom = 1.8 V IOmax = 600 mA LDO12C_1V8 109 PO

(1.8 V output for I/O Vnom = 1.8 V add 14 F bypass power supply of IOmax = 150 mA capacitors with a LCM) 1.8 V output LDO8C_1V8 112 PO

(1.8 V output for sensors) Vnom = 1.8 V IOmax = 150 mA total capacitance not exceeding 4 F. When using it, it is recommended to add 14.7 F bypass capacitors with a total capacitance not exceeding 18.8 F. LDO3C_3V0 624 PO 3.0 V output Vnom = 3.0 V When using them,

(reserved power) IOmax = 150 mA it is recommended SG560D_Series_Hardware_Design 26 / 134 LDO2C_1V8 626 PO 1.8 V output Vnom = 1.8 V

(reserved power) IOmax = 150 mA Smart Module Series to add 14 F bypass capacitors with a total capacitance not exceeding 4 F. VRTC 312 PIO Power supply for RTC Vmin = 2.0 V Vnom = 3.0 V Vmax = 3.25 V 6, 810, 12, 13, 22, 23, 32, 34, 35, 37, 39, 46, 47, 5658, 7678, 8185, 8791, 93, 96, 97, 100, 101, 105, 108, 114, 115, 118, 125, 127, 129, 132, 143, 146, 171, 179, 182, 204206, 208, 209, 212218, 221, 224, 225, 228230, 233237, 239241, 243, 245, GND 246, 248250, 252, 253, 255, 257, 260, 261, 264266, 269273, 275277, 279, 281, 282, 284, 285, 288290, 293, 295297, 299301, 303, 304, 313, 316, 334, 335, 344, 350, 359, 361364, 367, 371, 379, 381, 382, 387, 394, 404406, 411, 413, 414, 416, 417, 425428, 433580, 592, 595, 604, 623 Battery Detection Pin Name Pin No. I/O Description DC Characteristics Comment BAT_P BAT_M 418 419 AI AI Battery voltage detect (+) Battery voltage detect (-) BAT_THERM 407 AI Battery temperature detect BAT_ID 410 AI Battery ID detect Turn On/Off Must be connected. Internally pulled up. Supports 100 k NTC thermistor by default. Connect it to 100 k NTC thermistor. If not used, connect it to GND with a 100 k resistor. If not used, keep it unconnected. Pin Name Pin No. I/O Description DC Characteristics Comment PWRKEY VOL_DOWN VOL_UP 332 333 329 DI DI DI Turn on/off the module Volume down 1.8 V Volume up SG560D_Series_Hardware_Design 27 / 134 USB Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment Smart Module Series USB_VBUS 429432 PIO USB0_DP 354 AIO USB0_DM 358 AIO Vmax = 12.6 V Vmin = 3.7 V Vnom = 5.0 V USB/charger insertion detection Charging power input Power output for OTG device USB0 2.0 differential data (+) USB0 2.0 differential data (-) USB 3.1 channel 1 USB0_SS1_TX_P 360 AO SuperSpeed transmit (+) USB 3.1 channel 1 USB0_SS1_TX_M 357 AO SuperSpeed transmit (-) USB 3.1 channel 1 USB0_SS1_RX_P 356 AI SuperSpeed receive (+) USB 3.1 channel 1 USB0_SS1_RX_M 353 AI SuperSpeed receive (-) USB 3.1 channel 2 USB0_SS2_TX_P 348 AO SuperSpeed transmit (+) USB 3.1 channel 2 USB0_SS2_TX_M 345 AO SuperSpeed transmit (-) USB 3.1 channel 2 USB0_SS2_RX_P 352 AI SuperSpeed receive (+) USB 3.1 channel 2 USB0_SS2_RX_M 349 AI SuperSpeed receive (-) The maximum output current in OTG mode is 1.5 A. Requires differential impedance of 90 . Complies with USB 2.0 specification. Supports OTG. Requires differential impedance of 90 . Complies with USB 3.1 Gen 1 specification. USB_VCONN 375 PI Power supply for Vmax =4.5 V E-Mark cables Vmin = 3.0 V Externally connected to VPH_PWR or SG560D_Series_Hardware_Design 28 / 134 Smart Module Series dedicated boost converter. When Micro-USB mode is used, this pin can be used as USB_ID. When USB Type-C mode is used, connect it to SS_DIR_OUT. When Micro-USB mode is used, this pin should be connected to the ground through a 1 k resistor. When USB Type-C mode is used, keep it unconnected. When Micro-USB mode is used, it should be connected to ground. Requires differential impedance of 90 . Complies with USB 2.0 specification. Only supports host mode. USB0_CC1 339 AI USB0_CC2 342 AI USB Type-C detect 1 USB Type-C detect 2 USB_PHY_PS 338 DI CC status detection SS_DIR_OUT 341 DO CC status output USB_OPTION 337 AI Initial configuration for mode selection when powering up USB USB1_DP 622 AIO USB1 2.0 differential data (+) USB1_DM 621 AIO USB1 2.0 differential data (-) USB0_DP_AUX_P 620 AIO auxiliary channel Displayport USB0_DP_AUX_M 619 AIO PCIe Interface

(+) Displayport auxiliary channel (-) SG560D_Series_Hardware_Design 29 / 134 Pin Name Pin No. I/O Description DC Characteristics Comment Smart Module Series PCIE1_REFCLK_P 594 AIO PCIE1_REFCLK_ M 593 AIO PCIE1_RX0_P 597 PCIE1_RX0_M 596 PCIE1_RX1_P 599 PCIE1_RX1_M 598 AI AI AI AI PCIE1_TX0_P 601 AO PCIe1 reference clock (+) PCIe1 reference clock (-) PCIe1 recive 0 (+) PCIe1 recive 0 (-) PCIe1 recive 1 (+) PCIe1 recive 1 (-) PCIe1 transmit 0

(+) PCIE1_TX0_M 600 AO PCIe1 transmit 0 (-) PCIE1_TX1_P 603 AO PCIe1 transmit 1

(+) PCIE1_TX1_M 602 AO PCIe1 transmit 1 (-) PCIE1_RST_N 605 DO PCIe1 reset PCIE1_CLKREQ_ N 606 DI PCIe1 clock request 1.8 V PCIE1_WAKE_N 607 DI PCIe1 wake up LCM Interface Requires differential impedance of 85 . Pin Name Pin No. I/O Description DC Characteristics Comment DSI_CLK_P DSI_CLK_N 366 370 AO LCD MIPI clock (+) AO LCD MIPI clock (-) DSI_LN0_P 380 AO DSI_LN0_N 377 AO DSI_LN1_P 376 AO DSI_LN1_N 373 AO DSI_LN2_P 372 AO LCD MIPI lane 0 data (+) LCD MIPI lane 0 data (-) LCD MIPI lane 1 data (+) LCD MIPI lane 1 data (-) LCD MIPI lane 2 data (+) Requires differential impedance of 85 . SG560D_Series_Hardware_Design 30 / 134 Smart Module Series DSI_LN2_N 369 AO DSI_LN3_P 368 AO DSI_LN3_N 365 AO LCD MIPI lane 2 data (-) LCD MIPI lane 3 data (+) LCD MIPI lane 3 data (-) LCD_TE 374 DI LCD tearing effect LCD_RST 378 DO LCD reset Camera Interfaces 1.8 V External pull-up is not required. Pin Name Pin No. I/O Description DC Characteristics Comment CSI0_CLK_P CSI0_CLK_N CSI0_LN0_P CSI0_LN0_N CSI0_LN1_P CSI0_LN1_N CSI0_LN2_P CSI0_LN2_N CSI0_LN3_P CSI0_LN3_N CAM0_MCLK CAM0_RST CSI1_CLK_P CSI1_CLK_N CSI1_LN0_P 14 18 16 17 20 21 24 25 28 29 30 26 38 42 40 AI AI AI AI AI AI AI AI AI AI MIPI CSI0 clock (+) MIPI CSI0 clock (-) MIPI CSI0 lane 0 data (+) MIPI CSI0 lane 0 data (-) MIPI CSI0 lane 1 data (+) MIPI CSI0 lane 1 data (-) MIPI CSI0 lane 2 data (+) MIPI CSI0 lane 2 data (-) MIPI CSI0 lane 3 data (+) MIPI CSI0 lane 3 data (-) DO Master clock of camera 0 DO Reset of camera 0 1.8 V AI AI AI MIPI CS1 clock (+) MIPI CSI1 clock (-) MIPI CSI1 lane 0 data (+) Requires differential impedance of 85 . Requires differential impedance of 85 . SG560D_Series_Hardware_Design 31 / 134 CSI1_LN0_N CSI1_LN1_P CSI1_LN1_N CSI1_LN2_P CSI1_LN2_N CSI1_LN3_P CSI1_LN3_N CAM1_MCLK CAM1_RST CSI2_CLK_P CSI2_CLK_N 41 44 45 48 49 52 53 54 50 390 386 CSI2_LN0_P 392 CSI2_LN0_N 389 CSI2_LN1_P 388 CSI2_LN1_N 385 CSI2_LN2_P 396 CSI2_LN2_N 393 CSI2_LN3_P 400 CSI2_LN3_N 397 Smart Module Series AI AI AI AI AI AI AI MIPI CSI1 lane 0 data (-) MIPI CSI1 lane 1 data (+) MIPI CSI1 lane 1 data (-) MIPI CSI1 lane 2 data (+) MIPI CSI1 lane 2 data (-) MIPI CSI1 lane 3 data (+) MIPI CSI1 lane 3 data (-) DO Master clock of camera 1 DO Reset of camera 1 1.8 V AI AI AI AI AI AI AI AI AI AI MIPI CSI2 clock (+) MIPI CSI2 clock (-) MIPI CSI2 lane 0 data (+) MIPI CSI2 lane 0 data (-) MIPI CSI2 lane 1 data (+) MIPI CSI2 lane 1 data (-) MIPI CSI2 lane 2 data (+) MIPI CSI2 lane 2 data (-) MIPI CSI2 lane 3 data (+) MIPI CSI2 lane 3 data (-) Master clock of camera 2 1.8 V Requires differential impedance of 85 . CAM2_MCLK 398 DO CAM2_RST 384 DO Reset of camera 2 CSI3_CLK_P 62 AI MIPI CSI3 clock (+) Requires SG560D_Series_Hardware_Design 32 / 134 Smart Module Series differential impedance of 85 . CSI3_CLK_N CSI3_LN0_P CSI3_LN0_N CSI3_LN1_P CSI3_LN1_N CSI3_LN2_P CSI3_LN2_N CSI3_LN3_P CSI3_LN3_N CAM3_MCLK CAM3_RST 66 60 61 68 69 64 65 72 73 74 67 AI MIPI CSI3 clock (-) AI AI AI AI AI AI AI AI MIPI CSI3 lane 0 data (+) MIPI CSI3 lane 0 data (-) MIPI CSI3 lane 1 data (+) MIPI CSI3 lane 1 data (-) MIPI CSI3 lane 2 data (+) MIPI CSI3 lane 2 data (-) MIPI CSI3 lane 3 data (+) MIPI CSI3 lane 3 data (-) DO Master clock of camera 3 DO Reset of camera 3 1.8 V VREG_L1P_1P05 116 PO DVDD for cameras Vnom = 1.05 V When using them, 1 and 2 IOmax = 600 mA it is recommended VREG_L2P_1P1 121 PO DVDD for cameras Vnom = 1.1 V 0 and 3 IOmax = 600 mA to add bypass capacitors with a total capacitance not exceeding 45.3 F. VREG_L3P_2P8 113 PO 1 and 3 AVDD for cameras Vnom = 2.8 V VREG_L4P_2P9 124 PO AVDD for camera 0 VREG_L5P_2P8 128 PO AFVDD for camera Vnom = 2.8 V to add bypass IOmax = 300 mA Vnom = 2.9 V IOmax = 300 mA When using them, it is recommended IOmax = 300 mA capacitors with a total capacitance not exceeding 19 F. Vnom = 1.8 V IOmax = 300 mA Vnom = 2.8 V IOmax = 300 mA 0 DOVDD for VREG_L6P_1P8 117 PO cameras 0, 1, 2 and 3 VREG_L7P_2P8 120 PO AVDD for camera 2

(U)SIM Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment SG560D_Series_Hardware_Design 33 / 134 Smart Module Series Either 1.8 V or 2.95 V (U)SIM card is supported and can be identified automatically by USIM1_VDD 160 PO

(U)SIM1 card power supply Vmin = 1.65 V the module. Vmax = 3.05 V When using it, it is Imax = 150 mA recommended to USIM1_DATA 165 DIO

(U)SIM1 card data USIM1_CLK USIM1_RST 164 162 DO

(U)SIM1 card clock DO

(U)SIM1 card reset 1.8/2.95 V USIM1_DET 159 DI

(U)SIM1 card hot-swap detect 1.8 V add bypass capacitors with a total capacitance not exceeding 3 F. Pull it up to USIM1_VDD with an external 20 k resistor. Active low. Pull it up to 1.8 V externally. If not used, keep it unconnected. Disabled by default, and can be enabled via software configuration. Either 1.8 V or 2.95 V (U)SIM card is supported and can be identified automatically by USIM2_VDD 172 PO

(U)SIM2 card power supply Vmin = 1.65 V the module. Vmax = 3.05 V When using it, it is Imax = 150 mA recommended to add bypass capacitors with a total capacitance not exceeding 3 F. SG560D_Series_Hardware_Design 34 / 134 USIM2_DATA 169 DIO

(U)SIM2 card data USIM2_CLK USIM2_RST 168 166 DO

(U)SIM2 card clock DO

(U)SIM2 card reset 1.8/2.95 V USIM2_DET 163 DI

(U)SIM2 card detect 1.8 V Smart Module Series Pull it up to USIM2_VDD with an external 20 k resistor. Active low. Pull it up to 1.8 V externally. If not used, keep it unconnected. Disabled by default, and can be enabled via software configuration. SD Card Interface Pin Name Pin No. I/O Description DC Characteristics Comment SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 188 180 184 185 177 181 DO SD card clock DIO SD card command DIO SDIO data bit 0 DIO SDIO data bit 1 DIO SDIO data bit 2 DIO SDIO data bit 3 1.8/2.95 V Control characteristic impedance as 45 . SD_DET 174 DI SD card hot-swap detect 1.8 V SD_LDO9C 176 PO Power supply for Vnom = 2.95 V SD card IOmax = 600 mA Active low by default. External 1.8 V pull-up is required. When using it, it is recommended to add 14.7 F bypass capacitors with a total capacitance not exceeding 18.8 F. SD_LDO6C 173 PO SD card pull-up Vnom = 1.8/2.95 V Only for SD card SG560D_Series_Hardware_Design 35 / 134 Smart Module Series power supply;

IOmax = 150 mA pull-up. When 1.8/2.95 V output using it, it is recommended to add 13 F bypass capacitors with a total capacitance not exceeding 3 F. UART Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment DBG_TXD 317 DO DBG_RXD 320 DI Debug UART transmit Debug UART receive UART_TXD UART_RXD 308 309 DO UART transmit 1.8 V DI UART receive UART_RTS 305 DO DCE request to send UART_CTS 306 DI DCE clear to send I2C Interfaces Cannot be multiplexed into generic GPIOs. If not used, keep them unconnected. If not used, keep them unconnected. Pin Name Pin No. I/O Description DC Characteristics Comment 192 189 OD I2C serial clock OD I2C serial data I2C0_SCL I2C0_SDA LPI_SENSOR_ I2C1_SDA LPI_SENSOR_ I2C1_SCL LPI_SENSOR_ I2C2_SDA LPI_SENSOR_ I2C2_SCL 152 OD 149 OD 153 OD 156 OD CCI_I2C_SDA2 71 CCI_I2C_SCL2 70 OD OD CCI_I2C_SDA1 401 OD I2C data 1 for external sensor I2C clock 1 for external sensor I2C data 2 for external sensor I2C clock 2 for external sensor I2C data of cameras 2 and 3 I2C clock of cameras 2 and 3 I2C data of camera 1 1.8 V 1.8 V External 1.8 V pull-up is required. If not used, keep them unconnected. External 1.8 V pull-up is required. If not used, keep them unconnected. SG560D_Series_Hardware_Design 36 / 134 Smart Module Series CCI_I2C_SCL1 402 OD CCI_I2C_SDA0 33 CCI_I2C_SCL0 36 OD OD I2C clock of camera 1 I2C data of camera 0 I2C clock of camera 0 I2S Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment MI2S_MCLK MI2S_SCLK MI2S_WS MI2S_DATA0 MI2S_DATA1 142 140 137 133 136 DO I2S master clock DO I2S serial clock DO I2S word select DIO I2S data channel 0 DIO I2S data channel 1 LPI_MI2S_SCLK 138 DO LPI I2S serial clock LPI_MI2S_WS 139 DO LPI I2S word select 1.8 V LPI_MI2S_DATA0 135 DIO LPI_MI2S_DATA1 134 DIO LPI_MI2S_DATA2 130 DIO LPI_MI2S_DATA3 131 DIO LPI I2S data channel 0 LPI I2S data channel 1 LPI I2S data channel 2 LPI I2S data channel 3 CODEC_RST_N 126 DO Audio codec reset DMIC Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment LPI_DMIC1_CLK 144 DO LPI_DMIC1_DATA 141 DI LPI_DMIC2_CLK 145 DO LPI_DMIC2_DATA 148 DI LPI digital MIC1 clock LPI digital MIC1 data LPI digital MIC2 clock LPI digital MIC2 data 1.8 V SG560D_Series_Hardware_Design 37 / 134 Smart Module Series LPI_DMIC3_CLK 612 DO LPI_DMIC3_DATA 611 DI LPI digital MIC3 clock LPI digital MIC3 data TP Interface Pin Name Pin No. I/O Description DC Characteristics Comment TP_RST TP_INT TP_I2C_SCL 324 321 328 DO TP reset DI TP interrupt OD TP I2C clock 1.8 V TP_I2C_SDA 325 OD TP I2C data SPI Interface External 1.8 V pull-up is required. If not used, keep them unconnected. Pin Name Pin No. I/O Description DC Characteristics Comment SPI_CLK SPI_CS 197 193 DO SPI clock DO SPI chip select SPI_MISO 196 DI SPI_MOSI 194 DO SPI master-in slave-out SPI master-out slave-in ADC Interfaces 1.8 V Supports master mode only. Pin Name Pin No. I/O Description DC Characteristics Comment ADC0 ADC1 ADC2 ADC3 PWM Interfaces 399 11 15 403 AI AI AI AI General-purpose ADC interface Maximum input voltage 1.8 V. Pin Name Pin No. I/O Description DC Characteristics Comment PWM2 PWM1 79 DO PWM output 2 1.8 V 340 DO PWM output 1 VPH_PWR Backlight control. SG560D_Series_Hardware_Design 38 / 134 Smart Module Series RGB Interfaces Pin No. Pin No. I/O Description DC Characteristics Comment RGB_BLU RGB_GRN RGB_RED NFC Interface*

59 55 63 AO RGB light-blue AO RGB light-green IOmax = 12 mA AO RGB light-red Pin No. Pin No. I/O Description DC Characteristics Comment NFC_CLK 95 DO NFC clock NFC_CLK_REQ 102 DI NFC clock request NFC_DWL_REQ 103 DO NFC download control request NFC_EN NFC_INT 98 99 DO NFC enable DI NFC interrupt 1.8 V NFC_I2C_SDA 106 OD NFC I2C data NFC_I2C_SCL 107 OD NFC I2C clock Sensor Interrupt Interfaces Internally pulled up by default. External 1.8 V pull-up is required. If not used, keep them unconnected. Pin No. Pin No. I/O Description DC Characteristics Comment ACCEL_GYRO_ INT1 ACCEL_GYRO_ INT2 Acceleration/

161 DI gyroscope sensor interrupt 1 Acceleration/

158 DI gyroscope sensor MAG_INT ALPS_INT HALL_INT 186 157 190 DI DI DI GPIO Interfaces interrupt 2 Geomagnetic sensor interrupt Light/proximity sensor interrupt Hall sensor interrupt 1.8 V Can be multiplexed into generic GPIOs. SG560D_Series_Hardware_Design 39 / 134 Pin No. Pin No. I/O Description DC Characteristics Comment Smart Module Series GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_12 GPIO_13 94 19 311 307 198 191 DIO DIO DIO DIO DIO DIO GPIO_14 183 DIO GPIO_15 187 DIO GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_24 GPIO_32 GPIO_33 GPIO_34 GPIO_35 GPIO_42 GPIO_43 GPIO_44 GPIO_45 GPIO_46 GPIO_47 111 110 122 119 43 351 170 315 178 318 155 202 203 207 319 DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO General-purpose input/output 1.8 V Wakeup. Wakeup. Do not pull it up during startup Do not pull it up during startup. Wakeup. Wakeup. Wakeup. Wakeup. Wakeup. Wakeup. SG560D_Series_Hardware_Design 40 / 134 GPIO_61 GPIO_62 51 322 DIO DIO GPIO_63 326 DIO GPIO_68 123 DIO GPIO_93 147 DIO GPIO_105 GPIO_106 GPIO_107 GPIO_108 GPIO_165 GPIO_166 GPIO_158 175 167 210 310 150 154 151 DIO DIO DIO DIO DIO DIO DIO RF Antenna Interface Smart Module Series Do not pull it up during startup. Wakeup. Do not pull it up during startup. Wakeup. Wakeup. Pin No. Pin No. I/O Description DC Characteristics Comment SG560D-CN:

5G NR (n1/

n3/n5/n8/n28 TRX, n41/n78/n79 TRX1)

& LTE LMHB TRX WCDMA B1/B5/B8 TRX SG560D-EU:

NR LMHB TRX0 +

n77/n78 TRX0 LTE LMHB TRX0 +

B42 TRX0 WCDMA B1/B5/B8 TRX GSM900/DCS1800 TRX SG560D-CN:

5G NR ANT0 211 AIO ANT1 244 AI SG560D_Series_Hardware_Design 41 / 134 Smart Module Series

(n1/n41/n78/n79 DRX MIMO) & LTE

(B1/B41 DRX MIMO) SG560D-EU:

NR MHB PRX AIO MIMO + n28 TRX0 LTE MHB PRX MIMO + B28 TRX0 SG560D-CN:

5G NR (n1 PRX MIMO, n41/n78/n79 TRX0) & LTE

(B1/B41 PRX MIMO) SG560D-EU:

NR LB DRX ANT3 292 AIO NR MHB (TX1 +

DRX MIMO) n5/n77/n78 TRX1 LTE LB DRX LTE MHB (TX1 +

DRX MIMO) B5/B42 TRX1 WCDMA B5/B8 DRX SG560D-CN:

5G NR

(n1/n3/n5/n8/n28/

n41/n78/n79 DRX)

& LTE (LB/MB/HB DRX) WCDMA B1/B5/B8 DRX SG560D-EU:

NR MHB DRX +

n77/n78 DRX MIMO + n28 TRX1 LTE MHB DRX +

B42 DRX MIMO +

B28 TRX1 WCDMA B1 DRX AI AIO ANT2 256 ANT_GNSS 302 Al GNSS antenna SG560D_Series_Hardware_Design 42 / 134 Smart Module Series ANT_WIFI/BT 92 AIO ANT_WIFI_MIMO 86 AIO Antenna Tuner Control Interfaces interface Wi-Fi/Bluetooth antenna interface Wi-Fi MIMO antenna interface GRFC_0 GRFC_1 242 238 DIO DIO General RF Controller 1.8 V Cannot be multiplexed into a generic GPIO. Other Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment FLASH_LED1 7 VIB_DRV_P 27 AO PO Flash/torch driver output IOmax = TBD Vibration motor Vmin = 1.50 V driver output control Vmax = 3.54 V USB_BOOT 200 DI into emergency download mode Force the module VILmax = 0.63 V VIHmin = 1.17 V Reserved Pins Pin Name Pin No. 31, 75, 80, 104, 195, 199, 201, 219, 220, 222, 223, 226, 227, 231, 232, 247, 251, 254, 258, 259, 262, 263, 267, 268, 274, 278, RESERVED 280, 283, 286, 287, 291, 294, 298, 314, 323, 327, 330, 331, 343, 346, 347, 355, 383, 391, 395, 415, 422, 423, 581591, 608610, 613618, 625, 627636 Comment Keep them unconnected. 2.6. EVB Kit To help you develop applications with the module, Quectel supplies an evaluation board with accessories to control or test the module. For more details, see document [1]. SG560D_Series_Hardware_Design 43 / 134 Smart Module Series 3 Operating Characteristics 3.1. Power Supply 3.1.1. Power Supply Pins SG560D series module provides five VBAT pins, which are dedicated for connection to external power supply. The power supply range of the module is 3.554.4 V, and the recommended value is 4.0 V. VPH_PWR is used for powering peripherals. Table 7: VBAT Pins Pin Name Pin No. I/O Description Min. Typ. Max. Unit VBAT 15 PIO Power supply for the module 3.55 4.0 4.4 V 3.1.2. Battery Charge and Management SG560D series module supports fully programmable switch-mode Li-ion battery charging. It can charge single-cell Li-ion and Li-polymer batteries. The switch-mode charging supports Quick Charge 2.0, 3.0 and 4.0, and the maximum charging current is 3.0 A. The battery charger of the module supports trickle charging, pre-charge, constant current charging and constant voltage charging modes. Trickle charging: when the battery voltage is below 2.1 V, a 75 mA trickle charging current is applied to the battery. Pre-charge: when the battery voltage is between 2.1 V and the pre-charge cut-off voltage (software progarmmable range: 2.73.4 V, default value: 3.0 V), the system enters pre-charge mode. The charging current is programmable between 100450 mA, 300 mA by default. Constant current mode (CC mode): when the battery voltage increases between the pre-charge cut-off voltage and constant current charing cut-off voltage (software progarmmable range: 3.64.4 V, default value: 4.4 V), the system switches to CC mode. The charging current is programmable between 503000 mA. The default charging current is 500 mA for USB charging and 3 A for adapter. Constant voltage mode (CV mode): when the battery voltage reaches the final value 4.4 V, the system switches to CV mode and the charging current decreases gradually. When the charging current reduces to about 100 mA, charging is completed. SG560D_Series_Hardware_Design 44 / 134 Smart Module Series Table 8: Pin Definition of Charging Interface Pin Name Pin No. I/O Description Comment USB_VBUS 429432 PIO USB/charger insertion detection;

charging power input;

Power output for OTG device VBAT 15 PIO Power supply for the module BAT_P BAT_M 418 419 AI AI Battery voltage detect (+) Battery voltage detect (-) BAT_THERM 407 AI Battery temperature detect BAT_ID 410 AI Battery ID detect The maximum output current in OTG mode is 1.5 A. It must be able to provide sufficient current up to 5.0 A. It is suggested to use a TVS diode for surge protection. Must be connected. Internally pulled up. Supports 100 k NTC thermistor by default. Connect it to 100 k NTC thermistor. If unused, connect it to GND with a 100 k resistor. If not used, keep it unconnected. SG560D series module supports battery temperature detection in the condition that the battery integrates a thermistor (100 k 1 % NTC thermistor with a B-constant of 4250 k 1 % by default) and the thermistor is connected to BAT_THERM. If BAT_THERM is not connected, there will be malfunctions such as battery charging failure, battery level display error. SG560D_Series_Hardware_Design 45 / 134 A reference design for the battery charging circuit is shown below. Smart Module Series Figure 2: Reference Circuit for Battery Charging Circuit Mobile devices such as mobile phones and handheld POS systems are powered by batteries. For different batteries, the charging and discharging curves must be modified correspondingly to achieve the best performance. If the thermistor is not available in the battery, or the adapter is utilized for powering the module, then you must connect BAT_THERM to GND via a 100 k resistor. Otherwise, the system may mistakenly judge that the battery temperature is abnormal, which will cause battery charging failure. BAT_P and BAT_M pins must be connected. Otherwise, the module will have abnormalities in voltage detection, as well as related turn-on/off and battery charging or discharging issues. 3.1.3. Reference Design for Power Supply The performance of the module largely depends on the power source. The power supply of the module should be able to provide sufficient current of 5 A at least. If the voltage difference between input and output is not too large, it is suggested that an LDO should be used for the module. If there is a large voltage difference between the input source and the desired output (VBAT), a buck converter is preferred to be used as the power supply. SG560D_Series_Hardware_Design 46 / 134 GNDBAT_THERMVBAT0 R100 FNTCVBAT4.7 F100 nFTVSTVS123USB_VBUSAdapter or USBSG560DBatteryGNDC1C2C3R1D1D2R3100 K 1% NTCBAT_PBAT_MBAT_IDBAT_IDR20 R4+C4C533 pF10 pF The following figure illustrates a reference design for +5 V input power source. Smart Module Series Figure 3: Reference Circuit of Power Supply 3.1.4. Requirements for Voltage Stability The recommended power supply value of the module is 4 V. The power supply performance, such as load capacity, voltage ripple, directly influences the modules performance and stability. Under ultimate conditions, the module may have a transient peak current of up to 5 A. If the power supply capability is not sufficient, there will be voltage drops, and if the voltage drops below 3.2 V, the module will be turned off automatically. Therefore, make sure the input voltage never drops below 3.2 V. Figure 4: Power Supply Limits During Burst Transmission To prevent the voltage from dropping below 3.2 V, it is recommended to connect a tantalum capacitor of about 100 F with low ESR (ESR 0.7 ) and reserve a multi-layer ceramic chip capacitor (MLCC) array due to its ultra-low ESR. It is recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) to compose the MLCC array, and place these capacitors close to VBAT pins. Additionally, add a 4.7 F capacitor in parallel. The width of VBAT trace should be no less than 5 mm. In principle, the longer the VBAT trace is, the wider it should be. SG560D_Series_Hardware_Design 47 / 134 DC_INC1C2U1INOUTENGNDADJ24135VBAT 100 nFC3470 FC4100 nFR2220K100KR3470 F470R51KR4R11%1%Power Supply (V)Burst TransmissionRippleDropBurst TransmissionLoad (A) In addition, in order to get a stable power source, it is suggested to use a TVS diode and place it as close to the VBAT pins as possible to enhance surge protection. The following figure shows the structure of the power supply. Smart Module Series Figure 5: Structure of Power Supply 3.2. Turn On Table 9: Pin Definition of PWRKEY Pin Name PWRKEY Pin No. 332 I/O DI Description Turn on/off the module The module can be turned on by driving the PWRKEY pin low for at least 1.6 s. PWRKEY is pulled up to 1.8 V internally. It is recommended to use an open drain/collector driver to control PWRKEY. A simple reference circuit is illustrated in the following figure. Figure 6: Turn On the Module Using Driving Circuit SG560D_Series_Hardware_Design 48 / 134 ModuleVBATVBATC1100 F+C24.7C5C333pFC410pFD1100 nFGND FPWRKEY 1.6 sMCUGPIOModuleTurn on pulse4.7K47KQ1 Another way to control the PWRKEY pin is to use a button directly. When you press the button, electrostatic strike may be generated from finger. Therefore, you must place a TVS component nearby the button for ESD protection. Additionally, a 1 k resistor is connected in series to PWRKEY for ESD protection. A reference circuit is shown in the following figure. Smart Module Series Figure 7: Turn On the Module Using Button The timing of turning on the module is illustrated in the following figure. Figure 8: Turn-on Timing NOTE 1. When the module is turned on for the first time, its turn-on timing may be different from that shown above. 2. Make sure that VBAT is stable before pulling down the PWRKEY pin. It is recommended to drive PWRKEY low after VBAT reaches 4.0 V and remains stable for 30 ms. PWRKEY pin cannot be pulled down all the time. SG560D_Series_Hardware_Design 49 / 134 PWRKEYModuleS1Close to S1TVS1KTurn-on pulseR1VBAT (Typ. 4.0 V)PWRKEY 1.6 sACTIVEOthersLDO18B_1V8 Smart Module Series 3.3. Turn Off/Restart The module can be turned off by driving the PWRKEY pin low for at least 3 s. If the PWRKEY pin is pulled low for at least 3 s, you can choose to turn off the module in the prompt window popped up. It is also possible to restart the module by driving the PWRKEY pin low for at least 8 s. If the PWRKEY pin is pulled low for at least 8 s, the module will execute a forced shut-down and then restart. The restart timing is illustrated in the following figure. Figure 9: Restart Timing 3.4. VRTC The RTC (Real Time Clock) can be powered by an external power source when the module is powered down and there is no power supply for the VBAT. The external power source can be a capacitor according to application demands. The following are reference circuit designs when an external battery is utilized for powering RTC. Figure 10: RTC Powered by a Rechargeable Cell Battery SG560D_Series_Hardware_Design 50 / 134 VBATPWRKEYOthers8 sHardware RestartCell BatteryModuleRTC CoreVRTC Smart Module Series Figure 11: RTC Powered by Capacitor If RTC fails, the module can synchronize time through the network after being powering up. The recommended input voltage range for VRTC is 2.03.25 V and the recommended typical value is 3.0 V. The average power consumption is 30 A when VBAT is disconnected. When powered by VBAT, the RTC error is 50 ppm. When powered by VRTC, the RTC error is 500 ppm. If a rechargeable battery is used, ESR of the battery should be less than 2 k. 3.5. Power Output The module supports output of regulated voltages for peripheral circuits. During application, it is recommended to connect a 30 pF and a 10 pF capacitor in parallel to suppress high-frequency noise. Table 10: Pin Definition of Power Suppy Interface Pin Name Pin No. I/O Description VPH_PWR 420, 421, 424 PO Power supply for peripherals LDO7C_3V0 412 PO 3.0 V output

(3.0 V output for sensors and TP) LDO13C_2V8 409 PO 2.8 V output

(2.8 V output for LCM) Comment Keep on. 1.5 A in total. When using it, it is recommended to add 14.7 F bypass capacitors with a total capacitance not exceeding 18.8 F. When using it, it is recommended to add 14 F bypass capacitors with a total capacitance not exceeding 4 F. SG560D_Series_Hardware_Design 51 / 134 Large Capacitance CapacitorModuleRTC CoreVRTCC LDO18B_1V8 336 PO 1.8 V output

(1.8 V output for I/O pull-up) LDO17B_1V8 408 PO 1.8 V output

(1.8 V output for I/O power supply) LDO12C_1V8 109 PO 1.8 V output

(1.8 V output for I/O power supply of LCM) LDO8C_1V8 112 PO 1.8 V output

(1.8 V output for sensors) LDO3C_3V0 624 PO LDO2C_1V8 626 PO 3.0 V output

(reserved power) 1.8 V output

(reserved power) VRTC 312 PIO Power supply for RTC USIM1_VDD 160 PO

(U)SIM1 card power supply USIM2_VDD 172 PO

(U)SIM2 card power supply Smart Module Series Keep on. When using it, it is recommended to add 14.7 F bypass capacitors with a total capacitance not exceeding 14.1 F. When using it, it is recommended to add 14.7 F bypass capacitors with a total capacitance not exceeding 18.8 F. When using it, it is recommended to add 14 F bypass capacitors with a total capacitance not exceeding 4 F. When using it, it is recommended to add 14.7 F bypass capacitors with a total capacitance not exceeding 18.8 F. When using them, it is recommended to add 14 F bypass capacitors with a total capacitance not exceeding 4 F. Either 1.8 V or 2.95 V

(U)SIM card is supported and can be identified automatically by the module. When using them, it is recommended to add bypass capacitors with a total capacitance not SG560D_Series_Hardware_Design 52 / 134 SD_LDO9C 176 PO Power supply for SD card SD_LDO6C 173 PO SD card pull-up power supply VREG_L1P_1P0 5 116 PO DVDD for cameras 1 and 2 VREG_L2P_1P1 121 PO DVDD for cameras 0 and 3 VREG_L3P_2P8 113 PO AVDD for cameras 1 and 3 VREG_L4P_2P9 124 PO AVDD for cameras 0 VREG_L5P_2P8 128 PO AFVDD for cameras 0 VREG_L6P_1P8 117 PO DOVDD for cameras 0, 1, 2 and 3 VREG_L7P_2P8 120 PO AVDD for camera 2 Smart Module Series exceeding 3 F. When using it, it is recommended to add 14.7 F bypass capacitors with a total capacitance not exceeding 18.8 F. Only for SD card pull-up. When using it, it is recommended to add 13 F bypass capacitors with a total capacitance not exceeding 3 F. When using them, it is recommended to add bypass capacitors with a total capacitance not exceeding 45.3 F. When using them, it is recommended to add bypass capacitors with a total capacitance not exceeding 19 F. SG560D_Series_Hardware_Design 53 / 134 Smart Module Series 4 Application Interfaces 4.1. USB Interfaces SG560D series module provides two USB interfaces: USB0 and USB1. USB0 complies with USB 3.1 Gen1 and USB 2.0 specifications and supports USB OTG. USB1 complies with USB 2.0 specification and only supports host mode. The module supports SuperSpeed (5 Gbps) for USB 3.1, and supports high-speed (480 Mbps), full-speed (12 Mbps) and low-speed (1.5 Mbps) for USB 2.0. USB0 can be used for AT command communication, data transmission, software debugging, firmware upgrade and vocie over USB. 4.1.1. USB0 Interface The following table shows the pin definition of USB0. Table 11: Pin Definition of USB0 Pin Name Pin No. I/O Description Comment USB_VBUS 429432 PIO USB/charger insertion detection. Charging power input. Power output for OTG device. USB0_DP 354 AIO USB 2.0 differential data (+) USB0_DM 358 AIO USB 2.0 differential data (-) USB0_SS1_TX_P 360 USB0_SS1_TX_M 357 USB0_SS1_RX_P 356 USB0_SS1_RX_M 353 AO AO AI AI USB 3.1 channel 1 SuperSpeed transmit (+) USB 3.1 channel 1 SuperSpeed transmit (-) USB 3.1 channel 1 SuperSpeed receive (+) USB 3.1 channel 1 SuperSpeed receive (-) The maximum output current in OTG mode is 1.5 A. Requires differential impedance of 90 . Complies with USB 2.0 specification. Supports OTG. Requires differential impedance of 90 . Complies with USB 3.1 Gen 1. specification. SG560D_Series_Hardware_Design 54 / 134 Smart Module Series USB0_SS2_TX_P 348 USB0_SS2_TX_M 345 USB0_SS2_RX_P 352 USB0_SS2_RX_M 349 AO AO AI AI USB 3.1 channel 2 SuperSpeed transmit (+) USB 3.1 channel 2 SuperSpeed transmit (-) USB 3.1 channel 2 SuperSpeed receive (+) USB 3.1 channel 2 SuperSpeed receive (-) USB_VCONN 375 PI Power supply for E-Mark cables USB0_CC1 339 AI USB Type-C detect 1 USB0_CC2 342 AI USB Type-C detect 2 USB_PHY_PS 338 DI CC status detection SS_DIR_OUT 341 DO CC status output USB_OPTION 337 AI Initial configuration for mode selection when powering up USB USB0_DP_AUX_P 620 AIO Displayport auxiliary channel (+) USB0_DP_AUX_M 619 AIO Displayport auxiliary channel (-) Externally connected to VPH_PWR or dedicated boost converter. When Micro-USB mode is used, this pin can be used as USB_ID. When USB Type-C mode is used, connect it to SS_DIR_OUT. When Micro-USB mode is used, this pin needs to be connected to ground through a 1 k resistor. When USB Type-C mode is used, keep it unconnected. When Micro-USB mode is used, it needs to be connected to ground. SG560D_Series_Hardware_Design 55 / 134 4.1.1.1. USB Type-C Mode A reference circuit of USB Type-C mode of USB0 is shown below. Smart Module Series Figure 12: USB Type-C Reference Circuit of USB0 4.1.1.2. Micro USB Mode USB Type-C mode is used on USB0 by default. Micro USB mode can be used via hardware configuration. A reference circuit of Micro USB mode of USB0 is shown below. Figure 13: Micro USB Reference Circuit of USB0 SG560D_Series_Hardware_Design 56 / 134 USB0_DPModuleUSB0_SS1_RX_PRX2+RX2-VBUSCC1D+D-TX2-TX2+CC2USB0_CC1USB0_CC2RX1+RX1-TX1+TX1-USB Type_CC6C7C8C9C10C11C12C13USB0_DMUSB_VBUSUSB0_SS1_RX_MUSB0_SS1_TX_PUSB0_SS1_TX_MUSB0_SS2_RX_PUSB0_SS2_RX_MUSB0_SS2_TX_PUSB0__TX_MSS2USB_PHY_PSSS_DIR_OUT0RUSB_OPTION220K220K220K220K330 nF330 nF220 nF220 nF330 nF330 nF220 nF220 nFUSB0_DPUSB0_DMModuleDPDMVBUSIDGND100 nF4.7 FUSB_VBUSUSB_PHY_PSUSB0_CC1USB_OPTION1KMicro USBSS_DIR_OUT Smart Module Series 4.1.1.3. DisplayPort Mode SG560D series module supports DisplayPort 1.4, which is implemented through USB Type-C interface and supports 4-lane interface with a resolution of 4K @ 60 fps. Pin mapping between USB Type-C interface and DisplayPort interface is defined as follows. Table 12: USB Type-C Mode and DisplayPort Mode Pin Mapping Phy_mode Port Select 10 Pin Name Type-C Receptable Pins

USB 3.1 only DP only Concurrent DP & USB 0 TX RX

1

TX RX

USB0_SS1_TX_P/M Tx1 USB0_SS1_RX_P/M Rx1 USB0_SS2_TX_P/M Tx2 USB0_SS2_RX_P/M Rx2 DP ML2 DP ML1 USB0_SS1_TX_P/M Tx1 DP ML3 DP ML0 USB0_SS1_RX_P/M Rx1 DP ML1 DP ML2 USB0_SS2_TX_P/M Tx2 DP ML0 DP ML3 USB0_SS2_RX_P/M Rx2 TX RX DP ML1 USB0_SS1_TX_P/M Tx1 DP ML0 USB0_SS1_RX_P/M Rx1 DP ML1 DP ML0 TX RX USB0_SS2_TX_P/M Tx2 USB0_SS2_RX_P/M Rx2 10 Port 0 and port 1 refer to the positive and negative selection of Type-C respectively. SG560D_Series_Hardware_Design 57 / 134 A reference circuit of the DisplayPort interface is given as follows. Smart Module Series Figure 14: DisplayPort Mode Reference Circuit 4.1.2. USB1 Interface The following table shows the pin definition of USB1 interface. Table 13: Pin Description of USB1 Interface Pin Name Pin No. I/O Description Comment USB1_DP 622 AIO USB1 2.0 differential data (+) USB1_DM 621 AIO USB1 2.0 differential data (-) Requires differential impedance of 90 . Complies with USB 2.0 specification. Only supports host mode. SG560D_Series_Hardware_Design 58 / 134 USB0_DPModuleUSB0_SS1_RX_PRX2+RX2-VBUSCC1D+D-TX2-TX2+CC2USB0_CC1USB0_CC2RX1+RX1-TX1+TX1-USB Type_CC6C7C8C9C10C11C12C13USB0_DMUSB_VBUSUSB0_SS1_RX_MUSB0_SS1_TX_PUSB0_SS1_TX_MUSB0_SS2_RX_PUSB0_SS2_RX_MUSB0_SS2_TX_PUSB0__TX_MSS2220K220K220K220K330 nF330 nF220 nF220 nF330 nF330 nF220 nF220 nFSBU1SBU2GPIO_7USB0_DP_AUX_MModuleOEHSD2+HSD2-100 nFUSB0_DP_AUX_P100 nFModuleSGM7227YMS10G/TRHSD1+HSD1-VDD_3V3VCCD+D-SSBU2SBU1VDD_3V3100K100K2.2KGPIO_8LDO18B_1V8 Smart Module Series 4.1.3. Design Principles for USB Interfaces Table 14: USB Trace Length Inside the Module Pin No. Signal Length (mm) Length Difference (P - M) 354 358 360 357 356 353 348 345 352 349 622 621 620 619 USB0_DP USB0_DM 35.95 35.48 USB0_SS1_TX_P 26.51 USB0_SS1_TX_M 26.65 USB0_SS1_RX_P 24.03 USB0_SS1_RX_M 24.13 USB0_SS2_TX_P 26.16 USB0_SS2_TX_M 26.30 USB0_SS2_RX_P 26.79 USB0_SS2_RX_M 26.67 USB1_DP USB1_DM 22.95 22.54 USB0_DP_AUX_P 21.41 USB0_DP_AUX_M 21.22 0.47

-0.14

-0.10

-0.14 0.12 0.41 0.19 To ensure USB performance, follow the following principles while designing the USB interface. It is important to route the USB signal traces as differential pairs with total grounding. The impedance of USB differential trace is 90 . The ground reference plane under the USB signals must be continuous without any cuts or any holes to ensure impedance continuity. Pay attention to the influence of junction capacitance of ESD protection components on USB data lines. Typically, the capacitance value should be less than 2 pF for USB 2.0 and less than 0.5 pF for USB 3.1. Keep the ESD protection components as close as possible to the USB connector. Do not route USB signal traces under crystals, oscillators, magnetic devices, audio signal, and RF signal traces. Route USB differential traces in inner-layer with ground shielding on not only upper and lower layers but also right and left sides. Do not route USB 3.1 signal traces under RF signal traces. Crossing or paralleling with RF signal SG560D_Series_Hardware_Design 59 / 134 Smart Module Series traces is forbidden. Isolation between USB 3.1 signals and RF signals should be more than 90 dB. Otherwise, the RF signals will be seriously affected. Ensure the trace length difference between TX_P and TX_M, as well as RX_P and RX_M of USB 3.1 does not exceed 0.7 mm. Ensure the trace length difference between USB 2.0 DP and USB 2.0 DM differential pair does not exceed 2 mm. For USB 3.1, the spacing between Rx and Tx signal traces should be three times the signal trace width. The spacing between USB 3.1 signal trace and other signal traces should be four times the signal trace width. For USB 2.0, the spacing between DP and DM signal traces should be three times the signal trace width. The spacing between USB 2.0 signal traces and other signal traces should be four times the signal trace width. 4.2. (U)SIM Interfaces The module provides two (U)SIM interfaces which meet ETSI and IMT-2000 requirements. Dual SIM Dual Standby is supported by default. Either 1.8 V or 2.95 V (U)SIM card is supported. Table 15: Pin Definition of (U)SIM Interfaces Pin Name Pin No. I/O Description Comment Either 1.8 V or 2.95 V

(U)SIM card is supported and can be identified automatically by the module. When using it, it is recommended to add bypass capacitors with a total capacitance not exceeding 3 F. Pull it up to USIM1_VDD with an external 20 k resistor. USIM1_VDD 160 PO

(U)SIM1 card power supply USIM1_DATA 165 DIO

(U)SIM1 card data USIM1_CLK USIM1_RST 164 162 DO

(U)SIM1 card clock DO

(U)SIM1 card reset SG560D_Series_Hardware_Design 60 / 134 USIM1_DET 159 DI

(U)SIM1 card hot-swap detect USIM2_VDD 172 PO

(U)SIM2 card power supply USIM2_DATA 169 DIO

(U)SIM2 card data USIM2_CLK USIM2_RST 168 166 DO

(U)SIM2 card clock DO

(U)SIM2 card reset USIM2_DET 163 DI

(U)SIM2 card detect Smart Module Series Active low. Pull it up to 1.8 V externally. If not used, keep it unconnected. Disabled by default, and can be enabled via software configuration. Either 1.8 V or 2.95 V

(U)SIM card is supported and can be identified automatically by the module. When using it, it is recommended to add bypass capacitors with a total capacitance not exceeding 3 F. Pull it up to USIM2_VDD with an external 20 k resistor. Active low. Pull it up to 1.8 V externally. If not used, keep it unconnected. Disabled by default, and can be enabled via software configuration. SG560D_Series_Hardware_Design 61 / 134 The following figure shows a reference design for (U)SIM interface with an 8-pin (U)SIM card connector. Smart Module Series Figure 15: Reference Circuit of (U)SIM Interface with 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_DET unconnected. A reference circuit for (U)SIM card interface with a 6-pin (U)SIM card connector is illustrated in the following figure. Figure 16: Reference Circuit of (U)SIM Interface with 6-Pin (U)SIM Card Connector To enhance the reliability and availability of the (U)SIM card in applications, please follow the criteria below in (U)SIM circuit design. Place the (U)SIM card connector as close to the module as possible. Keep the trace length as less than 200 mm as possible. Keep (U)SIM card signals away from RF and VBAT traces. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with surrounded ground. In addition, USIM_RST also needs to be shielded with surrounded ground. SG560D_Series_Hardware_Design 62 / 134 USIM_VDDUSIM_RSTUSIM_CLKUSIM_DATAUSIM_DET22 R100 nF (U)SIM Card ConnectorTVS array22 pFVCCRSTCLKIOVPPGNDModuleC122 pF22 pFC2C3C4D122 R22 RR1R2R3 20KR4GND100KR5LDO18B_1V8ModuleUSIM_VDDUSIM_RSTUSIM_CLKUSIM_DATA22 R22 R22 R100 nFTVS array22 pFVCCRSTCLKIOVPPGND22 pF22 pFC1D1R2R3R4C2C3C4USIM_DET (U)SIM Card Connector 20KR1GND Smart Module Series To offer good ESD protection, it is recommended to add a TVS diode array with a parasitic capacitance not exceeding 50 pF. The 22 resistors should be added in series between the module and the (U)SIM card to facilitate debugging. Add 22 pF capacitors parallel on USIM_DATA, USIM_CLK and USIM_RST signal traces to filter RF interference, and place them as close to the

(U)SIM card connector as possible. Please note that the (U)SIM peripheral circuit should be close to the (U)SIM card connector. The pull-up resistor on USIM_DATA can improve anti-jamming capability of the (U)SIM card. If the

(U)SIM card traces are too long, or the interference source is relatively close, it is recommended to add a pull-up resistor near the (U)SIM card connector. 4.3. SD Card Interface The module supports SD 3.0 protocol. The pin definition of the SD card interface is shown below. Table 16: Pin Definition of SD Card Interface Pin Name Pin No. I/O Description Comment SD_CLK SD_CMD 188 180 DO SD card clock DIO SD card command SD_DATA0 184 DIO SDIO data bit 0 SD_DATA1 185 DIO SDIO data bit 1 SD_DATA2 177 DIO SDIO data bit 2 SD_DATA3 181 DIO SDIO data bit 3 SD_DET 174 DI SD card hot-swap detect SD_LDO9C 176 PO Power supply for SD card SD_LDO6C 173 PO SD card pull-up power supply Control characteristic impedance as 45 . Active low by default. External 1.8 V pull-up is required. When using it, it is recommended to add 14.7 F bypass capacitors with a total capacitance not exceeding 18.8 F. Only for SD card pull-up. When using it, it is recommended to add 13 F bypass capacitors with a total capacitance not exceeding 3 F. SG560D_Series_Hardware_Design 63 / 134 A reference circuit for SD card interface is shown below. Smart Module Series Figure 17: Reference Circuit for SD Card Interface SD_LDO9C is a peripheral driver power supply for SD card. The maximum drive current is 600 mA. Because of the high drive current, it is recommended that the trace width is 0.6 mm or above. To ensure the stability of drive power, add a 4.7 F and a 33 pF capacitor in parallel near the SD card connector. SD_CMD, SD_CLK and SD_DATA[0:3] are all high speed signal traces. In PCB design, control the characteristic impedance of them as 45 , and do not cross them with other traces. It is recommended to route these traces on the inner layer of PCB, and keep them of the same length. Additionally, SD_CLK needs separate ground shielding. Layout guidelines:

Control impedance to 45 10 %, and add ground shielding. The trace length difference between SD_CLK and SD_CMD/SD_DATA[0:3] should be less than 2 mm. Trace length requirements: less than 150 mm for traces of 50 Mbps, less than 50 mm for traces of 140 Mbps. The spacing between signal lines should be 1.5 times the line width. The capacitive reactance of SD_DATA[0:3] traces should be less than 8 pF. Table 17: SD Card Signal Trace Length Inside the Module Pin No. 188 Signal SD_CLK Length (mm) 49.18 SG560D_Series_Hardware_Design 64 / 134 SD_CMD120KNM_51KSD_DATA3SD_DATA2LDO18B_1V8SD_CLKSD_DATA0SD_DETSD_DATA1P1-DAT2P2-CD/DAT3P3-CMDP4-VDDP5-CLKP8-DAT1GNDP6-VSSP7-DAT0DETECTIVEGNDGNDGND12345678910111213SD_LDO9C33R33R33R33R33R33R1K33 pF4.7 FSD_LDO6CModuleR1R2R3R4R5R6NM_51KNM_10KNM_51KNM_51KR7R8R9R10R11R12R13D1D2D3D4D5D6D7D8C1C2SD Card Connector Smart Module Series 49.16 49.46 49.79 49.42 49.64 180 184 185 177 181 SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 4.4. GPIO Interfaces The module has abundant GPIO interfaces with power domain of 1.8 V. The pin definition is listed below. Table 18: Pin Definition of GPIO Interfaces Pin Name Pin No. I/O Description Comment GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_12 GPIO_13 GPIO_14 94 19 311 307 198 191 183 DIO DIO DIO DIO DIO DIO DIO GPIO_15 187 DIO GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_24 111 110 122 119 43 DIO DIO DIO DIO DIO General-purpose input/output Wakeup. Wakeup. Do not pull it up during startup. Do not pull it up during startup;

Wakeup. Wakeup. Wakeup. SG560D_Series_Hardware_Design 65 / 134 GPIO_32 GPIO_33 GPIO_34 GPIO_35 GPIO_42 GPIO_43 GPIO_44 GPIO_45 GPIO_46 GPIO_47 GPIO_61 GPIO_62 GPIO_63 GPIO_68 351 170 315 178 318 155 202 203 207 319 51 322 326 123 DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO GPIO_93 147 DIO GPIO_105 GPIO_106 GPIO_107 GPIO_108 GPIO_165 GPIO_166 GPIO_158 175 167 210 310 150 154 151 DIO DIO DIO DIO DIO DIO DIO Smart Module Series Wakeup. Wakeup. Wakeup. Do not pull it up during startup. Wakeup. Do not pull it up during startup;

Wakeup. Wakeup. SG560D_Series_Hardware_Design 66 / 134 Smart Module Series 4.5. UART Interfaces The module supports up to eleven groups of UART interfaces. Two of them are default configurations, see Table 19 for details. Nine of them can be multiplexed from other interfaces, see Table 23 for details. Two default UART interfaces are:

UART: 4-wire UART interface, supports RTS and CTS hardware flow control, up to 4 Mbps. DBG_UART: 2-wire UART interface, dedicated for debugging. Pin definition of the UART interfaces is given as follows:

Table 19: Pin Definition of UART Interfaces Pin Name Pin No. I/O Description Comment DBG_TXD 317 DO Debug UART transmit DBG_RXD 320 DI Debug UART receive UART_TXD 308 DO UART transmit UART_RXD 309 DI UART receive UART_RTS 305 DO DCE request to send UART_CTS 306 DI DCE clear to send If not used, keep them unconnected. Cannot be multiplexed into generic GPIOs. If not used, keep them unconnected. UART is a 4-wire UART interface with 1.8 V power domain. A level-shifting chip should be used if your application is equipped with a 3.3 V UART interface. The following figure shows a reference design. Figure 18: Reference Circuit with Level-Shifting Chip (for UART) SG560D_Series_Hardware_Design 67 / 134 VCCAVCCBOEA1A2A3A4GNDB1B2B3B4LDO18B_1V8UART_RTSUART_RXDUART_CTSUART_TXDRTS_3.3VRXD_3.3VCTS_3.3VTXD_3.3VVDD_3V3C1100 pFC2U1100 pF A level translator and an RS-232 level-shifting chip are recommended to be added between the module and PC, as shown below. Smart Module Series Figure 19: Reference Circuit with RS232 Level-Shifting Chip (for UART) NOTE DBG_UART is similar to UART. For the reference design of DBG_UART, refer to that of UART. 4.6. I2C Interfaces The module provides up to sixteen groups of I2C interfaces. Five of them are dedicated I2C interfaces used for camera and sensor peripherals. Three of them are generic I2C interfaces that can be used for TP and NFC peripherals, see Table 20 for details. Eight of them can be multiplexed from other interfaces, see Table 23 for details. All I2C interfaces are open drain signals and therefore must be pulled up externally. The reference power domain is 1.8 V. The sensor I2C intreface only supports sensors of aDSP architecture. CCI_I2C signals are controlled by Linux Kernel code and support connection to video output related devices. Table 20: Pin Definition of I2C Interfaces Pin Name Pin No. I/O Description Comment I2C0_SCL 192 OD I2C serial clock I2C0_SDA 189 OD I2C serial data External 1.8 V pull-up is required. If not used, keep SG560D_Series_Hardware_Design 68 / 134 RTS_3.3VRXD_3.3VCTS_3.3VTXD_3.3VUART_RTSUART_RXDUART_CTSUART_TXDRTS_1.8VRXD_1.8VCTS_1.8VTXD_1.8VVCCAModuleGNDGND1.8 VVCCB3.3 VDIN1ROUT3ROUT2ROUT1DIN4DIN3DIN2DIN5R1OUTBFORCEON/FORCEOFF/INVALID3.3 VDOUT1DOUT2DOUT3DOUT4DOUT5RIN3RIN2RIN1VCCGNDOEDB-9RTSTXDCTSRXDGND Smart Module Series them unconnected. 1.8 V power domain. 1.8 V power domain. External 1.8 V pull-up is required. If not used, keep them unconnected. LPI_SENSOR_I2C1_ SDA LPI_SENSOR_I2C1_ SCL LPI_SENSOR_I2C2_ SDA LPI_SENSOR_I2C2_ SCL 152 OD I2C data 1 for external sensor 149 OD I2C clock 1 for external sensor 153 OD I2C data 2 for external sensor 156 OD I2C clock 2 for external sensor TP_I2C_SCL 328 OD TP I2C clock TP_I2C_SDA 325 OD TP I2C data NFC_I2C_SDA 106 OD NFC I2C clock NFC_I2C_SCL 107 OD NFC I2C data CCI_I2C_SDA0 CCI_I2C_SCL0 33 36 OD I2C data of camera 0 OD I2C clock of camera 0 CCI_I2C_SDA1 401 OD I2C data of camera 1 CCI_I2C_SCL1 402 OD I2C clock of camera 1 CCI_I2C_SDA2 CCI_I2C_SCL2 71 70 OD I2C data of camera 2 and 3 OD I2C clock of camera 2 and 3 4.7. SPI Interface The module supports up to ten groups of SPI interfaces. One of them is default configuration, and supports master mode only, see Table 21 for details. Nine of them can be multiplexed from other interfaces, see Table 23 for details. Table 21: Pin Definition of SPI Interface Pin Name Pin No. SPI_CLK SPI_CS SPI_MISO 197 193 196 I/O DO DO DI Description Comment SPI clock SPI chip select SPI master-in salve-out 1.8 V power doamin. Supports master mode only. SG560D_Series_Hardware_Design 69 / 134 SPI_MOSI 194 DO SPI master-out slave-in Smart Module Series 4.8. I2S Interfaces The module supports up to five groups of I2S interfaces. Two of them are default configurations, see Table 22 for details. Three of them can be multiplexed from other interfaces, see Table 25 for details. Table 22: Pin Definition of I2S Interfaces Pin Name Pin No. MI2S_MCLK MI2S_SCLK MI2S_WS MI2S_DATA0 MI2S_DATA1 LPI_MI2S_SCLK LPI_MI2S_WS LPI_MI2S_DATA0 LPI_MI2S_DATA1 LPI_MI2S_DATA2 LPI_MI2S_DATA3 CODEC_RST_N 142 140 137 133 136 138 139 135 134 130 131 126 I/O DO DO DO DIO DIO DO DO DIO DIO DIO DIO DO Description I2S master clock I2S serial clock I2S word select I2S data channel 0 I2S data channel 1 LPI I2S serial clock LPI I2S word select LPI I2S data channel 0 LPI I2S data channel 1 LPI I2S data channel 2 LPI I2S data channel 3 Audio codec reset SG560D_Series_Hardware_Design 70 / 134 Smart Module Series 4.9. UART/SPI/I2C/I2S Multiplexing Relationship UART/SPI/I2C multiplexing relationship is shown in the following table. Table 23: UART/SPI/I2C Multiplex Relationship Channel Pin No. Pin Name GPIO No. Multiplex Function UART SPI I2C 189 I2C0_SDA GPIO_0 UART00_CTS SPI00_MISO I2C00_SDA 192 I2C0_SCL GPIO_1 UART00_RTS SPI00_MOSI I2C00_SCL QUP0-SE0 605 PCIE1_RST_N GPIO_2 UART00_TXD SPI00_CLK 607 PCIE1_WAKE_N GPIO_3 UART00_RXD SPI00_CS0

QUP0-SE2 311 GPIO_8 GPIO_8 307 GPIO_9 GPIO_9

I2C02_SDA I2C02_SCL 198 GPIO_12 GPIO_12 UART03_CTS SPI03_MISO I2C03_SDA 191 GPIO_13 GPIO_13 UART03_RTS SPI03_MOSI I2C03_SCL 183 GPIO_14 GPIO_14 UART03_TXD SPI03_CLK 187 GPIO_15 GPIO_15 UART03_RXD SPI03_CS0

111 GPIO_16 GPIO_16 UART04_CTS SPI04_MISO I2C04_SDA 110 GPIO_17 GPIO_17 UART04_RTS SPI04_MOSI I2C04_SCL 122 GPIO_18 GPIO_18 UART04_TXD SPI04_CLK 119 GPIO_19 GPIO_19 UART04_RXD SPI04_CS0

351 GPIO_32 GPIO_32 UART10_CTS SPI10_MISO I2C10_SDA 170 GPIO_33 GPIO_33 UART10_RTS SPI10_MOSI I2C10_SCL 315 GPIO_34 GPIO_34 UART10_TXD SPI10_CLK 178 GPIO_35 GPIO_35 UART10_RXD SPI10_CS0

106 NFC_I2C_SDA*

GPIO_36 UART11_CTS SPI11_MISO I2C11_SDA 107 NFC_I2C_SCL*

GPIO_37 UART11_RTS SPI11_MOSI I2C11_SCL QUP0-SE3 QUP0-SE4 QUP1-SE0 QUP1-SE1 SG560D_Series_Hardware_Design 71 / 134 Smart Module Series QUP1-SE2 QUP1-SE3 98 NFC_EN*

GPIO_38 UART11_TXD SPI11_CLK 102 NFC_CLK_REQ* GPIO_39 UART11_RXD SPI11_CS0

103 NFC_DWL_REQ* GPIO_40 UART12_CTS SPI12_MISO I2C12_SDA 99 NFC_INT*

GPIO_41 UART12_RTS SPI12_MOSI I2C12_SCL 318 GPIO_42 GPIO_42 UART12_TXD SPI12_CLK 155 GPIO_43 GPIO_43 UART12_RXD SPI12_CS0

202 GPIO_44 GPIO_44 UART13_CTS SPI13_MISO I2C13_SDA 203 GPIO_45 GPIO_45 UART13_RTS SPI13_MOSI I2C13_SCL 207 GPIO_46 GPIO_46 UART13_TXD SPI13_CLK 319 GPIO_47 GPIO_47 UART13_RXD SPI13_CS0

306 UART_CTS GPIO_48 UART14_CTS SPI14_MISO I2C14_SDA 305 UART_RTS GPIO_49 UART14_RTS SPI14_MOSI I2C14_SCL 308 UART_TXD GPIO_50 UART14_TXD SPI14_CLK QUP1-SE4 309 UART_RXD GPIO_51 UART14_RXD SPI14_CS0 324 TP_RST GPIO_55 378 LCD_RST GPIO_54 98 NFC_EN*

GPIO_38

SPI14_CS1 SPI14_CS2 SPI14_CS3

325 TP_I2C_SDA GPIO_52 UART15_CTS SPI15_MISO I2C15_SDA 328 TP_I2C_SCL GPIO_53 UART15_RTS SPI15_MOSI I2C15_SCL QUP1-SE5 378 LCD_RST GPIO_54 UART15_TXD SPI15_CLK 324 TP_RST GPIO_55 UART15_RXD SPI15_CS0

196 SPI_MISO GPIO_56 UART16_CTS SPI16_MISO I2C16_SDA 194 SPI_MOSI GPIO_57 UART16_RTS SPI16_MOSI I2C16_SCL QUP1-SE6 197 SPI_CLK GPIO_58 UART16_TXD SPI16_CLK 193 SPI_CS GPIO_59 UART16_RXD SPI16_CS0 322 GPIO_62 GPIO_62

SPI16_CS1

SG560D_Series_Hardware_Design 72 / 134 Smart Module Series 326 GPIO_63 GPIO_63 308 UART_TXD GPIO_50

SPI16_CS2 SPI16_CS3

NOTE 1. The QUP SE channel can be used flexibly to support UART, SPI and I2C interfaces. 2. Note that one QUP SE channel cannot support two protocols at the same time. For example, QUP0-SE0 cannot support UART and I2C at the same time. If one interface only occupies parts of the pins in one QUP SE channel, then other pins in the channel can only be used as GPIOs. Table 24: I2S Multiplex Relationship Table Channel Pin No. Pin Name GPIO No. Multiplex Function I2S 144 141 145 148 142 140 137 133 136 175 167 210 310 190 158 LPI_DMIC1_CLK GPIO_150 LPI_I2S1_SCLK LPI_DMIC1_DATA GPIO_151 LPI_I2S1_WS LPI_DMIC2_CLK GPIO_152 LPI_I2S1_DATA0 LPI_DMIC2_DATA GPIO_153 LPI_I2S1_DATA1 MI2S_MCLK GPIO_96 PRI_MI2S_MCLK MI2S_SCLK GPIO_97 MI2S0_SCLK MI2S_WS GPIO_100 MI2S0_WS MI2S_DATA0 GPIO_98 MI2S0_DATA0 MI2S_DATA1 GPIO_99 MI2S0_DATA1 GPIO_105 GPIO_105 MI2S1_DATA1 GPIO_106 GPIO_106 MI2S1_SCLK GPIO_107 GPIO_107 MI2S1_DATA0 GPIO_108 GPIO_108 MI2S1_WS HALL_INT GPIO_101 MI2S2_SCLK ACCEL_GYRO_INT2 GPIO_102 MI2S2_DATA0 1 2 3 4 SG560D_Series_Hardware_Design 73 / 134 Smart Module Series 161 186 138 139 135 134 130 131 ACCEL_GYRO_INT1 GPIO_103 MI2S2_WS MAG_INT GPIO_104 MI2S2_DATA1 LPI_MI2S_SCLK GPIO_144 LPI_MI2S_SCLK LPI_MI2S_WS GPIO_145 LPI_MI2S_WS LPI_MI2S_DATA0 GPIO_146 LPI_MI2S_DATA0 LPI_MI2S_DATA1 GPIO_147 LPI_MI2S_DATA1 LPI_MI2S_DATA2 GPIO_148 LPI_MI2S_DATA2 LPI_MI2S_DATA3 GPIO_149 LPI_MI2S_DATA3 5 4.10. ADC Interfaces The module provides four analog-to-digital converter (ADC) interfaces that support up to 15-bit resolution. The pin definition is shown below. Table 25: Pin Definition of ADC Interfaces Pin Name Pin No. I/O Description Comment ADC0 ADC1 ADC2 ADC3 399 11 15 403 AI AI AI AI General-purpose ADC interface Maximum input voltage 1.8 V. SG560D_Series_Hardware_Design 74 / 134 Smart Module Series 4.11. LCM Interface The module provides one LCM interface based on MIPI_DSI standard. The interface supports one group of 4-lane high-speed differential data transmission with maximum speed rate of 2.5 Gbps/lane and supports FHD + (1200 2520 ) @144 fps. The pin definition of the LCM interface is shown below. Table 26: Pin Definition of LCM Interface Pin Name Pin No. I/O Description Comment PWM1 340 DO PWM output 1 Backlight control. DSI_CLK_P 366 AO LCD MIPI clock (+) DSI_CLK_N 370 AO LCD MIPI clock (-) DSI_LN0_P 380 AO LCD MIPI lane 0 data (+) DSI_LN0_N 377 AO LCD MIPI lane 0 data (-) DSI_LN1_P 376 AO LCD MIPI lane 1 data (+) DSI_LN1_N 373 AO LCD MIPI lane 1 data (-) DSI_LN2_P 372 AO LCD MIPI lane 2 data (+) DSI_LN2_N 369 AO LCD MIPI lane 2 data (-) DSI_LN3_P 368 AO LCD MIPI lane 3 data (+) DSI_LN3_N 365 AO LCD MIPI lane 3 data (-) Requires differential impedance of 85 . LCD_TE 374 DI LCD tearing effect 1.8 V power domain. LCD_RST 378 DO LCD reset 1.8 V power domain. External pull-up is not required. SG560D_Series_Hardware_Design 75 / 134 The following figure shows a reference design for LCM interface. Smart Module Series Figure 20: Reference Circuit for LCM Interface MIPI are high speed signal traces. It is recommended to add common-mode filters in series near the LCM connector to improve protection against electromagnetic radiation interference. It is recommended to read the LCM ID register through MIPI when compatible design with other displays is required. If several LCMs share the same IC, it is recommended that the LCM module factory should burn an OTP register to distinguish different screens. You can also connect the LCD_ID pin of LCM to the ADC pin of the module, but note that the output voltage of LCD_ID should not exceed the voltage range of the ADC pin. You can design external backlight driver circuit for LCM according to actual requirement. The reference design is shown in the figure below, in which PWM1 is used for backlight brightness adjustment. SG560D_Series_Hardware_Design 76 / 134 DSI_CLK_PLEDANCLEDKLPTENC (SDA-TP) VIO18NC (VTP-TP) DSI_LN3_PLCD_TELCD_RSTDSI_LN3_NDSI_LN2_P_CLK_NDSI_LN2_NRESETLCD_IDNC (SCL-TP) NC (RST-TP) NC (EINT-TP) GNDVCC28GNDMIPI_TDP3MIPI_TDN3GNDMIPI_TDP2MIPI_TDN2GNDMIPI_TDP1MIPI_TDN1GNDLDO13C_2V8LDO17B_1V8LCM_LED+LCM_LED-1234567891012131415161718192021222324252627MIPI_TDP0MIPI_TDN0GNDMIPI_TCPMIPI_TCN2928303456345634563456DSI_LN1_NDSI_LN1_PDSI_LN0_NDSI_LN0_P1234561112121212100 nF1 F 1 FModuleLCMFL1FL2FL3FL4FL5EMI filterC3C2C1NCGNDGNDGNDGNDADC31323334DSIGNDNM_0RLDO12C_1V80RR1R2NM_0R Smart Module Series Figure 21: LCM External Backlight Driver Reference Circuit 4.12. Touch Panel Interface The module provides one group of I2C interface for connection with Touch Panel (TP), and provides the corresponding power supply and interrupt pins for TP. The pin definition of touch panel interface is given below. Table 27: Pin Definition of Touch Panel Interface Description Comment Pin Name Pin No. TP_RST TP_INT TP_I2C_SCL TP_I2C_SDA 324 321 328 325 I/O DO DI OD TP reset TP interrupt TP I2C clock OD TP I2C data 1.8 V power domain. External 1.8 V pull-up is required. If not used, keep them unconnected. SG560D_Series_Hardware_Design 77 / 134 LCM_LED+Module2.2 FBacklight DriverLCM_LED-VPH_PWRC1PWM1GNDR110K A reference design for TP interface is shown below. Smart Module Series Figure 22: Reference Circuit for TP Interface 4.13. Camera Interfaces Based on the MIPI_CSI standard, the module provides four groups of 4-lane MIPI_CSI with maximum transmission rate of 2.5 Gbps/lane. The module supports two cameras (4-lane + 4-lane), or three cameras (4-lane + 4-lane + 4-lane), or four cameras (4-lane + 4-lane + 4-lane + 4-lane). The video and photo quality are determined by various factors such as the camera sensor, camera lens quality. Table 28: Pin Definition of Camera Interfaces Pin Name Pin No. I/O Description VREG_L1P_1P05 116 PO DVDD for cameras 1 and 2 VREG_L2P_1P1 121 PO DVDD for cameras 0 and 3 VREG_L3P_2P8 VREG_L4P_2P9 VREG_L5P_2P8 113 124 128 PO AVDD for cameras 1 and 3 PO AVDD for camera 0 PO AFVDD for camera 0 Comment When using them, it is recommended to add bypass capacitors with a total capacitance not exceeding 45.3 F. When using them, it is recommended to add bypass capacitors with SG560D_Series_Hardware_Design 78 / 134 TP_RSTTP_I2C_SCLTP_I2C_SDATP_INT1234564.7 F100nFModuleRESET 1.8 V SCL 1.8 VSDA 1.8 V INT 1.8 V GNDVDD TPC1C2D1D2D3D4D5LDO7C_3V0LDO18B_1V82.2KR1R22.2KGND Smart Module Series VREG_L6P_1P8 117 PO DOVDD for cameras 0, 1, 2 and 3 VREG_L7P_2P8 120 PO AVDD for camera 2 CSI0_CLK_P CSI0_CLK_N CSI0_LN0_P CSI0_LN0_N CSI0_LN1_P CSI0_LN1_N CSI0_LN2_P CSI0_LN2_N CSI0_LN3_P CSI0_LN3_N CAM0_MCLK CAM0_RST CSI1_CLK_P CSI1_CLK_N CSI1_LN0_P CSI1_LN0_N CSI1_LN1_P CSI1_LN1_N CSI1_LN2_P CSI1_LN2_N CSI1_LN3_P CSI1_LN3_N CAM1_MCLK 14 18 16 17 20 21 24 25 28 29 30 26 38 42 40 41 44 45 48 49 52 53 54 AI AI AI AI AI AI AI AI AI AI MIPI CSI0 clock (+) MIPI CSI0 clock (-) MIPI CSI0 lane 0 data (+) MIPI CSI0 lane 0 data (-) MIPI CSI0 lane 1 data (+) MIPI CSI0 lane 1 data (-) MIPI CSI0 lane 2 data (+) MIPI CSI0 lane 2 data (-) MIPI CSI0 lane 3 data (+) MIPI CSI0 lane 3 data (-) DO Master clock of camera 0 DO Reset of camera 0 AI AI AI AI AI AI AI AI AI AI MIPI CS1 clock (+) MIPI CSI1 clock (-) MIPI CSI1 lane 0 data (+) MIPI CSI1 lane 0 data (-) MIPI CSI1 lane 1 data (+) MIPI CSI1 lane 1 data (-) MIPI CSI1 lane 2 data (+) MIPI CSI1 lane 2 data (-) MIPI CSI1 lane 3 data (+) MIPI CSI1 lane 3 data (-) DO Master clock of camera 1 a total capacitance not exceeding 19 F. Requires differential impedance of 85 . Requires differential impedance of 85 . SG560D_Series_Hardware_Design 79 / 134 Smart Module Series Requires differential impedance of 85 . Requires differential impedance of 85 . CAM1_RST CSI2_CLK_P CSI2_CLK_N CSI2_LN0_P CSI2_LN0_N CSI2_LN1_P CSI2_LN1_N CSI2_LN2_P CSI2_LN2_N CSI2_LN3_P CSI2_LN3_N CAM2_MCLK CAM2_RST CSI3_CLK_P CSI3_CLK_N CSI3_LN0_P CSI3_LN0_N CSI3_LN1_P CSI3_LN1_N CSI3_LN2_P CSI3_LN2_N CSI3_LN3_P CSI3_LN3_N CAM3_MCLK CAM3_RST 50 390 386 392 389 388 385 396 393 400 397 398 384 62 66 60 61 68 69 64 65 72 73 74 67 DO Reset of camera 1 AI AI AI AI AI AI AI AI AI AI MIPI CSI2 clock (+) MIPI CSI2 clock (-) MIPI CSI2 lane 0 data (+) MIPI CSI2 lane 0 data (-) MIPI CSI2 lane 1 data (+) MIPI CSI2 lane 1 data (-) MIPI CSI2 lane 2 data (+) MIPI CSI2 lane 2 data (-) MIPI CSI2 lane 3 data (+) MIPI CSI2 lane 3 data (-) DO Master clock of camera 2 DO Reset of camera 2 AI AI AI AI AI AI AI AI AI AI MIPI CSI3 clock (+) MIPI CSI3 clock (-) MIPI CSI3 lane 0 data (+) MIPI CSI3 lane 0 data (-) MIPI CSI3 lane 1 data (+) MIPI CSI3 lane 1 data (-) MIPI CSI3 lane 2 data (+) MIPI CSI3 lane 2 data (-) MIPI CSI3 lane 3 data (+) MIPI CSI3 lane 3 data (-) DO Master clock of camera 3 DO Reset of camera 3 SG560D_Series_Hardware_Design 80 / 134 The following is a reference circuit for dual-camera applications. Smart Module Series Figure 23: Reference Circuit for Dual-Camera Applications SG560D_Series_Hardware_Design 81 / 134 VREG_L6P_1P8VREG_L4P_2P9 100 nF1 FEMIEMIEMIEMIEMIVREG_L5P_2P8AVDDAFVDDDVDDDOVDDCSI0_LN3_P1 FAVDDDOVDDVREG_L2P_1P1DVDDCSI0_LN3_NCSI0_LN2_PCSI0_LN2_NCSI0_LN1_PCSI0_LN1_NCSI0_LN0_PCSI0_LN0_NGPIO_12CAM0_MCLKCCI_I2C_SDA0CCI_I2C_SCL0CAM0_RSTCSI0_CLK_PCSI0_CLK_NCSI1_LN3_PCSI1_LN3_NCSI1_LN2_PCSI1_LN2_NCSI1_LN1_PCSI1_LN1_NCSI1_LN0_PCSI1_LN0_NGPIO_32CAM1_MCLKCAM1_RSTCSI1_CLK_PCSI1_CLK_NEMIEMIEMIEMIEMIVREG_L1P_1P05VREG_L3P_2P8100 nF2.2 F1 F100 nF1 F100 nF100 nF2.2 F2.2K2.2KCCI_I2C_SDA1CCI_I2C_SCL12.2K2.2K Camera connector Camera connector01 The following is a reference circuit for tri-camera applications. Smart Module Series Figure 24: Reference Circuit for Three-Camera Applications SG560D_Series_Hardware_Design 82 / 134 VREG_L6P_1P8VREG_L4P_2P9100 nF1 FEMIEMIEMIEMIEMIVREG_L5P_2P8AVDDAFVDDDVDDDOVDDCSI0_LN3_P1 FAVDDDOVDDVREG_L2P_1P1DVDDCSI0_LN3_NCSI0_LN2_PCSI0_LN2_NCSI0_LN1_PCSI0_LN1_NCSI0_LN0_PCSI0_LN0_NGPIO_12CAM0_MCLKCCI_I2C_SDA0CCI_I2C_SCL0CAM0_RSTCSI0_CLK_PCSI0_CLK_NCSI1_LN3_PCSI1_LN3_NCSI1_LN2_PCSI1_LN2_NCSI1_LN1_PCSI1_LN1_NCSI1_LN0_PCSI1_LN0_NGPIO_32CAM1_MCLKCAM1_RSTCSI1_CLK_PCSI1_CLK_NEMIEMIEMIEMIEMIVREG_L1P_1P05VREG_L3P_2P8100 nF2.2 F1 F100 nF1 F100 nF100 nF2.2 F2.2K2.2KCSI2_LN3_PCSI2_LN3_NCSI2_LN2_PCSI2_LN2_NCSI2_LN1_PCSI2_LN1_NCSI2_LN0_PCSI2_LN0_NGPIO_35CAM2_MCLKCAM2_RSTCSI2_CLK_PCSI2_CLK_NCCI_I2C_SDA2CCI_I2C_SCL2AVDDDOVDDDVDDVREG_L7P_2P8100nF1F2.2K2.2KEMIEMIEMIEMIEMICCI_I2C_SDA1CCI_I2C_SCL12.2K2.2KCamera 2 connectorCamera 1 connectorCamera 0 connector Smart Module Series 4.13.1. MIPI Design Considerations Special attention should be paid to the pin definition of LCM/camera connectors. Ensure that the module and the connectors are correctly connected. MIPI are high speed signal lines, supporting maximum data rate of 2.5 Gbps/lane. The differential impedance should be controlled to 85 . Additionally, it is recommended to route the traces on the inner layer of PCB, and do not cross them with other traces. For the same group of DSI or CSI signals, keep all MIPI traces of the same length. To avoid crosstalk, a distance of 1.5 times the trace width among MIPI signal traces is recommended. During impedance matching, do not connect GND on different planes so as to ensure impedance consistency. Make sure the reference ground plane for CSI/DSI is complete and integral without any cut or void. Route the camera CLK signals on the inner layer of the PCB and surround them with ground. Route CSI and DSI traces according to the following rules:

a) The intra-pair (P/N) spacing should be equal to the trace width. b) The inter-pair spacing should be 1.5 times the trace width. c) The spacing relative to other signal lines should be 2.5 times the trace width. Route MIPI traces according to the following rules:

a) Control the differential impedance to 85 10 %. b) Control intra-lane (P/N) length difference within 0.7 mm. c) Control inter-lane length difference within 2.1 mm. Table 29: Relationship Between CSI Rate and Line Length (D-PHY) Data Rate Cable Length (mm) Cable Insertion Loss (dB) Line Length (mm) 500 Mbps/Lane 750 Mbps/Lane 1.0 Gbps/Lane 1.5 Gbps/Lane 2.1 Gbps/Lane 76.2 152.4 76.2 152.4 76.2 152.4 76.2 152.4 76.2 152.4 2.5 Gbps/Lane 76.2

-0.5

-1

-0.7

-1.15

-0.75

-1.4

-0.9

-1.8

-1.3

-2.3

-2.1

< 260

< 190

< 210

< 155

< 200

< 125

< 145

< 60

< 170

< 90

< 210 SG560D_Series_Hardware_Design 83 / 134 Smart Module Series 152.4

-3.5

< 150 Table 30: Relationship Between DSI Rate and Line Length (D-PHY) Data Rate Cable Length (mm) Cable Insertion Loss (dB) Line Length (mm) 76.2 152.4 76.2 152.4 76.2 152.4 76.2 152.4 76.2 152.4 76.2 152.4 500 Mbps/Lane 750 Mbps/Lane 1.0 Gbps/Lane 1.5 Gbps/lane 2.1 Gbps/lane 2.5 Gbps/lane NOTE

-0.5

-1.0

-0.7

-1.15

-0.75

-1.4

-0.9

-1.8

-1.3

-2.3

-2.1

-3.5

< 280

< 210

< 210

< 150

< 200

< 100

< 135

< 40

< 150

< 80

< 70

< 0 1. The cable length listed above is an example with specified insertion loss. 2. The cable insertion loss can be obtained from the cable datasheet provided by the manufacturer. The cable insertion loss in the actual design should not be worse than those listed above. 3. The line length in the above table includes the length of the line inside the module. Table 31: Trace Length of MIPI Differential Pairs Inside the Module Pin No. Pin Name Length (mm) Length Difference (P - N) 370 366 DSI_CLK_N DSI_CLK_P 25.97 25.68

-0.29 SG560D_Series_Hardware_Design 84 / 134 Smart Module Series 377 380 373 376 369 372 365 368 18 14 17 16 21 20 25 24 29 28 42 38 41 40 45 44 49 DSI_LN0_N DSI_LN0_P DSI_LN1_N DSI_LN1_P DSI_LN2_N DSI_LN2_P DSI_LN3_N DSI_LN3_P CSI0_CLK_N CSI0_CLK_P CSI0_LN0_N CSI0_LN0_P CSI0_LN1_N CSI0_LN1_P CSI0_LN2_N CSI0_LN2_P CSI0_LN3_N CSI0_LN3_P CSI1_CLK_N CSI1_CLK_P CSI1_LN0_N CSI1_LN0_P CSI1_LN1_N CSI1_LN1_P CSI1_LN2_N 25.81 26.14 26.22 26.06 25.65 25.79 26.01 25.96 45.18 45.15 45.23 45.22 45.18 45.10 45.25 45.17 45.15 45.03 41.75 41.87 41.72 41.76 41.25 41.46 41.73 0.33

-0.16 0.14

-0.05

-0.03

-0.01

-0.08

-0.08

-0.12 0.12 0.04 0.21

-0.01 SG560D_Series_Hardware_Design 85 / 134 Smart Module Series 48 53 52 386 390 389 392 385 388 393 396 397 400 66 62 61 60 69 68 65 64 73 72 CSI1_LN2_P CSI1_LN3_N CSI1_LN3_P CSI2_CLK_N CSI2_CLK_P CSI2_LN0_N CSI2_LN0_P CSI2_LN1_N CSI2_LN1_P CSI2_LN2_N CSI2_LN2_P CSI2_LN3_N CSI2_LN3_P CSI3_CLK_N CSI3_CLK_P CSI3_LN0_N CSI3_LN0_P CSI3_LN1_N CSI3_LN1_P CSI3_LN2_N CSI3_LN2_P CSI3_LN3_N CSI3_LN3_P 41.72 41.70 41.74 40.54 40.69 40.69 40.86 40.84 40.93 40.51 40.71 41.01 40.85 39.49 39.43 39.33 39.38 39.36 39.35 39.41 39.46 39.47 39.34 0.04 0.15 0.17 0.09 0.20

-0.16

-0.06 0.05

-0.01 0.05

-0.13 SG560D_Series_Hardware_Design 86 / 134 Smart Module Series 4.14. Sensor Interfaces The module supports communication with sensors via I2C interface, and supports various sensors such as acceleration sensor, gyroscopic sensor, compass, light sensor and temperature sensor. Table 32: Pin Definition of Sensor Interfaces Pin Name Pin No. I/O Description Comment ACCEL_GYRO_INT1 161 ACCEL_GYRO_INT2 158 MAG_INT ALPS_INT HALL_INT 186 157 190 DI DI DI DI DI Acceleration/

gyroscope sensor interrupt 1 Acceleration/

gyroscope sensor interrupt 2 Geomagnetic sensor interrupt Light/proximity sensor interrupt Hall sensor interrupt Can be multiplexed into generic GPIOs. 1.8 V power domain. 4.15. Emergency Download Interface USB_BOOT is an emergency download interface. Pulling it up to LDO18B_1V8 during power-up will force the module into emergency download mode. This is an emergency option when failures such as abnormal start-up or running occur. For the convenient firmware upgrade and debugging in the future, please reserve this pin. Figure 25: Reference Circuit for Emergency Download Interface SG560D_Series_Hardware_Design 87 / 134 S1 ModuleUSB_BOOTR110KGNDLDO18B_1V8 Smart Module Series 4.16. PCIe Interface The module provides one PCIe interface, which supports 2-lane PCIe Gen 3 with data rate up to 8 Gbps. Table 33: Pin Definition of PCIe Interface Pin Name Pin No. I/O Description Comment PCIE1_REFCLK_P 594 AIO PCIe1 reference clock (+) PCIE1_REFCLK_M 593 AIO PCIe1 reference clock (-) PCIE1_RX0_P PCIE1_RX0_M PCIE1_RX1_P PCIE1_RX1_M PCIE1_TX0_P PCIE1_TX0_M PCIE1_TX1_P PCIE1_TX1_M PCIE1_RST_N 597 596 599 598 601 600 603 602 605 AI AI AI AI AO AO AO AO PCIe1 recive 0 (+) PCIe1 recive 0 (-) PCIe1 recive 1 (+) PCIe1 recive 1 (-) PCIe1 transmit 0 (+) PCIe1 transmit 0 (-) PCIe1 transmit 1 (+) PCIe1 transmit 1 (-) DO PCIe1 reset Requires differential impedance of 85 . PCIE1_CLKREQ_N 606 PCIE1_WAKE_N 607 DI DI PCIe1 clock request PCIe1 wake up 1.8 V power domain. Table 34: Trace Length of Differential Pairs Inside the Module Pin No. Signal Length (mm) Length Difference (P - M) 594 593 601 600 PCIE1_REFCLK_P PCIE1_REFCLK_M PCIE1_TX0_P PCIE1_TX0_M 19.72 19.65 28.37 28.39 0.07

-0.02 SG560D_Series_Hardware_Design 88 / 134 Smart Module Series 603 602 597 596 599 598 PCIE1_TX1_P PCIE1_TX1_M PCIE1_RX0_P PCIE1_RX0_M PCIE1_RX1_P PCIE1_RX1_M 34.28 34.61 19.32 19.17 21.40 21.30

-0.33 0.15 0.10 4.17. NFC Interface*

SG560D series module provides one NFC interface. Table 35: Pin Definition of NFC Interface Pin Name Pin No. NFC_CLK NFC_CLK_REQ NFC_DWL_REQ NFC_EN NFC_INT 95 102 103 98 99 I/O DO DI DO Description Comment NFC clock NFC clock request NFC download control request DO NFC enable DI NFC interrupt NFC_I2C_SDA 106 OD NFC I2C data NFC_I2C_SCL 107 OD NFC I2C clock Internally pulled up by default. External 1.8 V pull-up is required. If not used, keep them unconnected. SG560D_Series_Hardware_Design 89 / 134 Smart Module Series 5 RF Specifications Appropriate antenna type and design should be used with matched antenna parameters according to specific application. It is required to perform a comprehensive functional test for the RF design before mass production of terminal products. The entire content of this chapter is provided for illustration only. Analysis, evaluation and determination are still necessary when designing target products. 5.1. Cellular Network 5.1.1. Antenna Interfaces & Frequency Bands The pin definition is shown below:

Table 36: Pin Definition of Cellular Network Interfaces of SG560D-CN Pin Name Pin No. I/O Description ANT0 ANT1 ANT2 ANT3 211 244 256 292 AIO AI AI AIO 5G NR (n1/n3/n5/n8/n28 TRX, n41/n78/n79 TRX1) &

LTE LMHB TRX, WCDMA B1/B5/B8 TRX 5G NR (n1/n41/n78/n79 DRX MIMO) & LTE (B1/B41 DRX MIMO) 5G NR (n1/n3/n5/n8/n28/n41/n78/n79 DRX) & LTE

(LB/MB/HB DRX), WCDMA B1/B5/B8 DRX 5G NR (n1 PRX MIMO, n41/n78/n79 TRX0) & LTE

(B1/B41PRX MIMO) Table 37: Pin Definition of Cellular Network Interfaces of SG560D-EU Pin Name Pin No. I/O Description ANT0 211 AIO NR LMHB TRX0 + n77/n78 TRX0 LTE LMHB TRX0 + B42 TRX0 WCDMA B1/B5/B8 TRX GSM900/DCS1800 TRX SG560D_Series_Hardware_Design 90 / 134 Smart Module Series ANT1 244 AIO NR MHB PRX MIMO + n28 TRX0 LTE MHB PRX MIMO + B28 TRX0 ANT2 256 AIO NR MHB DRX + n77/n78 DRX MIMO + n28 TRX1 LTE MHB DRX + B42 DRX MIMO + B28 TRX1 WCDMA B1 DRX ANT3 292 AIO NR LB DRX NR MHB (TX1 + DRX MIMO) n5/n77/n78 TRX1 LTE LB DRX LTE MHB (TX1 + DRX MIMO) B5/B42 TRX1 WCDMA B5/B8 DRX Table 38: Operating Frequency of SG560D-CN Operating Frequency Transmit (MHz) Receive (MHz) LTE-FDD LTE-TDD UMTS 5G NR IMT (2100) 19201980 21102170 DCS (1800) 17101785 18051880 Cell (850) 824849 869894 EGSM (950) 880915 925960 700 APAC 703748 758803 B34 B38 B39 B40 20102025 20102025 25702620 25702620 18801920 18801920 23002400 23002400 B41/B41-XGP 24962690 24962690 n78 n79 33003800 33003800 44005000 44005000 B1 B3 B5 B8

B34 B38 B39 B40 B41

B1 n1

B5 B8

n3-

n5 n8 n28

n41 n78 n79 SG560D_Series_Hardware_Design 91 / 134 Table 39: Operating Frequency of SG560D-EU Operating Frequency Transmit (MHz) Receive

(MHz) GSM LTE-FDD LTE-TDD UMTS IMT (2100) 19201980 21102170

B1 B3 B5 B7 B8 B20 B28 B32 B38 B39 B40 17101785 18051880 DCS1800 B3 824849 869894 2500-2570 2620-2690

B5 B7 880915 925960 GSM900 B8 832862 791-821 703748 758803

1452-1496 25702620 25702620 18801920 18801920 23002400 23002400 B41/B41-XGP 24962690 24962690 B42 n77 n78 3400-3600 3400-3600 3300-4200 3300-4200 33003800 33003800

B20 B28 B32

Smart Module Series 5G NR n1 n3 n5 n7 n8 n20 n28

n38

n40 n41

n77 n78

B38 B39 B40 B41 B42

B1

B5

B8

5.1.2. Transmitting Power The following table shows the RF output power of the module. Table 40: Tx Power of SG560D-CN Mode Frequency Range Max. Min. WCDMA WCDMA bands 23 dBm 2 dB (Class 3)

< -50 dBm LTE LTE HPUE band (B41) 26 dBm 2 dB (Class 2)

< -40 dBm SG560D_Series_Hardware_Design 92 / 134 Smart Module Series Other LTE bands 23 dBm 2 dB (Class 3)

< -40 dBm 5G NR HPUE bands

(n41/n78/n79) 5G NR 26 dBm +2/-3 dB (Class 2)

< -40 dBm 11 Other 5G NR bands 23 dBm 2 dB (Class 3)

< -40 dBm 11 Table 41: Tx Power of SG560D-EU Mode Frequency Range Max. Min. GSM EGSM900 DCS1800 33 dBm 2 dB 5 dBm 5 dB 30 dBm 2 dB 0 dBm 5 dB WCDMA WCDMA bands 23 dBm 2 dB (Class 3)

< -50 dBm LTE 5G NR LTE HPUE band (B41) 26 dBm 2 dB (Class 2)

< -40 dBm Other LTE bands 23 dBm 2 dB (Class 3)

< -40 dBm 5G NR HPUE bands

(n41/n77/n78) 26 dBm +2/-3 dB (Class 2)

< -40 dBm 11 Other 5G NR bands 23 dBm 2 dB (Class 3)

< -40 dBm 11 5.1.3. Rx Sensitivity The following table shows conducted RF receiving sensitivity of the module. Table 42: Conducted RF Rx Sensitivity of SG560D-CN Mode Frequency Primary Diversity SIMO 12 3GPP (SIMO) WCDMA B1 WCDMA WCDMA B5

-110

-112.4

-110

-113 WCDMA B8

-111

-112.5 TBD TBD TBD

-106.7 dBm

-104.7 dBm

-103.7 dBm LTE LTE-FDD B1 (10 MHz)

-97.2

-97

-102.3

-96.3 dBm 11 For 5G NR frequency band, there are different minimum power standards under different channel bandwidths. For details, see clause 6.3.1 of TS 38.101-1 [2]. 12 For the SIMO receiving sensitivity, WCDMA and LTE B3/B5/B8/B34/B38/B39/B40 bands and 5G NR n28 are tested with 2 RX antennas, and LTE B1/B41 bands and 5G NR n1/n41/n78/n79 bands are tested with 4 RX antennas. SG560D_Series_Hardware_Design 93 / 134 Smart Module Series LTE-FDD B3 (10 MHz)

-97

-97 LTE-FDD B5 (10 MHz)

-99.5

-100.5 LTE-FDD B8 (10 MHz)

-98.5

-100 LTE- TDD B34 (10 MHz)

-98 LTE- TDD B38 (10 MHz)

-96.5

-98

-97

-100

-103

-102

-101

-93.3 dBm

-94.3 dBm

-93.3 dBm

-96.3 dBm

-99.5

-96.3 dBm LTE- TDD B39 (10 MHz)

-99

-98.5

-102

-96.3 dBm LTE- TDD B40 (10 MHz)

-97.3

-98

-100.5

-96.3 dBm LTE- TDD B41 (10 MHz)

-95

-96.5

-100.5

-94.3 dBm 5G NR FDD n1 (20 MHz)

-93.4 5G NR FDD n3 (20 MHz) TBD 5G NR FDD n5 (20 MHz) TBD 5G NR FDD n8 (20 MHz) TBD

-95 TBD TBD TBD

-100 TBD TBD TBD

-93.1 dBm

-90.8 dBm

-90.8 dBm

-90.0 dBm 5G NR 5G NR FDD n28 (20 MHz)

-97

-96.5

-99.5

-90.1 dBm 5G NR TDD n41 (100 MHz)

-84 5G NR TDD n78 (100 MHz)

-87.5

-87

-87

-91

-92

-84.0 dBm

-84.6 dBm 5G NR TDD n79 (100 MHz)

-87.5

-86.5

-92.5

-84.6 dBm Table 43: Conducted RF Rx Sensitivity of SG560D-EU (Unit:dBm) Mode Frequency Primary Diversity SIMO 13 3GPP (SIMO) GSM EGSM900 DCS1800

-109

-108

WCDMA WCDMA B1

-109.5

-110.5 WCDMA B5

-111

-112

-102.4

-102.4

-106.7

-104.7

TBD TBD 13 For the SIMO receiving sensitivity, WCDMA and LTE B5/B8/B20/B28/B32/B39 bands and 5G NR n5/n8/n20/n28 bands are tested with 2 RX antennas, and LTE B1/B3/B7/B38/B40/B41/B42 bands and 5G NR n1/n3/n7/n38/n40/n41/n77/n78 bands are tested with 4 RX antennas. SG560D_Series_Hardware_Design 94 / 134 Smart Module Series WCDMA B8

-110.5

-112 TBD

-103.7 LTE-FDD B1 (10 MHz)

-98 LTE-FDD B3 (10 MHz)

-97.5

-98.8

-98.2

-102.6

-96.3

-102.9

-93.3 LTE-FDD B5 (10 MHz)

-99.5

-100.5

-102.6

-94.3 LTE-FDD B7 (10 MHz)

-97.3

-98

-101.5

-94.3 LTE-FDD B8 (10 MHz)

-99

-100.5

-102.4

-93.3 LTE- FDD B20 (10 MHz)

-99.5

-100.5

-102.5

-93.3 LTE LTE- FDD B28 (10 MHz)

-98.4

-99.9 LTE- FDD B32 (10 MHz) TBD TBD LTE- TDD B38 (10 MHz)

-96 LTE- TDD B39 (10 MHz)

-98.5 LTE- TDD B40 (10 MHz)

-96.5 LTE- TDD B41 (10 MHz)

-95 LTE- TDD B42 (10 MHz)

-97.5 5G NR FDD n1 (20 MHz)

-95.6 5G NR FDD n3 (20 MHz)

-94.8

-98

-98

-97

-96

-98.5

-95.7

-94.3 5G NR FDD n5 (20 MHz)

-95.8

-95.8 5G NR FDD n7 (20 MHz)

-94.5 5G NR FDD n8 (20 MHz)

-95 5G NR 5G NR FDD n20 (20 MHz)

-96.5

-94.4

-94.8

-96.6 5G NR FDD n28 (30 MHz)

-93.4

-93 5G NR FDD n38 (40 MHz)

-91.3 5G NR FDD n40 (80 MHz)

-89.5 5G NR TDD n41 (100 MHz)

-87 5G NR TDD n77 (100 MHz)

-86.5

-91.4

-89.6

-87.2

-87.6

-102 TBD

-94.8

-95.3

-100.9

-96.3

-100.8

-96.3

-100

-96.3

-102.8

-94.3

-102.8

-95.0

-100.1

-93.8

-100.1

-90.8

-99.2

-99.1

-99.3

-99.2

-96

-96.4

-93.5

-91.5

-93.6

-90.8

-91.8

-90

-89.8

-90.8

-90.7

-87.6

-84.7

-85.1 SG560D_Series_Hardware_Design 95 / 134 5G NR TDD n78 (100 MHz)

-87.2

-87.7

-93.5

-85.6 Smart Module Series 5.1.4. Reference Design of Cellular Antenna Interfaces The module provides four RF antenna interfaces for antenna connection. It is recommended to reserve a -type matching circuit for better RF performance, and the -type matching components (a capacitor-resistor-capacitor group) should be placed as close to the antenna as possible. The capacitors are not mounted by default. Figure 26: Reference Circuit for RF Antenna Interfaces 5.2. GNSS The module integrates the IZat GNSS engine (Gen 9) which supports multiple positioning and navigation systems including GPS, GLONASS, BDS, Galileo, NavIC, QZSS, SBAS. With an embedded LNA, the module provides greatly improved positioning accuracy. 5.2.1. Antenna Interface & Frequency Bands The following table shows the pin definition, frequency, and performance of GNSS antenna interface. SG560D_Series_Hardware_Design 96 / 134 ANT_0R1 0 RC1ModuleMainantennaNMC2NMR2 0 RC3Diversity antennaNMC4NMANT_3 Smart Module Series Table 44: Pin Definition of GNSS Antenna Interface Pin Name ANT_GNSS Pin No. 302 I/O AI Description GNSS antenna interface Table 45: Operating Frequency Type Frequency Unit GPS/SBAS/QZSS 1575.42 1.023 (L1) 1176.45 1 0.23 (L5) GLONASS 1597.51605.8 Galileo BDS NAVIC 1575.42 2.046 (E1) 1176.45 10.23 (E5a) 1561.098 2.046 1176.45 10.23 (L5) MHz 5.2.2. GNSS Performance Table 46: GNSS Performance Parameter Description Acquisition Reacquisition Tracking Typ.

-146

-158

-159 Cold start @ open sky 33.21 Warm start @ open sky 22.84 Hot start @ open sky 0.92 CEP-50 2 Sensitivity

(GNSS) TTFF

(GNSS) Accuracy

(GNSS) Unit dBm s m SG560D_Series_Hardware_Design 97 / 134 Smart Module Series NOTE 1. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep positioning for at least 3 minutes continuously). 2. Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock within 3 minutes after loss of lock. 3. Acquisition sensitivity: the minimum GNSS signal power at which the module can fix position successfully within 3 minutes after executing cold start command. 5.2.3. Reference Design 5.2.3.1. Reference Design for GNSS Passive Antenna GNSS antenna interface supports passive ceramic antennas and other types of passive antennas. A reference circuit design is given below. Figure 27: Reference Circuit for GNSS Passive Antenna NOTE It is not recommended to add an external LNA when using a passive GNSS antenna. 5.2.3.2. Reference Design for GNSS Active Antenna In any case, it is recommended to use a passive antenna. If active antenna is indeed needed in your application, it is recommended to reserve a -type attenuation circuit and use high-performance LDO as the power supply. The active antenna is powered by a 56 nH inductor through the antenna's signal path. The common power supply voltage ranges from 3.3 V to 5.0 V. Although featuring low power consumption, the active antenna still requires stable and clean power supplies. It is recommended to use a high-performance LDO. A reference design of the GNSS active antenna is shown below. SG560D_Series_Hardware_Design 98 / 134 Passive AntennaModuleANT_GNSSNMC1C2R1C4NM0R Smart Module Series Figure 28: Reference Circuit for GNSS Active Antenna 5.2.3.3. GNSS RF Design Guidelines Improper design of antenna and layout may cause reduced GNSS receiving sensitivity, longer GNSS positioning time, or reduced positioning accuracy. To avoid this, follow the reference design rules as below:

Maximize the distance between the GNSS RF part and the cellular RF part (including trace routing and antenna layout) to avoid mutual interference. In user systems, GNSS RF signal traces and RF components should be placed far away from high-speed circuits, switch-mode power supplies, power inductors, the clock circuit of single-chip microcomputers, etc. For harsh electromagnetic environment or a design that requires better ESD protection, diodes with ultra-low junction capacitance such as 0.5 pF can be selected and added in the antenna interface. Otherwise, there will be effects on the impedance characteristic of the RF circuit loop or attenuation of the bypass RF signal may be caused. Control the impedance of either feeder line or PCB trace to 50 , and keep the trace length as short as possible. Refer to Chapter 5.5 for the GNSS reference circuit design. 5.3. Wi-Fi/Bluetooth (SG560D-WF) The module provides one shared antenna interface ANT_WIFI_BT to suppport Wi-Fi and Bluetooth functions. The interface impedance is 50 . You can connect external antennas such as PCB antenna, sucker antenna and ceramic antenna to the module via the interface to achieve Wi-Fi and Bluetooth functions. The module further provides one Wi-Fi antenna interface ANT_WIFI_MIMO to support Wi-Fi 2 2 MU-MIMO, tri-band 2.4 GHz, 5 GHz and 6 GHz function. The module complies with IEE 802.11a/b/g/n/ac/ax and supports Dual Band Simultaneous (DBS) with dual MAC. SG560D_Series_Hardware_Design 99 / 134 Active Antenna3V3ModuleANT_GNSS56 nH10 1 F100 pFC1R1L1C3C2100 pFR3R4R50 NMNM Smart Module Series 5.3.1. Antenna Interface & Frequency Bands Table 47: Pin Definition of Wi-Fi/Bluetooth Interfaces Pin Name Pin No. ANT_WIFI/BT ANT_WIFI_MIMO 92 86 I/O AIO AIO Description Wi-Fi/Bluetooth antenna interface Wi-Fi MIMO antenna interface Table 48: Wi-Fi/Bluetooth Frequency Type Wi-Fi 802.11a/b/g/n/ac/ax Bluetooth 5.2 LE Frequency 24022482 51805825 5925-7125 24022480 5.3.2. Wi-Fi Overview(SG560D-WF) Unit MHz MHz The module supports 2.4 GHz single-band, 2.4 GHz & 5 GHz dual-band and 2.4 GHz & 5 GHz & 6 GHz tri-band WLAN wireless communication based on IEEE 802.11a/b/g/n/ac/ax standard protocols. The maximum data rate is 3.6 Gbps. The features are as below:

Support Wake-on-WLAN (WoWLAN) Support ad hoc mode Support WAPI SMS4 hardware encryption Support AP and STA modes Support Wi-Fi Direct Support Dual Band Simultaneous (DBS) Support 20/40 MHz channel bandwidths for 2.4 GHz and 20/40/80/160 MHz channel bandwidths for 5 GHz and 6 GHz Support MCS 07 for HT20 and HT40 Support MCS 08 for VHT20 Support MCS 09 for VHT40 and VHT80 Support MCS 013 for HE20, HE40, HE80 and HE160 SG560D_Series_Hardware_Design 100 / 134 Smart Module Series The following table lists the Wi-Fi transmitting and receiving performance of the module. Table 49: Wi-Fi Transmitting Performance Frequency Standard Rate Output 802.11b 802.11b 802.11g 802.11g 1 Mbps 18 dBm 2.5 dB 11 Mbps 16 dBm 2.5 dB 6 Mbps 18 dBm 2.5 dB 54 Mbps 16 dBm 2.5 dB 802.11n HT20 MCS0 18 dBm 2.5 d B 802.11n HT20 MCS7 16 dBm 2.5 dB 802.11n HT40 MCS0 18 dBm 2.5 dB 802.11n HT40 MCS7 16 dBm 2.5 dB 802.11ax HE20 MCS0 18 dBm 2.5 dB 802.11ax HE20 MCS7 16 dBm 2.5 dB 802.11ax HE20 MCS9 15 dBm 2.5 dB 802.11ax HE20 MCS11 14 dBm 2.5 dB 802.11ax HE20 MCS13 13 dBm 2.5 dB 802.11ax HE40 MCS0 18 dBm 2.5 dB 802.11ax HE40 MCS7 16 dBm 2.5 dB 802.11ax HE40 MCS9 15 dBm 2.5 dB 802.11ax HE40 MCS11 14 dBm 2.5 dB 802.11ax HE40 MCS13 13 dBm 2.5 dB 802.11a 802.11a 6 Mbps 17 dBm 2.5 dB 54 Mbps 16 dBm 2.5 dB 802.11n HT20 MCS0 17 dBm 2.5 dB 802.11n HT20 MCS7 16 dBm 2.5 dB 2.4 GHz 5 GHz SG560D_Series_Hardware_Design 101 / 134 Smart Module Series 802.11n HT40 MCS0 16.5 dBm 2.5 dB 802.11n HT40 MCS7 15.5 dBm 2.5 dB 802.11ac VHT20 MCS0 17 dBm 2.5 dB 802.11ac VHT20 MCS8 16 dBm 2.5 dB 802.11ac VHT40 MCS0 16.5 dBm 2.5 dB 802.11ac VHT40 MCS9 15.5 dBm 2.5 dB 802.11ac VHT80 MCS0 15.5 dBm 2.5 dB 802.11ac VHT80 MCS9 14.5 dBm 2.5 dB 802.11ax HE20 MCS0 17 dBm 2.5 dB 802.11ax HE20 MCS7 16 dBm 2.5 dB 802.11ax HE20 MCS9 15 dBm 2.5 dB 802.11ax HE20 MCS11 14 dBm 2.5 dB 802.11ax HE20 MCS13 13 dBm 2.5 dB 802.11ax HE40 MCS0 16.5 dBm 2.5 dB 802.11ax HE40 MCS7 15.5 dBm 2.5 dB 802.11ax HE40 MCS9 14.5 dBm 2.5 dB 802.11ax HE40 MCS11 13.5 dBm 2.5 dB 802.11ax HE40 MCS13 12.5 dBm 2.5 dB 802.11ax HE80 MCS0 15.5 dBm 2.5 dB 802.11ax HE80 MCS7 14.5 dBm 2.5 dB 802.11ax HE80 MCS9 13.5 dBm 2.5 dB 802.11ax HE80 MCS11 12.5 dBm 2.5 dB 802.11ax HE80 MCS13 11.5 dBm 2.5 dB 802.11ax HE160 MCS0 14.5 dBm 2.5 dB 802.11ax HE160 MCS7 13.5 dBm 2.5 dB SG560D_Series_Hardware_Design 102 / 134 Smart Module Series 802.11ax HE160 MCS9 12.5 dBm 2.5 dB 802.11ax HE160 MCS11 11.5 dBm 2.5 dB 802.11ax HE160 MCS13 10.5 dBm 2.5 dB 802.11a 802.11a 6 Mbps 8.5 dBm 2.5 dB 54 Mbps 7.5 dBm 2.5 dB 802.11ax HE20 MCS0 8.5 dBm 2.5 dB 802.11ax HE20 MCS7 7.5 dBm 2.5 dB 802.11ax HE20 MCS9 6.5 dBm 2.5 dB 802.11ax HE20 MCS11 5.5 dBm 2.5 dB 802.11ax HE20 MCS13 4.5 dBm 2.5 dB 802.11ax HE40 MCS0 11 dBm 2.5 dB 802.11ax HE40 MCS7 10 dBm 2.5 dB 802.11ax HE40 MCS9 9 dBm 2.5 dB 6 GHz 802.11ax HE40 MCS11 8 dBm 2.5 dB 802.11ax HE40 MCS13 7 dBm 2.5 dB 802.11ax HE80 MCS0 14.5 dBm 2.5 dB 802.11ax HE80 MCS7 13.5 dBm 2.5 dB 802.11ax HE80 MCS9 12.5 dBm 2.5 dB 802.11ax HE80 MCS11 11.5 dBm 2.5 dB 802.11ax HE80 MCS13 10.5 dBm 2.5 dB 802.11ax HE160 MCS0 17.5 dBm 2.5 dB 802.11ax HE160 MCS7 16.5 dBm 2.5 dB 802.11ax HE160 MCS9 15.5 dBm 2.5 dB 802.11ax HE160 MCS11 14.5 dBm 2.5 d B 802.11ax HE160 MCS13 13.5 dBm 2.5 dB SG560D_Series_Hardware_Design 103 / 134 Table 50: Wi-Fi Receiving Performance Frequency Standard Rate Sensitivity Smart Module Series 802.11b 802.11b 802.11g 802.11g 802.11n HT20 802.11n HT20 802.11n HT40 802.11n HT40 1 Mbps

-96 dBm 11 Mbps

-87 dBm 6 Mbps

-91 dBm 54 Mbps

-73 dBm MCS0 MCS7 MCS0 MCS7 2.4 GHz 802.11ax HE20 MCS0 802.11ax HE20 MCS7 802.11ax HE20 MCS9 802.11ax HE20 MCS11 802.11ax HE20 MCS13 802.11ax HE40 MCS0 802.11ax HE40 MCS7 802.11ax HE40 MCS9 802.11ax HE40 MCS11 802.11ax HE40 MCS13 802.11a 802.11a 5 GHz 802.11n HT20 802.11n HT20 802.11n HT40 6 Mbps 54 Mbps

-70 dBm MCS0 MCS7 MCS0

-88 dBm

-70 dBm

-86 dBm

-90 dBm

-72 dBm

-87 dBm

-68 dBm

-89 dBm

-70dBm

-65 dBm

-60 dBm

-54 dBm

-86 dBm

-68 dBm

-63 dBm

-57 dBm

-50 dBm

-90 dBm SG560D_Series_Hardware_Design 104 / 134 Smart Module Series 802.11n HT40 MCS7 802.11ac VHT20 MCS0 802.11ac VHT20 MCS8 802.11ac VHT40 MCS0 802.11ac VHT40 MCS9 802.11ac VHT80 MCS0 802.11ac VHT80 MCS9 802.11ax HE20 MCS0 802.11ax HE20 MCS7 802.11ax HE20 MCS9 802.11ax HE20 MCS11 802.11ax HE20 MCS13 802.11ax HE40 MCS0 802.11ax HE40 MCS7 802.11ax HE40 MCS9 802.11ax HE40 MCS11 802.11ax HE40 MCS13 802.11ax HE80 MCS0 802.11ax HE80 MCS7 802.11ax HE80 MCS9 802.11ax HE80 MCS11 802.11ax HE80 MCS13 802.11ax HE160 MCS0 802.11ax HE160 MCS7 802.11ax HE160 MCS9

-66 dBm

-87 dBm

-66 dBm

-84 dBm

-64 dBm

-81 dBm

-60 dBm

-86 dBm

-68 dBm

-64 dBm

-60 dBm

-54 dBm

-83 dBm

-66 dBm

-62 dBm

-57 dBm

-51 dBm

-80 dBm

-62 dBm

-58 dBm

-54 dBm

-48 dBm

-78 dBm

-61 dBm

-55 dBm SG560D_Series_Hardware_Design 105 / 134 802.11ax HE160 MCS11 802.11ax HE160 MCS13 802.11a 802.11a 6 Mbps 54 Mbps

-70 dBm Smart Module Series

-49 dBm

-43 dBm

-89 dBm 802.11ax HE20 MCS0 802.11ax HE20 MCS7 802.11ax HE20 MCS9 802.11ax HE20 MCS11 802.11ax HE20 MCS13 802.11ax HE40 MCS0 802.11ax HE40 MCS7 802.11ax HE40 MCS9 6 GHz 802.11ax HE40 MCS11 802.11ax HE40 MCS13 802.11ax HE80 MCS0 802.11ax HE80 MCS7 802.11ax HE80 MCS9 802.11ax HE80 MCS11 802.11ax HE80 MCS13 802.11ax HE160 MCS0 802.11ax HE160 MCS7 802.11ax HE160 MCS9 802.11ax HE160 MCS11 802.11ax HE160 MCS13

-85 dBm

-67 dBm

-63 dBm

-59 dBm

-53 dBm

-83 dBm

-65 dBm

-61 dBm

-56 dBm

-51 dBm

-80 dBm

-62 dBm

-57 dBm

-52 dBm

-47 dBm

-77 dBm

-60 dBm

-55 dBm

-49 dBm

-43 dBm SG560D_Series_Hardware_Design 106 / 134 Smart Module Series NOTE The module conforms to the IEEE specifications. 5.3.3. Bluetooth Overview The module supports Bluetooth 5.2 (BR/EDR+BLE) specification, as well as GFSK, 8-DPSK, /4-DQPSK modulation modes. Maximally support up to 7-lane wireless connections. Maximally support up to 3.5 Piconets at the same time. Support one SCO or eSCO connection. The BR/EDR channel bandwidth is 1 MHz, and can accommodate 79 channels. The BLE channel bandwidth is 2 MHz, and can accommodate 40 channels. Table 51: Bluetooth Data Rate and Version Version Data Rate Maximum Application Throughput 1.2 2.0 + EDR 3.0 + HS 4.0 5.0 5.1 5.2 1 Mbit/s 3 Mbit/s 24 Mbit/s 24 Mbit/s 48 Mbit/s TBD TBD Referenced specifications are listed below:

> 80 kbit/s

> 80 kbit/s Refer to 3.0 + HS Refer to 4.0 LE Refer to 5.0 LE Refer to 5.1 LE Refer to 5.2 LE Bluetooth Radio Frequency TSS and TP Specification 1.2/2.0/2.0 + EDR/2.1/2.1+ EDR/3.0/3.0 + HS, August 6, 2009 Bluetooth Low Energy RF PHY Test Specification, RF-PHY.TS/4.0.0, December 15, 2009 Bluetooth 5.0 RF-PHY Cover Standard: RF-PHY.TS.5.0.0, December 06, 2016 SG560D_Series_Hardware_Design 107 / 134 Smart Module Series Table 52: Bluetooth Transmitting and Receiving Performance Transmitter Performance Packet Types DH5 2-DH5 3-DH5 Transmitting Power 10 2.5 dBm 8 2.5 dBm 8 2.5 dBm Receiver Performance Packet Types DH5 Receiving Sensitivity

-93 dBm 5.3.4. Reference Design 2-DH5

-92 dBm 3-DH5

-86 dBm A reference circuit design for Wi-Fi/Bluetooth antenna interface is shown as below. C1 and C2 are not mounted and a 0 resistor is mounted on R1 by default. Figure 29: Reference Circuit for Wi-Fi/Bluetooth Antenna A reference circuit design for Wi-Fi MIMO antenna interface is shown as below. C3 and C4 are not mounted and a 0 resistor is mounted on R2 by default. Figure 30: Reference Circuit for Wi-Fi MIMO Antenna SG560D_Series_Hardware_Design 108 / 134 ANT_WIFI/BTR1 0RC1ModuleNMC2NMANT_WIFI_MIMOR2 0RC3ModuleNMC4NM Smart Module Series 5.4. Reference Design of RF Routing When designing PCB, characteristic impedance of all RF traces should be controlled to 50 . Generally, the impedance of RF traces is determined by materials dielectric constant, trace width (W), spacing between RF traces and grounds (S) and height from the reference ground to the signal layer (H). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB structures when characteristic impedance of RF traces is controlled to 50 . Figure 31: Microstrip Design on a 2-layer PCB Figure 32: Coplanar Waveguide Design on a 2-layer PCB Figure 33: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) SG560D_Series_Hardware_Design 109 / 134 Smart Module Series Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure better RF performance and reliability, the following conditions should be complied with in RF layout design:

Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 . GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground. Clearance between RF pins and RF connector should be as short as possible, and all right-angle

(90) traces should be changed to the ones with the angle of 135. There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, ground vias around RF traces and the reference ground can improve RF performance. The clearance between ground vias and RF traces should be at least twice the width of RF signal traces (2 W). Keep RF traces away from interference sources, and avoid intersection and paralleling between any traces on adjacent layers. For more details about RF layout, see document [2]. SG560D_Series_Hardware_Design 110 / 134 Smart Module Series 5.5. Antenna Installation 5.5.1. Antenna Design Requirement Requirements for antenna design are as follows:

Table 53: Antenna Design Requiremets Antenna Type Requirements GNSS GSM/UMTS/LTE/5G NR Wi-Fi/Bluetooth Frequency range:

L1: 15591609 MHz L5: 11661187 MHz Polarization: RHCP or linear VSWR: 2 (Typ.) For passive antenna application:

Passive antenna gain: > 0 dBi For active antenna application:

Passive antenna gain: > 0 dBi Active antenna noise figure: < 1.5 dB Active antenna gain: > -2 dBi Active antenna embedded LNA gain: < 17 dB VSWR: 2 Gain: 1 dBi Max Input Power: 50 W Input Impedance: 50 Polarization Type: Vertical Cable insertion loss:

< 1 dB: LB (<1 GHz)

< 1.5 dB: MB (12.3 GHz)

< 2 dB: HB (> 2.3 GHz) VSWR: 2 Gain: 1 dBi Max Input Power: 50 W Input Impedance: 50 Polarization Type: Vertical Cable Insertion Loss:

< 1 dB: LB (<1 GHz) SG560D_Series_Hardware_Design 111 / 134 Smart Module Series 5.5.2. RF Connector Recommendation If RF connector is used for antenna connection, it is recommended to use U.FL-R-SMT connector provided by Hirose. Figure 35: Dimensions of the Receptacle (Unit: mm) U.FL-LP series mated plugs listed in the following figure can be used to match the U.FL-R-SMT connector. Figure 36: Specifications of Mated Plugs (Unit: mm) SG560D_Series_Hardware_Design 112 / 134 The following figure describes the space factor of mated connector. Smart Module Series Figure 37: Space Factor of Mated Connectors (Unit: mm) Please visit http://www.hirose.com for more information. SG560D_Series_Hardware_Design 113 / 134 Smart Module Series 6 Electrical Characteristics and Reliability 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 54: Absolute Maximum Ratings Parameter VBAT USB_VBUS Min.

-0.5

-0.3 Peak current of VBAT

Voltage on digital pins

-0.3 Max. 4.8 12.6 TBD 2.1 Unit V V A V 6.2. Power Supply Ratings Table 55: Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT VBAT The actual input voltages must stay between the minimum and maximum values. USB_VBUS USB/charger insertion detection;

3.55 4 4.4 V 3.7 5.0 12.6 V SG560D_Series_Hardware_Design 114 / 134 Smart Module Series Charging power input Power output for OTG device VRTC Power supply for RTC

2.0 3.0 3.25 V 6.3. Power Consumption Table 56: Power Consumption of SG560D-CN Mode OFF state Sleep state

(USB disconnected) Conditions Power down WCDMA PF = 64 WCDMA PF = 128 WCDMA PF = 256 WCDMA PF = 512 LTE-FDD PF = 32 LTE-FDD PF = 64 LTE-FDD PF = 128 LTE-FDD PF = 256 LTE-TDD PF = 32 LTE-TDD PF = 64 LTE-TDD PF = 128 LTE-TDD PF = 256 5G NR FDD PF = 32 5G NR FDD PF = 64 5G NR FDD PF = 128 Typ. 196 6.5 6.1 5.8 5.7 8.6 6.9 6.2 5.8 8.7 6.8 6.2 5.9 10.8 8.3 7.1 Unit A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA SG560D_Series_Hardware_Design 115 / 134 Smart Module Series 5G NR FDD PF = 256 5G NR TDD PF = 32 5G NR TDD PF = 64 5G NR TDD PF = 128 5G NR TDD PF = 256 B1 @ max power WCDMA voice calls B5 @ max power B8 @ max power LTE-FDD B1 @ max power LTE-FDD B3 @ max power LTE-FDD B5 @ max power LTE-FDD B8 @ max power LTE data transmission LTE-TDD B34 @ max power LTE-TDD B38 @ max power LTE-TDD B39 @ max power LTE-TDD B40 @ max power LTE-TDD B41 @ max power B1 (HSDPA) @ max power WCDMA data transmission B5 (HSDPA) @ max power 5G NR SA data transmission B8 (HSDPA) @ max power n1 @ max power 40 MHz, SCS 15 kHz n3 @ max power 20 MHz, SCS 15 kHz n5 @ max power 20 MHz, SCS 15 kHz n8 @ max power 20 MHz, SCS 15 kHz 6.4 10.3 7.8 6.6 6.1 630 500 600 720 850 620 570 260 435 270 340 470 565 480 550 670 TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA SG560D_Series_Hardware_Design 116 / 134 n28 @ max power 30 MHz, SCS 15 kHz n41 @ max power 100 MHz, SCS 30 kHz n78 @ max power 100 MHz, SCS 30 kHz n79 @ max power 100 MHz, SCS 30 kHz DC_3A_n41A 100 MHz, SCS 30 kHz DC_39A_n41A 100 MHz, SCS 30 kHz DC_1A_n78A 100 MHz, SCS 30 kHz DC_3A_n78A 100 MHz, SCS 30 kHz DC_5A_n78A 100 MHz, SCS 30 kHz DC_8A_n78A 100 MHz, SCS 30 kHz DC_3A_n79A 100 MHz, SCS 30 kHz DC_39A_n79A 100 MHz, SCS 30 kHz n41 @ max power 100 MHz, SCS 30 kHz n78 @ max power 100 MHz, SCS 30 kHz n79 @ max power 100 MHz, SCS 30 kHz Smart Module Series 453 555 475 400 800 400 650 783 650 648 780 360 490 420 380 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 5G NR NSA data transmission 5G NR UL MIMO data transmission Table 57: Power Consumption of SG560D-EU Mode OFF state GSM/GPRS supply current Conditions Power down Sleep state (USB disconnected)

@ DRX = 2 Sleep state (USB disconnected)

@ DRX = 5 Typ. 203 7.67 6.39 Sleep state (USB disconnected) 5.94 Unit A mA mA mA SG560D_Series_Hardware_Design 117 / 134 Smart Module Series

@ DRX = 9 WCDMA PF = 64 WCDMA PF = 128 WCDMA PF = 256 WCDMA PF = 512 7.38 6.87 6.56 6.4 LTE-FDD PF = 32 10.07 LTE-FDD PF = 64 LTE-FDD PF = 128 LTE-FDD PF = 256 LTE-TDD PF = 32 LTE-TDD PF = 64 LTE-TDD PF = 128 LTE-TDD PF = 256 8.11 7.23 6.75 9.8 8.06 7.22 6.73 5G NR FDD PF = 32 10.84 5G NR FDD PF = 64 5G NR FDD PF = 128 5G NR FDD PF = 256 8.31 7.05 6.43 5G NR TDD PF = 32 10.05 5G NR TDD PF = 64 5G NR TDD PF = 128 5G NR TDD PF = 256 EGSM900 @ PCL 5 EGSM900 @ PCL 12 EGSM900 @ PCL 19 DCS1800 @ PCL 0 7.8 6.65 6.1 320 92 75 236 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Sleep state

(USB disconnected) GSM voice call SG560D_Series_Hardware_Design 118 / 134 Smart Module Series DCS1800 @ PCL 7 DCS1800 @ PCL 15 B1 @23dBm WCDMA voice calls B5 @22.87dBm B8 @22.9dBm 91 83 712 432 496 LTE-FDD B1 @ 22.48dBm 1029 LTE data transmission LTE-FDD B3 @ 22.69dBm LTE-FDD B5 @ 22.79dBm LTE-FDD B7 @ 22.65dBm LTE-FDD B8 @ 22.69dBm LTE-FDD B20 @ 22.63dBm LTE-FDD B28 @ 22.59dBm LTE-TDD B38 @ 22.7dBm LTE-TDD B39 @ 22.8dBm LTE-TDD B40 @ 22.86dBm LTE-TDD B41 @ 23.86dBm LTE-TDD B42 @ 22.9dBm B1 (HSDPA) @ 21.9dBm WCDMA data transmission B5 (HSDPA) @ 21.47dBm B8 (HSDPA) @ 21.55dBm 888 454 821 486 453 576 401 283 440 539 300 641 410 456 EGSM900 (1UL/4DL) @ PCL 5 330 EGSM900 (2UL/3DL) @ PCL 5 513 GPRS data transmission EGSM900 (3UL/2DL) @ PCL 5 657 EGSM900 (4UL/1DL) @ PCL 5 685 DCS1800 (1UL/4DL) @ PCL 0 260 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA SG560D_Series_Hardware_Design 119 / 134 EDGE data transmission 5G NR SA data transmission Smart Module Series DCS1800 (2UL/3DL) @ PCL 0 380 DCS1800 (3UL/2DL) @ PCL 0 397 DCS1800 (4UL/1DL) @ PCL 0 436 EGSM900 (1UL/4DL) @ PCL 8 188 EGSM900 (2UL/3DL) @ PCL 8 275 EGSM900 (3UL/2DL) @ PCL 8 309 EGSM900 (4UL/1DL) @ PCL 8 354 DCS1800 (1UL/4DL) @ PCL 2 165 DCS1800 (2UL/3DL) @ PCL 2 228 DCS1800 (3UL/2DL) @ PCL 2 256 DCS1800 (4UL/1DL) @ PCL 2 295 n1 @ 23dBm 20 MHz, SCS 15 kHz n3 @ 23dBm 20 MHz, SCS 15 kHz n5 @ 23dBm 20 MHz, SCS 15 kHz n7 @ 23.5dBm 20 MHz, SCS 15 kHz n8 @ 23dBm 20 MHz, SCS 15 kHz n20 @ 23dBm 20 MHz, SCS 15 kHz n28 @ 23dBm 20 MHz, SCS 15 kHz n38 @ 23dBm 20 MHz, SCS 30 kHz n40 @ 23dBm 20 MHz, SCS 30 kHz n41 @ 25dBm 100 MHz, SCS 30 kHz n77 @ 25dBm 100 MHz, SCS 30 kHz n78 @ 25dBm 100 MHz, SCS 30 kHz 994 749 454 747 506 421 544 280 306 357 304 308 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA SG560D_Series_Hardware_Design 120 / 134 5G NR NSA data transmission 5G NR UL MIMO data transmission DC_3A_n78A@23dBm 100 MHz, SCS 30 kHz DC_7A_n78A@23dBm 100 MHz, SCS 30 kHz DC_5A_n78A@23dBm 100 MHz, SCS 30 kHz n41 @ 23.6dBm 100 MHz, SCS 30 kHz n77 @ 23.8dBm 100 MHz, SCS 30 kHz n78 @ 23.8dBm 100 MHz, SCS 30 kHz Smart Module Series 900 950 600 372 365 378 mA mA mA mA mA mA NOTE The power consumption data above is for reference only, which may vary among different modules. For detailed information, contact Quectel Technical Support for the power consumption test report of the specific module. 6.4. Digital I/O Characteristic Table 58: 1.8 V I/O Requirements Parameter Description VIH VIL VOH VOL Min. 1.17

-0.3 Input high voltage Input low voltage Output high voltage 1.35 Output low voltage 0 Table 59: (U)SIM 1.8 V I/O Requirements Parameter Description USIM_VDD Power supply VIH Input high voltage Min. 1.65 1.16 Max. Unit 2.1 0.63 1.8 0.45 Max. 1.95 2.25 V V V V Unit V V SG560D_Series_Hardware_Design 121 / 134 Smart Module Series VIL VOH VOL Input low voltage

-0.3 Output high voltage 1.32 Output low voltage 0 0.39 1.95 0.4 V V V Table 60: (U)SIM 2.95 V I/O Requirements Parameter Description SD card pull-up power supply Input high voltage Input low voltage Min. 2.7 1.89

-0.3 Output high voltage 2.16 Output low voltage 0 USIM_VDD VIH VIL VOH VOL Table 61: SD card 1.8 V I/O Requirements Parameter Description SD_LDO6C Power supply Min. 1.65 VIH VIL VOH VOL Input high voltage 1.27 Input low voltage

-0.3 Output high voltage 1.4 Output low voltage

Table 62: SD card 2.95 V I/O Requirements Parameter Description SD_LDO6C Power supply Min. 2.72 VIH VIL Input high voltage 1.7 Input low voltage

-0.3 Max. Unit 3.05 3.35 0.61 3.05 0.4 Max. 1.9 2 0.58

0.45 Max. 3.54 3.84 0.89 V V V V V Unit V V V V V Unit V V V SG560D_Series_Hardware_Design 122 / 134 Smart Module Series VOH VOL Output high voltage 2.04 Output low voltage 0 3.54 0.44 V V 6.5. ESD Protection Static electricity occurs naturally and it may damage the module. Therefore, applying proper ESD countermeasures and handling methods is imperative. For example, wear anti-static gloves during the development, production, assembly and testing of the module; add ESD protection components to the ESD sensitive interfaces and points in the product design. Table 63: Electrostatics Discharge Characteristics (Temperature: 2530 C, Humidity: 40 5 % ) Tested Interfaces Contact Discharge Air Discharge Unit VBAT, GND TBD Antenna Interface TBD Other Interfaces TBD TBD TBD TBD kV kV kV 6.6. Operating and Storage Temperatures Table 64: Operating and Storage Temperatures Parameter Min. Typ. Max. Unit Operating Temperature Range 14 Storage Temperature Range

-35

-40

+25

+75

+90 C C 14 Within operating temperature range, the module is 3GPP compliant. SG560D_Series_Hardware_Design 123 / 134 Smart Module Series 7 Mechanical Information This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are 0.2 mm unless otherwise specified. 7.1. Mechanical Dimensions Pin 1 Figure 38: Module Top and Side Dimensions SG560D_Series_Hardware_Design 124 / 134 Smart Module Series Figure 39: Module Bottom Dimensions (Bottom View) NOTE The package warpage level of the module conforms to the JEITA ED-7306 standard. SG560D_Series_Hardware_Design 125 / 134 7.2. Recommended Footprint Smart Module Series Figure 40: Recommended Footprint NOTE Keep at least 3 mm between the module and other components on the motherboard to improve soldering quality and maintenance convenience. SG560D_Series_Hardware_Design 126 / 134 7.3. Top and Bottom Views Smart Module Series Figure 41: Top & Bottom Views of the Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. SG560D_Series_Hardware_Design 127 / 134 Smart Module Series 8 Storage, Manufacturing and Packaging 8.1. Storage Conditions The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: the temperature should be 23 5 C and the relative humidity should be 3560 %. 2. Shelf life (in a vacuum-sealed packaging): 12 months in Recommended Storage Condition. 3. Floor life: 168 hours 15 in a factory where the temperature is 23 5 C and relative humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g., a dry cabinet). 4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under the following circumstances:

The module is not stored in Recommended Storage Condition;

Violation of the third requirement mentioned above;

Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;

Before module repairing. 5. If needed, the pre-baking should follow the requirements below:

The module should be baked for 8 hours at 120 5 C;

The module must be soldered to PCB within 24 hours after the baking, otherwise it should be put in a dry environment such as in a dry cabinet. 15 This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to, or are not sure to conform to IPC/JEDEC J-STD-033. Do not unpack the modules in large quantities until they are ready for soldering. SG560D_Series_Hardware_Design 128 / 134 Smart Module Series NOTE 1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to the air is forbidden. 2. Take out the module from the package and put it on high-temperature-resistant fixtures before baking. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure. 3. Pay attention to ESD protection, such as wearing anti-static gloves, when touching the modules. 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. Apply proper force on the squeegee to produce a clean stencil surface on a single pass. To guarantee module soldering quality, the thickness of stencil for the module is recommended to be 0.150.18 mm. For more details, see document [3]. The recommended peak reflow temperature should be 235246 C, with 246 C as the absolute maximum reflow temperature. To avoid damage to the module caused by repeated heating, it is recommended that the module should be mounted only after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. Figure 42: Recommended Reflow Soldering Thermal Profile SG560D_Series_Hardware_Design 129 / 134 Temp. (C)Reflow ZoneSoak Zone246200217235CDBA150100 Ramp-to-soak slope:02 C/s Cool-down slope:-10 C/s Ramp-up slope:01 C/s Smart Module Series Table 65: Recommended Thermal Profile Parameters Factor Soak Zone Recommended Value Ramp-to-soak slope 02 C/s Soak time (between A and B: 150 C and 200 C) 70120 s Reflow Zone 217235 C ramp-up slope Reflow time (D: over 217C) Max temperature 235217 C cool-down slope Reflow Cycle Max reflow cycle NOTE 01 C/s 4065 s 235246 C

-10 C/s 1 1. The above profile parameter requirements are for the measured temperature of the solder joints. Both the hottest and coldest spots of solder joints on the PCB should meet the above requirements. 2. Due to the large-size form factor, to avoid excessive temperature change, which may cause excessive thermal deformation of the metal shielding frame and cover, it is recommended to reduce the ramp-up and cool-down slopes in the liquid phase of the solder paste. If possible, please choose a reflow oven with more than 10 temperature zones during production so that there are more temperature zones to set up to meet the optimal temperature curve. If a conformal coating is necessary for the module, do NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module. 3. 4. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the module. 5. Due to the complexity of the SMT process, please contact Quectel Technical Support in advance for any situation that you are not sure about, or any process (e.g. selective soldering, ultrasonic soldering) that is not mentioned in document [3]. SG560D_Series_Hardware_Design 130 / 134 Smart Module Series 8.3. Packaging Specification This chapter describes only the key parameters and process of packaging. All figures below are for reference only. The appearance and structure of the packaging materials are subject to the actual delivery. The module adopts injection tray packaging and details are as follow:

8.3.1. Injection Tray Dimension details are as follow:

Figure 43: Injection Tray Dimension Drawing SG560D_Series_Hardware_Design 131 / 134 8.3.2. Packaging Process Smart Module Series Each injection tray packs 8 modules. Stack 10 injection trays with modules together, and put 1 empty injection tray on the top. Packing 11 injection trays together. Place 1 humidity indicator card and 1 desiccant bag on the top of injection tray, then put 2 EPE on the top and bottom of injection tray. Put injection trays protected by EPE into the vacuum bag, vacuumize vacuum-packed the injection pizza box. 1 pizza box can pack 80 modules. it. Put into trays Put 2 packaged pizza boxes into 1 carton box and then seal it. 1 carton box can pack 160 modules. Figure 44: Packaging Process SG560D_Series_Hardware_Design 132 / 134 Smart Module Series 9 Appendix References Table 66: Related Documents Document Name

[1] Quectel_Smart_5G_EVB_User_Guide

[2] Quectel_RF_Layout_Application_Note

[3] Quectel_Module_Secondary_SMT_Application_Note Table 67: Terms and Abbreviations Abbreviation Description AMR BDS BLE bps BPSK BR CDMA CEP CPE CPU CS CSI Adaptive Multi-Rate BeiDou Navigation Satellite System Bluetooth Low Energy Bytes per second Binary Phase Shift Keying Basic Rate Code Division Multiple Access Circular Error Probable Customer-Premise Equipment Central Processing Unit Coding Scheme Camera Serial Interface SG560D_Series_Hardware_Design 133 / 134 Smart Module Series CTS DBS DCE DCS DMIC DRX DSI DTE EDR EFR EPE EGSM eSCO ESD ESR ETSI EVB Clear To Send Dual Band Simultaneous Data Communications Equipment Data Coding Scheme Digital Microphone Discontinuous Reception Display Serial Interface Data Terminal Equipment Enhanced Data Rate Enhanced Full Rate Expandable Polyethylene Enhanced GSM Extended Synchronous Connection Oriented Electrostatic Discharge Equivalent Series Resistance European Telecommunications Standards Institute Evaluation Board EVDO Evolution-Data Optimized FDD FHD FR Frequency Division Duplexing Full High Definition Full Rate Galileo Galileo Satellite Navigation System (EU) GLONASS Global Navigation Satellite System (Russia) GND GNSS Ground Global Navigation Satellite System SG560D_Series_Hardware_Design 134 / 134 Smart Module Series GPIO GPRS GPS GPU GSM HPUE HR General-Purpose Input/Output General Packet Radio Service Global Positioning System Graphics Processing Unit Global System for Mobile Communications High Power User Equipment Half Rate HSDPA High Speed Downlink Packet Access HTTP I2S IEEE IMT LCD LCM LDO LED LGA LTE MCS ME MIMO MLCC MO MT NFC Hypertext Transfer Protocol Inter-IC Sound Institute of Electrical and Electronics Engineers International Mobile Telecommunications Liquid Crystal Display Liquid Crystal Monitor Low-dropout Regulator Light Emitting Diode Land Grid Array Long Term Evolution Modulation and Coding Scheme Mobile Equipment Multi-Input Multi-Output / Multiple Input Multiple Output Multi-layer Ceramic Capacitor Mobile Origination Mobile Terminating Near Field Communication SG560D_Series_Hardware_Design 135 / 134 Smart Module Series NSA NTC OTA OTG PCB PDA PDU PF PMU PND POS PSK QAM QPSK QZSS RF RHCP RoHS RTC RTS SA SCO SCS SDIO SIM Non-Standalone Negative Temperature Coefficient Over-the-air programming On-The-Go Printed Circuit Board Personal Digital Assistant Protocol Data Unit Paging Frame Power Management Unit Portable Navigation Devices Point of Sale Phase Shift Keying Quadrature Amplitude Modulation Quadrature Phase Shift Keying Quasi-Zenith Satellite System Radio Frequency Right Hand Circular Polarization Restriction of Hazardous Substances Right Hand Circular Polarization Request To Send Standalone Synchronous Connection Oriented Sub-Carrier Space Secure Digital Input and Output Card Subscriber Identity Module SG560D_Series_Hardware_Design 136 / 134 Smart Module Series SMS SPI STA TDD Short Message Service Serial Peripheral Interface Station Time Division Duplexing TD-SCDMA Time Division-Synchronous Code Division Multiple Access TP TTFF TVS UART UFS UMTS USB Touch Panel Time to First Fix Transient Voltage Suppressor Universal Asynchronous Receiver/Transmitter Universal Flash Storage Universal Mobile Telecommunications System Universal Serial Bus

(U)SIM

(Universal) Subscriber Identity Module Vmax Vnom Vmin VIH VIL VOH VOL VSWR WCDMA WCN WLAN Maximum Voltage Value Nominal Voltage Minimum Voltage High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Voltage Standing Wave Ratio Wideband Code Division Multiple Access Wireless Communication Network Wireless Local Area Network SG560D_Series_Hardware_Design 137 / 134

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RF_734_02 04 April 16 Quectel Wireless Solutions Co., Ltd. Modular Approval Request FCC (KDB 996369 D01 & Part 15.212) FCC ID: XMR2023SG560DWF Items to be covered by Single modular transmitters. 1. The modular transmitter must have its own RF shielding. 2. The modular transmitter must have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with Part 15 requirements under conditions of excessive data rates or over-modulation. Answer from applicant Yes, please see exhibition external photos Yes, the modular has buffer modulation /data inputs 3. The modular transmitter must have its own power supply regulation. Yes, please see the SCH.pdf 4. The modular transmitter must comply with the antenna requirements of Section 15.203 and 15.204(b)(c). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). 5. The modular transmitter must be tested in a stand-alone configuration, i.e., the module must not be inside another device during testing. This is intended to demonstrate that the module is capable of complying with Part 15 emission limits regardless of the device into which it is eventually installed. 6. The modular transmitter must be equipped with either a permanently affixed label or must be capable of electronically displaying its FCC identification number in accordance with 15.212 (a)(1)(vi)(A) / (B). 7. The modular transmitter must comply with any specific rule or operating requirements applicable to the transmitter and the manufacturer must provide adequate instructions along with the module to explain any such requirements. A copy of these instructions must be included in the application for equipment authorization. For example, timing requirements that must be met before a transmitter is authorized for operation under Section 15.231. For instance, data transmission is prohibited, except for operation under Section 15.231(e), in which case there are separate field strength level and timing requirements. Compliance with these requirements must be assured. there are very strict operational and 8. The modular transmitter must comply with any applicable RF exposure requirements. For example, FCC Rules in Sections 1.1310, 2.1091, 2.1093, and specific Sections of Part 15, including 15.319(i), 15.407(f), 15.253(f) and 15.255(g), require that Unlicensed PCS, UNII and millimeter wave devices perform routine environmental evaluation for RF Exposure to demonstrate compliance. In addition, spread spectrum transmitters operating under Section 15.247 are required to address RF Exposure compliance. Modular transmitters approved under other Sections of Part 15, when necessary, may also need to address certain RF Exposure concerns, typically by providing specific installation and operating instructions for users, installers and other interested parties to ensure compliance. Yes, the requirements of antenna connector and spurious emission have been fulfilled. Please refer to the test report exhibition. Yes, please refer to the setup photo exhibition for the stand-alone configuration Yes, the module will be label with its own FCC ID, and the instruction on the labelling rule of the end product has been stated in the user manual of this module. Please refer to the label and user manual exhibition. Yes, the required FCC rule has been fulfilled and all the instruction for maintaining compliance have been clearly stated in the user manual. Yes, please refer exhibition RF exposure for the compliance of MPE RF exposure rule. Note: A limited modular approval (LMA) may be granted for single modular transmitters that comply partially with the requirements above. RF_734_02 04 April 16 Name and surname of applicant (or authorized representative):

Date:

City:

Name:

Email:

2023/05/26.. Shanghai .. Jean hu .. (2) jean.hu@quectel.com. Signature: