FCC ID: XMR2022SA800UWF Smart Module with WiFi and BT

SA800U-WF Hardware Design Smart Module Series Version: 1.0 Date: 2021-01-13 Status: Released www.quectel.com Smart Module Series SA800U-WF Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters:

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit:

http://www.quectel.com/support/sales.htm. For technical support, or to report documentation errors, please visit:

http://www.quectel.com/support/technical.htm Or email to support@quectel.com. General Notes Quectel offers the information as a service to its customers. The information provided is based upon customers requirements. Quectel makes every effort to ensure the quality of the information it makes available. Quectel does not make any warranty as to the information contained herein, and does not accept any liability for any injury, loss or damage of any kind incurred by use of or reliance upon the information. All information supplied herein is subject to change without prior notice. Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors, it is possible that these functions and features could contain errors, inaccuracies and omissions. Unless otherwise provided by valid agreement, Quectel makes no warranties of any kind, implied or express, with respect to the use of features and functions under development. To the maximum extent permitted by law, Quectel excludes all liability for any loss or damage suffered in connection with the use of the functions and features under development, regardless of whether such loss or damage may have been foreseeable. Duty of Confidentiality The Receiving Party shall keep confidential all documentation and information provided by Quectel, except when the specific permission has been granted by Quectel. The Receiving Party shall not access or use Quectels documentation and information for any purpose except as expressly provided herein. Furthermore, the Receiving Party shall not disclose any of the Quectel's documentation and information to any third party without the prior written consent by Quectel. For any noncompliance to the above requirements, unauthorized use, or other illegal or malicious use of the documentation and information, Quectel will reserve the right to take legal action. SA800U-WF_Hardware_Design 1 / 106 Smart Module Series SA800U-WF Hardware Design Copyright The information contained here is proprietary technical information of Quectel. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design. Copyright Quectel Wireless Solutions Co., Ltd. 2021. All rights reserved. SA800U-WF_Hardware_Design 2 / 106 Smart Module Series SA800U-WF Hardware Design Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be paid to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances in an aircraft is forbidden to prevent interference with communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft. Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions, such as when the mobile bill is unpaid or the (U)SIM card is invalid. When emergency help is needed in such conditions, use emergency call if the device supports it. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. In an emergency, the device with emergency call function cannot be used as the only contact method considering network connection cannot be guaranteed under all circumstances. The cellular terminal or mobile contains a transceiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV sets, radios, computers or other electric equipment. In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or metal powders. SA800U-WF_Hardware_Design 3 / 106 Smart Module Series SA800U-WF Hardware Design About the Document Revision History Version Date Author Description

2020-07-31 1.0 2021-01-13 Light WANG/

Finley ZHANG Light WANG/

Finley ZHANG Creation of the document First official release SA800U-WF_Hardware_Design 4 / 106 Smart Module Series SA800U-WF Hardware Design Contents Safety Information ....................................................................................................................................... 3 About the Document ................................................................................................................................... 4 Contents ....................................................................................................................................................... 5 Table Index ................................................................................................................................................... 7 Figure Index ................................................................................................................................................. 9 1 Introduction ........................................................................................................................................ 10 2 Product Concept ................................................................................................................................ 11 2.1. General Description .................................................................................................................. 11 2.2. Key Features ............................................................................................................................. 12 2.3. Functional Diagram ................................................................................................................... 14 2.4. Evaluation Board ....................................................................................................................... 15 3 Application Interfaces ....................................................................................................................... 16 3.1. General Description .................................................................................................................. 16 3.2. Pin Assignment ......................................................................................................................... 17 3.3. Pin Description .......................................................................................................................... 18 3.4. Power Supply ............................................................................................................................ 38 3.4.1. Power Supply Pins ......................................................................................................... 38 3.4.2. Decrease Voltage Drop .................................................................................................. 38 3.4.3. Reference Design for Power Supply .............................................................................. 39 3.5. Turn on and off Scenarios ......................................................................................................... 40 3.5.1. Turn on the Module Using PWRKEY ............................................................................. 40 3.5.2. Turn on the Module Automatically Using CBL_PWR_N ................................................ 42 3.5.3. Turn off/Restart the Module ........................................................................................... 43 3.6. VRTC Interface ......................................................................................................................... 44 3.7. Power Output ............................................................................................................................ 44 3.8. Battery Charging and Management .......................................................................................... 45 3.9. USB Interfaces .......................................................................................................................... 49 3.9.1. USB1 Interface ............................................................................................................... 49 3.9.1.1. USB Type-C Mode ............................................................................................... 49 3.9.1.2. DisplayPort Mode ................................................................................................. 51 3.9.2. USB2 Interface ............................................................................................................... 52 3.9.3. Design Principles ........................................................................................................... 53 3.10. UART Interface.......................................................................................................................... 55 3.11. PCIe Interfaces ......................................................................................................................... 56 3.12. SD Card Interface ..................................................................................................................... 58 3.13. GPIO Interfaces ........................................................................................................................ 60 3.14. I2C Interfaces ............................................................................................................................ 61 3.15. SPI Interfaces ............................................................................................................................ 62 3.16. ADC Interfaces .......................................................................................................................... 63 3.17. Vibrator Drive Interface ............................................................................................................. 63 SA800U-WF_Hardware_Design 5 / 106 Smart Module Series SA800U-WF Hardware Design 3.18. LCM Interfaces .......................................................................................................................... 64 3.19. Touch Panel Interface ............................................................................................................... 69 3.20. Camera Interfaces..................................................................................................................... 70 3.20.1. Design Considerations ................................................................................................... 75 3.20.2. Flashlight Interfaces ....................................................................................................... 79 3.21. Sensor Interfaces ...................................................................................................................... 80 3.22. Audio Interfaces ........................................................................................................................ 81 3.23. Emergency Download Interface ................................................................................................ 82 4 Wi-Fi and BT ....................................................................................................................................... 83 4.1. Wi-Fi Overview .......................................................................................................................... 83 4.1.1. Wi-Fi Performance ......................................................................................................... 84 4.2. BT Overview .............................................................................................................................. 86 4.2.1. BT Performance ............................................................................................................. 87 5 Antenna Connection .......................................................................................................................... 88 5.1. Antenna Connectors ................................................................................................................. 88 5.2. Antenna Installation .................................................................................................................. 89 5.2.1. Antenna Requirements .................................................................................................. 89 5.2.2. Recommended Mating Plug for Antenna Connection ................................................... 90 6 Reliability, Radio and Electrical Characteristics ............................................................................ 92 6.1. Absolute Maximum Ratings ...................................................................................................... 92 6.2. Power Supply Ratings ............................................................................................................... 92 6.3. Operating and Storage Temperatures ...................................................................................... 93 6.4. Current Consumption ................................................................................................................ 93 6.5. Electrostatic Discharge ............................................................................................................. 95 6.6. Thermal Dissipation .................................................................................................................. 95 7 Mechanical Dimensions .................................................................................................................... 97 7.1. Mechanical Dimensions of the Module ..................................................................................... 97 7.2. Recommended Footprint .......................................................................................................... 99 7.3. Top and Bottom View of the Module ....................................................................................... 100 8 Storage and Packaging ................................................................................................................... 101 8.1. Storage .................................................................................................................................... 101 8.2. Packaging ............................................................................................................................... 102 9 Appendix References ...................................................................................................................... 104 SA800U-WF_Hardware_Design 6 / 106 Smart Module Series SA800U-WF Hardware Design Table Index Table 1: SA800U-WF Frequency Bands .....................................................................................................11 Table 2: SA800U-WF Key Features ........................................................................................................... 12 Table 3: I/O Parameters Definition ............................................................................................................. 18 Table 4: Pin Description ............................................................................................................................. 18 Table 5: Power Description ........................................................................................................................ 45 Table 6: Pin Definition of Charging Interface ............................................................................................. 46 Table 7: Pin Definition of USB TYPE-C Interface ...................................................................................... 49 Table 8: Pin Definition of VCONN Circuit ................................................................................................... 50 Table 9: Pin Definition of USB Type-C/DisplayPort Mode ......................................................................... 51 Table 10: Pin Definition of USB2 ................................................................................................................ 52 Table 11: USB Trace Length Inside the Module ......................................................................................... 53 Table 12: Pin Definition of Debug UART Interface ..................................................................................... 55 Table 13: Pin Definition of PCIe Interfaces ................................................................................................ 56 Table 14: Pin Definition of SD Card Interface ............................................................................................ 58 Table 15: SD Card Signal Trace Length Inside the Module ....................................................................... 60 Table 16: Pin Definition of GPIO Interfaces ............................................................................................... 61 Table 17: Pin Definition of I2C Interfaces ................................................................................................... 61 Table 18: Pin Definition of SPI Interfaces .................................................................................................. 62 Table 19: Pin Definition of ADC Interfaces ................................................................................................. 63 Table 20: Pin Definition of Vibrator Drive Interface .................................................................................... 64 Table 21: Pin Definition of LCM Interfaces ................................................................................................. 65 Table 22: Pin Definition of Touch Panel Interface ...................................................................................... 69 Table 23: Pin Definition of Camera Interfaces ........................................................................................... 70 Table 24: CSI Data Rate and PCB Maximum Trace Length (D-PHY) ....................................................... 75 Table 25: DSI Data Rate and PCB Maximum Trace Length (D-PHY) ....................................................... 76 Table 26: MIPI Trace Length Inside the Module ........................................................................................ 76 Table 27: Pin Definition of Flashlight Interfaces ......................................................................................... 79 Table 28: Pin Definition of Sensor Interfaces ............................................................................................. 80 Table 29: Pin Definition of Audio Interfaces ............................................................................................... 81 Table 30: Wi-Fi Transmitting Performance ................................................................................................. 84 Table 31: Wi-Fi Receiving Performance ..................................................................................................... 85 Table 32: BT Data Rate and Versions ........................................................................................................ 86 Table 33: BT Transmitting and Receiving Performance............................................................................. 87 Table 34: Definition of Antenna Connectors ............................................................................................... 88 Table 35: Operating Frequency .................................................................................................................. 89 Table 36: Antenna Requirements ............................................................................................................... 89 Table 37: Absolute Maximum Ratings ........................................................................................................ 92 Table 38: SA800U-WF Power Supply Ratings ........................................................................................... 92 Table 39: Operating and Storage Temperatures ........................................................................................ 93 Table 40: SA800U-WF Current Consumption (2 2 MIMO) ..................................................................... 93 Table 41: ESD Characteristics (Temperature: 25 C, Humidity: 45 %) ...................................................... 95 SA800U-WF_Hardware_Design 7 / 106 Smart Module Series SA800U-WF Hardware Design Table 42: Tray Package ............................................................................................................................ 103 Table 43: Related Documents .................................................................................................................. 104 Table 44: Terms and Abbreviations .......................................................................................................... 104 SA800U-WF_Hardware_Design 8 / 106 Smart Module Series SA800U-WF Hardware Design Figure Index Figure 1: Functional Diagram ..................................................................................................................... 15 Figure 2: Pin Assignment (Top View) ......................................................................................................... 17 Figure 3: Voltage Drop Sample .................................................................................................................. 38 Figure 4: Star Structure of Power Supply .................................................................................................. 39 Figure 5: Reference Circuit of Power Supply ............................................................................................. 40 Figure 6: Turn on the Module Using Driving Circuit ................................................................................... 41 Figure 7: Turn on the Module Using Keystroke ......................................................................................... 41 Figure 8: Timing of Turning on the Module ................................................................................................ 42 Figure 9: Turn on the Module Using CBL_PWR_N ................................................................................... 43 Figure 10: Timing of Restarting the Module ............................................................................................... 44 Figure 11: RTC Powered by Coin Cell ....................................................................................................... 44 Figure 12: Reference Design for Battery Charging Circuit ........................................................................ 48 Figure 13: USB Type-C Interface Reference Design ................................................................................. 50 Figure 14: VCONN Reference Design ....................................................................................................... 51 Figure 15: DisplayPort Reference Design ................................................................................................. 52 Figure 16: USB Type-A Interface Reference Design (USB2 for Host Mode) ............................................ 53 Figure 17: Reference Circuit with Level Translator Chip ........................................................................... 55 Figure 18: RS-232 Level Match Circuit ...................................................................................................... 56 Figure 19: PCIe Interfaces Reference Circuit ............................................................................................ 58 Figure 20: Reference Circuit for SD Card Interface ................................................................................... 59 Figure 21: Reference Circuit for Vibrator Connection ................................................................................ 64 Figure 22: Reference Circuit Design for LCM0 Interface ........................................................................... 67 Figure 23: Reference Circuit Design for LCM1 Interface ........................................................................... 68 Figure 24: Reference Design of LCM1 External Backlight Driving Circuit ................................................ 69 Figure 25: Reference Circuit Design for Touch Panel Interface ................................................................ 70 Figure 26: Reference Circuit Design for CSI0 ........................................................................................... 73 Figure 27: Reference Circuit Design for Power of CSI0 ............................................................................ 74 Figure 28: Reference Circuit Design for Flashlight Interfaces ................................................................... 79 Figure 29: Reference Circuit Design for Emergency Download Interface ................................................. 82 Figure 30: Antenna Connectors ................................................................................................................. 88 Figure 31: Dimensions of the ECT 818000500 Connector (Unit: mm) ...................................................... 90 Figure 32: Mechanicals of the Mating Plug (Unit: mm) .............................................................................. 91 Figure 33: Thermal Dissipation .................................................................................................................. 96 Figure 34: Module Top and Side Dimensions ............................................................................................ 97 Figure 35: Module Bottom Dimensions (Bottom View) .............................................................................. 98 Figure 36: Recommended Footprint (Top View) ........................................................................................ 99 Figure 37: Top View of SA800U-WF Module ........................................................................................... 100 Figure 38: Bottom View of SA800U-WF Module ..................................................................................... 100 Figure 39: Tray Dimensions ..................................................................................................................... 102 Figure 40: Package Details ...................................................................................................................... 103 SA800U-WF_Hardware_Design 9 / 106 Smart Module Series SA800U-WF Hardware Design 1 Introduction This document defines the SA800U-WF module and describes its air interfaces and hardware interfaces. This document helps you quickly understand module interface specifications, electrical and mechanical details as well as other related information of the module. Associated with application notes and user guides, you can use the module to design and set up applications easily. SA800U-WF_Hardware_Design 10 / 106 Smart Module Series SA800U-WF Hardware Design 2 Product Concept 2.1. General Description SA800U-WF is a smart module based on Qualcomm platform and Android operating system, which provides industrial grade performance. Its general features are listed below:

Support short-range wireless communication via Wi-Fi 802.11a/b/g/n/ac and BT 5.0 Support multiple audio and video codecs Built-in high performance AdrenoTM 630 graphics processing unit Dedicated low-power Snapdragon sensor core DSP to support always-on use cases Provide multiple audio and video input/output interfaces as well as abundant GPIO interfaces The following table shows the supported frequency bands of the module. Table 1: SA800U-WF Frequency Bands Type 802.11a/b/g/n/ac BT 5.0 FM*

Frequency Bands 24022482 MHz 51805825 MHz 24022480 MHz 76108 MHz SA800U-WF is a 396-pin module, which supports B2B connection. With a compact profile of 60.0 mm 37.0 mm 6.55 mm, the module can meet almost all requirements for M2M applications such as smart meeting, smart home, security, routers, AR glasses, mobile computing devices, PDA phone, tablet PC, etc. NOTE

* means under development. SA800U-WF_Hardware_Design 11 / 106 Smart Module Series SA800U-WF Hardware Design 2.2. Key Features The following table describes the detailed features of the module. Table 2: SA800U-WF Key Features Features Details Applications Processor 64-bit Kryo 385 applications processor Quad high-performance Kyro cores at 2.649 GHz with 256 KB L2 cache per core Quad low-power Kyro cores at 1.766 GHz with 128 KB L2 cache per core GPU AdrenoTM 630 graphics processing unit 4K @ 60 fps or 2 2K @ 90 fps Memory 64 GB UFS + 4 GB LPDDR4X (default) 256 GB UFS + 8 GB LPDDR4X (optional) Operating System Android 9.0/10.0 Power Supply WLAN Features VBAT Supply Voltage: 3.554.4 V Typ. 3.8 V 2.4/5 GHz, 802.11a/b/g/n/ac Support 2 2 MIMO, maximally up to 866 Mbps Support AP and STA modes Bluetooth Features BT 2.1+EDR/3.0/4.1 LE/4.2 BLE/BT 5.0 Support two groups of 4-lane MIPI DSI Support dual LCDs Support 2560 1600 @ 60 fps VESA DSC 1.1 primary display with 4 lanes LCM Interfaces Support 4K @ 60 fps over DisplayPort Provide one high voltage output for powering strings of WLEDs and 29.6 V OVP Provide four drivers for sinking the current from WLED strings, and each sink current can reach up to 30 mA Support three groups of 4-lane MIPI CSI and one 2-lane MIPI CSI 1), up Camera Interfaces to 2.5 Gbps/lane, Support 4 cameras (4-lane + 4-lane + 4-lane + 2-lane) Up to 32 MP with dual ISP Video Codec Video encoding and decoding up to 4K @ 60 fps Audio Codec QCELP, EVS, EVRC, EVRC-B, EVRC-WB, G.7Gen, G.729 A/AB SA800U-WF_Hardware_Design 12 / 106 Smart Module Series SA800U-WF Hardware Design USB Interfaces PCIe Interfaces 2 USB interfaces which comply with both USB 3.1 and USB 2.0 specifications Support up to 5 Gbps on USB 3.1 and 480 Mbps on USB 2.0 USB1 supports USB OTG and DisplayPort, and can be used for AT command communication, data transmission, software debugging and firmware upgrade USB2 only supports USB host mode 2 PCIe Interfaces:

PCIe0 is a Gen 2 1-lane interface PCIe1 is a Gen 3 1-lane interface UART Interface One 2-wire debug UART interface used for debugging by default Vibrator Drive Interface Drive ERM/LRA vibrator SDIO Interfaces 2 SDIO interfaces:

The SDIO function of SDC4 is not supported by default As the SD card interface, SDC2 complies with SD 3.0 specifications I2C Interfaces 6 I2C interfaces, used for peripherals such as TP, camera, sensor, etc. I2S Interfaces 3 I2S interfaces Flashlight Interfaces 3 high-current flash LED drivers, which supports both flash and torch modes Up to 1.5 A for FLASH_LED1/FLASH_LED2 in flash mode Up to 0.75 A for FLASH_LED3 in flash mode ADC Interfaces 2 general-purpose ADC interfaces SPI Interfaces 3 SPI interfaces, only support master mode Charging Interface Used for battery voltage detection, fuel gauge, battery temperature detection Real Time Clock Supported Antenna Connection 4 antenna connectors: Wi-Fi/BT, Wi-Fi MIMO, BT*, FM*

Physical Characteristics Size: (60.0 0.15) mm (37.0 0.15) mm (6.55 0.2) mm Package: B2B Weight: approx. 15 g Temperature Range Operating temperature range: -35 C to +75 C 2) Storage temperature range: -40 C to +90 C Firmware Upgrade Over USB interface or OTA RoHS All hardware components are fully compliant with EU RoHS directive SA800U-WF_Hardware_Design 13 / 106 Smart Module Series SA800U-WF Hardware Design NOTES 1. 2. 3. 1) The 2-lane MIPI CSI can only get data of RAW format. It can be used for ToF/3D camera modules but cannot be used for display. 2) Within the operating temperature range, the module is IEEE compliant.

* means under development. 2.3. Functional Diagram The following figure shows a block diagram of SA800U-WF and illustrates the major functional parts. Power management Baseband LPDDR4X + UFS flash Peripheral interfaces

-- USB interfaces

-- PCIe interfaces

-- UART interface

-- I2C interfaces

-- SPI interfaces

-- SD card interface

-- GPIO interfaces

-- SLIMbus interface

-- I2S interfaces

-- ADC interfaces

-- Vibrator drive interface

-- LCM (MIPI) interfaces

-- TP (touch panel) interface

-- Camera (MIPI) interfaces

-- Flashlight interfaces

-- Sensor interfaces

-- Emergency download interface SA800U-WF_Hardware_Design 14 / 106 Smart Module Series SA800U-WF Hardware Design Figure 1: Functional Diagram 2.4. Evaluation Board To help you develop applications with SA800U-WF conveniently, Quectel supplies the evaluation board, USB to RS-232 converter cable, USB Type-C data cable, power adapter, earphone, antenna and other peripherals to control or test the module. For more details, see document [1]. SA800U-WF_Hardware_Design 15 / 106 BasebandWCNLPDDR4XUFSUSB_VBUS3Flash LEDsWLEDMotorChargeOTG Wi-Fi/BT ANTGPIOsI2CsUART2USB3.14CAMTP2LCMSPIs2ADCLPGFlashHapticsRFCLKBBCLKMEMMultimediaConnectivityWireless InterfaceProcessorsPowerSignalPowerFunctionRFFE 0XOPMUHK ADC VRTCVBAT2PWMPWRKEYPMISD_LDO13AVREG_S4A_1V8SD_LDO21ALVS1A_1V8LVS2A_1V8LDO19A_3V0LDO24A_3V075LDO14A_1V88LDO28A_3V0Audio38.4MFM ANTRGBRGBWLEDBatteryDisplay BiasVDISPXO38.4M2PCIe2SDIORFFE 1Wi-Fi MIMO ANTBT ANTPDET_IN CH0PDET_IN CH12.4G_TRX2.4G_TRX5G_TX5G_TX5G_RX5G_RXVREG_BOBLDO12A_1V8 Smart Module Series SA800U-WF Hardware Design 3 Application Interfaces 3.1. General Description SA800U-WF is equipped with 396 pins that can be embedded into cellular application platform. The following chapters provide the detailed description of interfaces listed below. Power supply VRTC interface Charging interface USB interfaces UART interface PCIe interfaces SD card interface GPIO interfaces I2C interfaces SPI interfaces ADC interfaces Vibrator drive interface LCM interfaces TP interface Camera interfaces Flashlight interfaces Sensor interfaces Audio interfaces Emergency download interface SA800U-WF_Hardware_Design 16 / 106 Smart Module Series SA800U-WF Hardware Design 3.2. Pin Assignment The following figure shows the pin assignment of SA800U-WF module. Figure 2: Pin Assignment (Top View) SA800U-WF_Hardware_Design 17 / 106 J1-2J1-4J1-10J1-6J1-8J1-14J1-18J1-12J1-16J1-20J1-26J1-22J1-24J1-28J1-34J1-30J1-32J1-36J1-42J1-38J1-40J1-44J1-50J1-46J1-48J1-52J1-58J1-54J1-56J1-60J1-66J1-62J1-64J1-68J1-74J1-70J1-72J1-76J1-82J1-78J1-80J1-84J1-86J1-95J1-97J1-57J1-99J1-101J1-61J1-65J1-59J1-63J1-67J1-73J1-69J1-71J1-75J1-35J1-77J1-33J1-37J1-43J1-39J1-41J1-45J1-51J1-47J1-49J1-17J1-23J1-19J1-21J1-25J1-31J1-27J1-29J1-55J1-7J1-53J1-15J1-9J1-5J1-11J1-13J1-3J1-1J1-88J1-90J1-96J1-92J1-94J1-100J1-104J1-98J1-102J1-106J1-112J1-108J1-110J1-114J1-120J1-116J1-118J1-122J1-128J1-124J1-126J1-130J1-136J1-132J1-134J1-138J1-144J1-140J1-142J1-146J1-152J1-148J1-150J1-154J1-160J1-156J1-158J1-162J1-168J1-164J1-166J1-93J1-91J1-85J1-89J1-87J1-81J1-103J1-83J1-79J1-117J1-123J1-119J1-121J1-125J1-131J1-127J1-129J1-133J1-105J1-109J1-107J1-151J1-145J1-149J1-147J1-143J1-137J1-141J1-139J1-135J1-115J1-111J1-113J1-153J1-159J1-155J1-157J1-161J1-167J1-163J1-165PCIeGNDPOWERCameraOtherSDIOUFSSPIJ2-2J2-4J2-10J2-6J2-8J2-14J2-18J2-12J2-16J2-20J2-26J2-22J2-24J2-28J2-34J2-30J2-32J2-36J2-42J2-38J2-40J2-44J2-50J2-46J2-48J2-52J2-58J2-54J2-56J2-60J2-66J2-62J2-64J2-68J2-74J2-70J2-72J2-76J2-82J2-78J2-80J2-84J2-86J2-95J2-97J2-57J2-99J2-101J2-61J2-65J2-59J2-63J2-67J2-73J2-69J2-71J2-75J2-35J2-77J2-33J2-37J2-43J2-39J2-41J2-45J2-51J2-47J2-49J2-17J2-23J2-19J2-21J2-25J2-31J2-27J2-29J2-55J2-7J2-53J2-15J2-9J2-5J2-11J2-13J2-3J2-1J2-88J2-90J2-96J2-92J2-94J2-100J2-104J2-98J2-102J2-106J2-112J2-108J2-110J2-114J2-120J2-116J2-118J2-122J2-128J2-124J2-126J2-130J2-136J2-132J2-134J2-138J2-144J2-140J2-142J2-146J2-152J2-148J2-150J2-154J2-160J2-156J2-158J2-162J2-168J2-164J2-166J2-93J2-91J2-85J2-89J2-87J2-81J2-103J2-83J2-79J2-117J2-123J2-119J2-121J2-125J2-131J2-127J2-129J2-133J2-105J2-109J2-107J2-151J2-145J2-149J2-147J2-143J2-137J2-141J2-139J2-135J2-115J2-111J2-113J2-153J2-159J2-155J2-157J2-161J2-167J2-163J2-165GPIOLCMTPUSBAUDIOKeypadChargingUARTIICJ1J2TOP ViewTOP ViewJ4-30J4-29J4-28J4-8J4-9J4-10J4-11J4-27J4-26J4-23J4-25J4-24J4-21J4-19J4-22J4-20J4-18J4-17J4-16J4-7J4-6J4-3J4-5J4-4J4-1J4-12J4-2J4-13J4-15J4-14J3-15J3-14J3-13J3-23J3-24J3-25J3-26J3-12J3-11J3-8J3-10J3-9J3-6J3-4J3-7J3-5J3-3J3-2J3-1J3-22J3-21J3-18J3-20J3-19J3-16J3-27J3-17J3-28J3-30J3-29J3J4TOP ViewTOP View Smart Module Series SA800U-WF Hardware Design 3.3. Pin Description Table 3: I/O Parameters Definition Description Analog Input Analog Output Analog Input/Output Digital Input Digital Output Digital Input/Output Open Drain Power Input Power Output Type AI AO AIO DI DO DIO OD PI PO The following tables show the SA800U-WFs pin definitions and electrical characteristics. Table 4: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment J1-159, J1-160, J1-161, J1-162, J1-163, J1-164, J1-165, J1-166, J1-167, J1-168 J2-140, J2-142 VBAT VREG_BOB PI/

PO Power supply for the module Vmax = 4.4 V Vmin = 3.55 V Vnom = 3.8 V Must be provided with sufficient current of up to 3 A. It is suggested to use a TVS to increase voltage surge withstand capability. PO BOB output Vnom = 3.7 V IOmax = 2000 mA Power supply for external LDOs. SA800U-WF_Hardware_Design 18 / 106 Smart Module Series SA800U-WF Hardware Design VREG_S4A_1V8 J2-124, J2-126, J2-128 PO 1.8 V output Vnom = 1.8 V IOmax = 2000 mA LVS1A_1V8 J1-149 PO 1.8 V output Vnom = 1.8 V IOmax = 300 mA LVS2A_1V8 J2-148 PO 1.8 V output Vnom = 1.8 V IOmax = 100 mA LDO12A_1V8 J3-12 PO 1.8 V output Vnom = 1.8 V IOmax = 300 mA LDO14A_1V88 J4-9 PO 1.8 V output Vnom = 1.8 V IOmax = 50 mA LDO19A_3V0 J2-150 PO 3.0 V output Vnom = 3.0 V IOmax = 600 mA Power supply for external GPIOs pull-up circuit and level shift circuit. Power supply for IOVDD of cameras. Add a 1.04.7 F bypass capacitor if used. If unused, keep this pin open. Power supply for IOVDD or VDD of sensors. Add a 1.02.2 F bypass capacitor if used. If unused, keep this pin open. Connect this pin to SHDN of SMB1355 parallel charger to make the charger enter low power mode. If SMB1355 is unused, keep this pin open. Power supply for IOVDD of TP and LCDs. Add a 1.04.7 F bypass capacitor if used. If unused, keep this pin open. Power supply for sensors Add a 1.02.2 F bypass capacitor if used. If unused, keep this pin open. SA800U-WF_Hardware_Design 19 / 106 Smart Module Series SA800U-WF Hardware Design LDO24A_3V075 J4-8 PO 3.075 V output Vnom = 3.075 V IOmax = 150 mA LDO28A_3V0 J4-10 PO 3.0 V output Vnom = 3.0 V IOmax = 150 mA Power supply for DPs pull-up circuits. Add a 1.04.7 F bypass capacitor if used. If unused, keep this pin open. Power supply for VDD of TP. Add a 1.04.7 F bypass capacitor if used. If unused, keep this pin open. J1-2, J1-7, J1-8, J1-13, J1-14, J1-19, J1-20, J1-25, J1-26, J1-31, J1-32, J1-37, J1-38, J1-41, J1-44, J1-50, J1-56, J1-59, J1-62, J1-65, J1-68, J1-71, J1-74, J1-77, J1-80, J1-83, J1-89, J1-93, J1-94, J1-97, J1-101, J1-105, J1-113, J1-119, J1-125, J1-131, J1-156, J1-157, J1-158, J2-11, J2-12, J2-17, J2-18, J2-23, J2-24, J2-29, J2-30, J2-35, J2-36, J2-41, J2-42, J2-45, J2-53, J2-98, J2-103, J2-104, J2-109, J2-110, J2-115, J2-116, J2-121, J2-122, J2-127, J2-155, J2-158, J2-161, J2-167, J3-1, J3-8, J3-13, J3-21, J3-28, J4-7, J4-12, J4-19, J4-22, J4-25, J4-28 GND USB Interface Pin Name Pin No. I/O Description DC Characteristics Comment USB_VBUS J2-160, J2-162, J2-164, J2-166, J2-168, J4-13, J4-14, J4-15, J4-16, J4-17, J4-18 PI/

PO Charging power input. Power output for OTG device. USB/adaptor insertion detect. Vmax = 14 V Vmin = 4.0 V Vnom = 5.0 V USB1_DM J2-117 AIO USB1_DP J2-119 AIO USB1 2.0 differential data

(-) USB1 2.0 differential data

(+) 90 differential impedance. USB 2.0 standard compliant. SA800U-WF_Hardware_Design 20 / 106 Smart Module Series SA800U-WF Hardware Design USB1_SS1_TX_M J2-123 AO USB1_SS1_TX_P J2-125 AO USB1_SS1_RX_M J2-118 AI USB1_SS1_RX_P J2-120 AI USB1_SS2_TX_M J2-111 AO USB1_SS2_TX_P J2-113 AO USB1_SS2_RX_M J2-114 AI USB1_SS2_RX_P J2-112 AI USB_CC1 J2-141 AI USB_CC2 J2-139 AI USB1 3.1 channel 1 super-speed transmit (-) USB1 3.1 channel 1 super-speed transmit (+) USB1 3.1 channel 1 super-speed receive (-) USB1 3.1 channel 1 super-speed receive (+) USB1 3.1 channel 2 super-speed transmit (-) USB1 3.1 channel 2 super-speed transmit (+) USB1 3.1 channel 2 super-speed receive (-) USB1 3.1 channel 2 super-speed receive (+) USB Type-C configuration channel 1 USB Type-C configuration channel 2 90 differential impedance. USB 3.1 standard compliant. USB2_DP J2-105 AIO USB2 2.0 differential data

(+) 90 differential impedance. USB 2.0 standard SA800U-WF_Hardware_Design 21 / 106 Smart Module Series SA800U-WF Hardware Design USB2_DM J2-107 AIO USB2_SS_TX_M J2-108 AO USB2_SS_TX_P J2-106 AO USB2_SS_RX_M J2-100 AI USB2_SS_RX_P J2-102 AI PCIe Interfaces USB2 2.0 differential data

(-) USB2 3.1 channel 1 super-speed transmit (-) USB2 3.1 channel 1 super-speed transmit (+) USB2 3.1 channel 1 super-speed receive (-) USB2 3.1 channel 1 super-speed receive (+) compliant. Only support host mode. 90 differential impedance. USB 3.1 standard compliant. Only support host mode. Pin Name Pin No. I/O Description DC Characteristics Comment PCIE0_RST_N J1-1 DO PCIe0 reset VOLmax = 0.45 V VOHmin = 1.35 V PCIE0_WAKE_N J1-3 PCIE0_CLKREQ_N J1-5 DI DI PCIe0 wake up host VILmax = 0.63 V VIHmin = 1.17 V PCIe0 clock request VILmax = 0.63 V VIHmin = 1.17 V PCIE0_REFCLK_P J1-15 AO PCIE0_REFCLK_M J1-17 AO PCIE0_TX_P J1-11 AO PCIE0_TX_M J1-9 AO PCIE0_RX_P J1-21 AI PCIe0 reference clock (+) PCIe0 reference clock (-) PCIe0 transmit

(+) PCIe0 transmit

(-) PCIe0 receive

(+) PCIE0_RX_M J1-23 AI PCIe0 receive (-) PCIE1_RST_N J1-107 DO PCIe1 reset VOLmax = 0.45 V VOHmin = 1.35 V Control the characteristic impedance as 85 . SA800U-WF_Hardware_Design 22 / 106 Smart Module Series SA800U-WF Hardware Design PCIE1_WAKE_N J1-111 DI PCIE1_CLKREQ_N J1-109 DI PCIe1 wake up host VILmax = 0.63 V VIHmin = 1.17 V PCIe1 clock request VILmax = 0.63 V VIHmin = 1.17 V PCIE1_REFCLK_P J1-121 AO PCIE1_REFCLK_M J1-123 AO PCIE1_TX_P J1-129 AO PCIE1_TX_M J1-127 AO PCIE1_RX_P J1-115 AI PCIe1 reference clock (+) PCIe1 reference clock (-) PCIe1 transmit

(+) PCIe1 transmit

(-) PCIe1 receive

(+) PCIE1_RX_M J1-117 AI PCIe1 receive (-) SDIO Interface Control the characteristic impedance as 85 . Pin Name Pin No. I/O Description DC Characteristics Comment SDC4_CLK J1-86 DO SDIO clock SDC4_CMD J1-92 DO SDIO command SDC4_DATA0 J1-82 DIO SDIO data bit 0 SDC4_DATA1 J1-84 DIO SDIO data bit 1 SDC4_DATA2 J1-88 DIO SDIO data bit 2 SDC4_DATA3 J1-90 DIO SDIO data bit 3 VOLmax = 0.45 V VOHmin = 1.35 V VOLmax = 0.45 V VOHmin = 1.35 V VILmax = 0.63 V VIHmin = 1.17 V VOLmax = 0.45 V VOHmin = 1.35 V SD Card Interface SDIO function is not supported by default. Can be multiplexed into GPIOs. Pin Name Pin No. I/O Description DC Characteristics Comment SD_CLK J1-45 DO SD card clock SD_CMD J1-47 DO SD card command 1.8 V SD card:

VOLmax = 0.45 V VOHmin = 1.4 V 2.95 V SD card:

VOLmax = 0.36 V VOHmin = 2.22 V Control characteristic impedance as 45 . SD_DATA0 J1-51 DIO SDIO data bit 0 1.8 V SD card:

SA800U-WF_Hardware_Design 23 / 106 Smart Module Series SA800U-WF Hardware Design SD_DATA1 J1-53 DIO SDIO data bit 1 SD_DATA2 J1-57 DIO SDIO data bit 2 SD_DATA3 J1-55 DIO SDIO data bit 3 VILmax = 0.58 V VIHmin = 1.27 V VOLmax = 0.45 V VOHmin = 1.4 V 2.95 V SD card:

VILmax = 0.73 V VIHmin = 1.85 V VOLmax = 0.36 V VOHmin = 2.22 V SD_DET J1-49 DI SD card hot-plug detect VILmax = 0.63 V VIHmin = 1.17 V Active low. SD_LDO21A J1-151, J1-153, J1-155 PO SD card power supply Vnom = 2.95 V IOmax = 800 mA SD_LDO13A J4-11 PO TP (Touch Panel) Interface 1.8/2.95 V output power for SD card pull-up circuits Vnom = 1.8/2.95 V IOmax = 50 mA Pin Name Pin No. I/O Description DC Characteristics Comment TP_INT J2-48 DI TP interrupt TP_RST J2-50 DO TP reset TP_I2C_SCL J2-44 OD TP I2C clock TP_I2C_SDA J2-46 OD TP I2C data LCM Interfaces VILmax = 0.63 V VIHmin = 1.17 V VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. Pin Name Pin No. I/O Description DC Characteristics Comment LCD_BL_A J4-4 PO LCD_BL_K1 J4-3 AI LCD_BL_K2 J4-2 AI LCD_BL_K3 J4-27 AI LCD_BL_K4 J4-26 AI Power output for LCD backlight Current sink 1 for LCD backlight Current sink 2 for LCD backlight Current sink 3 for LCD backlight Current sink 4 for LCD backlight SA800U-WF_Hardware_Design 24 / 106 Smart Module Series SA800U-WF Hardware Design VDISP_P J4-29 PO VDISP_M J4-30 PO Display bias output (+) Display bias output (-) LCD_RST J2-62 DO LCD reset VOLmax = 0.45 V VOHmin = 1.35 V LCD_TE J2-60 DI LCD tearing effect VILmax = 0.63 V VIHmin = 1.17 V Active low. 1.8 V power domain. 1.8 V power domain. DSI0_CLK_N J2-26 AO DSI0_CLK_P J2-28 AO DSI0_LN0_N J2-38 AO DSI0_LN0_P J2-40 AO DSI0_LN1_N J2-32 AO DSI0_LN1_P J2-34 AO DSI0_LN2_N J2-20 AO DSI0_LN2_P J2-22 AO DSI0_LN3_N J2-14 AO DSI0_LN3_P J2-16 AO DSI1_CLK_N J2-21 AO DSI1_CLK_P J2-19 AO DSI1_LN0_N J2-13 AO DSI1_LN0_P J2-15 AO DSI1_LN1_N J2-37 AO DSI1_LN1_P J2-39 AO LCD0 MIPI clock

(-) LCD0 MIPI clock

(+) LCD0 MIPI lane 0 data (-) LCD0 MIPI lane 0 data (+) LCD0 MIPI lane 1 data (-) LCD0 MIPI lane 1 data (+) LCD0 MIPI lane 2 data (-) LCD0 MIPI lane 2 data (+) LCD0 MIPI lane 3 data (-) LCD0 MIPI lane 3 data (+) LCD1 MIPI clock

(-) LCD1 MIPI clock

(+) LCD1 MIPI lane 0 data (-) LCD1 MIPI lane 0 data (+) LCD1 MIPI lane 1 data (-) LCD1 MIPI lane 1 data (+) 100 differential impedance. SA800U-WF_Hardware_Design 25 / 106 Smart Module Series SA800U-WF Hardware Design DSI1_LN2_N J2-27 AO DSI1_LN2_P J2-25 AO DSI1_LN3_N J2-31 AO DSI1_LN3_P J2-33 AO Camera Interfaces LCD1 MIPI lane 2 data (-) LCD1 MIPI lane 2 data (+) LCD1 MIPI lane 3 data (-) LCD1 MIPI lane 3 data (+) Pin Name Pin No. I/O Description DC Characteristics Comment CSI0_CLK_N J1-30 AI CSI0_CLK_P J1-28 AI CSI0_LN0_N J1-22 AI CSI0_LN0_P J1-24 AI CSI0_LN1_N J1-16 AI CSI0_LN1_P J1-18 AI CSI0_LN2_N J1-10 AI CSI0_LN2_P J1-12 AI CSI0_LN3_N J1-6 AI CSI0_LN3_P J1-4 AI CSI1_CLK_N J1-58 AI CSI1_CLK_P J1-60 AI CSI1_LN0_N J1-52 AI CSI1_LN0_P J1-54 AI CSI1_LN1_N J1-46 AI MIPI clock of camera 0 (-) MIPI clock of camera 0 (+) MIPI lane 0 data of camera 0 (-) MIPI lane 0 data of camera 0 (+) MIPI lane 1 data of camera 0 (-) MIPI lane 1 data of camera 0 (+) MIPI lane 2 data of camera 0 (-) MIPI lane 2 data of camera 0 (+) MIPI lane 3 data of camera 0 (-) MIPI lane 3 data of camera 0 (+) MIPI clock of camera 1 (-) MIPI clock of camera 1 (+) MIPI lane 0 data of camera 1 (-) MIPI lane 0 data of camera 1 (+) MIPI lane 1 data of camera 1 (-) 100 differential impedance. SA800U-WF_Hardware_Design 26 / 106 Smart Module Series SA800U-WF Hardware Design CSI1_LN1_P J1-48 AI CSI1_LN2_N J1-42 AI CSI1_LN2_P J1-40 AI CSI1_LN3_N J1-34 AI CSI1_LN3_P J1-36 AI CSI2_CLK_N J1-63 AI CSI2_CLK_P J1-61 AI CSI2_LN0_N J1-67 AI CSI2_LN0_P J1-69 AI CSI2_LN1_N J1-66 AI CSI2_LN1_P J1-64 AI CSI2_LN2_N J1-72 AI CSI2_LN2_P J1-70 AI CSI2_LN3_N J1-78 AI CSI2_LN3_P J1-76 AI CSI3_CLK_N J1-85 AI CSI3_CLK_P J1-87 AI CSI3_LN0_N J1-81 AI CSI3_LN0_P J1-79 AI CSI3_LN1_N J1-73 AI CSI3_LN1_P J1-75 AI MIPI lane 1 data of camera 1 (+) MIPI lane 2 data of camera 1 (-) MIPI lane 2 data of camera 1 (+) MIPI lane 3 data of camera 1 (-) MIPI lane 3 data of camera 1 (+) MIPI clock of camera 2 (-) MIPI clock of camera 2 (+) MIPI lane 0 data of camera 2 (-) MIPI lane 0 data of camera 2 (+) MIPI lane 1 data of camera 2 (-) MIPI lane 1 data of camera 2 (+) MIPI lane 2 data of camera 2 (-) MIPI lane 2 data of camera 2 (+) MIPI lane 3 data of camera 2 (-) MIPI lane 3 data of camera 2 (+) MIPI clock of camera 3 (-) MIPI clock of camera 3 (+) MIPI lane 0 data of camera 3 (-) MIPI lane 0 data of camera 3 (+) MIPI lane 1 data of camera 3 (-) MIPI lane 1 data of camera 3 (+) 100 differential impedance. CSI3 can only receive data of RAW format. It can be used for ToF/3D camera modules but cannot be used for display. SA800U-WF_Hardware_Design 27 / 106 Smart Module Series SA800U-WF Hardware Design CAM0_MCLK J1-91 DO CAM1_MCLK J1-95 DO CAM2_MCLK J1-99 DO CAM3_MCLK J1-103 DO CAM0_STROBE J1-122 DO CAM1_STROBE J1-116 DO CAM2_STROBE J1-118 DO CAM0_RST J1-100 DO CAM1_RST J1-96 DO CAM2_RST J1-124 DO CAM3_RST J1-126 DO CAM0_PWDN J1-114 DO CAM1_PWDN J1-120 DO CAM2_PWDN J1-106 DO CAM3_PWDN J1-112 DO CAM0_AVDD_EN J1-102 DO CAM1_AVDD_EN J1-98 DO CAM2_AVDD_EN J1-104 DO CAM3_AVDD_EN J1-108 DO CAM0_DVDD_EN J1-132 DO CAM1_DVDD_EN J1-130 DO Master clock of camera 0 Master clock of camera 1 Master clock of camera 2 Master clock of camera 3 Strobe of camera 0 Strobe of camera 1 Strobe of camera 2 Reset of camera 0 Reset of camera 1 Reset of camera 2 Reset of camera 3 Power down of camera 0 Power down of camera 1 Power down of camera 2 Power down of camera 3 AVDD enable of camera 0 AVDD enable of camera 1 AVDD enable of camera 2 AVDD enable of camera 3 DVDD enable of camera 0 DVDD enable of camera 1 VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. SA800U-WF_Hardware_Design 28 / 106 Smart Module Series SA800U-WF Hardware Design CAM2_DVDD_EN J1-110 DO CAM3_DVDD_EN J1-128 DO DVDD enable of camera 2 DVDD enable of camera 3 CCI0_I2C_SCL J1-142 OD CCI0 I2C clock CCI0_I2C_SDA J1-144 OD CCI0 I2C data CCI1_I2C_SDA J1-146 OD CCI1 I2C data CCI1_I2C_SCL J1-148 OD CC1 I2C clock Keypad Interfaces 1.8 V power domain. Pin Name Pin No. I/O Description DC Characteristics Comment PWRKEY J2-5 DI Turns on/off the module VOL_UP J2-9 DI Volume up VILmax = 0.63 V VIHmin = 1.17 V VOL_DOWN J2-7 DI Volume down HOME_KEY J2-145 DI Home key Sensor Interfaces Pulled up to 1.8 V internally. Active low. If unused, keep this pin open. If unused, keep this pin open. If unused, keep this pin open. Pin Name Pin No. I/O Description DC Characteristics Comment SSC_I2C1_SDA J2-8 OD SSC_I2C1_SCL J2-10 OD SSC_SPI1_CS0 J1-136 DO SSC_SPI1_CS1 J1-138 DO SSC_SPI1_CS2 J1-140 DO SSC_SPI1_CLK J1-154 DO Sensor core I2C1 data Sensor core I2C1 clock Sensor core SPI1 chip select 0 Sensor core SPI1 chip select 1 Sensor core SPI1 chip select 2 Sensor core SPI1 clock 1.8 V power domain. VOLmax = 0.45 V VOHmin = 1.35 V SA800U-WF_Hardware_Design 29 / 106 Smart Module Series SA800U-WF Hardware Design SSC_SPI1_MOSI J1-152 DO SSC_SPI1_MISO J1-150 DI SSC_SPI2_CS J1-141 DO SSC_SPI2_CLK J1-145 DO SSC_SPI2_MOSI J1-143 DO SSC_SPI2_MISO J1-147 DI MAG_INT J1-133 DI MAG_DRDY_INT J1-135 DI GYRO_INT J1-137 DI ACCEL_INT J1-139 DI ADC Interfaces Sensor core SPI1 master-out slave-in Sensor core SPI1 master-in salve-out Sensor core SPI2 chip select Sensor core SPI2 clock Sensor core SPI2 master-out slave-in Sensor core SPI2 master-in salve-out Magnetic sensor interrupt Magnetic sensor DRDY interrupt Gyroscopic sensor interrupt Acceleration sensor interrupt VILmax = 0.63 V VIHmin = 1.17 V VOLmax = 0.45 V VOHmin = 1.35 V VILmax = 0.63 V VIHmin = 1.17 V Pin Name Pin No. I/O Description DC Characteristics Comment ADC_PMU_GPIO8 J2-153 AI ADC_PMU_GPIO21 J2-151 AI General-purpose ADC interface General-purpose ADC interface Charging Interface Maximum input voltage: 1.8 V. Maximum input voltage: 4.5 V. Pin Name Pin No. I/O Description DC Characteristics Comment SA800U-WF_Hardware_Design 30 / 106 Smart Module Series SA800U-WF Hardware Design BAT_THERM J2-143 AI Battery temperature detect BAT_P J2-163 AI BAT_M J2-165 AI CS_P CS_M J2-157 AI J2-159 AI BAT_RBIAS J3-11 PO Battery voltage detect (+) Battery voltage detect (-) Current sense

(+) Current sense

(-) Power supply for NTC pull-up circuit BAT_ID J3-16 AI Battery type detect SMB_USB_IN J3-2, J3-3, J3-4, J3-5, J3-6, J3-7 PO Power output for SMB1355 parallel charging Internally pulled up. Supports 47 k NTC by default -

externally connect BAT_THERM to 47 k NTC to GND. If you need to connect 10 k NTC, pull up BAT_THERM to BAT_RBIAS with a 12 k resistor. If unused, pull BAT_THERM down to GND with a 47 k resistor. Must be connected. If NTC = 10 k, pull BAT_THERM up to BAT_RBIAS with a 12 k resistor. If NTC = 47 k, keep BAT_RBIAS open. Parallel charging is not supported by default and if it is needed please contact Quectel Technical Support. SA800U-WF_Hardware_Design 31 / 106 Smart Module Series SA800U-WF Hardware Design If unused, keep these pins open. SMB_EN_CHG J3-9 DO SMB_STAT J3-10 DI SMB_THERM J3-17 AI SMB_CS_P J3-15 AI SMB_CS_M J3-14 AI Audio Interfaces SMB1355 parallel charging enable SMB1355 parallel charging status indicator SMB1355 parallel charging temperature detect SMB1355 parallel charging current sense (+) SMB1355 parallel charging current sense (-) Pin Name Pin No. I/O Description DC Characteristics Comment CODEC_RST J2-90 DO Codec reset CODEC_INT1 J2-91 DI CODEC_INT2 J2-93 DI CODEC_SPI_CS J2-96 DO CODEC_SPI_CLK J2-92 DO CODEC_SPI_MOSI J2-94 DO CODEC_SPI_MISO J2-89 DI Codec interrupt 1 Codec interrupt 2 SPI chip select for codec SPI clock for codec SPI master-out slave-in for codec SPI master-in salve-out for codec WCD_CLK J2-43 DO WCD clock SLIMBUS_CLK J2-51 DO SLIMbus clock VOLmax = 0.45 V VOHmin = 1.35 V VILmax = 0.63 V VIHmin = 1.17 V VOLmax = 0.45 V VOHmin = 1.35 V VILmax = 0.63 V VIHmin = 1.17 V VOLmax = 0.45 V VOHmin = 1.35 V SLIMBUS_DATA0 J2-47 DIO SLIMBUS_DATA1 J2-49 DIO SLIMbus data bit 0 SLIMbus data bit 1 VILmax = 0.63 V VIHmin = 1.17 V VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. SA800U-WF_Hardware_Design 32 / 106 Smart Module Series SA800U-WF Hardware Design I2S1_WS J2-79 DO I2S1 word select I2S1_MCLK J2-81 DO I2S1 master clock VOLmax = 0.45 V VOHmin = 1.35 V I2S1_SCK J2-83 DO I2S1 bit clock I2S1_DATA0 J2-87 DIO I2S1_DATA1 J2-85 DIO I2S1 data channel 0 I2S1 data channel 1 I2S2_WS J2-55 DO I2S2 word select I2S2_SCK J2-57 DO I2S2 bit clock I2S2_DATA0 J2-59 DIO I2S2_DATA1 J2-61 DIO I2S2 data channel 0 I2S2 data channel 1 I2S3_WS J2-63 DO I2S3 word select I2S3_SCK J2-73 DO I2S3 bit clock I2S3_DATA0 J2-69 DIO I2S3_DATA1 J2-65 DIO I2S3_DATA2 J2-67 DIO I2S3_DATA3 J2-71 DIO I2S3 data channel 0 I2S3 data channel 1 I2S3 data channel 2 I2S3 data channel 3 GPIO Interfaces VILmax = 0.63 V VIHmin = 1.17 V VOLmax = 0.45 V VOHmin = 1.35 V VOLmax = 0.45 V VOHmin = 1.35 V VILmax = 0.63 V VIHmin = 1.17 V VOLmax = 0.45 V VOHmin = 1.35 V VOLmax = 0.45 V VOHmin = 1.35 V VILmax = 0.63 V VIHmin = 1.17 V VOLmax = 0.45 V VOHmin = 1.35 V Pin Name Pin No. I/O Description DC Characteristics Comment GPIO_25 J2-2 DIO GPIO_42 J2-64 DIO GPIO_44 J2-66 DIO GPIO_49 J2-78 DIO GPIO_50 J2-70 DIO General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output VILmax = 0.63 V VIHmin = 1.17 V VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. SA800U-WF_Hardware_Design 33 / 106 Smart Module Series SA800U-WF Hardware Design GPIO_52 J2-68 DIO GPIO_122 J2-74 DIO GPIO_124 J2-76 DIO GPIO_128 J2-132 DIO GPIO_129 J2-136 DIO GPIO_134 J2-72 DIO GPIO_135 J2-134 DIO SPI Interfaces General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output General-purpose input/output Pin Name Pin No. I/O Description DC Characteristics Comment SPI2_CLK J2-52 DO SPI2 clock SPI2_CS J2-54 DO SPI2 chip select SPI2_MOSI J2-58 DO SPI2 master-out slave-in VOLmax = 0.45 V VOHmin = 1.35 V SPI2_MISO J2-56 DI SPI2 master-in salve-out VILmax = 0.63 V VIHmin = 1.17 V SPI0_CLK J2-86 DO SPI0 clock SPI0_CS J2-80 DO SPI0 chip select SPI0_MOSI J2-82 DO SPI0 master-out slave-in VOLmax = 0.45 V VOHmin = 1.35 V SPI0_MISO J2-84 DI SPI0 master-in salve-out VILmax = 0.63 V VIHmin = 1.17 V SPI11_CLK J2-99 DO SPI11 clock SPI11_CS J2-101 DO SPI11 chip select VOLmax = 0.45 V VOHmin = 1.35 V SPI11_MISO J2-97 DI SPI11_MOSI J2-95 DO SPI11 master-in salve-out VILmax = 0.63 V VIHmin = 1.17 V SPI11 master-out slave-in VOLmax = 0.45 V VOHmin = 1.35 V RGB interfaces 1.8 V power domain. SA800U-WF_Hardware_Design 34 / 106 Smart Module Series SA800U-WF Hardware Design R_LED J2-152 AO G_LED J2-156 AO B_LED J2-154 AO DisplayPort Interface Current source for red LED Current source for green LED Current source for blue LED Pin Name Pin No. I/O Description DC Characteristics Comment EDP_AUX_P J2-129 AIO EDP_AUX_N J2-131 AIO SBU_SW_OE J2-1 DO SBU_SW_SEL J2-3 DO Vibrator Drive Interface DisplayPort auxiliary channel

(+) DisplayPort auxiliary channel

(-) DisplayPort auxiliary channel switch output enable DisplayPort auxiliary channel switch select VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. Pin Name Pin No. I/O Description DC Characteristics Comment HAP_PWM_IN J3-18 DI HAP_P J3-20 AO HAP_M J3-19 AO Haptic PWM input Haptic driver output (+) Haptic driver output (-) UFS Interface Pin Name Pin No. I/O Description DC Characteristics Comment UFS_DET J1-43 DI UFS card hot-plug detect UFS_CLK J1-39 DO UFS card clock UFS_TX_P J1-33 AO UFS_TX_M J1-35 AO UFS card transmit (+) UFS card transmit (-) UFS is not supported by default. SA800U-WF_Hardware_Design 35 / 106 Smart Module Series SA800U-WF Hardware Design UFS_RX_P J1-29 AI UFS_RX_M J1-27 AI UFS card receive

(+) UFS card receive

(-) PWM Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment PWM_PMI_GPIO5 J2-146 DO PWM output PWM_PMI_GPIO8 J2-144 DO PWM output 1.8 V power domain. Flashlight Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment FLASH_LED1 FLASH_LED2 FLASH_LED3 VRTC Interface J4-23, J4-24 J4-20, J4-21 J4-5, J4-6 AO AO AO Flash/torch driver output 1 Flash/torch driver output 2 Flash/torch driver output 3 ILED1 = 1.5 A ILED2 = 1.5 A ILED3 = 0.75 A Support flash and torch modes. Pin Name Pin No. I/O Description DC Characteristics Comment VRTC J2-133 PI/P O Power supply for RTC Vnom = 3.2 V VI = 2.53.2 V Emergency Download Interface Pin Name Pin No. I/O Description DC Characteristics Comment USB_BOOT J2-130 DI Forces the module into emergency download mode Pulling it up to VREG_S4A_1V8 during power-up will force the module to enter emergency download mode. I2C Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment I2C4_SDA J2-4 OD I2C4 data I2C4_SCL J2-6 OD I2C4 clock 1.8 V power domain. SA800U-WF_Hardware_Design 36 / 106 Smart Module Series SA800U-WF Hardware Design I2C10_SCL J2-75 OD I2C10 clock I2C10_SDA J2-77 OD I2C10 data Other Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment VCONN_EN J3-30 DO VCONN enable VCONN J3-29 PI CBL_PWR_N J1-134 DI DBG_TXD J2-137 DO DBG_RXD J2-135 DI PMU_GPIO10 J2-147 DIO PMU_GPIO13 J2-149 DIO Reserved Pins Power supply for active cables Initiates power-on when grounded. Debug UART transmit Debug UART receive General-purpose input/output General-purpose input/output VOLmax = 0.45 V VOHmin = 1.35 V VILmax = 0.63 V VIHmin = 1.17 V VILmax = 0.63 V VIHmin = 1.17 V VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. Pin Name Pin No. Comment RESERVED J2-88, J2-138, J3-22, J3-23, J3-24, J3-25, J3-26, J3-27, J4-1 Keep these pins open. SA800U-WF_Hardware_Design 37 / 106 Smart Module Series SA800U-WF Hardware Design 3.4. Power Supply 3.4.1. Power Supply Pins SA800U-WF provides 10 VBAT pins, which are dedicated for connection with external power supply. 3.4.2. Decrease Voltage Drop The power supply range of the module is from 3.55 V to 4.4 V, and the recommended value is 3.8 V. The power supply performance, such as load capacity, voltage ripple, etc. directly influences the modules performance and stability. Under ultimate conditions, the module may have a transient peak current up to 3 A. If the power supply capability is not sufficient, there will be voltage drops, and if the voltage drops below 3.1 V, the module will be powered off automatically. Therefore, make sure the input voltage will never drop below 3.1 V. Figure 3: Voltage Drop Sample To decrease voltage drop, a bypass capacitor of about 100 F with low ESR (ESR = 0.7 ) should be used for the VBAT inputs, and a multi-layer ceramic chip capacitor (MLCC) array should also be used due to its ultra-low ESR. It is recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) to form the MLCC array, and place these capacitors close to the VBAT pins. The width of VBAT traces should be no less than 3 mm. In principle, the longer the VBAT trace is, the wider it should be. In addition, in order to get a stable power source, it is suggested to use a 2000 W TVS and place it as close to the VBAT pins as possible to increase voltage surge withstand capability. SA800U-WF_Hardware_Design 38 / 106 3.1 VVoltage3.8 VInput current3 A Smart Module Series SA800U-WF Hardware Design The following figure shows the structure of the power supply. Figure 4: Star Structure of Power Supply 3.4.3. Reference Design for Power Supply The power design for the module is important, as the performance of module largely depends on the power source. The power supply of SA800U-WF should be able to provide sufficient current of at least 3 A. By default, it is recommended to use a battery to supply power for the module. If battery is not used, it is recommended to use a regulator for the module. If the voltage difference between the input and output is not too high, it is suggested to use an LDO to supply power for the module. If there is a big voltage difference between the input source and the desired output (VBAT), a buck converter is preferred to be used as the power supply. The following figure shows a reference design for +12 V input power source which adopts a buck converter (TPS54428DDAR) from TI. The typical output voltage is 3.8 V and the maximum rated current is 5.3 A. SA800U-WF_Hardware_Design 39 / 106 ModuleVBATVBATC1100 F+C2100 nFC333 pFC410 pFD1 Smart Module Series SA800U-WF Hardware Design Figure 5: Reference Circuit of Power Supply NOTES 1. It is recommended to switch off the power supply for the module in abnormal condition, and then switch on the power to restart the module. 2. The module supports battery charging function by default. If battery is not used and the above power supply design is adopted, make sure the charging function is disabled by software, or connect a Schottky diode with higher than 5 A average current capacity between the output of the inductor L1 and the VBAT pins of the module. 3. When the battery voltage is below 3.1 V, the system will trigger automatic shutdown, so the design of power supply should be consistent with the configuration of fuel gauge driver. 3.5. Turn on and off Scenarios 3.5.1. Turn on the Module Using PWRKEY The module can be turned on by driving PWRKEY low for at least 1.6 s. PWRKEY is pulled up to 1.8 V internally. It is recommended to use an open drain/collector driver to control PWRKEY. A simple reference circuit is illustrated in the following figure. SA800U-WF_Hardware_Design 40 / 106 DC_INC1C2TPS54428DDARU1VBAT 10 FC822 FC9100 nFR2120K27KR322 F10K1 %1 %EN100 nFC3R1GNDGNDSSVREG5C722 FVFBINVBSTSWL1 3.3 H 1 F8 nF100 nFC4C5C6 Smart Module Series SA800U-WF Hardware Design Figure 6: Turn on the Module Using Driving Circuit Another way to control PWRKEY is using a button directly. A TVS component should be placed nearby the button for ESD protection. A reference circuit is shown in the following figure. Figure 7: Turn on the Module Using Keystroke The timing of turning on is illustrated in the following figure. SA800U-WF_Hardware_Design 41 / 106 Turn on pulsePWRKEY4.7K47K>1.6 sR1R2Q1R31KPWRKEYS1Close to S1TVS1K Smart Module Series SA800U-WF Hardware Design Figure 8: Timing of Turning on the Module NOTES 1. The turn-on timing might be different from the above figure when the module powers on for the first time. 2. Make sure that VBAT is stable before pulling down PWRKEY. It is recommended to wait until VBAT to be stable for at least 30 ms before pulling down PWRKEY. Additionally, PWRKEY cannot be pulled down all the time. 3.5.2. Turn on the Module Automatically Using CBL_PWR_N The module can be turned on automatically by driving the CBL_PWR_N pin to GND through a 1 k resistor. CBL_PWR_N pin is pulled up internally. A simple reference circuit is illustrated in the following figure. SA800U-WF_Hardware_Design 42 / 106 VBAT (Typ. 3.8 V)PWRKEY> 1.6 sOthersVREG_S4A_1V830 sSD_LDO13A40.7 msSoftware controlledLDO24A_3V075ActiveLDO12A_1V8Note2Software controlled Smart Module Series SA800U-WF Hardware Design Figure 9: Turn on the Module Using CBL_PWR_N NOTE The module can be turned on automatically by driving CBL_PWR_N pin to GND, and cannot be turned off manually unless you shut down the VBAT. 3.5.3. Turn off/Restart the Module Pull down PWRKEY for at least 1 s, and then choose to turn off the module when a prompt window comes up. Another way to restart the module is to drive PWRKEY low for at least 8 s. The module will execute forced restart. The forced restart timing is illustrated in the following figure. SA800U-WF_Hardware_Design 43 / 106 CBL_PWR_NModule1KVBATPWRKEYOthers> 8sRestart Smart Module Series SA800U-WF Hardware Design Figure 10: Timing of Restarting the Module 3.6. VRTC Interface The RTC (Real Time Clock) can be powered by an external power source through VRTC when the module is powered down and there is no power supply for the VBAT. The external power source can be a rechargeable battery (such as coin cell) according to application demands. The following reference circuit design shows a design where an external battery is utilized to power RTC. Figure 11: RTC Powered by Coin Cell If RTC is ineffective, it can be synchronized through network after the module is powered on. 2.53.2 V input voltage range and 3.2 V typical value for VRTC, when VBAT is disconnected. When powered by VBAT, the RTC error is 50 ppm. When powered by VRTC, the RTC error is about 200 ppm. If rechargeable battery is used, the ESR of battery should be less than 2 k, and it is recommended to use the MS621FE-FL11E of SEIKO. 3.7. Power Output SA800U-WF supports output of regulated voltages for peripheral circuits. During application, it is recommended to use parallel capacitors (33 pF and 10 pF) in the circuit to suppress high-frequency noise. SA800U-WF_Hardware_Design 44 / 106 Coin CellModuleRTC CoreVRTC Smart Module Series SA800U-WF Hardware Design Table 5: Power Description Pin Name Default Voltage (V) Drive Current (mA) Comment VREG_S4A_1V8 LVS1A_1V8 LVS2A_1V8 LDO12A_1V8 1.8 1.8 1.8 1.8 SD_LDO13A 1.8/2.95 LDO14A_1V88 LDO19A_3V0 SD_LDO21A LDO24A_3V075 LDO28A_3V0 VREG_BOB 1.8 3.0 2.95 3.075 3.0 3.7 2000 300 100 300 50 50 600 800 150 150 Keep

Keep

2000 Keep 3.8. Battery Charging and Management SA800U-WF supports a fully programmable switch-mode Li-ion battery charging function. It can charge single-cell Li-ion and Li-polymer batteries. It supports QC 3.0 and QC 4.0 and the maximum charging current is up to 4.5 A. The battery charger of SA800U-WF supports trickle charging, pre-charge, constant current charging and constant voltage charging modes, which optimize the charging procedure for Li-ion and Li-polymer batteries. Trickle charging: When the battery voltage is below 2.1 V, a 45 mA trickle charging current is applied to the battery. Pre-charge: When the battery voltage is charged up and is between 2.1 V and 3.0 V

(the maximum pre-charge voltage is 2.13.0 V programmable, 3.0 V by default), the system will enter the pre-charge mode. The charging current is 500 mA (01575 mA programmable). Constant current mode (CC mode): When the battery voltage is between the maximum pre-charge voltage and 4.35 V (3.04.35 V programmable, 4.35 V by SA800U-WF_Hardware_Design 45 / 106 Smart Module Series SA800U-WF Hardware Design default), the system will switch to CC mode. The charging current is programmable from 3004500 mA. The default charging current is 500 mA for USB charging and 4000 mA for adapter. Constant voltage mode (CV mode): When the battery voltage reaches the final value 4.35 V, the system will switch to CV mode and the charging current will decrease gradually. When the charging current reduces to about 100 mA, the charging is completed. Table 6: Pin Definition of Charging Interface Pin Name Pin No. I/O Description Comment USB_VBUS VBAT J2-160, J2-162, J2-164, J2-166, J2-168, J4-13, J4-14, J4-15, J4-16, J4-17, J4-18 J1-159, J1-160, J1-161, J1-162, J1-163, J1-164, J1-165, J1-166, J1-167, J1-168 PI/PO Charging power input. Power output for OTG device. USB/adaptor insertion detect. PI/PO Power supply for the module Vmax = 14 V Vmin = 4.0 V Vnom = 5.0 V Vmax = 4.4 V Vmin = 3.55 V Vnom = 3.8 V Internally pulled up. Supports 47 k NTC by default - externally connect BAT_THERM to 47 k NTC to GND. If you need to connect 10 k NTC, pull up BAT_THERM to BAT_RBIAS with a 12 k resistor. If unused, pull BAT_THERM down to GND with a 47 k resistor. Must be connected. BAT_THERM J2-143 AI Battery temperature detect BAT_P J2-163 BAT_M J2-165 CS_P J2-157 CS_M J2-159 AI AI AI AI Battery voltage detect (+) Battery voltage detect (-) Current sense (+) Current sense (-) SA800U-WF_Hardware_Design 46 / 106 Smart Module Series SA800U-WF Hardware Design BAT_RBIAS J3-11 PO Power supply for NTC pull-up circuit BAT_ID J3-16 AI Battery type detect SMB_USB_IN J3-2, J3-3, J3-4, J3-5, J3-6, J3-7 SMB_CS_P J3-15 SMB_CS_M J3-14 SMB_THERM J3-17 SMB_EN_CHG J3-9 SMB_STAT J3-10 PO AI AI AI DO DI Power output for SMB1355 parallel charging SMB1355 parallel charging current sense (+) SMB1355 parallel charging current sense (-) SMB1355 parallel charging temperature detect SMB1355 parallel charging enable SMB1355 parallel charging status indicator If NTC = 10 k, pull BAT_THERM up to BAT_RBIAS with a 12 k resistor. If NTC = 47 k, keep BAT_RBIAS open. Parallel charging is not supported by default and if it is needed please contact Quectel Technical Support. If unused, keep these pins open. SA800U-WF supports battery temperature detection in the condition that the battery integrates a thermistor (47 k 1 % NTC thermistor with B-constant of 4050 K by default;

SDNT1608X473F4050FTF of SUNLORD is recommended) and the thermistor is connected to the BAT_THERM pin. If BAT_THERM is not connected, there will be malfunctions such as boot error, battery charging failure, battery level display error, etc. A reference design for battery charging circuit is shown below. SA800U-WF_Hardware_Design 47 / 106 Smart Module Series SA800U-WF Hardware Design Figure 12: Reference Design for Battery Charging Circuit SA800U-WF offers a fuel gauge algorithm which is able to accurately estimate the batterys health state by current and voltage monitoring techniques. Using precise measurements of battery voltage, current, and temperature, the fuel gauge provides a dependable state of charge estimate throughout the entire life of the battery and across a broad from over-discharging, and also allows you to estimate the battery life based on the battery level to timely save important data before complete power-down. range of operating conditions. It effectively protects the battery Mobile devices such as mobile phone and game machine systems are powered by batteries. When different batteries are used, the charging and discharging curve has to be modified according to the battery type to achieve the best performance. If thermistor is not available in the battery, or an adapter rather than a battery is used to power the module, BAT_THERM should be connected to GND with a 47 k resistor. Otherwise the system may be unable to detect the battery, which will cause power-on failure. BAT_P and BAT_M must be connected, and also CS_P and CS_M must be connected, otherwise there may be abnormalities in using the module. BAT_P and BAT_M are used for battery level detection, and they should be routed as a differential pair to ensure accuracy. CS_P and CS_M are used for charging current sensing, and they should be routed as a differential pair to ensure accuracy. SA800U-WF_Hardware_Design 48 / 106 GNDBAT_THERMVBAT0.01R100FNTCVBAT33 pF1 FESDUSB_VBUSAdapter or USBModuleBatteryC1C2C3R1D1D2BAT_PESDBAT_MGNDCS_MCS_P Smart Module Series SA800U-WF Hardware Design 3.9. USB Interfaces SA800U-WF provides two USB interfaces which comply with both USB 3.1 and USB 2.0 specifications and support super speed (5 Gbps) on USB 3.1, high speed (480 Mbps) and full speed (12 Mbps) modes on USB 2.0. USB1 can be used for AT command transmission, data transmission, software debugging and firmware upgrade. USB2 only supports host mode. 3.9.1. USB1 Interface 3.9.1.1. USB Type-C Mode The USB1 interface has one USB 2.0 compliant high-speed differential channel

(USB1_DP, USB1_DM) and two USB 3.1 compliant super-speed differential channels

(USB1_SS1_RX_P/M, USB1_SS2_RX_P/M, USB1_SS2_TX_P/M). USB1_SS1_TX_P/M and When Type-C is plugged in with one side up, USB_CC1 will detect the external device, and the data will be transmitted through USB_SS1; when it is plugged in with the other side up, USB_CC2 will detect the external device, and the data will be transmitted through USB_SS2. The following table shows the pin definition of USB Type-C interface. The following table shows the pin definition of USB1 interface. Table 7: Pin Definition of USB TYPE-C Interface Pin Name Pin No. I/O Description Comment USB_VBUS J2-160, J2-162, J2-164, J2-166, J2-168, J4-13, J4-14, J4-15, J4-16, J4-17, J4-18 PI/PO Charging power input. Power output for OTG device. USB/adaptor insertion detect. Vmax = 14 V Vmin = 4.0 V Vnom = 5.0 V USB1_DM J2-117 AIO USB1 2.0 differential data (-) USB1_DP J2-119 AIO USB1 2.0 differential data (+) USB1_SS1_TX_M J2-123 USB1_SS1_TX_P J2-125 USB1_SS1_RX_M J2-118 AO AO AI USB1 3.1 channel 1 super-speed transmit (-) USB1 3.1 channel 1 super-speed transmit (+) USB1 3.1 channel 1 super-speed receive (-) 90 differential impedance. USB 2.0 standard compliant. 90 differential impedance. USB 3.1 standard compliant. SA800U-WF_Hardware_Design 49 / 106 Smart Module Series SA800U-WF Hardware Design USB1_SS1_RX_P J2-120 USB1_SS2_TX_M J2-111 USB1_SS2_TX_P J2-113 USB1_SS2_RX_M J2-114 USB1_SS2_RX_P J2-112 USB_CC1 J2-141 USB_CC2 J2-139 AI AO AO AI AI AI AI USB1 3.1 channel 1 super-speed receive (+) USB1 3.1 channel 2 super-speed transmit (-) USB1 3.1 channel 2 super-speed transmit (+) USB1 3.1 channel 2 super-speed receive (-) USB1 3.1 channel 2 super-speed receive (+) USB Type-C configuration channel 1 USB Type-C configuration channel 2 The following is a reference design for USB Type-C interface:

Figure 13: USB Type-C Interface Reference Design SA800U-WF can support E-mark cable and active cable. Table 8: Pin Definition of VCONN Circuit Pin Name Pin No. I/O Description VCONN VCONN_EN J3-29 J3-30 PI Power supply for active cables DO VCONN enable SA800U-WF_Hardware_Design 50 / 106 USB1_HS_DMModuleUSB_SS1_RX_PRX2+RX2-VBUSCC1D-D+TX2-TX2+CC2USB_CC1USB_CC2RX1+RX1-TX1+TX1-USB Type-CC3C4C7C8USB1_HS_DPUSB_VBUSUSB_SS1_RX_MUSB_SS1_TX_PUSB_SS1_TX_MUSB_SS2_RX_PUSB_SS2_RX_MUSB_SS2_TX_PUSB__TX_MSS2C1C2C5C6 Smart Module Series SA800U-WF Hardware Design SMB_USB_IN J3-2, J3-3, J3-4, J3-5, J3-6, J3-7 PO Power output for SMB1355 parallel charging If you need to support E-mark cables or active cables, you need to add the following reference circuit:

Figure 14: VCONN Reference Design 3.9.1.2. DisplayPort Mode SA800U-WF supports DisplayPort mode with 4 lanes up to 4K @ 60 fps over USB Type-C. The pin definition of USB Type-C/DisplayPort mode is listed below:

Table 9: Pin Definition of USB Type-C/DisplayPort Mode Pin Name USB Type-C Mode DisplayPort Mode USB1_SS2_RX_P/M USB1_SS2_RX_P/M DP_LANE0_P/M USB1_SS2_TX_P/M USB1_SS2_TX_P/M DP_LANE1_P/M USB1_SS1_RX_P/M USB1_SS1_RX_P/M DP_LANE3_P/M USB1_SS1_TX_P/M USB1_SS1_TX_P/M DP_LANE2_P/M EDP_AUX_P/N SBU1/2 DP_AUX_P/N USB1_DP/M USB1_DP/M USB1_DP/M USB_CC1/CC2 USB_CC1/CC2 HOTPLUG_DET/VCONN USB_VBUS USB_VBUS USB_VBUS GND GND GND SA800U-WF_Hardware_Design 51 / 106 SMB_USB_INVCONN_ENVBAT0R10K100KVCONN1 FR1R2R3Q1C1Q2D1 Smart Module Series SA800U-WF Hardware Design The reference design of DisplayPort is shown below:

Figure 15: DisplayPort Reference Design 3.9.2. USB2 Interface USB2 only supports host mode. The following table shows the pin definition of USB2 interface. Table 10: Pin Definition of USB2 Pin Name Pin No. I/O Description Comment SA800U-WF_Hardware_Design 52 / 106 USB1_HS_DPModuleUSB1_SS1_RX_PRX2+RX2-USB_VBUSCC1D+D-TX2-TX2+CC2USB_CC1USB_CC2RX1+RX1-TX1+TX1-USB Type-CC1C2C7C8USB1_HS_DMUSB_VBUSUSB1_SS1_RX_MUSB1_SS1_TX_PUSB1_SS1_TX_MUSB1_SS2_RX_PUSB1_SS2_RX_MUSB1_SS2_TX_PUSB1__TX_MSS2SBU1SBU2OEHSD2+HSD2-HSD1+HSD1-VCCSD+D-GNDLDO24A_3V075EDP_AUX_PEDP_AUX_NLDO24A_3V075100K100KSBU_SW_OEVREG_S4A_1V80.1 F0.1 FModule1 FSBU1SBU22.2KSGM7227YMS10G/TRSBU_SW_SELC3C4C5C6C1C2R1R1R3C3 Smart Module Series SA800U-WF Hardware Design USB2_DP J2-105 AIO USB2_DM J2-107 AIO USB2 2.0 differential data (+) 90 differential impedance. USB 2.0 standard compliant. Only support host mode. USB2 2.0 differential data (-) USB2_SS_TX_M J2-108 AO USB2_SS_TX_P J2-106 AO USB2_SS_RX_M J2-100 AI USB2_SS_RX_P J2-102 AI USB2 3.1 channel 1 super-speed transmit (-) USB2 3.1 channel 1 super-speed transmit (+) USB2 3.1 channel 1 super-speed receive (-) USB2 3.1 channel 1 super-speed receive (+) 90 differential impedance. USB 3.1 standard compliant. Only support host mode. Figure 16: USB Type-A Interface Reference Design (USB2 for Host Mode) 3.9.3. Design Principles Table 11: USB Trace Length Inside the Module Pin No. Signal Length (mm) Length Difference (P - M) J2-117 USB1_DM J2-119 USB1_DP J2-123 USB1_SS1_TX_M J2-125 USB1_SS1_TX_P J2-118 USB1_SS1_RX_M 39.59 39.44 22.37 23.27 19.53

-0.15 0.90 0.64 SA800U-WF_Hardware_Design 53 / 106 USB2_DPUSB2_DMModuleDPDMVBUSGND100 nF4.7 FAW3605DNRSWVINENVOUTVOUTGPIO`1 HVBAT10 F1 FGND10KUSB2_VBUSUSB2_VBUSUSB2_SS_RX_MUSB2_SS_RX_PUSB2_SS_TX_MUSB2_SS_TX_PC3C4C5C6RX-RX+TX-TX+L1C1R1C2C8C9D1D2D3 Smart Module Series SA800U-WF Hardware Design J2-120 USB1_SS1_RX_P J2-111 USB1_SS2_TX_M J2-113 USB1_SS2_TX_P J2-114 USB1_SS2_RX_M J2-112 USB1_SS2_RX_P J2-131 EDP_AUX_N J2-129 EDP_AUX_P J2-107 USB2_DM J2-105 USB2_DP J2-108 USB2_SS_TX_M J2-106 USB2_SS_TX_P J2-100 USB2_SS_RX_M J2-102 USB2_SS_RX_P 20.17 19.65 19.96 15.36 14.86 26.00 25.73 19.93 19.90 15.93 15.60 11.58 11.99 0.31

-0.50

-0.27

-0.03

-0.33 0.41 To ensure USB performance, follow the following principles while designing USB interface. It is important to route the USB signal traces as differential pairs with total grounding. The impedance of USB differential traces is 90 . Pay attention to the influence of junction capacitance of ESD protection devices on USB data lines. Typically, the capacitance value should be less than 2 pF for USB 2.0 and less than 0.5 pF for USB 3.1. Do not route signal traces under crystal oscillators, magnetic devices and RF signal traces. It is important to route the USB differential traces in inner-layer with ground shielding on not only upper and lower layers but also right and left sides. Do not route USB 3.1 signal lines under RF signal lines. Crossing or parallel with RF signal lines is forbidden. Isolation between USB 3.1 signals and RF signals should be more than 90 dB. Otherwise, the RF signals will be seriously affected. Keep the ESD protection devices as close as possible to the USB connector. Make sure the intra-pair length difference within USB 2.0 differential pair and that within USB 3.1 RX or TX differential pair does not exceed 0.7 mm. The spacing between USB signals and all other signals should be at least 4 times the trace width while that between RX and TX should be at least 3 times the trace width. length difference between EDP_AUX_N and For DisplayPort, routing the EDP_AUX_P should be less than 7 mm. SA800U-WF_Hardware_Design 54 / 106 Smart Module Series SA800U-WF Hardware Design 3.10. UART Interface The module provides one debug UART used for debugging by default. The following table shows the pin definition of debug UART interface. Table 12: Pin Definition of Debug UART Interface Pin Name Pin No. DBG_TXD J2-137 DBG_RXD J2-135 I/O DO DI Description Comment Debug UART transmit Debug UART receive 1.8 V power domain. Debug UART is a 2-wire UART interface of 1.8 V power domain. A level translator chip should be used if your application is equipped with a 3.3 V UART interface. The level translator chip TXS0102DCUR provided by Texas Instruments is recommended. The following figure shows a reference design. Figure 17: Reference Circuit with Level Translator Chip The following figure is an example of connection between SA800U-WF and PC. A level translator and an RS-232 level translator chip is recommended to be added between the module and PC, as shown below. SA800U-WF_Hardware_Design 55 / 106 VCCAVCCBOEA1A2GNDB1B2VREG_S4A_1V8DBG_RXDDBG_TXDRXD_3.3VTXD_3.3VVDD_3.3VTXS0102DCURC1100pFC2U1100pF Smart Module Series SA800U-WF Hardware Design Figure 18: RS-232 Level Match Circuit 3.11. PCIe Interfaces SA800U-WF provides two PCIe interfaces. PCIe0 is a Gen 2 1-lane interface that transmits up to 5 Gbps/lane. PCIe1 is a Gen 3 1-lane interface that transmits up to 8 Gbps/lane. Table 13: Pin Definition of PCIe Interfaces Pin Name Pin No. I/O Description Comment PCIE0_RST_N J1-1 DO PCIe0 reset PCIE0_WAKE_N J1-3 DI PCIe0 wakes up host PCIE0_CLKREQ_N J1-5 DI PCIe0 clock request PCIE0_REFCLK_P J1-15 AO PCIe0 reference clock (+) PCIE0_REFCLK_M J1-17 AO PCIe0 reference clock (-) PCIE0_TX_P J1-11 AO PCIe0 transmit (+) PCIE0_TX_M J1-9 AO PCIe0 transmit (-) PCIE0_RX_P J1-21 AI PCIe0 receive (+) PCIE0_RX_M J1-23 AI PCIe0 receive (-) PCIE1_RST_N J1-107 DO PCIe1 reset PCIE1_WAKE_N J1-111 DI PCIe1 wakes up host Control the characteristic impedance as 85 . SA800U-WF_Hardware_Design 56 / 106 TXS0102DCURRXD_3.3VVCCAModuleGNDGND1.8VVCCB3.3VDIN1ROUT3ROUT2ROUT1DIN4DIN3DIN2DIN5FORCEON3.3VDOUT1DOUT2DOUT3DOUT4DOUT5RIN3RIN2RIN1VCCGNDOESN65C3238DB-9TXDRXDGNDDBG_TXDDBG_RXDTXD_1.8VRXD_1.8V/FORCEOFF/INVALIDR1OUTBTXD_3.3V Smart Module Series SA800U-WF Hardware Design PCIE1_CLKREQ_N J1-109 DI PCIe1 clock request PCIE1_REFCLK_P J1-121 AO PCIe1 reference clock (+) PCIE1_REFCLK_M J1-123 AO PCIe1 reference clock (-) PCIE1_TX_P J1-129 AO PCIe1 transmit (+) PCIE1_TX_M J1-127 AO PCIe1 transmit (-) PCIE1_RX_P J1-115 AI PCIe1 receive (+) PCIE1_RX_M J1-117 AI PCIe1 receive (-) Control the characteristic impedance as 85 . SA800U-WF_Hardware_Design 57 / 106 PCIE_REFCLK_PPCIE_REFCLK_MPCIE_RX_PPCIE_RX_MPCIE_TX_PPCIE_TX_MPCIE0_REFCLK_PPCIE0_REFCLK_MPCIE0_RX_PPCIE0_RX_MPCIE0_TX_PPCIE0_TX_MPCIE0_CLKREQ_NPCIE0_RST_NPCIE0_WAKE_NPCIE_CLKREQ_NPCIE_RST_NPCIE_WAKE_NC1C2PCIE_REFCLK_PPCIE_REFCLK_MPCIE_RX_PPCIE_RX_MPCIE_TX_PPCIE_TX_MPCIE1_REFCLK_PPCIE1_REFCLK_MPCIE1_RX_PPCIE1_RX_MPCIE1_TX_PPCIE1_TX_MPCIE1_CLKREQ_NPCIE1_RST_NPCIE1_WAKE_NPCIE_CLKREQ_NPCIE_RST_NPCIE_WAKE_NVREG_S4A_1V8R11KR210KR310KC3 C4 optionalRTL8111HModule Smart Module Series SA800U-WF Hardware Design Figure 19: PCIe Interfaces Reference Circuit To enhance the reliability and availability in applications, follow the criteria below in the circuit design of PCIe interfaces:

Keep the PCIe signals away from noisy signals, such as clock signals, SMPS, and so forth. It is recommended to place the AC coupling capacitors (C1/C2/C3/C4) close to the TX side to ensure signal integrity of trace routing on PCB. Keep the intra-pair length difference within each differential data pair less than 0.7 mm during PCIe trace routing. Trace length matching between the reference clock, TX, and RX pairs is not required. Keep the impedance of PCIe differential traces as 85 10 %. You must not route PCIe data traces under components or cross them with other traces. The spacing between PCIe signals and all other signals and that between RX and TX should be at least 4 times the trace width. 3.12. SD Card Interface SA800U-WF supports two SDIO interfaces (SDC2 and SDC4). The SDIO function of SDC4 is not supported by default. As the SD card interface, SDC2 complies with SD 3.0 specifications. The pin definition is shown below. Table 14: Pin Definition of SD Card Interface Pin Name Pin No. I/O Description Comment SD_LDO21A J1-151, J1-153, J1-155 PO SD card power supply Vnom = 2.95 V IOmax = 800 mA SD_LDO13A J4-11 PO 1.8/2.95 V output power for SD card pull-up circuits Vnom = 1.8/2.95 V IOmax = 50 mA SD_CLK J1-45 DO SD card clock SD_CMD J1-47 DO SD card command SD_DATA0 J1-51 DIO SDIO data bit 0 SD_DATA1 J1-53 DIO SDIO data bit 1 Control characteristic impedance as 45 . SA800U-WF_Hardware_Design 58 / 106 Smart Module Series SA800U-WF Hardware Design SD_DATA2 J1-57 DIO SDIO data bit 2 SD_DATA3 J1-55 DIO SDIO data bit 3 SD_DET J1-49 DI SD card hot-plug detect Active low. SDC4_CLK J1-86 DO SDIO clock SDC4_CMD J1-92 DO SDIO command SDC4_DATA0 J1-82 DIO SDIO data bit 0 SDC4_DATA1 J1-84 DIO SDIO data bit 1 SDC4_DATA2 J1-88 DIO SDIO data bit 2 SDC4_DATA3 J1-90 DIO SDIO data bit 3 SDIO function is not supported by default. Can be multiplexed into GPIOs. A reference circuit for SD card interface is shown as below. Figure 20: Reference Circuit for SD Card Interface SD_LDO21A is a peripheral power supply driver for SD card. The maximum drive current is about 800 mA. Because of the high drive current, it is recommended that the trace width should be 0.8 mm or above. To ensure the stability of drive power, a 4.7 F and a 33 pF capacitor should be added in parallel near the SD card connector. SA800U-WF_Hardware_Design 59 / 106 SD_CMD120KNM_51KSD_DATA3SD_DATA2VREG_S4A_1V8SD_CLKSD_DATA0SD_DETSD_DATA1P1-DAT2P2-CD/DAT3P3-CMDP4-VDDP5-CLKP8-DAT1GNDP6-VSSP7-DAT0DETECTIVEGNDGNDGND12345678910111213SD_LDO21A33R33R33R33R33R33R1K33 pF4.7 FSD_LDO13AModuleR1R2R3R4R5R6NM_51KNM_10KNM_51KNM_51KR7R8R9R10R11R12R13D1D2D3D4D5D6D7D8C1C2SD Card Connector Smart Module Series SA800U-WF Hardware Design SD_CMD, SD_CLK, SD_DATA0, SD_DATA1, SD_DATA2 and SD_DATA3 are all high speed signal lines. In PCB design, control the characteristic impedance of them to 45 , and do not cross them with other traces. It is recommended to route these traces on the inner layer of PCB, and keep them of the same trace length. Additionally, SD_CLK needs separate ground shielding. Layout guidelines:

Control characteristic impedance to 45 10 %, and add ground shielding. The length difference between SD_CLK and SD_DATA should be less than 2 mm. The spacing between SDIO signals and all other signals and that between different SDIO signals should be at least 1.5 times the trace width. For SDR104 mode, the total routing length recommended is less than 50 mm, and the total capacitance should be less than 5 pF For SDR50 and DDR50 modes, the total routing length recommended is less than 150 mm, and the total capacitance should be less than 10 pF Table 15: SD Card Signal Trace Length Inside the Module Pin No. Signal Length (mm) J1-45 J1-47 J1-51 J1-53 J1-57 J1-55 SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 16.07 14.78 15.32 14.61 14.43 14.10 3.13. GPIO Interfaces SA800U-WF has abundant GPIO pins with power domain of 1.8 V. The pin definition is listed below. SA800U-WF_Hardware_Design 60 / 106 Smart Module Series SA800U-WF Hardware Design Table 16: Pin Definition of GPIO Interfaces Pin Name Pin No. I/O Description Comment GPIO_25 J2-2 DIO General-purpose input/output GPIO_42 J2-64 DIO General-purpose input/output GPIO_44 J2-66 DIO General-purpose input/output Wakeup 1) GPIO_49 J2-78 DIO General-purpose input/output Wakeup GPIO_50 J2-70 DIO General-purpose input/output GPIO_52 J2-68 DIO General-purpose input/output Wakeup GPIO_122 J2-74 DIO General-purpose input/output Wakeup GPIO_124 J2-76 DIO General-purpose input/output Wakeup GPIO_128 J2-132 DIO General-purpose input/output Wakeup GPIO_129 J2-136 DIO General-purpose input/output Wakeup GPIO_134 J2-72 DIO General-purpose input/output GPIO_135 J2-134 DIO General-purpose input/output NOTES 1) Wakeup: Interrupt pins that can wake up the system. 1. 2. For more details about GPIO configuration, see document [2]. 3.14. I2C Interfaces SA800U-WF provides six groups of I2C interfaces. As an open drain output, each I2C interface should be pulled up to 1.8 V. CCI_I2C bus is controlled by Linux Kernel code and supports connection to video output related devices. SSC_I2C only supports connection to sensor which is dedicated to support low-power and always-on use cases. Table 17: Pin Definition of I2C Interfaces Pin Name Pin No. I/O Description Comment SA800U-WF_Hardware_Design 61 / 106 Smart Module Series SA800U-WF Hardware Design TP_I2C_SCL J2-44 OD TP I2C clock TP_I2C_SDA J2-46 OD TP I2C data I2C4_SDA J2-4 OD I2C4 data I2C4_SCL J2-6 OD I2C4 clock I2C10_SCL J2-75 OD I2C10 clock I2C10_SDA J2-77 OD I2C10 data CCI0_I2C_SCL J1-142 OD CCI0 I2C clock CCI0_I2C_SDA J1-144 OD CCI0 I2C data CCI1_I2C_SDA J1-146 OD CCI1 I2C data CCI1_I2C_SCL J1-148 OD CC1 I2C clock Used for touch panel. Used for video output devices. SSC_I2C1_SDA J2-8 OD Sensor core I2C1 data SSC_I2C1_SCL J2-10 OD Sensor core I2C1 clock Used for external sensors. 3.15. SPI Interfaces SA800U-WF provides three SPI interfaces which only support master mode. Table 18: Pin Definition of SPI Interfaces Pin Name Pin No I/O Description Comment SPI2_CLK J2-52 DO SPI2 clock SPI2_CS J2-54 DO SPI2 chip select SPI2_MISO J2-56 DI SPI2 master-in salve-out SPI2_MOSI J2-58 DO SPI2 master-out slave-in 1.8 V power domain. SPI0_CLK J2-86 DO SPI0 clock SPI0_CS J2-80 DO SPI0 chip select SPI0_MISO J2-84 DI SPI0 master-in salve-out SA800U-WF_Hardware_Design 62 / 106 Smart Module Series SA800U-WF Hardware Design SPI0_MOSI J2-82 DO SPI0 master-out slave-in SPI11_CLK J2-99 DO SPI11 clock SPI11_CS J2-101 DO SPI11 chip select SPI11_MISO J2-97 DI SPI11 master-in salve-out SPI11_MOSI J2-95 DO SPI11 master-out slave-in 3.16. ADC Interfaces SA800U-WF provides two analog-to-digital converter (ADC) interfaces, and the pin definition is shown below. Table 19: Pin Definition of ADC Interfaces Pin Name Pin No. I/O Description Comment ADC_PMU_GPIO8 J2-153 AI ADC_PMU_GPIO21 J2-151 AI General-purpose ADC interface General-purpose ADC interface Maximum input voltage: 1.8 V. Maximum input voltage: 4.5 V. The accuracy for ADC_PMU_GPIO8 is 6 mV typically, while that for ADC_PMU_GPIO21 is 10 mV typically. 3.17. Vibrator Drive Interface SA800U-WF supports eccentric rotating mass (ERM) motor and linear resonant actuator SA800U-WF_Hardware_Design 63 / 106 Smart Module Series SA800U-WF Hardware Design

(LRA). The pin definition of vibrator drive interface is listed below. Table 20: Pin Definition of Vibrator Drive Interface Pin Name Pin No. I/O Description HAP_PWM_IN J3-18 HAP_P HAP_M J3-20 J3-19 DI AO AO Haptic PWM input Haptic driver output (+) Haptic driver output (-) The vibrator is driven by an exclusive circuit, and a reference circuit design is shown below. Figure 21: Reference Circuit for Vibrator Connection 3.18. LCM Interfaces Based on MIPI DSI standard, the video output interfaces (LCM interfaces) of SA800U-WF support 2560 1600 @ 60 fps VESA DSC 1.1 primary display with 4 lanes. Additionally, with a MIPI to HDMI converter (LT9611 is recommended), its 8 lanes can support QUXGA display (resolution: 3840 2160). The module supports dual-LCD SA800U-WF_Hardware_Design 64 / 106 ModuleVIB+MotorVIB-33 pFC1HAP_PHAP_M33 pFC2 Smart Module Series SA800U-WF Hardware Design independent display: default - DSI + DP (over USB Type-C), optional - DSI0 + DSI1. Please note that DSI1 does not support screens with command mode. Table 21: Pin Definition of LCM Interfaces Pin Name Pin No. I/O Description Comment LDO14A_1V88 J4-9 PO 1.8 V output for IOVDD of LCDs Vnom = 1.8 V IOmax = 50 mA LCD_RST J2-62 DO LCD reset Active low. 1.8 V power domain. LCD_TE J2-60 DI LCD tearing effect 1.8 V power domain. DSI0_CLK_N J2-26 AO LCD0 MIPI clock (-) DSI0_CLK_P J2-28 AO LCD0 MIPI clock (+) DSI0_LN0_N J2-38 AO LCD0 MIPI lane 0 data (-) DSI0_LN0_P J2-40 AO LCD0 MIPI lane 0 data (+) DSI0_LN1_N J2-32 AO LCD0 MIPI lane 1 data (-) DSI0_LN1_P J2-34 AO LCD0 MIPI lane 1 data (+) DSI0_LN2_N J2-20 AO LCD0 MIPI lane 2 data (-) DSI0_LN2_P J2-22 AO LCD0 MIPI lane 2 data (+) DSI0_LN3_N J2-14 AO LCD0 MIPI lane 3 data (-) DSI0_LN3_P J2-16 AO LCD0 MIPI lane 3 data (+) 100 differential impedance. DSI1_CLK_N J2-21 AO LCD1 MIPI clock (-) DSI1_CLK_P J2-19 AO LCD1 MIPI clock (+) DSI1_LN0_N J2-13 AO LCD1 MIPI lane 0 data (-) DSI1_LN0_P J2-15 AO LCD1 MIPI lane 0 data (+) DSI1_LN1_N J2-37 AO LCD1 MIPI lane 1 data (-) DSI1_LN1_P J2-39 AO LCD10 MIPI lane 1 data (+) DSI1_LN2_N J2-27 AO LCD1 MIPI lane 2 data (-) DSI1_LN2_P J2-25 AO LCD1 MIPI lane 2 data (+) SA800U-WF_Hardware_Design 65 / 106 Smart Module Series SA800U-WF Hardware Design DSI1_LN3_N J2-31 AO LCD1 MIPI lane 3 data (-) DSI1_LN3_P J2-33 AO LCD1 MIPI lane 3 data (+) LCD_BL_A J4-4 PO LCD_BL_K1 LCD_BL_K2 J4-3 J4-2 LCD_BL_K3 J4-27 LCD_BL_K4 J4-26 AI AI AI AI Power output for LCD backlight Current sink 1 for LCD backlight Current sink 2 for LCD backlight Current sink 3 for LCD backlight Current sink 4 for LCD backlight VDISP_P J4-29 PO Display bias output (+) VDISP_M J4-30 PO Display bias output (-) PWM_PMI_GPIO5 J2-146 DO PWM output PWM_PMI_GPIO8 J2-144 DO PWM output 1.8 V power domain. The following are the reference designs for LCM interfaces. SA800U-WF_Hardware_Design 66 / 106 Smart Module Series SA800U-WF Hardware Design Figure 22: Reference Circuit Design for LCM0 Interface SA800U-WF_Hardware_Design 67 / 106 DSI0_CLK_PLEDANCLEDKLPTENC (SDA-TP) VIO18NC (VTP-TP) DSI0_LN3_PLCD_TELCD_RSTDSI0_LN3_NDSI0_LN2_PDSI0_CLK_NDSI0_LN2_NRESETLCD_IDNC (SCL-TP) NC (RST-TP) NC (EINT-TP) GNDVCC28GNDMIPI_TDP3MIPI_TDN3GNDMIPI_TDP2MIPI_TDN2GNDMIPI_TDP1MIPI_TDN1GNDLCD_BL_ALCD_BL_K11234567891012131415161718192021222324252627MIPI_TDP0MIPI_TDN0GNDMIPI_TCPMIPI_TCN2928303456345634563456DSI0_LN1_NDSI0_LN1_PDSI0_LN0_NDSI0_LN0_P1234561112121212100 nF4.7 F1FModuleLCMFL1FL2FL3FL4FL5EMI filterC3C2C1NCGNDGNDGNDGND31323334LCD_BL_K2ADC_PMU_GPIO8LDO14A_1V882.2 FLDO_ICVBATC5C4100KGPIO2.2 FR1 Smart Module Series SA800U-WF Hardware Design Figure 23: Reference Circuit Design for LCM1 Interface MIPI are high-speed signals. It is recommended that common-mode filters should be added in series near the LCM connector, so as to improve protection against electromagnetic radiation interference. ICMEF112P900MFR is recommended. When compatible design with other displays is required, connect the LCD_ID pin of LCM to the modules ADC pin, and please note that the output voltage of LCD_ID cannot exceed the voltage range of the ADC pin. SA800U-WF provides a backlight driving output which can be used to drive LCM backlight WLEDs directly. The features are listed below:

Use the high voltage output (LCD_BL_A) for powering WLED strings, and the OVP voltage output is 29.6 V. Support 4 current sink drivers

(LCD_BL_K1, LCD_BL_K2, LCD_BL_K3, LCD_BL_K4), with maximum sink current of up to 30 mA for each. 2 of them can be connected in parallel for powering 16 WLEDs and 4 of them for 32 WLEDs. SA800U-WF_Hardware_Design 68 / 106 DSI1_CLK_PLEDANCLEDKNC (SDA-TP)VIO18NC (VTP-TP)DSI1_LN3_PLCD1_RSTDSI1_LN3_NDSI1_LN2_PDSI1_CLK_NDSI1_LN2_NRESETLCD_IDNC (SCL-TP) NC (RST-TP) NC (EINT-TP) GNDVCC28GNDMIPI_TDP3MIPI_TDN3GNDMIPI_TDP2MIPI_TDN2GNDMIPI_TDP1MIPI_TDN1GNDLCM1_LED+1234567891012131415161718192021222324252627MIPI_TDP0MIPI_TDN0GNDMIPI_TCPMIPI_TCN2928303456345634563456DSI1_LN1_NDSI1_LN1_PDSI1_LN0_NDSI1_LN0_P12345611121212121FModuleLCMFL1FL2FL3FL4FL5EMI filterC3NCGNDGNDGNDGNDADC_PMU_GPIO2131323334LCM1_LED-1004.7 FC2C12.2 FLDO_ICVBATC5C4100KnFLDO14A_1V88GPIONC2.2 FR1 Smart Module Series SA800U-WF Hardware Design To adjust the backlight brightness, you can configure the sink current of the four current sink drivers via software. For LCM0, use the internal backlight driving circuit provided by SA800U-WF by default. For LCM1, you can use the internal circuit or an external backlight driving circuit according to your demand. The following is a reference design for LCM1 external backlight driving circuit where PWM_PMI_GPIO5 is used to adjust the backlight brightness. Figure 24: Reference Design of LCM1 External Backlight Driving Circuit 3.19. Touch Panel Interface SA800U-WF provides one I2C interface to connect with touch panel, and also provides the corresponding power supply and interrupt pins. The pin definition of touch panel interfaces is illustrated below. Table 22: Pin Definition of Touch Panel Interface Pin Name Pin No I/O Description Comment LDO28A_3V0 J4-10 PO 3.0 V output for VDD of TP LDO14A_1V88 J4-9 PO 1.8 V output for TP I2C pull-up circuit TP_INT TP_RST J2-48 DI TP interrupt J2-50 DO TP reset Vnom = 3.0 V IOmax = 150 mA Vnom = 1.8 V IOmax = 50 mA 1.8 V power domain. SA800U-WF_Hardware_Design 69 / 106 LCM1_LED+PWM_PMI_GPIO5Module2.2 FBacklight DriverLCM1_LED-VBATC1R110K Smart Module Series SA800U-WF Hardware Design TP_I2C_SCL J2-44 OD TP I2C clock TP_I2C_SDA J2-46 OD TP I2C data A reference design for touch panel interface is shown below. Figure 25: Reference Circuit Design for Touch Panel Interface 3.20. Camera Interfaces Based on standard MIPI CSI input interface, SA800U-WF supports 4 cameras (4-lane +

4-lane + 4-lane + 2-lane), with maximum pixels up to 32 MP. The 2-lane MIPI CSI can only receive data of RAW format. It can be used for ToF/3D camera modules and cannot be used for display. The video and photo quality are determined by various factors such as camera sensor, camera lens quality, etc. Table 23: Pin Definition of Camera Interfaces Pin Name Pin No. I/O Description LVS1A_1V8 J1-149 PO 1.8 V output for IOVDD of cameras CSI0_CLK_N J1-30 CSI0_CLK_P J1-28 CSI0_LN0_N J1-22 AI AI AI MIPI clock of camera 0 (-) MIPI clock of camera 0 (+) MIPI lane 0 data of camera 0 (-) Comment Vnom = 1.8 V IOmax = 300 mA 100 differential impedance. SA800U-WF_Hardware_Design 70 / 106 TP_RSTTP_I2C_SCLTP_I2C_SDATP_INT1234562.2K2.2K4.7 F100nFModuleRESET SCL SDA INT GNDVDD TPR2R1C1C2D1D2D3D4D5LDO28A_3V0LDO14A_1V88 Smart Module Series SA800U-WF Hardware Design CSI0_LN0_P J1-24 CSI0_LN1_N J1-16 CSI0_LN1_P J1-18 CSI0_LN2_N J1-10 CSI0_LN2_P J1-12 CSI0_LN3_N J1-6 CSI0_LN3_P J1-4 CSI1_CLK_N J1-58 CSI1_CLK_P J1-60 CSI1_LN0_N J1-52 CSI1_LN0_P J1-54 CSI1_LN1_N J1-46 CSI1_LN1_P J1-48 CSI1_LN2_N J1-42 CSI1_LN2_P J1-40 CSI1_LN3_N J1-34 CSI1_LN3_P J1-36 CSI2_CLK_N J1-63 CSI2_CLK_P J1-61 CSI2_LN0_N J1-67 CSI2_LN0_P J1-69 CSI2_LN1_N J1-66 CSI2_LN1_P J1-64 CSI2_LN2_N J1-72 CSI2_LN2_P J1-70 AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI AI MIPI lane 0 data of camera 0 (+) MIPI lane 1 data of camera 0 (-) MIPI lane 1 data of camera 0 (+) MIPI lane 2 data of camera 0 (-) MIPI lane 2 data of camera 0 (+) MIPI lane 3 data of camera 0 (-) MIPI lane 3 data of camera 0 (+) MIPI clock of camera 1 (-) MIPI clock of camera 1 (+) MIPI lane 0 data of camera 1 (-) MIPI lane 0 data of camera 1 (+) MIPI lane 1 data of camera 1 (-) MIPI lane 1 data of camera 1 (+) MIPI lane 2 data of camera 1 (-) MIPI lane 2 data of camera 1 (+) MIPI lane 3 data of camera 1 (-) MIPI lane 3 data of camera 1 (+) MIPI clock of camera 2 (-) MIPI clock of camera 2 (+) MIPI lane 0 data of camera 2 (-) MIPI lane 0 data of camera 2 (+) MIPI lane 1 data of camera 2 (-) MIPI lane 1 data of camera 2 (+) MIPI lane 2 data of camera 2 (-) MIPI lane 2 data of camera 2 (+) SA800U-WF_Hardware_Design 71 / 106 Smart Module Series SA800U-WF Hardware Design 100 differential impedance. CSI3 can only receive data of RAW format. It can be used for ToF/3D camera modules but cannot be used for display. CSI2_LN3_N J1-78 CSI2_LN3_P J1-76 CSI3_CLK_N J1-85 CSI3_CLK_P J1-87 CSI3_LN0_N J1-81 CSI3_LN0_P J1-79 CSI3_LN1_N J1-73 CSI3_LN1_P J1-75 AI AI AI AI AI AI AI AI MIPI lane 3 data of camera 2 (-) MIPI lane 3 data of camera 2 (+) MIPI clock of camera 3 (-) MIPI clock of camera 3 (+) MIPI lane 0 data of camera 3 (-) MIPI lane 0 data of camera 3 (+) MIPI lane 1 data of camera 3 (-) MIPI lane 1 data of camera 3 (+) CAM0_STROBE J1-122 DO Strobe of camera 0 CAM1_STROBE J1-116 DO Strobe of camera 1 CAM2_STROBE J1-118 DO Strobe of camera 2 CAM0_MCLK J1-91 DO Master clock of camera 0 CAM1_MCLK J1-95 DO Master clock of camera 1 CAM2_MCLK J1-99 DO Master clock of camera 2 CAM3_MCLK J1-103 DO Master clock of camera 3 CAM0_RST J1-100 DO Reset of camera 0 CAM1_RST J1-96 DO Reset of camera 1 1.8 V power domain. CAM2_RST J1-124 DO Reset of camera 2 CAM3_RST J1-126 DO Reset of camera 3 CAM0_PWDN J1-114 DO Power down of camera 0 CAM1_PWDN J1-120 DO Power down of camera 1 CAM2_PWDN J1-106 DO Power down of camera 2 CAM3_PWDN J1-112 DO Power down of camera 3 CAM0_AVDD_EN J1-102 DO AVDD enable of camera 0 CAM1_AVDD_EN J1-98 DO AVDD enable of camera 1 SA800U-WF_Hardware_Design 72 / 106 Smart Module Series SA800U-WF Hardware Design CAM2_AVDD_EN J1-104 DO AVDD enable of camera 2 CAM3_AVDD_EN J1-108 DO AVDD enable of camera 3 CAM0_DVDD_EN J1-132 DO DVDD enable of camera 0 CAM1_DVDD_EN J1-130 DO DVDD enable of camera 1 CAM2_DVDD_EN J1-110 DO DVDD enable of camera 2 CAM3_DVDD_EN J1-128 DO DVDD enable of camera 3 CCI0_I2C_SCL J1-142 OD CCI0 I2C clock CCI0_I2C_SDA J1-144 OD CCI0 I2C data CCI1_I2C_SDA J1-146 OD CCI1 I2C data CCI1_I2C_SCL J1-148 OD CC1 I2C clock The following is a reference circuit design for camera applications. Figure 26: Reference Circuit Design for CSI0 SA800U-WF_Hardware_Design 73 / 106 Rear camera connectorCAM0_PWDNCAM0_MCLKCCI0_I2C_SDACCI0_I2C_SCLCSI0_CLK_PCSI0_CLK_N2.2K2.2KCAM0_RSTEMIEMIEMIEMIEMIAVDDDVDDDOVDD1 FCSI0_LN0_PCSI0_LN0_NCSI0_LN1_PCSI0_LN1_NCSI0_LN2_PCSI0_LN2_NCSI0_LN3_PCSI0_LN3_NCAM0_AVDDCAM0_AF_VDDCAM0_DVDDLVS1A_1V8AFVDDMODULECAM0_STROBE1 F4.7 F4.7 FR1R2C1C2C3C4 Smart Module Series SA800U-WF Hardware Design Figure 27: Reference Circuit Design for Power of CSI0 NOTE CSI3 can only receive data of RAW format. It can be used for ToF/3D camera modules but cannot be used for display. SA800U-WF_Hardware_Design 74 / 106 CAM0_AF_VDDModule2.2 FLDO_ICVBATC1CAM0_AFVDD_ENR1100KC2 CAM0_DVDDModule2.2 FDCDC_ICVBATC5CAM0_DVDD_ENR3100KC6 CAM0_AVDDModule2.2 FLDO_ICVBATC3R2100KC4CAM0_AVDD_ENL12.2 F2.2 F2.2 F Smart Module Series SA800U-WF Hardware Design 3.20.1. Design Considerations Special attention should be paid to the pin definition of LCM/camera connectors. Ensure the SA800U-WF module and the connectors are correctly connected. MIPI are high-speed signals, supporting maximum data rate of up to 2.5 Gbps. The differential impedance should be controlled as 100 . Additionally, it is recommended to route the trace on the inner layer of PCB, and do not cross it with other traces. Any cut or hole on GND reference plane under MIPI signals should be avoided. For the same group of DSI or CSI signals, keep all the MIPI traces of the same length. Route the CAM_MCLK signals in the inner layer of the PCB and surround them with ground. Spacing for the lanes should comply with the following rules:

Intra-lane P to N: 1 trace width a) b) Lane to lane: 1.5 trace width c) Lanes to all other signals: 2.5 trace width Route MIPI traces according to the following rules:

a) Control the differential impedance to 100 10 %;

b) Control intra-lane length difference within 0.7 mm;

c) Control inter-lane length difference within 1.4 mm. Table 24: CSI Data Rate and PCB Maximum Trace Length (D-PHY) Data Rate 500 Mbps/lane 750 Mbps/lane 1.0 Gbps/lane 1.5 Gbps/lane 2.1 Gbps/lane Flex Cable Length

(inch) Cable Insertion Loss

(dB) Maximum PCB Trace Length (mm) 3 6 3 6 3 6 3 6 3 6

-0.5

-1

-0.7

-1.15

-0.75

-1.4

-0.9

-1.8

-1.3

-2.3

< 260

< 190

< 210

< 155

< 200

< 125

< 145

< 60

< 170

< 90 SA800U-WF_Hardware_Design 75 / 106 Smart Module Series SA800U-WF Hardware Design Table 25: DSI Data Rate and PCB Maximum Trace Length (D-PHY) Data Rate 500 Mbps/lane 750 Mbps/lane 1.0 Gbps/lane 1.5 Gbps/lane 2.1 Gbps/lane Flex Cable Length

(inch) Cable Insertion Loss

(dB) Maximum PCB Trace Length (mm) 3 6 3 6 3 6 3 6 3 6

-0.8

-1.4

-1

-1.5

-1.1

-1.7

-1.2

-2.2

-1.6

-2.8

< 280

< 210

< 210

< 150

< 200

< 100

< 135

< 40

< 110 0 NOTES 1. The flex cable length used in this table is an example with specified insertion loss. 2. The flex cable insertion loss can be measured using a vector signal analyzer or obtained from the flex cable datasheet. Cable insertion loss on the design should be no worse than what is listed above. 3. The maximum PCB trace length listed above includes the length routed inside the module. Table 26: MIPI Trace Length Inside the Module Pin No. Pin Name Length (mm) Length Difference (P - N) J2-26 J2-28 J2-38 J2-40 J2-32 J2-34 DSI0_CLK_N DSI0_CLK_P DSI0_LN0_N DSI0_LN0_P DSI0_LN1_N DSI0_LN1_P 13.12 13.27 13.41 12.89 13.21 12.78 0.15

-0.52

-0.43 SA800U-WF_Hardware_Design 76 / 106 Smart Module Series SA800U-WF Hardware Design J2-20 J2-22 J2-14 J2-16 J2-21 J2-19 J2-13 J2-15 J2-37 J2-39 J2-27 J2-25 J2-31 J2-33 J1-30 J1-28 J1-22 J1-24 J1-16 J1-18 J1-10 J1-12 J1-6 J1-4 DSI0_LN2_N DSI0_LN2_P DSI0_LN3_N DSI0_LN3_P DSI1_CLK_N DSI1_CLK_P DSI1_LN0_N DSI1_LN0_P DSI1_LN1_N DSI1_LN1_P DSI1_LN2_N DSI1_LN2_P DSI1_LN3_N DSI1_LN3_P CSI0_CLK_N CSI0_CLK_P CSI0_LN0_N CSI0_LN0_P CSI0_LN1_N CSI0_LN1_P CSI0_LN2_N CSI0_LN2_P CSI0_LN3_N CSI0_LN3_P J1-58 CSI1_CLK_N 13.35 12.81 13.67 13.10 24.35 23.95 22.42 22.71 23.35 24.02 22.45 22.99 23.73 23.27 23.90 23.54 24.31 24.19 23.33 22.99 24.53 24.95 23.61 23.35 15.49

-0.54

-0.57

-0.40 0.29 0.67 0.54

-0.46

-0.36

-0.12

-0.34 0.42

-0.26 0.16 SA800U-WF_Hardware_Design 77 / 106 Smart Module Series SA800U-WF Hardware Design J1-60 J1-52 J1-54 J1-46 J1-48 J1-42 J1-40 J1-34 J1-36 J1-63 J1-61 J1-67 J1-69 J1-66 J1-64 J1-72 J1-70 J1-78 J1-76 J1-85 J1-87 J1-81 J1-79 J1-73 J1-75 CSI1_CLK_P CSI1_LN0_N CSI1_LN0_P CSI1_LN1_N CSI1_LN1_P CSI1_LN2_N CSI1_LN2_P CSI1_LN3_N CSI1_LN3_P CSI2_CLK_N CSI2_CLK_P CSI2_LN0_N CSI2_LN0_P CSI2_LN1_N CSI2_LN1_P CSI2_LN2_N CSI2_LN2_P CSI2_LN3_N CSI2_LN3_P CSI3_CLK_N CSI3_CLK_P CSI3_LN0_N CSI3_LN0_P CSI3_LN1_N CSI3_LN1_P 15.65 14.99 14.71 14.93 14.81 14.74 15.28 15.61 15.31 16.36 16.72 15.84 16.09 15.71 16.11 14.90 15.39 15.98 16.47 10.27 10.35 9.57 9.68 11.20 10.55

-0.28

-0.12 0.54

-0.30 0.36 0.25 0.40 0.49 0.49 0.08 0.11

-0.65 SA800U-WF_Hardware_Design 78 / 106 Smart Module Series SA800U-WF Hardware Design 3.20.2. Flashlight Interfaces SA800U-WF supports 3 flash LED drivers with 2 1.5 A + 1 0.75 A, and supports both flash and torch modes. As for FLASH_LED1 and FLASH_LED2, in flash mode, the maximum output current is 0.75 A for each when the two LEDs work together and 1.5 A for each when they work separately. In torch mode, the maximum output current is 500 mA for each whether the two LEDs work together or separately. As for FLASH_LED3, in flash mode, the maximum output current is 0.75 A and in torch mode, the maximum output current is 500 mA. Table 27: Pin Definition of Flashlight Interfaces Pin Name Pin No. I/O Description Comment FLASH_LED1 J4-23, J4-24 AO Flash/torch driver output 1 ILED1 = 1.5 A FLASH_LED2 J4-20, J4-21 AO Flash/torch driver output 2 ILED2 = 1.5 A FLASH_LED3 J4-5, J4-6 AO Flash/torch driver output 3 ILED3 = 0.75 A A reference circuit design is shown below. Figure 28: Reference Circuit Design for Flashlight Interfaces SA800U-WF_Hardware_Design 79 / 106 ModuleD2FLASH_LED1D1FLASH_LED2D3FLASH_LED3 Smart Module Series SA800U-WF Hardware Design 3.21. Sensor Interfaces SA800U-WF has an integrated sensor subsystem called the Snapdragon sensor core, which is dedicated to support low-power, always-on use cases. Snapdragon sensor core supports communication with sensors via I2C interface and SPI interface, and it supports various sensors such as acceleration sensor, gyroscopic sensor, compass, optical sensor, temperature sensor. Snapdragon sensor core pins cannot be used for non-Snapdragon sensor core cases. They are dedicated for Snapdragon sensor core DSP. Table 28: Pin Definition of Sensor Interfaces Pin Name Pin No. I/O Description Comment SSC_SPI1_CS0 J1-136 DO Sensor core SPI1 chip select 0 SSC_SPI1_CS1 J1-138 DO Sensor core SPI1 chip select 1 SSC_SPI1_CS2 J1-140 DO Sensor core SPI1 chip select 2 SSC_SPI1_CLK J1-154 DO Sensor core SPI1 clock SSC_SPI1_MOSI J1-152 DO SSC_SPI1_MISO J1-150 DI Sensor core SPI1 master-out slave-in Sensor core SPI1 master-in salve-out SSC_SPI2_CS J1-141 DO Sensor core SPI2 chip select SSC_SPI2_CLK J1-145 DO Sensor core SPI2 clock SSC_SPI2_MOSI J1-143 DO SSC_SPI2_MISO J1-147 DI Sensor core SPI2 master-out slave-in Sensor core SPI2 master-in salve-out SSC_I2C1_SDA J2-8 OD Sensor core I2C1 data SSC_I2C1_SCL J2-10 OD Sensor core I2C1 clock MAG_INT J1-133 DI Magnetic sensor interrupt MAG_DRDY_INT J1-135 DI Magnetic sensor DRDY interrupt GYRO_INT J1-137 DI Gyroscopic sensor interrupt ACCEL_INT J1-139 DI Acceleration sensor interrupt 1.8 V power domain. SA800U-WF_Hardware_Design 80 / 106 Smart Module Series SA800U-WF Hardware Design 3.22. Audio Interfaces SA800U-WF provides one SPI interface which is dedicated for the control of WCD934x audio codec, one 2-lane SLIMbus interface dedicated for data transmission between SA800U-WF and WCD934x, three I2S interfaces which can support TDM function. The following table shows the pin definition. Table 29: Pin Definition of Audio Interfaces Pin Name Pin No. I/O Description Comment CODEC_RST J2-90 DO Codec reset CODEC_SPI_CLK J2-92 DO SPI clock for codec CODEC_SPI_MOSI J2-94 DO SPI master-out slave-in for codec CODEC_SPI_CS J2-96 DO SPI chip select for codec CODEC_SPI_MISO J2-89 DI SPI master-in salve-out for codec CODEC_INT1 J2-91 DI Codec interrupt 1 CODEC_INT2 J2-93 DI Codec interrupt 2 WCD_CLK J2-43 DO WCD clock SLIMBUS_CLK J2-51 DO SLIMbus clock 1.8 V power domain. SLIMBUS_DATA0 J2-47 DIO SLIMbus data bit 0 SLIMBUS_DATA1 J2-49 DIO SLIMbus data bit 1 I2S1_WS J2-79 DO I2S1 word select I2S1_MCLK J2-81 DO I2S1 master clock I2S1_SCK J2-83 DO I2S1 bit clock I2S1_DATA1 J2-85 DIO I2S1 data channel 1 I2S1_DATA0 J2-87 DIO I2S1 data channel 0 I2S2_WS J2-55 DO I2S2 word select SA800U-WF_Hardware_Design 81 / 106 Smart Module Series SA800U-WF Hardware Design I2S2_SCK J2-57 DO I2S2 bit clock I2S2_DATA0 J2-59 DIO I2S2 data channel 0 I2S2_DATA1 J2-61 DIO I2S2 data channel 1 I2S3_WS J2-63 DO I2S3 word select I2S3_DATA1 J2-65 DIO I2S3 data channel 1 I2S3_DATA2 J2-67 DIO I2S3 data channel 2 I2S3_DATA0 J2-69 DIO I2S3 data channel 0 I2S3_DATA3 J2-71 DIO I2S3 data channel 3 I2S3_SCK J2-73 DO I2S3 bit clock 3.23. Emergency Download Interface USB_BOOT is an emergency download interface. Pulling it up to VREG_S4A_1V8 during power-up will force the module into emergency download mode. This is an emergency option when there are failures such as abnormal startup or operation. For convenient firmware upgrade and debugging in the future, please reserve the reference circuit design shown as below. Figure 29: Reference Circuit Design for Emergency Download Interface SA800U-WF_Hardware_Design 82 / 106 VREG_S4A_1V8S1 ModuleUSB_BOOTR110K Smart Module Series SA800U-WF Hardware Design 4 Wi-Fi and BT SA800U-WF provides a shared antenna connector ANT-CH0 for Wi-Fi and Bluetooth functions, a Wi-Fi MIMO antenna connector ANT-CH1 for better Wi-Fi performance and a Bluetooth antenna connector BT*. The interface impedance is 50 . External antennas such as PCB antenna, sucker antenna and ceramic antenna can be connected to the module via these connectors, so as to achieve Wi-Fi and BT functions. NOTE

* means under development. 4.1. Wi-Fi Overview SA800U-WF supports 2.4 GHz and 5 GHz dual-band WLAN wireless communication based on IEEE 802.11a/b/g/n/ac standard protocols. The maximum data rate is up to 866 Mbps. The features are as below:

Support 2 2 MIMO Support Wake-on-WLAN (WoWLAN) Support ad hoc mode Support WAPI SMS4 hardware encryption Support AP mode Support Wi-Fi Direct Support MCS 07 for HT20 and HT40 Support MCS 08 for VHT20 Support MCS 09 for VHT40 and VHT80 SA800U-WF_Hardware_Design 83 / 106 Smart Module Series SA800U-WF Hardware Design 4.1.1. Wi-Fi Performance The following table lists the Wi-Fi transmitting and receiving performance of SA800U-WF module. 2.4 GHz Table 30: Wi-Fi Transmitting Performance Standard Rate Output Power 802.11b 802.11b 802.11g 802.11g 1 Mbps 11 Mbps 6 Mbps 54 Mbps 17 dBm 2.5 dB 17 dBm 2.5 dB 17 dBm 2.5 dB 14 dBm 2.5 dB 802.11n HT20 MCS0 16 dBm 2.5 dB 802.11n HT20 MCS7 13 dBm 2.5 dB 802.11n HT40 MCS0 16 dBm 2.5 dB 802.11n HT40 MCS7 13 dBm 2.5 dB 802.11a 802.11a 6 Mbps 54 Mbps 18.1 dBm 2.5 dB 15 dBm 2.5 dB 802.11n HT20 MCS0 17.5 dBm 2.5 dB 802.11n HT20 MCS7 14 dBm 2.5 dB 802.11n HT40 MCS0 17.5 dBm 2.5 dB 5 GHz 802.11n HT40 MCS7 14 dBm 2.5 dB 802.11ac VHT20 MCS0 17.5 dBm 2.5 dB 802.11ac VHT20 MCS8 14 dBm 2.5 dB 802.11ac VHT40 MCS0 17.5 dBm 2.5 dB 802.11ac VHT40 MCS9 14 dBm 2.5 dB 802.11ac VHT80 MCS0 17.5 dBm 2.5 dB SA800U-WF_Hardware_Design 84 / 106 Smart Module Series SA800U-WF Hardware Design 802.11ac VHT80 MCS9 13.5 dBm 2.5 dB 2.4 GHz Table 31: Wi-Fi Receiving Performance Standard Rate Sensitivity 802.11b 802.11b 802.11g 802.11g 802.11n HT20 802.11n HT20 802.11n HT40 802.11n HT40 802.11a 802.11a 1 Mbps

-96 dBm 11 Mbps

-87 dBm 6 Mbps

-90 dBm 54 Mbps

-74 dBm MCS0 MCS7 MCS0 MCS7 6 Mbps

-90 dBm

-72 dBm

-87 dBm

-70 dBm

-91 dBm 54 Mbps

-75 dBm 802.11n HT20 MCS0 802.11n HT20 MCS7 5 GHz 802.11n HT40 MCS0 802.11n HT40 MCS7 802.11ac VHT20 MCS8 802.11ac VHT40 MCS9 802.11ac VHT80 MCS9

-91 dBm

-72 dBm

-87 dBm

-70 dBm

-68 dBm

-64 dBm

-59 dBm Reference specifications: IEEE 802.11a/b/g/n/ac. SA800U-WF_Hardware_Design 85 / 106 Smart Module Series SA800U-WF Hardware Design 4.2. BT Overview SA800U-WF supports BT 5.0 (BR/EDR + BLE) specifications, as well as GFSK, 8-DPSK,

/4-DQPSK modulation modes. Maximally support up to 7 wireless connections Maximally support up to 3.5 piconets at the same time Support one SCO or eSCO (Extended Synchronous Connection Oriented) connection The BR/EDR channel bandwidth is 1 MHz, and can accommodate 79 channels. The BLE channel bandwidth is 2 MHz, and can accommodate 40 channels. Table 32: BT Data Rate and Versions Version Data rate Maximum Application Throughput 1.2 1 Mbit/s

> 80 kbit/s 2.0 + EDR 3 Mbit/s

> 80 kbit/s 3.0 + HS 24 Mbit/s Reference to 3.0 + HS 4.0 5.0 24 Mbit/s Reference to 4.0 LE 48 Mbit/s Reference to 5.0 LE Reference specifications are listed below:

Bluetooth Radio Frequency TSS and TP Specification 1.2/2.0/2.0 + EDR/2.1/2.1+

EDR/3.0/3.0 + HS, August 6, 2009 Bluetooth Low Energy RF PHY Test Specification, RF-PHY.TS/4.0.0, December 15, 2009 Bluetooth 5.0 RF-PHY Cover StandardRF-PHY.TS.5.0.0, December 06, 2016 SA800U-WF_Hardware_Design 86 / 106 Smart Module Series SA800U-WF Hardware Design 4.2.1. BT Performance The following table lists the BT transmitting and receiving performance of SA800U-WF module. Table 33: BT Transmitting and Receiving Performance Transmitter Performance Packet Types DH5 2-DH5 3-DH5 Transmitting Power 7.5 dBm 2.5 dB 7.5 dBm 2.5 dB 8 dBm 2.5 dB Receiver Performance Packet Types DH5 2-DH5 Receiving Sensitivity

-92 dBm

-93 dBm 3-DH5

-86 dBm SA800U-WF_Hardware_Design 87 / 106 Smart Module Series SA800U-WF Hardware Design 5 Antenna Connection 5.1. Antenna Connectors SA800U-WF is mounted with four antenna connectors: ANT-CH0 (Wi-Fi/BT antenna connector), ANT-CH1 (Wi-Fi MIMO antenna connector), BT* (BT antenna connector), and FM* (FM antenna connector) respectively. The impedance of the antenna connectors is 50 . FM BT ANT-CH0 Figure 30: Antenna Connectors ANT-CH1 Table 34: Definition of Antenna Connectors Antenna Connector Name I/O Description Comment ANT-CH0 ANT-CH1 AIO AIO Wi-Fi/BT antenna connector 50 impedance Wi-Fi MIMO antenna connector 50 impedance SA800U-WF_Hardware_Design 88 / 106 Smart Module Series SA800U-WF Hardware Design BT*

FM*

AIO BT antenna connector 50 impedance AI FM antenna connector 50 impedance Unit MHz MHz MHz Table 35: Operating Frequency Type 802.11a/b/g/n/ac BT 5.0 FM*

Frequency 24022482 51805825 24022480 76108 NOTE

* means under development. 5.2. Antenna Installation 5.2.1. Antenna Requirements The following table shows the requirements for Wi-Fi/BT/FM antennas. Table 36: Antenna Requirements Antenna Type Requirements Wi-Fi/BT/FM VSWR: 2 Gain: 1 dBi Max Input Power: 50 W Input Impedance: 50 Polarization Type: Vertical Cable Insertion Loss: <1 dB SA800U-WF_Hardware_Design 89 / 106 Smart Module Series SA800U-WF Hardware Design 5.2.2. Recommended Mating Plug for Antenna Connection SA800U-WF is mounted with RF connectors (receptacles) for convenient antenna connection. The connector being used is 818000500 from ECT and its dimensions are shown as below. Figure 31: Dimensions of the ECT 818000500 Connector (Unit: mm) SA800U-WF_Hardware_Design 90 / 106 Smart Module Series SA800U-WF Hardware Design The mating plug listed in the following figure can be used to match the receptacles. Figure 32: Mechanicals of the Mating Plug (Unit: mm) SA800U-WF_Hardware_Design 91 / 106 Smart Module Series SA800U-WF Hardware Design 6 Reliability, Radio and Electrical Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 37: Absolute Maximum Ratings Parameter VBAT USB_VBUS Voltage on Digital Pins Min.

-0.3

-0.3

-0.5 Max. Unit 6 28 2.3 V V V 6.2. Power Supply Ratings Table 38: SA800U-WF Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT VBAT The actual input voltages must the fall between minimum and maximum values 3.55 3.8 4.4 V Voltage drop during power-on Maximum power control level during power-on IVBAT Peak supply current

(during power-on) Maximum power control level during power-on

400 mV 3.0 5.0 A SA800U-WF_Hardware_Design 92 / 106 Smart Module Series SA800U-WF Hardware Design Charging power input. Power output for OTG device. USB/charger detection. insertion Power supply voltage of backup battery

USB_VBUS VRTC 4.0 5.0 14 V 2.5 3.2 3.2 V 6.3. Operating and Storage Temperatures The operating and storage temperatures are listed in the following table. Table 39: Operating and Storage Temperatures Parameter Min. Operating temperature range 1) -35 Storage temperature range

-40 Typ.

+25

Max. Unit

+75

+90 C C NOTE 1) Within the operating temperature range, the module is IEEE compliant. 6.4. Current Consumption The current consumption of different conditions is listed in the following table. Table 40: SA800U-WF Current Consumption (2 2 MIMO) Description Conditions OFF Power down Airplane Mode RF sleep Wi-Fi 802.11a Tx

@ 6 Mbps Typ. 80 5.5 210 Unit A mA mA SA800U-WF_Hardware_Design 93 / 106 Smart Module Series SA800U-WF Hardware Design Wi-Fi 802.11b Tx Wi-Fi 802.11g Tx Wi-Fi 802.11n Tx Wi-Fi 802.11ac Tx

@ 54 Mbps

@ 1 Mbps

@ 11 Mbps

@ 6 Mbps

@ 54 Mbps

@ 14.4 Mbps, 20 MHz

@ 144.4 Mbps, 20 MHz

@ 30 Mbps, 40 MHz

@ 300 Mbps, 40 MHz

@ 14.4 Mbps, 20 MHz

@ 173.2 Mbps, 20 MHz

@ 30 Mbps, 40 MHz

@ 400 Mbps, 40 MHz

@ 65 Mbps, 80 MHz

@ 866.6 Mbps, 80 MHz Wi-Fi 802.11a Rx

@ 54 Mbps Wi-Fi 802.11b Rx

@ 11 Mbps Wi-Fi 802.11g Rx

@ 54 Mbps Wi-Fi 802.11n Rx

@ 300 Mbps, 40 MHz Wi-Fi 802.11ac Rx

@ 866.6 Mbps, 80 MHz BT Tx Channel 0 BT Tx Channel 38 BT Tx Channel 78 BT Rx Channel 38

190 305 175 170 150 750 625 770 615 760 655 740 610 685 565 160 175 155 615 550 110 112 113 109 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA SA800U-WF_Hardware_Design 94 / 106 Smart Module Series SA800U-WF Hardware Design 6.5. Electrostatic Discharge The module is not protected against electrostatic discharge (ESD) in general. Consequently, it should be subject to ESD handling precautions that are typically applied to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. The following table shows the electrostatic discharge characteristics of SA800U-WF module. Table 41: ESD Characteristics (Temperature: 25 C, Humidity: 45 %) Test Points Contact Discharge Air Discharge Unit VBAT, GND

+/-8 FM Antenna Interface

+/-4 BT Antenna Interface

+/-3 Other Antenna Interfaces +/-4 Other Interfaces

+/-0.5

+/-12

+/-8

+/-6

+/-8

+/-1 kV kV kV kV kV 6.6. Thermal Dissipation To achieve a maximum performance while working under extended temperatures or extreme conditions (such as with maximum power) for a long time, it is strongly recommended to apply thermal conductive gap fillers to the gaps between the shielding cover and heat-generating components in the module for better thermal dissipation. There are other measures to enhance thermal dissipation:

Place the module away from other heat sources. Select a suitable mechanical enclosure for the terminal product integrating the SA800U-WF module, and apply special treatment to the surface of the enclosure to enhance its heat radiation capability. Forced convection cooling scheme is highly recommended for the module to decrease the temperature rise, such as attaching an active heat sink with adequate cooling capacity to the top of the shielding cover. SA800U-WF_Hardware_Design 95 / 106 Smart Module Series SA800U-WF Hardware Design The following figure shows the thermal dissipation area:

Figure 33: Thermal Dissipation NOTE If a conformal coating is necessary for the module, do NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module. SA800U-WF_Hardware_Design 96 / 106 Smart Module Series SA800U-WF Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimension tolerances are 0.05 mm unless otherwise specified. 7.1. Mechanical Dimensions of the Module Figure 34: Module Top and Side Dimensions SA800U-WF_Hardware_Design 97 / 106 Smart Module Series SA800U-WF Hardware Design Figure 35: Module Bottom Dimensions (Bottom View) SA800U-WF_Hardware_Design 98 / 106 Smart Module Series SA800U-WF Hardware Design 7.2. Recommended Footprint Figure 36: Recommended Footprint (Top View) NOTES 1. For easy maintenance of the module, keep about 5 mm between the module and other components on the host PCB. 2. All RESERVED pins should be kept open and MUST NOT be connected to ground. 3. The 168-pin connector FX10A-168S-SV(21) of HIROSE should be used for connection with the module. SA800U-WF_Hardware_Design 99 / 106 Smart Module Series SA800U-WF Hardware Design 7.3. Top and Bottom View of the Module Figure 37: Top View of SA800U-WF Module Figure 38: Bottom View of SA800U-WF Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. SA800U-WF_Hardware_Design 100 / 106 Smart Module Series SA800U-WF Hardware Design 8 Storage and Packaging 8.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 5 C and the relative humidity should be 3560 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition. 3. The floor life of the module is 168 hours 1) in a plant where the temperature is 23 5 C and relative humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be installed within 168 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g. a drying cabinet). NOTE 1) This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. SA800U-WF_Hardware_Design 101 / 106 Smart Module Series SA800U-WF Hardware Design 8.2. Packaging SA800U-WF is packaged in tray carriers. Each tray is 350 mm 245 mm 15.8 mm and contains 18 modules. The following figures show the package details, measured in mm. Figure 39: Tray Dimensions SA800U-WF_Hardware_Design 102 / 106 Smart Module Series SA800U-WF Hardware Design 10 trays are overlaid in one vacuum-sealed package. The package details are shown below. Figure 40: Package Details Table 42: Tray Package Model Name MOQ for MP Minimum Package: 180 pcs SA800U-WF 180 pcs N.W.: 4.67 kg G.W.: 5.07 kg SA800U-WF_Hardware_Design 103 / 106 Smart Module Series SA800U-WF Hardware Design 9 Appendix References Table 43: Related Documents SN Document Name Description

[1]

Quectel_SA800U-WF_EVB_User_Guide EVB User Guide for SA800U-WF

[2]

Quectel_SA800U-WF_Pin_Description_and_GPIO_ Configuration Pin Description and GPIO Configuration of SA800U-WF

[3]

Quectel_SA800U-WF_Reference_Design Reference Design for SA800U-WF Table 44: Terms and Abbreviations Abbreviation Description 3D ADC AP B2B BOB bps BT CS CSI CTS DP DRDY 3-Dimensional Analog-to-Digital Converter Access Point Board-to-Board Buck or Boost Bits per Second Bluetooth Coding Scheme Camera Serial Interface Clear to Send DisplayPort Data Ready SA800U-WF_Hardware_Design 104 / 106 Smart Module Series SA800U-WF Hardware Design Display Stream Compression Display Serial Interface Digital Signal Processor Data Terminal Equipment (typically computer, external controller) Data Terminal Ready Eccentric Rotating Mass Electrostatic Discharge Equivalent Series Resistance Enhanced Variable Rate Codec Enhanced Voice Services Frequency Modulation General Purpose Input/Output Graphics Processing Unit DSC DSI DSP DTE DTR ERM ESD ESR EVRC EVS FM GPIO GPU HK ADC Housekeeping ADC HT I2C I2S IEEE Imax I/O ISP LCD LCM LE LED High Throughput Inter-Integrated Circuit Inter-IC Sound Institute of Electrical and Electronics Engineers Maximum Load Current Input/Output Image Signal Processor Liquid Crystal Display LCD Module Low Energy Light Emitting Diode SA800U-WF_Hardware_Design 105 / 106 Smart Module Series SA800U-WF Hardware Design LPDDR Low-Power Double Data Rate LPG LRA MCS MIMO MIPI MLCC NTC OTG OVP PCB PCIe PHY PMU PWM QC QCELP QUXGA RF RFFE RoHS RTC RTS RX SD Light Pulse Generator Linear Resonant Actuator Modulation and Coding Scheme Multiple Input Multiple Output Mobile Industry Processor Interface Multi-layer Ceramic Capacitor Negative Temperature Coefficient On-The-Go Over Voltage Protection Printed Circuit Board Peripheral Component Interconnect Express Physical Layer Power Management Unit Pulse Width Modulation Quick Charge Qualcomm Code-Excited Linear Prediction Quad Ultra Extended Graphics Array Radio Frequency RF Front End Restriction of Hazardous Substances Real Time Clock Request to Send Receive Secure Digital SA800U-WF_Hardware_Design 106 / 106 Smart Module Series SA800U-WF Hardware Design SDIO SLIMbus SMPS SPI SSC TDM ToF TP TX UART UFS USB VESA VHT Vmax Vnom Vmin VI VIHmax VIHmin VILmax VILmin VImax VImin VO Secure Digital Input Output Serial Low-power Inter-chip Media Bus Switched-Mode Power Supply Serial Peripheral Interface Snapdragon Sensor Core Time-Division Multiplexing Time-of-Flight Touch Panel Transmitting Direction Universal Asynchronous Receiver & Transmitter Universal Flash Storage Universal Serial Bus Video Electronics Standards Association Very High Throughput Maximum Voltage Value Nominal Voltage Value Minimum Voltage Value Voltage Input Maximum Input High Level Voltage Value Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Minimum Input Low Level Voltage Value Absolute Maximum Input Voltage Value Absolute Minimum Input Voltage Value Voltage Output SA800U-WF_Hardware_Design 107 / 106 Smart Module Series SA800U-WF Hardware Design VOHmax VOHmin VOLmax VOLmin WAPI WLAN WLED XO Maximum Output High Level Voltage Value Minimum Output High Level Voltage Value Maximum Output Low Level Voltage Value Minimum Output Low Level Voltage Value WLAN Authentication and Privacy Infrastructure Wireless Local Area Network White LED Crystal Oscillator The device could be used with a separation distance of 20cm to the human body. Product Marketing NameQuectel SA800U-WF FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met:

1. This Modular Approval is limited to OEM installation for mobile and fixed applications only. The antenna installation and operating configurations of this transmitter, including any applicable source-based timeaveraging duty factor, antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements of 2.1091. 2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the users body and must not transmit simultaneously with any other antenna or transmitter. 3. A label with the following statements must be attached to the host end product: This device contains FCC ID: XMR2022SA800UWF 4. This module must not transmit simultaneously with any other antenna or transmitter 5. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093 If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations. For this device, OEM integrators must be provided with labeling instructions of finished products. Please refer to KDB784748 D01 v07, section 8. Page 6/7 last two paragraphs:

A certified modular has the option to use a permanently affixed label, or an electronic label. For a permanently affixed label, the module must be labeled with an FCC ID - Section 2.926 (see 2.2 Certification (labeling requirements) above). The OEM manual must provide clear instructions explaining SA800U-WF_Hardware_Design 108 / 106 Smart Module Series SA800U-WF Hardware Design to the OEM the labeling requirements, options and OEM user manual instructions that are required (see next paragraph). For a host using a certified modular with a standard fixed label, if (1) the modules FCC ID is not visible when installed in the host, or (2) if the host is marketed so that end users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible;

then an additional permanent label referring to the enclosed module: Contains Transmitter Module FCC ID: XMR2022SA800UWF or Contains FCC ID: XMR2022SA800UWF must be used. The host OEM user manual must also contain clear instructions on how end users can find and/or access the module and the FCC ID. The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The users manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. In cases where the manual is provided only in a form other than paper, such as on a computer disk or over the Internet, the information required by this section may be included in the manual in that alternative form, provided the user can reasonably be expected to have the capability to access information in that form. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the manufacturer could void the users authority to operate the equipment. To ensure compliance with all non-transmitter functions the host manufacturer is responsible for ensuring compliance with the module(s) installed and fully operational. For example, if a host was previously authorized as an unintentional radiator under the Suppliers Declaration of Conformity procedure without a transmitter certified module and a module is added, the host manufacturer is responsible for ensuring that the after the module is installed and operational the host continues to be compliant with the Part 15B unintentional radiator requirements. Manual Information To the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. IC Statement IRSS-GEN

"This device complies with Industry Canadas licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device." The transmitter module may not be co-located with any other transmitter or antenna.or "Le prsent appareil est conforme aux CNR dIndustrie Canada applicables aux appareils radio exempts de licence. Lexploitation est autorise aux deux conditions suivantes :

1) lappareil ne doit pas produire de brouillage; 2) lutilisateur de lappareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible den compromettre le fonctionnement."

Dclaration sur l'exposition aux rayonnements RF L'autre utilis pour l'metteur doit tre install pour fournir une distance de sparation d'au moins 20 cm SA800U-WF_Hardware_Design 109 / 106 Smart Module Series SA800U-WF Hardware Design de toutes les personnes et ne doit pas tre colocalis ou fonctionner conjointement avec une autre antenne ou un autre metteur. The host product shall be properly labeled to identify the modules within the host product. The Innovation, Science and Economic Development Canada certification label of a module shall be clearly visible at all times when installed in the host product; otherwise, the host product must be labeled to display the Innovation, Science and Economic Development Canada certification number for the module, preceded by the word Contains or similar wording expressing the same meaning, as follows:

Contains IC: 10224A-22SA800UWF or where: 10224A-22SA800UWF is the modules certification number. Le produit hte doit tre correctement tiquet pour identifier les modules dans le produit hte. L'tiquette de certification d'Innovation, Sciences et Dveloppement conomique Canada d'un module doit tre clairement visible en tout temps lorsqu'il est installdans le produit hte; sinon, le produit hte doit porter une tiquette indiquant le numro de certification d'Innovation, Sciences et Dveloppement conomique Canada pour le module, prc d du mot Contient ou d'un libell semblable exprimant la mme signification, comme suit:

"Contient IC: 10224A-22SA800UWF " ou "o: 10224A-22SA800UWF est le numro de certification du module". i. the device for operation in the band 51505250 MHz is only for indoor use to reduce the potential for harmful interference to co-channel mobile satellite systems;

ii. for devices with detachable antenna(s), the maximum antenna gain permitted for devices in the bands 5250-5350 MHz and 5470-5725 MHz shall be such that the equipment still complies with the e.i.r.p. limit;

iii. for devices with detachable antenna(s), the maximum antenna gain permitted for devices in the band 5725-5850 MHz shall be such that the equipment still complies with the e.i.r.p. limits as appropriate;

iv. Omnidirectional antenna is recommended SA800U-WF_Hardware_Design 110 / 106

Quectel Wireless Solutions Co., Ltd. Statement We Quectel Wireless Solutions Co., Ltd. the following statement on BT antenna port fastening. The BT has two antenna ports, ANT0-CH0 for BT TX port, and the other BT antenna port cannot be used alone. Sincerely, Name: Jean Hu Date2022/9/26 Telephone Number: +86-21-51086236-6511 Extension: 800 Fax Number: +86-21-54453668 Email: jean hu@quectel.com