FCC ID: XMR202103FG50V Wi-Fi & BT Module

FG50V Hardware Design Wi-Fi&BT Module Series Version: 1.0 Date: 2020-12-08 Status: Released www.quectel.com Wi-Fi&BT Module Series FG50V Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters:

Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit:

http://www.quectel.com/support/sales.htm. For technical support, or to report documentation errors, please visit:

http://www.quectel.com/support/technical.htm Or email to support@quectel.com. General Notes Quectel offers the information as a service to its customers. The information provided is based upon customers requirements. Quectel makes every effort to ensure the quality of the information it makes available. Quectel does not make any warranty as to the information contained herein, and does not accept any liability for any injury, loss or damage of any kind incurred by use of or reliance upon the information. All information supplied herein is subject to change without prior notice. Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors, it is possible that these functions and features could contain errors, inaccuracies and omissions. Unless otherwise provided by valid agreement, Quectel makes no warranties of any kind, implied or express, with respect to the use of features and functions under development. To the maximum extent permitted by law, Quectel excludes all liability for any loss or damage suffered in connection with the use of the functions and features under development, regardless of whether such loss or damage may have been foreseeable. Duty of Confidentiality The Receiving Party shall keep confidential all documentation and information provided by Quectel, except when the specific permission has been granted by Quectel. The Receiving Party shall not access or use Quectels documentation and information for any purpose except as expressly provided herein. Furthermore, the Receiving Party shall not disclose any of the Quectel's documentation and information to any third party without the prior written consent by Quectel. For any noncompliance to the above requirements, unauthorized use, or other illegal or malicious use of the documentation and information, Quectel will reserve the right to take legal action. Copyright FG50V_Hardware_Design 1 / 54 Wi-Fi&BT Module Series FG50V Hardware Design The information contained here is proprietary technical information of Quectel. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design. Copyright Quectel Wireless Solutions Co., Ltd. 2020. All rights reserved. FG50V_Hardware_Design 2 / 54 Wi-Fi&BT Module Series FG50V Hardware Design About the Document Revision History

1.0 Version Date Author Description 2019-11-25 2020-12-08 Jared WANG/

Felix FU Hidy CHAI/

Lucas HUANG Creation of the document First official release FG50V_Hardware_Design 3 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Contents About the Document ...................................................................................................................................... 3 Contents ........................................................................................................................................................ 4 Table Index ..................................................................................................................................................... 6 Figure Index ................................................................................................................................................... 7 1 2 Introduction ............................................................................................................................................ 8 Safety Information ................................................................................................................................. 10 1.1. Product Concept .................................................................................................................................... 12 2.1. General Description ............................................................................................................................... 12 Key Features ........................................................................................................................................... 12 2.2. Functional Diagram ................................................................................................................................ 14 2.3. Evaluation Board .................................................................................................................................... 14 2.4. 3.6. 3.6.1. 3.6.2. 3.6.3. 3.6.4. 3 Application Interfaces ............................................................................................................................ 15 3.1. General Description ............................................................................................................................... 15 Pin Assignment ...................................................................................................................................... 16 3.2. Pin Description ....................................................................................................................................... 17 3.3. 3.4. Power Supply ......................................................................................................................................... 21 3.5. WLAN Interface ...................................................................................................................................... 23 3.5.1. WLAN_EN ................................................................................................................................... 24 PCIe Interface ............................................................................................................................. 24 3.5.2. BT Interface ............................................................................................................................................ 25 BT_EN ......................................................................................................................................... 26 BT_WAKEUP_HOST* and HOST_WAKEUP_BT* ......................................................................... 26 PCM Interface* .......................................................................................................................... 27 UART Interface ........................................................................................................................... 28 3.7. Conexistence Interface .......................................................................................................................... 29 3.8. WLAN_SLP_CLK Interface ...................................................................................................................... 30 3.9. Others Interfaces ................................................................................................................................... 30 3.9.1. SW_CTRL* .................................................................................................................................. 30 3.9.2. WLAN Debug Interface .............................................................................................................. 31 BT Debug Interface ..................................................................................................................... 31 3.9.3. RF Antenna Interfaces ........................................................................................................................ 31 3.10.1. Operating Frequency ................................................................................................................. 32 3.10.2. Reference Design of RF Antenna Interfaces ............................................................................... 32 3.10.3. Reference Design of RF Layout ................................................................................................... 33 3.10.4. Antenna Requirements .............................................................................................................. 35 3.10.5. Recommended RF Connector for Antenna Installation ............................................................. 35 3.10. 4 Reliability, Radio and Electrical Characteristics ........................................................................................ 38 4.1. General Description ............................................................................................................................... 38 FG50V_Hardware_Design 4 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Electrical Characteristics ........................................................................................................................ 38 4.2. 4.3. I/O Interface Characteristics .................................................................................................................. 39 4.4. Operating and Storage Temperatures .................................................................................................... 40 Current Consumption ............................................................................................................................ 40 4.5. Current Consumption in Low Power Modes .............................................................................. 40 Current Consumption in Normal Operation .............................................................................. 41 RF Performances .................................................................................................................................... 42 Conducted RF Output Power ..................................................................................................... 42 Conducted RF Receiving Sensitivity ........................................................................................... 44 Electrostatic Discharge ........................................................................................................................... 45 4.5.1. 4.5.2. 4.6.1. 4.6.2. 4.6. 4.7. 5 Mechanical Dimensions .......................................................................................................................... 47 5.1. Mechanical Dimensions of the Module ................................................................................................. 47 Recommended Footprint ....................................................................................................................... 49 5.2. Top and Bottom Views of the Module ................................................................................................... 50 5.3. 6 Storage, Manufacturing and Packaging ................................................................................................... 51 Storage ................................................................................................................................................... 51 6.1. 6.2. Manufacturing and Soldering ................................................................................................................ 52 Packaging ............................................................................................................................................... 53 6.3. 7 Appendix References .............................................................................................................................. 54 FG50V_Hardware_Design 5 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Table Index Table 1: Key Features ................................................................................................................................................. 12 Table 2: I/O Parameters Definition ............................................................................................................................ 17 Table 3: Pin Description ............................................................................................................................................. 17 Table 4: Definition of Power Supply and GND Pins .................................................................................................... 22 Table 5: Pin Definition of WLAN_EN .......................................................................................................................... 24 Table 6: Pin Definition of PCIe Interface .................................................................................................................... 24 Table 7: Pin Definition of BT_EN ................................................................................................................................ 26 Table 8: Pin Definition of BT_WAKEUP_HOST and HOST_WAKEUP_BT ..................................................................... 27 Table 9: Pin Definition of Coexistence Interface ........................................................................................................ 29 Table 10: Pin Definition of WLAN_SLP_CLK Interface ................................................................................................ 30 Table 11: Pin Definition of SW_CTRL ......................................................................................................................... 30 Table 12: Pin Definition of WLAN Debug Interface .................................................................................................... 31 Table 13: Pin Definition of BT Debug interface .......................................................................................................... 31 Table 14: Pin Definition of RF Antenna Interfaces ..................................................................................................... 32 Table 15: Operating Frequency of the Module .......................................................................................................... 32 Table 16: Antenna Requirements .............................................................................................................................. 35 Table 17: Absolute Maximum Ratings ....................................................................................................................... 38 Table 18: Recommended Operating Conditions ........................................................................................................ 39 Table 19: General DC Electrical Characteristics.......................................................................................................... 39 Table 20: Operating and storage Temperatures ......................................................................................................... 40 Table 21: Current Consumption of the Module (Low Power Modes, Unit: mm) ....................................................... 40 Table 22: Current Consumption of the Module (Normal Operation, Unit: mA) ........................................................ 41 Table 23: Conducted RF Output Power at 2.4 GHz .................................................................................................... 42 Table 24: Conducted RF Output Power at 5 GHz ....................................................................................................... 43 Table 25: Conducted RF Receiving Sensitivity at 2.4 GHz .......................................................................................... 44 Table 26: Conducted RF Receiving Sensitivity at 5 GHz ............................................................................................. 45 Table 27: Electrostatic Discharge Characteristics ....................................................................................................... 46 Table 28: Recommended Thermal Profile Parameters .............................................................................................. 52 Table 29: Related Documents .................................................................................................................................... 54 Table 30: Terms and Abbreviations ............................................................................................................................ 54 FG50V_Hardware_Design 6 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Figure Index Figure 1: Functional Diagram of FG50V Module........................................................................................................ 14 Figure 2: Pin Assignment (Top View) ......................................................................................................................... 16 Figure 3: Reference Circuit of power supply from SDX55 platform ........................................................................... 22 Figure 4: WLAN Interface Connection ....................................................................................................................... 23 Figure 5: PCIe Interface Connection .......................................................................................................................... 25 Figure 6: Block Diagram of BT Interface Connection ................................................................................................. 26 Figure 7: PCM Interface Connection .......................................................................................................................... 28 Figure 8: Coexistence Interface Connection .............................................................................................................. 29 Figure 9: SW_CTRL Connection ................................................................................................................................. 30 Figure 10: Reference Circuit for RF Antenna Interfaces ............................................................................................. 33 Figure 11: Microstrip Design on a 2-layer PCB........................................................................................................... 33 Figure 12: Coplanar Waveguide Design on a 2-layer PCB .......................................................................................... 34 Figure 13: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) ........................................ 34 Figure 14: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) ........................................ 34 Figure 15: Dimensions of the U.FL-R-SMT Connector (Unit: mm) ............................................................................. 36 Figure 16: Mechanicals of UF.L-LP Connectors (Unit: mm) ........................................................................................ 36 Figure 17: Space Factor of Mated Connector (Unit: mm) .......................................................................................... 37 Figure 18: FG50V Top and Side Dimensions (Top and Side View) ............................................................................. 47 Figure 19: FG50V Bottom Dimension (Bottom View) ................................................................................................ 48 Figure 20: Recommended Footprint (Top View) ....................................................................................................... 49 Figure 21: Top View of the Module ........................................................................................................................... 50 Figure 22: Bottom View of the Module ..................................................................................................................... 50 Figure 23: Recommended Reflow Soldering Thermal Profile .................................................................................... 52 FG50V_Hardware_Design 7 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 1 Introduction This document defines the FG50V module and describes its air interfaces and hardware interfaces which are connected with your application. This document can help you quickly understand module interface specifications, electrical and mechanical details, as well as other related information of the module. Associated with application notes and user guides, you can use FG50V module to design and set up applications easily. Hereby, [Quectel Wireless Solutions Co., Ltd.] declares that the radio equipment type [FG50V] is in compliance with Directive 2014/53/EU. The full text of the EU declaration of conformity is available at the following internet address:

http://www.quectel.com. The device could be used with a separation distance of 20cm to the human body. FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met:

1. This Modular Approval is limited to OEM installation for mobile and fixed applications only. The antenna installation and operating configurations of this transmitter, including any applicable source-based timeaveraging duty factor, antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements of 2.1091. 2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the users body and must not transmit simultaneously with any other antenna or transmitter. 3. A label with the following statements must be attached to the host end product: This device contains FCC ID:

XMR202103FG50V 4. To comply with FCC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed:

WIFI 2.4G/5G : 5.38 dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093 If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations. For this device, OEM integrators must be provided with labeling instructions of finished products. Please refer to KDB784748 D01 v07, section 8. Page 6/7 last two paragraphs:

FG50V_Hardware_Design 8 / 54 Wi-Fi&BT Module Series FG50V Hardware Design A certified modular has the option to use a permanently affixed label, or an electronic label. For a permanently affixed label, the module must be labeled with an FCC ID - Section 2.926 (see 2.2 Certification (labeling requirements) above). The OEM manual must provide clear instructions explaining to the OEM the labeling requirements, options and OEM user manual instructions that are required (see next paragraph). For a host using a certified modular with a standard fixed label, if (1) the modules FCC ID is not visible when installed in the host, or (2) if the host is marketed so that end users do not have straightforward commonly used methods for access to remove the module so that the FCC ID of the module is visible; then an additional permanent label referring to the enclosed module: Contains Transmitter Module FCC ID: XMR202103FG50V or Contains FCC ID: XMR202103FG50V must be used. The host OEM user manual must also contain clear instructions on how end users can find and/or access the module and the FCC ID. The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The users manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. In cases where the manual is provided only in a form other than paper, such as on a computer disk or over the Internet, the information required by this section may be included in the manual in that alternative form, provided the user can reasonably be expected to have the capability to access information in that form. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the manufacturer could void the users authority to operate the equipment. To ensure compliance with all non-transmitter functions the host manufacturer is responsible for ensuring compliance with the module(s) installed and fully operational. For example, if a host was previously authorized as an unintentional radiator under the Suppliers Declaration of Conformity procedure without a transmitter certified module and a module is added, the host manufacturer is responsible for ensuring that the after the module is installed and operational the host continues to be compliant with the Part 15B unintentional radiator requirements. Manual Information To the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the users manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. Wireless Access Systems including Radio Local Area Networks (WAS/RLANs) frequency range 5150 5350 MHz is Restricted to indoor use in EU, this device contains 5150-5250 MHz. FG50V_Hardware_Design 9 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating FG50V module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers failure to comply with these precautions. Full attention must be given to driving at all times in order to reduce the risk of an accident. Using a mobile while driving (even with a handsfree kit) causes distraction and can lead to an accident. Please comply with laws and regulations restricting the use of wireless devices while driving. Switch off the cellular terminal or mobile before boarding an aircraft. The operation of wireless appliances interference with communication systems. If there is an Airplane Mode, it should be enabled prior to boarding an aircraft. Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft. forbidden to prevent in an aircraft is Wireless devices may cause interference on sensitive medical equipment, so please be aware of the restrictions on the use of wireless devices when in hospitals, clinics or other healthcare facilities. Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions, such as when the mobile bill is unpaid or the

(U)SIM card is invalid. When emergency help is needed in such conditions, use emergency call if the device supports it. In order to make or receive a call, the cellular terminal or mobile must be switched on in a service area with adequate cellular signal strength. In an emergency, the device with emergency call function cannot be used as the only contact method considering network connection cannot be guaranteed under all circumstances. The cellular terminal or mobile contains a transceiver. When it is ON, it receives and transmits radio frequency signals. RF interference can occur if it is used close to TV sets, radios, computers or other electric equipment. FG50V_Hardware_Design 10 / 54 Wi-Fi&BT Module Series FG50V Hardware Design In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or metal powders. FG50V_Hardware_Design 11 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 2 Product Concept 2.1. General Description FG50V is a Wi-Fi and Bluetooth (BT) module with low power consumption. It is a single-die WLAN (Wireless Local Area Network) and BT combo solution supporting IEEE 802.11a/b/g/n/ac/ax 2.4/5 GHz WLAN standards and BT 5.1* standard, which enables seamless integration of WLAN and BT low energy technologies. With a low-power PCIe Gen 2 interface for WLAN, a UART and PCM* interface for BT, and an LTE/5G & WLAN/BT coexistence interface, FG50V can provide WLAN and BT functions. 2.2. Key Features The following table describes the key features of FG50V module. Table 1: Key Features Features Details Power Supply Operating Frequency Core supply voltage: 0.95 V, 1.35 V, 1.95 V I/O supply voltage: 1.8 V RF supply voltage: 3.85 V 2.4 GHz WLAN: 2.4002.4835 GHz 5 GHz WLAN: 5.1505.850 GHz BT: 2.4022.480 GHz 802.11a: 6 Mbps, 9 Mbps, 12 Mbps, 18 Mbps, 24 Mbps, 36 Mbps, 48 Mbps, 54 Mbps 802.11b: 1 Mbps, 2 Mbps, 5.5 Mbps, 11 Mbps 802.11g: 6 Mbps, 9 Mbps, 12 Mbps, 18 Mbps, 24 Mbps, 36 Mbps, 48 Transmission Data Rates Mbps, 54 Mbps 802.11n: HT20 (MCS0-7), HT40 (MCS8-15) 802.11ac: VHT20 (MCS0-8), VHT40 (MCS0-9), VHT80 (MCS0-9) 802.11ax: HE20 (MCS0-11), HE40 (MCS0-11), HE80 (MCS0-11) FG50V_Hardware_Design 12 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Transmitting Power 2.4 GHz 802.11b @ 11 Mbps: 20 dBm 802.11g @ 54 Mbps: 17 dBm 802.11n, HT20 @ MCS7: 16 dBm 802.11n, HT40 @ MCS7: 16 dBm 802.11ax, HE20 @ MCS11: 13 dBm 802.11ax, HE40 @ MCS11: 13 dBm 5 GHz 802.11a @ 54 Mbps: 15.5 dBm 802.11n, HT20 @ MCS7: 15 dBm 802.11n, HT40 @ MCS7: 15 dBm 802.11ac, VHT20 @ MCS8: 14 dBm 802.11ac, VHT40 @ MCS9: 14 dBm 802.11ac, VHT80 @ MCS9: 14 dBm 802.11ax, HE20 @ MCS11: 13 dBm 802.11ax, HE40 @ MCS11: 13 dBm 802.11ax, HE80 @ MCS11: 13 dBm IEEE 802.11a/b/g/n/ac/ax BT 5.1*

Protocol Features Operation Mode AP, STA WLAN Interface PCIe BT Interface UART and PCM*

Modulation BPSK, QPSK, CCK, 16QAM, 64QAM, 256QAM, 1024QAM RF Antenna Interfaces ANT_WIFI0, ANT_WIFI1, ANT_BT*

50 impedance Physical Characteristics Temperature Range Size: (19.5 0.2) mm (21.5 0.2) mm (2.1 0.2) mm Package: LGA Weight: TBD Operating temperature range: -40 C to +85 C 1) Storage temperature range: -40 C to +95 C RoHS All hardware components are fully compliant with EU RoHS directive NOTES 1. 2. 1) Within operating temperature range, the module is IEEE compliant.

* means under development. FG50V_Hardware_Design 13 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 2.3. Functional Diagram The following figure shows a block diagram of FG50V module. VDD_CORE_VL VDD_CORE_VM VDD_CORE_VH VDD_IO PCIe COEX Control BT UART BT PCM Debug UART 2 WLAN_SLP_CLK BB 48MHz XO VDD_RF 5G xFEM 2.4G xFEM Diplexer ANT_WIFI1 BPF BPF Diplexer ANT_WIFI0 Switch/

BT xLNA BPF ANT_BT Optional dedicated BT antenna switch/xLNA Figure 1: Functional Diagram of FG50V Module 2.4. Evaluation Board In order to help you to develop applications with FG50V module conveniently, Quectel supplies the evaluation board (EVB), USB to RS-232 converter cable, USB data cable, power adapter, antenna and other peripherals to control or test the module. For more details, see document [1]. FG50V_Hardware_Design 14 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 3 Application Interfaces 3.1. General Description FG50V module is equipped with 108 LGA pins that can be connected to the cellular application platform. The subsequent chapters will provide a detailed introduction to the following interfaces and pins of the module:

Power supply WLAN interface BT interface*

Coexistence interface WLAN_SLP_CLK interface Other interfaces RF antenna interfaces NOTE

* means under development. FG50V_Hardware_Design 15 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 3.2. Pin Assignment Figure 2: Pin Assignment (Top View) FG50V_Hardware_Design 16 / 54 Wi-Fi&BT Module Series FG50V Hardware Design NOTE Please keep all RESERVED pins open. 3.3. Pin Description The following tables show the pin description of FG50V module. Table 2: I/O Parameters Definition Description Analog Input Analog Input Digital Input Digital Output Bidirectional Power Input Type AI AO DI DO IO PI Table 3: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Comment VDD_CORE_VL 1, 2, 47 PI VDD_CORE_VM 45 PI 0.95 V power supply for the modules main part 1.35 V power supply for the modules main part Vmin = 0.9 V Vnorm = 0.95 V Vmax = 1.0 V Vmin = 1.28 V Vnorm = 1.35 V Vmax = 1.42 V It must be provided with sufficient current of up to 1.7 A. It must be provided with sufficient current of up to 0.4 A. FG50V_Hardware_Design 17 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 1.95 V power supply for the modules main part Vmin = 1.85 V Vnorm = 1.95 V Vmax = 2.05 V 1.8 V power supply for the modules I/O pins Vmin = 1.7 V Vnorm = 1.8 V Vmax = 1.9 V 3.85 V power supply for the modules RF part Vmin = 3.3 V Vnorm = 3.85 V Vmax = 4.25 V It must be provided with sufficient current of up to 0.4 A. It must be provided with sufficient current of up to 0.05 A. It must be provided with sufficient current of up to 1.3 A. VDD_CORE_VH 46 PI VDD_IO 43 PI VDD_RF 19, 20, 63 PI WLAN Interface GND 6, 24, 26, 27, 29, 30, 31, 32, 34, 44, 51, 66, 67, 69, 70, 74, 75, 85108 Pin Name Pin No. I/O Description DC Characteristics Comment VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V 1.8 V power domain. Active high. It is suggested to pull down this pin with a 100 k resistor. Require impedance of 85 . differential WLAN_EN 84 DI WLAN enable PCIE_REFCLK_P PCIE_REFCLK_M PCIE_TX_P PCIE_TX_M PCIE_RX_P PCIE_RX_M 54 9 52 7 56 11 12 AI AI PCIe reference clock (+) PCIe reference clock (-) AO PCIe transmit (+) AO PCIe transmit (-) AI PCIe receive (+) AI PCIe receive (-) PCIE_CLKREQ_N DO PCIe clock request VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V PCIE_RST_N 14 DI PCIe reset 1.8 V power domain. Active low. PCIE_WAKE_N 13 DO PCIe wake up BT Interface Pin Name Pin No. I/O Description DC Characteristics Comment FG50V_Hardware_Design 18 / 54 Wi-Fi&BT Module Series FG50V Hardware Design BT_EN 83 DI BT enable 1.8 V power domain. Active high. It is suggested to pull down this pin with a 100 k resistor. VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V PCM_DIN*

76 DI PCM data input 1.8 V power domain. PCM_SYNC*

35 DI 1.8 V power domain. PCM data frame sync PCM_CLK*

37 DI PCM clock 1.8 V power domain. PCM_DOUT*

36 DO PCM data output BT_RTS 77 DO BT UART request to send VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. Externally pull this pin up to VDD_IO. 1.8 V power domain. BT_CTS 38 DI 1.8 V power domain. BT UART clear to send BT_TXD 39 DO BT UART transmit 1.8 V power domain. BT_RXD 78 DI BT UART receive 1.8 V power domain. BT_WAKEUP_ HOST*

HOST_WAKEUP_ BT*

Coexistence Interface 61 DO BT wakes up host 1.8 V power domain. 60 DI Host wakes up BT 1.8 V power domain. Externally pull this pin down. Pin Name Pin No. I/O Description DC Characteristics Comment FG50V_Hardware_Design 19 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 2.4G WWAN &

WLAN/BT coexistence transmit 2.4G WWAN &

WLAN/BT coexistence receive Allows LAA/n79 to control WLAN xFEM during WLAN sleep mode WLAN xFEM control to enable LAA/n79 transmit WLAN xFEM control for LAA/n79 receiver WLAN xFEM control to enable WLAN transmit WLAN xFEM control to disable WLAN PA COEX_TXD 59 DO COEX_RXD 16 DI LAA_AS_EN 82 DI LAA_TXEN 41 DI LAA_RX 81 DI WLAN_TXEN 42 DO PA_MUTE 80 DI Other Interfaces SW_CTRL*

57 DO Switch control WLAN_DBG_TXD 21 DO WLAN_DBG_RXD 65 DI BT_DBG_TXD 23 DO WLAN debug UART transmit WLAN debug UART receive BT debug UART transmit VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. If unused, keep these pins open. 1.8 V power domain. Active high. If unused, keep this pin open. 1.8 V power domain. If unused, keep these pins open. Pin Name Pin No. I/O Description DC Characteristics Comment FG50V_Hardware_Design 20 / 54 Wi-Fi&BT Module Series FG50V Hardware Design BT debug UART receive VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V BT_DBG_RXD 22 DI RF Antenna Interfaces Pin Name Pin No. I/O Description DC Characteristics Comment ANT_WIFI0 ANT_WIFI1 ANT_BT*

28 33 25 IO IO IO BT and WLAN antenna interface WLAN antenna interface Reserved dedicated BT antenna interface WLAN_SLP_CLK Interface 50 impedance. 50 impedance. 50 impedance. Pin Name Pin No. I/O Description DC Characteristics Comment WLAN_SLP_CLK 15 DI WLAN sleep clock RESERVED Interfaces VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V 1.8 V power domain. If unused, keep this pin open. Pin Name Pin No. I/O Description DC Characteristics Comment RESERVED 4, 5, 8, 10, 17, 18, 40, 49, 50, 53, 55, 58, 62, 64, 68, 7173, 79 Keep these pins open. NOTE

* means under development. 3.4. Power Supply The following table shows the power supply pins and ground pins of FG50V module. FG50V_Hardware_Design 21 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Table 4: Definition of Power Supply and GND Pins Pin Name Pin No. Description Min. Typ. Max. Unit VDD_CORE_VL 1, 2, 47 0.9 0.95 1.0 VDD_CORE_VM VDD_CORE_VH VDD_IO 45 46 43 0.95 V power supply for the modules main part 1.35 V power supply for the modules main part 1.95 V power supply for the modules main part 1.8 V power supply for the modules I/O pins 3.85 V power supply for the modules RF part 1.28 1.35 1.42 1.85 1.95 2.05 1.7 1.8 1.9 V V V V V VDD_RF 19, 20, 63 3.3 3.85 4.25 GND 6, 24, 26, 27, 29, 30, 31, 32, 34, 44, 51, 66, 67, 69, 70, 74, 75, 85108 Among them, VDD_CORE_VL, VDD_CORE_VM, VDD_CORE_VH, and VDD_IO can be powered by either Quectel RG50xQ series or discrete power supply chips while VDD_RF can be powered by a discrete power supply chip. The following figures show the two power designs. For more details, see document [2]. e.g. DC 5 V input DC-DC Typ. 3.85 V output VDD_RF VDD_WIFI_VL VDD_CORE_VL VDD_WIFI_VM RG50xQ VDD_WIFI_VH VDD_CORE_VM VDD_CORE_VH FG50V VDD_EXT VDD_IO Figure 3: Power Reference Design with RG50xQ Series FG50V_Hardware_Design 22 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Figure 4: Power Reference Design with Discrete Power Supply Chips 3.5. WLAN Interface The following figure shows the WLAN interface connection between FG50V and the host. Figure 4: WLAN Interface Connection FG50V_Hardware_Design 23 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 3.5.1. WLAN_EN WLAN_EN is used to control the WLAN function of FG50V module. WLAN function will be enabled when WLAN_EN is at high level. Table 5: Pin Definition of WLAN_EN Pin Name Pin No. I/O Description Comment WLAN_EN 84 DI WLAN enable 1.8 V power domain. Active high. It is suggested to pull down this pin with a 100 k resistor. 3.5.2. PCIe Interface The following table shows the pin definition of the PCIe interface of FG50V. Table 6: Pin Definition of PCIe Interface Pin Name Pin No. Description I/O Comment PCIE_REFCLK_P PCIE_REFCLK_M PCIE_TX_P PCIE_TX_M PCIE_RX_P PCIE_RX_M PCIE_RST_N PCIE_WAKE_N 54 9 52 7 56 11 12 14 13 AI AI AO AO AI AI DO DI DO PCIe reference clock (+) PCIe reference clock (-) PCIe transmit (+) PCIe transmit (-) PCIe receive (+) PCIe receive (-) PCIe reset PCIe wakes up PCIE_CLKREQ_N PCIe clock request Require differential impedance of 85 . 1.8 V power domain. Active low. FG50V_Hardware_Design 24 / 54 Wi-Fi&BT Module Series FG50V Hardware Design The following figure shows the PCIe interface connection between FG50V and the host. 1V8 100K 100K NM FG50V PCIE_CLKREQ_N PCIE_WAKE_N PCIE_RST_N PCIE_REFCLK_P PCIE_REFCLK_M PCIE_TX_P PCIE_TX_M PCIE_RX_P PCIE_RX_M R1 R2 C1 C2 0R 0R 100 nF 100 nF 100 nF 100 nF Host PCIE_CLKREQ PCIE_WAKE PCIE_RST PCIE_REFCLK_P PCIE_REFCLK_M PCIE_RX0_P PCIE_RX0_M PCIE_TX0_P PCIE_TX0_M C3 C4 Figure 5: PCIe Interface Connection To ensure the signal integrity of PCIe interface, C1 and C2 should be placed close to the FG50V module, and C3 and C4 should be placed close to the host The extra stubs of traces must be avoided. The following principles of PCIe interface design should be complied with, so as to meet PCIe Gen2 specifications. It is important to route PCIE_TX_P/M, PCIE_RX_P/M, and PCIE_REFCLK_P/M as differential pairs with total grounding. And the differential impedance should be 85 10 %. The maximum trace length of each differential pair (PCIE_TX_P/M, PCIE_RX_P/M, and PCIE_REFCLK_P/M) should be less than 300 mm, and trace length matching within each differential pair should be less than 0.7 mm. Space between PCIe signals and all other signals (inter-interface) should be four times the trace width. Do not route signal traces under crystals, oscillators, magnetic devices, or RF signal traces. It is important to route the PCIe differential traces in inner-layer of the PCB and surround the traces with ground on that layer and with ground planes above and below. 3.6. BT Interface The following figure shows the block diagram of BT interface connection between FG50V and the host. FG50V_Hardware_Design 25 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Figure 6: Block Diagram of BT Interface Connection NOTE The GPIO_1 connected to BT_WAKEUP_HOST must be interruptible. 3.6.1. BT_EN BT_EN is used to control the BT function of FG50V module. BT function will be enabled when BT_EN is at high level. Table 7: Pin Definition of BT_EN Pin Name Pin No. I/O Description Comment BT_EN 83 DI BT enable 1.8 V power domain. Active high. It is suggested to pull down this pin with a 100 k resistor. 3.6.2. BT_WAKEUP_HOST* and HOST_WAKEUP_BT*

BT_WAKEUP_HOST and HOST_WAKEUP_BT are used to wake up the host and FG50V. If you use Quectel RG50x series as the host, these two pins can be left unconnected because the wakeup function can be achieved through BT UART. FG50V_Hardware_Design 26 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Table 8: Pin Definition of BT_WAKEUP_HOST and HOST_WAKEUP_BT Pin Name Pin No. I/O Description Comment BT_WAKEUP_HOST DO BT wakes up host 1.8 V power domain. HOST_WAKEUP_BT DI Host wakes up BT 1.8 V power domain. Externally pull this pin down. 61 60 NOTE

* means under development. 3.6.3. PCM Interface*

The PCM interface is for audio over Bluetooth phone. The following table shows the pin definition of PCM interface. Table 10: Pin Definition of PCM Interface Pin Name Pin No. I/O Description Comment PCM_DIN PCM_SYNC PCM_CLK 76 35 37 36 DI DI DI PCM data input 1.8 V power domain. PCM data frame sync 1.8 V power domain. PCM clock 1.8 V power domain. PCM_DOUT DO PCM data output The following figure shows the PCM interface connection between FG50V and the host. 1.8 V power domain. Externally pull this pin up to VDD_IO. FG50V_Hardware_Design 27 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Figure 7: PCM Interface Connection NOTE

* means under development. 3.6.4. UART Interface FG50V supports an HCI UART as defined in Bluetooth Core Specification Version 4.0. In addition, the UART interface also supports software (in-band) sleep control of Bluetooth with Quectel RG50xQ series. You can also choose other 5G modules upon validation tests. If you have any questions, please contact Quectel Technical Support. The following table shows the pin definition of UART interface. Table 11: Pin Definition of UART Interface Pin Name Pin No. I/O Description Comment BT_RTS BT_CTS BT_TXD BT_RXD 77 38 39 78 DO BT UART request to send 1.8 V power domain. DI BT UART clear to send 1.8 V power domain. DO BT UART transmit 1.8 V power domain. DI BT UART receive 1.8 V power domain. FG50V_Hardware_Design 28 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 3.7. Conexistence Interface FG50V supports 2.4G WWAN & WLAN/BT coexistence (with coexistence UART) and 5G WWAN &

WLAN coexistence. The following table shows the pin definition of coexistence interface. Table 9: Pin Definition of Coexistence Interface Pin Name Pin No. I/O Description Comment COEX_TXD COEX_RXD LAA_AS_EN LAA_TXEN LAA_RX WLAN_TXEN 59 16 82 41 81 42 80 DO 2.4G WWAN & WLAN/BT coexistence transmit DI DI DI DI 2.4G WWAN & WLAN/BT coexistence receive Allows LAA/n79 to control WLAN xFEM during WLAN sleep mode WLAN xFEM control to enable LAA/n79 transmit WLAN xFEM control for LAA/n79 receiver DO WLAN xFEM control to enable WLAN transmit 1.8 V power domain. If unused, keep these pins open. PA_MUTE DI WLAN xFEM control to disable WLAN PA The following figure shows the coexistence interface connection between FG50V and Quectel RG50xQ series. You can also choose other 5G modules upon validation tests. If you have any questions, please contact Quectel Technical Support. Figure 8: Coexistence Interface Connection FG50V_Hardware_Design 29 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 3.8. WLAN_SLP_CLK Interface The 32.768 kHz clock is used in low power modes, such as IEEE power saving mode and sleep mode. It serves as a timer to determine when to wake up the FG50V module to receive signals in various power saving schemes, and to maintain basic logic operations when the module is in sleep mode. Table 10: Pin Definition of WLAN_SLP_CLK Interface Pin Name Pin No. I/O Description Comment WLAN_SLP_CLK 15 DI WLAN sleep clock If unused, keep this pin open. 3.9. Others Interfaces 3.9.1. SW_CTRL*

The following table shows the pin definition of SW_CTRL. Table 11: Pin Definition of SW_CTRL Pin Name Pin No. I/O Description Comment SW_CTRL 57 DO Switch control 1.8 V power domain. Active high. If unused, keep this pin open. The following figure shows the reference design for SW_CTRL connection between FG50V and the host. Figure 9: SW_CTRL Connection FG50V_Hardware_Design 30 / 54 Wi-Fi&BT Module Series FG50V Hardware Design NOTE

* means under development. 3.9.2. WLAN Debug Interface The following table shows the pin definition of WLAN debug interface. Connect this interface to the test points in your application. Table 12: Pin Definition of WLAN Debug Interface Pin Name Pin No. I/O Description Comment WLAN_DBG_TXD DO WLAN debug UART transmit WLAN_DBG_RXD DI WLAN debug UART receive 21 65 1.8 V power domain. If unused, keep these pins open. 3.9.3. BT Debug Interface The following table shows the pin definition of BT debug interface. Connect this interface to the test points in your application. Table 13: Pin Definition of BT Debug interface Pin Name Pin No. I/O Description Comment BT_DBG_TXD DO BT debug UART transmit BT_DBG_RXD DI BT debug UART receive 23 22 1.8 V power domain. If unused, keep these pins open. 3.10. RF Antenna Interfaces The following table shows the pin definition of RF antenna interfaces. FG50V_Hardware_Design 31 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Table 14: Pin Definition of RF Antenna Interfaces Pin Name Pin No. I/O Description Comment ANT_WIFI0 IO BT and WLAN antenna interface 50 impedance ANT_WIFI1 IO WLAN antenna interface 50 impedance ANT_BT*

IO Reserved dedicated BT antenna interface 50 impedance 28 33 25 NOTE

* means under development. 3.10.1. Operating Frequency Table 15: Operating Frequency of the Module Feature Frequency 2.4 GHz WLAN 2.4002.4835 5 GHz WLAN 5.1505.850 2.4022.480 BT Unit GHz GHz GHz 3.10.2. Reference Design of RF Antenna Interfaces FG50V provides three RF antenna interfaces for antenna connection. The following reference circuit design shows an example with ANT_WIFI0. For the other RF antenna interfaces, the reference design is the same. It is recommended to reserve a -type matching circuit for better RF performance, and the -type matching components (C1, C2, R1) should be placed as close to the antenna as possible. The capacitors are not mounted by default. FG50V_Hardware_Design 32 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Figure 10: Reference Circuit for RF Antenna Interfaces 3.10.3. Reference Design of RF Layout For users PCB, the characteristic impedance of all RF traces should be controlled to 50 . The impedance of the RF traces is usually determined by the trace width (W), the materials dielectric constant, the height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB structures. Figure 11: Microstrip Design on a 2-layer PCB FG50V_Hardware_Design 33 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Figure 12: Coplanar Waveguide Design on a 2-layer PCB Figure 13: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 14: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design:

Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 . connected to ground. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully The distance between the RF pins and the RF connector should be as short as possible, and all the right-angle traces should be changed to curved ones. The recommended trace angle is 135. There should be clearance under the signal pin of the antenna connector or solder joint. The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around RF traces and the reference ground could help to improve RF performance. The distance between FG50V_Hardware_Design 34 / 54 Wi-Fi&BT Module Series FG50V Hardware Design the ground vias and RF traces should be no less than two times the width of RF signal traces (2 W). Keep RF traces away from interference sources, and avoid intersection and paralleling between traces on adjacent layers. For more details about RF layout, see document [3]. 3.10.4. Antenna Requirements The following table shows the requirements for antennas. Table 16: Antenna Requirements Frequency Range Type VSWR Gain Max Input Power Input Impedance Polarization Type Cable insertion loss Requirements 2.4002.4835 GHz 5.1805.825 GHz

< 2:1 (Recommended) 5.38 dBi (Typ.) 50 W 50 Vertical

< 1 dB 3.10.5. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use U.FL-R-SMT connector provided by Hirose. FG50V_Hardware_Design 35 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Figure 15: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 16: Mechanicals of UF.L-LP Connectors (Unit: mm) The following figure describes the space factor of mated connector FG50V_Hardware_Design 36 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Figure 17: Space Factor of Mated Connector (Unit: mm) For more details, visit http://www.hirose.com. FG50V_Hardware_Design 37 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 4 Reliability, Radio and Electrical Characteristics 4.1. General Description This chapter mainly introduces electrical and radio characteristics of FG50V module. The details are listed in the subsequent chapters. Parameter VDD_CORE_VL VDD_CORE_VM VDD_CORE_VH VDD_IO VDD_RF NOTE 4.2. Electrical Characteristics The following table shows the absolute maximum ratings. Table 17: Absolute Maximum Ratings Min. Max. Unit

-0.3

-0.3

-0.3

-0.3

-0.3

-0.3 VDDX + 0.2 VDDX + 0.2 VDDX + 0.2 VDDX + 0.2 4.8 V V V V V V Digital I/O Input Voltage VDD_IO + 0.2 VDDX is the external supply voltage for the corresponding power input pins. FG50V_Hardware_Design 38 / 54 Wi-Fi&BT Module Series FG50V Hardware Design The following table shows the recommended operating conditions of the module. Table 18: Recommended Operating Conditions Max. Unit Typ. 0.95 1.35 1.95 1.8 3.85 1.0 1.42 2.05 1.9 4.25 Parameter VDD_CORE_VL VDD_CORE_VM VDD_CORE_VH VDD_IO VDD_RF Min. 0.9 1.28 1.85 1.7 3.3 4.3. I/O Interface Characteristics The following table shows the general DC electrical characteristics over recommended operating conditions (unless otherwise specified). Table 19: General DC Electrical Characteristics Symbol Parameter Min. Max. Unit VIH VIL VOH VOL IIL High Level Input Voltage 0.65 VDD_IO VDD_IO + 0.3 Low Level Input Voltage

-0.3 0.35 VDD_IO High Level Output Voltage VDD_IO - 0.45 VDD_IO Low Level Output Voltage 0 Input Leakage Current TBD 0.45 TBD V V V V V V V V V A FG50V_Hardware_Design 39 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 4.4. Operating and Storage Temperatures Table 20: Operating and storage Temperatures Parameter Operating Temperature Range 1) Storage Temperature Range Min.

-40

-40 Typ. 25 Max. Unit

+85

+95 C C NOTE 1) Within operating temperature range, the module is IEEE compliant. 4.5. Current Consumption The following tables show the current consumption of the module in different modes. 4.5.1. Current Consumption in Low Power Modes Table 21: Current Consumption of the Module (Low Power Modes, Unit: mm) Wi-Fi State VDD_CORE_VL

(0.95 V) VDD_CORE_ VM (1.35 V) VDD_CORE_VH

(1.95 V) VDD_IO

(1.8 V) VDD_RF

(3.85 V) Wi-Fi disabled 0.0479 Wi-Fi enabled 117.75 0.210 28.91 0.001 74.15 0.001 0.018 23.69 0.218 1. 1) OFF: A series of commands can be used to set the module to OFF state (Wi-Fi disabled). In this state, the sleep clock is disabled and no data is saved. 2) Idle: In this state, Wi-Fi is enabled but no device is connected. For more detailed commands for Wi-Fi state, see document [4]. 2. 3. 4. The current consumption above includes both ANT_WIFI0 and ANT_WIFI1. FG50V_Hardware_Design 40 / 54 Module State OFF 1) Idle 2) NOTES Wi-Fi&BT Module Series FG50V Hardware Design 4.5.2. Current Consumption in Normal Operation Table 22: Current Consumption of the Module (Normal Operation, Unit: mA) Description Conditions VDD_CORE_V VDD_CORE_V VDD_CORE_V VDD_IO VDD_RF L (0.95 V) M (1.35 V) H (1.95 V)

(1.8 V)

(3.85 V) 802.11b 802.11g 802.11n 802.11a 802.11ac TX (2.4 GHz) 1 Mbps TX (2.4 GHz) 11 Mbps TX (2.4 GHz) 6 Mbps TX (2.4 GHz) 54 Mbps TX (2.4 GHz) HT20 MCS0 TX (2.4 GHz) HT20 MCS7 TX (2.4 GHz) HT40 MCS0 TX (2.4 GHz) HT40 MCS7 TX (5 GHz) HT20 MCS0 TX (5 GHz) HT20 MCS7 TX (5 GHz) HT40 MCS0 TX (5 GHz) HT40 MCS7 TX (5 GHz) 6 Mbps TX (5 GHz) 54 Mbps TX (5 GHz) VHT20 MCS0 TX (5 GHz) VHT20 MCS8 TX (5 GHz) VHT40 MCS0 TX (5 GHz) VHT40 MCS9 460.7 185.5 127.0 501.9 179.7 118.3 460.5 175.9 123.3 512.2 174.2 115.1 442.6 170.6 120.7 443.9 170.2 120.3 475.8 171.2 120.2 476.1 170.7 120.0 418.7 206.8 118.0 421.3 206.6 117.4 452.7 207.6 117.5 451.9 207.2 116.9 438.2 212.6 120.5 479.3 200.6 111.7 432.1 201.5 117.9 418.1 200.1 117.2 453.6 201.8 118.0 451.4 201.1 117.3 2.3 2.5 2.2 2.7 2.4 2.4 2.4 2.4 2.7 2.8 2.8 2.8 2.9 3.0 2.8 2.8 2.8 2.8 565.1 445.1 521.3 330.4 521.2 472.9 517.2 495.2 497.2 427.1 504.3 429.6 499.5 237.9 481.0 408.4 486.7 410.5 FG50V_Hardware_Design 41 / 54 Wi-Fi&BT Module Series FG50V Hardware Design TX (5 GHz) VHT80 MCS0 TX (5 GHz) VHT80 MCS9 TX (2.4 GHz) HE20 MCS0 TX (2.4 GHz) HE20 MCS11 TX (2.4 GHz) HE40 MCS0 TX (2.4 GHz) HE40 MCS11 TX (5 GHz) HE20 MCS0 TX (5 GHz) HE20 MCS11 TX (5 GHz) HE40 MCS0 TX (5 GHz) HE40 MCS11 TX (5 GHz) HE80 MCS0 TX (5 GHz) HE80 MCS11 571.9 201.7 116.8 570.0 203.1 117.1 452.0 174.6 120.9 449.1 174.2 119.7 481.8 175.4 120.4 483.4 174.5 119.6 430.1 202.0 135.9 428.6 201.1 135.1 461.9 202.2 135.9 461.6 201.5 135.2 585.7 214.7 135.8 584.4 214.1 134.9 2.8 2.8 2.4 2.5 2.5 2.4 2.8 2.8 2.8 2.9 2.8 2.8 488.7 409.6 512.1 441.9 515.3 443.2 483.8 393.9 482.9 395.6 488.0 392.4 802.11ax 4.6. RF Performances The following tables summarize the transmitting and receiving performances of FG50V. 4.6.1. Conducted RF Output Power Table 23: Conducted RF Output Power at 2.4 GHz Frequency 802.11b @ 1 Mbps Min. 17.5 Typ. 20 Unit dBm FG50V_Hardware_Design 42 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Table 24: Conducted RF Output Power at 5 GHz 802.11b @ 11 Mbps 802.11g @ 6 Mbps 802.11g @ 54 Mbps 802.11n, HT20 @ MCS0 802.11n, HT20 @ MCS7 802.11n, HT40 @ MCS0 802.11n, HT40 @ MCS7 802.11ax, HE20 @ MCS0 802.11ax, HE20 @ MCS11 802.11ax, HE40 @ MCS0 802.11ax, HE40 @ MCS11 Frequency 802.11a @ 6 Mbps 802.11a @ 54 Mbps 802.11n, HT20 @ MCS0 802.11n, HT20 @ MCS7 802.11n, HT40 @ MCS0 802.11n, HT40 @ MCS7 802.11ac, VHT20 @ MCS0 802.11ac, VHT20 @ MCS8 802.11ac, VHT40 @ MCS0 802.11ac, VHT40 @ MCS9 802.11ac, VHT80 @ MCS0 17.5 15 14.5 15 13.5 15.5 13.5 15.5 10.5 15.5 10.5 Min. 15.5 13 15.5 12.5 15.5 12.5 15 11.5 15 11.5 15 20 18.5 17 18.5 16 18 16 18 13 18 13 Typ. 18 15.5 18 15 18 15 17.5 14 17.5 14 17.5 dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm Unit dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm FG50V_Hardware_Design 43 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 11.5 15 10.5 15 10.5 15 10.5 14 17.5 13 17.5 13 17.5 13 dBm dBm dBm dBm dBm dBm dBm 4.6.2. Conducted RF Receiving Sensitivity Table 25: Conducted RF Receiving Sensitivity at 2.4 GHz Receiving Sensitivity (Typ.) 802.11ac, VHT80 @ MCS9 802.11ax, HE20 @ MCS0 802.11ax, HE20 @ MCS11 802.11ax, HE40 @ MCS0 802.11ax, HE40 @ MCS11 802.11ax, HE80 @ MCS0 802.11ax, HE80 @ MCS11 Frequency 802.11b @ 1 Mbps 802.11b @ 11 Mbps 802.11g @ 6 Mbps 802.11g @ 54 Mbps 802.11n, HT20 @ MCS0 802.11n, HT20 @ MCS7 802.11n, HT40 @ MCS0 802.11n, HT40 @ MCS7 802.11ax, HE20 @ MCS0 802.11ax, HE20 @ MCS11 802.11ax, HE40 @ MCS0 802.11ax, HE40 @ MCS11

-96 dBm

-89 dBm

-93 dBm

-74 dBm

-93 dBm

-73 dBm

-91 dBm

-70 dBm

-93 dBm

-65 dBm

-91 dBm

-62 dBm FG50V_Hardware_Design 44 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Table 26: Conducted RF Receiving Sensitivity at 5 GHz Frequency Receiving Sensitivity (Typ.)

-94 dBm

-75 dBm

-93 dBm

-75 dBm

-91 dBm

-72 dBm

-94 dBm

-72 dBm

-92 dBm

-67 dBm

-89 dBm

-62 dBm

-94 dBm

-65 dBm

-92 dBm

-63 dBm

-89 dBm

-59 dBm 802.11a @ 6 Mbps 802.11a @ 54 Mbps 802.11n, HT20 @ MCS0 802.11n, HT20 @ MCS7 802.11n, HT40 @ MCS0 802.11n, HT40 @ MCS7 802.11ac, VHT20 @ MCS0 802.11ac, VHT20 @ MCS8 802.11ac, VHT40 @ MCS0 802.11ac, VHT40 @ MCS9 802.11ac, VHT80 @ MCS0 802.11ac, VHT80 @ MCS9 802.11ax, HE20 @ MCS0 802.11ax, HE20 @ MCS11 802.11ax, HE40 @ MCS0 802.11ax, HE40 @ MCS11 802.11ax, HE80 @ MCS0 802.11ax, HE80 @ MCS11 4.7. Electrostatic Discharge The module is not protected against Electrostatic Discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates the module. FG50V_Hardware_Design 45 / 54 Wi-Fi&BT Module Series FG50V Hardware Design The following table shows the module electrostatic discharge characteristics. Table 27: Electrostatic Discharge Characteristics Tested Points Contact Discharge Air Discharge Unit VDD_RF, GND Antenna Interfaces Other Interfaces 6 6 0.5 10 10 1 kV kV kV FG50V_Hardware_Design 46 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 5 Mechanical Dimensions This chapter describes the mechanical dimensions of FG50V module. All dimensions are measured in millimeter

(mm), and the dimensional tolerances are 0.05 mm unless otherwise specified. 5.1. Mechanical Dimensions of the Module Pin1 Figure 18: FG50V Top and Side Dimensions (Top and Side View) FG50V_Hardware_Design 47 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Pin1 Figure 19: FG50V Bottom Dimension (Bottom View) The package warpage level of the module conforms to JEITA ED-7306 standard. NOTE FG50V_Hardware_Design 48 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 5.2. Recommended Footprint Pin1 Figure 20: Recommended Footprint (Top View) NOTES the motherboard. 2. Keep all RESERVED pins open. 1. For easy maintenance of this module, keep at least 3 mm between the module and other components on FG50V_Hardware_Design 49 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 5.3. Top and Bottom Views of the Module Figure 21: Top View of the Module Figure 22: Bottom View of the Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. FG50V_Hardware_Design 50 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 6 Storage, Manufacturing and Packaging 6.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 5 C and the relative humidity should be 3560 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition. 3. The floor life of the module is 168 hours 1) in a plant where the temperature is 23 5 C and relative humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be processed in reflow soldering or other high-temperature operations within 24 hours. Otherwise, the module should be stored in an environment where the relative humidity is less than 10 % (e.g. a drying cabinet). 4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under the following circumstances:

The module is not stored in Recommended Storage Condition;

Violation of the third requirement above occurs;

Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;

Before module repairing. If needed, the pre-baking should follow the requirements below:

The module should be baked for 8 hours at 120 5 C;

All modules must be soldered to PCB within 24 hours after the baking, otherwise they should be put in a dry environment such as in a drying oven. 5. NOTES FG50V_Hardware_Design 51 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 1) This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 1. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. If the temperature and moisture do not conform to IPC/JEDEC J-STD-033 or the relative moisture is over 60%, it is recommended to start the solder reflow process within 24 hours after the package is removed. And do not remove the packages of tremendous modules if they are not ready for soldering. 3. Please take the module out of the packaging and put it on high-temperature resistant fixtures before the baking. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for baking procedure. 6.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.130.15 mm. For more details, see document [5]. It is suggested that the peak reflow temperature is 238246 C, and the absolute maximum reflow temperature is 246 C. To avoid damage to the module caused by repeated heating, it is strongly recommended that the module should be mounted after reflow soldering for the other side of PCB has been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related parameters are shown below. Temp. (C) 246 238 220 200 150 100 Soak Zone A Max slope: 1 to 3C/s Reflow Zone Max slope:

2 to 3C/s C Cooling down slope:

-1.5 to -3C/s B D Figure 23: Recommended Reflow Soldering Thermal Profile Table 28: Recommended Thermal Profile Parameters Factor Recommendation FG50V_Hardware_Design 52 / 54 Wi-Fi&BT Module Series FG50V Hardware Design Soak time (between A and B: 150 C and 200 C) 70120 s 13 C/s 1 23 C/s 4570 s 238 C to 246 C

-1.5 to -3 C/s Soak Zone Max slope Reflow Zone Max slope Reflow time (D: over 220 C) Max temperature Cooling down slope Reflow Cycle Max reflow cycle 6.3. Packaging Table 30: Reel Packaging FG50V is packaged in tape and reel carriers. Each reel is 330 mm in diameter and contains 200 modules. The dimensions of tape and reel will be added in the updated version of this document. Model Name MOQ for MP Minimum Package: TBD Minimum Package TBD FG50V TBD Size: TBD N.W: TBD G.W: TBD Size: TBD N.W: TBD G.W: TBD FG50V_Hardware_Design 53 / 54 Wi-Fi&BT Module Series FG50V Hardware Design 7 Appendix References Table 29: Related Documents SN Document Name Description

[1] Quectel_5G_EVB_User_Guide EVB user guide for Quectel 5G modules

[2] Quectel_FG50V_Reference_Design FG50V reference design

[3] Quectel_RF_Layout_Application_Note RF layout application note

[4] Quectel_RG500Q_Series_Wi-Fi_Application_Note FG50V Wi-Fi_application note

[5] Quectel_Module_Secondary_SMT_Application_Note Module secondary SMT application note Table 30: Terms and Abbreviations Abbreviation Description AP BPF BPSK BT CCK CTS ESD EVB FEM GND HCI Access Point Band-Pass Filter Binary Phase Shift Keying Bluetooth Complementary Code Keying Clear To Send Electrostatic Discharge Evaluation Board Front-End Module Ground Host Controller Interface FG50V_Hardware_Design 54 / 54 Wi-Fi&BT Module Series FG50V Hardware Design HE HT IEEE IIL I/O LNA LTE Mbps MCS MOQ PA PCB PCM QAM QPSK RF RoHS RTS RX TBD TX UART USB VHT VIHmax Institute of Electrical and Electronics Engineers High Efficiency High Throughput Input Leakage Current Input/Output Low-Noise Amplifier Long Term Evolution Megabits per second Modulation and Coding Scheme Minimum Order Quantity Power Amplifier Printed Circuit Board Pulse Code Modulation Quadrature Amplitude Modulation Quadrature Phase Shift Keying Radio Frequency Restriction of Hazardous Substances Request To Send Receive To Be Determined Transmit Universal Serial Bus Very High Throughput Maximum Input High Level Voltage Value Universal Asynchronous Receiver/Transmitter FG50V_Hardware_Design 55 / 54 Wi-Fi&BT Module Series FG50V Hardware Design VIHmin VILmax VILmin VOLmax VOHmin VSWR Wi-Fi WLAN Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Minimum Input Low Level Voltage Value Maximum Output Low Level Voltage Value Minimum Output High Level Voltage Value Voltage Standing Wave Ratio Wireless-Fidelity Wireless Local Area Network FG50V_Hardware_Design 56 / 54

Quectel Wireless Solutions Company Limited Request for Confidentiality Date:

_2021/5/31_ Subject: Confidentiality Request for: _____ FCC ID: XMR202103FG50V ______ Pursuant to FCC 47 CRF 0.457(d) and 0.459 and IC RSP-100, Section 10, the applicant requests that a part of the subject FCC application be held confidential. Type of Confidentiality Requested Permanent Short Term Short Term Short Term Short Term Short Term Short Term Short Term Short Term Short Term ______(Insert Explanation as Necessary)______ Permanent*1 Permanent Permanent Permanent Permanent Permanent*

Exhibit Block Diagrams External Photos Internal Photos Operation Description/Theory of Operation Parts List & Placement/BOM Tune-Up Procedure Schematics Test Setup Photos Users Manual

*Note:

______ FCC ID: XMR202103FG50V _____ has spent substantial effort in developing this product and it is one of the first of its kind in industry. Having the subject information easily available to "competition" would negate the advantage they have achieved by developing this product. Not protecting the details of the design will result in financial hardship. Permanent Confidentiality:

The applicant requests the exhibits listed above as permanently confidential be permanently withheld from public review due to materials that contain trade secrets and proprietary information not customarily released to the public. Short-Term Confidentiality:

The applicant requests the exhibits selected above as short term confidential be withheld from public view for a period of ______ days from the date of the Grant of Equipment Authorization and prior to marketing. This is to avoid premature release of sensitive information prior to marketing or release of the product to the public. Applicant is also aware that they are responsible to notify TCB in the event information regarding the product or the product is made available to the public. TCB will then release the documents listed above for public disclosure pursuant to FCC Public Notice DA 04-1705. NOTE for Industry Canada Applications:

The applicant understands that until such time that IC distinguishes between Short Term and Permanent Confidentiality, either type of marked exhibit above will simply be marked Confidential when submitted to IC. Sincerely, By:

Certification Section Manager

(Signature/Title2) Jean Hu

(Print name)

Quectel Wireless Solutions Company Limited Declaration of the Modular Approval Applicant / Grantee FCC ID:

Model:

Quectel Wireless Solutions Company Limited XMR202103FG50V FG50V The single module transmitter has been evaluated then tested meeting the requirements under Part 15C Section 212 as below:

Modular approval requirement

(a) The radio elements of the modular transmitter must have their own shielding. The physical crystal and tuning capacitors may be located external to the shielded radio elements. EUT Condition The radio elements of the modular transmitter have their own shielding. Comply YES

(b) The modular transmitter have buffered modulation/data inputs (if such inputs are provided) to ensure that the module will comply with part 15 requirements under conditions of excessive data rates or over-modulation. must The modular has buffered data inputs, it is integrated in chip. Please see schematic.pdf YES

(c)The modular transmitter must have its own power supply regulation. YES YES All power lines derived from the host device are regulated before energizing other circuits internal to SMART MODULE . Please see schematic.pdf Device uses a micro-strip trace on the hosts printed circuit board to an antenna connector on the host circuit board. YES SMART MODULE was tested in a standalone configuration via a PCMCIA extender. Please see spurious setup

(d) the The antenna modular transmitter must transmission comply system and with requirements of Sections 15.203, 15.204(b) and 15.204(c). The antenna must either be permanently attached or employ a unique antenna coupler (at all connections between the module and the antenna, including the cable). The professional installation provision of Section 15.203 is not applicable to modules but can apply to limited modular approvals under paragraph (b) of this section.

(e)The be must modular transmitter tested in a stand-alone configuration, i.e., the module must not be inside another device during testing for compliance with part 15 requirements. Unless the transmitter module will be battery powered, it must comply with the AC line conducted requirements found in Section 15.207. AC or DC power lines and data input/output Quectel Wireless Solutions Company Limited least 10 centimeters to insure that lines connected to the module must not contain ferrites, unless they will be marketed with the module (see Section 15.27(a)). The length of these lines shall be the length typical of actual use or, if that length is unknown, there is no at coupling between the case of the module and supporting equipment. Any accessories, peripherals, or support equipment connected to the module during testing shall be unmodified and commercially available

(see Section 15.31(i)) must not be in side another device during testing.

(f)The modular be transmitter equipped with either a permanently affixed label or must be capable of electronically displaying its FCC identification number. must

(g) The modular transmitter must comply with any specific rules or operating requirements that ordinarily apply to a complete transmitter and the manufacturer must provide adequate instructions along with the module to explain any suchrequirements. A copy of these instructions must be included in the application for equipmentauthorizationrequirements,whicharebasedon theintendeduse/configurations.

(h)The modular transmitter must comply with any applicable RF exposure requirements in its final configuration. YES YES YES The label position of SMART MODULE is clearly indicated. If the FCC ID of the module cannot be seen when it is installed, then the host label must include the text: Contains FCC ID:

XMR202103FG50V. Please see the label.pdf SMART MODULE is compliant with all applicable FCC rules. Detail instructions are given in the User Manual. SMART MODULE is approved to comply with the applicable RF exposure requirement, please see the MPE evaluation with 20cm as the distance restriction. Quectel Wireless Solutions Company Limited Dated By:

2021/05/31 Jean Hu Signature Printed Title: Project Manager On behalf of :

Quectel Wireless Solutions Company Limited Telephone:

+86-21-51086236 ext 6511

Quectel Wireless Solutions Company Limited POWER OF ATTORNEY DATE:May 31, 2021 To:

Federal Communications Commission, Authorization & Evaluation Division, 7435 Oakland Mills Road, Columbia, MD 21046 We, the undersigned, hereby authorize TA Technology (Shanghai) Co., Ltd.

/Jinnan Han on our behalf, to apply to FCC on our equipment for FCC ID:

XMR202103FG50V. Any and all acts carried out by TA Technology (Shanghai) Co., Ltd. / Jinnan Han on our behalf shall have the same effect as acts of our own. Sincerely, Signature:

Print name: Jean Hu Company:

Quectel Wireless Solutions Company Limited