FCC ID: TX2-RTL8187 802.11b/g RTL8187 miniCard

by: Realtek Semiconductor Corp. latest update: 2006-08-08 model: RTL8187

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1	Users Manual	Users Manual	pdf	1.35 MiB	August 08 2006
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1	Confidentiality Request Letter	Cover Letter(s)	pdf	211.45 KiB	August 08 2006
1	LMA Letter	Cover Letter(s)	pdf	47.46 KiB	August 08 2006
1		RF Exposure Info	pdf		August 08 2006
1		Test Report	pdf		August 08 2006
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RTL8187L 802.11b/g RTL8187 miniCard Rev. 1.2 06 September 2005 Track ID: JATR-1076-21 RTL8187L Datasheet COPYRIGHT 2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document as is, without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engineers reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process. REVISION HISTORY Revision 1.0 1.1 1.2 Release Date 2004/10/22 2005/04/25 2005/09/06 Summary First release. Revised data transaction content. Added offset 8 information (Table 27, page 23, and Table 28, page 23). Added RoHS declaration (see last 2 pages). Added lead (Pb)-free and package identification information on page 4. Corrected section 14 Mechanical Dimensions, page 34. Wireless LAN Network Interface Controller ii Track ID: JATR-1076-21 Rev. 1.2 Table of Contents RTL8187L Datasheet 1. GENERAL DESCRIPTION ...............................................................................................................................................1 2. FEATURES ..........................................................................................................................................................................2 3. SYSTEM APPLICATIONS ................................................................................................................................................3 4. BLOCK DIAGRAM ............................................................................................................................................................3 6.5.1. 6.5.2. 5. PIN ASSIGNMENTS...........................................................................................................................................................4 5.1. LEAD (PB)-FREE PACKAGE IDENTIFICATION...................................................................................................................4 6. PIN DESCRIPTIONS..........................................................................................................................................................5 6.1. USB TRANSCEIVER INTERFACE ......................................................................................................................................5 6.2. EEPROM INTERFACE .....................................................................................................................................................5 6.3. POWER PINS ....................................................................................................................................................................5 6.4. LED INTERFACE..............................................................................................................................................................6 6.5. ATTACHMENT UNIT INTERFACE......................................................................................................................................6 RTL8225 RF Chipset..............................................................................................................................................6 RTL8255 RF Chipset..............................................................................................................................................7 6.6. CLOCK AND OTHER PINS.................................................................................................................................................8 7. CPU ACCESS TO ENDPOINT DATA..............................................................................................................................9 7.1. CONTROL TRANSFER.......................................................................................................................................................9 7.2. BULK TRANSFER .............................................................................................................................................................9 8. USB REQUEST..................................................................................................................................................................10 8.1. GET DESCRIPTOR-DEVICE.............................................................................................................................................10 8.2. GET DESCRIPTOR-DEVICE QUALIFIER (HIGH SPEED)....................................................................................................10 8.3. GET DESCRIPTOR-CONFIGURATION ..............................................................................................................................11 8.4. GET DESCRIPTOR-STRING INDEX 0 ...............................................................................................................................11 8.5. GET DESCRIPTOR-STRING INDEX 1 ...............................................................................................................................12 8.6. GET DESCRIPTOR-STRING INDEX 2 ...............................................................................................................................12 8.7. GET DESCRIPTOR-STRING INDEX 3 ...............................................................................................................................13 8.8. GET DESCRIPTOR-STRING INDEX 4 ...............................................................................................................................13 8.9. GET DESCRIPTOR-STRING INDEX 5 ...............................................................................................................................14 GET DESCRIPTOR-OTHER SPEED CONFIGURATION....................................................................................................14 8.10. 8.11. SET ADDRESS............................................................................................................................................................15 8.12. SET INTERFACE 0 ......................................................................................................................................................15 8.13. SET FEATURE DEVICE ...............................................................................................................................................15 CLEAR FEATURE DEVICE ..........................................................................................................................................16 8.14. 8.15. SET CONFIG 0............................................................................................................................................................16 8.16. SET CONFIG 1............................................................................................................................................................16 9. EEPROM (93C46 OR 93C56) CONTENTS....................................................................................................................17 9.1. EEPROM REGISTERS SUMMARY..................................................................................................................................20 9.2. EEPROM POWER MANAGEMENT REGISTERS SUMMARY .............................................................................................20 10. USB PACKET BUFFERING........................................................................................................................................21 TRANSMIT BUFFER MANAGER ..................................................................................................................................21 RECEIVE BUFFER MANAGER .....................................................................................................................................21 Wireless LAN Network Interface Controller iii Track ID: JATR-1076-21 Rev. 1.2 10.1. 10.2. 11. 11.1. 10.3. RTL8187L Datasheet PACKET RECOGNITION ..............................................................................................................................................21 FUNCTIONAL DESCRIPTION ..................................................................................................................................22 TRANSMIT & RECEIVE OPERATIONS..........................................................................................................................22 11.1.1. Transmit ...............................................................................................................................................................22 11.1.2. Receive .................................................................................................................................................................25 LOOPBACK OPERATION.............................................................................................................................................27 TX ENCAPSULATION (WITH RTL8187L INTERNAL BASEBAND PROCESSOR)............................................................27 RX DECAPSULATION (WITH RTL8187L INTERNAL BASEBAND PROCESSOR) ...........................................................27 LED FUNCTIONS .......................................................................................................................................................28 11.5.1. Link Monitor.........................................................................................................................................................28 Infrastructure Monitor .........................................................................................................................................28 11.5.2. 11.5.3. Rx LED .................................................................................................................................................................28 11.5.4. Tx LED .................................................................................................................................................................29 11.5.5. Tx/Rx LED ............................................................................................................................................................29 11.5.6. LINK/ACT LED ....................................................................................................................................................30 12. APPLICATION DIAGRAM.........................................................................................................................................31 11.2. 11.3. 11.4. 11.5. 13. 13.1. 13.2. 13.3. ELECTRICAL CHARACTERISTICS........................................................................................................................32 TEMPERATURE LIMIT RATINGS .................................................................................................................................32 DC CHARACTERISTICS ..............................................................................................................................................32 AC CHARACTERISTICS ..............................................................................................................................................33 13.3.1. Serial EEPROM Interface Timing (93C46(64*16)/93C56(128*16))...................................................................33 14. MECHANICAL DIMENSIONS...................................................................................................................................34 14.1. MECHANICAL DIMENSIONS NOTES............................................................................................................................35 15. ORDERING INFORMATION .....................................................................................................................................36 List of Tables TABLE 1. USB TRANSCEIVER INTERFACE .....................................................................................................................................5 TABLE 2. EEPROM INTERFACE ....................................................................................................................................................5 TABLE 3. POWER PINS ...................................................................................................................................................................5 TABLE 4. LED INTERFACE.............................................................................................................................................................6 TABLE 5. ATTACHMENT UNIT INTERFACE.....................................................................................................................................6 TABLE 6. RTL8255 RF CHIPSET....................................................................................................................................................7 TABLE 7. CLOCK AND OTHER PINS................................................................................................................................................8 TABLE 8. GET DESCRIPTOR-DEVICE............................................................................................................................................10 TABLE 9. GET DESCRIPTOR- DEVICE QUALIFIER (HIGH SPEED) ..................................................................................................10 TABLE 10. GET DESCRIPTOR-CONFIGURATION.............................................................................................................................11 TABLE 11. GET DESCRIPTOR-STRING INDEX 0..............................................................................................................................11 TABLE 12. GET DESCRIPTOR-STRING INDEX 1..............................................................................................................................12 TABLE 13. GET DESCRIPTOR-STRING INDEX 2..............................................................................................................................12 TABLE 14. GET DESCRIPTOR-STRING INDEX 3..............................................................................................................................13 TABLE 15. GET DESCRIPTOR-STRING INDEX 4..............................................................................................................................13 TABLE 16. GET DESCRIPTOR-STRING INDEX 5..............................................................................................................................14 TABLE 17. GET DESCRIPTOR-OTHER SPEED CONFIGURATION ......................................................................................................14 TABLE 18. SET ADDRESS ..............................................................................................................................................................15 TABLE 19. SET INTERFACE 0 .........................................................................................................................................................15 Wireless LAN Network Interface Controller iv Track ID: JATR-1076-21 Rev. 1.2 RTL8187L Datasheet TABLE 20. SET FEATURE DEVICE..................................................................................................................................................15 TABLE 21. CLEAR FEATURE DEVICE.............................................................................................................................................16 TABLE 22. SET CONFIG 0 ..............................................................................................................................................................16 TABLE 23. SET CONFIG 1 ..............................................................................................................................................................16 TABLE 24. EEPROM (93C46 OR 93C56) CONTENTS....................................................................................................................17 TABLE 25. EEPROM REGISTERS SUMMARY ................................................................................................................................20 TABLE 26. EEPROM POWER MANAGEMENT REGISTERS SUMMARY............................................................................................20 TABLE 27. TX DESCRIPTOR FORMAT ............................................................................................................................................22 TABLE 28. TX STATUS DESCRIPTOR..............................................................................................................................................23 TABLE 29. RX DESCRIPTOR FORMAT ............................................................................................................................................25 TABLE 30. RX STATUS DESCRIPTOR..............................................................................................................................................25 TABLE 31. TEMPERATURE LIMIT RATINGS....................................................................................................................................32 TABLE 32. DC CHARACTERISTICS.................................................................................................................................................32 TABLE 33. EEPROM ACCESS TIMING PARAMETERS ....................................................................................................................33 TABLE 34. ORDERING INFORMATION ............................................................................................................................................36 List of Figures FIGURE 1. BLOCK DIAGRAM..........................................................................................................................................................3 FIGURE 2. PIN ASSIGNMENTS.........................................................................................................................................................4 FIGURE 3. RX LED ......................................................................................................................................................................28 FIGURE 4. TX LED ......................................................................................................................................................................29 FIGURE 5. TX/RX LED ................................................................................................................................................................29 FIGURE 6. LINK/ACT LED.........................................................................................................................................................30 FIGURE 7. APPLICATION DIAGRAM..............................................................................................................................................31 FIGURE 8. SERIAL EEPROM INTERFACE TIMING........................................................................................................................33 Wireless LAN Network Interface Controller v Track ID: JATR-1076-21 Rev. 1.2 RTL8187L Datasheet 1. General Description The Realtek RTL8187L is a low-profile highly integrated cost-effective Wireless LAN USB 2.0 network interface controller that integrates a USB 2.0 PHY, SIE (Serial Interface Engine), 8051 MCU, a Wireless LAN MAC, and a Direct Sequence Spread Spectrum/OFDM baseband processor onto one chip. It provides USB high speed (480Mbps), and full speed (12Mbps), and supports 4 endpoints for transfer pipes. To reduce protocol overhead, the RTL8187L supports Short InterFrame Space (SIFS) burst mode to send packets back-to-back. A protection mechanism prevents collisions among 802.11b nodes. The RTL8187L fully complies with IEEE 802.11a/b/g specifications. Direct Sequence Spread Spectrum (DSSS), Complementary Code Keying (CCK), and Orthogonal Frequency Division Multiplexing (OFDM) baseband processing are implemented to support all IEEE 802.11a, 802.11b, and 802.11g data rates. Differential phase shift keying modulation schemes, DBPSK and DQPSK with data scrambling capability, are available, along with complementary code keying to provide data rates of 1, 2, 5.5, and 11Mbps, with long or short preamble. A high-speed Fast Fourier Transform

(FFT)/Inverse Fast Fourier Transform (IFFT), combined with BPSK, QPSK, 16QAM and 64QAM modulation of the individual sub-carriers, provides data rates of 6, 9, 12, 18, 24, 36, 48 and 54Mbps, with rate-compatible punctured convolutional coding with a coding rate of 1/2, 2/3, and 3/4. An enhanced signal detector, an adaptive frequency domain equalizer, and a soft-decision Viterbi decoder are built-in to alleviate severe multipath effects. Efficient IQ-imbalance calibration, DC offset, phase noise, frequency offset, and timing offset compensation reduce radio frequency front-end impairments. Selectable digital transmit and receiver FIR filters are provided to meet the requirements of transmit spectrum masks, and to reject adjacent channel interference, respectively. Both in the transmitter and receiver, programmable scaling in the digital domain trades the quantization noise against the increased probability of clipping. Robust signal detection, symbol boundary detection, and channel estimation perform well at the minimum sensitivity. The RTL8187L supports fast receiver Automatic Gain Control (AGC) and antenna diversity functions, and an adaptive transmit power control function to obtain better performance in the analog portions of the transceiver. It also has on-chip digital-to-analog converters and analog-to-digital converters for analog I and Q inputs and outputs, transmit TSSI and receiver RSSI inputs, and transmit and receiver AGC outputs. The RTL8187L is highly integrated and requires no glue logic or external memory. It keeps network maintenance costs low and eliminates usage barriers. Wireless LAN Network Interface Controller 1 Track ID JATR-1076-21 Rev. 1.2 2. Features

128-Pin LQFP and 128-pin LQFP Lead

(Pb)-Free package

State machine implementation without external memory (RAM, flash) requirement

Complies with IEEE 802.11a/b/g standards

Supports descriptor-based buffer management

Integrated Wireless LAN MAC and Direct Sequence Spread Spectrum/OFDM Baseband Processor in one chip

Enhanced signal detector, adaptive frequency domain equalizer, and soft-decision Viterbi decoder to alleviate severe multipath effects

Processing Gain compliant with FCC

On-Chip A/D and D/A converters for I/Q Data, AGC, and Adaptive Power Control

Supports both transmit and receive Antenna Diversity

Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54Mbps

Supports 40MHz OSC as the internal clock source. The frequency deviation of the OSC must be within 25 PPM on IEEE 802.11g and 20 PPM on IEEE 802.11a

IEEE 802.11g protection mechanisms for both RTS/CTS and CTS-to-self

Burst-mode support for dramatically enhanced throughput

DSSS with DBPSK and DQPSK, CCK modulations and demodulations supported with long and short preamble RTL8187L Datasheet

OFDM with BPSK, QPSK, 16QAM and 64QAM modulations and demodulations supported with rate compatible punctured convolutional coding with coding rate of 1/2, 2/3, and 3/4

Efficient IQ-imbalance calibration, DC offset, phase noise, frequency offset and timing offset compensation reduce analog front-end impairments

Selectable digital transmit and receiver FIR filters provided to meet transmit spectrum mask requirements and to reject adjacent channel interference

Programmable scaling both in transmitter and receiver to trade quantization noise against the increased probability of clipping

Fast receiver Automatic Gain Control (AGC)

& antenna diversity functions

Hardware-based IEEE 802.11i encryption/decryption engine, including 64-bit/128-bit WEP, TKIP, and AES

Supports Wi-Fi alliance WPA and WPA2 security

Contains two large independent transmit and receive FIFO buffers

Advanced power saving mode when the LAN and wakeup function are not used

Uses 93C46 (64*16-bit EEPROM) or 93C56

(128*16-bit EEPROM) to store resource configuration and ID parameter data

LED pins for various network activity indications

Two GPIO pins supported Wireless LAN Network Interface Controller 2 Track ID JATR-1076-21 Rev. 1.2

Supports digital loopback capability on both ports

Scatter and gather operation

Complies with USB Specification 2.0

Supports Full-speed (12Mbps) and High-speed (480Mbps)

Embedded standard 8051 CPU with enhanced features:

Four cycles per instruction

Variable clock speed cuts power consumption RTL8187L Datasheet

Supports 4 endpoints:

64-Byte buffer for control endpoint

512-Byte buffer for bulk IN endpoint

Two 512-Byte buffers for bulk OUT endpoint

3.3V and 1.8V power supplies required

5V tolerant I/Os

0.18m CMOS process 3. System Applications

USB Dongle WLAN adapter

Embedded WLAN solution in notebook, desktop, mobile phone, and motherboard Wireless LAN Network Interface Controller 3 Track ID JATR-1076-21 Rev. 1.2 4. Block Diagram RTL8187L Datasheet MAC D+

D-

EEPROM Interface LED Driver Serial Control Power and TX/RX Timing Control Logic Radio and Synthesizer Control h t g n e L e m a r F i r e t s g e R Interrupt Control Logic RTS, CTS, ACK Frame Generator r e t s i g e R

E I S WEP/

TKIP/

AES Engine Checksum Logic e p y T e m a r F r o t a n m i i r c s D i CCA/

NAV From BBP FIFO FIFO Control Logic Transmit/

Receive Logic Interface MAC/BBP Interface BBP, TX Section MAC/BBP Interface From MAC Scrambler Coding Digital Filter Register TX State Machine TX AGC Control BBP, RX Section Descrambler Decoding Clear Channel Assessment/

Signal Quality RX AGC Control MAC/BBP Interface To MAC From MAC DAC DAC DAC ADC ADC ADC DAC ADC TXI TXQ TXAGC TXDET RXI RXQ RXAGC RSSI Register RX State Machine Antenna Diversity Control Figure 1. Block Diagram ANTSEL ANTSELB Wireless LAN Network Interface Controller 3 Track ID JATR-1076-21 Rev. 1.2 5. Pin Assignments RTL8187L Datasheet Figure 2. Pin Assignments 5.1. Lead (Pb)-Free Package Identification Lead (Pb)-free package is indicated by an L in the location marked T in Figure 2. Wireless LAN Network Interface Controller 4 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet 6. Pin Descriptions In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In such cases, the functions are separated with a / symbol. Refer to the Pin Assignments diagram on page 4 for a graphical representation. The following signal type codes are used in the tables:

I: Input. O: Output T/S: Tri-State bi-directional input/output pin. 6.1. USB Transceiver Interface S/T/S: Sustained Tri-State. O/D: Open Drain. Table 1. USB Transceiver Interface Symbol HSDP HSDM FSDP FSDM RUP RREF Type I/O I/O I/O I/O N/A N/A Pin No 26 24 27 25 28 31 Description High speed USB D+ signal High speed USB D- signal Full speed USB D+ signal Full speed USB D- signal External pull-up resistor (1.5kW) for D+ line. External Reference. Requires 1% precision 6.25K resistor to ground 6.2. EEPROM Interface Symbol EESK EEDI EEDO EECS Type O O I/O O Pin No 51 39 36 47 6.3. Power Pins Table 2. EEPROM Interface Description EESK in 93C46 (93C56) programming or auto-load mode. EEDI in 93C46 (93C56) programming or auto-load mode. EEDO in 93C46 (93C56) programming or auto-load mode. EEPROM Chip Select. 93C46 (93C56) chip select. Table 3. Power Pins Symbol VDD33 AVDD VDD GND AGND Type P P P P P Pin No Description 40, 59, 78, 93, 111

+3.3V (Digital). 2, 9, 22, 29, 32, 127 +3.3V (Analog). 44, 53, 72, 82, 90, 96,

+1.8V. 105, 115 41, 45, 52, 60, 73, 80, 83, 91, 110 3, 10, 21, 23, 30, 123, 126, 128 Ground (Digital). Ground (Analog). Wireless LAN Network Interface Controller 5 Track ID JATR-1076-21 Rev. 1.2 6.4. LED Interface Table 4. LED Interface RTL8187L Datasheet Symbol LED0, 1 Type O Pin No Description 48, 56 LEDS1~0 LED0 LED1 LED Pins (Active low) 00 01 TX/RX Infrastructure TX/RX LINK 10 TX RX 11 LINK/ACT Infrastructure During power down mode, the LED signals are logic high. 6.5. Attachment Unit Interface 6.5.1. RTL8225 RF Chipset Symbol RIFSCK RIFSD RFLE CALEN CALMODE LNA_HL ANTSEL ANTSELB TRSW TRSWB VCOPDN A_PAPE B_PAPE RFTXEN RFRXEN GPIO0 GPIO1 GPIO2 GPIO3 Table 5. Attachment Unit Interface Pin No Description 57 61 58 77 108 88 87 95 104 103 49 85 107 102 113 67 68 69 70 Serial Clock Output. For the RTL8225 RF chipset, all operation mode switching and register setting is done via a 4-wire serial interface. Serial Data Input/Output. Serial Enable control. Serial Read/Write control. Receiver Output. I and Q channel AC coupling high-pass corner frequency selection. The output function of this pin is not used in the RTL8225 RF chipset. Not used in the RTL8225 RF chipset. Antenna Select. The antenna detects signal change states as the receiver switches from antenna to antenna during the acquisition process in antenna diversity mode. This is a complement for ANTSELB for differential drive of antenna switches. Antenna Select B. The antenna detects signal change states as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. This is a complement for ANTSEL for differential drive of antenna switches. Transmit/Receive path select. The TRSW select signal controls the direction of the Transmit/Receive switch. Output Pin as shutdown mode select digital input. 2.4GHz Transmit Power Amplifier Power Enable. Not used in the RTL8225 RF chipset. Not used in the RTL8225 RF chipset. Not used in the RTL8225 RF chipset. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. Type O I/O O O O O O O O O O O O O O O O O O Wireless LAN Network Interface Controller 6 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet Symbol GPIO4 GPIO5 VREFO VRP VRN RXIP RXIN RXQP RXQN RXAGC TXAGC RSSI TSSI0 TSSI1 TXQP TXQN TXIP TXIN TXQTP TXQTN TXITP TXITN Type O O X X X I I I I I O I I I I I O O O O O O Pin No Description 100 94 118 119 120 121 122 124 125 4 5 6 7 8 11 12 14 13 15 16 17 18 General purpose input/output pin. General purpose input/output pin. Not used in the RTL8225 RF chipset. Not used in the RTL8225 RF chipset. Not used in the RTL8225 RF chipset. Receive (Rx) In-phase Analog Data. Receive (Rx) Quadrature-phase Analog Data. Not used in the RTL8225 RF chipset. Not used in the RTL8225 RF chipset. Analog Input to the Receive Power A/D Converter for Receive AGC Control. Input to the Transmit Power A/D Converter for 2.4GHz Transmit AGC Control. Not used in the RTL8225 RF chipset. Not used in the RTL8225 RF chipset. Not used in the RTL8225 RF chipset. Transmit (TX) Quadrature-phase Analog Data. Transmit (TX) In-phase Analog Data. 6.5.2. RTL8255 RF Chipset Symbol RIFSCK Type O RIFSD RFLE CALEN CALMODE LNAHL ANTSEL ANTSELB TRSW TRSWB VCOPDN APAPE BPAPE O O X O O O O O O O O O Table 6. RTL8255 RF Chipset Pin No Description 57 61 58 77 108 88 87 95 104 103 49 85 107 Serial Clock Output. For the RTL8255 RF chipset, all operation mode switching and register setting is done via a 3-wire serial interface. Serial Data Input/Output. Serial Enable control. Not used in the RTL8255 RF chipset. Receiver Output. I and Q channel AC coupling high-pass corner frequency selection. The output function of this pin is not used in the RTL8255 RF chipset. Not used in the RTL8255 RF chipset. Antenna Select. The antenna detects signal change states as the receiver switches from antenna to antenna during the acquisition process in antenna diversity mode. Transmit/Receive path select. The TRSW select signal controls the direction of the Transmit/Receive switch. Not used in the RTL8255 RF chipset. 2.4GHz Transmit Power Amplifier Power Enable. 5GHz Transmit Power Amplifier Power Enable. Wireless LAN Network Interface Controller 7 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet Not used in the RTL8255 RF chipset. Not used in the RTL8255 RF chipset. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. General purpose input/output pin. Not used in the RTL8255 RF chipset. Not used in the RTL8255 RF chipset. Not used in the RTL8255 RF chipset. Receive (Rx) In-phase Analog Data. Symbol RFTXEN RFRXEN GPIO[0]

GPIO[1]

GPIO[2]

GPIO[3]

GPIO[4]

GPIO[5]

VREFO VRP VRN RXIP RXIN RXQP RXQN RXAGC TXAGC RSSI TSSI0 TSSI1 TXQP TXQN TXIP TXIN TXQTP TXQTN TXITP TXITN Type O O O O O O O O X X X I I I I O O I I I O O O O O O O O Pin No Description 102 113 67 68 69 70 100 94 118 119 120 121 122 124 125 4 5 6 7 8 11 12 14 13 15 16 17 18 Transmit (TX) In-phase Analog Data. Not used in the RTL8255 RF chipset. Not used in the RTL8255 RF chipset. Receive (Rx) Quadrature-phase Analog Data. Not used in the RTL8255 RF chipset. Not used in the RTL8255 RF chipset. Analog Input to the Receive Power A/D Converter for Receive AGC Control. Input to the Transmit Power A/D Converter for 2.4GHz Transmit AGC Control. Input to the Transmit Power A/D Converter for 5GHz Transmit AGC Control. Transmit (TX) Quadrature-phase Analog Data. 6.6. Clock and Other Pins Table 7. Clock and Other Pins Type I/O I Pin No 1 20 Description This pin must be pulled low by a 15K resistor. 40MHz OSC Input. Symbol R15K XI Wireless LAN Network Interface Controller 8 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet 7. CPU Access to Endpoint Data 7.1. Control Transfer Control transfers configure and send commands to a device. Because they are so important, they employ extensive USB error checking. The host reserves a portion of each USB frame for control transfers. Control transfers consist of two or three stages. The SETUP stage contains eight bytes of USB control data. An optional DATA stage contains more data, if required. The STATUS stage allows the device to indicate successful completion of a control operation. 7.2. Bulk Transfer Bulk data is bursty, traveling in packets of 8, 16, 32, or 64 bytes at full speed, or at 512 bytes at high speed. Bulk data has guaranteed accuracy due to an automatic retry mechanism for erroneous data. The host schedules bulk packets when there is available bus time. Wireless LAN Network Interface Controller 9 Track ID JATR-1076-21 Rev. 1.2 8. USB Request 8.1. Get Descriptor-Device RTL8187L Datasheet Setup Transaction bReq 06 BmReq 80 Table 8. Get Descriptor-Device wValueL wValueH wIndexL wIndexH 00 01 00 00 wLengthL Lengh_L wLengthH Length_H High Speed Data Transaction DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 12 DA 03 01 0B 01 00 87 02 81 00 00 00 01 00 01 40 02 Full Speed Data Transaction DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 12 DA 03 01 0B 01 10 87 01 81 00 00 00 01 00 01 40 02 8.2. Get Descriptor-Device Qualifier (High Speed) Table 9. Get Descriptor- Device Qualifier (High Speed) Setup Transaction bReq 06 BmReq 80 Data Transaction DATA0 DATA1 wValueL wValueH wIndexL wIndexH 00 06 00 00 wLengthL Lengh_L wLengthH Length_H DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 0A 01 06 00 00 02 00 00 00 40 Wireless LAN Network Interface Controller 10 Track ID JATR-1076-21 Rev. 1.2 8.3. Get Descriptor-Configuration Table 10. Get Descriptor-Configuration RTL8187L Datasheet Setup Transaction bReq 06 BmReq 80 wValueL wValueH wIndexL wIndexH 00 02 00 00 wLengthL Lengh_L wLengthH Length_H High Speed Data Transaction DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 09 FA 00 00 07 02 09 05 07 05 27 04 07 05 03 00 00 05 02 02 01 00 81 02 00 01 03 02 00 02 04 00 00 02 00 80 00 02 00 Full Speed Data Transaction DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 09 01 00 00 07 02 09 05 07 05 27 04 07 05 03 00 00 05 02 02 01 00 81 02 40 01 03 02 40 00 00 00 40 00 00 E0 00 00 00 8.4. Get Descriptor-String Index 0 Table 11. Get Descriptor-String Index 0 Setup Transaction bReq 06 BmReq 80 Data Transaction DATA0 DATA1 04 03 wValueL wValueH wIndexL wIndexH 00 03 00 00 wLengthL Lengh_L wLengthH Length_H DATA2 09 DATA3 04 DATA4 DATA5 DATA6 DATA7

Wireless LAN Network Interface Controller 11 Track ID JATR-1076-21 Rev. 1.2 8.5. Get Descriptor-String Index 1 Table 12. Get Descriptor-String Index 1 RTL8187L Datasheet Setup Transaction bReq 06 BmReq 80 Data Transaction DATA0 DATA1 wValueL wValueH wIndexL wIndexH 01 03 09 04 wLengthL Lengh_L wLengthH Length_H DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 10 6C 03 00 52 74 00 00 65 65 00 00 61 6B 00 00 8.6. Get Descriptor-String Index 2 Table 13. Get Descriptor-String Index 2 Setup Transaction bReq 06 BmReq 80 Data Transaction DATA0 DATA1 wValueL wValueH wIndexL wIndexH 02 03 09 04 wLengthL Lengh_L wLengthH Length_H DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 3A 38 20 65 73 4E 61 72 03 00 00 00 00 00 00 00 52 31 57 6C 20 20 70 00 00 00 00 00 00 00 54 38 59 65 4C 41 74 00 00 00 00 00 00 00 4C 37 72 73 41 64 65 00 00 00 00 00 00 00 Wireless LAN Network Interface Controller 12 Track ID JATR-1076-21 Rev. 1.2 8.7. Get Descriptor-String Index 3 Table 14. Get Descriptor-String Index 3 RTL8187L Datasheet Setup Transaction bReq 06 BmReq 80 Data Transaction DATA0 DATA1 wValueL wValueH wIndexL wIndexH 03 03 09 04 wLengthL Lengh_L wLengthH Length_H DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 1A 30 30 31 03 00 00 00 30 34 30 00 00 00 30 63 30 00 00 00 65 30 30 00 00 00 8.8. Get Descriptor-String Index 4 Table 15. Get Descriptor-String Index 4 Setup Transaction bReq 06 BmReq 80 Data Transaction DATA0 DATA1 wValueL wValueH wIndexL wIndexH 04 03 09 04 wLengthL Lengh_L wLengthH Length_H DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 2C 65 73 74 6B 72 03 00 00 00 00 00 57 6C 20 77 20 64 00 00 00 00 00 00 69 65 4E 6F 43 00 00 00 00 00 72 73 65 72 61 00 00 00 00 00 Wireless LAN Network Interface Controller 13 Track ID JATR-1076-21 Rev. 1.2 8.9. Get Descriptor-String Index 5 Table 16. Get Descriptor-String Index 5 RTL8187L Datasheet Setup Transaction bReq 06 BmReq 80 Data Transaction DATA0 DATA1 wValueL wValueH wIndexL wIndexH 05 03 09 04 wLengthL Lengh_L wLengthH Length_H DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 34 6B 2C 6B 54 6C 55 03 00 00 00 00 00 00 42 2D 42 2D 2C 6B 54 00 00 00 00 00 00 00 75 49 75 4F 42 2D 00 00 00 00 00 00 6C 4E 6C 55 75 4F 00 00 00 00 00 00 8.10. Get Descriptor-Other Speed Configuration Table 17. Get Descriptor-Other Speed Configuration Setup Transaction bReq 06 BmReq 80 wValueL wValueH wIndexL wIndexH 00 07 00 00 wLengthL Lengh_L wLengthH Length_H High Speed Data Transaction DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 09 FA 00 00 07 02 09 05 07 05 27 04 07 05 03 00 00 05 02 02 01 00 81 02 00 01 03 02 00 02 04 00 00 02 00 80 00 02 00 Full Speed Data Transaction DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 09 01 00 00 07 02 09 05 07 05 27 04 07 05 03 00 00 05 02 02 01 00 81 02 40 01 03 02 40 00 00 00 40 00 00 E0 00 00 00 Wireless LAN Network Interface Controller 14 Track ID JATR-1076-21 Rev. 1.2 8.11. Set Address RTL8187L Datasheet Setup Transaction bReq 05 BmReq 00 Table 18. Set Address wValueL addrL wValueH addrH wIndexL wIndexH wLengthL wLengthH 00 00 00 00 Note: No data transaction. 8.12. Set Interface 0 Setup Transaction bReq 0B BmReq 01 Table 19. Set Interface 0 wValueL wValueH wIndexL wIndexH wLengthL wLengthH 00 00 00 00 00 00 Note: No data transaction. 8.13. Set Feature Device Setup Transaction bReq 03 BmReq 00 Table 20. Set Feature Device wValueL wValueH wIndexL wIndexH wLengthL wLengthH 01 00 00 00 00 00 Note: No data transaction. Wireless LAN Network Interface Controller 15 Track ID JATR-1076-21 Rev. 1.2 8.14. Clear Feature Device Table 21. Clear Feature Device RTL8187L Datasheet Setup Transaction bReq 01 BmReq 00 wValueL wValueH wIndexL wIndexH wLengthL wLengthH 01 00 00 00 00 00 Note: No data transaction. 8.15. Set Config 0 Setup Transaction bReq 09 BmReq 00 Table 22. Set Config 0 wValueL wValueH wIndexL wIndexH wLengthL wLengthH 00 02 00 00 00 00 Note: No data transaction. 8.16. Set Config 1 Setup Transaction bReq 09 BmReq 00 Table 23. Set Config 1 wValueL wValueH wIndexL wIndexH wLengthL wLengthH 01 00 00 00 00 00 Note: No data transaction. Wireless LAN Network Interface Controller 16 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet 9. EEPROM (93C46 or 93C56) Contents The RTL8187L supports the attachment of an external EEPROM. The 93C46 is a 1Kbit EEPROM (the 93C56 is a 2Kbit EEPROM). The EEPROM interface provides the ability for the RTL8187L to read from, and write data to, an external serial EEPROM device. If the EEPROM is not present, the RTL8187L initialization uses default values for the Operational Registers. Software can read and write to the EEPROM using bit-bang accesses via the 9346CR Register. Although it is actually addressed by words, its contents are listed below by bytes for convenience. After the initial power on or auto-load command in the 9346CR, the RTL8187L performs a series of EEPROM read operations from the 93C46 (93C56). Note: It is suggested to obtain Realtek approval before changing the default settings of the EEPROM. Bytes 00h 01h 02h-03h 04h-05h 06h 07h 08h 09h-0Ah 0Bh Table 24. EEPROM (93C46 or 93C56) Contents Contents 87h 81h VID DID ChannelPlan EnergyDetThr RFParm Version Description These 2 bytes contain the ID code word for the RTL8187L. The RTL8187L will load the contents of the EEPROM into the corresponding location if the ID word (8187h) is correct. USB Vendor ID. USB Device ID. Channel Plan: Map of channels to be scanned. Energy detection threshold. RF specific parameter. The version of EEPROM content. Options function Bit0: Timeout function. 0: Disable RTL8187Ls USB timeout mechanism. 1: Enable RTL8187Ls USB timeout mechanism. Bit1: USB remote wake up function. 0: There is no remote wake up feature for the RTL8187L. 1: There is a remote wake up feature for the RTL8187L. Bit2:

0: The RTL8187Ls remote wake-up is based on the WLANs wake-up signal 1: The RTL8187Ls remote wake-up is push-button based. Bit3: USB Status stage. 1: Bypass the check setup interrupt procedure of 8051 when host sends set_address command. Bit4: SelfloopbackISR function. 1: The UTM self loopback will be initialized by internal 8051. Bit7:

1: The power control signal to AFE will be auto controlled by suspendm. RF Chip ID. The identifier of the RF chip. 0Ch RFChipID Wireless LAN Network Interface Controller 17 Track ID JATR-1076-21 Rev. 1.2 Contents CONFIG3 Description RTL8187L Configuration register 3. Operational register FF59h. RTL8187L Datasheet MAC Address MAC Address. Bytes 0Dh 0Eh~13h 14h 15h 16h~17h 18h 19h

CONFIG1 CRC CONFIG2 CONFIG4 1Ah~1Dh ANA_PARM 1Eh TESTR 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch

OFDM_TxPower 1 OFDM_TxPower 2 OFDM_TxPower 3 OFDM_TxPower 4 OFDM_TxPower 5 OFDM_TxPower 6 OFDM_TxPower 7 OFDM_TxPower 8 OFDM_TxPower 9 OFDM_TxPower 10 OFDM_TxPower 11 OFDM_TxPower 12 After the auto-load command or a hardware reset, the RTL8187L loads MAC Addresses to IDR0~IDR5 of the I/O registers of the RTL8187L. Reserved. RTL8187L Configuration register 1. Operational register FF52h. 16-bit CRC value of EEPROM content. RTL8187L Configuration register 2. Operational register FF53h. RTL8187L Configuration register 4. Operational register FF5Ah. Analog Parameter for the RTL8187L. Operational registers of the RTL8187L are from FF54h to FF57h. Reserved. Do not change this field without Realtek approval. RTL8187L Test Mode Register. Operational register FF5Bh. Reserved. Do not change this field without Realtek approval. Reserved. Transmit Power Level for 802.11a-defined channel_ID 36

(Center frequency=5180MHz). Transmit Power Level for 802.11a-defined channel_ID 40

(Center frequency=5200MHz). Transmit Power Level for 802.11a-defined channel_ID 44

(Center frequency=5220MHz). Transmit Power Level for 802.11a-defined channel_ID 48

(Center frequency=5240MHz). Transmit Power Level for 802.11a-defined channel_ID 52

(Center frequency=5260MHz). Transmit Power Level for 802.11a-defined channel_ID 56

(Center frequency=5280MHz). Transmit Power Level for 802.11a-defined channel_ID 60

(Center frequency=5300MHz). Transmit Power Level for 802.11a-defined channel_ID 64

(Center frequency=5320MHz). Transmit Power Level for 802.11a-defined channel_ID 149

(Center frequency=5745MHz). Transmit Power Level for 802.11a-defined channel_ID 153

(Center frequency=5765MHz). Transmit Power Level for 802.11a-defined channel_ID 157

(Center frequency=5785MHz). Transmit Power Level for 802.11a-defined channel_ID 161

(Center frequency=5805MHz). CCK_TxPower1 Transmit Power Level for 802.11b(g)-defined channel_ID 1

(center frequency=2412MHz). Wireless LAN Network Interface Controller 18 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet Contents Description CCK_TxPower2 Transmit Power Level for 802.11b(g)-defined channel_ID 2

(center frequency=2417MHz). CCK_TxPower3 Transmit Power Level for 802.11b(g)-defined channel_ID 3

(center frequency=2422MHz). CCK_TxPower4 Transmit Power Level for 802.11b(g)-defined channel_ID 4

(center frequency=2427MHz). CCK_TxPower5 Transmit Power Level for 802.11b(g)-defined channel_ID 5

(center frequency=2432MHz). CCK_TxPower6 Transmit Power Level for 802.11b(g)-defined channel_ID 6

(center frequency=2437MHz). ANA_PARM2 Reserved: Do not change this field without Realtek approval. Analog Parameter1 for the RTL8187L: Operational registers of the RTL8187L are from FF60h to FF63h. CCK_TxPower11 Transmit Power Level for 802.11b(g)-defined channel_ID 11

(center frequency=2462MHz). CCK_TxPower12 Transmit Power Level for 802.11b(g)-defined channel_ID 12

(center frequency=2467MHz). CCK_TxPower13 Transmit Power Level for 802.11b(g)-defined channel_ID 13

(center frequency=2472MHz). CCK_TxPower14 Transmit Power Level for 802.11b(g)-defined channel_ID 14 Bytes 2Dh 2Eh 2Fh 30h 31h 32h-35h 36h 37h 38h 39h 3Ah-6Bh Manufacture String

(center frequency=2484MHz). Manufacture String and Product String:Those bits specify both manufacturers information and devices information for the USB standard request. Maximum two strings total length are 50 bytes. Reserved. Product String

6Ch-79h 7Ah 7Bh 7Ch 7Dh CCK_TxPower7 Transmit Power Level for 802.11b(g)-defined channel_ID 7

(center frequency=2442MHz). CCK_TxPower8 Transmit Power Level for 802.11b(g)-defined channel_ID 8

(center frequency=2447MHz). CCK_TxPower9 Transmit Power Level for 802.11b(g)-defined channel_ID 9

(center frequency=2452MHz). CCK_TxPower10 Transmit Power Level for 802.11b(g)-defined channel_ID 10

(center frequency=2457MHz). Wireless LAN Network Interface Controller 19 Track ID JATR-1076-21 Rev. 1.2 9.1. EEPROM Registers Summary Name Type Table 25. EEPROM Registers Summary Bit7 Bit6 Bit5 Bit4 Bit3 IDR0 IDR5 R/W*

Address FF00h-

FF05h FF52h CONFIG1 FF53h CONFIG2 R W*

R W*

FF54h-

FF57h ANA_PARM R/W**

FF59h CONFIG3 FF5Ah CONFIG4 R W*

R W*

LEDS1 LEDS1 LCK

LEDS0 LEDS0

LWACT LWACT

32-bit Read Write PARM_En Magic PARM_En Magic

LWPME LWPME 8-bit Read Write 32-bit Read Write TESTR FF5Bh FF60h-

FF63h ANA_PARM2 R/W CONFIG5 R/W**

FFD8h

Note 1: Registers marked 'W*' can be written only if bits EEM1=EEM0=1. Note 2: Registers marked 'W**' can be written only if bits EEM1:0=[1:1] and CONFIG3<PARM_EN>= 0.

RTL8187L Datasheet Bit2 Bit1 Bit0

PAPE _sign PAPE _sign

LWPTN LWPTN

PAPE _time PAPE _time

LANWake

9.2. EEPROM Power Management Registers Summary Table 26. EEPROM Power Management Registers Summary Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Configuration Space Offset 52h 53h PMC R R Aux_I_b1 Aux_I_b0 PME_D3cold PME_D3hot PME_D2 PME_D1 PME_D0 D2 DSI Reserved PMECLK Version D1 Aux_I_b2 Wireless LAN Network Interface Controller 20 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet 10. USB Packet Buffering The RTL8187L incorporates two independent FIFOs for transferring data to/from the system interface and from/to the network. The FIFOs provide temporary storage of data, freeing the host system from the real-time demands of the network. The way in which the FIFOs are emptied and filled is controlled by the FIFO threshold values in the Receive Configuration registers. These values determine how full or empty the FIFOs must be before the device requests the bus. Once the RTL8187L requests the bus, it will attempt to empty or fill the FIFOs as allowed by the respective MXDMA settings in the Transmit Configuration and Receive Configuration registers. 10.1. Transmit Buffer Manager The buffer management scheme used on the RTL8187L allows quick, simple, and efficient use of the frame buffer memory. The buffer management scheme uses separate buffers and descriptors for packet information. This allows effective transfers of data to the transmit buffer manager by simply transferring the descriptor information to the transmit queue. The Tx Buffer Manager DMAs packet data from system memory and places it in the 3.5KB transmit FIFO, and pulls data from the FIFO to send to the Tx MAC. Multiple packets may be present in the FIFO, allowing packets to be transmitted with Short InterFrame (SIF) space. Additionally, once the RTL8187L requests the bus, it will attempt to fill the FIFO as allowed by the MXDMA setting. The Tx Buffer Manager process also supports priority queuing of transmit packets. It handles this by drawing from two separate descriptor lists to fill the internal FIFO. If packets are available in the high priority queues, they will be loaded into the FIFO before those of low priority. 10.2. Receive Buffer Manager The Rx Buffer Manager uses the same buffer management scheme as used for transmits. The Rx Buffer Manager retrieves packet data from the Rx MAC and places it in the 4KB receive data FIFO, and pulls data from the FIFO for DMA to system memory. The receive FIFO is controlled by the FIFO threshold value in RXFTH. This value determines the number of long words written into the FIFO from the MAC unit before a DMA request for system memory occurs. Once the RTL8187L gets the bus, it will continue to transfer the long words from the FIFO until the data in the FIFO is less than one long word, or has reached the end of the packet, or the max DMA burst size is reached, as set in MXDMA. 10.3. Packet Recognition The Rx packet filter and recognition logic allows software to control which packets are accepted, based on destination address and packet type. Address recognition logic includes support for broadcast, multicast hash, and unicast addresses. The packet recognition logic includes support for WOL and programmable pattern recognition. Wireless LAN Network Interface Controller 21 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet 11. Functional Description 11.1. Transmit & Receive Operations The RTL8187L supports a new descriptor-based buffer management that will significantly lower host CPU utilization. The RTL8187L supports transmit descriptor and receive descriptor in memory. Each OUT packet contains 3-double-word transmit descriptors and each IN packet contains 4-double-word receive descriptors. 11.1.1. Transmit Tx Descriptor Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 27. Tx Descriptor Format RSVD TXRATE

(4 bits) R T S E N RTSRATE

(4 bits) RSVD TPKTSIZE (12 bits) S P L C P C T S E N M O R E F R A G N O _ E N C R Y P T Offset 0 L E N G E X T RATE_ FALL BACK_ LIMIT

(4 bits) Length (15 bits) RTSDUR (16 bits) Offset 4 AGC (8 bits) RETRY_LIMIT (8 bits) CWMAX

(4 bits) CWMIN

(4 bits) Offset 8 R S V D

(3 bits) A N T E N N A Wireless LAN Network Interface Controller 22 Track ID JATR-1076-21 Rev. 1.2 Offset#

0 0 Bit#

31:28 27:24 Symbol RSVD TXRATE 0 0 23 RTSEN 22:19 RTSRATE Bit 25 Bit 26 Bit 27 Table 28. Tx Status Descriptor Description Reserved. Tx Rate. These four bits indicate the current frames transmission rate. 1Mbps 2Mbps 5.5Mbps 11Mbps 6Mbps 9Mbps 12Mbps 18Mbps 24Mbps 36Mbps 48Mbps 54Mbps Reserved All other combinations 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 RTL8187L Datasheet Bit 24 0 1 0 1 0 1 0 1 0 1 0 1 Bit 20 Bit 21 Bit 22 RTS Enable. Set to 1 indicates that an RTS/CTS handshake shall be performed at the beginning of any frame exchange sequence where the frame is of type Data or Management, the frame has a unicast address in the Address1 field, and the length of the frame is greater than RTSThreshold. RTS Rate. These four bits indicate the RTS frames transmission rate before transmitting the current frame and will be ignored if the RTSEN bit is set to 0. 1Mbps 2Mbps 5.5Mbps 11Mbps 6Mbps 9Mbps 12Mbps 18Mbps 24Mbps 36Mbps 48Mbps 54Mbps Reserved All other combinations 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit 19 0 18 CTSEN CTS Enable. Both RTSEN and CTSEN set to 1 indicates that the CTS-to-Self protection mechanism will be used. Wireless LAN Network Interface Controller 23 Track ID JATR-1076-21 Rev. 1.2 Symbol Description RTL8187L Datasheet MOREFRAG More Fragment. SPLCP This bit is set to 1 in all data type frames that have another fragment of the current packet to follow. Short Physical Layer Convergence Protocol format. When set, this bit indicates that a short PLCP preamble will be added to the header before transmitting the frame. NO_ENCRYPT No Encryption. Bit#

17 16 15 14:12 11:0 RSVD TPKTSIZE 31 LENGEXT 30:16 Length 15:0 RTSDUR This packet will be sent out without encryption even if Tx encryption is enabled. Reserved. Transmit Packet Size. This field indicates the number of bytes required to transmit the frame. Length Extension. This bit is used to supplement the Length field (bits 30:16, offset 4). This bit will be ignored if the TXRATE is set to 1Mbps, 2Mbps, or 5.5Mbps. PLCP Length. The PLCP length field indicates the number of microseconds required to transmit the frame. RTS Duration. These bits indicate the RTS frames duration field before transmitting the current frame and will be ignored if the RTSEN bit is set to 0. Data Rate Auto Fallback Limit. 31:28 27:25 24 23:16 15:8 7:4 3:0 RATE_FALL BACK_LIMIT RSVD ANTENNA AGC Reserved. Tx Antenna. Tx AGC. RETRY_LIMIT Retry Count Limit. CWMAX CWMIN Maximum Contention Window. Minimum Contention Window. Offset#

0 0 0 0 0 4 4 4 8 8 8 8 8 8 8 Wireless LAN Network Interface Controller 24 Track ID JATR-1076-21 Rev. 1.2 11.1.2. Receive Rx Descriptor Format RTL8187L Datasheet 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 29. Rx Descriptor Format RSVD D M A F F O V F RSVD (6 bits) S P L C P W A K E U P R S V D D E C R Y P T E D RXRATE

(4 bits) R S V D M A R P A M B A R R E S I C V C R C 3 2 P W R M G T Frame_Length (12 bits) RSSI

(7 bits) SQ

(8 bits) AGC (8 bits) A N T E N N A TSFTL TSFTH Offset 0 Offset 4 Offset 8 Offset 12 Offset#

0 0 0 0 0 Bit#

31:28 27 26 25 24 Symbol RSVD DMAF FOVF SPLCP RSVD Table 30. Rx Status Descriptor Description Reserved. RX DMA Fail. When set, this packet will be dropped by software. FIFO Overflow. When set, this bit indicates that the receive FIFO was exhausted before this packet was fully received. Short Physical Layer Convergence Protocol format. When set, this bit indicates that a short PLCP preamble was added to the current received frame. Reserved. Wireless LAN Network Interface Controller 25 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet Bit 20 Bit 22 Bit 23 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1Mbps 2Mbps 5.5Mbps 11Mbps 6Mbps 9Mbps 12Mbps 18Mbps 24Mbps 36Mbps 48Mbps 54Mbps Reserved Description Rx Rate. These four bits indicate the current frames receiving rate. Bit 21 Reserved. Multicast Address Packet Received. When set, this bit indicates that a multicast packet was received. Physical Address Matched. When set, this bit indicates that the destination address of this Rx packet matches the value in the RTL8187Ls ID registers. Broadcast Address Received. When set, this bit indicates that a broadcast packet was received. BAR and MAR will not be set simultaneously. Receive Error. Valid if DMAF=0 Receive Power Management Packet. When set, this bit indicates that the Power Management bit is set on the received packet. CRC32 Error. When set, this bit indicates that a CRC32 error has occurred on the received packet. A CRC32 packet can be received only when RCR_ACRC32 is set. Integrity Check Value Error. When set, this bit indicates that an ICV error has occurred on the received packet. A ICV packet can be received only when RCR_AICV is set. All other combinations Offset#

0 Bit#

23:20 Symbol RXRATE RSVD MAR PAM BAR RES PWRMGT CRC32 ICV 0 0 0 0 0 0 0 0 0 4 4 4 4 4 4 19 18 17 16 15 14 13 12 11:0 31:26 25 24 23:16 15 14:8 Frame_Length This bit indicates the received packet length including CRC32, in bytes. RSVD WAKEUP Reserved. The received packet is a unicast wakeup packet. DECRYPTED The received packet has been decrypted. AGC ANTENNA RSSI The AGC of the received packet. The received packet is received through this antenna. Received Signal Strength Indicator. The RSSI is a measure of the RF energy received by the PHY. Wireless LAN Network Interface Controller 26 Track ID JATR-1076-21 Rev. 1.2 Offset#

4 Bit#

7:0 Symbol SQ 8 12 31:0 31:0 TSFTL TSFTH RTL8187L Datasheet Description Signal Quality. The SQ is a measure of the quality of BAKER code lock, providing an effective measure during the full reception of a PLCP preamble and header. A snapshot of the TSFTRs least significant 32 bits. A snapshot of the TSFTRs most significant 32 bits. 11.2. Loopback Operation Loopback mode is normally used to verify that the logic operations have performed correctly. In loopback mode, the RTL8187L takes frames from the transmit descriptor and transmits them up to internal Rx logic. The loopback function does not apply to an external PHYceiver. 11.3. Tx Encapsulation (With RTL8187L Internal Baseband Processor) While operating in Tx mode, the RTL8187L encapsulates the frames that it transmits according to the Differential Binary Phase Shift Keying (DBPSK) for 1Mbps, Differential Quaternary Phase Shift Keying

(DQPSK) for 2Mbps, and Complementary Code Keying (CCK) for 5.5Mbps and 11Mbps modulators. The changes to the original packet data are as follows:

1. The PLCP preamble is always transmitted as the DBPSK waveform and used by the receiver to achieve initial PN synchronization. 2. The PLCP header can be configured to be either DBPSK or DQPSK and includes the necessary data fields of the communications protocol to establish the physical layer link. 3. The MAC frame can be configured for DBPSK, DQPSK, or CCK. 11.4. Rx Decapsulation (With RTL8187L Internal Baseband Processor) The RTL8187L continuously monitors the network when reception is enabled. When activity is recognized it starts to process the incoming data. After detecting receive activity on the channel, the RTL8187L starts to process the PLCP preamble and header based on the mode of operation. The RTL8187L checks CRC16 and CRC32, then reports if CRC16 or CRC32 has errors. When using the 40-bit WEP and 104-bit WEP module for decryption, the RTL8187L also checks the Integrity Check Value

(ICV) and reports if the ICV has errors. Wireless LAN Network Interface Controller 27 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet 11.5. LED Functions The RTL8187L supports 2 LED signals in 4 configurable operation modes. The following sections describe the different LED actions. 11.5.1. Link Monitor The Link Monitor senses the link integrity. Whenever link status is established, the specific link LED pin is driven low. 11.5.2. Infrastructure Monitor The Infrastructure Monitor senses the link integrity of an Infrastructure network. Whenever Link OK in Infrastructure network status is established, the specific Infrastructure LED pin is driven low. 11.5.3. Rx LED Blinking of the Rx LED indicates that receive activity is occurring. Power On LED = High Receiving Packet?

No Yes LED = High for (100 +- 10) ms LED = Low for (12 +- 2) ms Figure 3. Rx LED Wireless LAN Network Interface Controller 28 Track ID JATR-1076-21 Rev. 1.2 11.5.4. Tx LED Blinking of the Tx LED indicates that transmit activity is occurring. RTL8187L Datasheet Power On LED = High Transmitting Packet?

No Yes LED = High for (100 +- 10) ms LED = Low for (12 +- 2) ms Figure 4. Tx LED 11.5.5. Tx/Rx LED Blinking of the Tx/Rx LED indicates that both transmit and receive activity is occurring. Power On LED = High Tx/Rx Packet?

No Yes LED = High for (100 +- 10) ms LED = Low for (12 +- 2) ms Figure 5. Tx/Rx LED Wireless LAN Network Interface Controller 29 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet 11.5.6. LINK/ACT LED Blinking of the LINK/ACT LED indicates that the RTL8187L is linked and operating properly. If this LED is high for extended periods it indicates that a link problem exists. Power On LED = High Link?

No Yes LED = Low No Tx/Rx packet?

Yes LED = High for (100 +- 10) ms LED = Low for (12 +- 2) ms Figure 6. LINK/ACT LED Wireless LAN Network Interface Controller 30 Track ID JATR-1076-21 Rev. 1.2 12. Application Diagram RTL8187L Datasheet Main/Aux. Power Regulators Power 3.3V, 1.8V Power 3.3V, 1.8V LED Power 3.3V, 1.8V RTL8187L External ROM/RAM Antenna External RF Devices Base Band MAC SIE D+

D-

40MHz Clock Figure 7. Application Diagram EEPROM Power 3.3V Wireless LAN Network Interface Controller 31 Track ID JATR-1076-21 Rev. 1.2 13. Electrical Characteristics 13.1. Temperature Limit Ratings RTL8187L Datasheet Parameter Storage temperature Operating temperature Table 31. Temperature Limit Ratings Minimum Maximum

-55

-10

+125 70 Units C C 13.2. DC Characteristics Table 32. DC Characteristics Symbol VDD33 VDD18 Voh Vol Vih Vil Iin Ioz Icc Conditions Ioh = -8mA Parameter 3.3V Supply Voltage 1.8V Supply Voltage Minimum High Level Output Voltage Maximum Low Level Output Voltage Minimum High Level Input Voltage Maximum Low Level Input Voltage Input Current Vin =Vcc or GND Tri-State Output Leakage Current Vout =Vcc or GND Average Operating Supply Current Iol = 8mA Iout = 0mA, Minimum Typical Maximum Units 3.0 1.7 0.9 * Vcc 0.5 * Vcc

-0.5

-1.0

-10 3.3 1.8 3.6 1.9 Vcc 0.1 * Vcc Vcc+0.5 0.3 * Vcc 1.0 10 460 V V V V V V A A mA Wireless LAN Network Interface Controller 32 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet 13.3. AC Characteristics 13.3.1. Serial EEPROM Interface Timing (93C46(64*16)/93C56(128*16)) EESK EECS EEDI

(Read) 1 1 0 An A2 A1 A0 EEDO

(Read) High Impedance EESK EECS EEDI

(Write) 1 0 1 An

... A0 Dn

... D0 tcs 0 Dn D1 D0 tcs BUSY READY twp EEDO

(Write) High Impedance EESK EECS EEDI EEDO

(Read) EEDO

(Program) tcss tdis tsv tsk tskh tdih tskl tdos tcsh tdoh STATUS VALID Figure 8. Serial EEPROM Interface Timing Table 33. EEPROM Access Timing Parameters Symbol Parameter tcs twp tsk tskh tskl tcss tcsh tdis tdih tdos tdoh tsv Minimum CS Low Time Write Cycle Time SK Clock Cycle Time SK High Time SK Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time DO Setup Time DO Hold Time CS to Status Valid 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 9346/9356 Minimum 1000/250 4/1 1000/500 1000/250 200/50 0/0 400/50 400/100 2000/500 Typical Maximum Units 10/10 2000/500 1000/500 ns ms s ns ns ns ns ns ns ns ns ns Wireless LAN Network Interface Controller 33 Track ID JATR-1076-21 Rev. 1.2 14. Mechanical Dimensions RTL8187L Datasheet See the Mechanical Dimensions notes on the next page. Wireless LAN Network Interface Controller 34 Track ID JATR-1076-21 Rev. 1.2 RTL8187L Datasheet

0.063 Symbol Dimension in inch Dimension in mm Min Typical Max Min Typical Max 1.60 14.1. Mechanical Dimensions Notes Note:

1.Dimension b does not include dambar protrusion/intrusion. 2.Controlling dimension: Millimeter 3.General appearance spec. should be based on final visual inspection spec. TITLE: 128LD LQFP ( 14x14x1.4 mm*2 ) PACKAGE OUTLINE

-CU L/F, FOOTPRINT 2.0 mm LEADFRAME MATERIAL:

APPROVE CHECK DWG NO. LQ128 - 2 DATE MAY. 13.2002 REALTEK SEMICONDUCTOR CORP. DOC. NO. 530-ASS-P004 VERSION 1 A A1 A2 b c D D1 e E E1 L L1 PAGE 0.05 1.35 0.13 0.09 15.85 13.90 0.002 0.053 0.005 0.004 0.624 0.547 0.057 0.009 0.006 0.636 0.555 1.45 0.23 0.20 16.15 14.10 16.00 14.00 0.60 0.636 0.555 0.030 0.630 0.551 0.024 15.85 13.90 0.45 0.624 0.547 0.018 16.15 14.10 0.75 16.00 14.00 0.630 0.551 0.055 0.007 0.016 BSC 0.039 REF 0.40 BSC 1.40 0.18 1.00 REF 3.5 3.5 OF 7 0 0 7

Wireless LAN Network Interface Controller 35 Track ID JATR-1076-21 Rev. 1.2 15. Ordering Information Part Number RTL8187L RTL8187L-LF Table 34. Ordering Information Package 128-pin LQFP RTL8187L with Lead (Pb)-Free package Status MP MP RTL8187L Datasheet Realtek Semiconductor Corp. Headquarters No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com.tw Wireless LAN Network Interface Controller 36 Track ID JATR-1076-21 Rev. 1.2

Federal Communication Commission Interference Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:

Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. FCC Caution: Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This device and its antenna(s) must not be co-located or operating in conjunction with any other antenna or transmitter. This device is intended only for OEM integrators under the following conditions:

OEM integrator is still responsible for testing their end product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.). IMPORTANT NOTE: In the event that these conditions can not be met (for example certain laptop configurations or co-location with another transmitter), then the FCC authorization is no longer considered valid and the FCC ID can not be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC authorization. Without Co-located The antenna (s) used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. Modular Approval OEM integrator is still responsible for testing their end product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.). IMPORTANT NOTE: In the event that these conditions can not be met (for example certain laptop configurations or co-location with another transmitter), then the FCC authorization is no longer considered valid and the FCC ID can not be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC authorization. Modular OEM Integrator Notice End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed such that 20 cm may be maintained between the antenna and users. The final end product must be labeled in a visible area with the following: Contains TX FCC ID:

TX2-RTL8187. IC Radiation Exposure Statement:

"Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device."

6317ARTL8187. 2. DQ661500301 Gain(dBi) 2.32 This device has been designed to operate with an antenna having a maximum gain of

[3.00] dBi. Antenna having a higher gain is strictly prohibited per regulations of Industry Canada. The required antenna impedance is 50 ohms."

List of antennas below:

Ant. Type PIFA PK Gain(dBi) 3 Connector IPEX Model No. Ant. Type PIFA PK Gain(dBi) 2.39 Connector IPEX Model No. Ant. Type PIFA PK Gain(dBi) 0.78 Connector IPEX Model WDAN-QMA6002 No.

-DF Ant. Type PIFA PK Gain(dBi) 0.3 Connector IPEX Model No. Ant. Type PIFA PK Gain(dBi) 1.97 Connector IPEX Model No. Ant. Type PIFA PK Gain(dBi) 2.37 Ant. Type PIFA PK Connector IPEX Model No. MA6001 Ant. Type PIFA PK Connector IPEX Model No. AR320WIPI02B Ant. Type PIFA PK Connector IPEX Model No. DQ661500115 Ant. Type PIFA PK Connector IPEX Model No. AR620WIPI02C Ant. Type PIFA PK 10

. Connector IPEX Model No. ARMK8WIPI02A Ant. Type PIFA PK Gain(dBi) 2.57 Gain(dBi) 2.11 Gain(dBi) 2.11 Gain(dBi) 1.1 Gain(dBi) 1 AAFJ5050002LF0 ARMK8WIPI02A AR830WIPI02A 4. 6. 8. 12

. Connector IPEX Model No. AR320WIPI01B AAFA5050004LQ 0 1. 3. 5. 7. 9. 11

. Connector IPEX Model No. Ant. Type PIFA PK Gain(dBi) 2.57 13

. Connector IPEX Model 15

. Connector IPEX Model No. Ant. Type PIFA PK Gain(dBi) 2.55 No. Ant. Type PIFA PK Gain(dBi) 2.49 No. Ant. Type PIFA PK Gain(dBi) 2.86 17

. Connector IPEX Model 19

. Connector IPEX Model No. Ant. Type PIFA PK Gain(dBi) 0.74 21

. Connector IPEX Model No. B0785028000003 AR621WIPI02D ARK8MWIPI01B AAFQ5050002LK 0 MA6002 Ant. Type PIFA PK 14

. Connector IPEX Model No. AR330WIPI01D Gain(dBi) 2.21 Ant. Type PIFA PK 16

. Connector IPEX Model No. ARW62WIPI01G Gain(dBi) 2.48 Ant. Type PIFA PK 18

. Connector IPEX Model No. AAFQ5050001L Gain(dBi) 0.46 Ant. Type PIFA PK 20

. Connector IPEX Model No. B012502800000 K0 Gain(dBi) 2.45 4 Ant. Type PIFA PK 22

. Connector IPEX Model No. W340UA1 Gain(dBi) 0.03 To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that permitted for successful communication. Installation Guide__ Installation Guide__ RReeaalltteekk RRTTLL88118877 ++ RRTTLL88222255--VVFF ((ZZ22)) 880022..1111 bb//gg mmiinniiCCaarrdd Date: 2006/06/06 Version: 1.0 This document is subject to change without notice. The document contains Realtek confidential information and must not be disclosed to any third party without appropriate NDA. Installation Description This module is to be installed only by the professionals. When IRF303JU/IRF303U2is installed in a product, we shall consider the following points;

1. Since RTL8187 miniCard owns its FCC ID Number/IC Number, we shall affix an exterior label on the outside of the product if the FCC ID/IC Number is not visible. The exterior label shall use wording such as either Contains Transmitter Module FCC ID: TX2-RTL8187/IC Number: 6317A-RTL8187or Contains FCC ID: TX2-RTL8187/ IC Number: 6317A-RTL8187. 2. RTL8187 miniCard complies with requirements of sub-sections 15.203, 15.205, 15.207, 15.247 and 15.407 in FCC Rules Part 15. We shall installRTL8187 miniCard in accordance with their requirements. RTL8187 miniCard complies with requirements of the sub-section 2.1091. When installers install RTL8187 miniCard into a product, they shall ensure that the public is not exposedto radio frequency energy levels in excess of the Commissions guidelines in accordance with the sub-section 15.247(e)(i) and 15.407(f) in FCC Rules Part 15.

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Internal Photo

Internal Photos

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251.33 KiB

August 08 2006

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External Photo

External Photos

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288.65 KiB

August 08 2006

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Label Info

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115.40 KiB

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Confidentiality Request Letter

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211.45 KiB

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LMA Letter

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47.46 KiB

August 08 2006

		frequency	equipment class	purpose
1	2006-08-08	2412 ~ 2462	DTS - Digital Transmission System	Original Equipment

Application Forms

app s	Applicant Information
1	Effective	2006-08-08
1	Applicant's complete, legal business name	Realtek Semiconductor Corp.
1	FCC Registration Number (FRN)	0020109807
1	Physical Address	No. 2
1		Hsinchu, 300
1		Taiwan

app s	TCB Information
1	TCB Application Email Address	h******@phoenix-testlab.de
1	TCB Scope	A4: UNII devices & low power transmitters using spread spectrum techniques

app s	FCC ID
1	Grantee Code	TX2
1	Equipment Product Code	RTL8187

app s	Person at the applicant's address to receive grant or for contact
1	Name	D**** L**
1	Title	Project Manager
1	Telephone Number	886-3******** Extension:
1	Fax Number	886-3********
1	E-mail	d******@realtek.com

app s	Technical Contact
1	Firm Name	Sporton International Inc.
1	Name	W****** H******
1	Physical Address	No 52. Hwa Ya 1st Rd., Hwa Ya Technology Park
1		Tao Yuan, 333
1		Taiwan
1	E-mail	w******@sporton.com.tw

app s	Non Technical Contact
		n/a

app s	Confidentiality (long or short term)
1	Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?:	Yes
1	Long-Term Confidentiality Does this application include a request for confidentiality for any portion(s) of the data contained in this application pursuant to 47 CFR § 0.459 of the Commission Rules?:	No
	if no date is supplied, the release date will be set to 45 calendar days past the date of grant.

app s	Cognitive Radio & Software Defined Radio, Class, etc
1	Is this application for software defined/cognitive radio authorization?	No
1	Equipment Class	DTS - Digital Transmission System
1	Description of product as it is marketed: (NOTE: This text will appear below the equipment class on the grant)	802.11b/g RTL8187 miniCard
1	Related OET KnowledgeDataBase Inquiry: Is there a KDB inquiry associated with this application?	No
1	Modular Equipment Type	Limited Single Modular Approval
1	Purpose / Application is for	Original Equipment
1	Composite Equipment: Is the equipment in this application a composite device subject to an additional equipment authorization?	No
1	Related Equipment: Is the equipment in this application part of a system that operates with, or is marketed with, another device that requires an equipment authorization?	No
1	Grant Comments	Limited Modular Approval. Power Output listed is conducted. Approval is limited to OEM installation only. The antenna(s) used for this transmitter must be installed to provide a separation distance of at least 20 cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter. OEM integrators must be provided with antenna installation instructions. OEM integrators and end-users must be provided with transmitter operation conditions for satisfying RF exposure compliance. This grant is valid only when the device is sold to OEM integrators and the OEM integrators are instructed to ensure that the end user has no manual instructions to remove or install the device.
1	Is there an equipment authorization waiver associated with this application?	No
1	If there is an equipment authorization waiver associated with this application, has the associated waiver been approved and all information uploaded?	No

app s	Test Firm Name and Contact Information
1	Firm Name	Sporton International Inc.
1	Name	K****** L****
1	Telephone Number	886-2******** Extension:
1	Fax Number	886-2********
1	E-mail	K******@sporton.com.tw

Equipment Specifications
	Line	Rule Parts	Grant Notes	Lower Frequency	Upper Frequency	Power Output	Tolerance	Emission Designator	Microprocessor Number
1	1	15C		2412.00000000	2462.00000000	0.1110000

some individual PII (Personally Identifiable Information) available on the public forms may be redacted, original source may include additional details