Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 LEO2-A Platform Hardware Manual Type Manual This document is hardware manual for LEO2-A Platform board. Contents of this document are descriptions of each blocks and usage directions. It is recommended to peruse this manual before operating LEO2-A Platform Title ABSTRACT HISTORY Rev Status KEY WORDS 1 2 3 4 5 6 7 8 9 10 11 Contents Date Author Mobile Communication Technology Research Lab. 533 Hogye-dong, Dongan-gu, Anyang-shi, Kyongki-do, KOREA Copyright, 2008 By LG Electronics Inc. All rights reserved. No part of this document may be reproduced in any way, or by any means, without the express written permission of LG Electronics Inc. LGE Proprietary i MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0
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1. The product described in this manual may be modified without prior notice for reliability, functionality or design improvement. 2. Information contained in this manual is correct and reliable, but LG shall not be held responsible for damage due to the use of information, product or circuit or infringement of property rights or other rights. 3. This manual does not grant users the property rights and other rights of the third party or LG Electronics Inc. 4. No part of this manual may be transcribed or duplicated without the written permission of LG Electronics Inc. 5. The appearance of the product shown in this manual may slightly differ from that of the actual product. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 LGE Proprietary ii MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 CONTENTS 1. Introduction............................................................................................................................... 1.1 Scope ..................................................................................................................................... 1.2 Terminology............................................................................................................................ 1.3 Trademark List........................................................................................................................ 1.4 Special Mark........................................................................................................................... 2. Features and top level diagram ................................................................................................. 2.1 Features ................................................................................................................................. 2.2 Photograph of the LEO2-A platform board............................................................................... 2.3 Top level block diagram .......................................................................................................... 2.4 Placement map....................................................................................................................... 3. Block description....................................................................................................................... 3.1 FPGA subsystem .................................................................................................................... 3.2 ARM subsystem...................................................................................................................... 3.3 Debugger Interface ................................................................................................................. 3.4 RF Interface............................................................................................................................ 3.5 Reference Clock ..................................................................................................................... 3.6 Reset ...................................................................................................................................... 3.7 Application interface................................................................................................................ 3.8 Power Supplies....................................................................................................................... 4. DIP switch, LED and logic probing connector ............................................................................ 4.1 ARM Processor debugging configuration switch setting........................................................... 4.2 General purpose LED indication........................................................................................... 4.3 Logic probing connector....................................................................................................... 5. Description of Smart antenna and beam forming modes if applicable ..................................... 6. Reference............................................................................................................................ 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 LGE Proprietary iii MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FIGURES Figure 1. Photograph of LEO2-A platform ........................................................................................ Figure 2. Top level block diagram .................................................................................................... Figure 3. Placement map of LEO2-A ............................................................................................. Figure 4. ARM processor Block ..................................................................................................... Figure 5. RF interface on LEO2-A platform board ............................................................................ Figure 6. Block diagram of RF daughter board................................................................................. Figure 7. Block diagram of clock distribution .................................................................................... Figure 8. Block diagram of platform board reset scheme.................................................................. Figure 9. Block diagram of application interface............................................................................... Figure 10. Block diagram of power supplies..................................................................................... LGE Proprietary iv MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 Table 1. ARM processor setting DIP switches............................................................................... Table 2. LED signal mapping........................................................................................................ TABLES 1 2 3 4 5 6 LGE Proprietary v MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 1. Introduction 1.1 Scope This document intends to describe the brief architecture and usage of the LEO2-A Platform board. LEO2-A Platform board is designed for LTE User Equipment test and verification. 1.2 Terminology ADC AMBA AHB DAC DDR SDRAM EPI ETM JTAG LNA UE UART SDIO USB VGA ZDB Analog to Digital Converter Advanced Microcontroller Bus Architecture Advanced High-performance Bus Digital to Analog Converter Double Data Rate Synchronous Dynamic Random Access Memory External Perallel Interface Embedded Trace Macro-cell Joint Test Action Group Low Noise Amplifier User Equipment Universal Asynchronous Receiver/Transmitter Secure Digital Input Output Universal Serial Bus Variable Gain Amplifier Zero Delay BufferAMBA 1.3 Trademark List ARM926EJ-S are registered trademarks of ARM Ltd. 1.4 Special Mark The following table defines special marks used in this manual. Mark Definition 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 LGE Proprietary MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 2. Features and top level diagram 2.1 Features
- ARM926EJ-S (max 333MHz)
- AMBA 2.0 (max 166MHz)
7 Virtex4 FX140 FPGA for Modem algorithm
- RF interface (2 Receivers and 1 Transmitter)
- Application interface
- USB 2.0 High speed device
512Mb DDR SDRAM, 1Gb NAND Flash 100 Ethernet port 1 Serial ports (up to 115 K baud) JTAG and ETM Debug port 2.2 Photograph of the LEO2-A platform board 22 23 24 25 26 27 Figure 1. Photograph of LEO2-A platform
- Mechanical size of platform board is 420 (W) x 300 (H) mm LGE Proprietary MCTR Lab. 1 2 3 4 5 6 7 8 9 2.3 Top level block diagram Application Interface EPI, NAND, USB SDIO, SPI, DIP SW 9 6 S i g n a ls 149 Signals TD1_START TD1_IMEM_WE, SEL[3]
TD1_IMEM_WADDR[12]
TD1_IMEM_WDATA[64]
TD1_DB_DONE, DEC_DONE HARQ1_START HARQ1_PARAM_START RSVD[64]
Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 32 Signals OPT_DCH1_SYMB0[8]
OPT_DCH1_SYMB1[8]
OPT_DCH1_STB, START, END RSVD[13]
51 Signals 310 Signals DATACH0_SYMB0[8]
DATACH0_SYMB1[8]
DATACH0_STB, START, END RSVD[32]
64bits mDDR s l i a n g S 0 0 1
0 0 1 D V S R DATACH1_STB, START, END DATACH1_SYMB0[8]
51 Signals DATACH1_SYMB1[8]
RSVD[32]
3 2 Sig C D T _ D _ T P C D T _ P O H O n als 0 _ S H 0 _ H C T 0 _ S R S P O D N B 0[8]
B 1[8]
M Y T, E M Y R S A T B , S D [1 3]
V RX_FRAME_SYNC_N RX_SUB_FRAME_SYNC_N ENG_EN[5]
ORX_WR, ADDR[10], DATA[32]
MIMO_WR_ADDR[10], DATA[32]
SC_RD_DATA0[32]
SC_RD_DATA1[32]
SC_RD_STB, IDX[2]
SC_RD_EN, ADDR[11]
SC_RD_SYMB_IDX[2]
ORX_OPT[100]
RSVD[64]
s l i a n g S 2 3 C C T L O C P H T 5 4 L C S H T _ S ig T _ C _ R X T L C _ F H R R S A V M B S n
, S Y M als B[
8]
T, E R _ID T A E X
1 0]
S _ Y N N D D[
3 2]
48 Signals RX0_I[12], RX0_Q[12]
RX1_I[12], RX1_Q[12]
0 1 D V S R 30.72/61.44/122.88MHz TurboDecoder_CLK PLL R F D a u g h t e r c o n n e c t o r
N _ C N Y S _ E M A R F _ X R 8 B M Y S _ H C L T C _ T P O D N E
, T R A T S
, B T S _ H C C _ T P O
I 0 1 X D _ H C C _ T P O C _ N 59 Signals TX_FILTER_OUT[48]
TX_FILTER_IQ_SEL RSVD[10]
26 Signals TX_I[12]
TX_Q[12]
RSVD[2]
32 Signals RF_GPIO[16]
4ch SPI 149 Signals TD0_START TD0_IMEM_WE, SEL[3]
TD0_IMEM_WADDR[12]
TD0_IMEM_WDATA[64]
TD0_DB_DONE, DEC_DONE HARQ0_START HARQ0_PARAM_START RSVD[64]
64bits mDDR JTAG UART USB SDRAM ETM Ethernet Serial Flash NAND ARM926EJ-S Figure 2. Top level block diagram 2.4 Placement map J 1 H A R Q T P 0 H A R Q T P 1 J 4 T D 1 T P 0 T D 1 T P 1 J 7 I M M O T P 0 I M M O T P 1 J 1 0 S R C H T P 0 S R C H T P 1 J 6 T D 0 T P 0 T D 0 T P 1 J 1 1 R F R X R F T X T X T P 0 T X T P 1 E T H E R N E T Figure 3. Placement map of the LEO2-A H A R Q 0 T P 0 H A R Q 0 T P 1 J 3 R E S E T LGE Proprietary MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 3. Block description 3.1 FPGA subsystem The LEO2-A Platform supports 7 FPGAs (xilinx virtex4 FX140, 1517pin package) for LTE UE modem algorithm. Functionality of each FPGA is
- TX FPGA : Transmit block, Viterbi decoder, RF board control
- SRCH FPGA : Receiver block
- MISO FPGA : Receiver block and MISO
- HARQ 0/1 FPGA : Hybrid ARQ block
- Turbo Decoder 0/1 FPGA : Decoder block Signal connection of FPGAs is
- ARM926 bus signal is connected to commonly all FPGAs, except MISO FPGA.
- Detailed signals are described on block diagram. 32 common reserved signals are connected commonly. 64 test signals of each FPGA are connected to MICTOR probing header. 4 GPIO LEDs of each FPGAs FPGA configure bitstream is stored in platform flash. The maximum configuration bitstream size of virtex4 FX140 is 47,856,896. Bitstream is stored in 2 serial daisy chained memories; capacity is 32Mb and 16Mb. Proper binary image should be fused on each platform memories. Xilinx Platform cable connection for image fusing are J12 (TX FPGA), J10 (SRCH FPGA), J7 (MISO FPGA), J3 (HARQ0 FPGA), J4 (HARQ1 FPGA), J6 (Turbo Decoder 0 FPGA) and J1 (Turbo Decoder1 FPGA), which are placed beside of each FPGAs. 3.2 ARM subsystem 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LGE Proprietary Figure 4. ARM processor block MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 The ARM processor is used to control the LTE UE modem logic. The processor has ARM926EJ-S core and peripheral controllers. ARM Processor
- ARM926EJ-S core max. 333MHz, 16KB-I/D cache, configurable TMC-I/D size, MMU, TLB, JTAG and ETM trace module (multiplexed interfaces). 32KByte Rom (code customizable) 8KByte common SRAM.
- High performance linked list 8 channels DMA.
- Ethernet MII, management interface
- USB2.0 High speed device
- Ext. memory interface : 16bit DDR1@200MHz
- Flash interface: 8bits NAND and Serial.
- RTC - WDOG - SYSCTR - MISC internal control registers.
- Current clock frequency setting : ARM Core 300MHz, Bus 150MHz, SDRAM 150MHz 10 independent Timers with programmable prescaler. JTAG (IEEE1149.1) interface. Memory The memory capacity and speed grade, that is on this board, are
- SDRAM : 512Mbits, 16bits data access, DDR @ 150MHz
- NAND Flash : 1Gbits, 8bits parallel, code stored.
- Serial Flash : 64Mbits, boot loader stored. External Interface The LEO2-A Platform supports external interface for diagnostic monitoring and user data transfer.
- High speed USB2.0 100Mbps Ethernet
Interrupt 9 interrupt inputs are from interrupt handler in Turbo decoder0 FPGA. 3.3 Debugger Interface The LEO2-A platform support debugging interface, JTAG and ETM, for ARM926 ARM926 core
JTAG : CON12
- ETM9 : CON11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 LGE Proprietary MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 3.4 RF Interface 1 2 3 4 5 6 7 Figure 5. RF interface on LEO2-A platform board 8 9 10 Figure 6. Block diagram of RF daughter board LGE Proprietary MCTR Lab. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 The LEO2-A Platform supports RF daughter board interface to verify and test LTE UE modem algorithm. The baseband IQ signals are transmitted and received on FPGAs, Transmit part is on TX FPGA and Receive part is on SRCH, MISO FPGA. The bit resolution of IQ signal is 12bits. The sampling frequencies are 122.88MHz for DAC and 61.44MHz for ADC. The transmit signal and sampling clock are delivered through LVDS, because of its over 100MHz data rate. The RF control signals, GPIO and SPIs, are generated on TX FPGA. RF daughter board consist in following blocks 2 antenna ports : 1 Tx and 2 Rx
14bits TX DAC, 14bits RX ADC
- TX synthesizer, RX synthesizer
- Modulator, Demodulator, VGA,
- Power amp, LNA and passive RF devices
3 x 120pin connector 3.5 Reference Clock Figure 7. Block diagram of clock distribution The 19.2MHz reference clock for LEO2-A platform board is supplied from TCXO in RF daughter board. From this ref. clock, all needed clock source for LTE UE modem is synthesized by PLLs. The PLLs generated clock frequencies 30.72, 61.44, 122.88MHz, and 32KHz. All PLL output clocks are supplied to FPGAs and other blocks. The clock skews on each FPGA input pad is very low <1nsec. There is additional reference clock oscillator on LEO2-A platform board for without RF daughter board test situations. This clock path selection is controlled by the 7pin on SW6. (1 on-board, 0 RF daughter board oscillator) LGE Proprietary MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 3.6 Reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Figure 8. Block diagram of platform board reset scheme The reset CPLD manages whole system reset scheme for ARM, Ethernet transceiver and each FPGA reset. In the lower left lower corner of the platform board, a manual reset switch is provided. 3.7 Application interface Figure 9. Block diagram of application interface The LEO2-A platform supports a interface for external connection to application side. 3 kinds of interfaces are supported, EPI, SDIO and USB. Application side will be designed as a platform phase. board next at LGE Proprietary MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 3.8 Power Supplies 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Figure 10. Block diagram of power supplies External power supplied from DC input jack on the platform board. To proper operation, external AC to DC power supply should be 12V and >5A. All needed power sources of platform board are supplied from DC-DC converters and LDOs devices. 4. DIP switch, LED and logic probing connector 4.1 ARM Processor debugging configuration switch setting Two DIP switches (SW3, SW6) are used to ARM processor configurations and platform board settings. Each control signals are assigned according to Table 1. Switch on represents logic low, switch off represents logic high as other platform boards. LEO2-A Platform default DIP switch settings are Table 1. Remark: Setting the DIP switch in a wrong way may cause unexpected behavior that can also damage the board since that all the production tests are intended to run in a different environment. SW3 Pin No. Name Description Default 1 2 3 4 5 LGE Proprietary ARM_INT(0) ARM_INT(1) ARM_INT(2) ARM_INT(3) ARM Processor interrupt input
"on" : assert interrupt
"off" : deassert interrupt DIPSW_CPLD(0) Test signal input to reset CPLD
"on" : low signal to CPLD
"off" : high signal to CPLD OFF OFF MCTR Lab. SW6 2 3 4 5 6 7 8 9 LED1 Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 DIPSW_CPLD(1)
"off" : high signal to CPLD 1 SSP2_SS1 ARM processor booting device selection
'on' Boot from USB
'off' Boot NAND flash SMI_WE Write enable signal of serial flash
"on" : write protected
"off" : write enabled OFF OFF 6 7 8 Pin No. Name Description Default 1 2 3 4 5 6 7 8 ARM_TEST(0) ARM_TEST(1) ARM_TEST(2) ARM_TEST(3) ARM_TEST(4) ARM_TEST(5) CLK_SEL ARM Processor configuration Reference clock selection
'on' Reference clock from RF daughter
'off' on board reference clock Table 1. ARM processor setting DIP switches OFF ON ON OFF ON OFF ON OFF 4.2 General purpose LED indication There are several LEDs are present on the board. Their meanings are described in Table 4-3. LED turn on represent signal is high or status is good. 1.2V power OK LED2 1.2V power OK LED3 1.2V power OK LED4 3.3V power OK LED5 DC IN OK LED6 1.0V power OK LED7 Ethernet duplex LED8 Ethernet link 1000 LED9 Ethernet link 100 LED10 Ethernet link 10 LED11 Ethernet activity LED13 2.5V power OK LED14 All FPGA done LED15 PLL Lock LED16 Turbo Dec1 FPGA done LED17 ARM INT(4) LED18 TD1 GPIO(0) LED19 ARM INT(5) LED20 TD1 GPIO(1) LED21 ARM INT(6) LED22 TD1 GPIO(2) LED23 ARM INT(7) LED24 TD1 GPIO(3) LED25 ARM INT(8) LED26 HARQ1 FPGA Done LED27 HARQ0 FPGA Done LED28 HARQ1 GPIO(0) LED29 HARQ0 GPIO(0) LED30 HARQ1 GPIO(1) LED31 HARQ0 GPIO(1) LED32 1.8V power OK LED33 HARQ1 GPIO(2) LED34 HARQ0 GPIO(2) LED35 HARQ1 GPIO(3) LED36 HARQ0 GPIO(3) LED37 MISO FPGA done LED38 TD0 FPGA Done LED39 MISO GPIO(0) LED40 TD0 GPIO(0) LED41 MISO GPIO(1) LED42 TD0 GPIO(1) LED43 MISO GPIO(2) LED44 TD0 GPIO(2) LED45 MISO GPIO(3) LED46 TD0 GPIO(3) LED47 SRCH FPGA Done LED48 TX FPGA Done LGE Proprietary MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 LED49 SRCH GPIO(0) LED50 TX GPIO(0) LED51 SRCH GPIO(1) LED52 TX GPIO(1) LED53 SRCH GPIO(2) LED54 TX GPIO(2) LED55 SRCH GPIO(3) LED56 TX GPIO(3) LED57 RF power OK Table 2. LED signal mapping 4.3 Logic probing connector All of the logic analyzer probing headers are MICTOR connector type, agilent E5346A logic analyzer probing adaptor is needed to signal monitoring. Refer to LEO2-A schematic for detailed signal mappings. 5 Description of Smart antenna and beam forming modes if applicable 1) SFBC(Space Frequency Block Code) mode : Transmit diversity mode Easily speaking, SFBC which eNB sends same data through 2 antennas means Tx diversity. 2) SM(Spatial multiplexing) mode SM which eNB sends different data through 2 antennas helps high data Rate. Our LTE UE supports upper 2cases functionality. That is, we support smart antenna and beam forming in wide meaning. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 LGE Proprietary MCTR Lab. Updated 2008-09-08 File LEO2 Platform Hardware Manual Rev. V1.0 6. Reference
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1 2 3 4 5 6 7 8 Notice OEM integrators and installers are instructed that the phrase. This device contains Warning: Exposure to Radio Frequency Radiation The radiated output power of this device is far below the FCC radio frequency exposure limits. Nevertheless, the device should be used in such a manner that the potential for human contact during normal operation is minimized. In order to avoid the possibility of exceeding the FCC radio frequency exposure limits, human proximity to the antenna should not be less than 20cm during normal operation. The gain of the antenna for 3GPP-Band4(1710~1755MHz) must not exceed -4 dBi. The antenna(s) used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. LGE Proprietary MCTR Lab.